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1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56#include <linux/kexec.h>
57#include <linux/numa.h>
58#include <linux/pgtable.h>
59#include <linux/overflow.h>
60#include <linux/stackprotector.h>
61#include <linux/cpuhotplug.h>
62#include <linux/mc146818rtc.h>
63#include <linux/acpi.h>
64
65#include <asm/acpi.h>
66#include <asm/cacheinfo.h>
67#include <asm/desc.h>
68#include <asm/nmi.h>
69#include <asm/irq.h>
70#include <asm/realmode.h>
71#include <asm/cpu.h>
72#include <asm/numa.h>
73#include <asm/tlbflush.h>
74#include <asm/mtrr.h>
75#include <asm/mwait.h>
76#include <asm/apic.h>
77#include <asm/io_apic.h>
78#include <asm/fpu/api.h>
79#include <asm/setup.h>
80#include <asm/uv/uv.h>
81#include <asm/microcode.h>
82#include <asm/i8259.h>
83#include <asm/misc.h>
84#include <asm/qspinlock.h>
85#include <asm/intel-family.h>
86#include <asm/cpu_device_id.h>
87#include <asm/spec-ctrl.h>
88#include <asm/hw_irq.h>
89#include <asm/stackprotector.h>
90#include <asm/sev.h>
91#include <asm/spec-ctrl.h>
92
93/* representing HT siblings of each logical CPU */
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
95EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
96
97/* representing HT and core siblings of each logical CPU */
98DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
99EXPORT_PER_CPU_SYMBOL(cpu_core_map);
100
101/* representing HT, core, and die siblings of each logical CPU */
102DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
103EXPORT_PER_CPU_SYMBOL(cpu_die_map);
104
105/* CPUs which are the primary SMT threads */
106struct cpumask __cpu_primary_thread_mask __read_mostly;
107
108/* Representing CPUs for which sibling maps can be computed */
109static cpumask_var_t cpu_sibling_setup_mask;
110
111struct mwait_cpu_dead {
112 unsigned int control;
113 unsigned int status;
114};
115
116#define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
117#define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
118
119/*
120 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
121 * that it's unlikely to be touched by other CPUs.
122 */
123static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
124
125/* Maximum number of SMT threads on any online core */
126int __read_mostly __max_smt_threads = 1;
127
128/* Flag to indicate if a complete sched domain rebuild is required */
129bool x86_topology_update;
130
131int arch_update_cpu_topology(void)
132{
133 int retval = x86_topology_update;
134
135 x86_topology_update = false;
136 return retval;
137}
138
139static unsigned int smpboot_warm_reset_vector_count;
140
141static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
142{
143 unsigned long flags;
144
145 spin_lock_irqsave(&rtc_lock, flags);
146 if (!smpboot_warm_reset_vector_count++) {
147 CMOS_WRITE(0xa, 0xf);
148 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
150 }
151 spin_unlock_irqrestore(&rtc_lock, flags);
152}
153
154static inline void smpboot_restore_warm_reset_vector(void)
155{
156 unsigned long flags;
157
158 /*
159 * Paranoid: Set warm reset code and vector here back
160 * to default values.
161 */
162 spin_lock_irqsave(&rtc_lock, flags);
163 if (!--smpboot_warm_reset_vector_count) {
164 CMOS_WRITE(0, 0xf);
165 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
166 }
167 spin_unlock_irqrestore(&rtc_lock, flags);
168
169}
170
171/* Run the next set of setup steps for the upcoming CPU */
172static void ap_starting(void)
173{
174 int cpuid = smp_processor_id();
175
176 /* Mop up eventual mwait_play_dead() wreckage */
177 this_cpu_write(mwait_cpu_dead.status, 0);
178 this_cpu_write(mwait_cpu_dead.control, 0);
179
180 /*
181 * If woken up by an INIT in an 82489DX configuration the alive
182 * synchronization guarantees that the CPU does not reach this
183 * point before an INIT_deassert IPI reaches the local APIC, so it
184 * is now safe to touch the local APIC.
185 *
186 * Set up this CPU, first the APIC, which is probably redundant on
187 * most boards.
188 */
189 apic_ap_setup();
190
191 /* Save the processor parameters. */
192 smp_store_cpu_info(cpuid);
193
194 /*
195 * The topology information must be up to date before
196 * notify_cpu_starting().
197 */
198 set_cpu_sibling_map(cpuid);
199
200 ap_init_aperfmperf();
201
202 pr_debug("Stack at about %p\n", &cpuid);
203
204 wmb();
205
206 /*
207 * This runs the AP through all the cpuhp states to its target
208 * state CPUHP_ONLINE.
209 */
210 notify_cpu_starting(cpuid);
211}
212
213static void ap_calibrate_delay(void)
214{
215 /*
216 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
217 * smp_store_cpu_info() stored a value that is close but not as
218 * accurate as the value just calculated.
219 *
220 * As this is invoked after the TSC synchronization check,
221 * calibrate_delay_is_known() will skip the calibration routine
222 * when TSC is synchronized across sockets.
223 */
224 calibrate_delay();
225 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
226}
227
228/*
229 * Activate a secondary processor.
230 */
231static void notrace start_secondary(void *unused)
232{
233 /*
234 * Don't put *anything* except direct CPU state initialization
235 * before cpu_init(), SMP booting is too fragile that we want to
236 * limit the things done here to the most necessary things.
237 */
238 cr4_init();
239
240 /*
241 * 32-bit specific. 64-bit reaches this code with the correct page
242 * table established. Yet another historical divergence.
243 */
244 if (IS_ENABLED(CONFIG_X86_32)) {
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir);
247 __flush_tlb_all();
248 }
249
250 cpu_init_exception_handling(false);
251
252 /*
253 * Load the microcode before reaching the AP alive synchronization
254 * point below so it is not part of the full per CPU serialized
255 * bringup part when "parallel" bringup is enabled.
256 *
257 * That's even safe when hyperthreading is enabled in the CPU as
258 * the core code starts the primary threads first and leaves the
259 * secondary threads waiting for SIPI. Loading microcode on
260 * physical cores concurrently is a safe operation.
261 *
262 * This covers both the Intel specific issue that concurrent
263 * microcode loading on SMT siblings must be prohibited and the
264 * vendor independent issue`that microcode loading which changes
265 * CPUID, MSRs etc. must be strictly serialized to maintain
266 * software state correctness.
267 */
268 load_ucode_ap();
269
270 /*
271 * Synchronization point with the hotplug core. Sets this CPUs
272 * synchronization state to ALIVE and spin-waits for the control CPU to
273 * release this CPU for further bringup.
274 */
275 cpuhp_ap_sync_alive();
276
277 cpu_init();
278 fpu__init_cpu();
279 rcutree_report_cpu_starting(raw_smp_processor_id());
280 x86_cpuinit.early_percpu_clock_init();
281
282 ap_starting();
283
284 /* Check TSC synchronization with the control CPU. */
285 check_tsc_sync_target();
286
287 /*
288 * Calibrate the delay loop after the TSC synchronization check.
289 * This allows to skip the calibration when TSC is synchronized
290 * across sockets.
291 */
292 ap_calibrate_delay();
293
294 speculative_store_bypass_ht_init();
295
296 /*
297 * Lock vector_lock, set CPU online and bring the vector
298 * allocator online. Online must be set with vector_lock held
299 * to prevent a concurrent irq setup/teardown from seeing a
300 * half valid vector space.
301 */
302 lock_vector_lock();
303 set_cpu_online(smp_processor_id(), true);
304 lapic_online();
305 unlock_vector_lock();
306 x86_platform.nmi_init();
307
308 /* enable local interrupts */
309 local_irq_enable();
310
311 x86_cpuinit.setup_percpu_clockev();
312
313 wmb();
314 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
315}
316
317/*
318 * The bootstrap kernel entry code has set these up. Save them for
319 * a given CPU
320 */
321void smp_store_cpu_info(int id)
322{
323 struct cpuinfo_x86 *c = &cpu_data(id);
324
325 /* Copy boot_cpu_data only on the first bringup */
326 if (!c->initialized)
327 *c = boot_cpu_data;
328 c->cpu_index = id;
329 /*
330 * During boot time, CPU0 has this setup already. Save the info when
331 * bringing up an AP.
332 */
333 identify_secondary_cpu(c);
334 c->initialized = true;
335}
336
337static bool
338topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
339{
340 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
341
342 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
343}
344
345static bool
346topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
347{
348 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
349
350 return !WARN_ONCE(!topology_same_node(c, o),
351 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
352 "[node: %d != %d]. Ignoring dependency.\n",
353 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
354}
355
356#define link_mask(mfunc, c1, c2) \
357do { \
358 cpumask_set_cpu((c1), mfunc(c2)); \
359 cpumask_set_cpu((c2), mfunc(c1)); \
360} while (0)
361
362static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
363{
364 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
365 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
366
367 if (c->topo.pkg_id == o->topo.pkg_id &&
368 c->topo.die_id == o->topo.die_id &&
369 c->topo.amd_node_id == o->topo.amd_node_id &&
370 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) {
371 if (c->topo.core_id == o->topo.core_id)
372 return topology_sane(c, o, "smt");
373
374 if ((c->topo.cu_id != 0xff) &&
375 (o->topo.cu_id != 0xff) &&
376 (c->topo.cu_id == o->topo.cu_id))
377 return topology_sane(c, o, "smt");
378 }
379
380 } else if (c->topo.pkg_id == o->topo.pkg_id &&
381 c->topo.die_id == o->topo.die_id &&
382 c->topo.core_id == o->topo.core_id) {
383 return topology_sane(c, o, "smt");
384 }
385
386 return false;
387}
388
389static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
390{
391 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id)
392 return false;
393
394 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1)
395 return c->topo.amd_node_id == o->topo.amd_node_id;
396
397 return true;
398}
399
400static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
401{
402 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
403
404 /* If the arch didn't set up l2c_id, fall back to SMT */
405 if (per_cpu_l2c_id(cpu1) == BAD_APICID)
406 return match_smt(c, o);
407
408 /* Do not match if L2 cache id does not match: */
409 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2))
410 return false;
411
412 return topology_sane(c, o, "l2c");
413}
414
415/*
416 * Unlike the other levels, we do not enforce keeping a
417 * multicore group inside a NUMA node. If this happens, we will
418 * discard the MC level of the topology later.
419 */
420static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
421{
422 if (c->topo.pkg_id == o->topo.pkg_id)
423 return true;
424 return false;
425}
426
427/*
428 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
429 *
430 * Any Intel CPU that has multiple nodes per package and does not
431 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
432 *
433 * When in SNC mode, these CPUs enumerate an LLC that is shared
434 * by multiple NUMA nodes. The LLC is shared for off-package data
435 * access but private to the NUMA node (half of the package) for
436 * on-package access. CPUID (the source of the information about
437 * the LLC) can only enumerate the cache as shared or unshared,
438 * but not this particular configuration.
439 */
440
441static const struct x86_cpu_id intel_cod_cpu[] = {
442 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */
443 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */
444 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */
445 {}
446};
447
448static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
449{
450 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
451 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
452 bool intel_snc = id && id->driver_data;
453
454 /* Do not match if we do not have a valid APICID for cpu: */
455 if (per_cpu_llc_id(cpu1) == BAD_APICID)
456 return false;
457
458 /* Do not match if LLC id does not match: */
459 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2))
460 return false;
461
462 /*
463 * Allow the SNC topology without warning. Return of false
464 * means 'c' does not share the LLC of 'o'. This will be
465 * reflected to userspace.
466 */
467 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
468 return false;
469
470 return topology_sane(c, o, "llc");
471}
472
473
474static inline int x86_sched_itmt_flags(void)
475{
476 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
477}
478
479#ifdef CONFIG_SCHED_MC
480static int x86_core_flags(void)
481{
482 return cpu_core_flags() | x86_sched_itmt_flags();
483}
484#endif
485#ifdef CONFIG_SCHED_SMT
486static int x86_smt_flags(void)
487{
488 return cpu_smt_flags();
489}
490#endif
491#ifdef CONFIG_SCHED_CLUSTER
492static int x86_cluster_flags(void)
493{
494 return cpu_cluster_flags() | x86_sched_itmt_flags();
495}
496#endif
497
498/*
499 * Set if a package/die has multiple NUMA nodes inside.
500 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
501 * Sub-NUMA Clustering have this.
502 */
503static bool x86_has_numa_in_package;
504
505static struct sched_domain_topology_level x86_topology[6];
506
507static void __init build_sched_topology(void)
508{
509 int i = 0;
510
511#ifdef CONFIG_SCHED_SMT
512 x86_topology[i++] = (struct sched_domain_topology_level){
513 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
514 };
515#endif
516#ifdef CONFIG_SCHED_CLUSTER
517 x86_topology[i++] = (struct sched_domain_topology_level){
518 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
519 };
520#endif
521#ifdef CONFIG_SCHED_MC
522 x86_topology[i++] = (struct sched_domain_topology_level){
523 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
524 };
525#endif
526 /*
527 * When there is NUMA topology inside the package skip the PKG domain
528 * since the NUMA domains will auto-magically create the right spanning
529 * domains based on the SLIT.
530 */
531 if (!x86_has_numa_in_package) {
532 x86_topology[i++] = (struct sched_domain_topology_level){
533 cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG)
534 };
535 }
536
537 /*
538 * There must be one trailing NULL entry left.
539 */
540 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
541
542 set_sched_topology(x86_topology);
543}
544
545void set_cpu_sibling_map(int cpu)
546{
547 bool has_smt = __max_threads_per_core > 1;
548 bool has_mp = has_smt || topology_num_cores_per_package() > 1;
549 struct cpuinfo_x86 *c = &cpu_data(cpu);
550 struct cpuinfo_x86 *o;
551 int i, threads;
552
553 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
554
555 if (!has_mp) {
556 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
557 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
558 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
559 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
560 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
561 c->booted_cores = 1;
562 return;
563 }
564
565 for_each_cpu(i, cpu_sibling_setup_mask) {
566 o = &cpu_data(i);
567
568 if (match_pkg(c, o) && !topology_same_node(c, o))
569 x86_has_numa_in_package = true;
570
571 if ((i == cpu) || (has_smt && match_smt(c, o)))
572 link_mask(topology_sibling_cpumask, cpu, i);
573
574 if ((i == cpu) || (has_mp && match_llc(c, o)))
575 link_mask(cpu_llc_shared_mask, cpu, i);
576
577 if ((i == cpu) || (has_mp && match_l2c(c, o)))
578 link_mask(cpu_l2c_shared_mask, cpu, i);
579
580 if ((i == cpu) || (has_mp && match_die(c, o)))
581 link_mask(topology_die_cpumask, cpu, i);
582 }
583
584 threads = cpumask_weight(topology_sibling_cpumask(cpu));
585 if (threads > __max_smt_threads)
586 __max_smt_threads = threads;
587
588 for_each_cpu(i, topology_sibling_cpumask(cpu))
589 cpu_data(i).smt_active = threads > 1;
590
591 /*
592 * This needs a separate iteration over the cpus because we rely on all
593 * topology_sibling_cpumask links to be set-up.
594 */
595 for_each_cpu(i, cpu_sibling_setup_mask) {
596 o = &cpu_data(i);
597
598 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
599 link_mask(topology_core_cpumask, cpu, i);
600
601 /*
602 * Does this new cpu bringup a new core?
603 */
604 if (threads == 1) {
605 /*
606 * for each core in package, increment
607 * the booted_cores for this new cpu
608 */
609 if (cpumask_first(
610 topology_sibling_cpumask(i)) == i)
611 c->booted_cores++;
612 /*
613 * increment the core count for all
614 * the other cpus in this package
615 */
616 if (i != cpu)
617 cpu_data(i).booted_cores++;
618 } else if (i != cpu && !c->booted_cores)
619 c->booted_cores = cpu_data(i).booted_cores;
620 }
621 }
622}
623
624/* maps the cpu to the sched domain representing multi-core */
625const struct cpumask *cpu_coregroup_mask(int cpu)
626{
627 return cpu_llc_shared_mask(cpu);
628}
629
630const struct cpumask *cpu_clustergroup_mask(int cpu)
631{
632 return cpu_l2c_shared_mask(cpu);
633}
634EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
635
636static void impress_friends(void)
637{
638 int cpu;
639 unsigned long bogosum = 0;
640 /*
641 * Allow the user to impress friends.
642 */
643 pr_debug("Before bogomips\n");
644 for_each_online_cpu(cpu)
645 bogosum += cpu_data(cpu).loops_per_jiffy;
646
647 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
648 num_online_cpus(),
649 bogosum/(500000/HZ),
650 (bogosum/(5000/HZ))%100);
651
652 pr_debug("Before bogocount - setting activated=1\n");
653}
654
655/*
656 * The Multiprocessor Specification 1.4 (1997) example code suggests
657 * that there should be a 10ms delay between the BSP asserting INIT
658 * and de-asserting INIT, when starting a remote processor.
659 * But that slows boot and resume on modern processors, which include
660 * many cores and don't require that delay.
661 *
662 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
663 * Modern processor families are quirked to remove the delay entirely.
664 */
665#define UDELAY_10MS_DEFAULT 10000
666
667static unsigned int init_udelay = UINT_MAX;
668
669static int __init cpu_init_udelay(char *str)
670{
671 get_option(&str, &init_udelay);
672
673 return 0;
674}
675early_param("cpu_init_udelay", cpu_init_udelay);
676
677static void __init smp_quirk_init_udelay(void)
678{
679 /* if cmdline changed it from default, leave it alone */
680 if (init_udelay != UINT_MAX)
681 return;
682
683 /* if modern processor, use no delay */
684 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
685 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
686 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
687 init_udelay = 0;
688 return;
689 }
690 /* else, use legacy delay */
691 init_udelay = UDELAY_10MS_DEFAULT;
692}
693
694/*
695 * Wake up AP by INIT, INIT, STARTUP sequence.
696 */
697static void send_init_sequence(u32 phys_apicid)
698{
699 int maxlvt = lapic_get_maxlvt();
700
701 /* Be paranoid about clearing APIC errors. */
702 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
703 /* Due to the Pentium erratum 3AP. */
704 if (maxlvt > 3)
705 apic_write(APIC_ESR, 0);
706 apic_read(APIC_ESR);
707 }
708
709 /* Assert INIT on the target CPU */
710 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
711 safe_apic_wait_icr_idle();
712
713 udelay(init_udelay);
714
715 /* Deassert INIT on the target CPU */
716 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
717 safe_apic_wait_icr_idle();
718}
719
720/*
721 * Wake up AP by INIT, INIT, STARTUP sequence.
722 */
723static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip)
724{
725 unsigned long send_status = 0, accept_status = 0;
726 int num_starts, j, maxlvt;
727
728 preempt_disable();
729 maxlvt = lapic_get_maxlvt();
730 send_init_sequence(phys_apicid);
731
732 mb();
733
734 /*
735 * Should we send STARTUP IPIs ?
736 *
737 * Determine this based on the APIC version.
738 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
739 */
740 if (APIC_INTEGRATED(boot_cpu_apic_version))
741 num_starts = 2;
742 else
743 num_starts = 0;
744
745 /*
746 * Run STARTUP IPI loop.
747 */
748 pr_debug("#startup loops: %d\n", num_starts);
749
750 for (j = 1; j <= num_starts; j++) {
751 pr_debug("Sending STARTUP #%d\n", j);
752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
753 apic_write(APIC_ESR, 0);
754 apic_read(APIC_ESR);
755 pr_debug("After apic_write\n");
756
757 /*
758 * STARTUP IPI
759 */
760
761 /* Target chip */
762 /* Boot on the stack */
763 /* Kick the second */
764 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
765 phys_apicid);
766
767 /*
768 * Give the other CPU some time to accept the IPI.
769 */
770 if (init_udelay == 0)
771 udelay(10);
772 else
773 udelay(300);
774
775 pr_debug("Startup point 1\n");
776
777 pr_debug("Waiting for send to finish...\n");
778 send_status = safe_apic_wait_icr_idle();
779
780 /*
781 * Give the other CPU some time to accept the IPI.
782 */
783 if (init_udelay == 0)
784 udelay(10);
785 else
786 udelay(200);
787
788 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
789 apic_write(APIC_ESR, 0);
790 accept_status = (apic_read(APIC_ESR) & 0xEF);
791 if (send_status || accept_status)
792 break;
793 }
794 pr_debug("After Startup\n");
795
796 if (send_status)
797 pr_err("APIC never delivered???\n");
798 if (accept_status)
799 pr_err("APIC delivery error (%lx)\n", accept_status);
800
801 preempt_enable();
802 return (send_status | accept_status);
803}
804
805/* reduce the number of lines printed when booting a large cpu count system */
806static void announce_cpu(int cpu, int apicid)
807{
808 static int width, node_width, first = 1;
809 static int current_node = NUMA_NO_NODE;
810 int node = early_cpu_to_node(cpu);
811
812 if (!width)
813 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
814
815 if (!node_width)
816 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
817
818 if (system_state < SYSTEM_RUNNING) {
819 if (first)
820 pr_info("x86: Booting SMP configuration:\n");
821
822 if (node != current_node) {
823 if (current_node > (-1))
824 pr_cont("\n");
825 current_node = node;
826
827 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
828 node_width - num_digits(node), " ", node);
829 }
830
831 /* Add padding for the BSP */
832 if (first)
833 pr_cont("%*s", width + 1, " ");
834 first = 0;
835
836 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
837 } else
838 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
839 node, cpu, apicid);
840}
841
842int common_cpu_up(unsigned int cpu, struct task_struct *idle)
843{
844 int ret;
845
846 /* Just in case we booted with a single CPU. */
847 alternatives_enable_smp();
848
849 per_cpu(pcpu_hot.current_task, cpu) = idle;
850 cpu_init_stack_canary(cpu, idle);
851
852 /* Initialize the interrupt stack(s) */
853 ret = irq_init_percpu_irqstack(cpu);
854 if (ret)
855 return ret;
856
857#ifdef CONFIG_X86_32
858 /* Stack for startup_32 can be just as for start_secondary onwards */
859 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
860#endif
861 return 0;
862}
863
864/*
865 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
866 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
867 * Returns zero if startup was successfully sent, else error code from
868 * ->wakeup_secondary_cpu.
869 */
870static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle)
871{
872 unsigned long start_ip = real_mode_header->trampoline_start;
873 int ret;
874
875#ifdef CONFIG_X86_64
876 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
877 if (apic->wakeup_secondary_cpu_64)
878 start_ip = real_mode_header->trampoline_start64;
879#endif
880 idle->thread.sp = (unsigned long)task_pt_regs(idle);
881 initial_code = (unsigned long)start_secondary;
882
883 if (IS_ENABLED(CONFIG_X86_32)) {
884 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
885 initial_stack = idle->thread.sp;
886 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
887 smpboot_control = cpu;
888 }
889
890 /* Enable the espfix hack for this CPU */
891 init_espfix_ap(cpu);
892
893 /* So we see what's up */
894 announce_cpu(cpu, apicid);
895
896 /*
897 * This grunge runs the startup process for
898 * the targeted processor.
899 */
900 if (x86_platform.legacy.warm_reset) {
901
902 pr_debug("Setting warm reset code and vector.\n");
903
904 smpboot_setup_warm_reset_vector(start_ip);
905 /*
906 * Be paranoid about clearing APIC errors.
907 */
908 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
909 apic_write(APIC_ESR, 0);
910 apic_read(APIC_ESR);
911 }
912 }
913
914 smp_mb();
915
916 /*
917 * Wake up a CPU in difference cases:
918 * - Use a method from the APIC driver if one defined, with wakeup
919 * straight to 64-bit mode preferred over wakeup to RM.
920 * Otherwise,
921 * - Use an INIT boot APIC message
922 */
923 if (apic->wakeup_secondary_cpu_64)
924 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
925 else if (apic->wakeup_secondary_cpu)
926 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
927 else
928 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
929
930 /* If the wakeup mechanism failed, cleanup the warm reset vector */
931 if (ret)
932 arch_cpuhp_cleanup_kick_cpu(cpu);
933 return ret;
934}
935
936int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
937{
938 u32 apicid = apic->cpu_present_to_apicid(cpu);
939 int err;
940
941 lockdep_assert_irqs_enabled();
942
943 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
944
945 if (apicid == BAD_APICID || !apic_id_valid(apicid)) {
946 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid);
947 return -EINVAL;
948 }
949
950 if (!test_bit(apicid, phys_cpu_present_map)) {
951 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid);
952 return -EINVAL;
953 }
954
955 /*
956 * Save current MTRR state in case it was changed since early boot
957 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
958 */
959 mtrr_save_state();
960
961 /* the FPU context is blank, nobody can own it */
962 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
963
964 err = common_cpu_up(cpu, tidle);
965 if (err)
966 return err;
967
968 err = do_boot_cpu(apicid, cpu, tidle);
969 if (err)
970 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
971
972 return err;
973}
974
975int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
976{
977 return smp_ops.kick_ap_alive(cpu, tidle);
978}
979
980void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
981{
982 /* Cleanup possible dangling ends... */
983 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
984 smpboot_restore_warm_reset_vector();
985}
986
987void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
988{
989 if (smp_ops.cleanup_dead_cpu)
990 smp_ops.cleanup_dead_cpu(cpu);
991
992 if (system_state == SYSTEM_RUNNING)
993 pr_info("CPU %u is now offline\n", cpu);
994}
995
996void arch_cpuhp_sync_state_poll(void)
997{
998 if (smp_ops.poll_sync_state)
999 smp_ops.poll_sync_state();
1000}
1001
1002/**
1003 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1004 */
1005void __init arch_disable_smp_support(void)
1006{
1007 disable_ioapic_support();
1008}
1009
1010/*
1011 * Fall back to non SMP mode after errors.
1012 *
1013 * RED-PEN audit/test this more. I bet there is more state messed up here.
1014 */
1015static __init void disable_smp(void)
1016{
1017 pr_info("SMP disabled\n");
1018
1019 disable_ioapic_support();
1020 topology_reset_possible_cpus_up();
1021
1022 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1023 cpumask_set_cpu(0, topology_core_cpumask(0));
1024 cpumask_set_cpu(0, topology_die_cpumask(0));
1025}
1026
1027void __init smp_prepare_cpus_common(void)
1028{
1029 unsigned int cpu, node;
1030
1031 /* Mark all except the boot CPU as hotpluggable */
1032 for_each_possible_cpu(cpu) {
1033 if (cpu)
1034 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids;
1035 }
1036
1037 for_each_possible_cpu(cpu) {
1038 node = cpu_to_node(cpu);
1039
1040 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node);
1041 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node);
1042 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node);
1043 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node);
1044 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node);
1045 }
1046
1047 set_cpu_sibling_map(0);
1048}
1049
1050void __init smp_prepare_boot_cpu(void)
1051{
1052 smp_ops.smp_prepare_boot_cpu();
1053}
1054
1055#ifdef CONFIG_X86_64
1056/* Establish whether parallel bringup can be supported. */
1057bool __init arch_cpuhp_init_parallel_bringup(void)
1058{
1059 if (!x86_cpuinit.parallel_bringup) {
1060 pr_info("Parallel CPU startup disabled by the platform\n");
1061 return false;
1062 }
1063
1064 smpboot_control = STARTUP_READ_APICID;
1065 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1066 return true;
1067}
1068#endif
1069
1070/*
1071 * Prepare for SMP bootup.
1072 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1073 * for common interface support.
1074 */
1075void __init native_smp_prepare_cpus(unsigned int max_cpus)
1076{
1077 smp_prepare_cpus_common();
1078
1079 switch (apic_intr_mode) {
1080 case APIC_PIC:
1081 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1082 disable_smp();
1083 return;
1084 case APIC_SYMMETRIC_IO_NO_ROUTING:
1085 disable_smp();
1086 /* Setup local timer */
1087 x86_init.timers.setup_percpu_clockev();
1088 return;
1089 case APIC_VIRTUAL_WIRE:
1090 case APIC_SYMMETRIC_IO:
1091 break;
1092 }
1093
1094 /* Setup local timer */
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 pr_info("CPU0: ");
1098 print_cpu_info(&cpu_data(0));
1099
1100 uv_system_init();
1101
1102 smp_quirk_init_udelay();
1103
1104 speculative_store_bypass_ht_init();
1105
1106 snp_set_wakeup_secondary_cpu();
1107}
1108
1109void arch_thaw_secondary_cpus_begin(void)
1110{
1111 set_cache_aps_delayed_init(true);
1112}
1113
1114void arch_thaw_secondary_cpus_end(void)
1115{
1116 cache_aps_init();
1117}
1118
1119/*
1120 * Early setup to make printk work.
1121 */
1122void __init native_smp_prepare_boot_cpu(void)
1123{
1124 int me = smp_processor_id();
1125
1126 /* SMP handles this from setup_per_cpu_areas() */
1127 if (!IS_ENABLED(CONFIG_SMP))
1128 switch_gdt_and_percpu_base(me);
1129
1130 native_pv_lock_init();
1131}
1132
1133void __init native_smp_cpus_done(unsigned int max_cpus)
1134{
1135 pr_debug("Boot done\n");
1136
1137 build_sched_topology();
1138 nmi_selftest();
1139 impress_friends();
1140 cache_aps_init();
1141}
1142
1143/* correctly size the local cpu masks */
1144void __init setup_cpu_local_masks(void)
1145{
1146 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1147}
1148
1149#ifdef CONFIG_HOTPLUG_CPU
1150
1151/* Recompute SMT state for all CPUs on offline */
1152static void recompute_smt_state(void)
1153{
1154 int max_threads, cpu;
1155
1156 max_threads = 0;
1157 for_each_online_cpu (cpu) {
1158 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1159
1160 if (threads > max_threads)
1161 max_threads = threads;
1162 }
1163 __max_smt_threads = max_threads;
1164}
1165
1166static void remove_siblinginfo(int cpu)
1167{
1168 int sibling;
1169 struct cpuinfo_x86 *c = &cpu_data(cpu);
1170
1171 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1172 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1173 /*/
1174 * last thread sibling in this cpu core going down
1175 */
1176 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1177 cpu_data(sibling).booted_cores--;
1178 }
1179
1180 for_each_cpu(sibling, topology_die_cpumask(cpu))
1181 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1182
1183 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1184 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1185 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1186 cpu_data(sibling).smt_active = false;
1187 }
1188
1189 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1190 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1191 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1192 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1193 cpumask_clear(cpu_llc_shared_mask(cpu));
1194 cpumask_clear(cpu_l2c_shared_mask(cpu));
1195 cpumask_clear(topology_sibling_cpumask(cpu));
1196 cpumask_clear(topology_core_cpumask(cpu));
1197 cpumask_clear(topology_die_cpumask(cpu));
1198 c->topo.core_id = 0;
1199 c->booted_cores = 0;
1200 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1201 recompute_smt_state();
1202}
1203
1204static void remove_cpu_from_maps(int cpu)
1205{
1206 set_cpu_online(cpu, false);
1207 numa_remove_cpu(cpu);
1208}
1209
1210void cpu_disable_common(void)
1211{
1212 int cpu = smp_processor_id();
1213
1214 remove_siblinginfo(cpu);
1215
1216 /* It's now safe to remove this processor from the online map */
1217 lock_vector_lock();
1218 remove_cpu_from_maps(cpu);
1219 unlock_vector_lock();
1220 fixup_irqs();
1221 lapic_offline();
1222}
1223
1224int native_cpu_disable(void)
1225{
1226 int ret;
1227
1228 ret = lapic_can_unplug_cpu();
1229 if (ret)
1230 return ret;
1231
1232 cpu_disable_common();
1233
1234 /*
1235 * Disable the local APIC. Otherwise IPI broadcasts will reach
1236 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1237 * messages.
1238 *
1239 * Disabling the APIC must happen after cpu_disable_common()
1240 * which invokes fixup_irqs().
1241 *
1242 * Disabling the APIC preserves already set bits in IRR, but
1243 * an interrupt arriving after disabling the local APIC does not
1244 * set the corresponding IRR bit.
1245 *
1246 * fixup_irqs() scans IRR for set bits so it can raise a not
1247 * yet handled interrupt on the new destination CPU via an IPI
1248 * but obviously it can't do so for IRR bits which are not set.
1249 * IOW, interrupts arriving after disabling the local APIC will
1250 * be lost.
1251 */
1252 apic_soft_disable();
1253
1254 return 0;
1255}
1256
1257void play_dead_common(void)
1258{
1259 idle_task_exit();
1260
1261 cpuhp_ap_report_dead();
1262
1263 local_irq_disable();
1264}
1265
1266/*
1267 * We need to flush the caches before going to sleep, lest we have
1268 * dirty data in our caches when we come back up.
1269 */
1270static inline void mwait_play_dead(void)
1271{
1272 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1273 unsigned int eax, ebx, ecx, edx;
1274 unsigned int highest_cstate = 0;
1275 unsigned int highest_subcstate = 0;
1276 int i;
1277
1278 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1279 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1280 return;
1281 if (!this_cpu_has(X86_FEATURE_MWAIT))
1282 return;
1283 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1284 return;
1285 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1286 return;
1287
1288 eax = CPUID_MWAIT_LEAF;
1289 ecx = 0;
1290 native_cpuid(&eax, &ebx, &ecx, &edx);
1291
1292 /*
1293 * eax will be 0 if EDX enumeration is not valid.
1294 * Initialized below to cstate, sub_cstate value when EDX is valid.
1295 */
1296 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1297 eax = 0;
1298 } else {
1299 edx >>= MWAIT_SUBSTATE_SIZE;
1300 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1301 if (edx & MWAIT_SUBSTATE_MASK) {
1302 highest_cstate = i;
1303 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1304 }
1305 }
1306 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1307 (highest_subcstate - 1);
1308 }
1309
1310 /* Set up state for the kexec() hack below */
1311 md->status = CPUDEAD_MWAIT_WAIT;
1312 md->control = CPUDEAD_MWAIT_WAIT;
1313
1314 wbinvd();
1315
1316 while (1) {
1317 /*
1318 * The CLFLUSH is a workaround for erratum AAI65 for
1319 * the Xeon 7400 series. It's not clear it is actually
1320 * needed, but it should be harmless in either case.
1321 * The WBINVD is insufficient due to the spurious-wakeup
1322 * case where we return around the loop.
1323 */
1324 mb();
1325 clflush(md);
1326 mb();
1327 __monitor(md, 0, 0);
1328 mb();
1329 __mwait(eax, 0);
1330
1331 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1332 /*
1333 * Kexec is about to happen. Don't go back into mwait() as
1334 * the kexec kernel might overwrite text and data including
1335 * page tables and stack. So mwait() would resume when the
1336 * monitor cache line is written to and then the CPU goes
1337 * south due to overwritten text, page tables and stack.
1338 *
1339 * Note: This does _NOT_ protect against a stray MCE, NMI,
1340 * SMI. They will resume execution at the instruction
1341 * following the HLT instruction and run into the problem
1342 * which this is trying to prevent.
1343 */
1344 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1345 while(1)
1346 native_halt();
1347 }
1348 }
1349}
1350
1351/*
1352 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1353 * mwait_play_dead().
1354 */
1355void smp_kick_mwait_play_dead(void)
1356{
1357 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1358 struct mwait_cpu_dead *md;
1359 unsigned int cpu, i;
1360
1361 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1362 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1363
1364 /* Does it sit in mwait_play_dead() ? */
1365 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1366 continue;
1367
1368 /* Wait up to 5ms */
1369 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1370 /* Bring it out of mwait */
1371 WRITE_ONCE(md->control, newstate);
1372 udelay(5);
1373 }
1374
1375 if (READ_ONCE(md->status) != newstate)
1376 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1377 }
1378}
1379
1380void __noreturn hlt_play_dead(void)
1381{
1382 if (__this_cpu_read(cpu_info.x86) >= 4)
1383 wbinvd();
1384
1385 while (1)
1386 native_halt();
1387}
1388
1389/*
1390 * native_play_dead() is essentially a __noreturn function, but it can't
1391 * be marked as such as the compiler may complain about it.
1392 */
1393void native_play_dead(void)
1394{
1395 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1396 __update_spec_ctrl(0);
1397
1398 play_dead_common();
1399 tboot_shutdown(TB_SHUTDOWN_WFS);
1400
1401 mwait_play_dead();
1402 if (cpuidle_play_dead())
1403 hlt_play_dead();
1404}
1405
1406#else /* ... !CONFIG_HOTPLUG_CPU */
1407int native_cpu_disable(void)
1408{
1409 return -ENOSYS;
1410}
1411
1412void native_play_dead(void)
1413{
1414 BUG();
1415}
1416
1417#endif
1/*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/module.h>
45#include <linux/sched.h>
46#include <linux/percpu.h>
47#include <linux/bootmem.h>
48#include <linux/err.h>
49#include <linux/nmi.h>
50#include <linux/tboot.h>
51#include <linux/stackprotector.h>
52#include <linux/gfp.h>
53
54#include <asm/acpi.h>
55#include <asm/desc.h>
56#include <asm/nmi.h>
57#include <asm/irq.h>
58#include <asm/idle.h>
59#include <asm/trampoline.h>
60#include <asm/cpu.h>
61#include <asm/numa.h>
62#include <asm/pgtable.h>
63#include <asm/tlbflush.h>
64#include <asm/mtrr.h>
65#include <asm/mwait.h>
66#include <asm/apic.h>
67#include <asm/io_apic.h>
68#include <asm/setup.h>
69#include <asm/uv/uv.h>
70#include <linux/mc146818rtc.h>
71
72#include <asm/smpboot_hooks.h>
73#include <asm/i8259.h>
74
75/* State of each CPU */
76DEFINE_PER_CPU(int, cpu_state) = { 0 };
77
78/* Store all idle threads, this can be reused instead of creating
79* a new thread. Also avoids complicated thread destroy functionality
80* for idle threads.
81*/
82#ifdef CONFIG_HOTPLUG_CPU
83/*
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
86 */
87static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
90
91/*
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
94 */
95static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
96
97void cpu_hotplug_driver_lock(void)
98{
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
100}
101
102void cpu_hotplug_driver_unlock(void)
103{
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
105}
106
107ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
109#else
110static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111#define get_idle_for_cpu(x) (idle_thread_array[(x)])
112#define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
113#endif
114
115/* Number of siblings per CPU package */
116int smp_num_siblings = 1;
117EXPORT_SYMBOL(smp_num_siblings);
118
119/* Last level cache ID of each logical CPU */
120DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
121
122/* representing HT siblings of each logical CPU */
123DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
125
126/* representing HT and core siblings of each logical CPU */
127DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128EXPORT_PER_CPU_SYMBOL(cpu_core_map);
129
130DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
131
132/* Per CPU bogomips and other parameters */
133DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134EXPORT_PER_CPU_SYMBOL(cpu_info);
135
136atomic_t init_deasserted;
137
138/*
139 * Report back to the Boot Processor.
140 * Running on AP.
141 */
142static void __cpuinit smp_callin(void)
143{
144 int cpuid, phys_id;
145 unsigned long timeout;
146
147 /*
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
152 */
153 if (apic->wait_for_init_deassert)
154 apic->wait_for_init_deassert(&init_deasserted);
155
156 /*
157 * (This works even if the APIC is not enabled.)
158 */
159 phys_id = read_apic_id();
160 cpuid = smp_processor_id();
161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
163 phys_id, cpuid);
164 }
165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
166
167 /*
168 * STARTUP IPIs are fragile beasts as they might sometimes
169 * trigger some glue motherboard logic. Complete APIC bus
170 * silence for 1 second, this overestimates the time the
171 * boot CPU is spending to send the up to 2 STARTUP IPIs
172 * by a factor of two. This should be enough.
173 */
174
175 /*
176 * Waiting 2s total for startup (udelay is not yet working)
177 */
178 timeout = jiffies + 2*HZ;
179 while (time_before(jiffies, timeout)) {
180 /*
181 * Has the boot CPU finished it's STARTUP sequence?
182 */
183 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
184 break;
185 cpu_relax();
186 }
187
188 if (!time_before(jiffies, timeout)) {
189 panic("%s: CPU%d started up but did not get a callout!\n",
190 __func__, cpuid);
191 }
192
193 /*
194 * the boot CPU has finished the init stage and is spinning
195 * on callin_map until we finish. We are free to set up this
196 * CPU, first the APIC. (this is probably redundant on most
197 * boards)
198 */
199
200 pr_debug("CALLIN, before setup_local_APIC().\n");
201 if (apic->smp_callin_clear_local_apic)
202 apic->smp_callin_clear_local_apic();
203 setup_local_APIC();
204 end_local_APIC_setup();
205
206 /*
207 * Need to setup vector mappings before we enable interrupts.
208 */
209 setup_vector_irq(smp_processor_id());
210 /*
211 * Get our bogomips.
212 *
213 * Need to enable IRQs because it can take longer and then
214 * the NMI watchdog might kill us.
215 */
216 local_irq_enable();
217 calibrate_delay();
218 local_irq_disable();
219 pr_debug("Stack at about %p\n", &cpuid);
220
221 /*
222 * Save our processor parameters
223 */
224 smp_store_cpu_info(cpuid);
225
226 /*
227 * This must be done before setting cpu_online_mask
228 * or calling notify_cpu_starting.
229 */
230 set_cpu_sibling_map(raw_smp_processor_id());
231 wmb();
232
233 notify_cpu_starting(cpuid);
234
235 /*
236 * Allow the master to continue.
237 */
238 cpumask_set_cpu(cpuid, cpu_callin_mask);
239}
240
241/*
242 * Activate a secondary processor.
243 */
244notrace static void __cpuinit start_secondary(void *unused)
245{
246 /*
247 * Don't put *anything* before cpu_init(), SMP booting is too
248 * fragile that we want to limit the things done here to the
249 * most necessary things.
250 */
251 cpu_init();
252 preempt_disable();
253 smp_callin();
254
255#ifdef CONFIG_X86_32
256 /* switch away from the initial page table */
257 load_cr3(swapper_pg_dir);
258 __flush_tlb_all();
259#endif
260
261 /* otherwise gcc will move up smp_processor_id before the cpu_init */
262 barrier();
263 /*
264 * Check TSC synchronization with the BP:
265 */
266 check_tsc_sync_target();
267
268 /*
269 * We need to hold call_lock, so there is no inconsistency
270 * between the time smp_call_function() determines number of
271 * IPI recipients, and the time when the determination is made
272 * for which cpus receive the IPI. Holding this
273 * lock helps us to not include this cpu in a currently in progress
274 * smp_call_function().
275 *
276 * We need to hold vector_lock so there the set of online cpus
277 * does not change while we are assigning vectors to cpus. Holding
278 * this lock ensures we don't half assign or remove an irq from a cpu.
279 */
280 ipi_call_lock();
281 lock_vector_lock();
282 set_cpu_online(smp_processor_id(), true);
283 unlock_vector_lock();
284 ipi_call_unlock();
285 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
286 x86_platform.nmi_init();
287
288 /*
289 * Wait until the cpu which brought this one up marked it
290 * online before enabling interrupts. If we don't do that then
291 * we can end up waking up the softirq thread before this cpu
292 * reached the active state, which makes the scheduler unhappy
293 * and schedule the softirq thread on the wrong cpu. This is
294 * only observable with forced threaded interrupts, but in
295 * theory it could also happen w/o them. It's just way harder
296 * to achieve.
297 */
298 while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask))
299 cpu_relax();
300
301 /* enable local interrupts */
302 local_irq_enable();
303
304 /* to prevent fake stack check failure in clock setup */
305 boot_init_stack_canary();
306
307 x86_cpuinit.setup_percpu_clockev();
308
309 wmb();
310 cpu_idle();
311}
312
313/*
314 * The bootstrap kernel entry code has set these up. Save them for
315 * a given CPU
316 */
317
318void __cpuinit smp_store_cpu_info(int id)
319{
320 struct cpuinfo_x86 *c = &cpu_data(id);
321
322 *c = boot_cpu_data;
323 c->cpu_index = id;
324 if (id != 0)
325 identify_secondary_cpu(c);
326}
327
328static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
329{
330 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
331 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
332 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
333 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
334 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
335 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
336}
337
338
339void __cpuinit set_cpu_sibling_map(int cpu)
340{
341 int i;
342 struct cpuinfo_x86 *c = &cpu_data(cpu);
343
344 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
345
346 if (smp_num_siblings > 1) {
347 for_each_cpu(i, cpu_sibling_setup_mask) {
348 struct cpuinfo_x86 *o = &cpu_data(i);
349
350 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
351 if (c->phys_proc_id == o->phys_proc_id &&
352 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
353 c->compute_unit_id == o->compute_unit_id)
354 link_thread_siblings(cpu, i);
355 } else if (c->phys_proc_id == o->phys_proc_id &&
356 c->cpu_core_id == o->cpu_core_id) {
357 link_thread_siblings(cpu, i);
358 }
359 }
360 } else {
361 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
362 }
363
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365
366 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
367 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
368 c->booted_cores = 1;
369 return;
370 }
371
372 for_each_cpu(i, cpu_sibling_setup_mask) {
373 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
374 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
375 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
376 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
377 }
378 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
379 cpumask_set_cpu(i, cpu_core_mask(cpu));
380 cpumask_set_cpu(cpu, cpu_core_mask(i));
381 /*
382 * Does this new cpu bringup a new core?
383 */
384 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
385 /*
386 * for each core in package, increment
387 * the booted_cores for this new cpu
388 */
389 if (cpumask_first(cpu_sibling_mask(i)) == i)
390 c->booted_cores++;
391 /*
392 * increment the core count for all
393 * the other cpus in this package
394 */
395 if (i != cpu)
396 cpu_data(i).booted_cores++;
397 } else if (i != cpu && !c->booted_cores)
398 c->booted_cores = cpu_data(i).booted_cores;
399 }
400 }
401}
402
403/* maps the cpu to the sched domain representing multi-core */
404const struct cpumask *cpu_coregroup_mask(int cpu)
405{
406 struct cpuinfo_x86 *c = &cpu_data(cpu);
407 /*
408 * For perf, we return last level cache shared map.
409 * And for power savings, we return cpu_core_map
410 */
411 if ((sched_mc_power_savings || sched_smt_power_savings) &&
412 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
413 return cpu_core_mask(cpu);
414 else
415 return cpu_llc_shared_mask(cpu);
416}
417
418static void impress_friends(void)
419{
420 int cpu;
421 unsigned long bogosum = 0;
422 /*
423 * Allow the user to impress friends.
424 */
425 pr_debug("Before bogomips.\n");
426 for_each_possible_cpu(cpu)
427 if (cpumask_test_cpu(cpu, cpu_callout_mask))
428 bogosum += cpu_data(cpu).loops_per_jiffy;
429 printk(KERN_INFO
430 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
431 num_online_cpus(),
432 bogosum/(500000/HZ),
433 (bogosum/(5000/HZ))%100);
434
435 pr_debug("Before bogocount - setting activated=1.\n");
436}
437
438void __inquire_remote_apic(int apicid)
439{
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 const char * const names[] = { "ID", "VERSION", "SPIV" };
442 int timeout;
443 u32 status;
444
445 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
446
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
449
450 /*
451 * Wait for idle.
452 */
453 status = safe_apic_wait_icr_idle();
454 if (status)
455 printk(KERN_CONT
456 "a previous APIC delivery may have failed\n");
457
458 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
459
460 timeout = 0;
461 do {
462 udelay(100);
463 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
464 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
465
466 switch (status) {
467 case APIC_ICR_RR_VALID:
468 status = apic_read(APIC_RRR);
469 printk(KERN_CONT "%08x\n", status);
470 break;
471 default:
472 printk(KERN_CONT "failed\n");
473 }
474 }
475}
476
477/*
478 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
479 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
480 * won't ... remember to clear down the APIC, etc later.
481 */
482int __cpuinit
483wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
484{
485 unsigned long send_status, accept_status = 0;
486 int maxlvt;
487
488 /* Target chip */
489 /* Boot on the stack */
490 /* Kick the second */
491 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
492
493 pr_debug("Waiting for send to finish...\n");
494 send_status = safe_apic_wait_icr_idle();
495
496 /*
497 * Give the other CPU some time to accept the IPI.
498 */
499 udelay(200);
500 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
501 maxlvt = lapic_get_maxlvt();
502 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
503 apic_write(APIC_ESR, 0);
504 accept_status = (apic_read(APIC_ESR) & 0xEF);
505 }
506 pr_debug("NMI sent.\n");
507
508 if (send_status)
509 printk(KERN_ERR "APIC never delivered???\n");
510 if (accept_status)
511 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
512
513 return (send_status | accept_status);
514}
515
516static int __cpuinit
517wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
518{
519 unsigned long send_status, accept_status = 0;
520 int maxlvt, num_starts, j;
521
522 maxlvt = lapic_get_maxlvt();
523
524 /*
525 * Be paranoid about clearing APIC errors.
526 */
527 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
529 apic_write(APIC_ESR, 0);
530 apic_read(APIC_ESR);
531 }
532
533 pr_debug("Asserting INIT.\n");
534
535 /*
536 * Turn INIT on target chip
537 */
538 /*
539 * Send IPI
540 */
541 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
542 phys_apicid);
543
544 pr_debug("Waiting for send to finish...\n");
545 send_status = safe_apic_wait_icr_idle();
546
547 mdelay(10);
548
549 pr_debug("Deasserting INIT.\n");
550
551 /* Target chip */
552 /* Send IPI */
553 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
554
555 pr_debug("Waiting for send to finish...\n");
556 send_status = safe_apic_wait_icr_idle();
557
558 mb();
559 atomic_set(&init_deasserted, 1);
560
561 /*
562 * Should we send STARTUP IPIs ?
563 *
564 * Determine this based on the APIC version.
565 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
566 */
567 if (APIC_INTEGRATED(apic_version[phys_apicid]))
568 num_starts = 2;
569 else
570 num_starts = 0;
571
572 /*
573 * Paravirt / VMI wants a startup IPI hook here to set up the
574 * target processor state.
575 */
576 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
577 stack_start);
578
579 /*
580 * Run STARTUP IPI loop.
581 */
582 pr_debug("#startup loops: %d.\n", num_starts);
583
584 for (j = 1; j <= num_starts; j++) {
585 pr_debug("Sending STARTUP #%d.\n", j);
586 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
587 apic_write(APIC_ESR, 0);
588 apic_read(APIC_ESR);
589 pr_debug("After apic_write.\n");
590
591 /*
592 * STARTUP IPI
593 */
594
595 /* Target chip */
596 /* Boot on the stack */
597 /* Kick the second */
598 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
599 phys_apicid);
600
601 /*
602 * Give the other CPU some time to accept the IPI.
603 */
604 udelay(300);
605
606 pr_debug("Startup point 1.\n");
607
608 pr_debug("Waiting for send to finish...\n");
609 send_status = safe_apic_wait_icr_idle();
610
611 /*
612 * Give the other CPU some time to accept the IPI.
613 */
614 udelay(200);
615 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
616 apic_write(APIC_ESR, 0);
617 accept_status = (apic_read(APIC_ESR) & 0xEF);
618 if (send_status || accept_status)
619 break;
620 }
621 pr_debug("After Startup.\n");
622
623 if (send_status)
624 printk(KERN_ERR "APIC never delivered???\n");
625 if (accept_status)
626 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
627
628 return (send_status | accept_status);
629}
630
631struct create_idle {
632 struct work_struct work;
633 struct task_struct *idle;
634 struct completion done;
635 int cpu;
636};
637
638static void __cpuinit do_fork_idle(struct work_struct *work)
639{
640 struct create_idle *c_idle =
641 container_of(work, struct create_idle, work);
642
643 c_idle->idle = fork_idle(c_idle->cpu);
644 complete(&c_idle->done);
645}
646
647/* reduce the number of lines printed when booting a large cpu count system */
648static void __cpuinit announce_cpu(int cpu, int apicid)
649{
650 static int current_node = -1;
651 int node = early_cpu_to_node(cpu);
652
653 if (system_state == SYSTEM_BOOTING) {
654 if (node != current_node) {
655 if (current_node > (-1))
656 pr_cont(" Ok.\n");
657 current_node = node;
658 pr_info("Booting Node %3d, Processors ", node);
659 }
660 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
661 return;
662 } else
663 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
664 node, cpu, apicid);
665}
666
667/*
668 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
669 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
670 * Returns zero if CPU booted OK, else error code from
671 * ->wakeup_secondary_cpu.
672 */
673static int __cpuinit do_boot_cpu(int apicid, int cpu)
674{
675 unsigned long boot_error = 0;
676 unsigned long start_ip;
677 int timeout;
678 struct create_idle c_idle = {
679 .cpu = cpu,
680 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
681 };
682
683 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
684
685 alternatives_smp_switch(1);
686
687 c_idle.idle = get_idle_for_cpu(cpu);
688
689 /*
690 * We can't use kernel_thread since we must avoid to
691 * reschedule the child.
692 */
693 if (c_idle.idle) {
694 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
695 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
696 init_idle(c_idle.idle, cpu);
697 goto do_rest;
698 }
699
700 schedule_work(&c_idle.work);
701 wait_for_completion(&c_idle.done);
702
703 if (IS_ERR(c_idle.idle)) {
704 printk("failed fork for CPU %d\n", cpu);
705 destroy_work_on_stack(&c_idle.work);
706 return PTR_ERR(c_idle.idle);
707 }
708
709 set_idle_for_cpu(cpu, c_idle.idle);
710do_rest:
711 per_cpu(current_task, cpu) = c_idle.idle;
712#ifdef CONFIG_X86_32
713 /* Stack for startup_32 can be just as for start_secondary onwards */
714 irq_ctx_init(cpu);
715#else
716 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
717 initial_gs = per_cpu_offset(cpu);
718 per_cpu(kernel_stack, cpu) =
719 (unsigned long)task_stack_page(c_idle.idle) -
720 KERNEL_STACK_OFFSET + THREAD_SIZE;
721#endif
722 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
723 initial_code = (unsigned long)start_secondary;
724 stack_start = c_idle.idle->thread.sp;
725
726 /* start_ip had better be page-aligned! */
727 start_ip = trampoline_address();
728
729 /* So we see what's up */
730 announce_cpu(cpu, apicid);
731
732 /*
733 * This grunge runs the startup process for
734 * the targeted processor.
735 */
736
737 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
738
739 atomic_set(&init_deasserted, 0);
740
741 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
742
743 pr_debug("Setting warm reset code and vector.\n");
744
745 smpboot_setup_warm_reset_vector(start_ip);
746 /*
747 * Be paranoid about clearing APIC errors.
748 */
749 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
750 apic_write(APIC_ESR, 0);
751 apic_read(APIC_ESR);
752 }
753 }
754
755 /*
756 * Kick the secondary CPU. Use the method in the APIC driver
757 * if it's defined - or use an INIT boot APIC message otherwise:
758 */
759 if (apic->wakeup_secondary_cpu)
760 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
761 else
762 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
763
764 if (!boot_error) {
765 /*
766 * allow APs to start initializing.
767 */
768 pr_debug("Before Callout %d.\n", cpu);
769 cpumask_set_cpu(cpu, cpu_callout_mask);
770 pr_debug("After Callout %d.\n", cpu);
771
772 /*
773 * Wait 5s total for a response
774 */
775 for (timeout = 0; timeout < 50000; timeout++) {
776 if (cpumask_test_cpu(cpu, cpu_callin_mask))
777 break; /* It has booted */
778 udelay(100);
779 /*
780 * Allow other tasks to run while we wait for the
781 * AP to come online. This also gives a chance
782 * for the MTRR work(triggered by the AP coming online)
783 * to be completed in the stop machine context.
784 */
785 schedule();
786 }
787
788 if (cpumask_test_cpu(cpu, cpu_callin_mask))
789 pr_debug("CPU%d: has booted.\n", cpu);
790 else {
791 boot_error = 1;
792 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
793 == 0xA5A5A5A5)
794 /* trampoline started but...? */
795 pr_err("CPU%d: Stuck ??\n", cpu);
796 else
797 /* trampoline code not run */
798 pr_err("CPU%d: Not responding.\n", cpu);
799 if (apic->inquire_remote_apic)
800 apic->inquire_remote_apic(apicid);
801 }
802 }
803
804 if (boot_error) {
805 /* Try to put things back the way they were before ... */
806 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
807
808 /* was set by do_boot_cpu() */
809 cpumask_clear_cpu(cpu, cpu_callout_mask);
810
811 /* was set by cpu_init() */
812 cpumask_clear_cpu(cpu, cpu_initialized_mask);
813
814 set_cpu_present(cpu, false);
815 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
816 }
817
818 /* mark "stuck" area as not stuck */
819 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
820
821 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
822 /*
823 * Cleanup possible dangling ends...
824 */
825 smpboot_restore_warm_reset_vector();
826 }
827
828 destroy_work_on_stack(&c_idle.work);
829 return boot_error;
830}
831
832int __cpuinit native_cpu_up(unsigned int cpu)
833{
834 int apicid = apic->cpu_present_to_apicid(cpu);
835 unsigned long flags;
836 int err;
837
838 WARN_ON(irqs_disabled());
839
840 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
841
842 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
843 !physid_isset(apicid, phys_cpu_present_map)) {
844 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
845 return -EINVAL;
846 }
847
848 /*
849 * Already booted CPU?
850 */
851 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
852 pr_debug("do_boot_cpu %d Already started\n", cpu);
853 return -ENOSYS;
854 }
855
856 /*
857 * Save current MTRR state in case it was changed since early boot
858 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
859 */
860 mtrr_save_state();
861
862 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
863
864 err = do_boot_cpu(apicid, cpu);
865 if (err) {
866 pr_debug("do_boot_cpu failed %d\n", err);
867 return -EIO;
868 }
869
870 /*
871 * Check TSC synchronization with the AP (keep irqs disabled
872 * while doing so):
873 */
874 local_irq_save(flags);
875 check_tsc_sync_source(cpu);
876 local_irq_restore(flags);
877
878 while (!cpu_online(cpu)) {
879 cpu_relax();
880 touch_nmi_watchdog();
881 }
882
883 return 0;
884}
885
886/**
887 * arch_disable_smp_support() - disables SMP support for x86 at runtime
888 */
889void arch_disable_smp_support(void)
890{
891 disable_ioapic_support();
892}
893
894/*
895 * Fall back to non SMP mode after errors.
896 *
897 * RED-PEN audit/test this more. I bet there is more state messed up here.
898 */
899static __init void disable_smp(void)
900{
901 init_cpu_present(cpumask_of(0));
902 init_cpu_possible(cpumask_of(0));
903 smpboot_clear_io_apic_irqs();
904
905 if (smp_found_config)
906 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
907 else
908 physid_set_mask_of_physid(0, &phys_cpu_present_map);
909 cpumask_set_cpu(0, cpu_sibling_mask(0));
910 cpumask_set_cpu(0, cpu_core_mask(0));
911}
912
913/*
914 * Various sanity checks.
915 */
916static int __init smp_sanity_check(unsigned max_cpus)
917{
918 preempt_disable();
919
920#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
921 if (def_to_bigsmp && nr_cpu_ids > 8) {
922 unsigned int cpu;
923 unsigned nr;
924
925 printk(KERN_WARNING
926 "More than 8 CPUs detected - skipping them.\n"
927 "Use CONFIG_X86_BIGSMP.\n");
928
929 nr = 0;
930 for_each_present_cpu(cpu) {
931 if (nr >= 8)
932 set_cpu_present(cpu, false);
933 nr++;
934 }
935
936 nr = 0;
937 for_each_possible_cpu(cpu) {
938 if (nr >= 8)
939 set_cpu_possible(cpu, false);
940 nr++;
941 }
942
943 nr_cpu_ids = 8;
944 }
945#endif
946
947 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
948 printk(KERN_WARNING
949 "weird, boot CPU (#%d) not listed by the BIOS.\n",
950 hard_smp_processor_id());
951
952 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
953 }
954
955 /*
956 * If we couldn't find an SMP configuration at boot time,
957 * get out of here now!
958 */
959 if (!smp_found_config && !acpi_lapic) {
960 preempt_enable();
961 printk(KERN_NOTICE "SMP motherboard not detected.\n");
962 disable_smp();
963 if (APIC_init_uniprocessor())
964 printk(KERN_NOTICE "Local APIC not detected."
965 " Using dummy APIC emulation.\n");
966 return -1;
967 }
968
969 /*
970 * Should not be necessary because the MP table should list the boot
971 * CPU too, but we do it for the sake of robustness anyway.
972 */
973 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
974 printk(KERN_NOTICE
975 "weird, boot CPU (#%d) not listed by the BIOS.\n",
976 boot_cpu_physical_apicid);
977 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
978 }
979 preempt_enable();
980
981 /*
982 * If we couldn't find a local APIC, then get out of here now!
983 */
984 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
985 !cpu_has_apic) {
986 if (!disable_apic) {
987 pr_err("BIOS bug, local APIC #%d not detected!...\n",
988 boot_cpu_physical_apicid);
989 pr_err("... forcing use of dummy APIC emulation."
990 "(tell your hw vendor)\n");
991 }
992 smpboot_clear_io_apic();
993 disable_ioapic_support();
994 return -1;
995 }
996
997 verify_local_APIC();
998
999 /*
1000 * If SMP should be disabled, then really disable it!
1001 */
1002 if (!max_cpus) {
1003 printk(KERN_INFO "SMP mode deactivated.\n");
1004 smpboot_clear_io_apic();
1005
1006 connect_bsp_APIC();
1007 setup_local_APIC();
1008 bsp_end_local_APIC_setup();
1009 return -1;
1010 }
1011
1012 return 0;
1013}
1014
1015static void __init smp_cpu_index_default(void)
1016{
1017 int i;
1018 struct cpuinfo_x86 *c;
1019
1020 for_each_possible_cpu(i) {
1021 c = &cpu_data(i);
1022 /* mark all to hotplug */
1023 c->cpu_index = nr_cpu_ids;
1024 }
1025}
1026
1027/*
1028 * Prepare for SMP bootup. The MP table or ACPI has been read
1029 * earlier. Just do some sanity checking here and enable APIC mode.
1030 */
1031void __init native_smp_prepare_cpus(unsigned int max_cpus)
1032{
1033 unsigned int i;
1034
1035 preempt_disable();
1036 smp_cpu_index_default();
1037
1038 /*
1039 * Setup boot CPU information
1040 */
1041 smp_store_cpu_info(0); /* Final full version of the data */
1042 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1043 mb();
1044
1045 current_thread_info()->cpu = 0; /* needed? */
1046 for_each_possible_cpu(i) {
1047 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1048 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1049 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1050 }
1051 set_cpu_sibling_map(0);
1052
1053
1054 if (smp_sanity_check(max_cpus) < 0) {
1055 printk(KERN_INFO "SMP disabled\n");
1056 disable_smp();
1057 goto out;
1058 }
1059
1060 default_setup_apic_routing();
1061
1062 preempt_disable();
1063 if (read_apic_id() != boot_cpu_physical_apicid) {
1064 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1065 read_apic_id(), boot_cpu_physical_apicid);
1066 /* Or can we switch back to PIC here? */
1067 }
1068 preempt_enable();
1069
1070 connect_bsp_APIC();
1071
1072 /*
1073 * Switch from PIC to APIC mode.
1074 */
1075 setup_local_APIC();
1076
1077 /*
1078 * Enable IO APIC before setting up error vector
1079 */
1080 if (!skip_ioapic_setup && nr_ioapics)
1081 enable_IO_APIC();
1082
1083 bsp_end_local_APIC_setup();
1084
1085 if (apic->setup_portio_remap)
1086 apic->setup_portio_remap();
1087
1088 smpboot_setup_io_apic();
1089 /*
1090 * Set up local APIC timer on boot CPU.
1091 */
1092
1093 printk(KERN_INFO "CPU%d: ", 0);
1094 print_cpu_info(&cpu_data(0));
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 if (is_uv_system())
1098 uv_system_init();
1099
1100 set_mtrr_aps_delayed_init();
1101out:
1102 preempt_enable();
1103}
1104
1105void arch_disable_nonboot_cpus_begin(void)
1106{
1107 /*
1108 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1109 * In the suspend path, we will be back in the SMP mode shortly anyways.
1110 */
1111 skip_smp_alternatives = true;
1112}
1113
1114void arch_disable_nonboot_cpus_end(void)
1115{
1116 skip_smp_alternatives = false;
1117}
1118
1119void arch_enable_nonboot_cpus_begin(void)
1120{
1121 set_mtrr_aps_delayed_init();
1122}
1123
1124void arch_enable_nonboot_cpus_end(void)
1125{
1126 mtrr_aps_init();
1127}
1128
1129/*
1130 * Early setup to make printk work.
1131 */
1132void __init native_smp_prepare_boot_cpu(void)
1133{
1134 int me = smp_processor_id();
1135 switch_to_new_gdt(me);
1136 /* already set me in cpu_online_mask in boot_cpu_init() */
1137 cpumask_set_cpu(me, cpu_callout_mask);
1138 per_cpu(cpu_state, me) = CPU_ONLINE;
1139}
1140
1141void __init native_smp_cpus_done(unsigned int max_cpus)
1142{
1143 pr_debug("Boot done.\n");
1144
1145 impress_friends();
1146#ifdef CONFIG_X86_IO_APIC
1147 setup_ioapic_dest();
1148#endif
1149 mtrr_aps_init();
1150}
1151
1152static int __initdata setup_possible_cpus = -1;
1153static int __init _setup_possible_cpus(char *str)
1154{
1155 get_option(&str, &setup_possible_cpus);
1156 return 0;
1157}
1158early_param("possible_cpus", _setup_possible_cpus);
1159
1160
1161/*
1162 * cpu_possible_mask should be static, it cannot change as cpu's
1163 * are onlined, or offlined. The reason is per-cpu data-structures
1164 * are allocated by some modules at init time, and dont expect to
1165 * do this dynamically on cpu arrival/departure.
1166 * cpu_present_mask on the other hand can change dynamically.
1167 * In case when cpu_hotplug is not compiled, then we resort to current
1168 * behaviour, which is cpu_possible == cpu_present.
1169 * - Ashok Raj
1170 *
1171 * Three ways to find out the number of additional hotplug CPUs:
1172 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1173 * - The user can overwrite it with possible_cpus=NUM
1174 * - Otherwise don't reserve additional CPUs.
1175 * We do this because additional CPUs waste a lot of memory.
1176 * -AK
1177 */
1178__init void prefill_possible_map(void)
1179{
1180 int i, possible;
1181
1182 /* no processor from mptable or madt */
1183 if (!num_processors)
1184 num_processors = 1;
1185
1186 i = setup_max_cpus ?: 1;
1187 if (setup_possible_cpus == -1) {
1188 possible = num_processors;
1189#ifdef CONFIG_HOTPLUG_CPU
1190 if (setup_max_cpus)
1191 possible += disabled_cpus;
1192#else
1193 if (possible > i)
1194 possible = i;
1195#endif
1196 } else
1197 possible = setup_possible_cpus;
1198
1199 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1200
1201 /* nr_cpu_ids could be reduced via nr_cpus= */
1202 if (possible > nr_cpu_ids) {
1203 printk(KERN_WARNING
1204 "%d Processors exceeds NR_CPUS limit of %d\n",
1205 possible, nr_cpu_ids);
1206 possible = nr_cpu_ids;
1207 }
1208
1209#ifdef CONFIG_HOTPLUG_CPU
1210 if (!setup_max_cpus)
1211#endif
1212 if (possible > i) {
1213 printk(KERN_WARNING
1214 "%d Processors exceeds max_cpus limit of %u\n",
1215 possible, setup_max_cpus);
1216 possible = i;
1217 }
1218
1219 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1220 possible, max_t(int, possible - num_processors, 0));
1221
1222 for (i = 0; i < possible; i++)
1223 set_cpu_possible(i, true);
1224 for (; i < NR_CPUS; i++)
1225 set_cpu_possible(i, false);
1226
1227 nr_cpu_ids = possible;
1228}
1229
1230#ifdef CONFIG_HOTPLUG_CPU
1231
1232static void remove_siblinginfo(int cpu)
1233{
1234 int sibling;
1235 struct cpuinfo_x86 *c = &cpu_data(cpu);
1236
1237 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1238 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1239 /*/
1240 * last thread sibling in this cpu core going down
1241 */
1242 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1243 cpu_data(sibling).booted_cores--;
1244 }
1245
1246 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1247 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1248 cpumask_clear(cpu_sibling_mask(cpu));
1249 cpumask_clear(cpu_core_mask(cpu));
1250 c->phys_proc_id = 0;
1251 c->cpu_core_id = 0;
1252 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1253}
1254
1255static void __ref remove_cpu_from_maps(int cpu)
1256{
1257 set_cpu_online(cpu, false);
1258 cpumask_clear_cpu(cpu, cpu_callout_mask);
1259 cpumask_clear_cpu(cpu, cpu_callin_mask);
1260 /* was set by cpu_init() */
1261 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1262 numa_remove_cpu(cpu);
1263}
1264
1265void cpu_disable_common(void)
1266{
1267 int cpu = smp_processor_id();
1268
1269 remove_siblinginfo(cpu);
1270
1271 /* It's now safe to remove this processor from the online map */
1272 lock_vector_lock();
1273 remove_cpu_from_maps(cpu);
1274 unlock_vector_lock();
1275 fixup_irqs();
1276}
1277
1278int native_cpu_disable(void)
1279{
1280 int cpu = smp_processor_id();
1281
1282 /*
1283 * Perhaps use cpufreq to drop frequency, but that could go
1284 * into generic code.
1285 *
1286 * We won't take down the boot processor on i386 due to some
1287 * interrupts only being able to be serviced by the BSP.
1288 * Especially so if we're not using an IOAPIC -zwane
1289 */
1290 if (cpu == 0)
1291 return -EBUSY;
1292
1293 clear_local_APIC();
1294
1295 cpu_disable_common();
1296 return 0;
1297}
1298
1299void native_cpu_die(unsigned int cpu)
1300{
1301 /* We don't do anything here: idle task is faking death itself. */
1302 unsigned int i;
1303
1304 for (i = 0; i < 10; i++) {
1305 /* They ack this in play_dead by setting CPU_DEAD */
1306 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1307 if (system_state == SYSTEM_RUNNING)
1308 pr_info("CPU %u is now offline\n", cpu);
1309
1310 if (1 == num_online_cpus())
1311 alternatives_smp_switch(0);
1312 return;
1313 }
1314 msleep(100);
1315 }
1316 pr_err("CPU %u didn't die...\n", cpu);
1317}
1318
1319void play_dead_common(void)
1320{
1321 idle_task_exit();
1322 reset_lazy_tlbstate();
1323 amd_e400_remove_cpu(raw_smp_processor_id());
1324
1325 mb();
1326 /* Ack it */
1327 __this_cpu_write(cpu_state, CPU_DEAD);
1328
1329 /*
1330 * With physical CPU hotplug, we should halt the cpu
1331 */
1332 local_irq_disable();
1333}
1334
1335/*
1336 * We need to flush the caches before going to sleep, lest we have
1337 * dirty data in our caches when we come back up.
1338 */
1339static inline void mwait_play_dead(void)
1340{
1341 unsigned int eax, ebx, ecx, edx;
1342 unsigned int highest_cstate = 0;
1343 unsigned int highest_subcstate = 0;
1344 int i;
1345 void *mwait_ptr;
1346 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1347
1348 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1349 return;
1350 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1351 return;
1352 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1353 return;
1354
1355 eax = CPUID_MWAIT_LEAF;
1356 ecx = 0;
1357 native_cpuid(&eax, &ebx, &ecx, &edx);
1358
1359 /*
1360 * eax will be 0 if EDX enumeration is not valid.
1361 * Initialized below to cstate, sub_cstate value when EDX is valid.
1362 */
1363 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1364 eax = 0;
1365 } else {
1366 edx >>= MWAIT_SUBSTATE_SIZE;
1367 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1368 if (edx & MWAIT_SUBSTATE_MASK) {
1369 highest_cstate = i;
1370 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1371 }
1372 }
1373 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1374 (highest_subcstate - 1);
1375 }
1376
1377 /*
1378 * This should be a memory location in a cache line which is
1379 * unlikely to be touched by other processors. The actual
1380 * content is immaterial as it is not actually modified in any way.
1381 */
1382 mwait_ptr = ¤t_thread_info()->flags;
1383
1384 wbinvd();
1385
1386 while (1) {
1387 /*
1388 * The CLFLUSH is a workaround for erratum AAI65 for
1389 * the Xeon 7400 series. It's not clear it is actually
1390 * needed, but it should be harmless in either case.
1391 * The WBINVD is insufficient due to the spurious-wakeup
1392 * case where we return around the loop.
1393 */
1394 clflush(mwait_ptr);
1395 __monitor(mwait_ptr, 0, 0);
1396 mb();
1397 __mwait(eax, 0);
1398 }
1399}
1400
1401static inline void hlt_play_dead(void)
1402{
1403 if (__this_cpu_read(cpu_info.x86) >= 4)
1404 wbinvd();
1405
1406 while (1) {
1407 native_halt();
1408 }
1409}
1410
1411void native_play_dead(void)
1412{
1413 play_dead_common();
1414 tboot_shutdown(TB_SHUTDOWN_WFS);
1415
1416 mwait_play_dead(); /* Only returns on failure */
1417 hlt_play_dead();
1418}
1419
1420#else /* ... !CONFIG_HOTPLUG_CPU */
1421int native_cpu_disable(void)
1422{
1423 return -ENOSYS;
1424}
1425
1426void native_cpu_die(unsigned int cpu)
1427{
1428 /* We said "no" in __cpu_disable */
1429 BUG();
1430}
1431
1432void native_play_dead(void)
1433{
1434 BUG();
1435}
1436
1437#endif