Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56#include <linux/kexec.h>
57#include <linux/numa.h>
58#include <linux/pgtable.h>
59#include <linux/overflow.h>
60#include <linux/stackprotector.h>
61#include <linux/cpuhotplug.h>
62#include <linux/mc146818rtc.h>
63#include <linux/acpi.h>
64
65#include <asm/acpi.h>
66#include <asm/cacheinfo.h>
67#include <asm/desc.h>
68#include <asm/nmi.h>
69#include <asm/irq.h>
70#include <asm/realmode.h>
71#include <asm/cpu.h>
72#include <asm/numa.h>
73#include <asm/tlbflush.h>
74#include <asm/mtrr.h>
75#include <asm/mwait.h>
76#include <asm/apic.h>
77#include <asm/io_apic.h>
78#include <asm/fpu/api.h>
79#include <asm/setup.h>
80#include <asm/uv/uv.h>
81#include <asm/microcode.h>
82#include <asm/i8259.h>
83#include <asm/misc.h>
84#include <asm/qspinlock.h>
85#include <asm/intel-family.h>
86#include <asm/cpu_device_id.h>
87#include <asm/spec-ctrl.h>
88#include <asm/hw_irq.h>
89#include <asm/stackprotector.h>
90#include <asm/sev.h>
91#include <asm/spec-ctrl.h>
92
93/* representing HT siblings of each logical CPU */
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
95EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
96
97/* representing HT and core siblings of each logical CPU */
98DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
99EXPORT_PER_CPU_SYMBOL(cpu_core_map);
100
101/* representing HT, core, and die siblings of each logical CPU */
102DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
103EXPORT_PER_CPU_SYMBOL(cpu_die_map);
104
105/* CPUs which are the primary SMT threads */
106struct cpumask __cpu_primary_thread_mask __read_mostly;
107
108/* Representing CPUs for which sibling maps can be computed */
109static cpumask_var_t cpu_sibling_setup_mask;
110
111struct mwait_cpu_dead {
112 unsigned int control;
113 unsigned int status;
114};
115
116#define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
117#define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
118
119/*
120 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
121 * that it's unlikely to be touched by other CPUs.
122 */
123static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
124
125/* Maximum number of SMT threads on any online core */
126int __read_mostly __max_smt_threads = 1;
127
128/* Flag to indicate if a complete sched domain rebuild is required */
129bool x86_topology_update;
130
131int arch_update_cpu_topology(void)
132{
133 int retval = x86_topology_update;
134
135 x86_topology_update = false;
136 return retval;
137}
138
139static unsigned int smpboot_warm_reset_vector_count;
140
141static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
142{
143 unsigned long flags;
144
145 spin_lock_irqsave(&rtc_lock, flags);
146 if (!smpboot_warm_reset_vector_count++) {
147 CMOS_WRITE(0xa, 0xf);
148 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
150 }
151 spin_unlock_irqrestore(&rtc_lock, flags);
152}
153
154static inline void smpboot_restore_warm_reset_vector(void)
155{
156 unsigned long flags;
157
158 /*
159 * Paranoid: Set warm reset code and vector here back
160 * to default values.
161 */
162 spin_lock_irqsave(&rtc_lock, flags);
163 if (!--smpboot_warm_reset_vector_count) {
164 CMOS_WRITE(0, 0xf);
165 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
166 }
167 spin_unlock_irqrestore(&rtc_lock, flags);
168
169}
170
171/* Run the next set of setup steps for the upcoming CPU */
172static void ap_starting(void)
173{
174 int cpuid = smp_processor_id();
175
176 /* Mop up eventual mwait_play_dead() wreckage */
177 this_cpu_write(mwait_cpu_dead.status, 0);
178 this_cpu_write(mwait_cpu_dead.control, 0);
179
180 /*
181 * If woken up by an INIT in an 82489DX configuration the alive
182 * synchronization guarantees that the CPU does not reach this
183 * point before an INIT_deassert IPI reaches the local APIC, so it
184 * is now safe to touch the local APIC.
185 *
186 * Set up this CPU, first the APIC, which is probably redundant on
187 * most boards.
188 */
189 apic_ap_setup();
190
191 /* Save the processor parameters. */
192 smp_store_cpu_info(cpuid);
193
194 /*
195 * The topology information must be up to date before
196 * notify_cpu_starting().
197 */
198 set_cpu_sibling_map(cpuid);
199
200 ap_init_aperfmperf();
201
202 pr_debug("Stack at about %p\n", &cpuid);
203
204 wmb();
205
206 /*
207 * This runs the AP through all the cpuhp states to its target
208 * state CPUHP_ONLINE.
209 */
210 notify_cpu_starting(cpuid);
211}
212
213static void ap_calibrate_delay(void)
214{
215 /*
216 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
217 * smp_store_cpu_info() stored a value that is close but not as
218 * accurate as the value just calculated.
219 *
220 * As this is invoked after the TSC synchronization check,
221 * calibrate_delay_is_known() will skip the calibration routine
222 * when TSC is synchronized across sockets.
223 */
224 calibrate_delay();
225 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
226}
227
228/*
229 * Activate a secondary processor.
230 */
231static void notrace start_secondary(void *unused)
232{
233 /*
234 * Don't put *anything* except direct CPU state initialization
235 * before cpu_init(), SMP booting is too fragile that we want to
236 * limit the things done here to the most necessary things.
237 */
238 cr4_init();
239
240 /*
241 * 32-bit specific. 64-bit reaches this code with the correct page
242 * table established. Yet another historical divergence.
243 */
244 if (IS_ENABLED(CONFIG_X86_32)) {
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir);
247 __flush_tlb_all();
248 }
249
250 cpu_init_exception_handling(false);
251
252 /*
253 * Load the microcode before reaching the AP alive synchronization
254 * point below so it is not part of the full per CPU serialized
255 * bringup part when "parallel" bringup is enabled.
256 *
257 * That's even safe when hyperthreading is enabled in the CPU as
258 * the core code starts the primary threads first and leaves the
259 * secondary threads waiting for SIPI. Loading microcode on
260 * physical cores concurrently is a safe operation.
261 *
262 * This covers both the Intel specific issue that concurrent
263 * microcode loading on SMT siblings must be prohibited and the
264 * vendor independent issue`that microcode loading which changes
265 * CPUID, MSRs etc. must be strictly serialized to maintain
266 * software state correctness.
267 */
268 load_ucode_ap();
269
270 /*
271 * Synchronization point with the hotplug core. Sets this CPUs
272 * synchronization state to ALIVE and spin-waits for the control CPU to
273 * release this CPU for further bringup.
274 */
275 cpuhp_ap_sync_alive();
276
277 cpu_init();
278 fpu__init_cpu();
279 rcutree_report_cpu_starting(raw_smp_processor_id());
280 x86_cpuinit.early_percpu_clock_init();
281
282 ap_starting();
283
284 /* Check TSC synchronization with the control CPU. */
285 check_tsc_sync_target();
286
287 /*
288 * Calibrate the delay loop after the TSC synchronization check.
289 * This allows to skip the calibration when TSC is synchronized
290 * across sockets.
291 */
292 ap_calibrate_delay();
293
294 speculative_store_bypass_ht_init();
295
296 /*
297 * Lock vector_lock, set CPU online and bring the vector
298 * allocator online. Online must be set with vector_lock held
299 * to prevent a concurrent irq setup/teardown from seeing a
300 * half valid vector space.
301 */
302 lock_vector_lock();
303 set_cpu_online(smp_processor_id(), true);
304 lapic_online();
305 unlock_vector_lock();
306 x86_platform.nmi_init();
307
308 /* enable local interrupts */
309 local_irq_enable();
310
311 x86_cpuinit.setup_percpu_clockev();
312
313 wmb();
314 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
315}
316
317/*
318 * The bootstrap kernel entry code has set these up. Save them for
319 * a given CPU
320 */
321void smp_store_cpu_info(int id)
322{
323 struct cpuinfo_x86 *c = &cpu_data(id);
324
325 /* Copy boot_cpu_data only on the first bringup */
326 if (!c->initialized)
327 *c = boot_cpu_data;
328 c->cpu_index = id;
329 /*
330 * During boot time, CPU0 has this setup already. Save the info when
331 * bringing up an AP.
332 */
333 identify_secondary_cpu(c);
334 c->initialized = true;
335}
336
337static bool
338topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
339{
340 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
341
342 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
343}
344
345static bool
346topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
347{
348 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
349
350 return !WARN_ONCE(!topology_same_node(c, o),
351 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
352 "[node: %d != %d]. Ignoring dependency.\n",
353 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
354}
355
356#define link_mask(mfunc, c1, c2) \
357do { \
358 cpumask_set_cpu((c1), mfunc(c2)); \
359 cpumask_set_cpu((c2), mfunc(c1)); \
360} while (0)
361
362static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
363{
364 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
365 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
366
367 if (c->topo.pkg_id == o->topo.pkg_id &&
368 c->topo.die_id == o->topo.die_id &&
369 c->topo.amd_node_id == o->topo.amd_node_id &&
370 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) {
371 if (c->topo.core_id == o->topo.core_id)
372 return topology_sane(c, o, "smt");
373
374 if ((c->topo.cu_id != 0xff) &&
375 (o->topo.cu_id != 0xff) &&
376 (c->topo.cu_id == o->topo.cu_id))
377 return topology_sane(c, o, "smt");
378 }
379
380 } else if (c->topo.pkg_id == o->topo.pkg_id &&
381 c->topo.die_id == o->topo.die_id &&
382 c->topo.core_id == o->topo.core_id) {
383 return topology_sane(c, o, "smt");
384 }
385
386 return false;
387}
388
389static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
390{
391 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id)
392 return false;
393
394 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1)
395 return c->topo.amd_node_id == o->topo.amd_node_id;
396
397 return true;
398}
399
400static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
401{
402 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
403
404 /* If the arch didn't set up l2c_id, fall back to SMT */
405 if (per_cpu_l2c_id(cpu1) == BAD_APICID)
406 return match_smt(c, o);
407
408 /* Do not match if L2 cache id does not match: */
409 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2))
410 return false;
411
412 return topology_sane(c, o, "l2c");
413}
414
415/*
416 * Unlike the other levels, we do not enforce keeping a
417 * multicore group inside a NUMA node. If this happens, we will
418 * discard the MC level of the topology later.
419 */
420static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
421{
422 if (c->topo.pkg_id == o->topo.pkg_id)
423 return true;
424 return false;
425}
426
427/*
428 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
429 *
430 * Any Intel CPU that has multiple nodes per package and does not
431 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
432 *
433 * When in SNC mode, these CPUs enumerate an LLC that is shared
434 * by multiple NUMA nodes. The LLC is shared for off-package data
435 * access but private to the NUMA node (half of the package) for
436 * on-package access. CPUID (the source of the information about
437 * the LLC) can only enumerate the cache as shared or unshared,
438 * but not this particular configuration.
439 */
440
441static const struct x86_cpu_id intel_cod_cpu[] = {
442 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */
443 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */
444 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */
445 {}
446};
447
448static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
449{
450 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
451 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
452 bool intel_snc = id && id->driver_data;
453
454 /* Do not match if we do not have a valid APICID for cpu: */
455 if (per_cpu_llc_id(cpu1) == BAD_APICID)
456 return false;
457
458 /* Do not match if LLC id does not match: */
459 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2))
460 return false;
461
462 /*
463 * Allow the SNC topology without warning. Return of false
464 * means 'c' does not share the LLC of 'o'. This will be
465 * reflected to userspace.
466 */
467 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
468 return false;
469
470 return topology_sane(c, o, "llc");
471}
472
473
474static inline int x86_sched_itmt_flags(void)
475{
476 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
477}
478
479#ifdef CONFIG_SCHED_MC
480static int x86_core_flags(void)
481{
482 return cpu_core_flags() | x86_sched_itmt_flags();
483}
484#endif
485#ifdef CONFIG_SCHED_SMT
486static int x86_smt_flags(void)
487{
488 return cpu_smt_flags();
489}
490#endif
491#ifdef CONFIG_SCHED_CLUSTER
492static int x86_cluster_flags(void)
493{
494 return cpu_cluster_flags() | x86_sched_itmt_flags();
495}
496#endif
497
498/*
499 * Set if a package/die has multiple NUMA nodes inside.
500 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
501 * Sub-NUMA Clustering have this.
502 */
503static bool x86_has_numa_in_package;
504
505static struct sched_domain_topology_level x86_topology[6];
506
507static void __init build_sched_topology(void)
508{
509 int i = 0;
510
511#ifdef CONFIG_SCHED_SMT
512 x86_topology[i++] = (struct sched_domain_topology_level){
513 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
514 };
515#endif
516#ifdef CONFIG_SCHED_CLUSTER
517 x86_topology[i++] = (struct sched_domain_topology_level){
518 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
519 };
520#endif
521#ifdef CONFIG_SCHED_MC
522 x86_topology[i++] = (struct sched_domain_topology_level){
523 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
524 };
525#endif
526 /*
527 * When there is NUMA topology inside the package skip the PKG domain
528 * since the NUMA domains will auto-magically create the right spanning
529 * domains based on the SLIT.
530 */
531 if (!x86_has_numa_in_package) {
532 x86_topology[i++] = (struct sched_domain_topology_level){
533 cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG)
534 };
535 }
536
537 /*
538 * There must be one trailing NULL entry left.
539 */
540 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
541
542 set_sched_topology(x86_topology);
543}
544
545void set_cpu_sibling_map(int cpu)
546{
547 bool has_smt = __max_threads_per_core > 1;
548 bool has_mp = has_smt || topology_num_cores_per_package() > 1;
549 struct cpuinfo_x86 *c = &cpu_data(cpu);
550 struct cpuinfo_x86 *o;
551 int i, threads;
552
553 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
554
555 if (!has_mp) {
556 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
557 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
558 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
559 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
560 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
561 c->booted_cores = 1;
562 return;
563 }
564
565 for_each_cpu(i, cpu_sibling_setup_mask) {
566 o = &cpu_data(i);
567
568 if (match_pkg(c, o) && !topology_same_node(c, o))
569 x86_has_numa_in_package = true;
570
571 if ((i == cpu) || (has_smt && match_smt(c, o)))
572 link_mask(topology_sibling_cpumask, cpu, i);
573
574 if ((i == cpu) || (has_mp && match_llc(c, o)))
575 link_mask(cpu_llc_shared_mask, cpu, i);
576
577 if ((i == cpu) || (has_mp && match_l2c(c, o)))
578 link_mask(cpu_l2c_shared_mask, cpu, i);
579
580 if ((i == cpu) || (has_mp && match_die(c, o)))
581 link_mask(topology_die_cpumask, cpu, i);
582 }
583
584 threads = cpumask_weight(topology_sibling_cpumask(cpu));
585 if (threads > __max_smt_threads)
586 __max_smt_threads = threads;
587
588 for_each_cpu(i, topology_sibling_cpumask(cpu))
589 cpu_data(i).smt_active = threads > 1;
590
591 /*
592 * This needs a separate iteration over the cpus because we rely on all
593 * topology_sibling_cpumask links to be set-up.
594 */
595 for_each_cpu(i, cpu_sibling_setup_mask) {
596 o = &cpu_data(i);
597
598 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
599 link_mask(topology_core_cpumask, cpu, i);
600
601 /*
602 * Does this new cpu bringup a new core?
603 */
604 if (threads == 1) {
605 /*
606 * for each core in package, increment
607 * the booted_cores for this new cpu
608 */
609 if (cpumask_first(
610 topology_sibling_cpumask(i)) == i)
611 c->booted_cores++;
612 /*
613 * increment the core count for all
614 * the other cpus in this package
615 */
616 if (i != cpu)
617 cpu_data(i).booted_cores++;
618 } else if (i != cpu && !c->booted_cores)
619 c->booted_cores = cpu_data(i).booted_cores;
620 }
621 }
622}
623
624/* maps the cpu to the sched domain representing multi-core */
625const struct cpumask *cpu_coregroup_mask(int cpu)
626{
627 return cpu_llc_shared_mask(cpu);
628}
629
630const struct cpumask *cpu_clustergroup_mask(int cpu)
631{
632 return cpu_l2c_shared_mask(cpu);
633}
634EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
635
636static void impress_friends(void)
637{
638 int cpu;
639 unsigned long bogosum = 0;
640 /*
641 * Allow the user to impress friends.
642 */
643 pr_debug("Before bogomips\n");
644 for_each_online_cpu(cpu)
645 bogosum += cpu_data(cpu).loops_per_jiffy;
646
647 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
648 num_online_cpus(),
649 bogosum/(500000/HZ),
650 (bogosum/(5000/HZ))%100);
651
652 pr_debug("Before bogocount - setting activated=1\n");
653}
654
655/*
656 * The Multiprocessor Specification 1.4 (1997) example code suggests
657 * that there should be a 10ms delay between the BSP asserting INIT
658 * and de-asserting INIT, when starting a remote processor.
659 * But that slows boot and resume on modern processors, which include
660 * many cores and don't require that delay.
661 *
662 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
663 * Modern processor families are quirked to remove the delay entirely.
664 */
665#define UDELAY_10MS_DEFAULT 10000
666
667static unsigned int init_udelay = UINT_MAX;
668
669static int __init cpu_init_udelay(char *str)
670{
671 get_option(&str, &init_udelay);
672
673 return 0;
674}
675early_param("cpu_init_udelay", cpu_init_udelay);
676
677static void __init smp_quirk_init_udelay(void)
678{
679 /* if cmdline changed it from default, leave it alone */
680 if (init_udelay != UINT_MAX)
681 return;
682
683 /* if modern processor, use no delay */
684 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
685 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
686 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
687 init_udelay = 0;
688 return;
689 }
690 /* else, use legacy delay */
691 init_udelay = UDELAY_10MS_DEFAULT;
692}
693
694/*
695 * Wake up AP by INIT, INIT, STARTUP sequence.
696 */
697static void send_init_sequence(u32 phys_apicid)
698{
699 int maxlvt = lapic_get_maxlvt();
700
701 /* Be paranoid about clearing APIC errors. */
702 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
703 /* Due to the Pentium erratum 3AP. */
704 if (maxlvt > 3)
705 apic_write(APIC_ESR, 0);
706 apic_read(APIC_ESR);
707 }
708
709 /* Assert INIT on the target CPU */
710 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
711 safe_apic_wait_icr_idle();
712
713 udelay(init_udelay);
714
715 /* Deassert INIT on the target CPU */
716 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
717 safe_apic_wait_icr_idle();
718}
719
720/*
721 * Wake up AP by INIT, INIT, STARTUP sequence.
722 */
723static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip)
724{
725 unsigned long send_status = 0, accept_status = 0;
726 int num_starts, j, maxlvt;
727
728 preempt_disable();
729 maxlvt = lapic_get_maxlvt();
730 send_init_sequence(phys_apicid);
731
732 mb();
733
734 /*
735 * Should we send STARTUP IPIs ?
736 *
737 * Determine this based on the APIC version.
738 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
739 */
740 if (APIC_INTEGRATED(boot_cpu_apic_version))
741 num_starts = 2;
742 else
743 num_starts = 0;
744
745 /*
746 * Run STARTUP IPI loop.
747 */
748 pr_debug("#startup loops: %d\n", num_starts);
749
750 for (j = 1; j <= num_starts; j++) {
751 pr_debug("Sending STARTUP #%d\n", j);
752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
753 apic_write(APIC_ESR, 0);
754 apic_read(APIC_ESR);
755 pr_debug("After apic_write\n");
756
757 /*
758 * STARTUP IPI
759 */
760
761 /* Target chip */
762 /* Boot on the stack */
763 /* Kick the second */
764 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
765 phys_apicid);
766
767 /*
768 * Give the other CPU some time to accept the IPI.
769 */
770 if (init_udelay == 0)
771 udelay(10);
772 else
773 udelay(300);
774
775 pr_debug("Startup point 1\n");
776
777 pr_debug("Waiting for send to finish...\n");
778 send_status = safe_apic_wait_icr_idle();
779
780 /*
781 * Give the other CPU some time to accept the IPI.
782 */
783 if (init_udelay == 0)
784 udelay(10);
785 else
786 udelay(200);
787
788 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
789 apic_write(APIC_ESR, 0);
790 accept_status = (apic_read(APIC_ESR) & 0xEF);
791 if (send_status || accept_status)
792 break;
793 }
794 pr_debug("After Startup\n");
795
796 if (send_status)
797 pr_err("APIC never delivered???\n");
798 if (accept_status)
799 pr_err("APIC delivery error (%lx)\n", accept_status);
800
801 preempt_enable();
802 return (send_status | accept_status);
803}
804
805/* reduce the number of lines printed when booting a large cpu count system */
806static void announce_cpu(int cpu, int apicid)
807{
808 static int width, node_width, first = 1;
809 static int current_node = NUMA_NO_NODE;
810 int node = early_cpu_to_node(cpu);
811
812 if (!width)
813 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
814
815 if (!node_width)
816 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
817
818 if (system_state < SYSTEM_RUNNING) {
819 if (first)
820 pr_info("x86: Booting SMP configuration:\n");
821
822 if (node != current_node) {
823 if (current_node > (-1))
824 pr_cont("\n");
825 current_node = node;
826
827 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
828 node_width - num_digits(node), " ", node);
829 }
830
831 /* Add padding for the BSP */
832 if (first)
833 pr_cont("%*s", width + 1, " ");
834 first = 0;
835
836 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
837 } else
838 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
839 node, cpu, apicid);
840}
841
842int common_cpu_up(unsigned int cpu, struct task_struct *idle)
843{
844 int ret;
845
846 /* Just in case we booted with a single CPU. */
847 alternatives_enable_smp();
848
849 per_cpu(pcpu_hot.current_task, cpu) = idle;
850 cpu_init_stack_canary(cpu, idle);
851
852 /* Initialize the interrupt stack(s) */
853 ret = irq_init_percpu_irqstack(cpu);
854 if (ret)
855 return ret;
856
857#ifdef CONFIG_X86_32
858 /* Stack for startup_32 can be just as for start_secondary onwards */
859 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
860#endif
861 return 0;
862}
863
864/*
865 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
866 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
867 * Returns zero if startup was successfully sent, else error code from
868 * ->wakeup_secondary_cpu.
869 */
870static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle)
871{
872 unsigned long start_ip = real_mode_header->trampoline_start;
873 int ret;
874
875#ifdef CONFIG_X86_64
876 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
877 if (apic->wakeup_secondary_cpu_64)
878 start_ip = real_mode_header->trampoline_start64;
879#endif
880 idle->thread.sp = (unsigned long)task_pt_regs(idle);
881 initial_code = (unsigned long)start_secondary;
882
883 if (IS_ENABLED(CONFIG_X86_32)) {
884 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
885 initial_stack = idle->thread.sp;
886 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
887 smpboot_control = cpu;
888 }
889
890 /* Enable the espfix hack for this CPU */
891 init_espfix_ap(cpu);
892
893 /* So we see what's up */
894 announce_cpu(cpu, apicid);
895
896 /*
897 * This grunge runs the startup process for
898 * the targeted processor.
899 */
900 if (x86_platform.legacy.warm_reset) {
901
902 pr_debug("Setting warm reset code and vector.\n");
903
904 smpboot_setup_warm_reset_vector(start_ip);
905 /*
906 * Be paranoid about clearing APIC errors.
907 */
908 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
909 apic_write(APIC_ESR, 0);
910 apic_read(APIC_ESR);
911 }
912 }
913
914 smp_mb();
915
916 /*
917 * Wake up a CPU in difference cases:
918 * - Use a method from the APIC driver if one defined, with wakeup
919 * straight to 64-bit mode preferred over wakeup to RM.
920 * Otherwise,
921 * - Use an INIT boot APIC message
922 */
923 if (apic->wakeup_secondary_cpu_64)
924 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
925 else if (apic->wakeup_secondary_cpu)
926 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
927 else
928 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
929
930 /* If the wakeup mechanism failed, cleanup the warm reset vector */
931 if (ret)
932 arch_cpuhp_cleanup_kick_cpu(cpu);
933 return ret;
934}
935
936int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
937{
938 u32 apicid = apic->cpu_present_to_apicid(cpu);
939 int err;
940
941 lockdep_assert_irqs_enabled();
942
943 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
944
945 if (apicid == BAD_APICID || !apic_id_valid(apicid)) {
946 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid);
947 return -EINVAL;
948 }
949
950 if (!test_bit(apicid, phys_cpu_present_map)) {
951 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid);
952 return -EINVAL;
953 }
954
955 /*
956 * Save current MTRR state in case it was changed since early boot
957 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
958 */
959 mtrr_save_state();
960
961 /* the FPU context is blank, nobody can own it */
962 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
963
964 err = common_cpu_up(cpu, tidle);
965 if (err)
966 return err;
967
968 err = do_boot_cpu(apicid, cpu, tidle);
969 if (err)
970 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
971
972 return err;
973}
974
975int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
976{
977 return smp_ops.kick_ap_alive(cpu, tidle);
978}
979
980void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
981{
982 /* Cleanup possible dangling ends... */
983 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
984 smpboot_restore_warm_reset_vector();
985}
986
987void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
988{
989 if (smp_ops.cleanup_dead_cpu)
990 smp_ops.cleanup_dead_cpu(cpu);
991
992 if (system_state == SYSTEM_RUNNING)
993 pr_info("CPU %u is now offline\n", cpu);
994}
995
996void arch_cpuhp_sync_state_poll(void)
997{
998 if (smp_ops.poll_sync_state)
999 smp_ops.poll_sync_state();
1000}
1001
1002/**
1003 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1004 */
1005void __init arch_disable_smp_support(void)
1006{
1007 disable_ioapic_support();
1008}
1009
1010/*
1011 * Fall back to non SMP mode after errors.
1012 *
1013 * RED-PEN audit/test this more. I bet there is more state messed up here.
1014 */
1015static __init void disable_smp(void)
1016{
1017 pr_info("SMP disabled\n");
1018
1019 disable_ioapic_support();
1020 topology_reset_possible_cpus_up();
1021
1022 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1023 cpumask_set_cpu(0, topology_core_cpumask(0));
1024 cpumask_set_cpu(0, topology_die_cpumask(0));
1025}
1026
1027void __init smp_prepare_cpus_common(void)
1028{
1029 unsigned int cpu, node;
1030
1031 /* Mark all except the boot CPU as hotpluggable */
1032 for_each_possible_cpu(cpu) {
1033 if (cpu)
1034 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids;
1035 }
1036
1037 for_each_possible_cpu(cpu) {
1038 node = cpu_to_node(cpu);
1039
1040 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node);
1041 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node);
1042 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node);
1043 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node);
1044 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node);
1045 }
1046
1047 set_cpu_sibling_map(0);
1048}
1049
1050void __init smp_prepare_boot_cpu(void)
1051{
1052 smp_ops.smp_prepare_boot_cpu();
1053}
1054
1055#ifdef CONFIG_X86_64
1056/* Establish whether parallel bringup can be supported. */
1057bool __init arch_cpuhp_init_parallel_bringup(void)
1058{
1059 if (!x86_cpuinit.parallel_bringup) {
1060 pr_info("Parallel CPU startup disabled by the platform\n");
1061 return false;
1062 }
1063
1064 smpboot_control = STARTUP_READ_APICID;
1065 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1066 return true;
1067}
1068#endif
1069
1070/*
1071 * Prepare for SMP bootup.
1072 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1073 * for common interface support.
1074 */
1075void __init native_smp_prepare_cpus(unsigned int max_cpus)
1076{
1077 smp_prepare_cpus_common();
1078
1079 switch (apic_intr_mode) {
1080 case APIC_PIC:
1081 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1082 disable_smp();
1083 return;
1084 case APIC_SYMMETRIC_IO_NO_ROUTING:
1085 disable_smp();
1086 /* Setup local timer */
1087 x86_init.timers.setup_percpu_clockev();
1088 return;
1089 case APIC_VIRTUAL_WIRE:
1090 case APIC_SYMMETRIC_IO:
1091 break;
1092 }
1093
1094 /* Setup local timer */
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 pr_info("CPU0: ");
1098 print_cpu_info(&cpu_data(0));
1099
1100 uv_system_init();
1101
1102 smp_quirk_init_udelay();
1103
1104 speculative_store_bypass_ht_init();
1105
1106 snp_set_wakeup_secondary_cpu();
1107}
1108
1109void arch_thaw_secondary_cpus_begin(void)
1110{
1111 set_cache_aps_delayed_init(true);
1112}
1113
1114void arch_thaw_secondary_cpus_end(void)
1115{
1116 cache_aps_init();
1117}
1118
1119/*
1120 * Early setup to make printk work.
1121 */
1122void __init native_smp_prepare_boot_cpu(void)
1123{
1124 int me = smp_processor_id();
1125
1126 /* SMP handles this from setup_per_cpu_areas() */
1127 if (!IS_ENABLED(CONFIG_SMP))
1128 switch_gdt_and_percpu_base(me);
1129
1130 native_pv_lock_init();
1131}
1132
1133void __init native_smp_cpus_done(unsigned int max_cpus)
1134{
1135 pr_debug("Boot done\n");
1136
1137 build_sched_topology();
1138 nmi_selftest();
1139 impress_friends();
1140 cache_aps_init();
1141}
1142
1143/* correctly size the local cpu masks */
1144void __init setup_cpu_local_masks(void)
1145{
1146 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1147}
1148
1149#ifdef CONFIG_HOTPLUG_CPU
1150
1151/* Recompute SMT state for all CPUs on offline */
1152static void recompute_smt_state(void)
1153{
1154 int max_threads, cpu;
1155
1156 max_threads = 0;
1157 for_each_online_cpu (cpu) {
1158 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1159
1160 if (threads > max_threads)
1161 max_threads = threads;
1162 }
1163 __max_smt_threads = max_threads;
1164}
1165
1166static void remove_siblinginfo(int cpu)
1167{
1168 int sibling;
1169 struct cpuinfo_x86 *c = &cpu_data(cpu);
1170
1171 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1172 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1173 /*/
1174 * last thread sibling in this cpu core going down
1175 */
1176 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1177 cpu_data(sibling).booted_cores--;
1178 }
1179
1180 for_each_cpu(sibling, topology_die_cpumask(cpu))
1181 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1182
1183 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1184 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1185 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1186 cpu_data(sibling).smt_active = false;
1187 }
1188
1189 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1190 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1191 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1192 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1193 cpumask_clear(cpu_llc_shared_mask(cpu));
1194 cpumask_clear(cpu_l2c_shared_mask(cpu));
1195 cpumask_clear(topology_sibling_cpumask(cpu));
1196 cpumask_clear(topology_core_cpumask(cpu));
1197 cpumask_clear(topology_die_cpumask(cpu));
1198 c->topo.core_id = 0;
1199 c->booted_cores = 0;
1200 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1201 recompute_smt_state();
1202}
1203
1204static void remove_cpu_from_maps(int cpu)
1205{
1206 set_cpu_online(cpu, false);
1207 numa_remove_cpu(cpu);
1208}
1209
1210void cpu_disable_common(void)
1211{
1212 int cpu = smp_processor_id();
1213
1214 remove_siblinginfo(cpu);
1215
1216 /* It's now safe to remove this processor from the online map */
1217 lock_vector_lock();
1218 remove_cpu_from_maps(cpu);
1219 unlock_vector_lock();
1220 fixup_irqs();
1221 lapic_offline();
1222}
1223
1224int native_cpu_disable(void)
1225{
1226 int ret;
1227
1228 ret = lapic_can_unplug_cpu();
1229 if (ret)
1230 return ret;
1231
1232 cpu_disable_common();
1233
1234 /*
1235 * Disable the local APIC. Otherwise IPI broadcasts will reach
1236 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1237 * messages.
1238 *
1239 * Disabling the APIC must happen after cpu_disable_common()
1240 * which invokes fixup_irqs().
1241 *
1242 * Disabling the APIC preserves already set bits in IRR, but
1243 * an interrupt arriving after disabling the local APIC does not
1244 * set the corresponding IRR bit.
1245 *
1246 * fixup_irqs() scans IRR for set bits so it can raise a not
1247 * yet handled interrupt on the new destination CPU via an IPI
1248 * but obviously it can't do so for IRR bits which are not set.
1249 * IOW, interrupts arriving after disabling the local APIC will
1250 * be lost.
1251 */
1252 apic_soft_disable();
1253
1254 return 0;
1255}
1256
1257void play_dead_common(void)
1258{
1259 idle_task_exit();
1260
1261 cpuhp_ap_report_dead();
1262
1263 local_irq_disable();
1264}
1265
1266/*
1267 * We need to flush the caches before going to sleep, lest we have
1268 * dirty data in our caches when we come back up.
1269 */
1270static inline void mwait_play_dead(void)
1271{
1272 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1273 unsigned int eax, ebx, ecx, edx;
1274 unsigned int highest_cstate = 0;
1275 unsigned int highest_subcstate = 0;
1276 int i;
1277
1278 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1279 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1280 return;
1281 if (!this_cpu_has(X86_FEATURE_MWAIT))
1282 return;
1283 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1284 return;
1285 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1286 return;
1287
1288 eax = CPUID_MWAIT_LEAF;
1289 ecx = 0;
1290 native_cpuid(&eax, &ebx, &ecx, &edx);
1291
1292 /*
1293 * eax will be 0 if EDX enumeration is not valid.
1294 * Initialized below to cstate, sub_cstate value when EDX is valid.
1295 */
1296 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1297 eax = 0;
1298 } else {
1299 edx >>= MWAIT_SUBSTATE_SIZE;
1300 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1301 if (edx & MWAIT_SUBSTATE_MASK) {
1302 highest_cstate = i;
1303 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1304 }
1305 }
1306 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1307 (highest_subcstate - 1);
1308 }
1309
1310 /* Set up state for the kexec() hack below */
1311 md->status = CPUDEAD_MWAIT_WAIT;
1312 md->control = CPUDEAD_MWAIT_WAIT;
1313
1314 wbinvd();
1315
1316 while (1) {
1317 /*
1318 * The CLFLUSH is a workaround for erratum AAI65 for
1319 * the Xeon 7400 series. It's not clear it is actually
1320 * needed, but it should be harmless in either case.
1321 * The WBINVD is insufficient due to the spurious-wakeup
1322 * case where we return around the loop.
1323 */
1324 mb();
1325 clflush(md);
1326 mb();
1327 __monitor(md, 0, 0);
1328 mb();
1329 __mwait(eax, 0);
1330
1331 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1332 /*
1333 * Kexec is about to happen. Don't go back into mwait() as
1334 * the kexec kernel might overwrite text and data including
1335 * page tables and stack. So mwait() would resume when the
1336 * monitor cache line is written to and then the CPU goes
1337 * south due to overwritten text, page tables and stack.
1338 *
1339 * Note: This does _NOT_ protect against a stray MCE, NMI,
1340 * SMI. They will resume execution at the instruction
1341 * following the HLT instruction and run into the problem
1342 * which this is trying to prevent.
1343 */
1344 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1345 while(1)
1346 native_halt();
1347 }
1348 }
1349}
1350
1351/*
1352 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1353 * mwait_play_dead().
1354 */
1355void smp_kick_mwait_play_dead(void)
1356{
1357 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1358 struct mwait_cpu_dead *md;
1359 unsigned int cpu, i;
1360
1361 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1362 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1363
1364 /* Does it sit in mwait_play_dead() ? */
1365 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1366 continue;
1367
1368 /* Wait up to 5ms */
1369 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1370 /* Bring it out of mwait */
1371 WRITE_ONCE(md->control, newstate);
1372 udelay(5);
1373 }
1374
1375 if (READ_ONCE(md->status) != newstate)
1376 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1377 }
1378}
1379
1380void __noreturn hlt_play_dead(void)
1381{
1382 if (__this_cpu_read(cpu_info.x86) >= 4)
1383 wbinvd();
1384
1385 while (1)
1386 native_halt();
1387}
1388
1389/*
1390 * native_play_dead() is essentially a __noreturn function, but it can't
1391 * be marked as such as the compiler may complain about it.
1392 */
1393void native_play_dead(void)
1394{
1395 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1396 __update_spec_ctrl(0);
1397
1398 play_dead_common();
1399 tboot_shutdown(TB_SHUTDOWN_WFS);
1400
1401 mwait_play_dead();
1402 if (cpuidle_play_dead())
1403 hlt_play_dead();
1404}
1405
1406#else /* ... !CONFIG_HOTPLUG_CPU */
1407int native_cpu_disable(void)
1408{
1409 return -ENOSYS;
1410}
1411
1412void native_play_dead(void)
1413{
1414 BUG();
1415}
1416
1417#endif
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/module.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/idle.h>
62#include <asm/realmode.h>
63#include <asm/cpu.h>
64#include <asm/numa.h>
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
68#include <asm/mwait.h>
69#include <asm/apic.h>
70#include <asm/io_apic.h>
71#include <asm/fpu/internal.h>
72#include <asm/setup.h>
73#include <asm/uv/uv.h>
74#include <linux/mc146818rtc.h>
75#include <asm/i8259.h>
76#include <asm/realmode.h>
77#include <asm/misc.h>
78
79/* Number of siblings per CPU package */
80int smp_num_siblings = 1;
81EXPORT_SYMBOL(smp_num_siblings);
82
83/* Last level cache ID of each logical CPU */
84DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
85
86/* representing HT siblings of each logical CPU */
87DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89
90/* representing HT and core siblings of each logical CPU */
91DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95
96/* Per CPU bogomips and other parameters */
97DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
98EXPORT_PER_CPU_SYMBOL(cpu_info);
99
100/* Logical package management. We might want to allocate that dynamically */
101static int *physical_to_logical_pkg __read_mostly;
102static unsigned long *physical_package_map __read_mostly;;
103static unsigned long *logical_package_map __read_mostly;
104static unsigned int max_physical_pkg_id __read_mostly;
105unsigned int __max_logical_packages __read_mostly;
106EXPORT_SYMBOL(__max_logical_packages);
107
108static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
109{
110 unsigned long flags;
111
112 spin_lock_irqsave(&rtc_lock, flags);
113 CMOS_WRITE(0xa, 0xf);
114 spin_unlock_irqrestore(&rtc_lock, flags);
115 local_flush_tlb();
116 pr_debug("1.\n");
117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
118 start_eip >> 4;
119 pr_debug("2.\n");
120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
121 start_eip & 0xf;
122 pr_debug("3.\n");
123}
124
125static inline void smpboot_restore_warm_reset_vector(void)
126{
127 unsigned long flags;
128
129 /*
130 * Install writable page 0 entry to set BIOS data area.
131 */
132 local_flush_tlb();
133
134 /*
135 * Paranoid: Set warm reset code and vector here back
136 * to default values.
137 */
138 spin_lock_irqsave(&rtc_lock, flags);
139 CMOS_WRITE(0, 0xf);
140 spin_unlock_irqrestore(&rtc_lock, flags);
141
142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
143}
144
145/*
146 * Report back to the Boot Processor during boot time or to the caller processor
147 * during CPU online.
148 */
149static void smp_callin(void)
150{
151 int cpuid, phys_id;
152
153 /*
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
158 */
159 cpuid = smp_processor_id();
160
161 /*
162 * (This works even if the APIC is not enabled.)
163 */
164 phys_id = read_apic_id();
165
166 /*
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
170 * boards)
171 */
172 apic_ap_setup();
173
174 /*
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
177 */
178 smp_store_cpu_info(cpuid);
179
180 /*
181 * Get our bogomips.
182 * Update loops_per_jiffy in cpu_data. Previous call to
183 * smp_store_cpu_info() stored a value that is close but not as
184 * accurate as the value just calculated.
185 */
186 calibrate_delay();
187 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
188 pr_debug("Stack at about %p\n", &cpuid);
189
190 /*
191 * This must be done before setting cpu_online_mask
192 * or calling notify_cpu_starting.
193 */
194 set_cpu_sibling_map(raw_smp_processor_id());
195 wmb();
196
197 notify_cpu_starting(cpuid);
198
199 /*
200 * Allow the master to continue.
201 */
202 cpumask_set_cpu(cpuid, cpu_callin_mask);
203}
204
205static int cpu0_logical_apicid;
206static int enable_start_cpu0;
207/*
208 * Activate a secondary processor.
209 */
210static void notrace start_secondary(void *unused)
211{
212 /*
213 * Don't put *anything* before cpu_init(), SMP booting is too
214 * fragile that we want to limit the things done here to the
215 * most necessary things.
216 */
217 cpu_init();
218 x86_cpuinit.early_percpu_clock_init();
219 preempt_disable();
220 smp_callin();
221
222 enable_start_cpu0 = 0;
223
224#ifdef CONFIG_X86_32
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir);
227 __flush_tlb_all();
228#endif
229
230 /* otherwise gcc will move up smp_processor_id before the cpu_init */
231 barrier();
232 /*
233 * Check TSC synchronization with the BP:
234 */
235 check_tsc_sync_target();
236
237 /*
238 * Lock vector_lock and initialize the vectors on this cpu
239 * before setting the cpu online. We must set it online with
240 * vector_lock held to prevent a concurrent setup/teardown
241 * from seeing a half valid vector space.
242 */
243 lock_vector_lock();
244 setup_vector_irq(smp_processor_id());
245 set_cpu_online(smp_processor_id(), true);
246 unlock_vector_lock();
247 cpu_set_state_online(smp_processor_id());
248 x86_platform.nmi_init();
249
250 /* enable local interrupts */
251 local_irq_enable();
252
253 /* to prevent fake stack check failure in clock setup */
254 boot_init_stack_canary();
255
256 x86_cpuinit.setup_percpu_clockev();
257
258 wmb();
259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
260}
261
262int topology_update_package_map(unsigned int apicid, unsigned int cpu)
263{
264 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
265
266 /* Called from early boot ? */
267 if (!physical_package_map)
268 return 0;
269
270 if (pkg >= max_physical_pkg_id)
271 return -EINVAL;
272
273 /* Set the logical package id */
274 if (test_and_set_bit(pkg, physical_package_map))
275 goto found;
276
277 new = find_first_zero_bit(logical_package_map, __max_logical_packages);
278 if (new >= __max_logical_packages) {
279 physical_to_logical_pkg[pkg] = -1;
280 pr_warn("APIC(%x) Package %u exceeds logical package map\n",
281 apicid, pkg);
282 return -ENOSPC;
283 }
284 set_bit(new, logical_package_map);
285 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
286 apicid, pkg, new);
287 physical_to_logical_pkg[pkg] = new;
288
289found:
290 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
291 return 0;
292}
293
294/**
295 * topology_phys_to_logical_pkg - Map a physical package id to a logical
296 *
297 * Returns logical package id or -1 if not found
298 */
299int topology_phys_to_logical_pkg(unsigned int phys_pkg)
300{
301 if (phys_pkg >= max_physical_pkg_id)
302 return -1;
303 return physical_to_logical_pkg[phys_pkg];
304}
305EXPORT_SYMBOL(topology_phys_to_logical_pkg);
306
307static void __init smp_init_package_map(void)
308{
309 unsigned int ncpus, cpu;
310 size_t size;
311
312 /*
313 * Today neither Intel nor AMD support heterogenous systems. That
314 * might change in the future....
315 *
316 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
317 * computation, this won't actually work since some Intel BIOSes
318 * report inconsistent HT data when they disable HT.
319 *
320 * In particular, they reduce the APIC-IDs to only include the cores,
321 * but leave the CPUID topology to say there are (2) siblings.
322 * This means we don't know how many threads there will be until
323 * after the APIC enumeration.
324 *
325 * By not including this we'll sometimes over-estimate the number of
326 * logical packages by the amount of !present siblings, but this is
327 * still better than MAX_LOCAL_APIC.
328 *
329 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
330 * on the command line leading to a similar issue as the HT disable
331 * problem because the hyperthreads are usually enumerated after the
332 * primary cores.
333 */
334 ncpus = boot_cpu_data.x86_max_cores;
335 if (!ncpus) {
336 pr_warn("x86_max_cores == zero !?!?");
337 ncpus = 1;
338 }
339
340 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
341
342 /*
343 * Possibly larger than what we need as the number of apic ids per
344 * package can be smaller than the actual used apic ids.
345 */
346 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
347 size = max_physical_pkg_id * sizeof(unsigned int);
348 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
349 memset(physical_to_logical_pkg, 0xff, size);
350 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
351 physical_package_map = kzalloc(size, GFP_KERNEL);
352 size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long);
353 logical_package_map = kzalloc(size, GFP_KERNEL);
354
355 pr_info("Max logical packages: %u\n", __max_logical_packages);
356
357 for_each_present_cpu(cpu) {
358 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
359
360 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
361 continue;
362 if (!topology_update_package_map(apicid, cpu))
363 continue;
364 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
365 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
366 set_cpu_possible(cpu, false);
367 set_cpu_present(cpu, false);
368 }
369}
370
371void __init smp_store_boot_cpu_info(void)
372{
373 int id = 0; /* CPU 0 */
374 struct cpuinfo_x86 *c = &cpu_data(id);
375
376 *c = boot_cpu_data;
377 c->cpu_index = id;
378 smp_init_package_map();
379}
380
381/*
382 * The bootstrap kernel entry code has set these up. Save them for
383 * a given CPU
384 */
385void smp_store_cpu_info(int id)
386{
387 struct cpuinfo_x86 *c = &cpu_data(id);
388
389 *c = boot_cpu_data;
390 c->cpu_index = id;
391 /*
392 * During boot time, CPU0 has this setup already. Save the info when
393 * bringing up AP or offlined CPU0.
394 */
395 identify_secondary_cpu(c);
396}
397
398static bool
399topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
400{
401 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
402
403 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
404}
405
406static bool
407topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
408{
409 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
410
411 return !WARN_ONCE(!topology_same_node(c, o),
412 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
413 "[node: %d != %d]. Ignoring dependency.\n",
414 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
415}
416
417#define link_mask(mfunc, c1, c2) \
418do { \
419 cpumask_set_cpu((c1), mfunc(c2)); \
420 cpumask_set_cpu((c2), mfunc(c1)); \
421} while (0)
422
423static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
424{
425 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
426 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
427
428 if (c->phys_proc_id == o->phys_proc_id &&
429 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
430 c->cpu_core_id == o->cpu_core_id)
431 return topology_sane(c, o, "smt");
432
433 } else if (c->phys_proc_id == o->phys_proc_id &&
434 c->cpu_core_id == o->cpu_core_id) {
435 return topology_sane(c, o, "smt");
436 }
437
438 return false;
439}
440
441static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
442{
443 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
444
445 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
446 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
447 return topology_sane(c, o, "llc");
448
449 return false;
450}
451
452/*
453 * Unlike the other levels, we do not enforce keeping a
454 * multicore group inside a NUMA node. If this happens, we will
455 * discard the MC level of the topology later.
456 */
457static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
458{
459 if (c->phys_proc_id == o->phys_proc_id)
460 return true;
461 return false;
462}
463
464static struct sched_domain_topology_level numa_inside_package_topology[] = {
465#ifdef CONFIG_SCHED_SMT
466 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
467#endif
468#ifdef CONFIG_SCHED_MC
469 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
470#endif
471 { NULL, },
472};
473/*
474 * set_sched_topology() sets the topology internal to a CPU. The
475 * NUMA topologies are layered on top of it to build the full
476 * system topology.
477 *
478 * If NUMA nodes are observed to occur within a CPU package, this
479 * function should be called. It forces the sched domain code to
480 * only use the SMT level for the CPU portion of the topology.
481 * This essentially falls back to relying on NUMA information
482 * from the SRAT table to describe the entire system topology
483 * (except for hyperthreads).
484 */
485static void primarily_use_numa_for_topology(void)
486{
487 set_sched_topology(numa_inside_package_topology);
488}
489
490void set_cpu_sibling_map(int cpu)
491{
492 bool has_smt = smp_num_siblings > 1;
493 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
494 struct cpuinfo_x86 *c = &cpu_data(cpu);
495 struct cpuinfo_x86 *o;
496 int i;
497
498 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
499
500 if (!has_mp) {
501 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
502 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
503 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
504 c->booted_cores = 1;
505 return;
506 }
507
508 for_each_cpu(i, cpu_sibling_setup_mask) {
509 o = &cpu_data(i);
510
511 if ((i == cpu) || (has_smt && match_smt(c, o)))
512 link_mask(topology_sibling_cpumask, cpu, i);
513
514 if ((i == cpu) || (has_mp && match_llc(c, o)))
515 link_mask(cpu_llc_shared_mask, cpu, i);
516
517 }
518
519 /*
520 * This needs a separate iteration over the cpus because we rely on all
521 * topology_sibling_cpumask links to be set-up.
522 */
523 for_each_cpu(i, cpu_sibling_setup_mask) {
524 o = &cpu_data(i);
525
526 if ((i == cpu) || (has_mp && match_die(c, o))) {
527 link_mask(topology_core_cpumask, cpu, i);
528
529 /*
530 * Does this new cpu bringup a new core?
531 */
532 if (cpumask_weight(
533 topology_sibling_cpumask(cpu)) == 1) {
534 /*
535 * for each core in package, increment
536 * the booted_cores for this new cpu
537 */
538 if (cpumask_first(
539 topology_sibling_cpumask(i)) == i)
540 c->booted_cores++;
541 /*
542 * increment the core count for all
543 * the other cpus in this package
544 */
545 if (i != cpu)
546 cpu_data(i).booted_cores++;
547 } else if (i != cpu && !c->booted_cores)
548 c->booted_cores = cpu_data(i).booted_cores;
549 }
550 if (match_die(c, o) && !topology_same_node(c, o))
551 primarily_use_numa_for_topology();
552 }
553}
554
555/* maps the cpu to the sched domain representing multi-core */
556const struct cpumask *cpu_coregroup_mask(int cpu)
557{
558 return cpu_llc_shared_mask(cpu);
559}
560
561static void impress_friends(void)
562{
563 int cpu;
564 unsigned long bogosum = 0;
565 /*
566 * Allow the user to impress friends.
567 */
568 pr_debug("Before bogomips\n");
569 for_each_possible_cpu(cpu)
570 if (cpumask_test_cpu(cpu, cpu_callout_mask))
571 bogosum += cpu_data(cpu).loops_per_jiffy;
572 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
573 num_online_cpus(),
574 bogosum/(500000/HZ),
575 (bogosum/(5000/HZ))%100);
576
577 pr_debug("Before bogocount - setting activated=1\n");
578}
579
580void __inquire_remote_apic(int apicid)
581{
582 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
583 const char * const names[] = { "ID", "VERSION", "SPIV" };
584 int timeout;
585 u32 status;
586
587 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
588
589 for (i = 0; i < ARRAY_SIZE(regs); i++) {
590 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
591
592 /*
593 * Wait for idle.
594 */
595 status = safe_apic_wait_icr_idle();
596 if (status)
597 pr_cont("a previous APIC delivery may have failed\n");
598
599 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
600
601 timeout = 0;
602 do {
603 udelay(100);
604 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
605 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
606
607 switch (status) {
608 case APIC_ICR_RR_VALID:
609 status = apic_read(APIC_RRR);
610 pr_cont("%08x\n", status);
611 break;
612 default:
613 pr_cont("failed\n");
614 }
615 }
616}
617
618/*
619 * The Multiprocessor Specification 1.4 (1997) example code suggests
620 * that there should be a 10ms delay between the BSP asserting INIT
621 * and de-asserting INIT, when starting a remote processor.
622 * But that slows boot and resume on modern processors, which include
623 * many cores and don't require that delay.
624 *
625 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
626 * Modern processor families are quirked to remove the delay entirely.
627 */
628#define UDELAY_10MS_DEFAULT 10000
629
630static unsigned int init_udelay = UINT_MAX;
631
632static int __init cpu_init_udelay(char *str)
633{
634 get_option(&str, &init_udelay);
635
636 return 0;
637}
638early_param("cpu_init_udelay", cpu_init_udelay);
639
640static void __init smp_quirk_init_udelay(void)
641{
642 /* if cmdline changed it from default, leave it alone */
643 if (init_udelay != UINT_MAX)
644 return;
645
646 /* if modern processor, use no delay */
647 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
648 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
649 init_udelay = 0;
650 return;
651 }
652 /* else, use legacy delay */
653 init_udelay = UDELAY_10MS_DEFAULT;
654}
655
656/*
657 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
658 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
659 * won't ... remember to clear down the APIC, etc later.
660 */
661int
662wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
663{
664 unsigned long send_status, accept_status = 0;
665 int maxlvt;
666
667 /* Target chip */
668 /* Boot on the stack */
669 /* Kick the second */
670 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
671
672 pr_debug("Waiting for send to finish...\n");
673 send_status = safe_apic_wait_icr_idle();
674
675 /*
676 * Give the other CPU some time to accept the IPI.
677 */
678 udelay(200);
679 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
680 maxlvt = lapic_get_maxlvt();
681 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
682 apic_write(APIC_ESR, 0);
683 accept_status = (apic_read(APIC_ESR) & 0xEF);
684 }
685 pr_debug("NMI sent\n");
686
687 if (send_status)
688 pr_err("APIC never delivered???\n");
689 if (accept_status)
690 pr_err("APIC delivery error (%lx)\n", accept_status);
691
692 return (send_status | accept_status);
693}
694
695static int
696wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
697{
698 unsigned long send_status = 0, accept_status = 0;
699 int maxlvt, num_starts, j;
700
701 maxlvt = lapic_get_maxlvt();
702
703 /*
704 * Be paranoid about clearing APIC errors.
705 */
706 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
707 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
708 apic_write(APIC_ESR, 0);
709 apic_read(APIC_ESR);
710 }
711
712 pr_debug("Asserting INIT\n");
713
714 /*
715 * Turn INIT on target chip
716 */
717 /*
718 * Send IPI
719 */
720 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
721 phys_apicid);
722
723 pr_debug("Waiting for send to finish...\n");
724 send_status = safe_apic_wait_icr_idle();
725
726 udelay(init_udelay);
727
728 pr_debug("Deasserting INIT\n");
729
730 /* Target chip */
731 /* Send IPI */
732 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
733
734 pr_debug("Waiting for send to finish...\n");
735 send_status = safe_apic_wait_icr_idle();
736
737 mb();
738
739 /*
740 * Should we send STARTUP IPIs ?
741 *
742 * Determine this based on the APIC version.
743 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
744 */
745 if (APIC_INTEGRATED(apic_version[phys_apicid]))
746 num_starts = 2;
747 else
748 num_starts = 0;
749
750 /*
751 * Run STARTUP IPI loop.
752 */
753 pr_debug("#startup loops: %d\n", num_starts);
754
755 for (j = 1; j <= num_starts; j++) {
756 pr_debug("Sending STARTUP #%d\n", j);
757 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
758 apic_write(APIC_ESR, 0);
759 apic_read(APIC_ESR);
760 pr_debug("After apic_write\n");
761
762 /*
763 * STARTUP IPI
764 */
765
766 /* Target chip */
767 /* Boot on the stack */
768 /* Kick the second */
769 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
770 phys_apicid);
771
772 /*
773 * Give the other CPU some time to accept the IPI.
774 */
775 if (init_udelay == 0)
776 udelay(10);
777 else
778 udelay(300);
779
780 pr_debug("Startup point 1\n");
781
782 pr_debug("Waiting for send to finish...\n");
783 send_status = safe_apic_wait_icr_idle();
784
785 /*
786 * Give the other CPU some time to accept the IPI.
787 */
788 if (init_udelay == 0)
789 udelay(10);
790 else
791 udelay(200);
792
793 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
794 apic_write(APIC_ESR, 0);
795 accept_status = (apic_read(APIC_ESR) & 0xEF);
796 if (send_status || accept_status)
797 break;
798 }
799 pr_debug("After Startup\n");
800
801 if (send_status)
802 pr_err("APIC never delivered???\n");
803 if (accept_status)
804 pr_err("APIC delivery error (%lx)\n", accept_status);
805
806 return (send_status | accept_status);
807}
808
809void smp_announce(void)
810{
811 int num_nodes = num_online_nodes();
812
813 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
814 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
815}
816
817/* reduce the number of lines printed when booting a large cpu count system */
818static void announce_cpu(int cpu, int apicid)
819{
820 static int current_node = -1;
821 int node = early_cpu_to_node(cpu);
822 static int width, node_width;
823
824 if (!width)
825 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
826
827 if (!node_width)
828 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
829
830 if (cpu == 1)
831 printk(KERN_INFO "x86: Booting SMP configuration:\n");
832
833 if (system_state == SYSTEM_BOOTING) {
834 if (node != current_node) {
835 if (current_node > (-1))
836 pr_cont("\n");
837 current_node = node;
838
839 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
840 node_width - num_digits(node), " ", node);
841 }
842
843 /* Add padding for the BSP */
844 if (cpu == 1)
845 pr_cont("%*s", width + 1, " ");
846
847 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
848
849 } else
850 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
851 node, cpu, apicid);
852}
853
854static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
855{
856 int cpu;
857
858 cpu = smp_processor_id();
859 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
860 return NMI_HANDLED;
861
862 return NMI_DONE;
863}
864
865/*
866 * Wake up AP by INIT, INIT, STARTUP sequence.
867 *
868 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
869 * boot-strap code which is not a desired behavior for waking up BSP. To
870 * void the boot-strap code, wake up CPU0 by NMI instead.
871 *
872 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
873 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
874 * We'll change this code in the future to wake up hard offlined CPU0 if
875 * real platform and request are available.
876 */
877static int
878wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
879 int *cpu0_nmi_registered)
880{
881 int id;
882 int boot_error;
883
884 preempt_disable();
885
886 /*
887 * Wake up AP by INIT, INIT, STARTUP sequence.
888 */
889 if (cpu) {
890 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
891 goto out;
892 }
893
894 /*
895 * Wake up BSP by nmi.
896 *
897 * Register a NMI handler to help wake up CPU0.
898 */
899 boot_error = register_nmi_handler(NMI_LOCAL,
900 wakeup_cpu0_nmi, 0, "wake_cpu0");
901
902 if (!boot_error) {
903 enable_start_cpu0 = 1;
904 *cpu0_nmi_registered = 1;
905 if (apic->dest_logical == APIC_DEST_LOGICAL)
906 id = cpu0_logical_apicid;
907 else
908 id = apicid;
909 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
910 }
911
912out:
913 preempt_enable();
914
915 return boot_error;
916}
917
918void common_cpu_up(unsigned int cpu, struct task_struct *idle)
919{
920 /* Just in case we booted with a single CPU. */
921 alternatives_enable_smp();
922
923 per_cpu(current_task, cpu) = idle;
924
925#ifdef CONFIG_X86_32
926 /* Stack for startup_32 can be just as for start_secondary onwards */
927 irq_ctx_init(cpu);
928 per_cpu(cpu_current_top_of_stack, cpu) =
929 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
930#else
931 clear_tsk_thread_flag(idle, TIF_FORK);
932 initial_gs = per_cpu_offset(cpu);
933#endif
934}
935
936/*
937 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
938 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
939 * Returns zero if CPU booted OK, else error code from
940 * ->wakeup_secondary_cpu.
941 */
942static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
943{
944 volatile u32 *trampoline_status =
945 (volatile u32 *) __va(real_mode_header->trampoline_status);
946 /* start_ip had better be page-aligned! */
947 unsigned long start_ip = real_mode_header->trampoline_start;
948
949 unsigned long boot_error = 0;
950 int cpu0_nmi_registered = 0;
951 unsigned long timeout;
952
953 idle->thread.sp = (unsigned long) (((struct pt_regs *)
954 (THREAD_SIZE + task_stack_page(idle))) - 1);
955
956 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
957 initial_code = (unsigned long)start_secondary;
958 stack_start = idle->thread.sp;
959
960 /*
961 * Enable the espfix hack for this CPU
962 */
963#ifdef CONFIG_X86_ESPFIX64
964 init_espfix_ap(cpu);
965#endif
966
967 /* So we see what's up */
968 announce_cpu(cpu, apicid);
969
970 /*
971 * This grunge runs the startup process for
972 * the targeted processor.
973 */
974
975 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
976
977 pr_debug("Setting warm reset code and vector.\n");
978
979 smpboot_setup_warm_reset_vector(start_ip);
980 /*
981 * Be paranoid about clearing APIC errors.
982 */
983 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
984 apic_write(APIC_ESR, 0);
985 apic_read(APIC_ESR);
986 }
987 }
988
989 /*
990 * AP might wait on cpu_callout_mask in cpu_init() with
991 * cpu_initialized_mask set if previous attempt to online
992 * it timed-out. Clear cpu_initialized_mask so that after
993 * INIT/SIPI it could start with a clean state.
994 */
995 cpumask_clear_cpu(cpu, cpu_initialized_mask);
996 smp_mb();
997
998 /*
999 * Wake up a CPU in difference cases:
1000 * - Use the method in the APIC driver if it's defined
1001 * Otherwise,
1002 * - Use an INIT boot APIC message for APs or NMI for BSP.
1003 */
1004 if (apic->wakeup_secondary_cpu)
1005 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1006 else
1007 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1008 &cpu0_nmi_registered);
1009
1010 if (!boot_error) {
1011 /*
1012 * Wait 10s total for first sign of life from AP
1013 */
1014 boot_error = -1;
1015 timeout = jiffies + 10*HZ;
1016 while (time_before(jiffies, timeout)) {
1017 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1018 /*
1019 * Tell AP to proceed with initialization
1020 */
1021 cpumask_set_cpu(cpu, cpu_callout_mask);
1022 boot_error = 0;
1023 break;
1024 }
1025 schedule();
1026 }
1027 }
1028
1029 if (!boot_error) {
1030 /*
1031 * Wait till AP completes initial initialization
1032 */
1033 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1034 /*
1035 * Allow other tasks to run while we wait for the
1036 * AP to come online. This also gives a chance
1037 * for the MTRR work(triggered by the AP coming online)
1038 * to be completed in the stop machine context.
1039 */
1040 schedule();
1041 }
1042 }
1043
1044 /* mark "stuck" area as not stuck */
1045 *trampoline_status = 0;
1046
1047 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1048 /*
1049 * Cleanup possible dangling ends...
1050 */
1051 smpboot_restore_warm_reset_vector();
1052 }
1053 /*
1054 * Clean up the nmi handler. Do this after the callin and callout sync
1055 * to avoid impact of possible long unregister time.
1056 */
1057 if (cpu0_nmi_registered)
1058 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1059
1060 return boot_error;
1061}
1062
1063int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1064{
1065 int apicid = apic->cpu_present_to_apicid(cpu);
1066 unsigned long flags;
1067 int err;
1068
1069 WARN_ON(irqs_disabled());
1070
1071 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1072
1073 if (apicid == BAD_APICID ||
1074 !physid_isset(apicid, phys_cpu_present_map) ||
1075 !apic->apic_id_valid(apicid)) {
1076 pr_err("%s: bad cpu %d\n", __func__, cpu);
1077 return -EINVAL;
1078 }
1079
1080 /*
1081 * Already booted CPU?
1082 */
1083 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1084 pr_debug("do_boot_cpu %d Already started\n", cpu);
1085 return -ENOSYS;
1086 }
1087
1088 /*
1089 * Save current MTRR state in case it was changed since early boot
1090 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1091 */
1092 mtrr_save_state();
1093
1094 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1095 err = cpu_check_up_prepare(cpu);
1096 if (err && err != -EBUSY)
1097 return err;
1098
1099 /* the FPU context is blank, nobody can own it */
1100 __cpu_disable_lazy_restore(cpu);
1101
1102 common_cpu_up(cpu, tidle);
1103
1104 /*
1105 * We have to walk the irq descriptors to setup the vector
1106 * space for the cpu which comes online. Prevent irq
1107 * alloc/free across the bringup.
1108 */
1109 irq_lock_sparse();
1110
1111 err = do_boot_cpu(apicid, cpu, tidle);
1112
1113 if (err) {
1114 irq_unlock_sparse();
1115 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1116 return -EIO;
1117 }
1118
1119 /*
1120 * Check TSC synchronization with the AP (keep irqs disabled
1121 * while doing so):
1122 */
1123 local_irq_save(flags);
1124 check_tsc_sync_source(cpu);
1125 local_irq_restore(flags);
1126
1127 while (!cpu_online(cpu)) {
1128 cpu_relax();
1129 touch_nmi_watchdog();
1130 }
1131
1132 irq_unlock_sparse();
1133
1134 return 0;
1135}
1136
1137/**
1138 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1139 */
1140void arch_disable_smp_support(void)
1141{
1142 disable_ioapic_support();
1143}
1144
1145/*
1146 * Fall back to non SMP mode after errors.
1147 *
1148 * RED-PEN audit/test this more. I bet there is more state messed up here.
1149 */
1150static __init void disable_smp(void)
1151{
1152 pr_info("SMP disabled\n");
1153
1154 disable_ioapic_support();
1155
1156 init_cpu_present(cpumask_of(0));
1157 init_cpu_possible(cpumask_of(0));
1158
1159 if (smp_found_config)
1160 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1161 else
1162 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1163 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1164 cpumask_set_cpu(0, topology_core_cpumask(0));
1165}
1166
1167enum {
1168 SMP_OK,
1169 SMP_NO_CONFIG,
1170 SMP_NO_APIC,
1171 SMP_FORCE_UP,
1172};
1173
1174/*
1175 * Various sanity checks.
1176 */
1177static int __init smp_sanity_check(unsigned max_cpus)
1178{
1179 preempt_disable();
1180
1181#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1182 if (def_to_bigsmp && nr_cpu_ids > 8) {
1183 unsigned int cpu;
1184 unsigned nr;
1185
1186 pr_warn("More than 8 CPUs detected - skipping them\n"
1187 "Use CONFIG_X86_BIGSMP\n");
1188
1189 nr = 0;
1190 for_each_present_cpu(cpu) {
1191 if (nr >= 8)
1192 set_cpu_present(cpu, false);
1193 nr++;
1194 }
1195
1196 nr = 0;
1197 for_each_possible_cpu(cpu) {
1198 if (nr >= 8)
1199 set_cpu_possible(cpu, false);
1200 nr++;
1201 }
1202
1203 nr_cpu_ids = 8;
1204 }
1205#endif
1206
1207 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1208 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1209 hard_smp_processor_id());
1210
1211 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1212 }
1213
1214 /*
1215 * If we couldn't find an SMP configuration at boot time,
1216 * get out of here now!
1217 */
1218 if (!smp_found_config && !acpi_lapic) {
1219 preempt_enable();
1220 pr_notice("SMP motherboard not detected\n");
1221 return SMP_NO_CONFIG;
1222 }
1223
1224 /*
1225 * Should not be necessary because the MP table should list the boot
1226 * CPU too, but we do it for the sake of robustness anyway.
1227 */
1228 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1229 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1230 boot_cpu_physical_apicid);
1231 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1232 }
1233 preempt_enable();
1234
1235 /*
1236 * If we couldn't find a local APIC, then get out of here now!
1237 */
1238 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1239 !cpu_has_apic) {
1240 if (!disable_apic) {
1241 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1242 boot_cpu_physical_apicid);
1243 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1244 }
1245 return SMP_NO_APIC;
1246 }
1247
1248 /*
1249 * If SMP should be disabled, then really disable it!
1250 */
1251 if (!max_cpus) {
1252 pr_info("SMP mode deactivated\n");
1253 return SMP_FORCE_UP;
1254 }
1255
1256 return SMP_OK;
1257}
1258
1259static void __init smp_cpu_index_default(void)
1260{
1261 int i;
1262 struct cpuinfo_x86 *c;
1263
1264 for_each_possible_cpu(i) {
1265 c = &cpu_data(i);
1266 /* mark all to hotplug */
1267 c->cpu_index = nr_cpu_ids;
1268 }
1269}
1270
1271/*
1272 * Prepare for SMP bootup. The MP table or ACPI has been read
1273 * earlier. Just do some sanity checking here and enable APIC mode.
1274 */
1275void __init native_smp_prepare_cpus(unsigned int max_cpus)
1276{
1277 unsigned int i;
1278
1279 smp_cpu_index_default();
1280
1281 /*
1282 * Setup boot CPU information
1283 */
1284 smp_store_boot_cpu_info(); /* Final full version of the data */
1285 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1286 mb();
1287
1288 current_thread_info()->cpu = 0; /* needed? */
1289 for_each_possible_cpu(i) {
1290 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1291 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1292 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1293 }
1294 set_cpu_sibling_map(0);
1295
1296 switch (smp_sanity_check(max_cpus)) {
1297 case SMP_NO_CONFIG:
1298 disable_smp();
1299 if (APIC_init_uniprocessor())
1300 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1301 return;
1302 case SMP_NO_APIC:
1303 disable_smp();
1304 return;
1305 case SMP_FORCE_UP:
1306 disable_smp();
1307 apic_bsp_setup(false);
1308 return;
1309 case SMP_OK:
1310 break;
1311 }
1312
1313 default_setup_apic_routing();
1314
1315 if (read_apic_id() != boot_cpu_physical_apicid) {
1316 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1317 read_apic_id(), boot_cpu_physical_apicid);
1318 /* Or can we switch back to PIC here? */
1319 }
1320
1321 cpu0_logical_apicid = apic_bsp_setup(false);
1322
1323 pr_info("CPU%d: ", 0);
1324 print_cpu_info(&cpu_data(0));
1325
1326 if (is_uv_system())
1327 uv_system_init();
1328
1329 set_mtrr_aps_delayed_init();
1330
1331 smp_quirk_init_udelay();
1332}
1333
1334void arch_enable_nonboot_cpus_begin(void)
1335{
1336 set_mtrr_aps_delayed_init();
1337}
1338
1339void arch_enable_nonboot_cpus_end(void)
1340{
1341 mtrr_aps_init();
1342}
1343
1344/*
1345 * Early setup to make printk work.
1346 */
1347void __init native_smp_prepare_boot_cpu(void)
1348{
1349 int me = smp_processor_id();
1350 switch_to_new_gdt(me);
1351 /* already set me in cpu_online_mask in boot_cpu_init() */
1352 cpumask_set_cpu(me, cpu_callout_mask);
1353 cpu_set_state_online(me);
1354}
1355
1356void __init native_smp_cpus_done(unsigned int max_cpus)
1357{
1358 pr_debug("Boot done\n");
1359
1360 nmi_selftest();
1361 impress_friends();
1362 setup_ioapic_dest();
1363 mtrr_aps_init();
1364}
1365
1366static int __initdata setup_possible_cpus = -1;
1367static int __init _setup_possible_cpus(char *str)
1368{
1369 get_option(&str, &setup_possible_cpus);
1370 return 0;
1371}
1372early_param("possible_cpus", _setup_possible_cpus);
1373
1374
1375/*
1376 * cpu_possible_mask should be static, it cannot change as cpu's
1377 * are onlined, or offlined. The reason is per-cpu data-structures
1378 * are allocated by some modules at init time, and dont expect to
1379 * do this dynamically on cpu arrival/departure.
1380 * cpu_present_mask on the other hand can change dynamically.
1381 * In case when cpu_hotplug is not compiled, then we resort to current
1382 * behaviour, which is cpu_possible == cpu_present.
1383 * - Ashok Raj
1384 *
1385 * Three ways to find out the number of additional hotplug CPUs:
1386 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1387 * - The user can overwrite it with possible_cpus=NUM
1388 * - Otherwise don't reserve additional CPUs.
1389 * We do this because additional CPUs waste a lot of memory.
1390 * -AK
1391 */
1392__init void prefill_possible_map(void)
1393{
1394 int i, possible;
1395
1396 /* no processor from mptable or madt */
1397 if (!num_processors)
1398 num_processors = 1;
1399
1400 i = setup_max_cpus ?: 1;
1401 if (setup_possible_cpus == -1) {
1402 possible = num_processors;
1403#ifdef CONFIG_HOTPLUG_CPU
1404 if (setup_max_cpus)
1405 possible += disabled_cpus;
1406#else
1407 if (possible > i)
1408 possible = i;
1409#endif
1410 } else
1411 possible = setup_possible_cpus;
1412
1413 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1414
1415 /* nr_cpu_ids could be reduced via nr_cpus= */
1416 if (possible > nr_cpu_ids) {
1417 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1418 possible, nr_cpu_ids);
1419 possible = nr_cpu_ids;
1420 }
1421
1422#ifdef CONFIG_HOTPLUG_CPU
1423 if (!setup_max_cpus)
1424#endif
1425 if (possible > i) {
1426 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1427 possible, setup_max_cpus);
1428 possible = i;
1429 }
1430
1431 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1432 possible, max_t(int, possible - num_processors, 0));
1433
1434 for (i = 0; i < possible; i++)
1435 set_cpu_possible(i, true);
1436 for (; i < NR_CPUS; i++)
1437 set_cpu_possible(i, false);
1438
1439 nr_cpu_ids = possible;
1440}
1441
1442#ifdef CONFIG_HOTPLUG_CPU
1443
1444static void remove_siblinginfo(int cpu)
1445{
1446 int sibling;
1447 struct cpuinfo_x86 *c = &cpu_data(cpu);
1448
1449 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1450 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1451 /*/
1452 * last thread sibling in this cpu core going down
1453 */
1454 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1455 cpu_data(sibling).booted_cores--;
1456 }
1457
1458 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1459 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1460 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1461 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1462 cpumask_clear(cpu_llc_shared_mask(cpu));
1463 cpumask_clear(topology_sibling_cpumask(cpu));
1464 cpumask_clear(topology_core_cpumask(cpu));
1465 c->phys_proc_id = 0;
1466 c->cpu_core_id = 0;
1467 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1468}
1469
1470static void remove_cpu_from_maps(int cpu)
1471{
1472 set_cpu_online(cpu, false);
1473 cpumask_clear_cpu(cpu, cpu_callout_mask);
1474 cpumask_clear_cpu(cpu, cpu_callin_mask);
1475 /* was set by cpu_init() */
1476 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1477 numa_remove_cpu(cpu);
1478}
1479
1480void cpu_disable_common(void)
1481{
1482 int cpu = smp_processor_id();
1483
1484 remove_siblinginfo(cpu);
1485
1486 /* It's now safe to remove this processor from the online map */
1487 lock_vector_lock();
1488 remove_cpu_from_maps(cpu);
1489 unlock_vector_lock();
1490 fixup_irqs();
1491}
1492
1493int native_cpu_disable(void)
1494{
1495 int ret;
1496
1497 ret = check_irq_vectors_for_cpu_disable();
1498 if (ret)
1499 return ret;
1500
1501 clear_local_APIC();
1502 cpu_disable_common();
1503
1504 return 0;
1505}
1506
1507int common_cpu_die(unsigned int cpu)
1508{
1509 int ret = 0;
1510
1511 /* We don't do anything here: idle task is faking death itself. */
1512
1513 /* They ack this in play_dead() by setting CPU_DEAD */
1514 if (cpu_wait_death(cpu, 5)) {
1515 if (system_state == SYSTEM_RUNNING)
1516 pr_info("CPU %u is now offline\n", cpu);
1517 } else {
1518 pr_err("CPU %u didn't die...\n", cpu);
1519 ret = -1;
1520 }
1521
1522 return ret;
1523}
1524
1525void native_cpu_die(unsigned int cpu)
1526{
1527 common_cpu_die(cpu);
1528}
1529
1530void play_dead_common(void)
1531{
1532 idle_task_exit();
1533 reset_lazy_tlbstate();
1534 amd_e400_remove_cpu(raw_smp_processor_id());
1535
1536 /* Ack it */
1537 (void)cpu_report_death();
1538
1539 /*
1540 * With physical CPU hotplug, we should halt the cpu
1541 */
1542 local_irq_disable();
1543}
1544
1545static bool wakeup_cpu0(void)
1546{
1547 if (smp_processor_id() == 0 && enable_start_cpu0)
1548 return true;
1549
1550 return false;
1551}
1552
1553/*
1554 * We need to flush the caches before going to sleep, lest we have
1555 * dirty data in our caches when we come back up.
1556 */
1557static inline void mwait_play_dead(void)
1558{
1559 unsigned int eax, ebx, ecx, edx;
1560 unsigned int highest_cstate = 0;
1561 unsigned int highest_subcstate = 0;
1562 void *mwait_ptr;
1563 int i;
1564
1565 if (!this_cpu_has(X86_FEATURE_MWAIT))
1566 return;
1567 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1568 return;
1569 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1570 return;
1571
1572 eax = CPUID_MWAIT_LEAF;
1573 ecx = 0;
1574 native_cpuid(&eax, &ebx, &ecx, &edx);
1575
1576 /*
1577 * eax will be 0 if EDX enumeration is not valid.
1578 * Initialized below to cstate, sub_cstate value when EDX is valid.
1579 */
1580 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1581 eax = 0;
1582 } else {
1583 edx >>= MWAIT_SUBSTATE_SIZE;
1584 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1585 if (edx & MWAIT_SUBSTATE_MASK) {
1586 highest_cstate = i;
1587 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1588 }
1589 }
1590 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1591 (highest_subcstate - 1);
1592 }
1593
1594 /*
1595 * This should be a memory location in a cache line which is
1596 * unlikely to be touched by other processors. The actual
1597 * content is immaterial as it is not actually modified in any way.
1598 */
1599 mwait_ptr = ¤t_thread_info()->flags;
1600
1601 wbinvd();
1602
1603 while (1) {
1604 /*
1605 * The CLFLUSH is a workaround for erratum AAI65 for
1606 * the Xeon 7400 series. It's not clear it is actually
1607 * needed, but it should be harmless in either case.
1608 * The WBINVD is insufficient due to the spurious-wakeup
1609 * case where we return around the loop.
1610 */
1611 mb();
1612 clflush(mwait_ptr);
1613 mb();
1614 __monitor(mwait_ptr, 0, 0);
1615 mb();
1616 __mwait(eax, 0);
1617 /*
1618 * If NMI wants to wake up CPU0, start CPU0.
1619 */
1620 if (wakeup_cpu0())
1621 start_cpu0();
1622 }
1623}
1624
1625static inline void hlt_play_dead(void)
1626{
1627 if (__this_cpu_read(cpu_info.x86) >= 4)
1628 wbinvd();
1629
1630 while (1) {
1631 native_halt();
1632 /*
1633 * If NMI wants to wake up CPU0, start CPU0.
1634 */
1635 if (wakeup_cpu0())
1636 start_cpu0();
1637 }
1638}
1639
1640void native_play_dead(void)
1641{
1642 play_dead_common();
1643 tboot_shutdown(TB_SHUTDOWN_WFS);
1644
1645 mwait_play_dead(); /* Only returns on failure */
1646 if (cpuidle_play_dead())
1647 hlt_play_dead();
1648}
1649
1650#else /* ... !CONFIG_HOTPLUG_CPU */
1651int native_cpu_disable(void)
1652{
1653 return -ENOSYS;
1654}
1655
1656void native_cpu_die(unsigned int cpu)
1657{
1658 /* We said "no" in __cpu_disable */
1659 BUG();
1660}
1661
1662void native_play_dead(void)
1663{
1664 BUG();
1665}
1666
1667#endif