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1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56#include <linux/kexec.h>
57#include <linux/numa.h>
58#include <linux/pgtable.h>
59#include <linux/overflow.h>
60#include <linux/stackprotector.h>
61#include <linux/cpuhotplug.h>
62#include <linux/mc146818rtc.h>
63#include <linux/acpi.h>
64
65#include <asm/acpi.h>
66#include <asm/cacheinfo.h>
67#include <asm/desc.h>
68#include <asm/nmi.h>
69#include <asm/irq.h>
70#include <asm/realmode.h>
71#include <asm/cpu.h>
72#include <asm/numa.h>
73#include <asm/tlbflush.h>
74#include <asm/mtrr.h>
75#include <asm/mwait.h>
76#include <asm/apic.h>
77#include <asm/io_apic.h>
78#include <asm/fpu/api.h>
79#include <asm/setup.h>
80#include <asm/uv/uv.h>
81#include <asm/microcode.h>
82#include <asm/i8259.h>
83#include <asm/misc.h>
84#include <asm/qspinlock.h>
85#include <asm/intel-family.h>
86#include <asm/cpu_device_id.h>
87#include <asm/spec-ctrl.h>
88#include <asm/hw_irq.h>
89#include <asm/stackprotector.h>
90#include <asm/sev.h>
91#include <asm/spec-ctrl.h>
92
93/* representing HT siblings of each logical CPU */
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
95EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
96
97/* representing HT and core siblings of each logical CPU */
98DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
99EXPORT_PER_CPU_SYMBOL(cpu_core_map);
100
101/* representing HT, core, and die siblings of each logical CPU */
102DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
103EXPORT_PER_CPU_SYMBOL(cpu_die_map);
104
105/* CPUs which are the primary SMT threads */
106struct cpumask __cpu_primary_thread_mask __read_mostly;
107
108/* Representing CPUs for which sibling maps can be computed */
109static cpumask_var_t cpu_sibling_setup_mask;
110
111struct mwait_cpu_dead {
112 unsigned int control;
113 unsigned int status;
114};
115
116#define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
117#define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
118
119/*
120 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
121 * that it's unlikely to be touched by other CPUs.
122 */
123static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
124
125/* Maximum number of SMT threads on any online core */
126int __read_mostly __max_smt_threads = 1;
127
128/* Flag to indicate if a complete sched domain rebuild is required */
129bool x86_topology_update;
130
131int arch_update_cpu_topology(void)
132{
133 int retval = x86_topology_update;
134
135 x86_topology_update = false;
136 return retval;
137}
138
139static unsigned int smpboot_warm_reset_vector_count;
140
141static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
142{
143 unsigned long flags;
144
145 spin_lock_irqsave(&rtc_lock, flags);
146 if (!smpboot_warm_reset_vector_count++) {
147 CMOS_WRITE(0xa, 0xf);
148 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
150 }
151 spin_unlock_irqrestore(&rtc_lock, flags);
152}
153
154static inline void smpboot_restore_warm_reset_vector(void)
155{
156 unsigned long flags;
157
158 /*
159 * Paranoid: Set warm reset code and vector here back
160 * to default values.
161 */
162 spin_lock_irqsave(&rtc_lock, flags);
163 if (!--smpboot_warm_reset_vector_count) {
164 CMOS_WRITE(0, 0xf);
165 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
166 }
167 spin_unlock_irqrestore(&rtc_lock, flags);
168
169}
170
171/* Run the next set of setup steps for the upcoming CPU */
172static void ap_starting(void)
173{
174 int cpuid = smp_processor_id();
175
176 /* Mop up eventual mwait_play_dead() wreckage */
177 this_cpu_write(mwait_cpu_dead.status, 0);
178 this_cpu_write(mwait_cpu_dead.control, 0);
179
180 /*
181 * If woken up by an INIT in an 82489DX configuration the alive
182 * synchronization guarantees that the CPU does not reach this
183 * point before an INIT_deassert IPI reaches the local APIC, so it
184 * is now safe to touch the local APIC.
185 *
186 * Set up this CPU, first the APIC, which is probably redundant on
187 * most boards.
188 */
189 apic_ap_setup();
190
191 /* Save the processor parameters. */
192 smp_store_cpu_info(cpuid);
193
194 /*
195 * The topology information must be up to date before
196 * notify_cpu_starting().
197 */
198 set_cpu_sibling_map(cpuid);
199
200 ap_init_aperfmperf();
201
202 pr_debug("Stack at about %p\n", &cpuid);
203
204 wmb();
205
206 /*
207 * This runs the AP through all the cpuhp states to its target
208 * state CPUHP_ONLINE.
209 */
210 notify_cpu_starting(cpuid);
211}
212
213static void ap_calibrate_delay(void)
214{
215 /*
216 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
217 * smp_store_cpu_info() stored a value that is close but not as
218 * accurate as the value just calculated.
219 *
220 * As this is invoked after the TSC synchronization check,
221 * calibrate_delay_is_known() will skip the calibration routine
222 * when TSC is synchronized across sockets.
223 */
224 calibrate_delay();
225 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
226}
227
228/*
229 * Activate a secondary processor.
230 */
231static void notrace start_secondary(void *unused)
232{
233 /*
234 * Don't put *anything* except direct CPU state initialization
235 * before cpu_init(), SMP booting is too fragile that we want to
236 * limit the things done here to the most necessary things.
237 */
238 cr4_init();
239
240 /*
241 * 32-bit specific. 64-bit reaches this code with the correct page
242 * table established. Yet another historical divergence.
243 */
244 if (IS_ENABLED(CONFIG_X86_32)) {
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir);
247 __flush_tlb_all();
248 }
249
250 cpu_init_exception_handling(false);
251
252 /*
253 * Load the microcode before reaching the AP alive synchronization
254 * point below so it is not part of the full per CPU serialized
255 * bringup part when "parallel" bringup is enabled.
256 *
257 * That's even safe when hyperthreading is enabled in the CPU as
258 * the core code starts the primary threads first and leaves the
259 * secondary threads waiting for SIPI. Loading microcode on
260 * physical cores concurrently is a safe operation.
261 *
262 * This covers both the Intel specific issue that concurrent
263 * microcode loading on SMT siblings must be prohibited and the
264 * vendor independent issue`that microcode loading which changes
265 * CPUID, MSRs etc. must be strictly serialized to maintain
266 * software state correctness.
267 */
268 load_ucode_ap();
269
270 /*
271 * Synchronization point with the hotplug core. Sets this CPUs
272 * synchronization state to ALIVE and spin-waits for the control CPU to
273 * release this CPU for further bringup.
274 */
275 cpuhp_ap_sync_alive();
276
277 cpu_init();
278 fpu__init_cpu();
279 rcutree_report_cpu_starting(raw_smp_processor_id());
280 x86_cpuinit.early_percpu_clock_init();
281
282 ap_starting();
283
284 /* Check TSC synchronization with the control CPU. */
285 check_tsc_sync_target();
286
287 /*
288 * Calibrate the delay loop after the TSC synchronization check.
289 * This allows to skip the calibration when TSC is synchronized
290 * across sockets.
291 */
292 ap_calibrate_delay();
293
294 speculative_store_bypass_ht_init();
295
296 /*
297 * Lock vector_lock, set CPU online and bring the vector
298 * allocator online. Online must be set with vector_lock held
299 * to prevent a concurrent irq setup/teardown from seeing a
300 * half valid vector space.
301 */
302 lock_vector_lock();
303 set_cpu_online(smp_processor_id(), true);
304 lapic_online();
305 unlock_vector_lock();
306 x86_platform.nmi_init();
307
308 /* enable local interrupts */
309 local_irq_enable();
310
311 x86_cpuinit.setup_percpu_clockev();
312
313 wmb();
314 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
315}
316
317/*
318 * The bootstrap kernel entry code has set these up. Save them for
319 * a given CPU
320 */
321void smp_store_cpu_info(int id)
322{
323 struct cpuinfo_x86 *c = &cpu_data(id);
324
325 /* Copy boot_cpu_data only on the first bringup */
326 if (!c->initialized)
327 *c = boot_cpu_data;
328 c->cpu_index = id;
329 /*
330 * During boot time, CPU0 has this setup already. Save the info when
331 * bringing up an AP.
332 */
333 identify_secondary_cpu(c);
334 c->initialized = true;
335}
336
337static bool
338topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
339{
340 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
341
342 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
343}
344
345static bool
346topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
347{
348 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
349
350 return !WARN_ONCE(!topology_same_node(c, o),
351 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
352 "[node: %d != %d]. Ignoring dependency.\n",
353 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
354}
355
356#define link_mask(mfunc, c1, c2) \
357do { \
358 cpumask_set_cpu((c1), mfunc(c2)); \
359 cpumask_set_cpu((c2), mfunc(c1)); \
360} while (0)
361
362static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
363{
364 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
365 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
366
367 if (c->topo.pkg_id == o->topo.pkg_id &&
368 c->topo.die_id == o->topo.die_id &&
369 c->topo.amd_node_id == o->topo.amd_node_id &&
370 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) {
371 if (c->topo.core_id == o->topo.core_id)
372 return topology_sane(c, o, "smt");
373
374 if ((c->topo.cu_id != 0xff) &&
375 (o->topo.cu_id != 0xff) &&
376 (c->topo.cu_id == o->topo.cu_id))
377 return topology_sane(c, o, "smt");
378 }
379
380 } else if (c->topo.pkg_id == o->topo.pkg_id &&
381 c->topo.die_id == o->topo.die_id &&
382 c->topo.core_id == o->topo.core_id) {
383 return topology_sane(c, o, "smt");
384 }
385
386 return false;
387}
388
389static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
390{
391 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id)
392 return false;
393
394 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1)
395 return c->topo.amd_node_id == o->topo.amd_node_id;
396
397 return true;
398}
399
400static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
401{
402 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
403
404 /* If the arch didn't set up l2c_id, fall back to SMT */
405 if (per_cpu_l2c_id(cpu1) == BAD_APICID)
406 return match_smt(c, o);
407
408 /* Do not match if L2 cache id does not match: */
409 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2))
410 return false;
411
412 return topology_sane(c, o, "l2c");
413}
414
415/*
416 * Unlike the other levels, we do not enforce keeping a
417 * multicore group inside a NUMA node. If this happens, we will
418 * discard the MC level of the topology later.
419 */
420static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
421{
422 if (c->topo.pkg_id == o->topo.pkg_id)
423 return true;
424 return false;
425}
426
427/*
428 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
429 *
430 * Any Intel CPU that has multiple nodes per package and does not
431 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
432 *
433 * When in SNC mode, these CPUs enumerate an LLC that is shared
434 * by multiple NUMA nodes. The LLC is shared for off-package data
435 * access but private to the NUMA node (half of the package) for
436 * on-package access. CPUID (the source of the information about
437 * the LLC) can only enumerate the cache as shared or unshared,
438 * but not this particular configuration.
439 */
440
441static const struct x86_cpu_id intel_cod_cpu[] = {
442 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */
443 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */
444 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */
445 {}
446};
447
448static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
449{
450 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
451 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
452 bool intel_snc = id && id->driver_data;
453
454 /* Do not match if we do not have a valid APICID for cpu: */
455 if (per_cpu_llc_id(cpu1) == BAD_APICID)
456 return false;
457
458 /* Do not match if LLC id does not match: */
459 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2))
460 return false;
461
462 /*
463 * Allow the SNC topology without warning. Return of false
464 * means 'c' does not share the LLC of 'o'. This will be
465 * reflected to userspace.
466 */
467 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
468 return false;
469
470 return topology_sane(c, o, "llc");
471}
472
473
474static inline int x86_sched_itmt_flags(void)
475{
476 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
477}
478
479#ifdef CONFIG_SCHED_MC
480static int x86_core_flags(void)
481{
482 return cpu_core_flags() | x86_sched_itmt_flags();
483}
484#endif
485#ifdef CONFIG_SCHED_SMT
486static int x86_smt_flags(void)
487{
488 return cpu_smt_flags();
489}
490#endif
491#ifdef CONFIG_SCHED_CLUSTER
492static int x86_cluster_flags(void)
493{
494 return cpu_cluster_flags() | x86_sched_itmt_flags();
495}
496#endif
497
498/*
499 * Set if a package/die has multiple NUMA nodes inside.
500 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
501 * Sub-NUMA Clustering have this.
502 */
503static bool x86_has_numa_in_package;
504
505static struct sched_domain_topology_level x86_topology[6];
506
507static void __init build_sched_topology(void)
508{
509 int i = 0;
510
511#ifdef CONFIG_SCHED_SMT
512 x86_topology[i++] = (struct sched_domain_topology_level){
513 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
514 };
515#endif
516#ifdef CONFIG_SCHED_CLUSTER
517 x86_topology[i++] = (struct sched_domain_topology_level){
518 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
519 };
520#endif
521#ifdef CONFIG_SCHED_MC
522 x86_topology[i++] = (struct sched_domain_topology_level){
523 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
524 };
525#endif
526 /*
527 * When there is NUMA topology inside the package skip the PKG domain
528 * since the NUMA domains will auto-magically create the right spanning
529 * domains based on the SLIT.
530 */
531 if (!x86_has_numa_in_package) {
532 x86_topology[i++] = (struct sched_domain_topology_level){
533 cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG)
534 };
535 }
536
537 /*
538 * There must be one trailing NULL entry left.
539 */
540 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
541
542 set_sched_topology(x86_topology);
543}
544
545void set_cpu_sibling_map(int cpu)
546{
547 bool has_smt = __max_threads_per_core > 1;
548 bool has_mp = has_smt || topology_num_cores_per_package() > 1;
549 struct cpuinfo_x86 *c = &cpu_data(cpu);
550 struct cpuinfo_x86 *o;
551 int i, threads;
552
553 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
554
555 if (!has_mp) {
556 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
557 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
558 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
559 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
560 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
561 c->booted_cores = 1;
562 return;
563 }
564
565 for_each_cpu(i, cpu_sibling_setup_mask) {
566 o = &cpu_data(i);
567
568 if (match_pkg(c, o) && !topology_same_node(c, o))
569 x86_has_numa_in_package = true;
570
571 if ((i == cpu) || (has_smt && match_smt(c, o)))
572 link_mask(topology_sibling_cpumask, cpu, i);
573
574 if ((i == cpu) || (has_mp && match_llc(c, o)))
575 link_mask(cpu_llc_shared_mask, cpu, i);
576
577 if ((i == cpu) || (has_mp && match_l2c(c, o)))
578 link_mask(cpu_l2c_shared_mask, cpu, i);
579
580 if ((i == cpu) || (has_mp && match_die(c, o)))
581 link_mask(topology_die_cpumask, cpu, i);
582 }
583
584 threads = cpumask_weight(topology_sibling_cpumask(cpu));
585 if (threads > __max_smt_threads)
586 __max_smt_threads = threads;
587
588 for_each_cpu(i, topology_sibling_cpumask(cpu))
589 cpu_data(i).smt_active = threads > 1;
590
591 /*
592 * This needs a separate iteration over the cpus because we rely on all
593 * topology_sibling_cpumask links to be set-up.
594 */
595 for_each_cpu(i, cpu_sibling_setup_mask) {
596 o = &cpu_data(i);
597
598 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
599 link_mask(topology_core_cpumask, cpu, i);
600
601 /*
602 * Does this new cpu bringup a new core?
603 */
604 if (threads == 1) {
605 /*
606 * for each core in package, increment
607 * the booted_cores for this new cpu
608 */
609 if (cpumask_first(
610 topology_sibling_cpumask(i)) == i)
611 c->booted_cores++;
612 /*
613 * increment the core count for all
614 * the other cpus in this package
615 */
616 if (i != cpu)
617 cpu_data(i).booted_cores++;
618 } else if (i != cpu && !c->booted_cores)
619 c->booted_cores = cpu_data(i).booted_cores;
620 }
621 }
622}
623
624/* maps the cpu to the sched domain representing multi-core */
625const struct cpumask *cpu_coregroup_mask(int cpu)
626{
627 return cpu_llc_shared_mask(cpu);
628}
629
630const struct cpumask *cpu_clustergroup_mask(int cpu)
631{
632 return cpu_l2c_shared_mask(cpu);
633}
634EXPORT_SYMBOL_GPL(cpu_clustergroup_mask);
635
636static void impress_friends(void)
637{
638 int cpu;
639 unsigned long bogosum = 0;
640 /*
641 * Allow the user to impress friends.
642 */
643 pr_debug("Before bogomips\n");
644 for_each_online_cpu(cpu)
645 bogosum += cpu_data(cpu).loops_per_jiffy;
646
647 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
648 num_online_cpus(),
649 bogosum/(500000/HZ),
650 (bogosum/(5000/HZ))%100);
651
652 pr_debug("Before bogocount - setting activated=1\n");
653}
654
655/*
656 * The Multiprocessor Specification 1.4 (1997) example code suggests
657 * that there should be a 10ms delay between the BSP asserting INIT
658 * and de-asserting INIT, when starting a remote processor.
659 * But that slows boot and resume on modern processors, which include
660 * many cores and don't require that delay.
661 *
662 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
663 * Modern processor families are quirked to remove the delay entirely.
664 */
665#define UDELAY_10MS_DEFAULT 10000
666
667static unsigned int init_udelay = UINT_MAX;
668
669static int __init cpu_init_udelay(char *str)
670{
671 get_option(&str, &init_udelay);
672
673 return 0;
674}
675early_param("cpu_init_udelay", cpu_init_udelay);
676
677static void __init smp_quirk_init_udelay(void)
678{
679 /* if cmdline changed it from default, leave it alone */
680 if (init_udelay != UINT_MAX)
681 return;
682
683 /* if modern processor, use no delay */
684 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
685 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
686 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
687 init_udelay = 0;
688 return;
689 }
690 /* else, use legacy delay */
691 init_udelay = UDELAY_10MS_DEFAULT;
692}
693
694/*
695 * Wake up AP by INIT, INIT, STARTUP sequence.
696 */
697static void send_init_sequence(u32 phys_apicid)
698{
699 int maxlvt = lapic_get_maxlvt();
700
701 /* Be paranoid about clearing APIC errors. */
702 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
703 /* Due to the Pentium erratum 3AP. */
704 if (maxlvt > 3)
705 apic_write(APIC_ESR, 0);
706 apic_read(APIC_ESR);
707 }
708
709 /* Assert INIT on the target CPU */
710 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
711 safe_apic_wait_icr_idle();
712
713 udelay(init_udelay);
714
715 /* Deassert INIT on the target CPU */
716 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
717 safe_apic_wait_icr_idle();
718}
719
720/*
721 * Wake up AP by INIT, INIT, STARTUP sequence.
722 */
723static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip)
724{
725 unsigned long send_status = 0, accept_status = 0;
726 int num_starts, j, maxlvt;
727
728 preempt_disable();
729 maxlvt = lapic_get_maxlvt();
730 send_init_sequence(phys_apicid);
731
732 mb();
733
734 /*
735 * Should we send STARTUP IPIs ?
736 *
737 * Determine this based on the APIC version.
738 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
739 */
740 if (APIC_INTEGRATED(boot_cpu_apic_version))
741 num_starts = 2;
742 else
743 num_starts = 0;
744
745 /*
746 * Run STARTUP IPI loop.
747 */
748 pr_debug("#startup loops: %d\n", num_starts);
749
750 for (j = 1; j <= num_starts; j++) {
751 pr_debug("Sending STARTUP #%d\n", j);
752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
753 apic_write(APIC_ESR, 0);
754 apic_read(APIC_ESR);
755 pr_debug("After apic_write\n");
756
757 /*
758 * STARTUP IPI
759 */
760
761 /* Target chip */
762 /* Boot on the stack */
763 /* Kick the second */
764 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
765 phys_apicid);
766
767 /*
768 * Give the other CPU some time to accept the IPI.
769 */
770 if (init_udelay == 0)
771 udelay(10);
772 else
773 udelay(300);
774
775 pr_debug("Startup point 1\n");
776
777 pr_debug("Waiting for send to finish...\n");
778 send_status = safe_apic_wait_icr_idle();
779
780 /*
781 * Give the other CPU some time to accept the IPI.
782 */
783 if (init_udelay == 0)
784 udelay(10);
785 else
786 udelay(200);
787
788 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
789 apic_write(APIC_ESR, 0);
790 accept_status = (apic_read(APIC_ESR) & 0xEF);
791 if (send_status || accept_status)
792 break;
793 }
794 pr_debug("After Startup\n");
795
796 if (send_status)
797 pr_err("APIC never delivered???\n");
798 if (accept_status)
799 pr_err("APIC delivery error (%lx)\n", accept_status);
800
801 preempt_enable();
802 return (send_status | accept_status);
803}
804
805/* reduce the number of lines printed when booting a large cpu count system */
806static void announce_cpu(int cpu, int apicid)
807{
808 static int width, node_width, first = 1;
809 static int current_node = NUMA_NO_NODE;
810 int node = early_cpu_to_node(cpu);
811
812 if (!width)
813 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
814
815 if (!node_width)
816 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
817
818 if (system_state < SYSTEM_RUNNING) {
819 if (first)
820 pr_info("x86: Booting SMP configuration:\n");
821
822 if (node != current_node) {
823 if (current_node > (-1))
824 pr_cont("\n");
825 current_node = node;
826
827 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
828 node_width - num_digits(node), " ", node);
829 }
830
831 /* Add padding for the BSP */
832 if (first)
833 pr_cont("%*s", width + 1, " ");
834 first = 0;
835
836 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
837 } else
838 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
839 node, cpu, apicid);
840}
841
842int common_cpu_up(unsigned int cpu, struct task_struct *idle)
843{
844 int ret;
845
846 /* Just in case we booted with a single CPU. */
847 alternatives_enable_smp();
848
849 per_cpu(pcpu_hot.current_task, cpu) = idle;
850 cpu_init_stack_canary(cpu, idle);
851
852 /* Initialize the interrupt stack(s) */
853 ret = irq_init_percpu_irqstack(cpu);
854 if (ret)
855 return ret;
856
857#ifdef CONFIG_X86_32
858 /* Stack for startup_32 can be just as for start_secondary onwards */
859 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
860#endif
861 return 0;
862}
863
864/*
865 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
866 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
867 * Returns zero if startup was successfully sent, else error code from
868 * ->wakeup_secondary_cpu.
869 */
870static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle)
871{
872 unsigned long start_ip = real_mode_header->trampoline_start;
873 int ret;
874
875#ifdef CONFIG_X86_64
876 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
877 if (apic->wakeup_secondary_cpu_64)
878 start_ip = real_mode_header->trampoline_start64;
879#endif
880 idle->thread.sp = (unsigned long)task_pt_regs(idle);
881 initial_code = (unsigned long)start_secondary;
882
883 if (IS_ENABLED(CONFIG_X86_32)) {
884 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
885 initial_stack = idle->thread.sp;
886 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
887 smpboot_control = cpu;
888 }
889
890 /* Enable the espfix hack for this CPU */
891 init_espfix_ap(cpu);
892
893 /* So we see what's up */
894 announce_cpu(cpu, apicid);
895
896 /*
897 * This grunge runs the startup process for
898 * the targeted processor.
899 */
900 if (x86_platform.legacy.warm_reset) {
901
902 pr_debug("Setting warm reset code and vector.\n");
903
904 smpboot_setup_warm_reset_vector(start_ip);
905 /*
906 * Be paranoid about clearing APIC errors.
907 */
908 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
909 apic_write(APIC_ESR, 0);
910 apic_read(APIC_ESR);
911 }
912 }
913
914 smp_mb();
915
916 /*
917 * Wake up a CPU in difference cases:
918 * - Use a method from the APIC driver if one defined, with wakeup
919 * straight to 64-bit mode preferred over wakeup to RM.
920 * Otherwise,
921 * - Use an INIT boot APIC message
922 */
923 if (apic->wakeup_secondary_cpu_64)
924 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
925 else if (apic->wakeup_secondary_cpu)
926 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
927 else
928 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
929
930 /* If the wakeup mechanism failed, cleanup the warm reset vector */
931 if (ret)
932 arch_cpuhp_cleanup_kick_cpu(cpu);
933 return ret;
934}
935
936int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
937{
938 u32 apicid = apic->cpu_present_to_apicid(cpu);
939 int err;
940
941 lockdep_assert_irqs_enabled();
942
943 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
944
945 if (apicid == BAD_APICID || !apic_id_valid(apicid)) {
946 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid);
947 return -EINVAL;
948 }
949
950 if (!test_bit(apicid, phys_cpu_present_map)) {
951 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid);
952 return -EINVAL;
953 }
954
955 /*
956 * Save current MTRR state in case it was changed since early boot
957 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
958 */
959 mtrr_save_state();
960
961 /* the FPU context is blank, nobody can own it */
962 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
963
964 err = common_cpu_up(cpu, tidle);
965 if (err)
966 return err;
967
968 err = do_boot_cpu(apicid, cpu, tidle);
969 if (err)
970 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
971
972 return err;
973}
974
975int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
976{
977 return smp_ops.kick_ap_alive(cpu, tidle);
978}
979
980void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
981{
982 /* Cleanup possible dangling ends... */
983 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
984 smpboot_restore_warm_reset_vector();
985}
986
987void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
988{
989 if (smp_ops.cleanup_dead_cpu)
990 smp_ops.cleanup_dead_cpu(cpu);
991
992 if (system_state == SYSTEM_RUNNING)
993 pr_info("CPU %u is now offline\n", cpu);
994}
995
996void arch_cpuhp_sync_state_poll(void)
997{
998 if (smp_ops.poll_sync_state)
999 smp_ops.poll_sync_state();
1000}
1001
1002/**
1003 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1004 */
1005void __init arch_disable_smp_support(void)
1006{
1007 disable_ioapic_support();
1008}
1009
1010/*
1011 * Fall back to non SMP mode after errors.
1012 *
1013 * RED-PEN audit/test this more. I bet there is more state messed up here.
1014 */
1015static __init void disable_smp(void)
1016{
1017 pr_info("SMP disabled\n");
1018
1019 disable_ioapic_support();
1020 topology_reset_possible_cpus_up();
1021
1022 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1023 cpumask_set_cpu(0, topology_core_cpumask(0));
1024 cpumask_set_cpu(0, topology_die_cpumask(0));
1025}
1026
1027void __init smp_prepare_cpus_common(void)
1028{
1029 unsigned int cpu, node;
1030
1031 /* Mark all except the boot CPU as hotpluggable */
1032 for_each_possible_cpu(cpu) {
1033 if (cpu)
1034 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids;
1035 }
1036
1037 for_each_possible_cpu(cpu) {
1038 node = cpu_to_node(cpu);
1039
1040 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node);
1041 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node);
1042 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node);
1043 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node);
1044 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node);
1045 }
1046
1047 set_cpu_sibling_map(0);
1048}
1049
1050void __init smp_prepare_boot_cpu(void)
1051{
1052 smp_ops.smp_prepare_boot_cpu();
1053}
1054
1055#ifdef CONFIG_X86_64
1056/* Establish whether parallel bringup can be supported. */
1057bool __init arch_cpuhp_init_parallel_bringup(void)
1058{
1059 if (!x86_cpuinit.parallel_bringup) {
1060 pr_info("Parallel CPU startup disabled by the platform\n");
1061 return false;
1062 }
1063
1064 smpboot_control = STARTUP_READ_APICID;
1065 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1066 return true;
1067}
1068#endif
1069
1070/*
1071 * Prepare for SMP bootup.
1072 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1073 * for common interface support.
1074 */
1075void __init native_smp_prepare_cpus(unsigned int max_cpus)
1076{
1077 smp_prepare_cpus_common();
1078
1079 switch (apic_intr_mode) {
1080 case APIC_PIC:
1081 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1082 disable_smp();
1083 return;
1084 case APIC_SYMMETRIC_IO_NO_ROUTING:
1085 disable_smp();
1086 /* Setup local timer */
1087 x86_init.timers.setup_percpu_clockev();
1088 return;
1089 case APIC_VIRTUAL_WIRE:
1090 case APIC_SYMMETRIC_IO:
1091 break;
1092 }
1093
1094 /* Setup local timer */
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 pr_info("CPU0: ");
1098 print_cpu_info(&cpu_data(0));
1099
1100 uv_system_init();
1101
1102 smp_quirk_init_udelay();
1103
1104 speculative_store_bypass_ht_init();
1105
1106 snp_set_wakeup_secondary_cpu();
1107}
1108
1109void arch_thaw_secondary_cpus_begin(void)
1110{
1111 set_cache_aps_delayed_init(true);
1112}
1113
1114void arch_thaw_secondary_cpus_end(void)
1115{
1116 cache_aps_init();
1117}
1118
1119/*
1120 * Early setup to make printk work.
1121 */
1122void __init native_smp_prepare_boot_cpu(void)
1123{
1124 int me = smp_processor_id();
1125
1126 /* SMP handles this from setup_per_cpu_areas() */
1127 if (!IS_ENABLED(CONFIG_SMP))
1128 switch_gdt_and_percpu_base(me);
1129
1130 native_pv_lock_init();
1131}
1132
1133void __init native_smp_cpus_done(unsigned int max_cpus)
1134{
1135 pr_debug("Boot done\n");
1136
1137 build_sched_topology();
1138 nmi_selftest();
1139 impress_friends();
1140 cache_aps_init();
1141}
1142
1143/* correctly size the local cpu masks */
1144void __init setup_cpu_local_masks(void)
1145{
1146 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1147}
1148
1149#ifdef CONFIG_HOTPLUG_CPU
1150
1151/* Recompute SMT state for all CPUs on offline */
1152static void recompute_smt_state(void)
1153{
1154 int max_threads, cpu;
1155
1156 max_threads = 0;
1157 for_each_online_cpu (cpu) {
1158 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1159
1160 if (threads > max_threads)
1161 max_threads = threads;
1162 }
1163 __max_smt_threads = max_threads;
1164}
1165
1166static void remove_siblinginfo(int cpu)
1167{
1168 int sibling;
1169 struct cpuinfo_x86 *c = &cpu_data(cpu);
1170
1171 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1172 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1173 /*/
1174 * last thread sibling in this cpu core going down
1175 */
1176 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1177 cpu_data(sibling).booted_cores--;
1178 }
1179
1180 for_each_cpu(sibling, topology_die_cpumask(cpu))
1181 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1182
1183 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1184 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1185 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1186 cpu_data(sibling).smt_active = false;
1187 }
1188
1189 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1190 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1191 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1192 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1193 cpumask_clear(cpu_llc_shared_mask(cpu));
1194 cpumask_clear(cpu_l2c_shared_mask(cpu));
1195 cpumask_clear(topology_sibling_cpumask(cpu));
1196 cpumask_clear(topology_core_cpumask(cpu));
1197 cpumask_clear(topology_die_cpumask(cpu));
1198 c->topo.core_id = 0;
1199 c->booted_cores = 0;
1200 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1201 recompute_smt_state();
1202}
1203
1204static void remove_cpu_from_maps(int cpu)
1205{
1206 set_cpu_online(cpu, false);
1207 numa_remove_cpu(cpu);
1208}
1209
1210void cpu_disable_common(void)
1211{
1212 int cpu = smp_processor_id();
1213
1214 remove_siblinginfo(cpu);
1215
1216 /* It's now safe to remove this processor from the online map */
1217 lock_vector_lock();
1218 remove_cpu_from_maps(cpu);
1219 unlock_vector_lock();
1220 fixup_irqs();
1221 lapic_offline();
1222}
1223
1224int native_cpu_disable(void)
1225{
1226 int ret;
1227
1228 ret = lapic_can_unplug_cpu();
1229 if (ret)
1230 return ret;
1231
1232 cpu_disable_common();
1233
1234 /*
1235 * Disable the local APIC. Otherwise IPI broadcasts will reach
1236 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1237 * messages.
1238 *
1239 * Disabling the APIC must happen after cpu_disable_common()
1240 * which invokes fixup_irqs().
1241 *
1242 * Disabling the APIC preserves already set bits in IRR, but
1243 * an interrupt arriving after disabling the local APIC does not
1244 * set the corresponding IRR bit.
1245 *
1246 * fixup_irqs() scans IRR for set bits so it can raise a not
1247 * yet handled interrupt on the new destination CPU via an IPI
1248 * but obviously it can't do so for IRR bits which are not set.
1249 * IOW, interrupts arriving after disabling the local APIC will
1250 * be lost.
1251 */
1252 apic_soft_disable();
1253
1254 return 0;
1255}
1256
1257void play_dead_common(void)
1258{
1259 idle_task_exit();
1260
1261 cpuhp_ap_report_dead();
1262
1263 local_irq_disable();
1264}
1265
1266/*
1267 * We need to flush the caches before going to sleep, lest we have
1268 * dirty data in our caches when we come back up.
1269 */
1270static inline void mwait_play_dead(void)
1271{
1272 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1273 unsigned int eax, ebx, ecx, edx;
1274 unsigned int highest_cstate = 0;
1275 unsigned int highest_subcstate = 0;
1276 int i;
1277
1278 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1279 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1280 return;
1281 if (!this_cpu_has(X86_FEATURE_MWAIT))
1282 return;
1283 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1284 return;
1285 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1286 return;
1287
1288 eax = CPUID_MWAIT_LEAF;
1289 ecx = 0;
1290 native_cpuid(&eax, &ebx, &ecx, &edx);
1291
1292 /*
1293 * eax will be 0 if EDX enumeration is not valid.
1294 * Initialized below to cstate, sub_cstate value when EDX is valid.
1295 */
1296 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1297 eax = 0;
1298 } else {
1299 edx >>= MWAIT_SUBSTATE_SIZE;
1300 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1301 if (edx & MWAIT_SUBSTATE_MASK) {
1302 highest_cstate = i;
1303 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1304 }
1305 }
1306 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1307 (highest_subcstate - 1);
1308 }
1309
1310 /* Set up state for the kexec() hack below */
1311 md->status = CPUDEAD_MWAIT_WAIT;
1312 md->control = CPUDEAD_MWAIT_WAIT;
1313
1314 wbinvd();
1315
1316 while (1) {
1317 /*
1318 * The CLFLUSH is a workaround for erratum AAI65 for
1319 * the Xeon 7400 series. It's not clear it is actually
1320 * needed, but it should be harmless in either case.
1321 * The WBINVD is insufficient due to the spurious-wakeup
1322 * case where we return around the loop.
1323 */
1324 mb();
1325 clflush(md);
1326 mb();
1327 __monitor(md, 0, 0);
1328 mb();
1329 __mwait(eax, 0);
1330
1331 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1332 /*
1333 * Kexec is about to happen. Don't go back into mwait() as
1334 * the kexec kernel might overwrite text and data including
1335 * page tables and stack. So mwait() would resume when the
1336 * monitor cache line is written to and then the CPU goes
1337 * south due to overwritten text, page tables and stack.
1338 *
1339 * Note: This does _NOT_ protect against a stray MCE, NMI,
1340 * SMI. They will resume execution at the instruction
1341 * following the HLT instruction and run into the problem
1342 * which this is trying to prevent.
1343 */
1344 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1345 while(1)
1346 native_halt();
1347 }
1348 }
1349}
1350
1351/*
1352 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1353 * mwait_play_dead().
1354 */
1355void smp_kick_mwait_play_dead(void)
1356{
1357 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1358 struct mwait_cpu_dead *md;
1359 unsigned int cpu, i;
1360
1361 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1362 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1363
1364 /* Does it sit in mwait_play_dead() ? */
1365 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1366 continue;
1367
1368 /* Wait up to 5ms */
1369 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1370 /* Bring it out of mwait */
1371 WRITE_ONCE(md->control, newstate);
1372 udelay(5);
1373 }
1374
1375 if (READ_ONCE(md->status) != newstate)
1376 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1377 }
1378}
1379
1380void __noreturn hlt_play_dead(void)
1381{
1382 if (__this_cpu_read(cpu_info.x86) >= 4)
1383 wbinvd();
1384
1385 while (1)
1386 native_halt();
1387}
1388
1389/*
1390 * native_play_dead() is essentially a __noreturn function, but it can't
1391 * be marked as such as the compiler may complain about it.
1392 */
1393void native_play_dead(void)
1394{
1395 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
1396 __update_spec_ctrl(0);
1397
1398 play_dead_common();
1399 tboot_shutdown(TB_SHUTDOWN_WFS);
1400
1401 mwait_play_dead();
1402 if (cpuidle_play_dead())
1403 hlt_play_dead();
1404}
1405
1406#else /* ... !CONFIG_HOTPLUG_CPU */
1407int native_cpu_disable(void)
1408{
1409 return -ENOSYS;
1410}
1411
1412void native_play_dead(void)
1413{
1414 BUG();
1415}
1416
1417#endif
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/export.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/realmode.h>
62#include <asm/cpu.h>
63#include <asm/numa.h>
64#include <asm/pgtable.h>
65#include <asm/tlbflush.h>
66#include <asm/mtrr.h>
67#include <asm/mwait.h>
68#include <asm/apic.h>
69#include <asm/io_apic.h>
70#include <asm/fpu/internal.h>
71#include <asm/setup.h>
72#include <asm/uv/uv.h>
73#include <linux/mc146818rtc.h>
74#include <asm/i8259.h>
75#include <asm/realmode.h>
76#include <asm/misc.h>
77
78/* Number of siblings per CPU package */
79int smp_num_siblings = 1;
80EXPORT_SYMBOL(smp_num_siblings);
81
82/* Last level cache ID of each logical CPU */
83DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
84
85/* representing HT siblings of each logical CPU */
86DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
88
89/* representing HT and core siblings of each logical CPU */
90DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91EXPORT_PER_CPU_SYMBOL(cpu_core_map);
92
93DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
94
95/* Per CPU bogomips and other parameters */
96DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
97EXPORT_PER_CPU_SYMBOL(cpu_info);
98
99/* Logical package management. We might want to allocate that dynamically */
100static int *physical_to_logical_pkg __read_mostly;
101static unsigned long *physical_package_map __read_mostly;;
102static unsigned int max_physical_pkg_id __read_mostly;
103unsigned int __max_logical_packages __read_mostly;
104EXPORT_SYMBOL(__max_logical_packages);
105static unsigned int logical_packages __read_mostly;
106
107/* Maximum number of SMT threads on any online core */
108int __max_smt_threads __read_mostly;
109
110/* Flag to indicate if a complete sched domain rebuild is required */
111bool x86_topology_update;
112
113int arch_update_cpu_topology(void)
114{
115 int retval = x86_topology_update;
116
117 x86_topology_update = false;
118 return retval;
119}
120
121static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
122{
123 unsigned long flags;
124
125 spin_lock_irqsave(&rtc_lock, flags);
126 CMOS_WRITE(0xa, 0xf);
127 spin_unlock_irqrestore(&rtc_lock, flags);
128 local_flush_tlb();
129 pr_debug("1.\n");
130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
131 start_eip >> 4;
132 pr_debug("2.\n");
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
134 start_eip & 0xf;
135 pr_debug("3.\n");
136}
137
138static inline void smpboot_restore_warm_reset_vector(void)
139{
140 unsigned long flags;
141
142 /*
143 * Install writable page 0 entry to set BIOS data area.
144 */
145 local_flush_tlb();
146
147 /*
148 * Paranoid: Set warm reset code and vector here back
149 * to default values.
150 */
151 spin_lock_irqsave(&rtc_lock, flags);
152 CMOS_WRITE(0, 0xf);
153 spin_unlock_irqrestore(&rtc_lock, flags);
154
155 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
156}
157
158/*
159 * Report back to the Boot Processor during boot time or to the caller processor
160 * during CPU online.
161 */
162static void smp_callin(void)
163{
164 int cpuid, phys_id;
165
166 /*
167 * If waken up by an INIT in an 82489DX configuration
168 * cpu_callout_mask guarantees we don't get here before
169 * an INIT_deassert IPI reaches our local APIC, so it is
170 * now safe to touch our local APIC.
171 */
172 cpuid = smp_processor_id();
173
174 /*
175 * (This works even if the APIC is not enabled.)
176 */
177 phys_id = read_apic_id();
178
179 /*
180 * the boot CPU has finished the init stage and is spinning
181 * on callin_map until we finish. We are free to set up this
182 * CPU, first the APIC. (this is probably redundant on most
183 * boards)
184 */
185 apic_ap_setup();
186
187 /*
188 * Save our processor parameters. Note: this information
189 * is needed for clock calibration.
190 */
191 smp_store_cpu_info(cpuid);
192
193 /*
194 * Get our bogomips.
195 * Update loops_per_jiffy in cpu_data. Previous call to
196 * smp_store_cpu_info() stored a value that is close but not as
197 * accurate as the value just calculated.
198 */
199 calibrate_delay();
200 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
201 pr_debug("Stack at about %p\n", &cpuid);
202
203 /*
204 * This must be done before setting cpu_online_mask
205 * or calling notify_cpu_starting.
206 */
207 set_cpu_sibling_map(raw_smp_processor_id());
208 wmb();
209
210 notify_cpu_starting(cpuid);
211
212 /*
213 * Allow the master to continue.
214 */
215 cpumask_set_cpu(cpuid, cpu_callin_mask);
216}
217
218static int cpu0_logical_apicid;
219static int enable_start_cpu0;
220/*
221 * Activate a secondary processor.
222 */
223static void notrace start_secondary(void *unused)
224{
225 /*
226 * Don't put *anything* before cpu_init(), SMP booting is too
227 * fragile that we want to limit the things done here to the
228 * most necessary things.
229 */
230 cpu_init();
231 x86_cpuinit.early_percpu_clock_init();
232 preempt_disable();
233 smp_callin();
234
235 enable_start_cpu0 = 0;
236
237#ifdef CONFIG_X86_32
238 /* switch away from the initial page table */
239 load_cr3(swapper_pg_dir);
240 __flush_tlb_all();
241#endif
242
243 /* otherwise gcc will move up smp_processor_id before the cpu_init */
244 barrier();
245 /*
246 * Check TSC synchronization with the BP:
247 */
248 check_tsc_sync_target();
249
250 /*
251 * Lock vector_lock and initialize the vectors on this cpu
252 * before setting the cpu online. We must set it online with
253 * vector_lock held to prevent a concurrent setup/teardown
254 * from seeing a half valid vector space.
255 */
256 lock_vector_lock();
257 setup_vector_irq(smp_processor_id());
258 set_cpu_online(smp_processor_id(), true);
259 unlock_vector_lock();
260 cpu_set_state_online(smp_processor_id());
261 x86_platform.nmi_init();
262
263 /* enable local interrupts */
264 local_irq_enable();
265
266 /* to prevent fake stack check failure in clock setup */
267 boot_init_stack_canary();
268
269 x86_cpuinit.setup_percpu_clockev();
270
271 wmb();
272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
273}
274
275/**
276 * topology_update_package_map - Update the physical to logical package map
277 * @pkg: The physical package id as retrieved via CPUID
278 * @cpu: The cpu for which this is updated
279 */
280int topology_update_package_map(unsigned int pkg, unsigned int cpu)
281{
282 unsigned int new;
283
284 /* Called from early boot ? */
285 if (!physical_package_map)
286 return 0;
287
288 if (pkg >= max_physical_pkg_id)
289 return -EINVAL;
290
291 /* Set the logical package id */
292 if (test_and_set_bit(pkg, physical_package_map))
293 goto found;
294
295 if (logical_packages >= __max_logical_packages) {
296 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
297 logical_packages, cpu, __max_logical_packages);
298 return -ENOSPC;
299 }
300
301 new = logical_packages++;
302 if (new != pkg) {
303 pr_info("CPU %u Converting physical %u to logical package %u\n",
304 cpu, pkg, new);
305 }
306 physical_to_logical_pkg[pkg] = new;
307
308found:
309 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
310 return 0;
311}
312
313/**
314 * topology_phys_to_logical_pkg - Map a physical package id to a logical
315 *
316 * Returns logical package id or -1 if not found
317 */
318int topology_phys_to_logical_pkg(unsigned int phys_pkg)
319{
320 if (phys_pkg >= max_physical_pkg_id)
321 return -1;
322 return physical_to_logical_pkg[phys_pkg];
323}
324EXPORT_SYMBOL(topology_phys_to_logical_pkg);
325
326static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu)
327{
328 unsigned int ncpus;
329 size_t size;
330
331 /*
332 * Today neither Intel nor AMD support heterogenous systems. That
333 * might change in the future....
334 *
335 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
336 * computation, this won't actually work since some Intel BIOSes
337 * report inconsistent HT data when they disable HT.
338 *
339 * In particular, they reduce the APIC-IDs to only include the cores,
340 * but leave the CPUID topology to say there are (2) siblings.
341 * This means we don't know how many threads there will be until
342 * after the APIC enumeration.
343 *
344 * By not including this we'll sometimes over-estimate the number of
345 * logical packages by the amount of !present siblings, but this is
346 * still better than MAX_LOCAL_APIC.
347 *
348 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
349 * on the command line leading to a similar issue as the HT disable
350 * problem because the hyperthreads are usually enumerated after the
351 * primary cores.
352 */
353 ncpus = boot_cpu_data.x86_max_cores;
354 if (!ncpus) {
355 pr_warn("x86_max_cores == zero !?!?");
356 ncpus = 1;
357 }
358
359 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
360 logical_packages = 0;
361
362 /*
363 * Possibly larger than what we need as the number of apic ids per
364 * package can be smaller than the actual used apic ids.
365 */
366 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
367 size = max_physical_pkg_id * sizeof(unsigned int);
368 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
369 memset(physical_to_logical_pkg, 0xff, size);
370 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
371 physical_package_map = kzalloc(size, GFP_KERNEL);
372
373 pr_info("Max logical packages: %u\n", __max_logical_packages);
374
375 topology_update_package_map(c->phys_proc_id, cpu);
376}
377
378void __init smp_store_boot_cpu_info(void)
379{
380 int id = 0; /* CPU 0 */
381 struct cpuinfo_x86 *c = &cpu_data(id);
382
383 *c = boot_cpu_data;
384 c->cpu_index = id;
385 smp_init_package_map(c, id);
386}
387
388/*
389 * The bootstrap kernel entry code has set these up. Save them for
390 * a given CPU
391 */
392void smp_store_cpu_info(int id)
393{
394 struct cpuinfo_x86 *c = &cpu_data(id);
395
396 *c = boot_cpu_data;
397 c->cpu_index = id;
398 /*
399 * During boot time, CPU0 has this setup already. Save the info when
400 * bringing up AP or offlined CPU0.
401 */
402 identify_secondary_cpu(c);
403}
404
405static bool
406topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
407{
408 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
409
410 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
411}
412
413static bool
414topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
415{
416 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
417
418 return !WARN_ONCE(!topology_same_node(c, o),
419 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
420 "[node: %d != %d]. Ignoring dependency.\n",
421 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
422}
423
424#define link_mask(mfunc, c1, c2) \
425do { \
426 cpumask_set_cpu((c1), mfunc(c2)); \
427 cpumask_set_cpu((c2), mfunc(c1)); \
428} while (0)
429
430static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
431{
432 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
434
435 if (c->phys_proc_id == o->phys_proc_id &&
436 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
437 if (c->cpu_core_id == o->cpu_core_id)
438 return topology_sane(c, o, "smt");
439
440 if ((c->cu_id != 0xff) &&
441 (o->cu_id != 0xff) &&
442 (c->cu_id == o->cu_id))
443 return topology_sane(c, o, "smt");
444 }
445
446 } else if (c->phys_proc_id == o->phys_proc_id &&
447 c->cpu_core_id == o->cpu_core_id) {
448 return topology_sane(c, o, "smt");
449 }
450
451 return false;
452}
453
454static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
455{
456 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
457
458 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
459 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
460 return topology_sane(c, o, "llc");
461
462 return false;
463}
464
465/*
466 * Unlike the other levels, we do not enforce keeping a
467 * multicore group inside a NUMA node. If this happens, we will
468 * discard the MC level of the topology later.
469 */
470static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
471{
472 if (c->phys_proc_id == o->phys_proc_id)
473 return true;
474 return false;
475}
476
477#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
478static inline int x86_sched_itmt_flags(void)
479{
480 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
481}
482
483#ifdef CONFIG_SCHED_MC
484static int x86_core_flags(void)
485{
486 return cpu_core_flags() | x86_sched_itmt_flags();
487}
488#endif
489#ifdef CONFIG_SCHED_SMT
490static int x86_smt_flags(void)
491{
492 return cpu_smt_flags() | x86_sched_itmt_flags();
493}
494#endif
495#endif
496
497static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
498#ifdef CONFIG_SCHED_SMT
499 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
500#endif
501#ifdef CONFIG_SCHED_MC
502 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
503#endif
504 { NULL, },
505};
506
507static struct sched_domain_topology_level x86_topology[] = {
508#ifdef CONFIG_SCHED_SMT
509 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
510#endif
511#ifdef CONFIG_SCHED_MC
512 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
513#endif
514 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
515 { NULL, },
516};
517
518/*
519 * Set if a package/die has multiple NUMA nodes inside.
520 * AMD Magny-Cours and Intel Cluster-on-Die have this.
521 */
522static bool x86_has_numa_in_package;
523
524void set_cpu_sibling_map(int cpu)
525{
526 bool has_smt = smp_num_siblings > 1;
527 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
528 struct cpuinfo_x86 *c = &cpu_data(cpu);
529 struct cpuinfo_x86 *o;
530 int i, threads;
531
532 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
533
534 if (!has_mp) {
535 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
536 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
537 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
538 c->booted_cores = 1;
539 return;
540 }
541
542 for_each_cpu(i, cpu_sibling_setup_mask) {
543 o = &cpu_data(i);
544
545 if ((i == cpu) || (has_smt && match_smt(c, o)))
546 link_mask(topology_sibling_cpumask, cpu, i);
547
548 if ((i == cpu) || (has_mp && match_llc(c, o)))
549 link_mask(cpu_llc_shared_mask, cpu, i);
550
551 }
552
553 /*
554 * This needs a separate iteration over the cpus because we rely on all
555 * topology_sibling_cpumask links to be set-up.
556 */
557 for_each_cpu(i, cpu_sibling_setup_mask) {
558 o = &cpu_data(i);
559
560 if ((i == cpu) || (has_mp && match_die(c, o))) {
561 link_mask(topology_core_cpumask, cpu, i);
562
563 /*
564 * Does this new cpu bringup a new core?
565 */
566 if (cpumask_weight(
567 topology_sibling_cpumask(cpu)) == 1) {
568 /*
569 * for each core in package, increment
570 * the booted_cores for this new cpu
571 */
572 if (cpumask_first(
573 topology_sibling_cpumask(i)) == i)
574 c->booted_cores++;
575 /*
576 * increment the core count for all
577 * the other cpus in this package
578 */
579 if (i != cpu)
580 cpu_data(i).booted_cores++;
581 } else if (i != cpu && !c->booted_cores)
582 c->booted_cores = cpu_data(i).booted_cores;
583 }
584 if (match_die(c, o) && !topology_same_node(c, o))
585 x86_has_numa_in_package = true;
586 }
587
588 threads = cpumask_weight(topology_sibling_cpumask(cpu));
589 if (threads > __max_smt_threads)
590 __max_smt_threads = threads;
591}
592
593/* maps the cpu to the sched domain representing multi-core */
594const struct cpumask *cpu_coregroup_mask(int cpu)
595{
596 return cpu_llc_shared_mask(cpu);
597}
598
599static void impress_friends(void)
600{
601 int cpu;
602 unsigned long bogosum = 0;
603 /*
604 * Allow the user to impress friends.
605 */
606 pr_debug("Before bogomips\n");
607 for_each_possible_cpu(cpu)
608 if (cpumask_test_cpu(cpu, cpu_callout_mask))
609 bogosum += cpu_data(cpu).loops_per_jiffy;
610 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
611 num_online_cpus(),
612 bogosum/(500000/HZ),
613 (bogosum/(5000/HZ))%100);
614
615 pr_debug("Before bogocount - setting activated=1\n");
616}
617
618void __inquire_remote_apic(int apicid)
619{
620 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
621 const char * const names[] = { "ID", "VERSION", "SPIV" };
622 int timeout;
623 u32 status;
624
625 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
626
627 for (i = 0; i < ARRAY_SIZE(regs); i++) {
628 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
629
630 /*
631 * Wait for idle.
632 */
633 status = safe_apic_wait_icr_idle();
634 if (status)
635 pr_cont("a previous APIC delivery may have failed\n");
636
637 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
638
639 timeout = 0;
640 do {
641 udelay(100);
642 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
643 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
644
645 switch (status) {
646 case APIC_ICR_RR_VALID:
647 status = apic_read(APIC_RRR);
648 pr_cont("%08x\n", status);
649 break;
650 default:
651 pr_cont("failed\n");
652 }
653 }
654}
655
656/*
657 * The Multiprocessor Specification 1.4 (1997) example code suggests
658 * that there should be a 10ms delay between the BSP asserting INIT
659 * and de-asserting INIT, when starting a remote processor.
660 * But that slows boot and resume on modern processors, which include
661 * many cores and don't require that delay.
662 *
663 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
664 * Modern processor families are quirked to remove the delay entirely.
665 */
666#define UDELAY_10MS_DEFAULT 10000
667
668static unsigned int init_udelay = UINT_MAX;
669
670static int __init cpu_init_udelay(char *str)
671{
672 get_option(&str, &init_udelay);
673
674 return 0;
675}
676early_param("cpu_init_udelay", cpu_init_udelay);
677
678static void __init smp_quirk_init_udelay(void)
679{
680 /* if cmdline changed it from default, leave it alone */
681 if (init_udelay != UINT_MAX)
682 return;
683
684 /* if modern processor, use no delay */
685 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
686 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
687 init_udelay = 0;
688 return;
689 }
690 /* else, use legacy delay */
691 init_udelay = UDELAY_10MS_DEFAULT;
692}
693
694/*
695 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
696 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
697 * won't ... remember to clear down the APIC, etc later.
698 */
699int
700wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
701{
702 unsigned long send_status, accept_status = 0;
703 int maxlvt;
704
705 /* Target chip */
706 /* Boot on the stack */
707 /* Kick the second */
708 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
709
710 pr_debug("Waiting for send to finish...\n");
711 send_status = safe_apic_wait_icr_idle();
712
713 /*
714 * Give the other CPU some time to accept the IPI.
715 */
716 udelay(200);
717 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
718 maxlvt = lapic_get_maxlvt();
719 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
720 apic_write(APIC_ESR, 0);
721 accept_status = (apic_read(APIC_ESR) & 0xEF);
722 }
723 pr_debug("NMI sent\n");
724
725 if (send_status)
726 pr_err("APIC never delivered???\n");
727 if (accept_status)
728 pr_err("APIC delivery error (%lx)\n", accept_status);
729
730 return (send_status | accept_status);
731}
732
733static int
734wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
735{
736 unsigned long send_status = 0, accept_status = 0;
737 int maxlvt, num_starts, j;
738
739 maxlvt = lapic_get_maxlvt();
740
741 /*
742 * Be paranoid about clearing APIC errors.
743 */
744 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
745 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
746 apic_write(APIC_ESR, 0);
747 apic_read(APIC_ESR);
748 }
749
750 pr_debug("Asserting INIT\n");
751
752 /*
753 * Turn INIT on target chip
754 */
755 /*
756 * Send IPI
757 */
758 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
759 phys_apicid);
760
761 pr_debug("Waiting for send to finish...\n");
762 send_status = safe_apic_wait_icr_idle();
763
764 udelay(init_udelay);
765
766 pr_debug("Deasserting INIT\n");
767
768 /* Target chip */
769 /* Send IPI */
770 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
771
772 pr_debug("Waiting for send to finish...\n");
773 send_status = safe_apic_wait_icr_idle();
774
775 mb();
776
777 /*
778 * Should we send STARTUP IPIs ?
779 *
780 * Determine this based on the APIC version.
781 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
782 */
783 if (APIC_INTEGRATED(boot_cpu_apic_version))
784 num_starts = 2;
785 else
786 num_starts = 0;
787
788 /*
789 * Run STARTUP IPI loop.
790 */
791 pr_debug("#startup loops: %d\n", num_starts);
792
793 for (j = 1; j <= num_starts; j++) {
794 pr_debug("Sending STARTUP #%d\n", j);
795 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
796 apic_write(APIC_ESR, 0);
797 apic_read(APIC_ESR);
798 pr_debug("After apic_write\n");
799
800 /*
801 * STARTUP IPI
802 */
803
804 /* Target chip */
805 /* Boot on the stack */
806 /* Kick the second */
807 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
808 phys_apicid);
809
810 /*
811 * Give the other CPU some time to accept the IPI.
812 */
813 if (init_udelay == 0)
814 udelay(10);
815 else
816 udelay(300);
817
818 pr_debug("Startup point 1\n");
819
820 pr_debug("Waiting for send to finish...\n");
821 send_status = safe_apic_wait_icr_idle();
822
823 /*
824 * Give the other CPU some time to accept the IPI.
825 */
826 if (init_udelay == 0)
827 udelay(10);
828 else
829 udelay(200);
830
831 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
832 apic_write(APIC_ESR, 0);
833 accept_status = (apic_read(APIC_ESR) & 0xEF);
834 if (send_status || accept_status)
835 break;
836 }
837 pr_debug("After Startup\n");
838
839 if (send_status)
840 pr_err("APIC never delivered???\n");
841 if (accept_status)
842 pr_err("APIC delivery error (%lx)\n", accept_status);
843
844 return (send_status | accept_status);
845}
846
847/* reduce the number of lines printed when booting a large cpu count system */
848static void announce_cpu(int cpu, int apicid)
849{
850 static int current_node = -1;
851 int node = early_cpu_to_node(cpu);
852 static int width, node_width;
853
854 if (!width)
855 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
856
857 if (!node_width)
858 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
859
860 if (cpu == 1)
861 printk(KERN_INFO "x86: Booting SMP configuration:\n");
862
863 if (system_state == SYSTEM_BOOTING) {
864 if (node != current_node) {
865 if (current_node > (-1))
866 pr_cont("\n");
867 current_node = node;
868
869 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
870 node_width - num_digits(node), " ", node);
871 }
872
873 /* Add padding for the BSP */
874 if (cpu == 1)
875 pr_cont("%*s", width + 1, " ");
876
877 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
878
879 } else
880 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
881 node, cpu, apicid);
882}
883
884static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
885{
886 int cpu;
887
888 cpu = smp_processor_id();
889 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
890 return NMI_HANDLED;
891
892 return NMI_DONE;
893}
894
895/*
896 * Wake up AP by INIT, INIT, STARTUP sequence.
897 *
898 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
899 * boot-strap code which is not a desired behavior for waking up BSP. To
900 * void the boot-strap code, wake up CPU0 by NMI instead.
901 *
902 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
903 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
904 * We'll change this code in the future to wake up hard offlined CPU0 if
905 * real platform and request are available.
906 */
907static int
908wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
909 int *cpu0_nmi_registered)
910{
911 int id;
912 int boot_error;
913
914 preempt_disable();
915
916 /*
917 * Wake up AP by INIT, INIT, STARTUP sequence.
918 */
919 if (cpu) {
920 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
921 goto out;
922 }
923
924 /*
925 * Wake up BSP by nmi.
926 *
927 * Register a NMI handler to help wake up CPU0.
928 */
929 boot_error = register_nmi_handler(NMI_LOCAL,
930 wakeup_cpu0_nmi, 0, "wake_cpu0");
931
932 if (!boot_error) {
933 enable_start_cpu0 = 1;
934 *cpu0_nmi_registered = 1;
935 if (apic->dest_logical == APIC_DEST_LOGICAL)
936 id = cpu0_logical_apicid;
937 else
938 id = apicid;
939 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
940 }
941
942out:
943 preempt_enable();
944
945 return boot_error;
946}
947
948void common_cpu_up(unsigned int cpu, struct task_struct *idle)
949{
950 /* Just in case we booted with a single CPU. */
951 alternatives_enable_smp();
952
953 per_cpu(current_task, cpu) = idle;
954
955#ifdef CONFIG_X86_32
956 /* Stack for startup_32 can be just as for start_secondary onwards */
957 irq_ctx_init(cpu);
958 per_cpu(cpu_current_top_of_stack, cpu) =
959 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
960#else
961 initial_gs = per_cpu_offset(cpu);
962#endif
963}
964
965/*
966 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
967 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
968 * Returns zero if CPU booted OK, else error code from
969 * ->wakeup_secondary_cpu.
970 */
971static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
972{
973 volatile u32 *trampoline_status =
974 (volatile u32 *) __va(real_mode_header->trampoline_status);
975 /* start_ip had better be page-aligned! */
976 unsigned long start_ip = real_mode_header->trampoline_start;
977
978 unsigned long boot_error = 0;
979 int cpu0_nmi_registered = 0;
980 unsigned long timeout;
981
982 idle->thread.sp = (unsigned long)task_pt_regs(idle);
983 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
984 initial_code = (unsigned long)start_secondary;
985 initial_stack = idle->thread.sp;
986
987 /*
988 * Enable the espfix hack for this CPU
989 */
990#ifdef CONFIG_X86_ESPFIX64
991 init_espfix_ap(cpu);
992#endif
993
994 /* So we see what's up */
995 announce_cpu(cpu, apicid);
996
997 /*
998 * This grunge runs the startup process for
999 * the targeted processor.
1000 */
1001
1002 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1003
1004 pr_debug("Setting warm reset code and vector.\n");
1005
1006 smpboot_setup_warm_reset_vector(start_ip);
1007 /*
1008 * Be paranoid about clearing APIC errors.
1009 */
1010 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1011 apic_write(APIC_ESR, 0);
1012 apic_read(APIC_ESR);
1013 }
1014 }
1015
1016 /*
1017 * AP might wait on cpu_callout_mask in cpu_init() with
1018 * cpu_initialized_mask set if previous attempt to online
1019 * it timed-out. Clear cpu_initialized_mask so that after
1020 * INIT/SIPI it could start with a clean state.
1021 */
1022 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1023 smp_mb();
1024
1025 /*
1026 * Wake up a CPU in difference cases:
1027 * - Use the method in the APIC driver if it's defined
1028 * Otherwise,
1029 * - Use an INIT boot APIC message for APs or NMI for BSP.
1030 */
1031 if (apic->wakeup_secondary_cpu)
1032 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1033 else
1034 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1035 &cpu0_nmi_registered);
1036
1037 if (!boot_error) {
1038 /*
1039 * Wait 10s total for first sign of life from AP
1040 */
1041 boot_error = -1;
1042 timeout = jiffies + 10*HZ;
1043 while (time_before(jiffies, timeout)) {
1044 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1045 /*
1046 * Tell AP to proceed with initialization
1047 */
1048 cpumask_set_cpu(cpu, cpu_callout_mask);
1049 boot_error = 0;
1050 break;
1051 }
1052 schedule();
1053 }
1054 }
1055
1056 if (!boot_error) {
1057 /*
1058 * Wait till AP completes initial initialization
1059 */
1060 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1061 /*
1062 * Allow other tasks to run while we wait for the
1063 * AP to come online. This also gives a chance
1064 * for the MTRR work(triggered by the AP coming online)
1065 * to be completed in the stop machine context.
1066 */
1067 schedule();
1068 }
1069 }
1070
1071 /* mark "stuck" area as not stuck */
1072 *trampoline_status = 0;
1073
1074 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1075 /*
1076 * Cleanup possible dangling ends...
1077 */
1078 smpboot_restore_warm_reset_vector();
1079 }
1080 /*
1081 * Clean up the nmi handler. Do this after the callin and callout sync
1082 * to avoid impact of possible long unregister time.
1083 */
1084 if (cpu0_nmi_registered)
1085 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1086
1087 return boot_error;
1088}
1089
1090int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1091{
1092 int apicid = apic->cpu_present_to_apicid(cpu);
1093 unsigned long flags;
1094 int err;
1095
1096 WARN_ON(irqs_disabled());
1097
1098 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1099
1100 if (apicid == BAD_APICID ||
1101 !physid_isset(apicid, phys_cpu_present_map) ||
1102 !apic->apic_id_valid(apicid)) {
1103 pr_err("%s: bad cpu %d\n", __func__, cpu);
1104 return -EINVAL;
1105 }
1106
1107 /*
1108 * Already booted CPU?
1109 */
1110 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1111 pr_debug("do_boot_cpu %d Already started\n", cpu);
1112 return -ENOSYS;
1113 }
1114
1115 /*
1116 * Save current MTRR state in case it was changed since early boot
1117 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1118 */
1119 mtrr_save_state();
1120
1121 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1122 err = cpu_check_up_prepare(cpu);
1123 if (err && err != -EBUSY)
1124 return err;
1125
1126 /* the FPU context is blank, nobody can own it */
1127 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1128
1129 common_cpu_up(cpu, tidle);
1130
1131 err = do_boot_cpu(apicid, cpu, tidle);
1132 if (err) {
1133 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1134 return -EIO;
1135 }
1136
1137 /*
1138 * Check TSC synchronization with the AP (keep irqs disabled
1139 * while doing so):
1140 */
1141 local_irq_save(flags);
1142 check_tsc_sync_source(cpu);
1143 local_irq_restore(flags);
1144
1145 while (!cpu_online(cpu)) {
1146 cpu_relax();
1147 touch_nmi_watchdog();
1148 }
1149
1150 return 0;
1151}
1152
1153/**
1154 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1155 */
1156void arch_disable_smp_support(void)
1157{
1158 disable_ioapic_support();
1159}
1160
1161/*
1162 * Fall back to non SMP mode after errors.
1163 *
1164 * RED-PEN audit/test this more. I bet there is more state messed up here.
1165 */
1166static __init void disable_smp(void)
1167{
1168 pr_info("SMP disabled\n");
1169
1170 disable_ioapic_support();
1171
1172 init_cpu_present(cpumask_of(0));
1173 init_cpu_possible(cpumask_of(0));
1174
1175 if (smp_found_config)
1176 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1177 else
1178 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1179 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1180 cpumask_set_cpu(0, topology_core_cpumask(0));
1181}
1182
1183enum {
1184 SMP_OK,
1185 SMP_NO_CONFIG,
1186 SMP_NO_APIC,
1187 SMP_FORCE_UP,
1188};
1189
1190/*
1191 * Various sanity checks.
1192 */
1193static int __init smp_sanity_check(unsigned max_cpus)
1194{
1195 preempt_disable();
1196
1197#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1198 if (def_to_bigsmp && nr_cpu_ids > 8) {
1199 unsigned int cpu;
1200 unsigned nr;
1201
1202 pr_warn("More than 8 CPUs detected - skipping them\n"
1203 "Use CONFIG_X86_BIGSMP\n");
1204
1205 nr = 0;
1206 for_each_present_cpu(cpu) {
1207 if (nr >= 8)
1208 set_cpu_present(cpu, false);
1209 nr++;
1210 }
1211
1212 nr = 0;
1213 for_each_possible_cpu(cpu) {
1214 if (nr >= 8)
1215 set_cpu_possible(cpu, false);
1216 nr++;
1217 }
1218
1219 nr_cpu_ids = 8;
1220 }
1221#endif
1222
1223 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1224 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1225 hard_smp_processor_id());
1226
1227 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1228 }
1229
1230 /*
1231 * If we couldn't find an SMP configuration at boot time,
1232 * get out of here now!
1233 */
1234 if (!smp_found_config && !acpi_lapic) {
1235 preempt_enable();
1236 pr_notice("SMP motherboard not detected\n");
1237 return SMP_NO_CONFIG;
1238 }
1239
1240 /*
1241 * Should not be necessary because the MP table should list the boot
1242 * CPU too, but we do it for the sake of robustness anyway.
1243 */
1244 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1245 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1246 boot_cpu_physical_apicid);
1247 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1248 }
1249 preempt_enable();
1250
1251 /*
1252 * If we couldn't find a local APIC, then get out of here now!
1253 */
1254 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
1255 !boot_cpu_has(X86_FEATURE_APIC)) {
1256 if (!disable_apic) {
1257 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1258 boot_cpu_physical_apicid);
1259 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1260 }
1261 return SMP_NO_APIC;
1262 }
1263
1264 /*
1265 * If SMP should be disabled, then really disable it!
1266 */
1267 if (!max_cpus) {
1268 pr_info("SMP mode deactivated\n");
1269 return SMP_FORCE_UP;
1270 }
1271
1272 return SMP_OK;
1273}
1274
1275static void __init smp_cpu_index_default(void)
1276{
1277 int i;
1278 struct cpuinfo_x86 *c;
1279
1280 for_each_possible_cpu(i) {
1281 c = &cpu_data(i);
1282 /* mark all to hotplug */
1283 c->cpu_index = nr_cpu_ids;
1284 }
1285}
1286
1287/*
1288 * Prepare for SMP bootup. The MP table or ACPI has been read
1289 * earlier. Just do some sanity checking here and enable APIC mode.
1290 */
1291void __init native_smp_prepare_cpus(unsigned int max_cpus)
1292{
1293 unsigned int i;
1294
1295 smp_cpu_index_default();
1296
1297 /*
1298 * Setup boot CPU information
1299 */
1300 smp_store_boot_cpu_info(); /* Final full version of the data */
1301 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1302 mb();
1303
1304 for_each_possible_cpu(i) {
1305 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1306 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1307 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1308 }
1309
1310 /*
1311 * Set 'default' x86 topology, this matches default_topology() in that
1312 * it has NUMA nodes as a topology level. See also
1313 * native_smp_cpus_done().
1314 *
1315 * Must be done before set_cpus_sibling_map() is ran.
1316 */
1317 set_sched_topology(x86_topology);
1318
1319 set_cpu_sibling_map(0);
1320
1321 switch (smp_sanity_check(max_cpus)) {
1322 case SMP_NO_CONFIG:
1323 disable_smp();
1324 if (APIC_init_uniprocessor())
1325 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1326 return;
1327 case SMP_NO_APIC:
1328 disable_smp();
1329 return;
1330 case SMP_FORCE_UP:
1331 disable_smp();
1332 apic_bsp_setup(false);
1333 return;
1334 case SMP_OK:
1335 break;
1336 }
1337
1338 if (read_apic_id() != boot_cpu_physical_apicid) {
1339 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1340 read_apic_id(), boot_cpu_physical_apicid);
1341 /* Or can we switch back to PIC here? */
1342 }
1343
1344 default_setup_apic_routing();
1345 cpu0_logical_apicid = apic_bsp_setup(false);
1346
1347 pr_info("CPU0: ");
1348 print_cpu_info(&cpu_data(0));
1349
1350 if (is_uv_system())
1351 uv_system_init();
1352
1353 set_mtrr_aps_delayed_init();
1354
1355 smp_quirk_init_udelay();
1356}
1357
1358void arch_enable_nonboot_cpus_begin(void)
1359{
1360 set_mtrr_aps_delayed_init();
1361}
1362
1363void arch_enable_nonboot_cpus_end(void)
1364{
1365 mtrr_aps_init();
1366}
1367
1368/*
1369 * Early setup to make printk work.
1370 */
1371void __init native_smp_prepare_boot_cpu(void)
1372{
1373 int me = smp_processor_id();
1374 switch_to_new_gdt(me);
1375 /* already set me in cpu_online_mask in boot_cpu_init() */
1376 cpumask_set_cpu(me, cpu_callout_mask);
1377 cpu_set_state_online(me);
1378}
1379
1380void __init native_smp_cpus_done(unsigned int max_cpus)
1381{
1382 pr_debug("Boot done\n");
1383
1384 if (x86_has_numa_in_package)
1385 set_sched_topology(x86_numa_in_package_topology);
1386
1387 nmi_selftest();
1388 impress_friends();
1389 setup_ioapic_dest();
1390 mtrr_aps_init();
1391}
1392
1393static int __initdata setup_possible_cpus = -1;
1394static int __init _setup_possible_cpus(char *str)
1395{
1396 get_option(&str, &setup_possible_cpus);
1397 return 0;
1398}
1399early_param("possible_cpus", _setup_possible_cpus);
1400
1401
1402/*
1403 * cpu_possible_mask should be static, it cannot change as cpu's
1404 * are onlined, or offlined. The reason is per-cpu data-structures
1405 * are allocated by some modules at init time, and dont expect to
1406 * do this dynamically on cpu arrival/departure.
1407 * cpu_present_mask on the other hand can change dynamically.
1408 * In case when cpu_hotplug is not compiled, then we resort to current
1409 * behaviour, which is cpu_possible == cpu_present.
1410 * - Ashok Raj
1411 *
1412 * Three ways to find out the number of additional hotplug CPUs:
1413 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1414 * - The user can overwrite it with possible_cpus=NUM
1415 * - Otherwise don't reserve additional CPUs.
1416 * We do this because additional CPUs waste a lot of memory.
1417 * -AK
1418 */
1419__init void prefill_possible_map(void)
1420{
1421 int i, possible;
1422
1423 /* No boot processor was found in mptable or ACPI MADT */
1424 if (!num_processors) {
1425 if (boot_cpu_has(X86_FEATURE_APIC)) {
1426 int apicid = boot_cpu_physical_apicid;
1427 int cpu = hard_smp_processor_id();
1428
1429 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1430
1431 /* Make sure boot cpu is enumerated */
1432 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1433 apic->apic_id_valid(apicid))
1434 generic_processor_info(apicid, boot_cpu_apic_version);
1435 }
1436
1437 if (!num_processors)
1438 num_processors = 1;
1439 }
1440
1441 i = setup_max_cpus ?: 1;
1442 if (setup_possible_cpus == -1) {
1443 possible = num_processors;
1444#ifdef CONFIG_HOTPLUG_CPU
1445 if (setup_max_cpus)
1446 possible += disabled_cpus;
1447#else
1448 if (possible > i)
1449 possible = i;
1450#endif
1451 } else
1452 possible = setup_possible_cpus;
1453
1454 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1455
1456 /* nr_cpu_ids could be reduced via nr_cpus= */
1457 if (possible > nr_cpu_ids) {
1458 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1459 possible, nr_cpu_ids);
1460 possible = nr_cpu_ids;
1461 }
1462
1463#ifdef CONFIG_HOTPLUG_CPU
1464 if (!setup_max_cpus)
1465#endif
1466 if (possible > i) {
1467 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1468 possible, setup_max_cpus);
1469 possible = i;
1470 }
1471
1472 nr_cpu_ids = possible;
1473
1474 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1475 possible, max_t(int, possible - num_processors, 0));
1476
1477 reset_cpu_possible_mask();
1478
1479 for (i = 0; i < possible; i++)
1480 set_cpu_possible(i, true);
1481}
1482
1483#ifdef CONFIG_HOTPLUG_CPU
1484
1485/* Recompute SMT state for all CPUs on offline */
1486static void recompute_smt_state(void)
1487{
1488 int max_threads, cpu;
1489
1490 max_threads = 0;
1491 for_each_online_cpu (cpu) {
1492 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1493
1494 if (threads > max_threads)
1495 max_threads = threads;
1496 }
1497 __max_smt_threads = max_threads;
1498}
1499
1500static void remove_siblinginfo(int cpu)
1501{
1502 int sibling;
1503 struct cpuinfo_x86 *c = &cpu_data(cpu);
1504
1505 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1506 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1507 /*/
1508 * last thread sibling in this cpu core going down
1509 */
1510 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1511 cpu_data(sibling).booted_cores--;
1512 }
1513
1514 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1515 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1516 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1517 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1518 cpumask_clear(cpu_llc_shared_mask(cpu));
1519 cpumask_clear(topology_sibling_cpumask(cpu));
1520 cpumask_clear(topology_core_cpumask(cpu));
1521 c->phys_proc_id = 0;
1522 c->cpu_core_id = 0;
1523 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1524 recompute_smt_state();
1525}
1526
1527static void remove_cpu_from_maps(int cpu)
1528{
1529 set_cpu_online(cpu, false);
1530 cpumask_clear_cpu(cpu, cpu_callout_mask);
1531 cpumask_clear_cpu(cpu, cpu_callin_mask);
1532 /* was set by cpu_init() */
1533 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1534 numa_remove_cpu(cpu);
1535}
1536
1537void cpu_disable_common(void)
1538{
1539 int cpu = smp_processor_id();
1540
1541 remove_siblinginfo(cpu);
1542
1543 /* It's now safe to remove this processor from the online map */
1544 lock_vector_lock();
1545 remove_cpu_from_maps(cpu);
1546 unlock_vector_lock();
1547 fixup_irqs();
1548}
1549
1550int native_cpu_disable(void)
1551{
1552 int ret;
1553
1554 ret = check_irq_vectors_for_cpu_disable();
1555 if (ret)
1556 return ret;
1557
1558 clear_local_APIC();
1559 cpu_disable_common();
1560
1561 return 0;
1562}
1563
1564int common_cpu_die(unsigned int cpu)
1565{
1566 int ret = 0;
1567
1568 /* We don't do anything here: idle task is faking death itself. */
1569
1570 /* They ack this in play_dead() by setting CPU_DEAD */
1571 if (cpu_wait_death(cpu, 5)) {
1572 if (system_state == SYSTEM_RUNNING)
1573 pr_info("CPU %u is now offline\n", cpu);
1574 } else {
1575 pr_err("CPU %u didn't die...\n", cpu);
1576 ret = -1;
1577 }
1578
1579 return ret;
1580}
1581
1582void native_cpu_die(unsigned int cpu)
1583{
1584 common_cpu_die(cpu);
1585}
1586
1587void play_dead_common(void)
1588{
1589 idle_task_exit();
1590 reset_lazy_tlbstate();
1591
1592 /* Ack it */
1593 (void)cpu_report_death();
1594
1595 /*
1596 * With physical CPU hotplug, we should halt the cpu
1597 */
1598 local_irq_disable();
1599}
1600
1601static bool wakeup_cpu0(void)
1602{
1603 if (smp_processor_id() == 0 && enable_start_cpu0)
1604 return true;
1605
1606 return false;
1607}
1608
1609/*
1610 * We need to flush the caches before going to sleep, lest we have
1611 * dirty data in our caches when we come back up.
1612 */
1613static inline void mwait_play_dead(void)
1614{
1615 unsigned int eax, ebx, ecx, edx;
1616 unsigned int highest_cstate = 0;
1617 unsigned int highest_subcstate = 0;
1618 void *mwait_ptr;
1619 int i;
1620
1621 if (!this_cpu_has(X86_FEATURE_MWAIT))
1622 return;
1623 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1624 return;
1625 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1626 return;
1627
1628 eax = CPUID_MWAIT_LEAF;
1629 ecx = 0;
1630 native_cpuid(&eax, &ebx, &ecx, &edx);
1631
1632 /*
1633 * eax will be 0 if EDX enumeration is not valid.
1634 * Initialized below to cstate, sub_cstate value when EDX is valid.
1635 */
1636 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1637 eax = 0;
1638 } else {
1639 edx >>= MWAIT_SUBSTATE_SIZE;
1640 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1641 if (edx & MWAIT_SUBSTATE_MASK) {
1642 highest_cstate = i;
1643 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1644 }
1645 }
1646 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1647 (highest_subcstate - 1);
1648 }
1649
1650 /*
1651 * This should be a memory location in a cache line which is
1652 * unlikely to be touched by other processors. The actual
1653 * content is immaterial as it is not actually modified in any way.
1654 */
1655 mwait_ptr = ¤t_thread_info()->flags;
1656
1657 wbinvd();
1658
1659 while (1) {
1660 /*
1661 * The CLFLUSH is a workaround for erratum AAI65 for
1662 * the Xeon 7400 series. It's not clear it is actually
1663 * needed, but it should be harmless in either case.
1664 * The WBINVD is insufficient due to the spurious-wakeup
1665 * case where we return around the loop.
1666 */
1667 mb();
1668 clflush(mwait_ptr);
1669 mb();
1670 __monitor(mwait_ptr, 0, 0);
1671 mb();
1672 __mwait(eax, 0);
1673 /*
1674 * If NMI wants to wake up CPU0, start CPU0.
1675 */
1676 if (wakeup_cpu0())
1677 start_cpu0();
1678 }
1679}
1680
1681void hlt_play_dead(void)
1682{
1683 if (__this_cpu_read(cpu_info.x86) >= 4)
1684 wbinvd();
1685
1686 while (1) {
1687 native_halt();
1688 /*
1689 * If NMI wants to wake up CPU0, start CPU0.
1690 */
1691 if (wakeup_cpu0())
1692 start_cpu0();
1693 }
1694}
1695
1696void native_play_dead(void)
1697{
1698 play_dead_common();
1699 tboot_shutdown(TB_SHUTDOWN_WFS);
1700
1701 mwait_play_dead(); /* Only returns on failure */
1702 if (cpuidle_play_dead())
1703 hlt_play_dead();
1704}
1705
1706#else /* ... !CONFIG_HOTPLUG_CPU */
1707int native_cpu_disable(void)
1708{
1709 return -ENOSYS;
1710}
1711
1712void native_cpu_die(unsigned int cpu)
1713{
1714 /* We said "no" in __cpu_disable */
1715 BUG();
1716}
1717
1718void native_play_dead(void)
1719{
1720 BUG();
1721}
1722
1723#endif