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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#include <linux/acpi.h>
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/dmaengine.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/gpio/consumer.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/mod_devicetable.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/property.h>
26#include <linux/slab.h>
27
28#include <linux/spi/pxa2xx_spi.h>
29#include <linux/spi/spi.h>
30
31#include "spi-pxa2xx.h"
32
33MODULE_AUTHOR("Stephen Street");
34MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
35MODULE_LICENSE("GPL");
36MODULE_ALIAS("platform:pxa2xx-spi");
37
38#define TIMOUT_DFLT 1000
39
40/*
41 * For testing SSCR1 changes that require SSP restart, basically
42 * everything except the service and interrupt enables, the PXA270 developer
43 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
44 * list, but the PXA255 developer manual says all bits without really meaning
45 * the service and interrupt enables.
46 */
47#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
48 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
49 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
50 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
51 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
53
54#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
55 | QUARK_X1000_SSCR1_EFWR \
56 | QUARK_X1000_SSCR1_RFT \
57 | QUARK_X1000_SSCR1_TFT \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59
60#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
68#define LPSS_CS_CONTROL_SW_MODE BIT(0)
69#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
73#define LPSS_PRIV_CLOCK_GATE 0x38
74#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
75#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
76
77struct lpss_config {
78 /* LPSS offset from drv_data->ioaddr */
79 unsigned offset;
80 /* Register offsets from drv_data->lpss_base or -1 */
81 int reg_general;
82 int reg_ssp;
83 int reg_cs_ctrl;
84 int reg_capabilities;
85 /* FIFO thresholds */
86 u32 rx_threshold;
87 u32 tx_threshold_lo;
88 u32 tx_threshold_hi;
89 /* Chip select control */
90 unsigned cs_sel_shift;
91 unsigned cs_sel_mask;
92 unsigned cs_num;
93 /* Quirks */
94 unsigned cs_clk_stays_gated : 1;
95};
96
97/* Keep these sorted with enum pxa_ssp_type */
98static const struct lpss_config lpss_platforms[] = {
99 { /* LPSS_LPT_SSP */
100 .offset = 0x800,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
109 { /* LPSS_BYT_SSP */
110 .offset = 0x400,
111 .reg_general = 0x08,
112 .reg_ssp = 0x0c,
113 .reg_cs_ctrl = 0x18,
114 .reg_capabilities = -1,
115 .rx_threshold = 64,
116 .tx_threshold_lo = 160,
117 .tx_threshold_hi = 224,
118 },
119 { /* LPSS_BSW_SSP */
120 .offset = 0x400,
121 .reg_general = 0x08,
122 .reg_ssp = 0x0c,
123 .reg_cs_ctrl = 0x18,
124 .reg_capabilities = -1,
125 .rx_threshold = 64,
126 .tx_threshold_lo = 160,
127 .tx_threshold_hi = 224,
128 .cs_sel_shift = 2,
129 .cs_sel_mask = 1 << 2,
130 .cs_num = 2,
131 },
132 { /* LPSS_SPT_SSP */
133 .offset = 0x200,
134 .reg_general = -1,
135 .reg_ssp = 0x20,
136 .reg_cs_ctrl = 0x24,
137 .reg_capabilities = -1,
138 .rx_threshold = 1,
139 .tx_threshold_lo = 32,
140 .tx_threshold_hi = 56,
141 },
142 { /* LPSS_BXT_SSP */
143 .offset = 0x200,
144 .reg_general = -1,
145 .reg_ssp = 0x20,
146 .reg_cs_ctrl = 0x24,
147 .reg_capabilities = 0xfc,
148 .rx_threshold = 1,
149 .tx_threshold_lo = 16,
150 .tx_threshold_hi = 48,
151 .cs_sel_shift = 8,
152 .cs_sel_mask = 3 << 8,
153 .cs_clk_stays_gated = true,
154 },
155 { /* LPSS_CNL_SSP */
156 .offset = 0x200,
157 .reg_general = -1,
158 .reg_ssp = 0x20,
159 .reg_cs_ctrl = 0x24,
160 .reg_capabilities = 0xfc,
161 .rx_threshold = 1,
162 .tx_threshold_lo = 32,
163 .tx_threshold_hi = 56,
164 .cs_sel_shift = 8,
165 .cs_sel_mask = 3 << 8,
166 .cs_clk_stays_gated = true,
167 },
168};
169
170static inline const struct lpss_config
171*lpss_get_config(const struct driver_data *drv_data)
172{
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
174}
175
176static bool is_lpss_ssp(const struct driver_data *drv_data)
177{
178 switch (drv_data->ssp_type) {
179 case LPSS_LPT_SSP:
180 case LPSS_BYT_SSP:
181 case LPSS_BSW_SSP:
182 case LPSS_SPT_SSP:
183 case LPSS_BXT_SSP:
184 case LPSS_CNL_SSP:
185 return true;
186 default:
187 return false;
188 }
189}
190
191static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
192{
193 return drv_data->ssp_type == QUARK_X1000_SSP;
194}
195
196static bool is_mmp2_ssp(const struct driver_data *drv_data)
197{
198 return drv_data->ssp_type == MMP2_SSP;
199}
200
201static bool is_mrfld_ssp(const struct driver_data *drv_data)
202{
203 return drv_data->ssp_type == MRFLD_SSP;
204}
205
206static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
207{
208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
209 pxa2xx_spi_write(drv_data, reg, value & mask);
210}
211
212static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
213{
214 switch (drv_data->ssp_type) {
215 case QUARK_X1000_SSP:
216 return QUARK_X1000_SSCR1_CHANGE_MASK;
217 case CE4100_SSP:
218 return CE4100_SSCR1_CHANGE_MASK;
219 default:
220 return SSCR1_CHANGE_MASK;
221 }
222}
223
224static u32
225pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
226{
227 switch (drv_data->ssp_type) {
228 case QUARK_X1000_SSP:
229 return RX_THRESH_QUARK_X1000_DFLT;
230 case CE4100_SSP:
231 return RX_THRESH_CE4100_DFLT;
232 default:
233 return RX_THRESH_DFLT;
234 }
235}
236
237static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
238{
239 u32 mask;
240
241 switch (drv_data->ssp_type) {
242 case QUARK_X1000_SSP:
243 mask = QUARK_X1000_SSSR_TFL_MASK;
244 break;
245 case CE4100_SSP:
246 mask = CE4100_SSSR_TFL_MASK;
247 break;
248 default:
249 mask = SSSR_TFL_MASK;
250 break;
251 }
252
253 return read_SSSR_bits(drv_data, mask) == mask;
254}
255
256static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
257 u32 *sccr1_reg)
258{
259 u32 mask;
260
261 switch (drv_data->ssp_type) {
262 case QUARK_X1000_SSP:
263 mask = QUARK_X1000_SSCR1_RFT;
264 break;
265 case CE4100_SSP:
266 mask = CE4100_SSCR1_RFT;
267 break;
268 default:
269 mask = SSCR1_RFT;
270 break;
271 }
272 *sccr1_reg &= ~mask;
273}
274
275static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
276 u32 *sccr1_reg, u32 threshold)
277{
278 switch (drv_data->ssp_type) {
279 case QUARK_X1000_SSP:
280 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
281 break;
282 case CE4100_SSP:
283 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
284 break;
285 default:
286 *sccr1_reg |= SSCR1_RxTresh(threshold);
287 break;
288 }
289}
290
291static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
292 u32 clk_div, u8 bits)
293{
294 switch (drv_data->ssp_type) {
295 case QUARK_X1000_SSP:
296 return clk_div
297 | QUARK_X1000_SSCR0_Motorola
298 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
299 default:
300 return clk_div
301 | SSCR0_Motorola
302 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
303 | (bits > 16 ? SSCR0_EDSS : 0);
304 }
305}
306
307/*
308 * Read and write LPSS SSP private registers. Caller must first check that
309 * is_lpss_ssp() returns true before these can be called.
310 */
311static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
312{
313 WARN_ON(!drv_data->lpss_base);
314 return readl(drv_data->lpss_base + offset);
315}
316
317static void __lpss_ssp_write_priv(struct driver_data *drv_data,
318 unsigned offset, u32 value)
319{
320 WARN_ON(!drv_data->lpss_base);
321 writel(value, drv_data->lpss_base + offset);
322}
323
324/*
325 * lpss_ssp_setup - perform LPSS SSP specific setup
326 * @drv_data: pointer to the driver private data
327 *
328 * Perform LPSS SSP specific setup. This function must be called first if
329 * one is going to use LPSS SSP private registers.
330 */
331static void lpss_ssp_setup(struct driver_data *drv_data)
332{
333 const struct lpss_config *config;
334 u32 value;
335
336 config = lpss_get_config(drv_data);
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
338
339 /* Enable software chip select control */
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
341 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
342 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
344
345 /* Enable multiblock DMA transfers */
346 if (drv_data->controller_info->enable_dma) {
347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
348
349 if (config->reg_general >= 0) {
350 value = __lpss_ssp_read_priv(drv_data,
351 config->reg_general);
352 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
353 __lpss_ssp_write_priv(drv_data,
354 config->reg_general, value);
355 }
356 }
357}
358
359static void lpss_ssp_select_cs(struct spi_device *spi,
360 const struct lpss_config *config)
361{
362 struct driver_data *drv_data =
363 spi_controller_get_devdata(spi->controller);
364 u32 value, cs;
365
366 if (!config->cs_sel_mask)
367 return;
368
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
370
371 cs = spi->chip_select;
372 cs <<= config->cs_sel_shift;
373 if (cs != (value & config->cs_sel_mask)) {
374 /*
375 * When switching another chip select output active the
376 * output must be selected first and wait 2 ssp_clk cycles
377 * before changing state to active. Otherwise a short
378 * glitch will occur on the previous chip select since
379 * output select is latched but state control is not.
380 */
381 value &= ~config->cs_sel_mask;
382 value |= cs;
383 __lpss_ssp_write_priv(drv_data,
384 config->reg_cs_ctrl, value);
385 ndelay(1000000000 /
386 (drv_data->controller->max_speed_hz / 2));
387 }
388}
389
390static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
391{
392 struct driver_data *drv_data =
393 spi_controller_get_devdata(spi->controller);
394 const struct lpss_config *config;
395 u32 value;
396
397 config = lpss_get_config(drv_data);
398
399 if (enable)
400 lpss_ssp_select_cs(spi, config);
401
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
403 if (enable)
404 value &= ~LPSS_CS_CONTROL_CS_HIGH;
405 else
406 value |= LPSS_CS_CONTROL_CS_HIGH;
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
408 if (config->cs_clk_stays_gated) {
409 u32 clkgate;
410
411 /*
412 * Changing CS alone when dynamic clock gating is on won't
413 * actually flip CS at that time. This ruins SPI transfers
414 * that specify delays, or have no data. Toggle the clock mode
415 * to force on briefly to poke the CS pin to move.
416 */
417 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
418 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
419 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
420
421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
423 }
424}
425
426static void cs_assert(struct spi_device *spi)
427{
428 struct driver_data *drv_data =
429 spi_controller_get_devdata(spi->controller);
430
431 if (drv_data->ssp_type == CE4100_SSP) {
432 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select);
433 return;
434 }
435
436 if (is_lpss_ssp(drv_data))
437 lpss_ssp_cs_control(spi, true);
438}
439
440static void cs_deassert(struct spi_device *spi)
441{
442 struct driver_data *drv_data =
443 spi_controller_get_devdata(spi->controller);
444 unsigned long timeout;
445
446 if (drv_data->ssp_type == CE4100_SSP)
447 return;
448
449 /* Wait until SSP becomes idle before deasserting the CS */
450 timeout = jiffies + msecs_to_jiffies(10);
451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
452 !time_after(jiffies, timeout))
453 cpu_relax();
454
455 if (is_lpss_ssp(drv_data))
456 lpss_ssp_cs_control(spi, false);
457}
458
459static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
460{
461 if (level)
462 cs_deassert(spi);
463 else
464 cs_assert(spi);
465}
466
467int pxa2xx_spi_flush(struct driver_data *drv_data)
468{
469 unsigned long limit = loops_per_jiffy << 1;
470
471 do {
472 while (read_SSSR_bits(drv_data, SSSR_RNE))
473 pxa2xx_spi_read(drv_data, SSDR);
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
475 write_SSSR_CS(drv_data, SSSR_ROR);
476
477 return limit;
478}
479
480static void pxa2xx_spi_off(struct driver_data *drv_data)
481{
482 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
483 if (is_mmp2_ssp(drv_data))
484 return;
485
486 pxa_ssp_disable(drv_data->ssp);
487}
488
489static int null_writer(struct driver_data *drv_data)
490{
491 u8 n_bytes = drv_data->n_bytes;
492
493 if (pxa2xx_spi_txfifo_full(drv_data)
494 || (drv_data->tx == drv_data->tx_end))
495 return 0;
496
497 pxa2xx_spi_write(drv_data, SSDR, 0);
498 drv_data->tx += n_bytes;
499
500 return 1;
501}
502
503static int null_reader(struct driver_data *drv_data)
504{
505 u8 n_bytes = drv_data->n_bytes;
506
507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
508 pxa2xx_spi_read(drv_data, SSDR);
509 drv_data->rx += n_bytes;
510 }
511
512 return drv_data->rx == drv_data->rx_end;
513}
514
515static int u8_writer(struct driver_data *drv_data)
516{
517 if (pxa2xx_spi_txfifo_full(drv_data)
518 || (drv_data->tx == drv_data->tx_end))
519 return 0;
520
521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
522 ++drv_data->tx;
523
524 return 1;
525}
526
527static int u8_reader(struct driver_data *drv_data)
528{
529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
531 ++drv_data->rx;
532 }
533
534 return drv_data->rx == drv_data->rx_end;
535}
536
537static int u16_writer(struct driver_data *drv_data)
538{
539 if (pxa2xx_spi_txfifo_full(drv_data)
540 || (drv_data->tx == drv_data->tx_end))
541 return 0;
542
543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
544 drv_data->tx += 2;
545
546 return 1;
547}
548
549static int u16_reader(struct driver_data *drv_data)
550{
551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
553 drv_data->rx += 2;
554 }
555
556 return drv_data->rx == drv_data->rx_end;
557}
558
559static int u32_writer(struct driver_data *drv_data)
560{
561 if (pxa2xx_spi_txfifo_full(drv_data)
562 || (drv_data->tx == drv_data->tx_end))
563 return 0;
564
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
566 drv_data->tx += 4;
567
568 return 1;
569}
570
571static int u32_reader(struct driver_data *drv_data)
572{
573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
575 drv_data->rx += 4;
576 }
577
578 return drv_data->rx == drv_data->rx_end;
579}
580
581static void reset_sccr1(struct driver_data *drv_data)
582{
583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
584 struct chip_data *chip;
585
586 if (drv_data->controller->cur_msg) {
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
588 threshold = chip->threshold;
589 } else {
590 threshold = 0;
591 }
592
593 switch (drv_data->ssp_type) {
594 case QUARK_X1000_SSP:
595 mask |= QUARK_X1000_SSCR1_RFT;
596 break;
597 case CE4100_SSP:
598 mask |= CE4100_SSCR1_RFT;
599 break;
600 default:
601 mask |= SSCR1_RFT;
602 break;
603 }
604
605 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
606}
607
608static void int_stop_and_reset(struct driver_data *drv_data)
609{
610 /* Clear and disable interrupts */
611 write_SSSR_CS(drv_data, drv_data->clear_sr);
612 reset_sccr1(drv_data);
613 if (pxa25x_ssp_comp(drv_data))
614 return;
615
616 pxa2xx_spi_write(drv_data, SSTO, 0);
617}
618
619static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
620{
621 int_stop_and_reset(drv_data);
622 pxa2xx_spi_flush(drv_data);
623 pxa2xx_spi_off(drv_data);
624
625 dev_err(drv_data->ssp->dev, "%s\n", msg);
626
627 drv_data->controller->cur_msg->status = err;
628 spi_finalize_current_transfer(drv_data->controller);
629}
630
631static void int_transfer_complete(struct driver_data *drv_data)
632{
633 int_stop_and_reset(drv_data);
634
635 spi_finalize_current_transfer(drv_data->controller);
636}
637
638static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
639{
640 u32 irq_status;
641
642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
643 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
644 irq_status &= ~SSSR_TFS;
645
646 if (irq_status & SSSR_ROR) {
647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
648 return IRQ_HANDLED;
649 }
650
651 if (irq_status & SSSR_TUR) {
652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
653 return IRQ_HANDLED;
654 }
655
656 if (irq_status & SSSR_TINT) {
657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
658 if (drv_data->read(drv_data)) {
659 int_transfer_complete(drv_data);
660 return IRQ_HANDLED;
661 }
662 }
663
664 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
665 do {
666 if (drv_data->read(drv_data)) {
667 int_transfer_complete(drv_data);
668 return IRQ_HANDLED;
669 }
670 } while (drv_data->write(drv_data));
671
672 if (drv_data->read(drv_data)) {
673 int_transfer_complete(drv_data);
674 return IRQ_HANDLED;
675 }
676
677 if (drv_data->tx == drv_data->tx_end) {
678 u32 bytes_left;
679 u32 sccr1_reg;
680
681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
682 sccr1_reg &= ~SSCR1_TIE;
683
684 /*
685 * PXA25x_SSP has no timeout, set up Rx threshold for
686 * the remaining Rx bytes.
687 */
688 if (pxa25x_ssp_comp(drv_data)) {
689 u32 rx_thre;
690
691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
692
693 bytes_left = drv_data->rx_end - drv_data->rx;
694 switch (drv_data->n_bytes) {
695 case 4:
696 bytes_left >>= 2;
697 break;
698 case 2:
699 bytes_left >>= 1;
700 break;
701 }
702
703 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
704 if (rx_thre > bytes_left)
705 rx_thre = bytes_left;
706
707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
708 }
709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
710 }
711
712 /* We did something */
713 return IRQ_HANDLED;
714}
715
716static void handle_bad_msg(struct driver_data *drv_data)
717{
718 int_stop_and_reset(drv_data);
719 pxa2xx_spi_off(drv_data);
720
721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
722}
723
724static irqreturn_t ssp_int(int irq, void *dev_id)
725{
726 struct driver_data *drv_data = dev_id;
727 u32 sccr1_reg;
728 u32 mask = drv_data->mask_sr;
729 u32 status;
730
731 /*
732 * The IRQ might be shared with other peripherals so we must first
733 * check that are we RPM suspended or not. If we are we assume that
734 * the IRQ was not for us (we shouldn't be RPM suspended when the
735 * interrupt is enabled).
736 */
737 if (pm_runtime_suspended(drv_data->ssp->dev))
738 return IRQ_NONE;
739
740 /*
741 * If the device is not yet in RPM suspended state and we get an
742 * interrupt that is meant for another device, check if status bits
743 * are all set to one. That means that the device is already
744 * powered off.
745 */
746 status = pxa2xx_spi_read(drv_data, SSSR);
747 if (status == ~0)
748 return IRQ_NONE;
749
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
751
752 /* Ignore possible writes if we don't need to write */
753 if (!(sccr1_reg & SSCR1_TIE))
754 mask &= ~SSSR_TFS;
755
756 /* Ignore RX timeout interrupt if it is disabled */
757 if (!(sccr1_reg & SSCR1_TINTE))
758 mask &= ~SSSR_TINT;
759
760 if (!(status & mask))
761 return IRQ_NONE;
762
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
765
766 if (!drv_data->controller->cur_msg) {
767 handle_bad_msg(drv_data);
768 /* Never fail */
769 return IRQ_HANDLED;
770 }
771
772 return drv_data->transfer_handler(drv_data);
773}
774
775/*
776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
777 * input frequency by fractions of 2^24. It also has a divider by 5.
778 *
779 * There are formulas to get baud rate value for given input frequency and
780 * divider parameters, such as DDS_CLK_RATE and SCR:
781 *
782 * Fsys = 200MHz
783 *
784 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
786 *
787 * DDS_CLK_RATE either 2^n or 2^n / 5.
788 * SCR is in range 0 .. 255
789 *
790 * Divisor = 5^i * 2^j * 2 * k
791 * i = [0, 1] i = 1 iff j = 0 or j > 3
792 * j = [0, 23] j = 0 iff i = 1
793 * k = [1, 256]
794 * Special case: j = 0, i = 1: Divisor = 2 / 5
795 *
796 * Accordingly to the specification the recommended values for DDS_CLK_RATE
797 * are:
798 * Case 1: 2^n, n = [0, 23]
799 * Case 2: 2^24 * 2 / 5 (0x666666)
800 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
801 *
802 * In all cases the lowest possible value is better.
803 *
804 * The function calculates parameters for all cases and chooses the one closest
805 * to the asked baud rate.
806 */
807static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
808{
809 unsigned long xtal = 200000000;
810 unsigned long fref = xtal / 2; /* mandatory division by 2,
811 see (2) */
812 /* case 3 */
813 unsigned long fref1 = fref / 2; /* case 1 */
814 unsigned long fref2 = fref * 2 / 5; /* case 2 */
815 unsigned long scale;
816 unsigned long q, q1, q2;
817 long r, r1, r2;
818 u32 mul;
819
820 /* Case 1 */
821
822 /* Set initial value for DDS_CLK_RATE */
823 mul = (1 << 24) >> 1;
824
825 /* Calculate initial quot */
826 q1 = DIV_ROUND_UP(fref1, rate);
827
828 /* Scale q1 if it's too big */
829 if (q1 > 256) {
830 /* Scale q1 to range [1, 512] */
831 scale = fls_long(q1 - 1);
832 if (scale > 9) {
833 q1 >>= scale - 9;
834 mul >>= scale - 9;
835 }
836
837 /* Round the result if we have a remainder */
838 q1 += q1 & 1;
839 }
840
841 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
842 scale = __ffs(q1);
843 q1 >>= scale;
844 mul >>= scale;
845
846 /* Get the remainder */
847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
848
849 /* Case 2 */
850
851 q2 = DIV_ROUND_UP(fref2, rate);
852 r2 = abs(fref2 / q2 - rate);
853
854 /*
855 * Choose the best between two: less remainder we have the better. We
856 * can't go case 2 if q2 is greater than 256 since SCR register can
857 * hold only values 0 .. 255.
858 */
859 if (r2 >= r1 || q2 > 256) {
860 /* case 1 is better */
861 r = r1;
862 q = q1;
863 } else {
864 /* case 2 is better */
865 r = r2;
866 q = q2;
867 mul = (1 << 24) * 2 / 5;
868 }
869
870 /* Check case 3 only if the divisor is big enough */
871 if (fref / rate >= 80) {
872 u64 fssp;
873 u32 m;
874
875 /* Calculate initial quot */
876 q1 = DIV_ROUND_UP(fref, rate);
877 m = (1 << 24) / q1;
878
879 /* Get the remainder */
880 fssp = (u64)fref * m;
881 do_div(fssp, 1 << 24);
882 r1 = abs(fssp - rate);
883
884 /* Choose this one if it suits better */
885 if (r1 < r) {
886 /* case 3 is better */
887 q = 1;
888 mul = m;
889 }
890 }
891
892 *dds = mul;
893 return q - 1;
894}
895
896static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
897{
898 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
899 const struct ssp_device *ssp = drv_data->ssp;
900
901 rate = min_t(int, ssp_clk, rate);
902
903 /*
904 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
905 * that the SSP transmission rate can be greater than the device rate.
906 */
907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
909 else
910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
911}
912
913static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
914 int rate)
915{
916 struct chip_data *chip =
917 spi_get_ctldata(drv_data->controller->cur_msg->spi);
918 unsigned int clk_div;
919
920 switch (drv_data->ssp_type) {
921 case QUARK_X1000_SSP:
922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
923 break;
924 default:
925 clk_div = ssp_get_clk_div(drv_data, rate);
926 break;
927 }
928 return clk_div << 8;
929}
930
931static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
932 struct spi_device *spi,
933 struct spi_transfer *xfer)
934{
935 struct chip_data *chip = spi_get_ctldata(spi);
936
937 return chip->enable_dma &&
938 xfer->len <= MAX_DMA_LEN &&
939 xfer->len >= chip->dma_burst_size;
940}
941
942static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
943 struct spi_device *spi,
944 struct spi_transfer *transfer)
945{
946 struct driver_data *drv_data = spi_controller_get_devdata(controller);
947 struct spi_message *message = controller->cur_msg;
948 struct chip_data *chip = spi_get_ctldata(spi);
949 u32 dma_thresh = chip->dma_threshold;
950 u32 dma_burst = chip->dma_burst_size;
951 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
952 u32 clk_div;
953 u8 bits;
954 u32 speed;
955 u32 cr0;
956 u32 cr1;
957 int err;
958 int dma_mapped;
959
960 /* Check if we can DMA this transfer */
961 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
962
963 /* Reject already-mapped transfers; PIO won't always work */
964 if (message->is_dma_mapped
965 || transfer->rx_dma || transfer->tx_dma) {
966 dev_err(&spi->dev,
967 "Mapped transfer length of %u is greater than %d\n",
968 transfer->len, MAX_DMA_LEN);
969 return -EINVAL;
970 }
971
972 /* Warn ... we force this to PIO mode */
973 dev_warn_ratelimited(&spi->dev,
974 "DMA disabled for transfer length %u greater than %d\n",
975 transfer->len, MAX_DMA_LEN);
976 }
977
978 /* Setup the transfer state based on the type of transfer */
979 if (pxa2xx_spi_flush(drv_data) == 0) {
980 dev_err(&spi->dev, "Flush failed\n");
981 return -EIO;
982 }
983 drv_data->tx = (void *)transfer->tx_buf;
984 drv_data->tx_end = drv_data->tx + transfer->len;
985 drv_data->rx = transfer->rx_buf;
986 drv_data->rx_end = drv_data->rx + transfer->len;
987
988 /* Change speed and bit per word on a per transfer */
989 bits = transfer->bits_per_word;
990 speed = transfer->speed_hz;
991
992 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
993
994 if (bits <= 8) {
995 drv_data->n_bytes = 1;
996 drv_data->read = drv_data->rx ? u8_reader : null_reader;
997 drv_data->write = drv_data->tx ? u8_writer : null_writer;
998 } else if (bits <= 16) {
999 drv_data->n_bytes = 2;
1000 drv_data->read = drv_data->rx ? u16_reader : null_reader;
1001 drv_data->write = drv_data->tx ? u16_writer : null_writer;
1002 } else if (bits <= 32) {
1003 drv_data->n_bytes = 4;
1004 drv_data->read = drv_data->rx ? u32_reader : null_reader;
1005 drv_data->write = drv_data->tx ? u32_writer : null_writer;
1006 }
1007 /*
1008 * If bits per word is changed in DMA mode, then must check
1009 * the thresholds and burst also.
1010 */
1011 if (chip->enable_dma) {
1012 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1013 spi,
1014 bits, &dma_burst,
1015 &dma_thresh))
1016 dev_warn_ratelimited(&spi->dev,
1017 "DMA burst size reduced to match bits_per_word\n");
1018 }
1019
1020 dma_mapped = controller->can_dma &&
1021 controller->can_dma(controller, spi, transfer) &&
1022 controller->cur_msg_mapped;
1023 if (dma_mapped) {
1024
1025 /* Ensure we have the correct interrupt handler */
1026 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1027
1028 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1029 if (err)
1030 return err;
1031
1032 /* Clear status and start DMA engine */
1033 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1034 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1035
1036 pxa2xx_spi_dma_start(drv_data);
1037 } else {
1038 /* Ensure we have the correct interrupt handler */
1039 drv_data->transfer_handler = interrupt_transfer;
1040
1041 /* Clear status */
1042 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1043 write_SSSR_CS(drv_data, drv_data->clear_sr);
1044 }
1045
1046 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1047 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1048 if (!pxa25x_ssp_comp(drv_data))
1049 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1050 controller->max_speed_hz
1051 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1052 dma_mapped ? "DMA" : "PIO");
1053 else
1054 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1055 controller->max_speed_hz / 2
1056 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1057 dma_mapped ? "DMA" : "PIO");
1058
1059 if (is_lpss_ssp(drv_data)) {
1060 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1061 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1062 }
1063
1064 if (is_mrfld_ssp(drv_data)) {
1065 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1066 u32 thresh = 0;
1067
1068 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1069 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1070
1071 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1072 }
1073
1074 if (is_quark_x1000_ssp(drv_data))
1075 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1076
1077 /* Stop the SSP */
1078 if (!is_mmp2_ssp(drv_data))
1079 pxa_ssp_disable(drv_data->ssp);
1080
1081 if (!pxa25x_ssp_comp(drv_data))
1082 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1083
1084 /* First set CR1 without interrupt and service enables */
1085 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1086
1087 /* See if we need to reload the configuration registers */
1088 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1089
1090 /* Restart the SSP */
1091 pxa_ssp_enable(drv_data->ssp);
1092
1093 if (is_mmp2_ssp(drv_data)) {
1094 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1095
1096 if (tx_level) {
1097 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1098 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1099 if (tx_level > transfer->len)
1100 tx_level = transfer->len;
1101 drv_data->tx += tx_level;
1102 }
1103 }
1104
1105 if (spi_controller_is_slave(controller)) {
1106 while (drv_data->write(drv_data))
1107 ;
1108 if (drv_data->gpiod_ready) {
1109 gpiod_set_value(drv_data->gpiod_ready, 1);
1110 udelay(1);
1111 gpiod_set_value(drv_data->gpiod_ready, 0);
1112 }
1113 }
1114
1115 /*
1116 * Release the data by enabling service requests and interrupts,
1117 * without changing any mode bits.
1118 */
1119 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1120
1121 return 1;
1122}
1123
1124static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1125{
1126 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1127
1128 int_error_stop(drv_data, "transfer aborted", -EINTR);
1129
1130 return 0;
1131}
1132
1133static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1134 struct spi_message *msg)
1135{
1136 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1137
1138 int_stop_and_reset(drv_data);
1139
1140 /* Disable the SSP */
1141 pxa2xx_spi_off(drv_data);
1142
1143 /*
1144 * Stop the DMA if running. Note DMA callback handler may have unset
1145 * the dma_running already, which is fine as stopping is not needed
1146 * then but we shouldn't rely this flag for anything else than
1147 * stopping. For instance to differentiate between PIO and DMA
1148 * transfers.
1149 */
1150 if (atomic_read(&drv_data->dma_running))
1151 pxa2xx_spi_dma_stop(drv_data);
1152}
1153
1154static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1155{
1156 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1157
1158 /* Disable the SSP now */
1159 pxa2xx_spi_off(drv_data);
1160
1161 return 0;
1162}
1163
1164static int setup(struct spi_device *spi)
1165{
1166 struct pxa2xx_spi_chip *chip_info;
1167 struct chip_data *chip;
1168 const struct lpss_config *config;
1169 struct driver_data *drv_data =
1170 spi_controller_get_devdata(spi->controller);
1171 uint tx_thres, tx_hi_thres, rx_thres;
1172
1173 switch (drv_data->ssp_type) {
1174 case QUARK_X1000_SSP:
1175 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1176 tx_hi_thres = 0;
1177 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1178 break;
1179 case MRFLD_SSP:
1180 tx_thres = TX_THRESH_MRFLD_DFLT;
1181 tx_hi_thres = 0;
1182 rx_thres = RX_THRESH_MRFLD_DFLT;
1183 break;
1184 case CE4100_SSP:
1185 tx_thres = TX_THRESH_CE4100_DFLT;
1186 tx_hi_thres = 0;
1187 rx_thres = RX_THRESH_CE4100_DFLT;
1188 break;
1189 case LPSS_LPT_SSP:
1190 case LPSS_BYT_SSP:
1191 case LPSS_BSW_SSP:
1192 case LPSS_SPT_SSP:
1193 case LPSS_BXT_SSP:
1194 case LPSS_CNL_SSP:
1195 config = lpss_get_config(drv_data);
1196 tx_thres = config->tx_threshold_lo;
1197 tx_hi_thres = config->tx_threshold_hi;
1198 rx_thres = config->rx_threshold;
1199 break;
1200 default:
1201 tx_hi_thres = 0;
1202 if (spi_controller_is_slave(drv_data->controller)) {
1203 tx_thres = 1;
1204 rx_thres = 2;
1205 } else {
1206 tx_thres = TX_THRESH_DFLT;
1207 rx_thres = RX_THRESH_DFLT;
1208 }
1209 break;
1210 }
1211
1212 /* Only allocate on the first setup */
1213 chip = spi_get_ctldata(spi);
1214 if (!chip) {
1215 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1216 if (!chip)
1217 return -ENOMEM;
1218
1219 if (drv_data->ssp_type == CE4100_SSP) {
1220 if (spi->chip_select > 4) {
1221 dev_err(&spi->dev,
1222 "failed setup: cs number must not be > 4.\n");
1223 kfree(chip);
1224 return -EINVAL;
1225 }
1226 }
1227 chip->enable_dma = drv_data->controller_info->enable_dma;
1228 chip->timeout = TIMOUT_DFLT;
1229 }
1230
1231 /*
1232 * Protocol drivers may change the chip settings, so...
1233 * if chip_info exists, use it.
1234 */
1235 chip_info = spi->controller_data;
1236
1237 /* chip_info isn't always needed */
1238 if (chip_info) {
1239 if (chip_info->timeout)
1240 chip->timeout = chip_info->timeout;
1241 if (chip_info->tx_threshold)
1242 tx_thres = chip_info->tx_threshold;
1243 if (chip_info->tx_hi_threshold)
1244 tx_hi_thres = chip_info->tx_hi_threshold;
1245 if (chip_info->rx_threshold)
1246 rx_thres = chip_info->rx_threshold;
1247 chip->dma_threshold = 0;
1248 }
1249
1250 chip->cr1 = 0;
1251 if (spi_controller_is_slave(drv_data->controller)) {
1252 chip->cr1 |= SSCR1_SCFR;
1253 chip->cr1 |= SSCR1_SCLKDIR;
1254 chip->cr1 |= SSCR1_SFRMDIR;
1255 chip->cr1 |= SSCR1_SPH;
1256 }
1257
1258 if (is_lpss_ssp(drv_data)) {
1259 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1260 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1261 SSITF_TxHiThresh(tx_hi_thres);
1262 }
1263
1264 if (is_mrfld_ssp(drv_data)) {
1265 chip->lpss_rx_threshold = rx_thres;
1266 chip->lpss_tx_threshold = tx_thres;
1267 }
1268
1269 /*
1270 * Set DMA burst and threshold outside of chip_info path so that if
1271 * chip_info goes away after setting chip->enable_dma, the burst and
1272 * threshold can still respond to changes in bits_per_word.
1273 */
1274 if (chip->enable_dma) {
1275 /* Set up legal burst and threshold for DMA */
1276 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1277 spi->bits_per_word,
1278 &chip->dma_burst_size,
1279 &chip->dma_threshold)) {
1280 dev_warn(&spi->dev,
1281 "in setup: DMA burst size reduced to match bits_per_word\n");
1282 }
1283 dev_dbg(&spi->dev,
1284 "in setup: DMA burst size set to %u\n",
1285 chip->dma_burst_size);
1286 }
1287
1288 switch (drv_data->ssp_type) {
1289 case QUARK_X1000_SSP:
1290 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1291 & QUARK_X1000_SSCR1_RFT)
1292 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1293 & QUARK_X1000_SSCR1_TFT);
1294 break;
1295 case CE4100_SSP:
1296 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1297 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1298 break;
1299 default:
1300 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1301 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1302 break;
1303 }
1304
1305 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1306 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1307 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1308
1309 if (spi->mode & SPI_LOOP)
1310 chip->cr1 |= SSCR1_LBM;
1311
1312 spi_set_ctldata(spi, chip);
1313
1314 return 0;
1315}
1316
1317static void cleanup(struct spi_device *spi)
1318{
1319 struct chip_data *chip = spi_get_ctldata(spi);
1320
1321 kfree(chip);
1322}
1323
1324static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1325{
1326 return param == chan->device->dev;
1327}
1328
1329static struct pxa2xx_spi_controller *
1330pxa2xx_spi_init_pdata(struct platform_device *pdev)
1331{
1332 struct pxa2xx_spi_controller *pdata;
1333 struct device *dev = &pdev->dev;
1334 struct device *parent = dev->parent;
1335 struct ssp_device *ssp;
1336 struct resource *res;
1337 enum pxa_ssp_type type = SSP_UNDEFINED;
1338 const void *match;
1339 bool is_lpss_priv;
1340 int status;
1341 u64 uid;
1342
1343 is_lpss_priv = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpss_priv");
1344
1345 match = device_get_match_data(dev);
1346 if (match)
1347 type = (enum pxa_ssp_type)match;
1348 else if (is_lpss_priv) {
1349 u32 value;
1350
1351 status = device_property_read_u32(dev, "intel,spi-pxa2xx-type", &value);
1352 if (status)
1353 return ERR_PTR(status);
1354
1355 type = (enum pxa_ssp_type)value;
1356 }
1357
1358 /* Validate the SSP type correctness */
1359 if (!(type > SSP_UNDEFINED && type < SSP_MAX))
1360 return ERR_PTR(-EINVAL);
1361
1362 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1363 if (!pdata)
1364 return ERR_PTR(-ENOMEM);
1365
1366 ssp = &pdata->ssp;
1367
1368 ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1369 if (IS_ERR(ssp->mmio_base))
1370 return ERR_CAST(ssp->mmio_base);
1371
1372 ssp->phys_base = res->start;
1373
1374 /* Platforms with iDMA 64-bit */
1375 if (is_lpss_priv) {
1376 pdata->tx_param = parent;
1377 pdata->rx_param = parent;
1378 pdata->dma_filter = pxa2xx_spi_idma_filter;
1379 }
1380
1381 ssp->clk = devm_clk_get(dev, NULL);
1382 if (IS_ERR(ssp->clk))
1383 return ERR_CAST(ssp->clk);
1384
1385 ssp->irq = platform_get_irq(pdev, 0);
1386 if (ssp->irq < 0)
1387 return ERR_PTR(ssp->irq);
1388
1389 ssp->type = type;
1390 ssp->dev = dev;
1391
1392 status = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &uid);
1393 if (status)
1394 ssp->port_id = -1;
1395 else
1396 ssp->port_id = uid;
1397
1398 pdata->is_slave = device_property_read_bool(dev, "spi-slave");
1399 pdata->num_chipselect = 1;
1400 pdata->enable_dma = true;
1401 pdata->dma_burst_size = 1;
1402
1403 return pdata;
1404}
1405
1406static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1407 unsigned int cs)
1408{
1409 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1410
1411 if (has_acpi_companion(drv_data->ssp->dev)) {
1412 switch (drv_data->ssp_type) {
1413 /*
1414 * For Atoms the ACPI DeviceSelection used by the Windows
1415 * driver starts from 1 instead of 0 so translate it here
1416 * to match what Linux expects.
1417 */
1418 case LPSS_BYT_SSP:
1419 case LPSS_BSW_SSP:
1420 return cs - 1;
1421
1422 default:
1423 break;
1424 }
1425 }
1426
1427 return cs;
1428}
1429
1430static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1431{
1432 return MAX_DMA_LEN;
1433}
1434
1435static int pxa2xx_spi_probe(struct platform_device *pdev)
1436{
1437 struct device *dev = &pdev->dev;
1438 struct pxa2xx_spi_controller *platform_info;
1439 struct spi_controller *controller;
1440 struct driver_data *drv_data;
1441 struct ssp_device *ssp;
1442 const struct lpss_config *config;
1443 int status;
1444 u32 tmp;
1445
1446 platform_info = dev_get_platdata(dev);
1447 if (!platform_info) {
1448 platform_info = pxa2xx_spi_init_pdata(pdev);
1449 if (IS_ERR(platform_info)) {
1450 dev_err(&pdev->dev, "missing platform data\n");
1451 return PTR_ERR(platform_info);
1452 }
1453 }
1454
1455 ssp = pxa_ssp_request(pdev->id, pdev->name);
1456 if (!ssp)
1457 ssp = &platform_info->ssp;
1458
1459 if (!ssp->mmio_base) {
1460 dev_err(&pdev->dev, "failed to get SSP\n");
1461 return -ENODEV;
1462 }
1463
1464 if (platform_info->is_slave)
1465 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1466 else
1467 controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1468
1469 if (!controller) {
1470 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1471 status = -ENOMEM;
1472 goto out_error_controller_alloc;
1473 }
1474 drv_data = spi_controller_get_devdata(controller);
1475 drv_data->controller = controller;
1476 drv_data->controller_info = platform_info;
1477 drv_data->ssp = ssp;
1478
1479 device_set_node(&controller->dev, dev_fwnode(dev));
1480
1481 /* The spi->mode bits understood by this driver: */
1482 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1483
1484 controller->bus_num = ssp->port_id;
1485 controller->dma_alignment = DMA_ALIGNMENT;
1486 controller->cleanup = cleanup;
1487 controller->setup = setup;
1488 controller->set_cs = pxa2xx_spi_set_cs;
1489 controller->transfer_one = pxa2xx_spi_transfer_one;
1490 controller->slave_abort = pxa2xx_spi_slave_abort;
1491 controller->handle_err = pxa2xx_spi_handle_err;
1492 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1493 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1494 controller->auto_runtime_pm = true;
1495 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1496
1497 drv_data->ssp_type = ssp->type;
1498
1499 if (pxa25x_ssp_comp(drv_data)) {
1500 switch (drv_data->ssp_type) {
1501 case QUARK_X1000_SSP:
1502 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1503 break;
1504 default:
1505 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1506 break;
1507 }
1508
1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1510 drv_data->dma_cr1 = 0;
1511 drv_data->clear_sr = SSSR_ROR;
1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1513 } else {
1514 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1516 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1519 | SSSR_ROR | SSSR_TUR;
1520 }
1521
1522 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1523 drv_data);
1524 if (status < 0) {
1525 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1526 goto out_error_controller_alloc;
1527 }
1528
1529 /* Setup DMA if requested */
1530 if (platform_info->enable_dma) {
1531 status = pxa2xx_spi_dma_setup(drv_data);
1532 if (status) {
1533 dev_warn(dev, "no DMA channels available, using PIO\n");
1534 platform_info->enable_dma = false;
1535 } else {
1536 controller->can_dma = pxa2xx_spi_can_dma;
1537 controller->max_dma_len = MAX_DMA_LEN;
1538 controller->max_transfer_size =
1539 pxa2xx_spi_max_dma_transfer_size;
1540 }
1541 }
1542
1543 /* Enable SOC clock */
1544 status = clk_prepare_enable(ssp->clk);
1545 if (status)
1546 goto out_error_dma_irq_alloc;
1547
1548 controller->max_speed_hz = clk_get_rate(ssp->clk);
1549 /*
1550 * Set minimum speed for all other platforms than Intel Quark which is
1551 * able do under 1 Hz transfers.
1552 */
1553 if (!pxa25x_ssp_comp(drv_data))
1554 controller->min_speed_hz =
1555 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1556 else if (!is_quark_x1000_ssp(drv_data))
1557 controller->min_speed_hz =
1558 DIV_ROUND_UP(controller->max_speed_hz, 512);
1559
1560 pxa_ssp_disable(ssp);
1561
1562 /* Load default SSP configuration */
1563 switch (drv_data->ssp_type) {
1564 case QUARK_X1000_SSP:
1565 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1566 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1567 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1568
1569 /* Using the Motorola SPI protocol and use 8 bit frame */
1570 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1571 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1572 break;
1573 case CE4100_SSP:
1574 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1575 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1576 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1577 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1578 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1579 break;
1580 default:
1581
1582 if (spi_controller_is_slave(controller)) {
1583 tmp = SSCR1_SCFR |
1584 SSCR1_SCLKDIR |
1585 SSCR1_SFRMDIR |
1586 SSCR1_RxTresh(2) |
1587 SSCR1_TxTresh(1) |
1588 SSCR1_SPH;
1589 } else {
1590 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1591 SSCR1_TxTresh(TX_THRESH_DFLT);
1592 }
1593 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1594 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1595 if (!spi_controller_is_slave(controller))
1596 tmp |= SSCR0_SCR(2);
1597 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1598 break;
1599 }
1600
1601 if (!pxa25x_ssp_comp(drv_data))
1602 pxa2xx_spi_write(drv_data, SSTO, 0);
1603
1604 if (!is_quark_x1000_ssp(drv_data))
1605 pxa2xx_spi_write(drv_data, SSPSP, 0);
1606
1607 if (is_lpss_ssp(drv_data)) {
1608 lpss_ssp_setup(drv_data);
1609 config = lpss_get_config(drv_data);
1610 if (config->reg_capabilities >= 0) {
1611 tmp = __lpss_ssp_read_priv(drv_data,
1612 config->reg_capabilities);
1613 tmp &= LPSS_CAPS_CS_EN_MASK;
1614 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1615 platform_info->num_chipselect = ffz(tmp);
1616 } else if (config->cs_num) {
1617 platform_info->num_chipselect = config->cs_num;
1618 }
1619 }
1620 controller->num_chipselect = platform_info->num_chipselect;
1621 controller->use_gpio_descriptors = true;
1622
1623 if (platform_info->is_slave) {
1624 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1625 "ready", GPIOD_OUT_LOW);
1626 if (IS_ERR(drv_data->gpiod_ready)) {
1627 status = PTR_ERR(drv_data->gpiod_ready);
1628 goto out_error_clock_enabled;
1629 }
1630 }
1631
1632 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1633 pm_runtime_use_autosuspend(&pdev->dev);
1634 pm_runtime_set_active(&pdev->dev);
1635 pm_runtime_enable(&pdev->dev);
1636
1637 /* Register with the SPI framework */
1638 platform_set_drvdata(pdev, drv_data);
1639 status = spi_register_controller(controller);
1640 if (status) {
1641 dev_err(&pdev->dev, "problem registering SPI controller\n");
1642 goto out_error_pm_runtime_enabled;
1643 }
1644
1645 return status;
1646
1647out_error_pm_runtime_enabled:
1648 pm_runtime_disable(&pdev->dev);
1649
1650out_error_clock_enabled:
1651 clk_disable_unprepare(ssp->clk);
1652
1653out_error_dma_irq_alloc:
1654 pxa2xx_spi_dma_release(drv_data);
1655 free_irq(ssp->irq, drv_data);
1656
1657out_error_controller_alloc:
1658 pxa_ssp_free(ssp);
1659 return status;
1660}
1661
1662static int pxa2xx_spi_remove(struct platform_device *pdev)
1663{
1664 struct driver_data *drv_data = platform_get_drvdata(pdev);
1665 struct ssp_device *ssp = drv_data->ssp;
1666
1667 pm_runtime_get_sync(&pdev->dev);
1668
1669 spi_unregister_controller(drv_data->controller);
1670
1671 /* Disable the SSP at the peripheral and SOC level */
1672 pxa_ssp_disable(ssp);
1673 clk_disable_unprepare(ssp->clk);
1674
1675 /* Release DMA */
1676 if (drv_data->controller_info->enable_dma)
1677 pxa2xx_spi_dma_release(drv_data);
1678
1679 pm_runtime_put_noidle(&pdev->dev);
1680 pm_runtime_disable(&pdev->dev);
1681
1682 /* Release IRQ */
1683 free_irq(ssp->irq, drv_data);
1684
1685 /* Release SSP */
1686 pxa_ssp_free(ssp);
1687
1688 return 0;
1689}
1690
1691static int pxa2xx_spi_suspend(struct device *dev)
1692{
1693 struct driver_data *drv_data = dev_get_drvdata(dev);
1694 struct ssp_device *ssp = drv_data->ssp;
1695 int status;
1696
1697 status = spi_controller_suspend(drv_data->controller);
1698 if (status)
1699 return status;
1700
1701 pxa_ssp_disable(ssp);
1702
1703 if (!pm_runtime_suspended(dev))
1704 clk_disable_unprepare(ssp->clk);
1705
1706 return 0;
1707}
1708
1709static int pxa2xx_spi_resume(struct device *dev)
1710{
1711 struct driver_data *drv_data = dev_get_drvdata(dev);
1712 struct ssp_device *ssp = drv_data->ssp;
1713 int status;
1714
1715 /* Enable the SSP clock */
1716 if (!pm_runtime_suspended(dev)) {
1717 status = clk_prepare_enable(ssp->clk);
1718 if (status)
1719 return status;
1720 }
1721
1722 /* Start the queue running */
1723 return spi_controller_resume(drv_data->controller);
1724}
1725
1726static int pxa2xx_spi_runtime_suspend(struct device *dev)
1727{
1728 struct driver_data *drv_data = dev_get_drvdata(dev);
1729
1730 clk_disable_unprepare(drv_data->ssp->clk);
1731 return 0;
1732}
1733
1734static int pxa2xx_spi_runtime_resume(struct device *dev)
1735{
1736 struct driver_data *drv_data = dev_get_drvdata(dev);
1737
1738 return clk_prepare_enable(drv_data->ssp->clk);
1739}
1740
1741static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1742 SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1743 RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1744};
1745
1746#ifdef CONFIG_ACPI
1747static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1748 { "80860F0E", LPSS_BYT_SSP },
1749 { "8086228E", LPSS_BSW_SSP },
1750 { "INT33C0", LPSS_LPT_SSP },
1751 { "INT33C1", LPSS_LPT_SSP },
1752 { "INT3430", LPSS_LPT_SSP },
1753 { "INT3431", LPSS_LPT_SSP },
1754 {}
1755};
1756MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1757#endif
1758
1759static const struct of_device_id pxa2xx_spi_of_match[] = {
1760 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1761 {}
1762};
1763MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1764
1765static struct platform_driver driver = {
1766 .driver = {
1767 .name = "pxa2xx-spi",
1768 .pm = pm_ptr(&pxa2xx_spi_pm_ops),
1769 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1770 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1771 },
1772 .probe = pxa2xx_spi_probe,
1773 .remove = pxa2xx_spi_remove,
1774};
1775
1776static int __init pxa2xx_spi_init(void)
1777{
1778 return platform_driver_register(&driver);
1779}
1780subsys_initcall(pxa2xx_spi_init);
1781
1782static void __exit pxa2xx_spi_exit(void)
1783{
1784 platform_driver_unregister(&driver);
1785}
1786module_exit(pxa2xx_spi_exit);
1787
1788MODULE_SOFTDEP("pre: dw_dmac");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, Intel Corporation
5 */
6
7#include <linux/acpi.h>
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/errno.h>
14#include <linux/gpio/consumer.h>
15#include <linux/gpio.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/mod_devicetable.h>
22#include <linux/of.h>
23#include <linux/pci.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/property.h>
27#include <linux/slab.h>
28#include <linux/spi/pxa2xx_spi.h>
29#include <linux/spi/spi.h>
30
31#include "spi-pxa2xx.h"
32
33MODULE_AUTHOR("Stephen Street");
34MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
35MODULE_LICENSE("GPL");
36MODULE_ALIAS("platform:pxa2xx-spi");
37
38#define TIMOUT_DFLT 1000
39
40/*
41 * for testing SSCR1 changes that require SSP restart, basically
42 * everything except the service and interrupt enables, the pxa270 developer
43 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
44 * list, but the PXA255 dev man says all bits without really meaning the
45 * service and interrupt enables
46 */
47#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
48 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
49 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
50 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
51 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
53
54#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
55 | QUARK_X1000_SSCR1_EFWR \
56 | QUARK_X1000_SSCR1_RFT \
57 | QUARK_X1000_SSCR1_TFT \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59
60#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
68#define LPSS_CS_CONTROL_SW_MODE BIT(0)
69#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
73#define LPSS_PRIV_CLOCK_GATE 0x38
74#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
75#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
76
77struct lpss_config {
78 /* LPSS offset from drv_data->ioaddr */
79 unsigned offset;
80 /* Register offsets from drv_data->lpss_base or -1 */
81 int reg_general;
82 int reg_ssp;
83 int reg_cs_ctrl;
84 int reg_capabilities;
85 /* FIFO thresholds */
86 u32 rx_threshold;
87 u32 tx_threshold_lo;
88 u32 tx_threshold_hi;
89 /* Chip select control */
90 unsigned cs_sel_shift;
91 unsigned cs_sel_mask;
92 unsigned cs_num;
93 /* Quirks */
94 unsigned cs_clk_stays_gated : 1;
95};
96
97/* Keep these sorted with enum pxa_ssp_type */
98static const struct lpss_config lpss_platforms[] = {
99 { /* LPSS_LPT_SSP */
100 .offset = 0x800,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
109 { /* LPSS_BYT_SSP */
110 .offset = 0x400,
111 .reg_general = 0x08,
112 .reg_ssp = 0x0c,
113 .reg_cs_ctrl = 0x18,
114 .reg_capabilities = -1,
115 .rx_threshold = 64,
116 .tx_threshold_lo = 160,
117 .tx_threshold_hi = 224,
118 },
119 { /* LPSS_BSW_SSP */
120 .offset = 0x400,
121 .reg_general = 0x08,
122 .reg_ssp = 0x0c,
123 .reg_cs_ctrl = 0x18,
124 .reg_capabilities = -1,
125 .rx_threshold = 64,
126 .tx_threshold_lo = 160,
127 .tx_threshold_hi = 224,
128 .cs_sel_shift = 2,
129 .cs_sel_mask = 1 << 2,
130 .cs_num = 2,
131 },
132 { /* LPSS_SPT_SSP */
133 .offset = 0x200,
134 .reg_general = -1,
135 .reg_ssp = 0x20,
136 .reg_cs_ctrl = 0x24,
137 .reg_capabilities = -1,
138 .rx_threshold = 1,
139 .tx_threshold_lo = 32,
140 .tx_threshold_hi = 56,
141 },
142 { /* LPSS_BXT_SSP */
143 .offset = 0x200,
144 .reg_general = -1,
145 .reg_ssp = 0x20,
146 .reg_cs_ctrl = 0x24,
147 .reg_capabilities = 0xfc,
148 .rx_threshold = 1,
149 .tx_threshold_lo = 16,
150 .tx_threshold_hi = 48,
151 .cs_sel_shift = 8,
152 .cs_sel_mask = 3 << 8,
153 .cs_clk_stays_gated = true,
154 },
155 { /* LPSS_CNL_SSP */
156 .offset = 0x200,
157 .reg_general = -1,
158 .reg_ssp = 0x20,
159 .reg_cs_ctrl = 0x24,
160 .reg_capabilities = 0xfc,
161 .rx_threshold = 1,
162 .tx_threshold_lo = 32,
163 .tx_threshold_hi = 56,
164 .cs_sel_shift = 8,
165 .cs_sel_mask = 3 << 8,
166 .cs_clk_stays_gated = true,
167 },
168};
169
170static inline const struct lpss_config
171*lpss_get_config(const struct driver_data *drv_data)
172{
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
174}
175
176static bool is_lpss_ssp(const struct driver_data *drv_data)
177{
178 switch (drv_data->ssp_type) {
179 case LPSS_LPT_SSP:
180 case LPSS_BYT_SSP:
181 case LPSS_BSW_SSP:
182 case LPSS_SPT_SSP:
183 case LPSS_BXT_SSP:
184 case LPSS_CNL_SSP:
185 return true;
186 default:
187 return false;
188 }
189}
190
191static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
192{
193 return drv_data->ssp_type == QUARK_X1000_SSP;
194}
195
196static bool is_mmp2_ssp(const struct driver_data *drv_data)
197{
198 return drv_data->ssp_type == MMP2_SSP;
199}
200
201static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
202{
203 switch (drv_data->ssp_type) {
204 case QUARK_X1000_SSP:
205 return QUARK_X1000_SSCR1_CHANGE_MASK;
206 case CE4100_SSP:
207 return CE4100_SSCR1_CHANGE_MASK;
208 default:
209 return SSCR1_CHANGE_MASK;
210 }
211}
212
213static u32
214pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
215{
216 switch (drv_data->ssp_type) {
217 case QUARK_X1000_SSP:
218 return RX_THRESH_QUARK_X1000_DFLT;
219 case CE4100_SSP:
220 return RX_THRESH_CE4100_DFLT;
221 default:
222 return RX_THRESH_DFLT;
223 }
224}
225
226static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
227{
228 u32 mask;
229
230 switch (drv_data->ssp_type) {
231 case QUARK_X1000_SSP:
232 mask = QUARK_X1000_SSSR_TFL_MASK;
233 break;
234 case CE4100_SSP:
235 mask = CE4100_SSSR_TFL_MASK;
236 break;
237 default:
238 mask = SSSR_TFL_MASK;
239 break;
240 }
241
242 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
243}
244
245static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
246 u32 *sccr1_reg)
247{
248 u32 mask;
249
250 switch (drv_data->ssp_type) {
251 case QUARK_X1000_SSP:
252 mask = QUARK_X1000_SSCR1_RFT;
253 break;
254 case CE4100_SSP:
255 mask = CE4100_SSCR1_RFT;
256 break;
257 default:
258 mask = SSCR1_RFT;
259 break;
260 }
261 *sccr1_reg &= ~mask;
262}
263
264static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
265 u32 *sccr1_reg, u32 threshold)
266{
267 switch (drv_data->ssp_type) {
268 case QUARK_X1000_SSP:
269 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
270 break;
271 case CE4100_SSP:
272 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
273 break;
274 default:
275 *sccr1_reg |= SSCR1_RxTresh(threshold);
276 break;
277 }
278}
279
280static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
281 u32 clk_div, u8 bits)
282{
283 switch (drv_data->ssp_type) {
284 case QUARK_X1000_SSP:
285 return clk_div
286 | QUARK_X1000_SSCR0_Motorola
287 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
288 | SSCR0_SSE;
289 default:
290 return clk_div
291 | SSCR0_Motorola
292 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
293 | SSCR0_SSE
294 | (bits > 16 ? SSCR0_EDSS : 0);
295 }
296}
297
298/*
299 * Read and write LPSS SSP private registers. Caller must first check that
300 * is_lpss_ssp() returns true before these can be called.
301 */
302static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
303{
304 WARN_ON(!drv_data->lpss_base);
305 return readl(drv_data->lpss_base + offset);
306}
307
308static void __lpss_ssp_write_priv(struct driver_data *drv_data,
309 unsigned offset, u32 value)
310{
311 WARN_ON(!drv_data->lpss_base);
312 writel(value, drv_data->lpss_base + offset);
313}
314
315/*
316 * lpss_ssp_setup - perform LPSS SSP specific setup
317 * @drv_data: pointer to the driver private data
318 *
319 * Perform LPSS SSP specific setup. This function must be called first if
320 * one is going to use LPSS SSP private registers.
321 */
322static void lpss_ssp_setup(struct driver_data *drv_data)
323{
324 const struct lpss_config *config;
325 u32 value;
326
327 config = lpss_get_config(drv_data);
328 drv_data->lpss_base = drv_data->ioaddr + config->offset;
329
330 /* Enable software chip select control */
331 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
332 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
333 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
334 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
335
336 /* Enable multiblock DMA transfers */
337 if (drv_data->controller_info->enable_dma) {
338 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
339
340 if (config->reg_general >= 0) {
341 value = __lpss_ssp_read_priv(drv_data,
342 config->reg_general);
343 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
344 __lpss_ssp_write_priv(drv_data,
345 config->reg_general, value);
346 }
347 }
348}
349
350static void lpss_ssp_select_cs(struct spi_device *spi,
351 const struct lpss_config *config)
352{
353 struct driver_data *drv_data =
354 spi_controller_get_devdata(spi->controller);
355 u32 value, cs;
356
357 if (!config->cs_sel_mask)
358 return;
359
360 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
361
362 cs = spi->chip_select;
363 cs <<= config->cs_sel_shift;
364 if (cs != (value & config->cs_sel_mask)) {
365 /*
366 * When switching another chip select output active the
367 * output must be selected first and wait 2 ssp_clk cycles
368 * before changing state to active. Otherwise a short
369 * glitch will occur on the previous chip select since
370 * output select is latched but state control is not.
371 */
372 value &= ~config->cs_sel_mask;
373 value |= cs;
374 __lpss_ssp_write_priv(drv_data,
375 config->reg_cs_ctrl, value);
376 ndelay(1000000000 /
377 (drv_data->controller->max_speed_hz / 2));
378 }
379}
380
381static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
382{
383 struct driver_data *drv_data =
384 spi_controller_get_devdata(spi->controller);
385 const struct lpss_config *config;
386 u32 value;
387
388 config = lpss_get_config(drv_data);
389
390 if (enable)
391 lpss_ssp_select_cs(spi, config);
392
393 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
394 if (enable)
395 value &= ~LPSS_CS_CONTROL_CS_HIGH;
396 else
397 value |= LPSS_CS_CONTROL_CS_HIGH;
398 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
399 if (config->cs_clk_stays_gated) {
400 u32 clkgate;
401
402 /*
403 * Changing CS alone when dynamic clock gating is on won't
404 * actually flip CS at that time. This ruins SPI transfers
405 * that specify delays, or have no data. Toggle the clock mode
406 * to force on briefly to poke the CS pin to move.
407 */
408 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
409 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
410 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
411
412 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
413 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
414 }
415}
416
417static void cs_assert(struct spi_device *spi)
418{
419 struct chip_data *chip = spi_get_ctldata(spi);
420 struct driver_data *drv_data =
421 spi_controller_get_devdata(spi->controller);
422
423 if (drv_data->ssp_type == CE4100_SSP) {
424 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
425 return;
426 }
427
428 if (chip->cs_control) {
429 chip->cs_control(PXA2XX_CS_ASSERT);
430 return;
431 }
432
433 if (chip->gpiod_cs) {
434 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
435 return;
436 }
437
438 if (is_lpss_ssp(drv_data))
439 lpss_ssp_cs_control(spi, true);
440}
441
442static void cs_deassert(struct spi_device *spi)
443{
444 struct chip_data *chip = spi_get_ctldata(spi);
445 struct driver_data *drv_data =
446 spi_controller_get_devdata(spi->controller);
447 unsigned long timeout;
448
449 if (drv_data->ssp_type == CE4100_SSP)
450 return;
451
452 /* Wait until SSP becomes idle before deasserting the CS */
453 timeout = jiffies + msecs_to_jiffies(10);
454 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
455 !time_after(jiffies, timeout))
456 cpu_relax();
457
458 if (chip->cs_control) {
459 chip->cs_control(PXA2XX_CS_DEASSERT);
460 return;
461 }
462
463 if (chip->gpiod_cs) {
464 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
465 return;
466 }
467
468 if (is_lpss_ssp(drv_data))
469 lpss_ssp_cs_control(spi, false);
470}
471
472static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
473{
474 if (level)
475 cs_deassert(spi);
476 else
477 cs_assert(spi);
478}
479
480int pxa2xx_spi_flush(struct driver_data *drv_data)
481{
482 unsigned long limit = loops_per_jiffy << 1;
483
484 do {
485 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
486 pxa2xx_spi_read(drv_data, SSDR);
487 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
488 write_SSSR_CS(drv_data, SSSR_ROR);
489
490 return limit;
491}
492
493static void pxa2xx_spi_off(struct driver_data *drv_data)
494{
495 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
496 if (is_mmp2_ssp(drv_data))
497 return;
498
499 pxa2xx_spi_write(drv_data, SSCR0,
500 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
501}
502
503static int null_writer(struct driver_data *drv_data)
504{
505 u8 n_bytes = drv_data->n_bytes;
506
507 if (pxa2xx_spi_txfifo_full(drv_data)
508 || (drv_data->tx == drv_data->tx_end))
509 return 0;
510
511 pxa2xx_spi_write(drv_data, SSDR, 0);
512 drv_data->tx += n_bytes;
513
514 return 1;
515}
516
517static int null_reader(struct driver_data *drv_data)
518{
519 u8 n_bytes = drv_data->n_bytes;
520
521 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
522 && (drv_data->rx < drv_data->rx_end)) {
523 pxa2xx_spi_read(drv_data, SSDR);
524 drv_data->rx += n_bytes;
525 }
526
527 return drv_data->rx == drv_data->rx_end;
528}
529
530static int u8_writer(struct driver_data *drv_data)
531{
532 if (pxa2xx_spi_txfifo_full(drv_data)
533 || (drv_data->tx == drv_data->tx_end))
534 return 0;
535
536 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
537 ++drv_data->tx;
538
539 return 1;
540}
541
542static int u8_reader(struct driver_data *drv_data)
543{
544 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
545 && (drv_data->rx < drv_data->rx_end)) {
546 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
547 ++drv_data->rx;
548 }
549
550 return drv_data->rx == drv_data->rx_end;
551}
552
553static int u16_writer(struct driver_data *drv_data)
554{
555 if (pxa2xx_spi_txfifo_full(drv_data)
556 || (drv_data->tx == drv_data->tx_end))
557 return 0;
558
559 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
560 drv_data->tx += 2;
561
562 return 1;
563}
564
565static int u16_reader(struct driver_data *drv_data)
566{
567 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
568 && (drv_data->rx < drv_data->rx_end)) {
569 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
570 drv_data->rx += 2;
571 }
572
573 return drv_data->rx == drv_data->rx_end;
574}
575
576static int u32_writer(struct driver_data *drv_data)
577{
578 if (pxa2xx_spi_txfifo_full(drv_data)
579 || (drv_data->tx == drv_data->tx_end))
580 return 0;
581
582 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
583 drv_data->tx += 4;
584
585 return 1;
586}
587
588static int u32_reader(struct driver_data *drv_data)
589{
590 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
591 && (drv_data->rx < drv_data->rx_end)) {
592 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
593 drv_data->rx += 4;
594 }
595
596 return drv_data->rx == drv_data->rx_end;
597}
598
599static void reset_sccr1(struct driver_data *drv_data)
600{
601 struct chip_data *chip =
602 spi_get_ctldata(drv_data->controller->cur_msg->spi);
603 u32 sccr1_reg;
604
605 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
606 switch (drv_data->ssp_type) {
607 case QUARK_X1000_SSP:
608 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
609 break;
610 case CE4100_SSP:
611 sccr1_reg &= ~CE4100_SSCR1_RFT;
612 break;
613 default:
614 sccr1_reg &= ~SSCR1_RFT;
615 break;
616 }
617 sccr1_reg |= chip->threshold;
618 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
619}
620
621static void int_error_stop(struct driver_data *drv_data, const char* msg)
622{
623 /* Stop and reset SSP */
624 write_SSSR_CS(drv_data, drv_data->clear_sr);
625 reset_sccr1(drv_data);
626 if (!pxa25x_ssp_comp(drv_data))
627 pxa2xx_spi_write(drv_data, SSTO, 0);
628 pxa2xx_spi_flush(drv_data);
629 pxa2xx_spi_off(drv_data);
630
631 dev_err(&drv_data->pdev->dev, "%s\n", msg);
632
633 drv_data->controller->cur_msg->status = -EIO;
634 spi_finalize_current_transfer(drv_data->controller);
635}
636
637static void int_transfer_complete(struct driver_data *drv_data)
638{
639 /* Clear and disable interrupts */
640 write_SSSR_CS(drv_data, drv_data->clear_sr);
641 reset_sccr1(drv_data);
642 if (!pxa25x_ssp_comp(drv_data))
643 pxa2xx_spi_write(drv_data, SSTO, 0);
644
645 spi_finalize_current_transfer(drv_data->controller);
646}
647
648static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
649{
650 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
651 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
652
653 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
654
655 if (irq_status & SSSR_ROR) {
656 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
657 return IRQ_HANDLED;
658 }
659
660 if (irq_status & SSSR_TUR) {
661 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
662 return IRQ_HANDLED;
663 }
664
665 if (irq_status & SSSR_TINT) {
666 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
667 if (drv_data->read(drv_data)) {
668 int_transfer_complete(drv_data);
669 return IRQ_HANDLED;
670 }
671 }
672
673 /* Drain rx fifo, Fill tx fifo and prevent overruns */
674 do {
675 if (drv_data->read(drv_data)) {
676 int_transfer_complete(drv_data);
677 return IRQ_HANDLED;
678 }
679 } while (drv_data->write(drv_data));
680
681 if (drv_data->read(drv_data)) {
682 int_transfer_complete(drv_data);
683 return IRQ_HANDLED;
684 }
685
686 if (drv_data->tx == drv_data->tx_end) {
687 u32 bytes_left;
688 u32 sccr1_reg;
689
690 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
691 sccr1_reg &= ~SSCR1_TIE;
692
693 /*
694 * PXA25x_SSP has no timeout, set up rx threshould for the
695 * remaining RX bytes.
696 */
697 if (pxa25x_ssp_comp(drv_data)) {
698 u32 rx_thre;
699
700 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
701
702 bytes_left = drv_data->rx_end - drv_data->rx;
703 switch (drv_data->n_bytes) {
704 case 4:
705 bytes_left >>= 2;
706 break;
707 case 2:
708 bytes_left >>= 1;
709 break;
710 }
711
712 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
713 if (rx_thre > bytes_left)
714 rx_thre = bytes_left;
715
716 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
717 }
718 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
719 }
720
721 /* We did something */
722 return IRQ_HANDLED;
723}
724
725static void handle_bad_msg(struct driver_data *drv_data)
726{
727 pxa2xx_spi_off(drv_data);
728 pxa2xx_spi_write(drv_data, SSCR1,
729 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
730 if (!pxa25x_ssp_comp(drv_data))
731 pxa2xx_spi_write(drv_data, SSTO, 0);
732 write_SSSR_CS(drv_data, drv_data->clear_sr);
733
734 dev_err(&drv_data->pdev->dev,
735 "bad message state in interrupt handler\n");
736}
737
738static irqreturn_t ssp_int(int irq, void *dev_id)
739{
740 struct driver_data *drv_data = dev_id;
741 u32 sccr1_reg;
742 u32 mask = drv_data->mask_sr;
743 u32 status;
744
745 /*
746 * The IRQ might be shared with other peripherals so we must first
747 * check that are we RPM suspended or not. If we are we assume that
748 * the IRQ was not for us (we shouldn't be RPM suspended when the
749 * interrupt is enabled).
750 */
751 if (pm_runtime_suspended(&drv_data->pdev->dev))
752 return IRQ_NONE;
753
754 /*
755 * If the device is not yet in RPM suspended state and we get an
756 * interrupt that is meant for another device, check if status bits
757 * are all set to one. That means that the device is already
758 * powered off.
759 */
760 status = pxa2xx_spi_read(drv_data, SSSR);
761 if (status == ~0)
762 return IRQ_NONE;
763
764 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
765
766 /* Ignore possible writes if we don't need to write */
767 if (!(sccr1_reg & SSCR1_TIE))
768 mask &= ~SSSR_TFS;
769
770 /* Ignore RX timeout interrupt if it is disabled */
771 if (!(sccr1_reg & SSCR1_TINTE))
772 mask &= ~SSSR_TINT;
773
774 if (!(status & mask))
775 return IRQ_NONE;
776
777 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
778 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
779
780 if (!drv_data->controller->cur_msg) {
781 handle_bad_msg(drv_data);
782 /* Never fail */
783 return IRQ_HANDLED;
784 }
785
786 return drv_data->transfer_handler(drv_data);
787}
788
789/*
790 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
791 * input frequency by fractions of 2^24. It also has a divider by 5.
792 *
793 * There are formulas to get baud rate value for given input frequency and
794 * divider parameters, such as DDS_CLK_RATE and SCR:
795 *
796 * Fsys = 200MHz
797 *
798 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
799 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
800 *
801 * DDS_CLK_RATE either 2^n or 2^n / 5.
802 * SCR is in range 0 .. 255
803 *
804 * Divisor = 5^i * 2^j * 2 * k
805 * i = [0, 1] i = 1 iff j = 0 or j > 3
806 * j = [0, 23] j = 0 iff i = 1
807 * k = [1, 256]
808 * Special case: j = 0, i = 1: Divisor = 2 / 5
809 *
810 * Accordingly to the specification the recommended values for DDS_CLK_RATE
811 * are:
812 * Case 1: 2^n, n = [0, 23]
813 * Case 2: 2^24 * 2 / 5 (0x666666)
814 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
815 *
816 * In all cases the lowest possible value is better.
817 *
818 * The function calculates parameters for all cases and chooses the one closest
819 * to the asked baud rate.
820 */
821static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
822{
823 unsigned long xtal = 200000000;
824 unsigned long fref = xtal / 2; /* mandatory division by 2,
825 see (2) */
826 /* case 3 */
827 unsigned long fref1 = fref / 2; /* case 1 */
828 unsigned long fref2 = fref * 2 / 5; /* case 2 */
829 unsigned long scale;
830 unsigned long q, q1, q2;
831 long r, r1, r2;
832 u32 mul;
833
834 /* Case 1 */
835
836 /* Set initial value for DDS_CLK_RATE */
837 mul = (1 << 24) >> 1;
838
839 /* Calculate initial quot */
840 q1 = DIV_ROUND_UP(fref1, rate);
841
842 /* Scale q1 if it's too big */
843 if (q1 > 256) {
844 /* Scale q1 to range [1, 512] */
845 scale = fls_long(q1 - 1);
846 if (scale > 9) {
847 q1 >>= scale - 9;
848 mul >>= scale - 9;
849 }
850
851 /* Round the result if we have a remainder */
852 q1 += q1 & 1;
853 }
854
855 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
856 scale = __ffs(q1);
857 q1 >>= scale;
858 mul >>= scale;
859
860 /* Get the remainder */
861 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
862
863 /* Case 2 */
864
865 q2 = DIV_ROUND_UP(fref2, rate);
866 r2 = abs(fref2 / q2 - rate);
867
868 /*
869 * Choose the best between two: less remainder we have the better. We
870 * can't go case 2 if q2 is greater than 256 since SCR register can
871 * hold only values 0 .. 255.
872 */
873 if (r2 >= r1 || q2 > 256) {
874 /* case 1 is better */
875 r = r1;
876 q = q1;
877 } else {
878 /* case 2 is better */
879 r = r2;
880 q = q2;
881 mul = (1 << 24) * 2 / 5;
882 }
883
884 /* Check case 3 only if the divisor is big enough */
885 if (fref / rate >= 80) {
886 u64 fssp;
887 u32 m;
888
889 /* Calculate initial quot */
890 q1 = DIV_ROUND_UP(fref, rate);
891 m = (1 << 24) / q1;
892
893 /* Get the remainder */
894 fssp = (u64)fref * m;
895 do_div(fssp, 1 << 24);
896 r1 = abs(fssp - rate);
897
898 /* Choose this one if it suits better */
899 if (r1 < r) {
900 /* case 3 is better */
901 q = 1;
902 mul = m;
903 }
904 }
905
906 *dds = mul;
907 return q - 1;
908}
909
910static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
911{
912 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
913 const struct ssp_device *ssp = drv_data->ssp;
914
915 rate = min_t(int, ssp_clk, rate);
916
917 /*
918 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
919 * that the SSP transmission rate can be greater than the device rate
920 */
921 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
922 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
923 else
924 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
925}
926
927static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
928 int rate)
929{
930 struct chip_data *chip =
931 spi_get_ctldata(drv_data->controller->cur_msg->spi);
932 unsigned int clk_div;
933
934 switch (drv_data->ssp_type) {
935 case QUARK_X1000_SSP:
936 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
937 break;
938 default:
939 clk_div = ssp_get_clk_div(drv_data, rate);
940 break;
941 }
942 return clk_div << 8;
943}
944
945static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
946 struct spi_device *spi,
947 struct spi_transfer *xfer)
948{
949 struct chip_data *chip = spi_get_ctldata(spi);
950
951 return chip->enable_dma &&
952 xfer->len <= MAX_DMA_LEN &&
953 xfer->len >= chip->dma_burst_size;
954}
955
956static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
957 struct spi_device *spi,
958 struct spi_transfer *transfer)
959{
960 struct driver_data *drv_data = spi_controller_get_devdata(controller);
961 struct spi_message *message = controller->cur_msg;
962 struct chip_data *chip = spi_get_ctldata(spi);
963 u32 dma_thresh = chip->dma_threshold;
964 u32 dma_burst = chip->dma_burst_size;
965 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
966 u32 clk_div;
967 u8 bits;
968 u32 speed;
969 u32 cr0;
970 u32 cr1;
971 int err;
972 int dma_mapped;
973
974 /* Check if we can DMA this transfer */
975 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
976
977 /* reject already-mapped transfers; PIO won't always work */
978 if (message->is_dma_mapped
979 || transfer->rx_dma || transfer->tx_dma) {
980 dev_err(&spi->dev,
981 "Mapped transfer length of %u is greater than %d\n",
982 transfer->len, MAX_DMA_LEN);
983 return -EINVAL;
984 }
985
986 /* warn ... we force this to PIO mode */
987 dev_warn_ratelimited(&spi->dev,
988 "DMA disabled for transfer length %ld greater than %d\n",
989 (long)transfer->len, MAX_DMA_LEN);
990 }
991
992 /* Setup the transfer state based on the type of transfer */
993 if (pxa2xx_spi_flush(drv_data) == 0) {
994 dev_err(&spi->dev, "Flush failed\n");
995 return -EIO;
996 }
997 drv_data->n_bytes = chip->n_bytes;
998 drv_data->tx = (void *)transfer->tx_buf;
999 drv_data->tx_end = drv_data->tx + transfer->len;
1000 drv_data->rx = transfer->rx_buf;
1001 drv_data->rx_end = drv_data->rx + transfer->len;
1002 drv_data->write = drv_data->tx ? chip->write : null_writer;
1003 drv_data->read = drv_data->rx ? chip->read : null_reader;
1004
1005 /* Change speed and bit per word on a per transfer */
1006 bits = transfer->bits_per_word;
1007 speed = transfer->speed_hz;
1008
1009 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1010
1011 if (bits <= 8) {
1012 drv_data->n_bytes = 1;
1013 drv_data->read = drv_data->read != null_reader ?
1014 u8_reader : null_reader;
1015 drv_data->write = drv_data->write != null_writer ?
1016 u8_writer : null_writer;
1017 } else if (bits <= 16) {
1018 drv_data->n_bytes = 2;
1019 drv_data->read = drv_data->read != null_reader ?
1020 u16_reader : null_reader;
1021 drv_data->write = drv_data->write != null_writer ?
1022 u16_writer : null_writer;
1023 } else if (bits <= 32) {
1024 drv_data->n_bytes = 4;
1025 drv_data->read = drv_data->read != null_reader ?
1026 u32_reader : null_reader;
1027 drv_data->write = drv_data->write != null_writer ?
1028 u32_writer : null_writer;
1029 }
1030 /*
1031 * if bits/word is changed in dma mode, then must check the
1032 * thresholds and burst also
1033 */
1034 if (chip->enable_dma) {
1035 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1036 spi,
1037 bits, &dma_burst,
1038 &dma_thresh))
1039 dev_warn_ratelimited(&spi->dev,
1040 "DMA burst size reduced to match bits_per_word\n");
1041 }
1042
1043 dma_mapped = controller->can_dma &&
1044 controller->can_dma(controller, spi, transfer) &&
1045 controller->cur_msg_mapped;
1046 if (dma_mapped) {
1047
1048 /* Ensure we have the correct interrupt handler */
1049 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1050
1051 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1052 if (err)
1053 return err;
1054
1055 /* Clear status and start DMA engine */
1056 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1057 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1058
1059 pxa2xx_spi_dma_start(drv_data);
1060 } else {
1061 /* Ensure we have the correct interrupt handler */
1062 drv_data->transfer_handler = interrupt_transfer;
1063
1064 /* Clear status */
1065 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1066 write_SSSR_CS(drv_data, drv_data->clear_sr);
1067 }
1068
1069 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1070 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1071 if (!pxa25x_ssp_comp(drv_data))
1072 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1073 controller->max_speed_hz
1074 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1075 dma_mapped ? "DMA" : "PIO");
1076 else
1077 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1078 controller->max_speed_hz / 2
1079 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1080 dma_mapped ? "DMA" : "PIO");
1081
1082 if (is_lpss_ssp(drv_data)) {
1083 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1084 != chip->lpss_rx_threshold)
1085 pxa2xx_spi_write(drv_data, SSIRF,
1086 chip->lpss_rx_threshold);
1087 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1088 != chip->lpss_tx_threshold)
1089 pxa2xx_spi_write(drv_data, SSITF,
1090 chip->lpss_tx_threshold);
1091 }
1092
1093 if (is_quark_x1000_ssp(drv_data) &&
1094 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1095 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1096
1097 /* see if we need to reload the config registers */
1098 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1099 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1100 != (cr1 & change_mask)) {
1101 /* stop the SSP, and update the other bits */
1102 if (!is_mmp2_ssp(drv_data))
1103 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1104 if (!pxa25x_ssp_comp(drv_data))
1105 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1106 /* first set CR1 without interrupt and service enables */
1107 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1108 /* restart the SSP */
1109 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1110
1111 } else {
1112 if (!pxa25x_ssp_comp(drv_data))
1113 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1114 }
1115
1116 if (is_mmp2_ssp(drv_data)) {
1117 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1118 & SSSR_TFL_MASK) >> 8;
1119
1120 if (tx_level) {
1121 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1122 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1123 tx_level);
1124 if (tx_level > transfer->len)
1125 tx_level = transfer->len;
1126 drv_data->tx += tx_level;
1127 }
1128 }
1129
1130 if (spi_controller_is_slave(controller)) {
1131 while (drv_data->write(drv_data))
1132 ;
1133 if (drv_data->gpiod_ready) {
1134 gpiod_set_value(drv_data->gpiod_ready, 1);
1135 udelay(1);
1136 gpiod_set_value(drv_data->gpiod_ready, 0);
1137 }
1138 }
1139
1140 /*
1141 * Release the data by enabling service requests and interrupts,
1142 * without changing any mode bits
1143 */
1144 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1145
1146 return 1;
1147}
1148
1149static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1150{
1151 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1152
1153 /* Stop and reset SSP */
1154 write_SSSR_CS(drv_data, drv_data->clear_sr);
1155 reset_sccr1(drv_data);
1156 if (!pxa25x_ssp_comp(drv_data))
1157 pxa2xx_spi_write(drv_data, SSTO, 0);
1158 pxa2xx_spi_flush(drv_data);
1159 pxa2xx_spi_off(drv_data);
1160
1161 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1162
1163 drv_data->controller->cur_msg->status = -EINTR;
1164 spi_finalize_current_transfer(drv_data->controller);
1165
1166 return 0;
1167}
1168
1169static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1170 struct spi_message *msg)
1171{
1172 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1173
1174 /* Disable the SSP */
1175 pxa2xx_spi_off(drv_data);
1176 /* Clear and disable interrupts and service requests */
1177 write_SSSR_CS(drv_data, drv_data->clear_sr);
1178 pxa2xx_spi_write(drv_data, SSCR1,
1179 pxa2xx_spi_read(drv_data, SSCR1)
1180 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1181 if (!pxa25x_ssp_comp(drv_data))
1182 pxa2xx_spi_write(drv_data, SSTO, 0);
1183
1184 /*
1185 * Stop the DMA if running. Note DMA callback handler may have unset
1186 * the dma_running already, which is fine as stopping is not needed
1187 * then but we shouldn't rely this flag for anything else than
1188 * stopping. For instance to differentiate between PIO and DMA
1189 * transfers.
1190 */
1191 if (atomic_read(&drv_data->dma_running))
1192 pxa2xx_spi_dma_stop(drv_data);
1193}
1194
1195static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1196{
1197 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1198
1199 /* Disable the SSP now */
1200 pxa2xx_spi_off(drv_data);
1201
1202 return 0;
1203}
1204
1205static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1206 struct pxa2xx_spi_chip *chip_info)
1207{
1208 struct driver_data *drv_data =
1209 spi_controller_get_devdata(spi->controller);
1210 struct gpio_desc *gpiod;
1211 int err = 0;
1212
1213 if (chip == NULL)
1214 return 0;
1215
1216 if (drv_data->cs_gpiods) {
1217 gpiod = drv_data->cs_gpiods[spi->chip_select];
1218 if (gpiod) {
1219 chip->gpiod_cs = gpiod;
1220 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1221 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1222 }
1223
1224 return 0;
1225 }
1226
1227 if (chip_info == NULL)
1228 return 0;
1229
1230 /* NOTE: setup() can be called multiple times, possibly with
1231 * different chip_info, release previously requested GPIO
1232 */
1233 if (chip->gpiod_cs) {
1234 gpiod_put(chip->gpiod_cs);
1235 chip->gpiod_cs = NULL;
1236 }
1237
1238 /* If (*cs_control) is provided, ignore GPIO chip select */
1239 if (chip_info->cs_control) {
1240 chip->cs_control = chip_info->cs_control;
1241 return 0;
1242 }
1243
1244 if (gpio_is_valid(chip_info->gpio_cs)) {
1245 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1246 if (err) {
1247 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1248 chip_info->gpio_cs);
1249 return err;
1250 }
1251
1252 gpiod = gpio_to_desc(chip_info->gpio_cs);
1253 chip->gpiod_cs = gpiod;
1254 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1255
1256 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1257 }
1258
1259 return err;
1260}
1261
1262static int setup(struct spi_device *spi)
1263{
1264 struct pxa2xx_spi_chip *chip_info;
1265 struct chip_data *chip;
1266 const struct lpss_config *config;
1267 struct driver_data *drv_data =
1268 spi_controller_get_devdata(spi->controller);
1269 uint tx_thres, tx_hi_thres, rx_thres;
1270
1271 switch (drv_data->ssp_type) {
1272 case QUARK_X1000_SSP:
1273 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1274 tx_hi_thres = 0;
1275 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1276 break;
1277 case CE4100_SSP:
1278 tx_thres = TX_THRESH_CE4100_DFLT;
1279 tx_hi_thres = 0;
1280 rx_thres = RX_THRESH_CE4100_DFLT;
1281 break;
1282 case LPSS_LPT_SSP:
1283 case LPSS_BYT_SSP:
1284 case LPSS_BSW_SSP:
1285 case LPSS_SPT_SSP:
1286 case LPSS_BXT_SSP:
1287 case LPSS_CNL_SSP:
1288 config = lpss_get_config(drv_data);
1289 tx_thres = config->tx_threshold_lo;
1290 tx_hi_thres = config->tx_threshold_hi;
1291 rx_thres = config->rx_threshold;
1292 break;
1293 default:
1294 tx_hi_thres = 0;
1295 if (spi_controller_is_slave(drv_data->controller)) {
1296 tx_thres = 1;
1297 rx_thres = 2;
1298 } else {
1299 tx_thres = TX_THRESH_DFLT;
1300 rx_thres = RX_THRESH_DFLT;
1301 }
1302 break;
1303 }
1304
1305 /* Only alloc on first setup */
1306 chip = spi_get_ctldata(spi);
1307 if (!chip) {
1308 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1309 if (!chip)
1310 return -ENOMEM;
1311
1312 if (drv_data->ssp_type == CE4100_SSP) {
1313 if (spi->chip_select > 4) {
1314 dev_err(&spi->dev,
1315 "failed setup: cs number must not be > 4.\n");
1316 kfree(chip);
1317 return -EINVAL;
1318 }
1319
1320 chip->frm = spi->chip_select;
1321 }
1322 chip->enable_dma = drv_data->controller_info->enable_dma;
1323 chip->timeout = TIMOUT_DFLT;
1324 }
1325
1326 /* protocol drivers may change the chip settings, so...
1327 * if chip_info exists, use it */
1328 chip_info = spi->controller_data;
1329
1330 /* chip_info isn't always needed */
1331 chip->cr1 = 0;
1332 if (chip_info) {
1333 if (chip_info->timeout)
1334 chip->timeout = chip_info->timeout;
1335 if (chip_info->tx_threshold)
1336 tx_thres = chip_info->tx_threshold;
1337 if (chip_info->tx_hi_threshold)
1338 tx_hi_thres = chip_info->tx_hi_threshold;
1339 if (chip_info->rx_threshold)
1340 rx_thres = chip_info->rx_threshold;
1341 chip->dma_threshold = 0;
1342 if (chip_info->enable_loopback)
1343 chip->cr1 = SSCR1_LBM;
1344 }
1345 if (spi_controller_is_slave(drv_data->controller)) {
1346 chip->cr1 |= SSCR1_SCFR;
1347 chip->cr1 |= SSCR1_SCLKDIR;
1348 chip->cr1 |= SSCR1_SFRMDIR;
1349 chip->cr1 |= SSCR1_SPH;
1350 }
1351
1352 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1353 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1354 | SSITF_TxHiThresh(tx_hi_thres);
1355
1356 /* set dma burst and threshold outside of chip_info path so that if
1357 * chip_info goes away after setting chip->enable_dma, the
1358 * burst and threshold can still respond to changes in bits_per_word */
1359 if (chip->enable_dma) {
1360 /* set up legal burst and threshold for dma */
1361 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1362 spi->bits_per_word,
1363 &chip->dma_burst_size,
1364 &chip->dma_threshold)) {
1365 dev_warn(&spi->dev,
1366 "in setup: DMA burst size reduced to match bits_per_word\n");
1367 }
1368 dev_dbg(&spi->dev,
1369 "in setup: DMA burst size set to %u\n",
1370 chip->dma_burst_size);
1371 }
1372
1373 switch (drv_data->ssp_type) {
1374 case QUARK_X1000_SSP:
1375 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1376 & QUARK_X1000_SSCR1_RFT)
1377 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1378 & QUARK_X1000_SSCR1_TFT);
1379 break;
1380 case CE4100_SSP:
1381 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1382 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1383 break;
1384 default:
1385 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1386 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1387 break;
1388 }
1389
1390 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1391 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1392 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1393
1394 if (spi->mode & SPI_LOOP)
1395 chip->cr1 |= SSCR1_LBM;
1396
1397 if (spi->bits_per_word <= 8) {
1398 chip->n_bytes = 1;
1399 chip->read = u8_reader;
1400 chip->write = u8_writer;
1401 } else if (spi->bits_per_word <= 16) {
1402 chip->n_bytes = 2;
1403 chip->read = u16_reader;
1404 chip->write = u16_writer;
1405 } else if (spi->bits_per_word <= 32) {
1406 chip->n_bytes = 4;
1407 chip->read = u32_reader;
1408 chip->write = u32_writer;
1409 }
1410
1411 spi_set_ctldata(spi, chip);
1412
1413 if (drv_data->ssp_type == CE4100_SSP)
1414 return 0;
1415
1416 return setup_cs(spi, chip, chip_info);
1417}
1418
1419static void cleanup(struct spi_device *spi)
1420{
1421 struct chip_data *chip = spi_get_ctldata(spi);
1422 struct driver_data *drv_data =
1423 spi_controller_get_devdata(spi->controller);
1424
1425 if (!chip)
1426 return;
1427
1428 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1429 chip->gpiod_cs)
1430 gpiod_put(chip->gpiod_cs);
1431
1432 kfree(chip);
1433}
1434
1435#ifdef CONFIG_ACPI
1436static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1437 { "INT33C0", LPSS_LPT_SSP },
1438 { "INT33C1", LPSS_LPT_SSP },
1439 { "INT3430", LPSS_LPT_SSP },
1440 { "INT3431", LPSS_LPT_SSP },
1441 { "80860F0E", LPSS_BYT_SSP },
1442 { "8086228E", LPSS_BSW_SSP },
1443 { },
1444};
1445MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1446#endif
1447
1448/*
1449 * PCI IDs of compound devices that integrate both host controller and private
1450 * integrated DMA engine. Please note these are not used in module
1451 * autoloading and probing in this module but matching the LPSS SSP type.
1452 */
1453static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1454 /* SPT-LP */
1455 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1456 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1457 /* SPT-H */
1458 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1459 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1460 /* KBL-H */
1461 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1462 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1463 /* CML-V */
1464 { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1465 { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1466 /* BXT A-Step */
1467 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1468 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1469 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1470 /* BXT B-Step */
1471 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1472 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1473 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1474 /* GLK */
1475 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1476 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1477 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1478 /* ICL-LP */
1479 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1480 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1481 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1482 /* EHL */
1483 { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1484 { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1485 { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1486 /* JSL */
1487 { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1488 { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1489 { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1490 /* TGL-H */
1491 { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
1492 { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
1493 { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
1494 { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
1495 /* APL */
1496 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1497 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1498 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1499 /* CNL-LP */
1500 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1501 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1502 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1503 /* CNL-H */
1504 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1505 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1506 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1507 /* CML-LP */
1508 { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1509 { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1510 { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1511 /* CML-H */
1512 { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1513 { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1514 { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1515 /* TGL-LP */
1516 { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1517 { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1518 { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1519 { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1520 { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1521 { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1522 { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1523 { },
1524};
1525
1526static const struct of_device_id pxa2xx_spi_of_match[] = {
1527 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1528 {},
1529};
1530MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1531
1532#ifdef CONFIG_ACPI
1533
1534static int pxa2xx_spi_get_port_id(struct device *dev)
1535{
1536 struct acpi_device *adev;
1537 unsigned int devid;
1538 int port_id = -1;
1539
1540 adev = ACPI_COMPANION(dev);
1541 if (adev && adev->pnp.unique_id &&
1542 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1543 port_id = devid;
1544 return port_id;
1545}
1546
1547#else /* !CONFIG_ACPI */
1548
1549static int pxa2xx_spi_get_port_id(struct device *dev)
1550{
1551 return -1;
1552}
1553
1554#endif /* CONFIG_ACPI */
1555
1556
1557#ifdef CONFIG_PCI
1558
1559static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1560{
1561 return param == chan->device->dev;
1562}
1563
1564#endif /* CONFIG_PCI */
1565
1566static struct pxa2xx_spi_controller *
1567pxa2xx_spi_init_pdata(struct platform_device *pdev)
1568{
1569 struct pxa2xx_spi_controller *pdata;
1570 struct ssp_device *ssp;
1571 struct resource *res;
1572 struct device *parent = pdev->dev.parent;
1573 struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1574 const struct pci_device_id *pcidev_id = NULL;
1575 enum pxa_ssp_type type;
1576 const void *match;
1577
1578 if (pcidev)
1579 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1580
1581 match = device_get_match_data(&pdev->dev);
1582 if (match)
1583 type = (enum pxa_ssp_type)match;
1584 else if (pcidev_id)
1585 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1586 else
1587 return ERR_PTR(-EINVAL);
1588
1589 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1590 if (!pdata)
1591 return ERR_PTR(-ENOMEM);
1592
1593 ssp = &pdata->ssp;
1594
1595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1596 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1597 if (IS_ERR(ssp->mmio_base))
1598 return ERR_CAST(ssp->mmio_base);
1599
1600 ssp->phys_base = res->start;
1601
1602#ifdef CONFIG_PCI
1603 if (pcidev_id) {
1604 pdata->tx_param = parent;
1605 pdata->rx_param = parent;
1606 pdata->dma_filter = pxa2xx_spi_idma_filter;
1607 }
1608#endif
1609
1610 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1611 if (IS_ERR(ssp->clk))
1612 return ERR_CAST(ssp->clk);
1613
1614 ssp->irq = platform_get_irq(pdev, 0);
1615 if (ssp->irq < 0)
1616 return ERR_PTR(ssp->irq);
1617
1618 ssp->type = type;
1619 ssp->dev = &pdev->dev;
1620 ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1621
1622 pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1623 pdata->num_chipselect = 1;
1624 pdata->enable_dma = true;
1625 pdata->dma_burst_size = 1;
1626
1627 return pdata;
1628}
1629
1630static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1631 unsigned int cs)
1632{
1633 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1634
1635 if (has_acpi_companion(&drv_data->pdev->dev)) {
1636 switch (drv_data->ssp_type) {
1637 /*
1638 * For Atoms the ACPI DeviceSelection used by the Windows
1639 * driver starts from 1 instead of 0 so translate it here
1640 * to match what Linux expects.
1641 */
1642 case LPSS_BYT_SSP:
1643 case LPSS_BSW_SSP:
1644 return cs - 1;
1645
1646 default:
1647 break;
1648 }
1649 }
1650
1651 return cs;
1652}
1653
1654static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1655{
1656 return MAX_DMA_LEN;
1657}
1658
1659static int pxa2xx_spi_probe(struct platform_device *pdev)
1660{
1661 struct device *dev = &pdev->dev;
1662 struct pxa2xx_spi_controller *platform_info;
1663 struct spi_controller *controller;
1664 struct driver_data *drv_data;
1665 struct ssp_device *ssp;
1666 const struct lpss_config *config;
1667 int status, count;
1668 u32 tmp;
1669
1670 platform_info = dev_get_platdata(dev);
1671 if (!platform_info) {
1672 platform_info = pxa2xx_spi_init_pdata(pdev);
1673 if (IS_ERR(platform_info)) {
1674 dev_err(&pdev->dev, "missing platform data\n");
1675 return PTR_ERR(platform_info);
1676 }
1677 }
1678
1679 ssp = pxa_ssp_request(pdev->id, pdev->name);
1680 if (!ssp)
1681 ssp = &platform_info->ssp;
1682
1683 if (!ssp->mmio_base) {
1684 dev_err(&pdev->dev, "failed to get ssp\n");
1685 return -ENODEV;
1686 }
1687
1688 if (platform_info->is_slave)
1689 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1690 else
1691 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1692
1693 if (!controller) {
1694 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1695 pxa_ssp_free(ssp);
1696 return -ENOMEM;
1697 }
1698 drv_data = spi_controller_get_devdata(controller);
1699 drv_data->controller = controller;
1700 drv_data->controller_info = platform_info;
1701 drv_data->pdev = pdev;
1702 drv_data->ssp = ssp;
1703
1704 controller->dev.of_node = pdev->dev.of_node;
1705 /* the spi->mode bits understood by this driver: */
1706 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1707
1708 controller->bus_num = ssp->port_id;
1709 controller->dma_alignment = DMA_ALIGNMENT;
1710 controller->cleanup = cleanup;
1711 controller->setup = setup;
1712 controller->set_cs = pxa2xx_spi_set_cs;
1713 controller->transfer_one = pxa2xx_spi_transfer_one;
1714 controller->slave_abort = pxa2xx_spi_slave_abort;
1715 controller->handle_err = pxa2xx_spi_handle_err;
1716 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1717 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1718 controller->auto_runtime_pm = true;
1719 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1720
1721 drv_data->ssp_type = ssp->type;
1722
1723 drv_data->ioaddr = ssp->mmio_base;
1724 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1725 if (pxa25x_ssp_comp(drv_data)) {
1726 switch (drv_data->ssp_type) {
1727 case QUARK_X1000_SSP:
1728 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1729 break;
1730 default:
1731 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1732 break;
1733 }
1734
1735 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1736 drv_data->dma_cr1 = 0;
1737 drv_data->clear_sr = SSSR_ROR;
1738 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1739 } else {
1740 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1741 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1742 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1743 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1744 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1745 | SSSR_ROR | SSSR_TUR;
1746 }
1747
1748 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1749 drv_data);
1750 if (status < 0) {
1751 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1752 goto out_error_controller_alloc;
1753 }
1754
1755 /* Setup DMA if requested */
1756 if (platform_info->enable_dma) {
1757 status = pxa2xx_spi_dma_setup(drv_data);
1758 if (status) {
1759 dev_warn(dev, "no DMA channels available, using PIO\n");
1760 platform_info->enable_dma = false;
1761 } else {
1762 controller->can_dma = pxa2xx_spi_can_dma;
1763 controller->max_dma_len = MAX_DMA_LEN;
1764 controller->max_transfer_size =
1765 pxa2xx_spi_max_dma_transfer_size;
1766 }
1767 }
1768
1769 /* Enable SOC clock */
1770 status = clk_prepare_enable(ssp->clk);
1771 if (status)
1772 goto out_error_dma_irq_alloc;
1773
1774 controller->max_speed_hz = clk_get_rate(ssp->clk);
1775 /*
1776 * Set minimum speed for all other platforms than Intel Quark which is
1777 * able do under 1 Hz transfers.
1778 */
1779 if (!pxa25x_ssp_comp(drv_data))
1780 controller->min_speed_hz =
1781 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1782 else if (!is_quark_x1000_ssp(drv_data))
1783 controller->min_speed_hz =
1784 DIV_ROUND_UP(controller->max_speed_hz, 512);
1785
1786 /* Load default SSP configuration */
1787 pxa2xx_spi_write(drv_data, SSCR0, 0);
1788 switch (drv_data->ssp_type) {
1789 case QUARK_X1000_SSP:
1790 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1791 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1792 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1793
1794 /* using the Motorola SPI protocol and use 8 bit frame */
1795 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1796 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1797 break;
1798 case CE4100_SSP:
1799 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1800 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1801 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1802 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1803 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1804 break;
1805 default:
1806
1807 if (spi_controller_is_slave(controller)) {
1808 tmp = SSCR1_SCFR |
1809 SSCR1_SCLKDIR |
1810 SSCR1_SFRMDIR |
1811 SSCR1_RxTresh(2) |
1812 SSCR1_TxTresh(1) |
1813 SSCR1_SPH;
1814 } else {
1815 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1816 SSCR1_TxTresh(TX_THRESH_DFLT);
1817 }
1818 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1819 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1820 if (!spi_controller_is_slave(controller))
1821 tmp |= SSCR0_SCR(2);
1822 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1823 break;
1824 }
1825
1826 if (!pxa25x_ssp_comp(drv_data))
1827 pxa2xx_spi_write(drv_data, SSTO, 0);
1828
1829 if (!is_quark_x1000_ssp(drv_data))
1830 pxa2xx_spi_write(drv_data, SSPSP, 0);
1831
1832 if (is_lpss_ssp(drv_data)) {
1833 lpss_ssp_setup(drv_data);
1834 config = lpss_get_config(drv_data);
1835 if (config->reg_capabilities >= 0) {
1836 tmp = __lpss_ssp_read_priv(drv_data,
1837 config->reg_capabilities);
1838 tmp &= LPSS_CAPS_CS_EN_MASK;
1839 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1840 platform_info->num_chipselect = ffz(tmp);
1841 } else if (config->cs_num) {
1842 platform_info->num_chipselect = config->cs_num;
1843 }
1844 }
1845 controller->num_chipselect = platform_info->num_chipselect;
1846
1847 count = gpiod_count(&pdev->dev, "cs");
1848 if (count > 0) {
1849 int i;
1850
1851 controller->num_chipselect = max_t(int, count,
1852 controller->num_chipselect);
1853
1854 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1855 controller->num_chipselect, sizeof(struct gpio_desc *),
1856 GFP_KERNEL);
1857 if (!drv_data->cs_gpiods) {
1858 status = -ENOMEM;
1859 goto out_error_clock_enabled;
1860 }
1861
1862 for (i = 0; i < controller->num_chipselect; i++) {
1863 struct gpio_desc *gpiod;
1864
1865 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1866 if (IS_ERR(gpiod)) {
1867 /* Means use native chip select */
1868 if (PTR_ERR(gpiod) == -ENOENT)
1869 continue;
1870
1871 status = PTR_ERR(gpiod);
1872 goto out_error_clock_enabled;
1873 } else {
1874 drv_data->cs_gpiods[i] = gpiod;
1875 }
1876 }
1877 }
1878
1879 if (platform_info->is_slave) {
1880 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1881 "ready", GPIOD_OUT_LOW);
1882 if (IS_ERR(drv_data->gpiod_ready)) {
1883 status = PTR_ERR(drv_data->gpiod_ready);
1884 goto out_error_clock_enabled;
1885 }
1886 }
1887
1888 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1889 pm_runtime_use_autosuspend(&pdev->dev);
1890 pm_runtime_set_active(&pdev->dev);
1891 pm_runtime_enable(&pdev->dev);
1892
1893 /* Register with the SPI framework */
1894 platform_set_drvdata(pdev, drv_data);
1895 status = spi_register_controller(controller);
1896 if (status != 0) {
1897 dev_err(&pdev->dev, "problem registering spi controller\n");
1898 goto out_error_pm_runtime_enabled;
1899 }
1900
1901 return status;
1902
1903out_error_pm_runtime_enabled:
1904 pm_runtime_disable(&pdev->dev);
1905
1906out_error_clock_enabled:
1907 clk_disable_unprepare(ssp->clk);
1908
1909out_error_dma_irq_alloc:
1910 pxa2xx_spi_dma_release(drv_data);
1911 free_irq(ssp->irq, drv_data);
1912
1913out_error_controller_alloc:
1914 spi_controller_put(controller);
1915 pxa_ssp_free(ssp);
1916 return status;
1917}
1918
1919static int pxa2xx_spi_remove(struct platform_device *pdev)
1920{
1921 struct driver_data *drv_data = platform_get_drvdata(pdev);
1922 struct ssp_device *ssp = drv_data->ssp;
1923
1924 pm_runtime_get_sync(&pdev->dev);
1925
1926 spi_unregister_controller(drv_data->controller);
1927
1928 /* Disable the SSP at the peripheral and SOC level */
1929 pxa2xx_spi_write(drv_data, SSCR0, 0);
1930 clk_disable_unprepare(ssp->clk);
1931
1932 /* Release DMA */
1933 if (drv_data->controller_info->enable_dma)
1934 pxa2xx_spi_dma_release(drv_data);
1935
1936 pm_runtime_put_noidle(&pdev->dev);
1937 pm_runtime_disable(&pdev->dev);
1938
1939 /* Release IRQ */
1940 free_irq(ssp->irq, drv_data);
1941
1942 /* Release SSP */
1943 pxa_ssp_free(ssp);
1944
1945 return 0;
1946}
1947
1948#ifdef CONFIG_PM_SLEEP
1949static int pxa2xx_spi_suspend(struct device *dev)
1950{
1951 struct driver_data *drv_data = dev_get_drvdata(dev);
1952 struct ssp_device *ssp = drv_data->ssp;
1953 int status;
1954
1955 status = spi_controller_suspend(drv_data->controller);
1956 if (status != 0)
1957 return status;
1958 pxa2xx_spi_write(drv_data, SSCR0, 0);
1959
1960 if (!pm_runtime_suspended(dev))
1961 clk_disable_unprepare(ssp->clk);
1962
1963 return 0;
1964}
1965
1966static int pxa2xx_spi_resume(struct device *dev)
1967{
1968 struct driver_data *drv_data = dev_get_drvdata(dev);
1969 struct ssp_device *ssp = drv_data->ssp;
1970 int status;
1971
1972 /* Enable the SSP clock */
1973 if (!pm_runtime_suspended(dev)) {
1974 status = clk_prepare_enable(ssp->clk);
1975 if (status)
1976 return status;
1977 }
1978
1979 /* Start the queue running */
1980 return spi_controller_resume(drv_data->controller);
1981}
1982#endif
1983
1984#ifdef CONFIG_PM
1985static int pxa2xx_spi_runtime_suspend(struct device *dev)
1986{
1987 struct driver_data *drv_data = dev_get_drvdata(dev);
1988
1989 clk_disable_unprepare(drv_data->ssp->clk);
1990 return 0;
1991}
1992
1993static int pxa2xx_spi_runtime_resume(struct device *dev)
1994{
1995 struct driver_data *drv_data = dev_get_drvdata(dev);
1996 int status;
1997
1998 status = clk_prepare_enable(drv_data->ssp->clk);
1999 return status;
2000}
2001#endif
2002
2003static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
2004 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
2005 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
2006 pxa2xx_spi_runtime_resume, NULL)
2007};
2008
2009static struct platform_driver driver = {
2010 .driver = {
2011 .name = "pxa2xx-spi",
2012 .pm = &pxa2xx_spi_pm_ops,
2013 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
2014 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
2015 },
2016 .probe = pxa2xx_spi_probe,
2017 .remove = pxa2xx_spi_remove,
2018};
2019
2020static int __init pxa2xx_spi_init(void)
2021{
2022 return platform_driver_register(&driver);
2023}
2024subsys_initcall(pxa2xx_spi_init);
2025
2026static void __exit pxa2xx_spi_exit(void)
2027{
2028 platform_driver_unregister(&driver);
2029}
2030module_exit(pxa2xx_spi_exit);
2031
2032MODULE_SOFTDEP("pre: dw_dmac");