Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#include <linux/acpi.h>
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/dmaengine.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/gpio/consumer.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/mod_devicetable.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/property.h>
26#include <linux/slab.h>
27
28#include <linux/spi/pxa2xx_spi.h>
29#include <linux/spi/spi.h>
30
31#include "spi-pxa2xx.h"
32
33MODULE_AUTHOR("Stephen Street");
34MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
35MODULE_LICENSE("GPL");
36MODULE_ALIAS("platform:pxa2xx-spi");
37
38#define TIMOUT_DFLT 1000
39
40/*
41 * For testing SSCR1 changes that require SSP restart, basically
42 * everything except the service and interrupt enables, the PXA270 developer
43 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
44 * list, but the PXA255 developer manual says all bits without really meaning
45 * the service and interrupt enables.
46 */
47#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
48 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
49 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
50 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
51 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
53
54#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
55 | QUARK_X1000_SSCR1_EFWR \
56 | QUARK_X1000_SSCR1_RFT \
57 | QUARK_X1000_SSCR1_TFT \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59
60#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
68#define LPSS_CS_CONTROL_SW_MODE BIT(0)
69#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
73#define LPSS_PRIV_CLOCK_GATE 0x38
74#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
75#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
76
77struct lpss_config {
78 /* LPSS offset from drv_data->ioaddr */
79 unsigned offset;
80 /* Register offsets from drv_data->lpss_base or -1 */
81 int reg_general;
82 int reg_ssp;
83 int reg_cs_ctrl;
84 int reg_capabilities;
85 /* FIFO thresholds */
86 u32 rx_threshold;
87 u32 tx_threshold_lo;
88 u32 tx_threshold_hi;
89 /* Chip select control */
90 unsigned cs_sel_shift;
91 unsigned cs_sel_mask;
92 unsigned cs_num;
93 /* Quirks */
94 unsigned cs_clk_stays_gated : 1;
95};
96
97/* Keep these sorted with enum pxa_ssp_type */
98static const struct lpss_config lpss_platforms[] = {
99 { /* LPSS_LPT_SSP */
100 .offset = 0x800,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
109 { /* LPSS_BYT_SSP */
110 .offset = 0x400,
111 .reg_general = 0x08,
112 .reg_ssp = 0x0c,
113 .reg_cs_ctrl = 0x18,
114 .reg_capabilities = -1,
115 .rx_threshold = 64,
116 .tx_threshold_lo = 160,
117 .tx_threshold_hi = 224,
118 },
119 { /* LPSS_BSW_SSP */
120 .offset = 0x400,
121 .reg_general = 0x08,
122 .reg_ssp = 0x0c,
123 .reg_cs_ctrl = 0x18,
124 .reg_capabilities = -1,
125 .rx_threshold = 64,
126 .tx_threshold_lo = 160,
127 .tx_threshold_hi = 224,
128 .cs_sel_shift = 2,
129 .cs_sel_mask = 1 << 2,
130 .cs_num = 2,
131 },
132 { /* LPSS_SPT_SSP */
133 .offset = 0x200,
134 .reg_general = -1,
135 .reg_ssp = 0x20,
136 .reg_cs_ctrl = 0x24,
137 .reg_capabilities = -1,
138 .rx_threshold = 1,
139 .tx_threshold_lo = 32,
140 .tx_threshold_hi = 56,
141 },
142 { /* LPSS_BXT_SSP */
143 .offset = 0x200,
144 .reg_general = -1,
145 .reg_ssp = 0x20,
146 .reg_cs_ctrl = 0x24,
147 .reg_capabilities = 0xfc,
148 .rx_threshold = 1,
149 .tx_threshold_lo = 16,
150 .tx_threshold_hi = 48,
151 .cs_sel_shift = 8,
152 .cs_sel_mask = 3 << 8,
153 .cs_clk_stays_gated = true,
154 },
155 { /* LPSS_CNL_SSP */
156 .offset = 0x200,
157 .reg_general = -1,
158 .reg_ssp = 0x20,
159 .reg_cs_ctrl = 0x24,
160 .reg_capabilities = 0xfc,
161 .rx_threshold = 1,
162 .tx_threshold_lo = 32,
163 .tx_threshold_hi = 56,
164 .cs_sel_shift = 8,
165 .cs_sel_mask = 3 << 8,
166 .cs_clk_stays_gated = true,
167 },
168};
169
170static inline const struct lpss_config
171*lpss_get_config(const struct driver_data *drv_data)
172{
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
174}
175
176static bool is_lpss_ssp(const struct driver_data *drv_data)
177{
178 switch (drv_data->ssp_type) {
179 case LPSS_LPT_SSP:
180 case LPSS_BYT_SSP:
181 case LPSS_BSW_SSP:
182 case LPSS_SPT_SSP:
183 case LPSS_BXT_SSP:
184 case LPSS_CNL_SSP:
185 return true;
186 default:
187 return false;
188 }
189}
190
191static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
192{
193 return drv_data->ssp_type == QUARK_X1000_SSP;
194}
195
196static bool is_mmp2_ssp(const struct driver_data *drv_data)
197{
198 return drv_data->ssp_type == MMP2_SSP;
199}
200
201static bool is_mrfld_ssp(const struct driver_data *drv_data)
202{
203 return drv_data->ssp_type == MRFLD_SSP;
204}
205
206static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
207{
208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
209 pxa2xx_spi_write(drv_data, reg, value & mask);
210}
211
212static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
213{
214 switch (drv_data->ssp_type) {
215 case QUARK_X1000_SSP:
216 return QUARK_X1000_SSCR1_CHANGE_MASK;
217 case CE4100_SSP:
218 return CE4100_SSCR1_CHANGE_MASK;
219 default:
220 return SSCR1_CHANGE_MASK;
221 }
222}
223
224static u32
225pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
226{
227 switch (drv_data->ssp_type) {
228 case QUARK_X1000_SSP:
229 return RX_THRESH_QUARK_X1000_DFLT;
230 case CE4100_SSP:
231 return RX_THRESH_CE4100_DFLT;
232 default:
233 return RX_THRESH_DFLT;
234 }
235}
236
237static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
238{
239 u32 mask;
240
241 switch (drv_data->ssp_type) {
242 case QUARK_X1000_SSP:
243 mask = QUARK_X1000_SSSR_TFL_MASK;
244 break;
245 case CE4100_SSP:
246 mask = CE4100_SSSR_TFL_MASK;
247 break;
248 default:
249 mask = SSSR_TFL_MASK;
250 break;
251 }
252
253 return read_SSSR_bits(drv_data, mask) == mask;
254}
255
256static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
257 u32 *sccr1_reg)
258{
259 u32 mask;
260
261 switch (drv_data->ssp_type) {
262 case QUARK_X1000_SSP:
263 mask = QUARK_X1000_SSCR1_RFT;
264 break;
265 case CE4100_SSP:
266 mask = CE4100_SSCR1_RFT;
267 break;
268 default:
269 mask = SSCR1_RFT;
270 break;
271 }
272 *sccr1_reg &= ~mask;
273}
274
275static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
276 u32 *sccr1_reg, u32 threshold)
277{
278 switch (drv_data->ssp_type) {
279 case QUARK_X1000_SSP:
280 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
281 break;
282 case CE4100_SSP:
283 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
284 break;
285 default:
286 *sccr1_reg |= SSCR1_RxTresh(threshold);
287 break;
288 }
289}
290
291static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
292 u32 clk_div, u8 bits)
293{
294 switch (drv_data->ssp_type) {
295 case QUARK_X1000_SSP:
296 return clk_div
297 | QUARK_X1000_SSCR0_Motorola
298 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
299 default:
300 return clk_div
301 | SSCR0_Motorola
302 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
303 | (bits > 16 ? SSCR0_EDSS : 0);
304 }
305}
306
307/*
308 * Read and write LPSS SSP private registers. Caller must first check that
309 * is_lpss_ssp() returns true before these can be called.
310 */
311static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
312{
313 WARN_ON(!drv_data->lpss_base);
314 return readl(drv_data->lpss_base + offset);
315}
316
317static void __lpss_ssp_write_priv(struct driver_data *drv_data,
318 unsigned offset, u32 value)
319{
320 WARN_ON(!drv_data->lpss_base);
321 writel(value, drv_data->lpss_base + offset);
322}
323
324/*
325 * lpss_ssp_setup - perform LPSS SSP specific setup
326 * @drv_data: pointer to the driver private data
327 *
328 * Perform LPSS SSP specific setup. This function must be called first if
329 * one is going to use LPSS SSP private registers.
330 */
331static void lpss_ssp_setup(struct driver_data *drv_data)
332{
333 const struct lpss_config *config;
334 u32 value;
335
336 config = lpss_get_config(drv_data);
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
338
339 /* Enable software chip select control */
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
341 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
342 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
344
345 /* Enable multiblock DMA transfers */
346 if (drv_data->controller_info->enable_dma) {
347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
348
349 if (config->reg_general >= 0) {
350 value = __lpss_ssp_read_priv(drv_data,
351 config->reg_general);
352 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
353 __lpss_ssp_write_priv(drv_data,
354 config->reg_general, value);
355 }
356 }
357}
358
359static void lpss_ssp_select_cs(struct spi_device *spi,
360 const struct lpss_config *config)
361{
362 struct driver_data *drv_data =
363 spi_controller_get_devdata(spi->controller);
364 u32 value, cs;
365
366 if (!config->cs_sel_mask)
367 return;
368
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
370
371 cs = spi->chip_select;
372 cs <<= config->cs_sel_shift;
373 if (cs != (value & config->cs_sel_mask)) {
374 /*
375 * When switching another chip select output active the
376 * output must be selected first and wait 2 ssp_clk cycles
377 * before changing state to active. Otherwise a short
378 * glitch will occur on the previous chip select since
379 * output select is latched but state control is not.
380 */
381 value &= ~config->cs_sel_mask;
382 value |= cs;
383 __lpss_ssp_write_priv(drv_data,
384 config->reg_cs_ctrl, value);
385 ndelay(1000000000 /
386 (drv_data->controller->max_speed_hz / 2));
387 }
388}
389
390static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
391{
392 struct driver_data *drv_data =
393 spi_controller_get_devdata(spi->controller);
394 const struct lpss_config *config;
395 u32 value;
396
397 config = lpss_get_config(drv_data);
398
399 if (enable)
400 lpss_ssp_select_cs(spi, config);
401
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
403 if (enable)
404 value &= ~LPSS_CS_CONTROL_CS_HIGH;
405 else
406 value |= LPSS_CS_CONTROL_CS_HIGH;
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
408 if (config->cs_clk_stays_gated) {
409 u32 clkgate;
410
411 /*
412 * Changing CS alone when dynamic clock gating is on won't
413 * actually flip CS at that time. This ruins SPI transfers
414 * that specify delays, or have no data. Toggle the clock mode
415 * to force on briefly to poke the CS pin to move.
416 */
417 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
418 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
419 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
420
421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
423 }
424}
425
426static void cs_assert(struct spi_device *spi)
427{
428 struct driver_data *drv_data =
429 spi_controller_get_devdata(spi->controller);
430
431 if (drv_data->ssp_type == CE4100_SSP) {
432 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select);
433 return;
434 }
435
436 if (is_lpss_ssp(drv_data))
437 lpss_ssp_cs_control(spi, true);
438}
439
440static void cs_deassert(struct spi_device *spi)
441{
442 struct driver_data *drv_data =
443 spi_controller_get_devdata(spi->controller);
444 unsigned long timeout;
445
446 if (drv_data->ssp_type == CE4100_SSP)
447 return;
448
449 /* Wait until SSP becomes idle before deasserting the CS */
450 timeout = jiffies + msecs_to_jiffies(10);
451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
452 !time_after(jiffies, timeout))
453 cpu_relax();
454
455 if (is_lpss_ssp(drv_data))
456 lpss_ssp_cs_control(spi, false);
457}
458
459static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
460{
461 if (level)
462 cs_deassert(spi);
463 else
464 cs_assert(spi);
465}
466
467int pxa2xx_spi_flush(struct driver_data *drv_data)
468{
469 unsigned long limit = loops_per_jiffy << 1;
470
471 do {
472 while (read_SSSR_bits(drv_data, SSSR_RNE))
473 pxa2xx_spi_read(drv_data, SSDR);
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
475 write_SSSR_CS(drv_data, SSSR_ROR);
476
477 return limit;
478}
479
480static void pxa2xx_spi_off(struct driver_data *drv_data)
481{
482 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
483 if (is_mmp2_ssp(drv_data))
484 return;
485
486 pxa_ssp_disable(drv_data->ssp);
487}
488
489static int null_writer(struct driver_data *drv_data)
490{
491 u8 n_bytes = drv_data->n_bytes;
492
493 if (pxa2xx_spi_txfifo_full(drv_data)
494 || (drv_data->tx == drv_data->tx_end))
495 return 0;
496
497 pxa2xx_spi_write(drv_data, SSDR, 0);
498 drv_data->tx += n_bytes;
499
500 return 1;
501}
502
503static int null_reader(struct driver_data *drv_data)
504{
505 u8 n_bytes = drv_data->n_bytes;
506
507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
508 pxa2xx_spi_read(drv_data, SSDR);
509 drv_data->rx += n_bytes;
510 }
511
512 return drv_data->rx == drv_data->rx_end;
513}
514
515static int u8_writer(struct driver_data *drv_data)
516{
517 if (pxa2xx_spi_txfifo_full(drv_data)
518 || (drv_data->tx == drv_data->tx_end))
519 return 0;
520
521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
522 ++drv_data->tx;
523
524 return 1;
525}
526
527static int u8_reader(struct driver_data *drv_data)
528{
529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
531 ++drv_data->rx;
532 }
533
534 return drv_data->rx == drv_data->rx_end;
535}
536
537static int u16_writer(struct driver_data *drv_data)
538{
539 if (pxa2xx_spi_txfifo_full(drv_data)
540 || (drv_data->tx == drv_data->tx_end))
541 return 0;
542
543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
544 drv_data->tx += 2;
545
546 return 1;
547}
548
549static int u16_reader(struct driver_data *drv_data)
550{
551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
553 drv_data->rx += 2;
554 }
555
556 return drv_data->rx == drv_data->rx_end;
557}
558
559static int u32_writer(struct driver_data *drv_data)
560{
561 if (pxa2xx_spi_txfifo_full(drv_data)
562 || (drv_data->tx == drv_data->tx_end))
563 return 0;
564
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
566 drv_data->tx += 4;
567
568 return 1;
569}
570
571static int u32_reader(struct driver_data *drv_data)
572{
573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
575 drv_data->rx += 4;
576 }
577
578 return drv_data->rx == drv_data->rx_end;
579}
580
581static void reset_sccr1(struct driver_data *drv_data)
582{
583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
584 struct chip_data *chip;
585
586 if (drv_data->controller->cur_msg) {
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
588 threshold = chip->threshold;
589 } else {
590 threshold = 0;
591 }
592
593 switch (drv_data->ssp_type) {
594 case QUARK_X1000_SSP:
595 mask |= QUARK_X1000_SSCR1_RFT;
596 break;
597 case CE4100_SSP:
598 mask |= CE4100_SSCR1_RFT;
599 break;
600 default:
601 mask |= SSCR1_RFT;
602 break;
603 }
604
605 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
606}
607
608static void int_stop_and_reset(struct driver_data *drv_data)
609{
610 /* Clear and disable interrupts */
611 write_SSSR_CS(drv_data, drv_data->clear_sr);
612 reset_sccr1(drv_data);
613 if (pxa25x_ssp_comp(drv_data))
614 return;
615
616 pxa2xx_spi_write(drv_data, SSTO, 0);
617}
618
619static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
620{
621 int_stop_and_reset(drv_data);
622 pxa2xx_spi_flush(drv_data);
623 pxa2xx_spi_off(drv_data);
624
625 dev_err(drv_data->ssp->dev, "%s\n", msg);
626
627 drv_data->controller->cur_msg->status = err;
628 spi_finalize_current_transfer(drv_data->controller);
629}
630
631static void int_transfer_complete(struct driver_data *drv_data)
632{
633 int_stop_and_reset(drv_data);
634
635 spi_finalize_current_transfer(drv_data->controller);
636}
637
638static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
639{
640 u32 irq_status;
641
642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
643 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
644 irq_status &= ~SSSR_TFS;
645
646 if (irq_status & SSSR_ROR) {
647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
648 return IRQ_HANDLED;
649 }
650
651 if (irq_status & SSSR_TUR) {
652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
653 return IRQ_HANDLED;
654 }
655
656 if (irq_status & SSSR_TINT) {
657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
658 if (drv_data->read(drv_data)) {
659 int_transfer_complete(drv_data);
660 return IRQ_HANDLED;
661 }
662 }
663
664 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
665 do {
666 if (drv_data->read(drv_data)) {
667 int_transfer_complete(drv_data);
668 return IRQ_HANDLED;
669 }
670 } while (drv_data->write(drv_data));
671
672 if (drv_data->read(drv_data)) {
673 int_transfer_complete(drv_data);
674 return IRQ_HANDLED;
675 }
676
677 if (drv_data->tx == drv_data->tx_end) {
678 u32 bytes_left;
679 u32 sccr1_reg;
680
681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
682 sccr1_reg &= ~SSCR1_TIE;
683
684 /*
685 * PXA25x_SSP has no timeout, set up Rx threshold for
686 * the remaining Rx bytes.
687 */
688 if (pxa25x_ssp_comp(drv_data)) {
689 u32 rx_thre;
690
691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
692
693 bytes_left = drv_data->rx_end - drv_data->rx;
694 switch (drv_data->n_bytes) {
695 case 4:
696 bytes_left >>= 2;
697 break;
698 case 2:
699 bytes_left >>= 1;
700 break;
701 }
702
703 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
704 if (rx_thre > bytes_left)
705 rx_thre = bytes_left;
706
707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
708 }
709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
710 }
711
712 /* We did something */
713 return IRQ_HANDLED;
714}
715
716static void handle_bad_msg(struct driver_data *drv_data)
717{
718 int_stop_and_reset(drv_data);
719 pxa2xx_spi_off(drv_data);
720
721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
722}
723
724static irqreturn_t ssp_int(int irq, void *dev_id)
725{
726 struct driver_data *drv_data = dev_id;
727 u32 sccr1_reg;
728 u32 mask = drv_data->mask_sr;
729 u32 status;
730
731 /*
732 * The IRQ might be shared with other peripherals so we must first
733 * check that are we RPM suspended or not. If we are we assume that
734 * the IRQ was not for us (we shouldn't be RPM suspended when the
735 * interrupt is enabled).
736 */
737 if (pm_runtime_suspended(drv_data->ssp->dev))
738 return IRQ_NONE;
739
740 /*
741 * If the device is not yet in RPM suspended state and we get an
742 * interrupt that is meant for another device, check if status bits
743 * are all set to one. That means that the device is already
744 * powered off.
745 */
746 status = pxa2xx_spi_read(drv_data, SSSR);
747 if (status == ~0)
748 return IRQ_NONE;
749
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
751
752 /* Ignore possible writes if we don't need to write */
753 if (!(sccr1_reg & SSCR1_TIE))
754 mask &= ~SSSR_TFS;
755
756 /* Ignore RX timeout interrupt if it is disabled */
757 if (!(sccr1_reg & SSCR1_TINTE))
758 mask &= ~SSSR_TINT;
759
760 if (!(status & mask))
761 return IRQ_NONE;
762
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
765
766 if (!drv_data->controller->cur_msg) {
767 handle_bad_msg(drv_data);
768 /* Never fail */
769 return IRQ_HANDLED;
770 }
771
772 return drv_data->transfer_handler(drv_data);
773}
774
775/*
776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
777 * input frequency by fractions of 2^24. It also has a divider by 5.
778 *
779 * There are formulas to get baud rate value for given input frequency and
780 * divider parameters, such as DDS_CLK_RATE and SCR:
781 *
782 * Fsys = 200MHz
783 *
784 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
786 *
787 * DDS_CLK_RATE either 2^n or 2^n / 5.
788 * SCR is in range 0 .. 255
789 *
790 * Divisor = 5^i * 2^j * 2 * k
791 * i = [0, 1] i = 1 iff j = 0 or j > 3
792 * j = [0, 23] j = 0 iff i = 1
793 * k = [1, 256]
794 * Special case: j = 0, i = 1: Divisor = 2 / 5
795 *
796 * Accordingly to the specification the recommended values for DDS_CLK_RATE
797 * are:
798 * Case 1: 2^n, n = [0, 23]
799 * Case 2: 2^24 * 2 / 5 (0x666666)
800 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
801 *
802 * In all cases the lowest possible value is better.
803 *
804 * The function calculates parameters for all cases and chooses the one closest
805 * to the asked baud rate.
806 */
807static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
808{
809 unsigned long xtal = 200000000;
810 unsigned long fref = xtal / 2; /* mandatory division by 2,
811 see (2) */
812 /* case 3 */
813 unsigned long fref1 = fref / 2; /* case 1 */
814 unsigned long fref2 = fref * 2 / 5; /* case 2 */
815 unsigned long scale;
816 unsigned long q, q1, q2;
817 long r, r1, r2;
818 u32 mul;
819
820 /* Case 1 */
821
822 /* Set initial value for DDS_CLK_RATE */
823 mul = (1 << 24) >> 1;
824
825 /* Calculate initial quot */
826 q1 = DIV_ROUND_UP(fref1, rate);
827
828 /* Scale q1 if it's too big */
829 if (q1 > 256) {
830 /* Scale q1 to range [1, 512] */
831 scale = fls_long(q1 - 1);
832 if (scale > 9) {
833 q1 >>= scale - 9;
834 mul >>= scale - 9;
835 }
836
837 /* Round the result if we have a remainder */
838 q1 += q1 & 1;
839 }
840
841 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
842 scale = __ffs(q1);
843 q1 >>= scale;
844 mul >>= scale;
845
846 /* Get the remainder */
847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
848
849 /* Case 2 */
850
851 q2 = DIV_ROUND_UP(fref2, rate);
852 r2 = abs(fref2 / q2 - rate);
853
854 /*
855 * Choose the best between two: less remainder we have the better. We
856 * can't go case 2 if q2 is greater than 256 since SCR register can
857 * hold only values 0 .. 255.
858 */
859 if (r2 >= r1 || q2 > 256) {
860 /* case 1 is better */
861 r = r1;
862 q = q1;
863 } else {
864 /* case 2 is better */
865 r = r2;
866 q = q2;
867 mul = (1 << 24) * 2 / 5;
868 }
869
870 /* Check case 3 only if the divisor is big enough */
871 if (fref / rate >= 80) {
872 u64 fssp;
873 u32 m;
874
875 /* Calculate initial quot */
876 q1 = DIV_ROUND_UP(fref, rate);
877 m = (1 << 24) / q1;
878
879 /* Get the remainder */
880 fssp = (u64)fref * m;
881 do_div(fssp, 1 << 24);
882 r1 = abs(fssp - rate);
883
884 /* Choose this one if it suits better */
885 if (r1 < r) {
886 /* case 3 is better */
887 q = 1;
888 mul = m;
889 }
890 }
891
892 *dds = mul;
893 return q - 1;
894}
895
896static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
897{
898 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
899 const struct ssp_device *ssp = drv_data->ssp;
900
901 rate = min_t(int, ssp_clk, rate);
902
903 /*
904 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
905 * that the SSP transmission rate can be greater than the device rate.
906 */
907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
909 else
910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
911}
912
913static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
914 int rate)
915{
916 struct chip_data *chip =
917 spi_get_ctldata(drv_data->controller->cur_msg->spi);
918 unsigned int clk_div;
919
920 switch (drv_data->ssp_type) {
921 case QUARK_X1000_SSP:
922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
923 break;
924 default:
925 clk_div = ssp_get_clk_div(drv_data, rate);
926 break;
927 }
928 return clk_div << 8;
929}
930
931static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
932 struct spi_device *spi,
933 struct spi_transfer *xfer)
934{
935 struct chip_data *chip = spi_get_ctldata(spi);
936
937 return chip->enable_dma &&
938 xfer->len <= MAX_DMA_LEN &&
939 xfer->len >= chip->dma_burst_size;
940}
941
942static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
943 struct spi_device *spi,
944 struct spi_transfer *transfer)
945{
946 struct driver_data *drv_data = spi_controller_get_devdata(controller);
947 struct spi_message *message = controller->cur_msg;
948 struct chip_data *chip = spi_get_ctldata(spi);
949 u32 dma_thresh = chip->dma_threshold;
950 u32 dma_burst = chip->dma_burst_size;
951 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
952 u32 clk_div;
953 u8 bits;
954 u32 speed;
955 u32 cr0;
956 u32 cr1;
957 int err;
958 int dma_mapped;
959
960 /* Check if we can DMA this transfer */
961 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
962
963 /* Reject already-mapped transfers; PIO won't always work */
964 if (message->is_dma_mapped
965 || transfer->rx_dma || transfer->tx_dma) {
966 dev_err(&spi->dev,
967 "Mapped transfer length of %u is greater than %d\n",
968 transfer->len, MAX_DMA_LEN);
969 return -EINVAL;
970 }
971
972 /* Warn ... we force this to PIO mode */
973 dev_warn_ratelimited(&spi->dev,
974 "DMA disabled for transfer length %u greater than %d\n",
975 transfer->len, MAX_DMA_LEN);
976 }
977
978 /* Setup the transfer state based on the type of transfer */
979 if (pxa2xx_spi_flush(drv_data) == 0) {
980 dev_err(&spi->dev, "Flush failed\n");
981 return -EIO;
982 }
983 drv_data->tx = (void *)transfer->tx_buf;
984 drv_data->tx_end = drv_data->tx + transfer->len;
985 drv_data->rx = transfer->rx_buf;
986 drv_data->rx_end = drv_data->rx + transfer->len;
987
988 /* Change speed and bit per word on a per transfer */
989 bits = transfer->bits_per_word;
990 speed = transfer->speed_hz;
991
992 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
993
994 if (bits <= 8) {
995 drv_data->n_bytes = 1;
996 drv_data->read = drv_data->rx ? u8_reader : null_reader;
997 drv_data->write = drv_data->tx ? u8_writer : null_writer;
998 } else if (bits <= 16) {
999 drv_data->n_bytes = 2;
1000 drv_data->read = drv_data->rx ? u16_reader : null_reader;
1001 drv_data->write = drv_data->tx ? u16_writer : null_writer;
1002 } else if (bits <= 32) {
1003 drv_data->n_bytes = 4;
1004 drv_data->read = drv_data->rx ? u32_reader : null_reader;
1005 drv_data->write = drv_data->tx ? u32_writer : null_writer;
1006 }
1007 /*
1008 * If bits per word is changed in DMA mode, then must check
1009 * the thresholds and burst also.
1010 */
1011 if (chip->enable_dma) {
1012 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1013 spi,
1014 bits, &dma_burst,
1015 &dma_thresh))
1016 dev_warn_ratelimited(&spi->dev,
1017 "DMA burst size reduced to match bits_per_word\n");
1018 }
1019
1020 dma_mapped = controller->can_dma &&
1021 controller->can_dma(controller, spi, transfer) &&
1022 controller->cur_msg_mapped;
1023 if (dma_mapped) {
1024
1025 /* Ensure we have the correct interrupt handler */
1026 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1027
1028 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1029 if (err)
1030 return err;
1031
1032 /* Clear status and start DMA engine */
1033 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1034 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1035
1036 pxa2xx_spi_dma_start(drv_data);
1037 } else {
1038 /* Ensure we have the correct interrupt handler */
1039 drv_data->transfer_handler = interrupt_transfer;
1040
1041 /* Clear status */
1042 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1043 write_SSSR_CS(drv_data, drv_data->clear_sr);
1044 }
1045
1046 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1047 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1048 if (!pxa25x_ssp_comp(drv_data))
1049 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1050 controller->max_speed_hz
1051 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1052 dma_mapped ? "DMA" : "PIO");
1053 else
1054 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1055 controller->max_speed_hz / 2
1056 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1057 dma_mapped ? "DMA" : "PIO");
1058
1059 if (is_lpss_ssp(drv_data)) {
1060 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1061 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1062 }
1063
1064 if (is_mrfld_ssp(drv_data)) {
1065 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1066 u32 thresh = 0;
1067
1068 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1069 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1070
1071 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1072 }
1073
1074 if (is_quark_x1000_ssp(drv_data))
1075 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1076
1077 /* Stop the SSP */
1078 if (!is_mmp2_ssp(drv_data))
1079 pxa_ssp_disable(drv_data->ssp);
1080
1081 if (!pxa25x_ssp_comp(drv_data))
1082 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1083
1084 /* First set CR1 without interrupt and service enables */
1085 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1086
1087 /* See if we need to reload the configuration registers */
1088 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1089
1090 /* Restart the SSP */
1091 pxa_ssp_enable(drv_data->ssp);
1092
1093 if (is_mmp2_ssp(drv_data)) {
1094 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1095
1096 if (tx_level) {
1097 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1098 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1099 if (tx_level > transfer->len)
1100 tx_level = transfer->len;
1101 drv_data->tx += tx_level;
1102 }
1103 }
1104
1105 if (spi_controller_is_slave(controller)) {
1106 while (drv_data->write(drv_data))
1107 ;
1108 if (drv_data->gpiod_ready) {
1109 gpiod_set_value(drv_data->gpiod_ready, 1);
1110 udelay(1);
1111 gpiod_set_value(drv_data->gpiod_ready, 0);
1112 }
1113 }
1114
1115 /*
1116 * Release the data by enabling service requests and interrupts,
1117 * without changing any mode bits.
1118 */
1119 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1120
1121 return 1;
1122}
1123
1124static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1125{
1126 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1127
1128 int_error_stop(drv_data, "transfer aborted", -EINTR);
1129
1130 return 0;
1131}
1132
1133static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1134 struct spi_message *msg)
1135{
1136 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1137
1138 int_stop_and_reset(drv_data);
1139
1140 /* Disable the SSP */
1141 pxa2xx_spi_off(drv_data);
1142
1143 /*
1144 * Stop the DMA if running. Note DMA callback handler may have unset
1145 * the dma_running already, which is fine as stopping is not needed
1146 * then but we shouldn't rely this flag for anything else than
1147 * stopping. For instance to differentiate between PIO and DMA
1148 * transfers.
1149 */
1150 if (atomic_read(&drv_data->dma_running))
1151 pxa2xx_spi_dma_stop(drv_data);
1152}
1153
1154static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1155{
1156 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1157
1158 /* Disable the SSP now */
1159 pxa2xx_spi_off(drv_data);
1160
1161 return 0;
1162}
1163
1164static int setup(struct spi_device *spi)
1165{
1166 struct pxa2xx_spi_chip *chip_info;
1167 struct chip_data *chip;
1168 const struct lpss_config *config;
1169 struct driver_data *drv_data =
1170 spi_controller_get_devdata(spi->controller);
1171 uint tx_thres, tx_hi_thres, rx_thres;
1172
1173 switch (drv_data->ssp_type) {
1174 case QUARK_X1000_SSP:
1175 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1176 tx_hi_thres = 0;
1177 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1178 break;
1179 case MRFLD_SSP:
1180 tx_thres = TX_THRESH_MRFLD_DFLT;
1181 tx_hi_thres = 0;
1182 rx_thres = RX_THRESH_MRFLD_DFLT;
1183 break;
1184 case CE4100_SSP:
1185 tx_thres = TX_THRESH_CE4100_DFLT;
1186 tx_hi_thres = 0;
1187 rx_thres = RX_THRESH_CE4100_DFLT;
1188 break;
1189 case LPSS_LPT_SSP:
1190 case LPSS_BYT_SSP:
1191 case LPSS_BSW_SSP:
1192 case LPSS_SPT_SSP:
1193 case LPSS_BXT_SSP:
1194 case LPSS_CNL_SSP:
1195 config = lpss_get_config(drv_data);
1196 tx_thres = config->tx_threshold_lo;
1197 tx_hi_thres = config->tx_threshold_hi;
1198 rx_thres = config->rx_threshold;
1199 break;
1200 default:
1201 tx_hi_thres = 0;
1202 if (spi_controller_is_slave(drv_data->controller)) {
1203 tx_thres = 1;
1204 rx_thres = 2;
1205 } else {
1206 tx_thres = TX_THRESH_DFLT;
1207 rx_thres = RX_THRESH_DFLT;
1208 }
1209 break;
1210 }
1211
1212 /* Only allocate on the first setup */
1213 chip = spi_get_ctldata(spi);
1214 if (!chip) {
1215 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1216 if (!chip)
1217 return -ENOMEM;
1218
1219 if (drv_data->ssp_type == CE4100_SSP) {
1220 if (spi->chip_select > 4) {
1221 dev_err(&spi->dev,
1222 "failed setup: cs number must not be > 4.\n");
1223 kfree(chip);
1224 return -EINVAL;
1225 }
1226 }
1227 chip->enable_dma = drv_data->controller_info->enable_dma;
1228 chip->timeout = TIMOUT_DFLT;
1229 }
1230
1231 /*
1232 * Protocol drivers may change the chip settings, so...
1233 * if chip_info exists, use it.
1234 */
1235 chip_info = spi->controller_data;
1236
1237 /* chip_info isn't always needed */
1238 if (chip_info) {
1239 if (chip_info->timeout)
1240 chip->timeout = chip_info->timeout;
1241 if (chip_info->tx_threshold)
1242 tx_thres = chip_info->tx_threshold;
1243 if (chip_info->tx_hi_threshold)
1244 tx_hi_thres = chip_info->tx_hi_threshold;
1245 if (chip_info->rx_threshold)
1246 rx_thres = chip_info->rx_threshold;
1247 chip->dma_threshold = 0;
1248 }
1249
1250 chip->cr1 = 0;
1251 if (spi_controller_is_slave(drv_data->controller)) {
1252 chip->cr1 |= SSCR1_SCFR;
1253 chip->cr1 |= SSCR1_SCLKDIR;
1254 chip->cr1 |= SSCR1_SFRMDIR;
1255 chip->cr1 |= SSCR1_SPH;
1256 }
1257
1258 if (is_lpss_ssp(drv_data)) {
1259 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1260 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1261 SSITF_TxHiThresh(tx_hi_thres);
1262 }
1263
1264 if (is_mrfld_ssp(drv_data)) {
1265 chip->lpss_rx_threshold = rx_thres;
1266 chip->lpss_tx_threshold = tx_thres;
1267 }
1268
1269 /*
1270 * Set DMA burst and threshold outside of chip_info path so that if
1271 * chip_info goes away after setting chip->enable_dma, the burst and
1272 * threshold can still respond to changes in bits_per_word.
1273 */
1274 if (chip->enable_dma) {
1275 /* Set up legal burst and threshold for DMA */
1276 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1277 spi->bits_per_word,
1278 &chip->dma_burst_size,
1279 &chip->dma_threshold)) {
1280 dev_warn(&spi->dev,
1281 "in setup: DMA burst size reduced to match bits_per_word\n");
1282 }
1283 dev_dbg(&spi->dev,
1284 "in setup: DMA burst size set to %u\n",
1285 chip->dma_burst_size);
1286 }
1287
1288 switch (drv_data->ssp_type) {
1289 case QUARK_X1000_SSP:
1290 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1291 & QUARK_X1000_SSCR1_RFT)
1292 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1293 & QUARK_X1000_SSCR1_TFT);
1294 break;
1295 case CE4100_SSP:
1296 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1297 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1298 break;
1299 default:
1300 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1301 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1302 break;
1303 }
1304
1305 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1306 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1307 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1308
1309 if (spi->mode & SPI_LOOP)
1310 chip->cr1 |= SSCR1_LBM;
1311
1312 spi_set_ctldata(spi, chip);
1313
1314 return 0;
1315}
1316
1317static void cleanup(struct spi_device *spi)
1318{
1319 struct chip_data *chip = spi_get_ctldata(spi);
1320
1321 kfree(chip);
1322}
1323
1324static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1325{
1326 return param == chan->device->dev;
1327}
1328
1329static struct pxa2xx_spi_controller *
1330pxa2xx_spi_init_pdata(struct platform_device *pdev)
1331{
1332 struct pxa2xx_spi_controller *pdata;
1333 struct device *dev = &pdev->dev;
1334 struct device *parent = dev->parent;
1335 struct ssp_device *ssp;
1336 struct resource *res;
1337 enum pxa_ssp_type type = SSP_UNDEFINED;
1338 const void *match;
1339 bool is_lpss_priv;
1340 int status;
1341 u64 uid;
1342
1343 is_lpss_priv = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpss_priv");
1344
1345 match = device_get_match_data(dev);
1346 if (match)
1347 type = (enum pxa_ssp_type)match;
1348 else if (is_lpss_priv) {
1349 u32 value;
1350
1351 status = device_property_read_u32(dev, "intel,spi-pxa2xx-type", &value);
1352 if (status)
1353 return ERR_PTR(status);
1354
1355 type = (enum pxa_ssp_type)value;
1356 }
1357
1358 /* Validate the SSP type correctness */
1359 if (!(type > SSP_UNDEFINED && type < SSP_MAX))
1360 return ERR_PTR(-EINVAL);
1361
1362 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1363 if (!pdata)
1364 return ERR_PTR(-ENOMEM);
1365
1366 ssp = &pdata->ssp;
1367
1368 ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1369 if (IS_ERR(ssp->mmio_base))
1370 return ERR_CAST(ssp->mmio_base);
1371
1372 ssp->phys_base = res->start;
1373
1374 /* Platforms with iDMA 64-bit */
1375 if (is_lpss_priv) {
1376 pdata->tx_param = parent;
1377 pdata->rx_param = parent;
1378 pdata->dma_filter = pxa2xx_spi_idma_filter;
1379 }
1380
1381 ssp->clk = devm_clk_get(dev, NULL);
1382 if (IS_ERR(ssp->clk))
1383 return ERR_CAST(ssp->clk);
1384
1385 ssp->irq = platform_get_irq(pdev, 0);
1386 if (ssp->irq < 0)
1387 return ERR_PTR(ssp->irq);
1388
1389 ssp->type = type;
1390 ssp->dev = dev;
1391
1392 status = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &uid);
1393 if (status)
1394 ssp->port_id = -1;
1395 else
1396 ssp->port_id = uid;
1397
1398 pdata->is_slave = device_property_read_bool(dev, "spi-slave");
1399 pdata->num_chipselect = 1;
1400 pdata->enable_dma = true;
1401 pdata->dma_burst_size = 1;
1402
1403 return pdata;
1404}
1405
1406static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1407 unsigned int cs)
1408{
1409 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1410
1411 if (has_acpi_companion(drv_data->ssp->dev)) {
1412 switch (drv_data->ssp_type) {
1413 /*
1414 * For Atoms the ACPI DeviceSelection used by the Windows
1415 * driver starts from 1 instead of 0 so translate it here
1416 * to match what Linux expects.
1417 */
1418 case LPSS_BYT_SSP:
1419 case LPSS_BSW_SSP:
1420 return cs - 1;
1421
1422 default:
1423 break;
1424 }
1425 }
1426
1427 return cs;
1428}
1429
1430static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1431{
1432 return MAX_DMA_LEN;
1433}
1434
1435static int pxa2xx_spi_probe(struct platform_device *pdev)
1436{
1437 struct device *dev = &pdev->dev;
1438 struct pxa2xx_spi_controller *platform_info;
1439 struct spi_controller *controller;
1440 struct driver_data *drv_data;
1441 struct ssp_device *ssp;
1442 const struct lpss_config *config;
1443 int status;
1444 u32 tmp;
1445
1446 platform_info = dev_get_platdata(dev);
1447 if (!platform_info) {
1448 platform_info = pxa2xx_spi_init_pdata(pdev);
1449 if (IS_ERR(platform_info)) {
1450 dev_err(&pdev->dev, "missing platform data\n");
1451 return PTR_ERR(platform_info);
1452 }
1453 }
1454
1455 ssp = pxa_ssp_request(pdev->id, pdev->name);
1456 if (!ssp)
1457 ssp = &platform_info->ssp;
1458
1459 if (!ssp->mmio_base) {
1460 dev_err(&pdev->dev, "failed to get SSP\n");
1461 return -ENODEV;
1462 }
1463
1464 if (platform_info->is_slave)
1465 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1466 else
1467 controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1468
1469 if (!controller) {
1470 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1471 status = -ENOMEM;
1472 goto out_error_controller_alloc;
1473 }
1474 drv_data = spi_controller_get_devdata(controller);
1475 drv_data->controller = controller;
1476 drv_data->controller_info = platform_info;
1477 drv_data->ssp = ssp;
1478
1479 device_set_node(&controller->dev, dev_fwnode(dev));
1480
1481 /* The spi->mode bits understood by this driver: */
1482 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1483
1484 controller->bus_num = ssp->port_id;
1485 controller->dma_alignment = DMA_ALIGNMENT;
1486 controller->cleanup = cleanup;
1487 controller->setup = setup;
1488 controller->set_cs = pxa2xx_spi_set_cs;
1489 controller->transfer_one = pxa2xx_spi_transfer_one;
1490 controller->slave_abort = pxa2xx_spi_slave_abort;
1491 controller->handle_err = pxa2xx_spi_handle_err;
1492 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1493 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1494 controller->auto_runtime_pm = true;
1495 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1496
1497 drv_data->ssp_type = ssp->type;
1498
1499 if (pxa25x_ssp_comp(drv_data)) {
1500 switch (drv_data->ssp_type) {
1501 case QUARK_X1000_SSP:
1502 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1503 break;
1504 default:
1505 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1506 break;
1507 }
1508
1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1510 drv_data->dma_cr1 = 0;
1511 drv_data->clear_sr = SSSR_ROR;
1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1513 } else {
1514 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1516 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1519 | SSSR_ROR | SSSR_TUR;
1520 }
1521
1522 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1523 drv_data);
1524 if (status < 0) {
1525 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1526 goto out_error_controller_alloc;
1527 }
1528
1529 /* Setup DMA if requested */
1530 if (platform_info->enable_dma) {
1531 status = pxa2xx_spi_dma_setup(drv_data);
1532 if (status) {
1533 dev_warn(dev, "no DMA channels available, using PIO\n");
1534 platform_info->enable_dma = false;
1535 } else {
1536 controller->can_dma = pxa2xx_spi_can_dma;
1537 controller->max_dma_len = MAX_DMA_LEN;
1538 controller->max_transfer_size =
1539 pxa2xx_spi_max_dma_transfer_size;
1540 }
1541 }
1542
1543 /* Enable SOC clock */
1544 status = clk_prepare_enable(ssp->clk);
1545 if (status)
1546 goto out_error_dma_irq_alloc;
1547
1548 controller->max_speed_hz = clk_get_rate(ssp->clk);
1549 /*
1550 * Set minimum speed for all other platforms than Intel Quark which is
1551 * able do under 1 Hz transfers.
1552 */
1553 if (!pxa25x_ssp_comp(drv_data))
1554 controller->min_speed_hz =
1555 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1556 else if (!is_quark_x1000_ssp(drv_data))
1557 controller->min_speed_hz =
1558 DIV_ROUND_UP(controller->max_speed_hz, 512);
1559
1560 pxa_ssp_disable(ssp);
1561
1562 /* Load default SSP configuration */
1563 switch (drv_data->ssp_type) {
1564 case QUARK_X1000_SSP:
1565 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1566 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1567 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1568
1569 /* Using the Motorola SPI protocol and use 8 bit frame */
1570 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1571 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1572 break;
1573 case CE4100_SSP:
1574 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1575 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1576 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1577 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1578 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1579 break;
1580 default:
1581
1582 if (spi_controller_is_slave(controller)) {
1583 tmp = SSCR1_SCFR |
1584 SSCR1_SCLKDIR |
1585 SSCR1_SFRMDIR |
1586 SSCR1_RxTresh(2) |
1587 SSCR1_TxTresh(1) |
1588 SSCR1_SPH;
1589 } else {
1590 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1591 SSCR1_TxTresh(TX_THRESH_DFLT);
1592 }
1593 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1594 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1595 if (!spi_controller_is_slave(controller))
1596 tmp |= SSCR0_SCR(2);
1597 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1598 break;
1599 }
1600
1601 if (!pxa25x_ssp_comp(drv_data))
1602 pxa2xx_spi_write(drv_data, SSTO, 0);
1603
1604 if (!is_quark_x1000_ssp(drv_data))
1605 pxa2xx_spi_write(drv_data, SSPSP, 0);
1606
1607 if (is_lpss_ssp(drv_data)) {
1608 lpss_ssp_setup(drv_data);
1609 config = lpss_get_config(drv_data);
1610 if (config->reg_capabilities >= 0) {
1611 tmp = __lpss_ssp_read_priv(drv_data,
1612 config->reg_capabilities);
1613 tmp &= LPSS_CAPS_CS_EN_MASK;
1614 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1615 platform_info->num_chipselect = ffz(tmp);
1616 } else if (config->cs_num) {
1617 platform_info->num_chipselect = config->cs_num;
1618 }
1619 }
1620 controller->num_chipselect = platform_info->num_chipselect;
1621 controller->use_gpio_descriptors = true;
1622
1623 if (platform_info->is_slave) {
1624 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1625 "ready", GPIOD_OUT_LOW);
1626 if (IS_ERR(drv_data->gpiod_ready)) {
1627 status = PTR_ERR(drv_data->gpiod_ready);
1628 goto out_error_clock_enabled;
1629 }
1630 }
1631
1632 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1633 pm_runtime_use_autosuspend(&pdev->dev);
1634 pm_runtime_set_active(&pdev->dev);
1635 pm_runtime_enable(&pdev->dev);
1636
1637 /* Register with the SPI framework */
1638 platform_set_drvdata(pdev, drv_data);
1639 status = spi_register_controller(controller);
1640 if (status) {
1641 dev_err(&pdev->dev, "problem registering SPI controller\n");
1642 goto out_error_pm_runtime_enabled;
1643 }
1644
1645 return status;
1646
1647out_error_pm_runtime_enabled:
1648 pm_runtime_disable(&pdev->dev);
1649
1650out_error_clock_enabled:
1651 clk_disable_unprepare(ssp->clk);
1652
1653out_error_dma_irq_alloc:
1654 pxa2xx_spi_dma_release(drv_data);
1655 free_irq(ssp->irq, drv_data);
1656
1657out_error_controller_alloc:
1658 pxa_ssp_free(ssp);
1659 return status;
1660}
1661
1662static int pxa2xx_spi_remove(struct platform_device *pdev)
1663{
1664 struct driver_data *drv_data = platform_get_drvdata(pdev);
1665 struct ssp_device *ssp = drv_data->ssp;
1666
1667 pm_runtime_get_sync(&pdev->dev);
1668
1669 spi_unregister_controller(drv_data->controller);
1670
1671 /* Disable the SSP at the peripheral and SOC level */
1672 pxa_ssp_disable(ssp);
1673 clk_disable_unprepare(ssp->clk);
1674
1675 /* Release DMA */
1676 if (drv_data->controller_info->enable_dma)
1677 pxa2xx_spi_dma_release(drv_data);
1678
1679 pm_runtime_put_noidle(&pdev->dev);
1680 pm_runtime_disable(&pdev->dev);
1681
1682 /* Release IRQ */
1683 free_irq(ssp->irq, drv_data);
1684
1685 /* Release SSP */
1686 pxa_ssp_free(ssp);
1687
1688 return 0;
1689}
1690
1691static int pxa2xx_spi_suspend(struct device *dev)
1692{
1693 struct driver_data *drv_data = dev_get_drvdata(dev);
1694 struct ssp_device *ssp = drv_data->ssp;
1695 int status;
1696
1697 status = spi_controller_suspend(drv_data->controller);
1698 if (status)
1699 return status;
1700
1701 pxa_ssp_disable(ssp);
1702
1703 if (!pm_runtime_suspended(dev))
1704 clk_disable_unprepare(ssp->clk);
1705
1706 return 0;
1707}
1708
1709static int pxa2xx_spi_resume(struct device *dev)
1710{
1711 struct driver_data *drv_data = dev_get_drvdata(dev);
1712 struct ssp_device *ssp = drv_data->ssp;
1713 int status;
1714
1715 /* Enable the SSP clock */
1716 if (!pm_runtime_suspended(dev)) {
1717 status = clk_prepare_enable(ssp->clk);
1718 if (status)
1719 return status;
1720 }
1721
1722 /* Start the queue running */
1723 return spi_controller_resume(drv_data->controller);
1724}
1725
1726static int pxa2xx_spi_runtime_suspend(struct device *dev)
1727{
1728 struct driver_data *drv_data = dev_get_drvdata(dev);
1729
1730 clk_disable_unprepare(drv_data->ssp->clk);
1731 return 0;
1732}
1733
1734static int pxa2xx_spi_runtime_resume(struct device *dev)
1735{
1736 struct driver_data *drv_data = dev_get_drvdata(dev);
1737
1738 return clk_prepare_enable(drv_data->ssp->clk);
1739}
1740
1741static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1742 SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1743 RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1744};
1745
1746#ifdef CONFIG_ACPI
1747static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1748 { "80860F0E", LPSS_BYT_SSP },
1749 { "8086228E", LPSS_BSW_SSP },
1750 { "INT33C0", LPSS_LPT_SSP },
1751 { "INT33C1", LPSS_LPT_SSP },
1752 { "INT3430", LPSS_LPT_SSP },
1753 { "INT3431", LPSS_LPT_SSP },
1754 {}
1755};
1756MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1757#endif
1758
1759static const struct of_device_id pxa2xx_spi_of_match[] = {
1760 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1761 {}
1762};
1763MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1764
1765static struct platform_driver driver = {
1766 .driver = {
1767 .name = "pxa2xx-spi",
1768 .pm = pm_ptr(&pxa2xx_spi_pm_ops),
1769 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1770 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1771 },
1772 .probe = pxa2xx_spi_probe,
1773 .remove = pxa2xx_spi_remove,
1774};
1775
1776static int __init pxa2xx_spi_init(void)
1777{
1778 return platform_driver_register(&driver);
1779}
1780subsys_initcall(pxa2xx_spi_init);
1781
1782static void __exit pxa2xx_spi_exit(void)
1783{
1784 platform_driver_unregister(&driver);
1785}
1786module_exit(pxa2xx_spi_exit);
1787
1788MODULE_SOFTDEP("pre: dw_dmac");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, Intel Corporation
5 */
6
7#include <linux/bitops.h>
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/device.h>
11#include <linux/ioport.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/platform_device.h>
18#include <linux/spi/pxa2xx_spi.h>
19#include <linux/spi/spi.h>
20#include <linux/delay.h>
21#include <linux/gpio.h>
22#include <linux/gpio/consumer.h>
23#include <linux/slab.h>
24#include <linux/clk.h>
25#include <linux/pm_runtime.h>
26#include <linux/acpi.h>
27#include <linux/of_device.h>
28
29#include "spi-pxa2xx.h"
30
31MODULE_AUTHOR("Stephen Street");
32MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
33MODULE_LICENSE("GPL");
34MODULE_ALIAS("platform:pxa2xx-spi");
35
36#define TIMOUT_DFLT 1000
37
38/*
39 * for testing SSCR1 changes that require SSP restart, basically
40 * everything except the service and interrupt enables, the pxa270 developer
41 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
42 * list, but the PXA255 dev man says all bits without really meaning the
43 * service and interrupt enables
44 */
45#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
46 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
47 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
48 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
49 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
50 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
51
52#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
53 | QUARK_X1000_SSCR1_EFWR \
54 | QUARK_X1000_SSCR1_RFT \
55 | QUARK_X1000_SSCR1_TFT \
56 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
57
58#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
59 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
60 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
61 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
62 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
65#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66#define LPSS_CS_CONTROL_SW_MODE BIT(0)
67#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68#define LPSS_CAPS_CS_EN_SHIFT 9
69#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
70
71struct lpss_config {
72 /* LPSS offset from drv_data->ioaddr */
73 unsigned offset;
74 /* Register offsets from drv_data->lpss_base or -1 */
75 int reg_general;
76 int reg_ssp;
77 int reg_cs_ctrl;
78 int reg_capabilities;
79 /* FIFO thresholds */
80 u32 rx_threshold;
81 u32 tx_threshold_lo;
82 u32 tx_threshold_hi;
83 /* Chip select control */
84 unsigned cs_sel_shift;
85 unsigned cs_sel_mask;
86 unsigned cs_num;
87};
88
89/* Keep these sorted with enum pxa_ssp_type */
90static const struct lpss_config lpss_platforms[] = {
91 { /* LPSS_LPT_SSP */
92 .offset = 0x800,
93 .reg_general = 0x08,
94 .reg_ssp = 0x0c,
95 .reg_cs_ctrl = 0x18,
96 .reg_capabilities = -1,
97 .rx_threshold = 64,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
100 },
101 { /* LPSS_BYT_SSP */
102 .offset = 0x400,
103 .reg_general = 0x08,
104 .reg_ssp = 0x0c,
105 .reg_cs_ctrl = 0x18,
106 .reg_capabilities = -1,
107 .rx_threshold = 64,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
110 },
111 { /* LPSS_BSW_SSP */
112 .offset = 0x400,
113 .reg_general = 0x08,
114 .reg_ssp = 0x0c,
115 .reg_cs_ctrl = 0x18,
116 .reg_capabilities = -1,
117 .rx_threshold = 64,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
120 .cs_sel_shift = 2,
121 .cs_sel_mask = 1 << 2,
122 .cs_num = 2,
123 },
124 { /* LPSS_SPT_SSP */
125 .offset = 0x200,
126 .reg_general = -1,
127 .reg_ssp = 0x20,
128 .reg_cs_ctrl = 0x24,
129 .reg_capabilities = -1,
130 .rx_threshold = 1,
131 .tx_threshold_lo = 32,
132 .tx_threshold_hi = 56,
133 },
134 { /* LPSS_BXT_SSP */
135 .offset = 0x200,
136 .reg_general = -1,
137 .reg_ssp = 0x20,
138 .reg_cs_ctrl = 0x24,
139 .reg_capabilities = 0xfc,
140 .rx_threshold = 1,
141 .tx_threshold_lo = 16,
142 .tx_threshold_hi = 48,
143 .cs_sel_shift = 8,
144 .cs_sel_mask = 3 << 8,
145 },
146 { /* LPSS_CNL_SSP */
147 .offset = 0x200,
148 .reg_general = -1,
149 .reg_ssp = 0x20,
150 .reg_cs_ctrl = 0x24,
151 .reg_capabilities = 0xfc,
152 .rx_threshold = 1,
153 .tx_threshold_lo = 32,
154 .tx_threshold_hi = 56,
155 .cs_sel_shift = 8,
156 .cs_sel_mask = 3 << 8,
157 },
158};
159
160static inline const struct lpss_config
161*lpss_get_config(const struct driver_data *drv_data)
162{
163 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
164}
165
166static bool is_lpss_ssp(const struct driver_data *drv_data)
167{
168 switch (drv_data->ssp_type) {
169 case LPSS_LPT_SSP:
170 case LPSS_BYT_SSP:
171 case LPSS_BSW_SSP:
172 case LPSS_SPT_SSP:
173 case LPSS_BXT_SSP:
174 case LPSS_CNL_SSP:
175 return true;
176 default:
177 return false;
178 }
179}
180
181static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
182{
183 return drv_data->ssp_type == QUARK_X1000_SSP;
184}
185
186static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
187{
188 switch (drv_data->ssp_type) {
189 case QUARK_X1000_SSP:
190 return QUARK_X1000_SSCR1_CHANGE_MASK;
191 case CE4100_SSP:
192 return CE4100_SSCR1_CHANGE_MASK;
193 default:
194 return SSCR1_CHANGE_MASK;
195 }
196}
197
198static u32
199pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
200{
201 switch (drv_data->ssp_type) {
202 case QUARK_X1000_SSP:
203 return RX_THRESH_QUARK_X1000_DFLT;
204 case CE4100_SSP:
205 return RX_THRESH_CE4100_DFLT;
206 default:
207 return RX_THRESH_DFLT;
208 }
209}
210
211static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
212{
213 u32 mask;
214
215 switch (drv_data->ssp_type) {
216 case QUARK_X1000_SSP:
217 mask = QUARK_X1000_SSSR_TFL_MASK;
218 break;
219 case CE4100_SSP:
220 mask = CE4100_SSSR_TFL_MASK;
221 break;
222 default:
223 mask = SSSR_TFL_MASK;
224 break;
225 }
226
227 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
228}
229
230static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
231 u32 *sccr1_reg)
232{
233 u32 mask;
234
235 switch (drv_data->ssp_type) {
236 case QUARK_X1000_SSP:
237 mask = QUARK_X1000_SSCR1_RFT;
238 break;
239 case CE4100_SSP:
240 mask = CE4100_SSCR1_RFT;
241 break;
242 default:
243 mask = SSCR1_RFT;
244 break;
245 }
246 *sccr1_reg &= ~mask;
247}
248
249static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
250 u32 *sccr1_reg, u32 threshold)
251{
252 switch (drv_data->ssp_type) {
253 case QUARK_X1000_SSP:
254 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
255 break;
256 case CE4100_SSP:
257 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
258 break;
259 default:
260 *sccr1_reg |= SSCR1_RxTresh(threshold);
261 break;
262 }
263}
264
265static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
266 u32 clk_div, u8 bits)
267{
268 switch (drv_data->ssp_type) {
269 case QUARK_X1000_SSP:
270 return clk_div
271 | QUARK_X1000_SSCR0_Motorola
272 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
273 | SSCR0_SSE;
274 default:
275 return clk_div
276 | SSCR0_Motorola
277 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
278 | SSCR0_SSE
279 | (bits > 16 ? SSCR0_EDSS : 0);
280 }
281}
282
283/*
284 * Read and write LPSS SSP private registers. Caller must first check that
285 * is_lpss_ssp() returns true before these can be called.
286 */
287static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
288{
289 WARN_ON(!drv_data->lpss_base);
290 return readl(drv_data->lpss_base + offset);
291}
292
293static void __lpss_ssp_write_priv(struct driver_data *drv_data,
294 unsigned offset, u32 value)
295{
296 WARN_ON(!drv_data->lpss_base);
297 writel(value, drv_data->lpss_base + offset);
298}
299
300/*
301 * lpss_ssp_setup - perform LPSS SSP specific setup
302 * @drv_data: pointer to the driver private data
303 *
304 * Perform LPSS SSP specific setup. This function must be called first if
305 * one is going to use LPSS SSP private registers.
306 */
307static void lpss_ssp_setup(struct driver_data *drv_data)
308{
309 const struct lpss_config *config;
310 u32 value;
311
312 config = lpss_get_config(drv_data);
313 drv_data->lpss_base = drv_data->ioaddr + config->offset;
314
315 /* Enable software chip select control */
316 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
317 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
318 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
319 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
320
321 /* Enable multiblock DMA transfers */
322 if (drv_data->controller_info->enable_dma) {
323 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
324
325 if (config->reg_general >= 0) {
326 value = __lpss_ssp_read_priv(drv_data,
327 config->reg_general);
328 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
329 __lpss_ssp_write_priv(drv_data,
330 config->reg_general, value);
331 }
332 }
333}
334
335static void lpss_ssp_select_cs(struct spi_device *spi,
336 const struct lpss_config *config)
337{
338 struct driver_data *drv_data =
339 spi_controller_get_devdata(spi->controller);
340 u32 value, cs;
341
342 if (!config->cs_sel_mask)
343 return;
344
345 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
346
347 cs = spi->chip_select;
348 cs <<= config->cs_sel_shift;
349 if (cs != (value & config->cs_sel_mask)) {
350 /*
351 * When switching another chip select output active the
352 * output must be selected first and wait 2 ssp_clk cycles
353 * before changing state to active. Otherwise a short
354 * glitch will occur on the previous chip select since
355 * output select is latched but state control is not.
356 */
357 value &= ~config->cs_sel_mask;
358 value |= cs;
359 __lpss_ssp_write_priv(drv_data,
360 config->reg_cs_ctrl, value);
361 ndelay(1000000000 /
362 (drv_data->controller->max_speed_hz / 2));
363 }
364}
365
366static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
367{
368 struct driver_data *drv_data =
369 spi_controller_get_devdata(spi->controller);
370 const struct lpss_config *config;
371 u32 value;
372
373 config = lpss_get_config(drv_data);
374
375 if (enable)
376 lpss_ssp_select_cs(spi, config);
377
378 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
379 if (enable)
380 value &= ~LPSS_CS_CONTROL_CS_HIGH;
381 else
382 value |= LPSS_CS_CONTROL_CS_HIGH;
383 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
384}
385
386static void cs_assert(struct spi_device *spi)
387{
388 struct chip_data *chip = spi_get_ctldata(spi);
389 struct driver_data *drv_data =
390 spi_controller_get_devdata(spi->controller);
391
392 if (drv_data->ssp_type == CE4100_SSP) {
393 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
394 return;
395 }
396
397 if (chip->cs_control) {
398 chip->cs_control(PXA2XX_CS_ASSERT);
399 return;
400 }
401
402 if (chip->gpiod_cs) {
403 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
404 return;
405 }
406
407 if (is_lpss_ssp(drv_data))
408 lpss_ssp_cs_control(spi, true);
409}
410
411static void cs_deassert(struct spi_device *spi)
412{
413 struct chip_data *chip = spi_get_ctldata(spi);
414 struct driver_data *drv_data =
415 spi_controller_get_devdata(spi->controller);
416 unsigned long timeout;
417
418 if (drv_data->ssp_type == CE4100_SSP)
419 return;
420
421 /* Wait until SSP becomes idle before deasserting the CS */
422 timeout = jiffies + msecs_to_jiffies(10);
423 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
424 !time_after(jiffies, timeout))
425 cpu_relax();
426
427 if (chip->cs_control) {
428 chip->cs_control(PXA2XX_CS_DEASSERT);
429 return;
430 }
431
432 if (chip->gpiod_cs) {
433 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
434 return;
435 }
436
437 if (is_lpss_ssp(drv_data))
438 lpss_ssp_cs_control(spi, false);
439}
440
441static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
442{
443 if (level)
444 cs_deassert(spi);
445 else
446 cs_assert(spi);
447}
448
449int pxa2xx_spi_flush(struct driver_data *drv_data)
450{
451 unsigned long limit = loops_per_jiffy << 1;
452
453 do {
454 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
455 pxa2xx_spi_read(drv_data, SSDR);
456 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
457 write_SSSR_CS(drv_data, SSSR_ROR);
458
459 return limit;
460}
461
462static int null_writer(struct driver_data *drv_data)
463{
464 u8 n_bytes = drv_data->n_bytes;
465
466 if (pxa2xx_spi_txfifo_full(drv_data)
467 || (drv_data->tx == drv_data->tx_end))
468 return 0;
469
470 pxa2xx_spi_write(drv_data, SSDR, 0);
471 drv_data->tx += n_bytes;
472
473 return 1;
474}
475
476static int null_reader(struct driver_data *drv_data)
477{
478 u8 n_bytes = drv_data->n_bytes;
479
480 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
481 && (drv_data->rx < drv_data->rx_end)) {
482 pxa2xx_spi_read(drv_data, SSDR);
483 drv_data->rx += n_bytes;
484 }
485
486 return drv_data->rx == drv_data->rx_end;
487}
488
489static int u8_writer(struct driver_data *drv_data)
490{
491 if (pxa2xx_spi_txfifo_full(drv_data)
492 || (drv_data->tx == drv_data->tx_end))
493 return 0;
494
495 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
496 ++drv_data->tx;
497
498 return 1;
499}
500
501static int u8_reader(struct driver_data *drv_data)
502{
503 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
504 && (drv_data->rx < drv_data->rx_end)) {
505 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
506 ++drv_data->rx;
507 }
508
509 return drv_data->rx == drv_data->rx_end;
510}
511
512static int u16_writer(struct driver_data *drv_data)
513{
514 if (pxa2xx_spi_txfifo_full(drv_data)
515 || (drv_data->tx == drv_data->tx_end))
516 return 0;
517
518 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
519 drv_data->tx += 2;
520
521 return 1;
522}
523
524static int u16_reader(struct driver_data *drv_data)
525{
526 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
527 && (drv_data->rx < drv_data->rx_end)) {
528 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
529 drv_data->rx += 2;
530 }
531
532 return drv_data->rx == drv_data->rx_end;
533}
534
535static int u32_writer(struct driver_data *drv_data)
536{
537 if (pxa2xx_spi_txfifo_full(drv_data)
538 || (drv_data->tx == drv_data->tx_end))
539 return 0;
540
541 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
542 drv_data->tx += 4;
543
544 return 1;
545}
546
547static int u32_reader(struct driver_data *drv_data)
548{
549 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
550 && (drv_data->rx < drv_data->rx_end)) {
551 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
552 drv_data->rx += 4;
553 }
554
555 return drv_data->rx == drv_data->rx_end;
556}
557
558static void reset_sccr1(struct driver_data *drv_data)
559{
560 struct chip_data *chip =
561 spi_get_ctldata(drv_data->controller->cur_msg->spi);
562 u32 sccr1_reg;
563
564 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
565 switch (drv_data->ssp_type) {
566 case QUARK_X1000_SSP:
567 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
568 break;
569 case CE4100_SSP:
570 sccr1_reg &= ~CE4100_SSCR1_RFT;
571 break;
572 default:
573 sccr1_reg &= ~SSCR1_RFT;
574 break;
575 }
576 sccr1_reg |= chip->threshold;
577 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
578}
579
580static void int_error_stop(struct driver_data *drv_data, const char* msg)
581{
582 /* Stop and reset SSP */
583 write_SSSR_CS(drv_data, drv_data->clear_sr);
584 reset_sccr1(drv_data);
585 if (!pxa25x_ssp_comp(drv_data))
586 pxa2xx_spi_write(drv_data, SSTO, 0);
587 pxa2xx_spi_flush(drv_data);
588 pxa2xx_spi_write(drv_data, SSCR0,
589 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
590
591 dev_err(&drv_data->pdev->dev, "%s\n", msg);
592
593 drv_data->controller->cur_msg->status = -EIO;
594 spi_finalize_current_transfer(drv_data->controller);
595}
596
597static void int_transfer_complete(struct driver_data *drv_data)
598{
599 /* Clear and disable interrupts */
600 write_SSSR_CS(drv_data, drv_data->clear_sr);
601 reset_sccr1(drv_data);
602 if (!pxa25x_ssp_comp(drv_data))
603 pxa2xx_spi_write(drv_data, SSTO, 0);
604
605 spi_finalize_current_transfer(drv_data->controller);
606}
607
608static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
609{
610 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
611 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
612
613 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
614
615 if (irq_status & SSSR_ROR) {
616 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
617 return IRQ_HANDLED;
618 }
619
620 if (irq_status & SSSR_TUR) {
621 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
622 return IRQ_HANDLED;
623 }
624
625 if (irq_status & SSSR_TINT) {
626 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
627 if (drv_data->read(drv_data)) {
628 int_transfer_complete(drv_data);
629 return IRQ_HANDLED;
630 }
631 }
632
633 /* Drain rx fifo, Fill tx fifo and prevent overruns */
634 do {
635 if (drv_data->read(drv_data)) {
636 int_transfer_complete(drv_data);
637 return IRQ_HANDLED;
638 }
639 } while (drv_data->write(drv_data));
640
641 if (drv_data->read(drv_data)) {
642 int_transfer_complete(drv_data);
643 return IRQ_HANDLED;
644 }
645
646 if (drv_data->tx == drv_data->tx_end) {
647 u32 bytes_left;
648 u32 sccr1_reg;
649
650 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
651 sccr1_reg &= ~SSCR1_TIE;
652
653 /*
654 * PXA25x_SSP has no timeout, set up rx threshould for the
655 * remaining RX bytes.
656 */
657 if (pxa25x_ssp_comp(drv_data)) {
658 u32 rx_thre;
659
660 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
661
662 bytes_left = drv_data->rx_end - drv_data->rx;
663 switch (drv_data->n_bytes) {
664 case 4:
665 bytes_left >>= 2;
666 break;
667 case 2:
668 bytes_left >>= 1;
669 break;
670 }
671
672 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
673 if (rx_thre > bytes_left)
674 rx_thre = bytes_left;
675
676 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
677 }
678 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
679 }
680
681 /* We did something */
682 return IRQ_HANDLED;
683}
684
685static void handle_bad_msg(struct driver_data *drv_data)
686{
687 pxa2xx_spi_write(drv_data, SSCR0,
688 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
689 pxa2xx_spi_write(drv_data, SSCR1,
690 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
691 if (!pxa25x_ssp_comp(drv_data))
692 pxa2xx_spi_write(drv_data, SSTO, 0);
693 write_SSSR_CS(drv_data, drv_data->clear_sr);
694
695 dev_err(&drv_data->pdev->dev,
696 "bad message state in interrupt handler\n");
697}
698
699static irqreturn_t ssp_int(int irq, void *dev_id)
700{
701 struct driver_data *drv_data = dev_id;
702 u32 sccr1_reg;
703 u32 mask = drv_data->mask_sr;
704 u32 status;
705
706 /*
707 * The IRQ might be shared with other peripherals so we must first
708 * check that are we RPM suspended or not. If we are we assume that
709 * the IRQ was not for us (we shouldn't be RPM suspended when the
710 * interrupt is enabled).
711 */
712 if (pm_runtime_suspended(&drv_data->pdev->dev))
713 return IRQ_NONE;
714
715 /*
716 * If the device is not yet in RPM suspended state and we get an
717 * interrupt that is meant for another device, check if status bits
718 * are all set to one. That means that the device is already
719 * powered off.
720 */
721 status = pxa2xx_spi_read(drv_data, SSSR);
722 if (status == ~0)
723 return IRQ_NONE;
724
725 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
726
727 /* Ignore possible writes if we don't need to write */
728 if (!(sccr1_reg & SSCR1_TIE))
729 mask &= ~SSSR_TFS;
730
731 /* Ignore RX timeout interrupt if it is disabled */
732 if (!(sccr1_reg & SSCR1_TINTE))
733 mask &= ~SSSR_TINT;
734
735 if (!(status & mask))
736 return IRQ_NONE;
737
738 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
739 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
740
741 if (!drv_data->controller->cur_msg) {
742 handle_bad_msg(drv_data);
743 /* Never fail */
744 return IRQ_HANDLED;
745 }
746
747 return drv_data->transfer_handler(drv_data);
748}
749
750/*
751 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
752 * input frequency by fractions of 2^24. It also has a divider by 5.
753 *
754 * There are formulas to get baud rate value for given input frequency and
755 * divider parameters, such as DDS_CLK_RATE and SCR:
756 *
757 * Fsys = 200MHz
758 *
759 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
760 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
761 *
762 * DDS_CLK_RATE either 2^n or 2^n / 5.
763 * SCR is in range 0 .. 255
764 *
765 * Divisor = 5^i * 2^j * 2 * k
766 * i = [0, 1] i = 1 iff j = 0 or j > 3
767 * j = [0, 23] j = 0 iff i = 1
768 * k = [1, 256]
769 * Special case: j = 0, i = 1: Divisor = 2 / 5
770 *
771 * Accordingly to the specification the recommended values for DDS_CLK_RATE
772 * are:
773 * Case 1: 2^n, n = [0, 23]
774 * Case 2: 2^24 * 2 / 5 (0x666666)
775 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
776 *
777 * In all cases the lowest possible value is better.
778 *
779 * The function calculates parameters for all cases and chooses the one closest
780 * to the asked baud rate.
781 */
782static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
783{
784 unsigned long xtal = 200000000;
785 unsigned long fref = xtal / 2; /* mandatory division by 2,
786 see (2) */
787 /* case 3 */
788 unsigned long fref1 = fref / 2; /* case 1 */
789 unsigned long fref2 = fref * 2 / 5; /* case 2 */
790 unsigned long scale;
791 unsigned long q, q1, q2;
792 long r, r1, r2;
793 u32 mul;
794
795 /* Case 1 */
796
797 /* Set initial value for DDS_CLK_RATE */
798 mul = (1 << 24) >> 1;
799
800 /* Calculate initial quot */
801 q1 = DIV_ROUND_UP(fref1, rate);
802
803 /* Scale q1 if it's too big */
804 if (q1 > 256) {
805 /* Scale q1 to range [1, 512] */
806 scale = fls_long(q1 - 1);
807 if (scale > 9) {
808 q1 >>= scale - 9;
809 mul >>= scale - 9;
810 }
811
812 /* Round the result if we have a remainder */
813 q1 += q1 & 1;
814 }
815
816 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
817 scale = __ffs(q1);
818 q1 >>= scale;
819 mul >>= scale;
820
821 /* Get the remainder */
822 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
823
824 /* Case 2 */
825
826 q2 = DIV_ROUND_UP(fref2, rate);
827 r2 = abs(fref2 / q2 - rate);
828
829 /*
830 * Choose the best between two: less remainder we have the better. We
831 * can't go case 2 if q2 is greater than 256 since SCR register can
832 * hold only values 0 .. 255.
833 */
834 if (r2 >= r1 || q2 > 256) {
835 /* case 1 is better */
836 r = r1;
837 q = q1;
838 } else {
839 /* case 2 is better */
840 r = r2;
841 q = q2;
842 mul = (1 << 24) * 2 / 5;
843 }
844
845 /* Check case 3 only if the divisor is big enough */
846 if (fref / rate >= 80) {
847 u64 fssp;
848 u32 m;
849
850 /* Calculate initial quot */
851 q1 = DIV_ROUND_UP(fref, rate);
852 m = (1 << 24) / q1;
853
854 /* Get the remainder */
855 fssp = (u64)fref * m;
856 do_div(fssp, 1 << 24);
857 r1 = abs(fssp - rate);
858
859 /* Choose this one if it suits better */
860 if (r1 < r) {
861 /* case 3 is better */
862 q = 1;
863 mul = m;
864 }
865 }
866
867 *dds = mul;
868 return q - 1;
869}
870
871static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
872{
873 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
874 const struct ssp_device *ssp = drv_data->ssp;
875
876 rate = min_t(int, ssp_clk, rate);
877
878 /*
879 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
880 * that the SSP transmission rate can be greater than the device rate
881 */
882 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
883 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
884 else
885 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
886}
887
888static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
889 int rate)
890{
891 struct chip_data *chip =
892 spi_get_ctldata(drv_data->controller->cur_msg->spi);
893 unsigned int clk_div;
894
895 switch (drv_data->ssp_type) {
896 case QUARK_X1000_SSP:
897 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
898 break;
899 default:
900 clk_div = ssp_get_clk_div(drv_data, rate);
901 break;
902 }
903 return clk_div << 8;
904}
905
906static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
907 struct spi_device *spi,
908 struct spi_transfer *xfer)
909{
910 struct chip_data *chip = spi_get_ctldata(spi);
911
912 return chip->enable_dma &&
913 xfer->len <= MAX_DMA_LEN &&
914 xfer->len >= chip->dma_burst_size;
915}
916
917static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
918 struct spi_device *spi,
919 struct spi_transfer *transfer)
920{
921 struct driver_data *drv_data = spi_controller_get_devdata(controller);
922 struct spi_message *message = controller->cur_msg;
923 struct chip_data *chip = spi_get_ctldata(spi);
924 u32 dma_thresh = chip->dma_threshold;
925 u32 dma_burst = chip->dma_burst_size;
926 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
927 u32 clk_div;
928 u8 bits;
929 u32 speed;
930 u32 cr0;
931 u32 cr1;
932 int err;
933 int dma_mapped;
934
935 /* Check if we can DMA this transfer */
936 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
937
938 /* reject already-mapped transfers; PIO won't always work */
939 if (message->is_dma_mapped
940 || transfer->rx_dma || transfer->tx_dma) {
941 dev_err(&spi->dev,
942 "Mapped transfer length of %u is greater than %d\n",
943 transfer->len, MAX_DMA_LEN);
944 return -EINVAL;
945 }
946
947 /* warn ... we force this to PIO mode */
948 dev_warn_ratelimited(&spi->dev,
949 "DMA disabled for transfer length %ld greater than %d\n",
950 (long)transfer->len, MAX_DMA_LEN);
951 }
952
953 /* Setup the transfer state based on the type of transfer */
954 if (pxa2xx_spi_flush(drv_data) == 0) {
955 dev_err(&spi->dev, "Flush failed\n");
956 return -EIO;
957 }
958 drv_data->n_bytes = chip->n_bytes;
959 drv_data->tx = (void *)transfer->tx_buf;
960 drv_data->tx_end = drv_data->tx + transfer->len;
961 drv_data->rx = transfer->rx_buf;
962 drv_data->rx_end = drv_data->rx + transfer->len;
963 drv_data->write = drv_data->tx ? chip->write : null_writer;
964 drv_data->read = drv_data->rx ? chip->read : null_reader;
965
966 /* Change speed and bit per word on a per transfer */
967 bits = transfer->bits_per_word;
968 speed = transfer->speed_hz;
969
970 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
971
972 if (bits <= 8) {
973 drv_data->n_bytes = 1;
974 drv_data->read = drv_data->read != null_reader ?
975 u8_reader : null_reader;
976 drv_data->write = drv_data->write != null_writer ?
977 u8_writer : null_writer;
978 } else if (bits <= 16) {
979 drv_data->n_bytes = 2;
980 drv_data->read = drv_data->read != null_reader ?
981 u16_reader : null_reader;
982 drv_data->write = drv_data->write != null_writer ?
983 u16_writer : null_writer;
984 } else if (bits <= 32) {
985 drv_data->n_bytes = 4;
986 drv_data->read = drv_data->read != null_reader ?
987 u32_reader : null_reader;
988 drv_data->write = drv_data->write != null_writer ?
989 u32_writer : null_writer;
990 }
991 /*
992 * if bits/word is changed in dma mode, then must check the
993 * thresholds and burst also
994 */
995 if (chip->enable_dma) {
996 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
997 spi,
998 bits, &dma_burst,
999 &dma_thresh))
1000 dev_warn_ratelimited(&spi->dev,
1001 "DMA burst size reduced to match bits_per_word\n");
1002 }
1003
1004 dma_mapped = controller->can_dma &&
1005 controller->can_dma(controller, spi, transfer) &&
1006 controller->cur_msg_mapped;
1007 if (dma_mapped) {
1008
1009 /* Ensure we have the correct interrupt handler */
1010 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1011
1012 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1013 if (err)
1014 return err;
1015
1016 /* Clear status and start DMA engine */
1017 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1018 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1019
1020 pxa2xx_spi_dma_start(drv_data);
1021 } else {
1022 /* Ensure we have the correct interrupt handler */
1023 drv_data->transfer_handler = interrupt_transfer;
1024
1025 /* Clear status */
1026 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1027 write_SSSR_CS(drv_data, drv_data->clear_sr);
1028 }
1029
1030 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1031 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1032 if (!pxa25x_ssp_comp(drv_data))
1033 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1034 controller->max_speed_hz
1035 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1036 dma_mapped ? "DMA" : "PIO");
1037 else
1038 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1039 controller->max_speed_hz / 2
1040 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1041 dma_mapped ? "DMA" : "PIO");
1042
1043 if (is_lpss_ssp(drv_data)) {
1044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1045 != chip->lpss_rx_threshold)
1046 pxa2xx_spi_write(drv_data, SSIRF,
1047 chip->lpss_rx_threshold);
1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1049 != chip->lpss_tx_threshold)
1050 pxa2xx_spi_write(drv_data, SSITF,
1051 chip->lpss_tx_threshold);
1052 }
1053
1054 if (is_quark_x1000_ssp(drv_data) &&
1055 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1056 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1057
1058 /* see if we need to reload the config registers */
1059 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1060 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1061 != (cr1 & change_mask)) {
1062 /* stop the SSP, and update the other bits */
1063 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1064 if (!pxa25x_ssp_comp(drv_data))
1065 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1066 /* first set CR1 without interrupt and service enables */
1067 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1068 /* restart the SSP */
1069 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1070
1071 } else {
1072 if (!pxa25x_ssp_comp(drv_data))
1073 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1074 }
1075
1076 if (drv_data->ssp_type == MMP2_SSP) {
1077 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1078 & SSSR_TFL_MASK) >> 8;
1079
1080 if (tx_level) {
1081 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1082 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1083 tx_level);
1084 if (tx_level > transfer->len)
1085 tx_level = transfer->len;
1086 drv_data->tx += tx_level;
1087 }
1088 }
1089
1090 if (spi_controller_is_slave(controller)) {
1091 while (drv_data->write(drv_data))
1092 ;
1093 if (drv_data->gpiod_ready) {
1094 gpiod_set_value(drv_data->gpiod_ready, 1);
1095 udelay(1);
1096 gpiod_set_value(drv_data->gpiod_ready, 0);
1097 }
1098 }
1099
1100 /*
1101 * Release the data by enabling service requests and interrupts,
1102 * without changing any mode bits
1103 */
1104 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1105
1106 return 1;
1107}
1108
1109static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1110{
1111 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1112
1113 /* Stop and reset SSP */
1114 write_SSSR_CS(drv_data, drv_data->clear_sr);
1115 reset_sccr1(drv_data);
1116 if (!pxa25x_ssp_comp(drv_data))
1117 pxa2xx_spi_write(drv_data, SSTO, 0);
1118 pxa2xx_spi_flush(drv_data);
1119 pxa2xx_spi_write(drv_data, SSCR0,
1120 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1121
1122 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1123
1124 drv_data->controller->cur_msg->status = -EINTR;
1125 spi_finalize_current_transfer(drv_data->controller);
1126
1127 return 0;
1128}
1129
1130static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1131 struct spi_message *msg)
1132{
1133 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1134
1135 /* Disable the SSP */
1136 pxa2xx_spi_write(drv_data, SSCR0,
1137 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1138 /* Clear and disable interrupts and service requests */
1139 write_SSSR_CS(drv_data, drv_data->clear_sr);
1140 pxa2xx_spi_write(drv_data, SSCR1,
1141 pxa2xx_spi_read(drv_data, SSCR1)
1142 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1143 if (!pxa25x_ssp_comp(drv_data))
1144 pxa2xx_spi_write(drv_data, SSTO, 0);
1145
1146 /*
1147 * Stop the DMA if running. Note DMA callback handler may have unset
1148 * the dma_running already, which is fine as stopping is not needed
1149 * then but we shouldn't rely this flag for anything else than
1150 * stopping. For instance to differentiate between PIO and DMA
1151 * transfers.
1152 */
1153 if (atomic_read(&drv_data->dma_running))
1154 pxa2xx_spi_dma_stop(drv_data);
1155}
1156
1157static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1158{
1159 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1160
1161 /* Disable the SSP now */
1162 pxa2xx_spi_write(drv_data, SSCR0,
1163 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1164
1165 return 0;
1166}
1167
1168static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1169 struct pxa2xx_spi_chip *chip_info)
1170{
1171 struct driver_data *drv_data =
1172 spi_controller_get_devdata(spi->controller);
1173 struct gpio_desc *gpiod;
1174 int err = 0;
1175
1176 if (chip == NULL)
1177 return 0;
1178
1179 if (drv_data->cs_gpiods) {
1180 gpiod = drv_data->cs_gpiods[spi->chip_select];
1181 if (gpiod) {
1182 chip->gpiod_cs = gpiod;
1183 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1184 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1185 }
1186
1187 return 0;
1188 }
1189
1190 if (chip_info == NULL)
1191 return 0;
1192
1193 /* NOTE: setup() can be called multiple times, possibly with
1194 * different chip_info, release previously requested GPIO
1195 */
1196 if (chip->gpiod_cs) {
1197 gpiod_put(chip->gpiod_cs);
1198 chip->gpiod_cs = NULL;
1199 }
1200
1201 /* If (*cs_control) is provided, ignore GPIO chip select */
1202 if (chip_info->cs_control) {
1203 chip->cs_control = chip_info->cs_control;
1204 return 0;
1205 }
1206
1207 if (gpio_is_valid(chip_info->gpio_cs)) {
1208 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1209 if (err) {
1210 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1211 chip_info->gpio_cs);
1212 return err;
1213 }
1214
1215 gpiod = gpio_to_desc(chip_info->gpio_cs);
1216 chip->gpiod_cs = gpiod;
1217 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1218
1219 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1220 }
1221
1222 return err;
1223}
1224
1225static int setup(struct spi_device *spi)
1226{
1227 struct pxa2xx_spi_chip *chip_info;
1228 struct chip_data *chip;
1229 const struct lpss_config *config;
1230 struct driver_data *drv_data =
1231 spi_controller_get_devdata(spi->controller);
1232 uint tx_thres, tx_hi_thres, rx_thres;
1233
1234 switch (drv_data->ssp_type) {
1235 case QUARK_X1000_SSP:
1236 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1237 tx_hi_thres = 0;
1238 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1239 break;
1240 case CE4100_SSP:
1241 tx_thres = TX_THRESH_CE4100_DFLT;
1242 tx_hi_thres = 0;
1243 rx_thres = RX_THRESH_CE4100_DFLT;
1244 break;
1245 case LPSS_LPT_SSP:
1246 case LPSS_BYT_SSP:
1247 case LPSS_BSW_SSP:
1248 case LPSS_SPT_SSP:
1249 case LPSS_BXT_SSP:
1250 case LPSS_CNL_SSP:
1251 config = lpss_get_config(drv_data);
1252 tx_thres = config->tx_threshold_lo;
1253 tx_hi_thres = config->tx_threshold_hi;
1254 rx_thres = config->rx_threshold;
1255 break;
1256 default:
1257 tx_hi_thres = 0;
1258 if (spi_controller_is_slave(drv_data->controller)) {
1259 tx_thres = 1;
1260 rx_thres = 2;
1261 } else {
1262 tx_thres = TX_THRESH_DFLT;
1263 rx_thres = RX_THRESH_DFLT;
1264 }
1265 break;
1266 }
1267
1268 /* Only alloc on first setup */
1269 chip = spi_get_ctldata(spi);
1270 if (!chip) {
1271 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1272 if (!chip)
1273 return -ENOMEM;
1274
1275 if (drv_data->ssp_type == CE4100_SSP) {
1276 if (spi->chip_select > 4) {
1277 dev_err(&spi->dev,
1278 "failed setup: cs number must not be > 4.\n");
1279 kfree(chip);
1280 return -EINVAL;
1281 }
1282
1283 chip->frm = spi->chip_select;
1284 }
1285 chip->enable_dma = drv_data->controller_info->enable_dma;
1286 chip->timeout = TIMOUT_DFLT;
1287 }
1288
1289 /* protocol drivers may change the chip settings, so...
1290 * if chip_info exists, use it */
1291 chip_info = spi->controller_data;
1292
1293 /* chip_info isn't always needed */
1294 chip->cr1 = 0;
1295 if (chip_info) {
1296 if (chip_info->timeout)
1297 chip->timeout = chip_info->timeout;
1298 if (chip_info->tx_threshold)
1299 tx_thres = chip_info->tx_threshold;
1300 if (chip_info->tx_hi_threshold)
1301 tx_hi_thres = chip_info->tx_hi_threshold;
1302 if (chip_info->rx_threshold)
1303 rx_thres = chip_info->rx_threshold;
1304 chip->dma_threshold = 0;
1305 if (chip_info->enable_loopback)
1306 chip->cr1 = SSCR1_LBM;
1307 }
1308 if (spi_controller_is_slave(drv_data->controller)) {
1309 chip->cr1 |= SSCR1_SCFR;
1310 chip->cr1 |= SSCR1_SCLKDIR;
1311 chip->cr1 |= SSCR1_SFRMDIR;
1312 chip->cr1 |= SSCR1_SPH;
1313 }
1314
1315 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1316 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1317 | SSITF_TxHiThresh(tx_hi_thres);
1318
1319 /* set dma burst and threshold outside of chip_info path so that if
1320 * chip_info goes away after setting chip->enable_dma, the
1321 * burst and threshold can still respond to changes in bits_per_word */
1322 if (chip->enable_dma) {
1323 /* set up legal burst and threshold for dma */
1324 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1325 spi->bits_per_word,
1326 &chip->dma_burst_size,
1327 &chip->dma_threshold)) {
1328 dev_warn(&spi->dev,
1329 "in setup: DMA burst size reduced to match bits_per_word\n");
1330 }
1331 dev_dbg(&spi->dev,
1332 "in setup: DMA burst size set to %u\n",
1333 chip->dma_burst_size);
1334 }
1335
1336 switch (drv_data->ssp_type) {
1337 case QUARK_X1000_SSP:
1338 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1339 & QUARK_X1000_SSCR1_RFT)
1340 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1341 & QUARK_X1000_SSCR1_TFT);
1342 break;
1343 case CE4100_SSP:
1344 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1345 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1346 break;
1347 default:
1348 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1349 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1350 break;
1351 }
1352
1353 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1354 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1355 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1356
1357 if (spi->mode & SPI_LOOP)
1358 chip->cr1 |= SSCR1_LBM;
1359
1360 if (spi->bits_per_word <= 8) {
1361 chip->n_bytes = 1;
1362 chip->read = u8_reader;
1363 chip->write = u8_writer;
1364 } else if (spi->bits_per_word <= 16) {
1365 chip->n_bytes = 2;
1366 chip->read = u16_reader;
1367 chip->write = u16_writer;
1368 } else if (spi->bits_per_word <= 32) {
1369 chip->n_bytes = 4;
1370 chip->read = u32_reader;
1371 chip->write = u32_writer;
1372 }
1373
1374 spi_set_ctldata(spi, chip);
1375
1376 if (drv_data->ssp_type == CE4100_SSP)
1377 return 0;
1378
1379 return setup_cs(spi, chip, chip_info);
1380}
1381
1382static void cleanup(struct spi_device *spi)
1383{
1384 struct chip_data *chip = spi_get_ctldata(spi);
1385 struct driver_data *drv_data =
1386 spi_controller_get_devdata(spi->controller);
1387
1388 if (!chip)
1389 return;
1390
1391 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1392 chip->gpiod_cs)
1393 gpiod_put(chip->gpiod_cs);
1394
1395 kfree(chip);
1396}
1397
1398static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1399 { "INT33C0", LPSS_LPT_SSP },
1400 { "INT33C1", LPSS_LPT_SSP },
1401 { "INT3430", LPSS_LPT_SSP },
1402 { "INT3431", LPSS_LPT_SSP },
1403 { "80860F0E", LPSS_BYT_SSP },
1404 { "8086228E", LPSS_BSW_SSP },
1405 { },
1406};
1407MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1408
1409/*
1410 * PCI IDs of compound devices that integrate both host controller and private
1411 * integrated DMA engine. Please note these are not used in module
1412 * autoloading and probing in this module but matching the LPSS SSP type.
1413 */
1414static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1415 /* SPT-LP */
1416 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1417 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1418 /* SPT-H */
1419 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1420 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1421 /* KBL-H */
1422 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1423 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1424 /* BXT A-Step */
1425 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1426 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1427 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1428 /* BXT B-Step */
1429 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1430 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1431 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1432 /* GLK */
1433 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1434 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1435 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1436 /* ICL-LP */
1437 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1438 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1439 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1440 /* EHL */
1441 { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1442 { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1443 { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1444 /* APL */
1445 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1446 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1447 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1448 /* CNL-LP */
1449 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1450 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1451 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1452 /* CNL-H */
1453 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1454 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1455 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1456 /* CML-LP */
1457 { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1458 { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1459 { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1460 /* TGL-LP */
1461 { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1462 { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1463 { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1464 { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1465 { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1466 { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1467 { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1468 { },
1469};
1470
1471static const struct of_device_id pxa2xx_spi_of_match[] = {
1472 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1473 {},
1474};
1475MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1476
1477#ifdef CONFIG_ACPI
1478
1479static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1480{
1481 unsigned int devid;
1482 int port_id = -1;
1483
1484 if (adev && adev->pnp.unique_id &&
1485 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1486 port_id = devid;
1487 return port_id;
1488}
1489
1490#else /* !CONFIG_ACPI */
1491
1492static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1493{
1494 return -1;
1495}
1496
1497#endif /* CONFIG_ACPI */
1498
1499
1500#ifdef CONFIG_PCI
1501
1502static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1503{
1504 return param == chan->device->dev;
1505}
1506
1507#endif /* CONFIG_PCI */
1508
1509static struct pxa2xx_spi_controller *
1510pxa2xx_spi_init_pdata(struct platform_device *pdev)
1511{
1512 struct pxa2xx_spi_controller *pdata;
1513 struct acpi_device *adev;
1514 struct ssp_device *ssp;
1515 struct resource *res;
1516 const struct acpi_device_id *adev_id = NULL;
1517 const struct pci_device_id *pcidev_id = NULL;
1518 const struct of_device_id *of_id = NULL;
1519 enum pxa_ssp_type type;
1520
1521 adev = ACPI_COMPANION(&pdev->dev);
1522
1523 if (pdev->dev.of_node)
1524 of_id = of_match_device(pdev->dev.driver->of_match_table,
1525 &pdev->dev);
1526 else if (dev_is_pci(pdev->dev.parent))
1527 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1528 to_pci_dev(pdev->dev.parent));
1529 else if (adev)
1530 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1531 &pdev->dev);
1532 else
1533 return NULL;
1534
1535 if (adev_id)
1536 type = (enum pxa_ssp_type)adev_id->driver_data;
1537 else if (pcidev_id)
1538 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1539 else if (of_id)
1540 type = (enum pxa_ssp_type)of_id->data;
1541 else
1542 return NULL;
1543
1544 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1545 if (!pdata)
1546 return NULL;
1547
1548 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1549 if (!res)
1550 return NULL;
1551
1552 ssp = &pdata->ssp;
1553
1554 ssp->phys_base = res->start;
1555 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1556 if (IS_ERR(ssp->mmio_base))
1557 return NULL;
1558
1559#ifdef CONFIG_PCI
1560 if (pcidev_id) {
1561 pdata->tx_param = pdev->dev.parent;
1562 pdata->rx_param = pdev->dev.parent;
1563 pdata->dma_filter = pxa2xx_spi_idma_filter;
1564 }
1565#endif
1566
1567 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1568 ssp->irq = platform_get_irq(pdev, 0);
1569 ssp->type = type;
1570 ssp->pdev = pdev;
1571 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1572
1573 pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
1574 pdata->num_chipselect = 1;
1575 pdata->enable_dma = true;
1576 pdata->dma_burst_size = 1;
1577
1578 return pdata;
1579}
1580
1581static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1582 unsigned int cs)
1583{
1584 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1585
1586 if (has_acpi_companion(&drv_data->pdev->dev)) {
1587 switch (drv_data->ssp_type) {
1588 /*
1589 * For Atoms the ACPI DeviceSelection used by the Windows
1590 * driver starts from 1 instead of 0 so translate it here
1591 * to match what Linux expects.
1592 */
1593 case LPSS_BYT_SSP:
1594 case LPSS_BSW_SSP:
1595 return cs - 1;
1596
1597 default:
1598 break;
1599 }
1600 }
1601
1602 return cs;
1603}
1604
1605static int pxa2xx_spi_probe(struct platform_device *pdev)
1606{
1607 struct device *dev = &pdev->dev;
1608 struct pxa2xx_spi_controller *platform_info;
1609 struct spi_controller *controller;
1610 struct driver_data *drv_data;
1611 struct ssp_device *ssp;
1612 const struct lpss_config *config;
1613 int status, count;
1614 u32 tmp;
1615
1616 platform_info = dev_get_platdata(dev);
1617 if (!platform_info) {
1618 platform_info = pxa2xx_spi_init_pdata(pdev);
1619 if (!platform_info) {
1620 dev_err(&pdev->dev, "missing platform data\n");
1621 return -ENODEV;
1622 }
1623 }
1624
1625 ssp = pxa_ssp_request(pdev->id, pdev->name);
1626 if (!ssp)
1627 ssp = &platform_info->ssp;
1628
1629 if (!ssp->mmio_base) {
1630 dev_err(&pdev->dev, "failed to get ssp\n");
1631 return -ENODEV;
1632 }
1633
1634 if (platform_info->is_slave)
1635 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1636 else
1637 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1638
1639 if (!controller) {
1640 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1641 pxa_ssp_free(ssp);
1642 return -ENOMEM;
1643 }
1644 drv_data = spi_controller_get_devdata(controller);
1645 drv_data->controller = controller;
1646 drv_data->controller_info = platform_info;
1647 drv_data->pdev = pdev;
1648 drv_data->ssp = ssp;
1649
1650 controller->dev.of_node = pdev->dev.of_node;
1651 /* the spi->mode bits understood by this driver: */
1652 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1653
1654 controller->bus_num = ssp->port_id;
1655 controller->dma_alignment = DMA_ALIGNMENT;
1656 controller->cleanup = cleanup;
1657 controller->setup = setup;
1658 controller->set_cs = pxa2xx_spi_set_cs;
1659 controller->transfer_one = pxa2xx_spi_transfer_one;
1660 controller->slave_abort = pxa2xx_spi_slave_abort;
1661 controller->handle_err = pxa2xx_spi_handle_err;
1662 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1663 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1664 controller->auto_runtime_pm = true;
1665 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1666
1667 drv_data->ssp_type = ssp->type;
1668
1669 drv_data->ioaddr = ssp->mmio_base;
1670 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1671 if (pxa25x_ssp_comp(drv_data)) {
1672 switch (drv_data->ssp_type) {
1673 case QUARK_X1000_SSP:
1674 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1675 break;
1676 default:
1677 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1678 break;
1679 }
1680
1681 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1682 drv_data->dma_cr1 = 0;
1683 drv_data->clear_sr = SSSR_ROR;
1684 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1685 } else {
1686 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1687 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1688 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1689 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1690 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1691 | SSSR_ROR | SSSR_TUR;
1692 }
1693
1694 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1695 drv_data);
1696 if (status < 0) {
1697 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1698 goto out_error_controller_alloc;
1699 }
1700
1701 /* Setup DMA if requested */
1702 if (platform_info->enable_dma) {
1703 status = pxa2xx_spi_dma_setup(drv_data);
1704 if (status) {
1705 dev_warn(dev, "no DMA channels available, using PIO\n");
1706 platform_info->enable_dma = false;
1707 } else {
1708 controller->can_dma = pxa2xx_spi_can_dma;
1709 controller->max_dma_len = MAX_DMA_LEN;
1710 }
1711 }
1712
1713 /* Enable SOC clock */
1714 status = clk_prepare_enable(ssp->clk);
1715 if (status)
1716 goto out_error_dma_irq_alloc;
1717
1718 controller->max_speed_hz = clk_get_rate(ssp->clk);
1719 /*
1720 * Set minimum speed for all other platforms than Intel Quark which is
1721 * able do under 1 Hz transfers.
1722 */
1723 if (!pxa25x_ssp_comp(drv_data))
1724 controller->min_speed_hz =
1725 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1726 else if (!is_quark_x1000_ssp(drv_data))
1727 controller->min_speed_hz =
1728 DIV_ROUND_UP(controller->max_speed_hz, 512);
1729
1730 /* Load default SSP configuration */
1731 pxa2xx_spi_write(drv_data, SSCR0, 0);
1732 switch (drv_data->ssp_type) {
1733 case QUARK_X1000_SSP:
1734 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1735 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1736 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1737
1738 /* using the Motorola SPI protocol and use 8 bit frame */
1739 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1740 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1741 break;
1742 case CE4100_SSP:
1743 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1744 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1745 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1746 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1747 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1748 break;
1749 default:
1750
1751 if (spi_controller_is_slave(controller)) {
1752 tmp = SSCR1_SCFR |
1753 SSCR1_SCLKDIR |
1754 SSCR1_SFRMDIR |
1755 SSCR1_RxTresh(2) |
1756 SSCR1_TxTresh(1) |
1757 SSCR1_SPH;
1758 } else {
1759 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1760 SSCR1_TxTresh(TX_THRESH_DFLT);
1761 }
1762 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1763 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1764 if (!spi_controller_is_slave(controller))
1765 tmp |= SSCR0_SCR(2);
1766 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1767 break;
1768 }
1769
1770 if (!pxa25x_ssp_comp(drv_data))
1771 pxa2xx_spi_write(drv_data, SSTO, 0);
1772
1773 if (!is_quark_x1000_ssp(drv_data))
1774 pxa2xx_spi_write(drv_data, SSPSP, 0);
1775
1776 if (is_lpss_ssp(drv_data)) {
1777 lpss_ssp_setup(drv_data);
1778 config = lpss_get_config(drv_data);
1779 if (config->reg_capabilities >= 0) {
1780 tmp = __lpss_ssp_read_priv(drv_data,
1781 config->reg_capabilities);
1782 tmp &= LPSS_CAPS_CS_EN_MASK;
1783 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1784 platform_info->num_chipselect = ffz(tmp);
1785 } else if (config->cs_num) {
1786 platform_info->num_chipselect = config->cs_num;
1787 }
1788 }
1789 controller->num_chipselect = platform_info->num_chipselect;
1790
1791 count = gpiod_count(&pdev->dev, "cs");
1792 if (count > 0) {
1793 int i;
1794
1795 controller->num_chipselect = max_t(int, count,
1796 controller->num_chipselect);
1797
1798 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1799 controller->num_chipselect, sizeof(struct gpio_desc *),
1800 GFP_KERNEL);
1801 if (!drv_data->cs_gpiods) {
1802 status = -ENOMEM;
1803 goto out_error_clock_enabled;
1804 }
1805
1806 for (i = 0; i < controller->num_chipselect; i++) {
1807 struct gpio_desc *gpiod;
1808
1809 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1810 if (IS_ERR(gpiod)) {
1811 /* Means use native chip select */
1812 if (PTR_ERR(gpiod) == -ENOENT)
1813 continue;
1814
1815 status = PTR_ERR(gpiod);
1816 goto out_error_clock_enabled;
1817 } else {
1818 drv_data->cs_gpiods[i] = gpiod;
1819 }
1820 }
1821 }
1822
1823 if (platform_info->is_slave) {
1824 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1825 "ready", GPIOD_OUT_LOW);
1826 if (IS_ERR(drv_data->gpiod_ready)) {
1827 status = PTR_ERR(drv_data->gpiod_ready);
1828 goto out_error_clock_enabled;
1829 }
1830 }
1831
1832 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1833 pm_runtime_use_autosuspend(&pdev->dev);
1834 pm_runtime_set_active(&pdev->dev);
1835 pm_runtime_enable(&pdev->dev);
1836
1837 /* Register with the SPI framework */
1838 platform_set_drvdata(pdev, drv_data);
1839 status = devm_spi_register_controller(&pdev->dev, controller);
1840 if (status != 0) {
1841 dev_err(&pdev->dev, "problem registering spi controller\n");
1842 goto out_error_pm_runtime_enabled;
1843 }
1844
1845 return status;
1846
1847out_error_pm_runtime_enabled:
1848 pm_runtime_put_noidle(&pdev->dev);
1849 pm_runtime_disable(&pdev->dev);
1850
1851out_error_clock_enabled:
1852 clk_disable_unprepare(ssp->clk);
1853
1854out_error_dma_irq_alloc:
1855 pxa2xx_spi_dma_release(drv_data);
1856 free_irq(ssp->irq, drv_data);
1857
1858out_error_controller_alloc:
1859 spi_controller_put(controller);
1860 pxa_ssp_free(ssp);
1861 return status;
1862}
1863
1864static int pxa2xx_spi_remove(struct platform_device *pdev)
1865{
1866 struct driver_data *drv_data = platform_get_drvdata(pdev);
1867 struct ssp_device *ssp;
1868
1869 if (!drv_data)
1870 return 0;
1871 ssp = drv_data->ssp;
1872
1873 pm_runtime_get_sync(&pdev->dev);
1874
1875 /* Disable the SSP at the peripheral and SOC level */
1876 pxa2xx_spi_write(drv_data, SSCR0, 0);
1877 clk_disable_unprepare(ssp->clk);
1878
1879 /* Release DMA */
1880 if (drv_data->controller_info->enable_dma)
1881 pxa2xx_spi_dma_release(drv_data);
1882
1883 pm_runtime_put_noidle(&pdev->dev);
1884 pm_runtime_disable(&pdev->dev);
1885
1886 /* Release IRQ */
1887 free_irq(ssp->irq, drv_data);
1888
1889 /* Release SSP */
1890 pxa_ssp_free(ssp);
1891
1892 return 0;
1893}
1894
1895#ifdef CONFIG_PM_SLEEP
1896static int pxa2xx_spi_suspend(struct device *dev)
1897{
1898 struct driver_data *drv_data = dev_get_drvdata(dev);
1899 struct ssp_device *ssp = drv_data->ssp;
1900 int status;
1901
1902 status = spi_controller_suspend(drv_data->controller);
1903 if (status != 0)
1904 return status;
1905 pxa2xx_spi_write(drv_data, SSCR0, 0);
1906
1907 if (!pm_runtime_suspended(dev))
1908 clk_disable_unprepare(ssp->clk);
1909
1910 return 0;
1911}
1912
1913static int pxa2xx_spi_resume(struct device *dev)
1914{
1915 struct driver_data *drv_data = dev_get_drvdata(dev);
1916 struct ssp_device *ssp = drv_data->ssp;
1917 int status;
1918
1919 /* Enable the SSP clock */
1920 if (!pm_runtime_suspended(dev)) {
1921 status = clk_prepare_enable(ssp->clk);
1922 if (status)
1923 return status;
1924 }
1925
1926 /* Start the queue running */
1927 return spi_controller_resume(drv_data->controller);
1928}
1929#endif
1930
1931#ifdef CONFIG_PM
1932static int pxa2xx_spi_runtime_suspend(struct device *dev)
1933{
1934 struct driver_data *drv_data = dev_get_drvdata(dev);
1935
1936 clk_disable_unprepare(drv_data->ssp->clk);
1937 return 0;
1938}
1939
1940static int pxa2xx_spi_runtime_resume(struct device *dev)
1941{
1942 struct driver_data *drv_data = dev_get_drvdata(dev);
1943 int status;
1944
1945 status = clk_prepare_enable(drv_data->ssp->clk);
1946 return status;
1947}
1948#endif
1949
1950static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1951 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1952 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1953 pxa2xx_spi_runtime_resume, NULL)
1954};
1955
1956static struct platform_driver driver = {
1957 .driver = {
1958 .name = "pxa2xx-spi",
1959 .pm = &pxa2xx_spi_pm_ops,
1960 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1961 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1962 },
1963 .probe = pxa2xx_spi_probe,
1964 .remove = pxa2xx_spi_remove,
1965};
1966
1967static int __init pxa2xx_spi_init(void)
1968{
1969 return platform_driver_register(&driver);
1970}
1971subsys_initcall(pxa2xx_spi_init);
1972
1973static void __exit pxa2xx_spi_exit(void)
1974{
1975 platform_driver_unregister(&driver);
1976}
1977module_exit(pxa2xx_spi_exit);
1978
1979MODULE_SOFTDEP("pre: dw_dmac");