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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#include <linux/acpi.h>
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/dmaengine.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/gpio/consumer.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/mod_devicetable.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/property.h>
26#include <linux/slab.h>
27
28#include <linux/spi/pxa2xx_spi.h>
29#include <linux/spi/spi.h>
30
31#include "spi-pxa2xx.h"
32
33MODULE_AUTHOR("Stephen Street");
34MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
35MODULE_LICENSE("GPL");
36MODULE_ALIAS("platform:pxa2xx-spi");
37
38#define TIMOUT_DFLT 1000
39
40/*
41 * For testing SSCR1 changes that require SSP restart, basically
42 * everything except the service and interrupt enables, the PXA270 developer
43 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
44 * list, but the PXA255 developer manual says all bits without really meaning
45 * the service and interrupt enables.
46 */
47#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
48 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
49 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
50 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
51 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
53
54#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
55 | QUARK_X1000_SSCR1_EFWR \
56 | QUARK_X1000_SSCR1_RFT \
57 | QUARK_X1000_SSCR1_TFT \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59
60#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
68#define LPSS_CS_CONTROL_SW_MODE BIT(0)
69#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72
73#define LPSS_PRIV_CLOCK_GATE 0x38
74#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
75#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
76
77struct lpss_config {
78 /* LPSS offset from drv_data->ioaddr */
79 unsigned offset;
80 /* Register offsets from drv_data->lpss_base or -1 */
81 int reg_general;
82 int reg_ssp;
83 int reg_cs_ctrl;
84 int reg_capabilities;
85 /* FIFO thresholds */
86 u32 rx_threshold;
87 u32 tx_threshold_lo;
88 u32 tx_threshold_hi;
89 /* Chip select control */
90 unsigned cs_sel_shift;
91 unsigned cs_sel_mask;
92 unsigned cs_num;
93 /* Quirks */
94 unsigned cs_clk_stays_gated : 1;
95};
96
97/* Keep these sorted with enum pxa_ssp_type */
98static const struct lpss_config lpss_platforms[] = {
99 { /* LPSS_LPT_SSP */
100 .offset = 0x800,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
109 { /* LPSS_BYT_SSP */
110 .offset = 0x400,
111 .reg_general = 0x08,
112 .reg_ssp = 0x0c,
113 .reg_cs_ctrl = 0x18,
114 .reg_capabilities = -1,
115 .rx_threshold = 64,
116 .tx_threshold_lo = 160,
117 .tx_threshold_hi = 224,
118 },
119 { /* LPSS_BSW_SSP */
120 .offset = 0x400,
121 .reg_general = 0x08,
122 .reg_ssp = 0x0c,
123 .reg_cs_ctrl = 0x18,
124 .reg_capabilities = -1,
125 .rx_threshold = 64,
126 .tx_threshold_lo = 160,
127 .tx_threshold_hi = 224,
128 .cs_sel_shift = 2,
129 .cs_sel_mask = 1 << 2,
130 .cs_num = 2,
131 },
132 { /* LPSS_SPT_SSP */
133 .offset = 0x200,
134 .reg_general = -1,
135 .reg_ssp = 0x20,
136 .reg_cs_ctrl = 0x24,
137 .reg_capabilities = -1,
138 .rx_threshold = 1,
139 .tx_threshold_lo = 32,
140 .tx_threshold_hi = 56,
141 },
142 { /* LPSS_BXT_SSP */
143 .offset = 0x200,
144 .reg_general = -1,
145 .reg_ssp = 0x20,
146 .reg_cs_ctrl = 0x24,
147 .reg_capabilities = 0xfc,
148 .rx_threshold = 1,
149 .tx_threshold_lo = 16,
150 .tx_threshold_hi = 48,
151 .cs_sel_shift = 8,
152 .cs_sel_mask = 3 << 8,
153 .cs_clk_stays_gated = true,
154 },
155 { /* LPSS_CNL_SSP */
156 .offset = 0x200,
157 .reg_general = -1,
158 .reg_ssp = 0x20,
159 .reg_cs_ctrl = 0x24,
160 .reg_capabilities = 0xfc,
161 .rx_threshold = 1,
162 .tx_threshold_lo = 32,
163 .tx_threshold_hi = 56,
164 .cs_sel_shift = 8,
165 .cs_sel_mask = 3 << 8,
166 .cs_clk_stays_gated = true,
167 },
168};
169
170static inline const struct lpss_config
171*lpss_get_config(const struct driver_data *drv_data)
172{
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
174}
175
176static bool is_lpss_ssp(const struct driver_data *drv_data)
177{
178 switch (drv_data->ssp_type) {
179 case LPSS_LPT_SSP:
180 case LPSS_BYT_SSP:
181 case LPSS_BSW_SSP:
182 case LPSS_SPT_SSP:
183 case LPSS_BXT_SSP:
184 case LPSS_CNL_SSP:
185 return true;
186 default:
187 return false;
188 }
189}
190
191static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
192{
193 return drv_data->ssp_type == QUARK_X1000_SSP;
194}
195
196static bool is_mmp2_ssp(const struct driver_data *drv_data)
197{
198 return drv_data->ssp_type == MMP2_SSP;
199}
200
201static bool is_mrfld_ssp(const struct driver_data *drv_data)
202{
203 return drv_data->ssp_type == MRFLD_SSP;
204}
205
206static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
207{
208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
209 pxa2xx_spi_write(drv_data, reg, value & mask);
210}
211
212static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
213{
214 switch (drv_data->ssp_type) {
215 case QUARK_X1000_SSP:
216 return QUARK_X1000_SSCR1_CHANGE_MASK;
217 case CE4100_SSP:
218 return CE4100_SSCR1_CHANGE_MASK;
219 default:
220 return SSCR1_CHANGE_MASK;
221 }
222}
223
224static u32
225pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
226{
227 switch (drv_data->ssp_type) {
228 case QUARK_X1000_SSP:
229 return RX_THRESH_QUARK_X1000_DFLT;
230 case CE4100_SSP:
231 return RX_THRESH_CE4100_DFLT;
232 default:
233 return RX_THRESH_DFLT;
234 }
235}
236
237static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
238{
239 u32 mask;
240
241 switch (drv_data->ssp_type) {
242 case QUARK_X1000_SSP:
243 mask = QUARK_X1000_SSSR_TFL_MASK;
244 break;
245 case CE4100_SSP:
246 mask = CE4100_SSSR_TFL_MASK;
247 break;
248 default:
249 mask = SSSR_TFL_MASK;
250 break;
251 }
252
253 return read_SSSR_bits(drv_data, mask) == mask;
254}
255
256static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
257 u32 *sccr1_reg)
258{
259 u32 mask;
260
261 switch (drv_data->ssp_type) {
262 case QUARK_X1000_SSP:
263 mask = QUARK_X1000_SSCR1_RFT;
264 break;
265 case CE4100_SSP:
266 mask = CE4100_SSCR1_RFT;
267 break;
268 default:
269 mask = SSCR1_RFT;
270 break;
271 }
272 *sccr1_reg &= ~mask;
273}
274
275static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
276 u32 *sccr1_reg, u32 threshold)
277{
278 switch (drv_data->ssp_type) {
279 case QUARK_X1000_SSP:
280 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
281 break;
282 case CE4100_SSP:
283 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
284 break;
285 default:
286 *sccr1_reg |= SSCR1_RxTresh(threshold);
287 break;
288 }
289}
290
291static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
292 u32 clk_div, u8 bits)
293{
294 switch (drv_data->ssp_type) {
295 case QUARK_X1000_SSP:
296 return clk_div
297 | QUARK_X1000_SSCR0_Motorola
298 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
299 default:
300 return clk_div
301 | SSCR0_Motorola
302 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
303 | (bits > 16 ? SSCR0_EDSS : 0);
304 }
305}
306
307/*
308 * Read and write LPSS SSP private registers. Caller must first check that
309 * is_lpss_ssp() returns true before these can be called.
310 */
311static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
312{
313 WARN_ON(!drv_data->lpss_base);
314 return readl(drv_data->lpss_base + offset);
315}
316
317static void __lpss_ssp_write_priv(struct driver_data *drv_data,
318 unsigned offset, u32 value)
319{
320 WARN_ON(!drv_data->lpss_base);
321 writel(value, drv_data->lpss_base + offset);
322}
323
324/*
325 * lpss_ssp_setup - perform LPSS SSP specific setup
326 * @drv_data: pointer to the driver private data
327 *
328 * Perform LPSS SSP specific setup. This function must be called first if
329 * one is going to use LPSS SSP private registers.
330 */
331static void lpss_ssp_setup(struct driver_data *drv_data)
332{
333 const struct lpss_config *config;
334 u32 value;
335
336 config = lpss_get_config(drv_data);
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
338
339 /* Enable software chip select control */
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
341 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
342 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
344
345 /* Enable multiblock DMA transfers */
346 if (drv_data->controller_info->enable_dma) {
347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
348
349 if (config->reg_general >= 0) {
350 value = __lpss_ssp_read_priv(drv_data,
351 config->reg_general);
352 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
353 __lpss_ssp_write_priv(drv_data,
354 config->reg_general, value);
355 }
356 }
357}
358
359static void lpss_ssp_select_cs(struct spi_device *spi,
360 const struct lpss_config *config)
361{
362 struct driver_data *drv_data =
363 spi_controller_get_devdata(spi->controller);
364 u32 value, cs;
365
366 if (!config->cs_sel_mask)
367 return;
368
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
370
371 cs = spi->chip_select;
372 cs <<= config->cs_sel_shift;
373 if (cs != (value & config->cs_sel_mask)) {
374 /*
375 * When switching another chip select output active the
376 * output must be selected first and wait 2 ssp_clk cycles
377 * before changing state to active. Otherwise a short
378 * glitch will occur on the previous chip select since
379 * output select is latched but state control is not.
380 */
381 value &= ~config->cs_sel_mask;
382 value |= cs;
383 __lpss_ssp_write_priv(drv_data,
384 config->reg_cs_ctrl, value);
385 ndelay(1000000000 /
386 (drv_data->controller->max_speed_hz / 2));
387 }
388}
389
390static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
391{
392 struct driver_data *drv_data =
393 spi_controller_get_devdata(spi->controller);
394 const struct lpss_config *config;
395 u32 value;
396
397 config = lpss_get_config(drv_data);
398
399 if (enable)
400 lpss_ssp_select_cs(spi, config);
401
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
403 if (enable)
404 value &= ~LPSS_CS_CONTROL_CS_HIGH;
405 else
406 value |= LPSS_CS_CONTROL_CS_HIGH;
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
408 if (config->cs_clk_stays_gated) {
409 u32 clkgate;
410
411 /*
412 * Changing CS alone when dynamic clock gating is on won't
413 * actually flip CS at that time. This ruins SPI transfers
414 * that specify delays, or have no data. Toggle the clock mode
415 * to force on briefly to poke the CS pin to move.
416 */
417 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
418 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
419 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
420
421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
423 }
424}
425
426static void cs_assert(struct spi_device *spi)
427{
428 struct driver_data *drv_data =
429 spi_controller_get_devdata(spi->controller);
430
431 if (drv_data->ssp_type == CE4100_SSP) {
432 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select);
433 return;
434 }
435
436 if (is_lpss_ssp(drv_data))
437 lpss_ssp_cs_control(spi, true);
438}
439
440static void cs_deassert(struct spi_device *spi)
441{
442 struct driver_data *drv_data =
443 spi_controller_get_devdata(spi->controller);
444 unsigned long timeout;
445
446 if (drv_data->ssp_type == CE4100_SSP)
447 return;
448
449 /* Wait until SSP becomes idle before deasserting the CS */
450 timeout = jiffies + msecs_to_jiffies(10);
451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
452 !time_after(jiffies, timeout))
453 cpu_relax();
454
455 if (is_lpss_ssp(drv_data))
456 lpss_ssp_cs_control(spi, false);
457}
458
459static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
460{
461 if (level)
462 cs_deassert(spi);
463 else
464 cs_assert(spi);
465}
466
467int pxa2xx_spi_flush(struct driver_data *drv_data)
468{
469 unsigned long limit = loops_per_jiffy << 1;
470
471 do {
472 while (read_SSSR_bits(drv_data, SSSR_RNE))
473 pxa2xx_spi_read(drv_data, SSDR);
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
475 write_SSSR_CS(drv_data, SSSR_ROR);
476
477 return limit;
478}
479
480static void pxa2xx_spi_off(struct driver_data *drv_data)
481{
482 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
483 if (is_mmp2_ssp(drv_data))
484 return;
485
486 pxa_ssp_disable(drv_data->ssp);
487}
488
489static int null_writer(struct driver_data *drv_data)
490{
491 u8 n_bytes = drv_data->n_bytes;
492
493 if (pxa2xx_spi_txfifo_full(drv_data)
494 || (drv_data->tx == drv_data->tx_end))
495 return 0;
496
497 pxa2xx_spi_write(drv_data, SSDR, 0);
498 drv_data->tx += n_bytes;
499
500 return 1;
501}
502
503static int null_reader(struct driver_data *drv_data)
504{
505 u8 n_bytes = drv_data->n_bytes;
506
507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
508 pxa2xx_spi_read(drv_data, SSDR);
509 drv_data->rx += n_bytes;
510 }
511
512 return drv_data->rx == drv_data->rx_end;
513}
514
515static int u8_writer(struct driver_data *drv_data)
516{
517 if (pxa2xx_spi_txfifo_full(drv_data)
518 || (drv_data->tx == drv_data->tx_end))
519 return 0;
520
521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
522 ++drv_data->tx;
523
524 return 1;
525}
526
527static int u8_reader(struct driver_data *drv_data)
528{
529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
531 ++drv_data->rx;
532 }
533
534 return drv_data->rx == drv_data->rx_end;
535}
536
537static int u16_writer(struct driver_data *drv_data)
538{
539 if (pxa2xx_spi_txfifo_full(drv_data)
540 || (drv_data->tx == drv_data->tx_end))
541 return 0;
542
543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
544 drv_data->tx += 2;
545
546 return 1;
547}
548
549static int u16_reader(struct driver_data *drv_data)
550{
551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
553 drv_data->rx += 2;
554 }
555
556 return drv_data->rx == drv_data->rx_end;
557}
558
559static int u32_writer(struct driver_data *drv_data)
560{
561 if (pxa2xx_spi_txfifo_full(drv_data)
562 || (drv_data->tx == drv_data->tx_end))
563 return 0;
564
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
566 drv_data->tx += 4;
567
568 return 1;
569}
570
571static int u32_reader(struct driver_data *drv_data)
572{
573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
575 drv_data->rx += 4;
576 }
577
578 return drv_data->rx == drv_data->rx_end;
579}
580
581static void reset_sccr1(struct driver_data *drv_data)
582{
583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
584 struct chip_data *chip;
585
586 if (drv_data->controller->cur_msg) {
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
588 threshold = chip->threshold;
589 } else {
590 threshold = 0;
591 }
592
593 switch (drv_data->ssp_type) {
594 case QUARK_X1000_SSP:
595 mask |= QUARK_X1000_SSCR1_RFT;
596 break;
597 case CE4100_SSP:
598 mask |= CE4100_SSCR1_RFT;
599 break;
600 default:
601 mask |= SSCR1_RFT;
602 break;
603 }
604
605 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
606}
607
608static void int_stop_and_reset(struct driver_data *drv_data)
609{
610 /* Clear and disable interrupts */
611 write_SSSR_CS(drv_data, drv_data->clear_sr);
612 reset_sccr1(drv_data);
613 if (pxa25x_ssp_comp(drv_data))
614 return;
615
616 pxa2xx_spi_write(drv_data, SSTO, 0);
617}
618
619static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
620{
621 int_stop_and_reset(drv_data);
622 pxa2xx_spi_flush(drv_data);
623 pxa2xx_spi_off(drv_data);
624
625 dev_err(drv_data->ssp->dev, "%s\n", msg);
626
627 drv_data->controller->cur_msg->status = err;
628 spi_finalize_current_transfer(drv_data->controller);
629}
630
631static void int_transfer_complete(struct driver_data *drv_data)
632{
633 int_stop_and_reset(drv_data);
634
635 spi_finalize_current_transfer(drv_data->controller);
636}
637
638static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
639{
640 u32 irq_status;
641
642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
643 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
644 irq_status &= ~SSSR_TFS;
645
646 if (irq_status & SSSR_ROR) {
647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
648 return IRQ_HANDLED;
649 }
650
651 if (irq_status & SSSR_TUR) {
652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
653 return IRQ_HANDLED;
654 }
655
656 if (irq_status & SSSR_TINT) {
657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
658 if (drv_data->read(drv_data)) {
659 int_transfer_complete(drv_data);
660 return IRQ_HANDLED;
661 }
662 }
663
664 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
665 do {
666 if (drv_data->read(drv_data)) {
667 int_transfer_complete(drv_data);
668 return IRQ_HANDLED;
669 }
670 } while (drv_data->write(drv_data));
671
672 if (drv_data->read(drv_data)) {
673 int_transfer_complete(drv_data);
674 return IRQ_HANDLED;
675 }
676
677 if (drv_data->tx == drv_data->tx_end) {
678 u32 bytes_left;
679 u32 sccr1_reg;
680
681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
682 sccr1_reg &= ~SSCR1_TIE;
683
684 /*
685 * PXA25x_SSP has no timeout, set up Rx threshold for
686 * the remaining Rx bytes.
687 */
688 if (pxa25x_ssp_comp(drv_data)) {
689 u32 rx_thre;
690
691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
692
693 bytes_left = drv_data->rx_end - drv_data->rx;
694 switch (drv_data->n_bytes) {
695 case 4:
696 bytes_left >>= 2;
697 break;
698 case 2:
699 bytes_left >>= 1;
700 break;
701 }
702
703 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
704 if (rx_thre > bytes_left)
705 rx_thre = bytes_left;
706
707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
708 }
709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
710 }
711
712 /* We did something */
713 return IRQ_HANDLED;
714}
715
716static void handle_bad_msg(struct driver_data *drv_data)
717{
718 int_stop_and_reset(drv_data);
719 pxa2xx_spi_off(drv_data);
720
721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
722}
723
724static irqreturn_t ssp_int(int irq, void *dev_id)
725{
726 struct driver_data *drv_data = dev_id;
727 u32 sccr1_reg;
728 u32 mask = drv_data->mask_sr;
729 u32 status;
730
731 /*
732 * The IRQ might be shared with other peripherals so we must first
733 * check that are we RPM suspended or not. If we are we assume that
734 * the IRQ was not for us (we shouldn't be RPM suspended when the
735 * interrupt is enabled).
736 */
737 if (pm_runtime_suspended(drv_data->ssp->dev))
738 return IRQ_NONE;
739
740 /*
741 * If the device is not yet in RPM suspended state and we get an
742 * interrupt that is meant for another device, check if status bits
743 * are all set to one. That means that the device is already
744 * powered off.
745 */
746 status = pxa2xx_spi_read(drv_data, SSSR);
747 if (status == ~0)
748 return IRQ_NONE;
749
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
751
752 /* Ignore possible writes if we don't need to write */
753 if (!(sccr1_reg & SSCR1_TIE))
754 mask &= ~SSSR_TFS;
755
756 /* Ignore RX timeout interrupt if it is disabled */
757 if (!(sccr1_reg & SSCR1_TINTE))
758 mask &= ~SSSR_TINT;
759
760 if (!(status & mask))
761 return IRQ_NONE;
762
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
765
766 if (!drv_data->controller->cur_msg) {
767 handle_bad_msg(drv_data);
768 /* Never fail */
769 return IRQ_HANDLED;
770 }
771
772 return drv_data->transfer_handler(drv_data);
773}
774
775/*
776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
777 * input frequency by fractions of 2^24. It also has a divider by 5.
778 *
779 * There are formulas to get baud rate value for given input frequency and
780 * divider parameters, such as DDS_CLK_RATE and SCR:
781 *
782 * Fsys = 200MHz
783 *
784 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
786 *
787 * DDS_CLK_RATE either 2^n or 2^n / 5.
788 * SCR is in range 0 .. 255
789 *
790 * Divisor = 5^i * 2^j * 2 * k
791 * i = [0, 1] i = 1 iff j = 0 or j > 3
792 * j = [0, 23] j = 0 iff i = 1
793 * k = [1, 256]
794 * Special case: j = 0, i = 1: Divisor = 2 / 5
795 *
796 * Accordingly to the specification the recommended values for DDS_CLK_RATE
797 * are:
798 * Case 1: 2^n, n = [0, 23]
799 * Case 2: 2^24 * 2 / 5 (0x666666)
800 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
801 *
802 * In all cases the lowest possible value is better.
803 *
804 * The function calculates parameters for all cases and chooses the one closest
805 * to the asked baud rate.
806 */
807static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
808{
809 unsigned long xtal = 200000000;
810 unsigned long fref = xtal / 2; /* mandatory division by 2,
811 see (2) */
812 /* case 3 */
813 unsigned long fref1 = fref / 2; /* case 1 */
814 unsigned long fref2 = fref * 2 / 5; /* case 2 */
815 unsigned long scale;
816 unsigned long q, q1, q2;
817 long r, r1, r2;
818 u32 mul;
819
820 /* Case 1 */
821
822 /* Set initial value for DDS_CLK_RATE */
823 mul = (1 << 24) >> 1;
824
825 /* Calculate initial quot */
826 q1 = DIV_ROUND_UP(fref1, rate);
827
828 /* Scale q1 if it's too big */
829 if (q1 > 256) {
830 /* Scale q1 to range [1, 512] */
831 scale = fls_long(q1 - 1);
832 if (scale > 9) {
833 q1 >>= scale - 9;
834 mul >>= scale - 9;
835 }
836
837 /* Round the result if we have a remainder */
838 q1 += q1 & 1;
839 }
840
841 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
842 scale = __ffs(q1);
843 q1 >>= scale;
844 mul >>= scale;
845
846 /* Get the remainder */
847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
848
849 /* Case 2 */
850
851 q2 = DIV_ROUND_UP(fref2, rate);
852 r2 = abs(fref2 / q2 - rate);
853
854 /*
855 * Choose the best between two: less remainder we have the better. We
856 * can't go case 2 if q2 is greater than 256 since SCR register can
857 * hold only values 0 .. 255.
858 */
859 if (r2 >= r1 || q2 > 256) {
860 /* case 1 is better */
861 r = r1;
862 q = q1;
863 } else {
864 /* case 2 is better */
865 r = r2;
866 q = q2;
867 mul = (1 << 24) * 2 / 5;
868 }
869
870 /* Check case 3 only if the divisor is big enough */
871 if (fref / rate >= 80) {
872 u64 fssp;
873 u32 m;
874
875 /* Calculate initial quot */
876 q1 = DIV_ROUND_UP(fref, rate);
877 m = (1 << 24) / q1;
878
879 /* Get the remainder */
880 fssp = (u64)fref * m;
881 do_div(fssp, 1 << 24);
882 r1 = abs(fssp - rate);
883
884 /* Choose this one if it suits better */
885 if (r1 < r) {
886 /* case 3 is better */
887 q = 1;
888 mul = m;
889 }
890 }
891
892 *dds = mul;
893 return q - 1;
894}
895
896static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
897{
898 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
899 const struct ssp_device *ssp = drv_data->ssp;
900
901 rate = min_t(int, ssp_clk, rate);
902
903 /*
904 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
905 * that the SSP transmission rate can be greater than the device rate.
906 */
907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
909 else
910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
911}
912
913static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
914 int rate)
915{
916 struct chip_data *chip =
917 spi_get_ctldata(drv_data->controller->cur_msg->spi);
918 unsigned int clk_div;
919
920 switch (drv_data->ssp_type) {
921 case QUARK_X1000_SSP:
922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
923 break;
924 default:
925 clk_div = ssp_get_clk_div(drv_data, rate);
926 break;
927 }
928 return clk_div << 8;
929}
930
931static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
932 struct spi_device *spi,
933 struct spi_transfer *xfer)
934{
935 struct chip_data *chip = spi_get_ctldata(spi);
936
937 return chip->enable_dma &&
938 xfer->len <= MAX_DMA_LEN &&
939 xfer->len >= chip->dma_burst_size;
940}
941
942static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
943 struct spi_device *spi,
944 struct spi_transfer *transfer)
945{
946 struct driver_data *drv_data = spi_controller_get_devdata(controller);
947 struct spi_message *message = controller->cur_msg;
948 struct chip_data *chip = spi_get_ctldata(spi);
949 u32 dma_thresh = chip->dma_threshold;
950 u32 dma_burst = chip->dma_burst_size;
951 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
952 u32 clk_div;
953 u8 bits;
954 u32 speed;
955 u32 cr0;
956 u32 cr1;
957 int err;
958 int dma_mapped;
959
960 /* Check if we can DMA this transfer */
961 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
962
963 /* Reject already-mapped transfers; PIO won't always work */
964 if (message->is_dma_mapped
965 || transfer->rx_dma || transfer->tx_dma) {
966 dev_err(&spi->dev,
967 "Mapped transfer length of %u is greater than %d\n",
968 transfer->len, MAX_DMA_LEN);
969 return -EINVAL;
970 }
971
972 /* Warn ... we force this to PIO mode */
973 dev_warn_ratelimited(&spi->dev,
974 "DMA disabled for transfer length %u greater than %d\n",
975 transfer->len, MAX_DMA_LEN);
976 }
977
978 /* Setup the transfer state based on the type of transfer */
979 if (pxa2xx_spi_flush(drv_data) == 0) {
980 dev_err(&spi->dev, "Flush failed\n");
981 return -EIO;
982 }
983 drv_data->tx = (void *)transfer->tx_buf;
984 drv_data->tx_end = drv_data->tx + transfer->len;
985 drv_data->rx = transfer->rx_buf;
986 drv_data->rx_end = drv_data->rx + transfer->len;
987
988 /* Change speed and bit per word on a per transfer */
989 bits = transfer->bits_per_word;
990 speed = transfer->speed_hz;
991
992 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
993
994 if (bits <= 8) {
995 drv_data->n_bytes = 1;
996 drv_data->read = drv_data->rx ? u8_reader : null_reader;
997 drv_data->write = drv_data->tx ? u8_writer : null_writer;
998 } else if (bits <= 16) {
999 drv_data->n_bytes = 2;
1000 drv_data->read = drv_data->rx ? u16_reader : null_reader;
1001 drv_data->write = drv_data->tx ? u16_writer : null_writer;
1002 } else if (bits <= 32) {
1003 drv_data->n_bytes = 4;
1004 drv_data->read = drv_data->rx ? u32_reader : null_reader;
1005 drv_data->write = drv_data->tx ? u32_writer : null_writer;
1006 }
1007 /*
1008 * If bits per word is changed in DMA mode, then must check
1009 * the thresholds and burst also.
1010 */
1011 if (chip->enable_dma) {
1012 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1013 spi,
1014 bits, &dma_burst,
1015 &dma_thresh))
1016 dev_warn_ratelimited(&spi->dev,
1017 "DMA burst size reduced to match bits_per_word\n");
1018 }
1019
1020 dma_mapped = controller->can_dma &&
1021 controller->can_dma(controller, spi, transfer) &&
1022 controller->cur_msg_mapped;
1023 if (dma_mapped) {
1024
1025 /* Ensure we have the correct interrupt handler */
1026 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1027
1028 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1029 if (err)
1030 return err;
1031
1032 /* Clear status and start DMA engine */
1033 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1034 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1035
1036 pxa2xx_spi_dma_start(drv_data);
1037 } else {
1038 /* Ensure we have the correct interrupt handler */
1039 drv_data->transfer_handler = interrupt_transfer;
1040
1041 /* Clear status */
1042 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1043 write_SSSR_CS(drv_data, drv_data->clear_sr);
1044 }
1045
1046 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1047 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1048 if (!pxa25x_ssp_comp(drv_data))
1049 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1050 controller->max_speed_hz
1051 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1052 dma_mapped ? "DMA" : "PIO");
1053 else
1054 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1055 controller->max_speed_hz / 2
1056 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1057 dma_mapped ? "DMA" : "PIO");
1058
1059 if (is_lpss_ssp(drv_data)) {
1060 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1061 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1062 }
1063
1064 if (is_mrfld_ssp(drv_data)) {
1065 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1066 u32 thresh = 0;
1067
1068 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1069 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1070
1071 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1072 }
1073
1074 if (is_quark_x1000_ssp(drv_data))
1075 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1076
1077 /* Stop the SSP */
1078 if (!is_mmp2_ssp(drv_data))
1079 pxa_ssp_disable(drv_data->ssp);
1080
1081 if (!pxa25x_ssp_comp(drv_data))
1082 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1083
1084 /* First set CR1 without interrupt and service enables */
1085 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1086
1087 /* See if we need to reload the configuration registers */
1088 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1089
1090 /* Restart the SSP */
1091 pxa_ssp_enable(drv_data->ssp);
1092
1093 if (is_mmp2_ssp(drv_data)) {
1094 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1095
1096 if (tx_level) {
1097 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1098 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1099 if (tx_level > transfer->len)
1100 tx_level = transfer->len;
1101 drv_data->tx += tx_level;
1102 }
1103 }
1104
1105 if (spi_controller_is_slave(controller)) {
1106 while (drv_data->write(drv_data))
1107 ;
1108 if (drv_data->gpiod_ready) {
1109 gpiod_set_value(drv_data->gpiod_ready, 1);
1110 udelay(1);
1111 gpiod_set_value(drv_data->gpiod_ready, 0);
1112 }
1113 }
1114
1115 /*
1116 * Release the data by enabling service requests and interrupts,
1117 * without changing any mode bits.
1118 */
1119 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1120
1121 return 1;
1122}
1123
1124static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1125{
1126 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1127
1128 int_error_stop(drv_data, "transfer aborted", -EINTR);
1129
1130 return 0;
1131}
1132
1133static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1134 struct spi_message *msg)
1135{
1136 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1137
1138 int_stop_and_reset(drv_data);
1139
1140 /* Disable the SSP */
1141 pxa2xx_spi_off(drv_data);
1142
1143 /*
1144 * Stop the DMA if running. Note DMA callback handler may have unset
1145 * the dma_running already, which is fine as stopping is not needed
1146 * then but we shouldn't rely this flag for anything else than
1147 * stopping. For instance to differentiate between PIO and DMA
1148 * transfers.
1149 */
1150 if (atomic_read(&drv_data->dma_running))
1151 pxa2xx_spi_dma_stop(drv_data);
1152}
1153
1154static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1155{
1156 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1157
1158 /* Disable the SSP now */
1159 pxa2xx_spi_off(drv_data);
1160
1161 return 0;
1162}
1163
1164static int setup(struct spi_device *spi)
1165{
1166 struct pxa2xx_spi_chip *chip_info;
1167 struct chip_data *chip;
1168 const struct lpss_config *config;
1169 struct driver_data *drv_data =
1170 spi_controller_get_devdata(spi->controller);
1171 uint tx_thres, tx_hi_thres, rx_thres;
1172
1173 switch (drv_data->ssp_type) {
1174 case QUARK_X1000_SSP:
1175 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1176 tx_hi_thres = 0;
1177 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1178 break;
1179 case MRFLD_SSP:
1180 tx_thres = TX_THRESH_MRFLD_DFLT;
1181 tx_hi_thres = 0;
1182 rx_thres = RX_THRESH_MRFLD_DFLT;
1183 break;
1184 case CE4100_SSP:
1185 tx_thres = TX_THRESH_CE4100_DFLT;
1186 tx_hi_thres = 0;
1187 rx_thres = RX_THRESH_CE4100_DFLT;
1188 break;
1189 case LPSS_LPT_SSP:
1190 case LPSS_BYT_SSP:
1191 case LPSS_BSW_SSP:
1192 case LPSS_SPT_SSP:
1193 case LPSS_BXT_SSP:
1194 case LPSS_CNL_SSP:
1195 config = lpss_get_config(drv_data);
1196 tx_thres = config->tx_threshold_lo;
1197 tx_hi_thres = config->tx_threshold_hi;
1198 rx_thres = config->rx_threshold;
1199 break;
1200 default:
1201 tx_hi_thres = 0;
1202 if (spi_controller_is_slave(drv_data->controller)) {
1203 tx_thres = 1;
1204 rx_thres = 2;
1205 } else {
1206 tx_thres = TX_THRESH_DFLT;
1207 rx_thres = RX_THRESH_DFLT;
1208 }
1209 break;
1210 }
1211
1212 /* Only allocate on the first setup */
1213 chip = spi_get_ctldata(spi);
1214 if (!chip) {
1215 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1216 if (!chip)
1217 return -ENOMEM;
1218
1219 if (drv_data->ssp_type == CE4100_SSP) {
1220 if (spi->chip_select > 4) {
1221 dev_err(&spi->dev,
1222 "failed setup: cs number must not be > 4.\n");
1223 kfree(chip);
1224 return -EINVAL;
1225 }
1226 }
1227 chip->enable_dma = drv_data->controller_info->enable_dma;
1228 chip->timeout = TIMOUT_DFLT;
1229 }
1230
1231 /*
1232 * Protocol drivers may change the chip settings, so...
1233 * if chip_info exists, use it.
1234 */
1235 chip_info = spi->controller_data;
1236
1237 /* chip_info isn't always needed */
1238 if (chip_info) {
1239 if (chip_info->timeout)
1240 chip->timeout = chip_info->timeout;
1241 if (chip_info->tx_threshold)
1242 tx_thres = chip_info->tx_threshold;
1243 if (chip_info->tx_hi_threshold)
1244 tx_hi_thres = chip_info->tx_hi_threshold;
1245 if (chip_info->rx_threshold)
1246 rx_thres = chip_info->rx_threshold;
1247 chip->dma_threshold = 0;
1248 }
1249
1250 chip->cr1 = 0;
1251 if (spi_controller_is_slave(drv_data->controller)) {
1252 chip->cr1 |= SSCR1_SCFR;
1253 chip->cr1 |= SSCR1_SCLKDIR;
1254 chip->cr1 |= SSCR1_SFRMDIR;
1255 chip->cr1 |= SSCR1_SPH;
1256 }
1257
1258 if (is_lpss_ssp(drv_data)) {
1259 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1260 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1261 SSITF_TxHiThresh(tx_hi_thres);
1262 }
1263
1264 if (is_mrfld_ssp(drv_data)) {
1265 chip->lpss_rx_threshold = rx_thres;
1266 chip->lpss_tx_threshold = tx_thres;
1267 }
1268
1269 /*
1270 * Set DMA burst and threshold outside of chip_info path so that if
1271 * chip_info goes away after setting chip->enable_dma, the burst and
1272 * threshold can still respond to changes in bits_per_word.
1273 */
1274 if (chip->enable_dma) {
1275 /* Set up legal burst and threshold for DMA */
1276 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1277 spi->bits_per_word,
1278 &chip->dma_burst_size,
1279 &chip->dma_threshold)) {
1280 dev_warn(&spi->dev,
1281 "in setup: DMA burst size reduced to match bits_per_word\n");
1282 }
1283 dev_dbg(&spi->dev,
1284 "in setup: DMA burst size set to %u\n",
1285 chip->dma_burst_size);
1286 }
1287
1288 switch (drv_data->ssp_type) {
1289 case QUARK_X1000_SSP:
1290 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1291 & QUARK_X1000_SSCR1_RFT)
1292 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1293 & QUARK_X1000_SSCR1_TFT);
1294 break;
1295 case CE4100_SSP:
1296 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1297 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1298 break;
1299 default:
1300 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1301 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1302 break;
1303 }
1304
1305 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1306 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1307 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1308
1309 if (spi->mode & SPI_LOOP)
1310 chip->cr1 |= SSCR1_LBM;
1311
1312 spi_set_ctldata(spi, chip);
1313
1314 return 0;
1315}
1316
1317static void cleanup(struct spi_device *spi)
1318{
1319 struct chip_data *chip = spi_get_ctldata(spi);
1320
1321 kfree(chip);
1322}
1323
1324static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1325{
1326 return param == chan->device->dev;
1327}
1328
1329static struct pxa2xx_spi_controller *
1330pxa2xx_spi_init_pdata(struct platform_device *pdev)
1331{
1332 struct pxa2xx_spi_controller *pdata;
1333 struct device *dev = &pdev->dev;
1334 struct device *parent = dev->parent;
1335 struct ssp_device *ssp;
1336 struct resource *res;
1337 enum pxa_ssp_type type = SSP_UNDEFINED;
1338 const void *match;
1339 bool is_lpss_priv;
1340 int status;
1341 u64 uid;
1342
1343 is_lpss_priv = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpss_priv");
1344
1345 match = device_get_match_data(dev);
1346 if (match)
1347 type = (enum pxa_ssp_type)match;
1348 else if (is_lpss_priv) {
1349 u32 value;
1350
1351 status = device_property_read_u32(dev, "intel,spi-pxa2xx-type", &value);
1352 if (status)
1353 return ERR_PTR(status);
1354
1355 type = (enum pxa_ssp_type)value;
1356 }
1357
1358 /* Validate the SSP type correctness */
1359 if (!(type > SSP_UNDEFINED && type < SSP_MAX))
1360 return ERR_PTR(-EINVAL);
1361
1362 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1363 if (!pdata)
1364 return ERR_PTR(-ENOMEM);
1365
1366 ssp = &pdata->ssp;
1367
1368 ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1369 if (IS_ERR(ssp->mmio_base))
1370 return ERR_CAST(ssp->mmio_base);
1371
1372 ssp->phys_base = res->start;
1373
1374 /* Platforms with iDMA 64-bit */
1375 if (is_lpss_priv) {
1376 pdata->tx_param = parent;
1377 pdata->rx_param = parent;
1378 pdata->dma_filter = pxa2xx_spi_idma_filter;
1379 }
1380
1381 ssp->clk = devm_clk_get(dev, NULL);
1382 if (IS_ERR(ssp->clk))
1383 return ERR_CAST(ssp->clk);
1384
1385 ssp->irq = platform_get_irq(pdev, 0);
1386 if (ssp->irq < 0)
1387 return ERR_PTR(ssp->irq);
1388
1389 ssp->type = type;
1390 ssp->dev = dev;
1391
1392 status = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &uid);
1393 if (status)
1394 ssp->port_id = -1;
1395 else
1396 ssp->port_id = uid;
1397
1398 pdata->is_slave = device_property_read_bool(dev, "spi-slave");
1399 pdata->num_chipselect = 1;
1400 pdata->enable_dma = true;
1401 pdata->dma_burst_size = 1;
1402
1403 return pdata;
1404}
1405
1406static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1407 unsigned int cs)
1408{
1409 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1410
1411 if (has_acpi_companion(drv_data->ssp->dev)) {
1412 switch (drv_data->ssp_type) {
1413 /*
1414 * For Atoms the ACPI DeviceSelection used by the Windows
1415 * driver starts from 1 instead of 0 so translate it here
1416 * to match what Linux expects.
1417 */
1418 case LPSS_BYT_SSP:
1419 case LPSS_BSW_SSP:
1420 return cs - 1;
1421
1422 default:
1423 break;
1424 }
1425 }
1426
1427 return cs;
1428}
1429
1430static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1431{
1432 return MAX_DMA_LEN;
1433}
1434
1435static int pxa2xx_spi_probe(struct platform_device *pdev)
1436{
1437 struct device *dev = &pdev->dev;
1438 struct pxa2xx_spi_controller *platform_info;
1439 struct spi_controller *controller;
1440 struct driver_data *drv_data;
1441 struct ssp_device *ssp;
1442 const struct lpss_config *config;
1443 int status;
1444 u32 tmp;
1445
1446 platform_info = dev_get_platdata(dev);
1447 if (!platform_info) {
1448 platform_info = pxa2xx_spi_init_pdata(pdev);
1449 if (IS_ERR(platform_info)) {
1450 dev_err(&pdev->dev, "missing platform data\n");
1451 return PTR_ERR(platform_info);
1452 }
1453 }
1454
1455 ssp = pxa_ssp_request(pdev->id, pdev->name);
1456 if (!ssp)
1457 ssp = &platform_info->ssp;
1458
1459 if (!ssp->mmio_base) {
1460 dev_err(&pdev->dev, "failed to get SSP\n");
1461 return -ENODEV;
1462 }
1463
1464 if (platform_info->is_slave)
1465 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1466 else
1467 controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1468
1469 if (!controller) {
1470 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1471 status = -ENOMEM;
1472 goto out_error_controller_alloc;
1473 }
1474 drv_data = spi_controller_get_devdata(controller);
1475 drv_data->controller = controller;
1476 drv_data->controller_info = platform_info;
1477 drv_data->ssp = ssp;
1478
1479 device_set_node(&controller->dev, dev_fwnode(dev));
1480
1481 /* The spi->mode bits understood by this driver: */
1482 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1483
1484 controller->bus_num = ssp->port_id;
1485 controller->dma_alignment = DMA_ALIGNMENT;
1486 controller->cleanup = cleanup;
1487 controller->setup = setup;
1488 controller->set_cs = pxa2xx_spi_set_cs;
1489 controller->transfer_one = pxa2xx_spi_transfer_one;
1490 controller->slave_abort = pxa2xx_spi_slave_abort;
1491 controller->handle_err = pxa2xx_spi_handle_err;
1492 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1493 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1494 controller->auto_runtime_pm = true;
1495 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1496
1497 drv_data->ssp_type = ssp->type;
1498
1499 if (pxa25x_ssp_comp(drv_data)) {
1500 switch (drv_data->ssp_type) {
1501 case QUARK_X1000_SSP:
1502 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1503 break;
1504 default:
1505 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1506 break;
1507 }
1508
1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1510 drv_data->dma_cr1 = 0;
1511 drv_data->clear_sr = SSSR_ROR;
1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1513 } else {
1514 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1516 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1519 | SSSR_ROR | SSSR_TUR;
1520 }
1521
1522 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1523 drv_data);
1524 if (status < 0) {
1525 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1526 goto out_error_controller_alloc;
1527 }
1528
1529 /* Setup DMA if requested */
1530 if (platform_info->enable_dma) {
1531 status = pxa2xx_spi_dma_setup(drv_data);
1532 if (status) {
1533 dev_warn(dev, "no DMA channels available, using PIO\n");
1534 platform_info->enable_dma = false;
1535 } else {
1536 controller->can_dma = pxa2xx_spi_can_dma;
1537 controller->max_dma_len = MAX_DMA_LEN;
1538 controller->max_transfer_size =
1539 pxa2xx_spi_max_dma_transfer_size;
1540 }
1541 }
1542
1543 /* Enable SOC clock */
1544 status = clk_prepare_enable(ssp->clk);
1545 if (status)
1546 goto out_error_dma_irq_alloc;
1547
1548 controller->max_speed_hz = clk_get_rate(ssp->clk);
1549 /*
1550 * Set minimum speed for all other platforms than Intel Quark which is
1551 * able do under 1 Hz transfers.
1552 */
1553 if (!pxa25x_ssp_comp(drv_data))
1554 controller->min_speed_hz =
1555 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1556 else if (!is_quark_x1000_ssp(drv_data))
1557 controller->min_speed_hz =
1558 DIV_ROUND_UP(controller->max_speed_hz, 512);
1559
1560 pxa_ssp_disable(ssp);
1561
1562 /* Load default SSP configuration */
1563 switch (drv_data->ssp_type) {
1564 case QUARK_X1000_SSP:
1565 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1566 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1567 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1568
1569 /* Using the Motorola SPI protocol and use 8 bit frame */
1570 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1571 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1572 break;
1573 case CE4100_SSP:
1574 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1575 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1576 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1577 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1578 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1579 break;
1580 default:
1581
1582 if (spi_controller_is_slave(controller)) {
1583 tmp = SSCR1_SCFR |
1584 SSCR1_SCLKDIR |
1585 SSCR1_SFRMDIR |
1586 SSCR1_RxTresh(2) |
1587 SSCR1_TxTresh(1) |
1588 SSCR1_SPH;
1589 } else {
1590 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1591 SSCR1_TxTresh(TX_THRESH_DFLT);
1592 }
1593 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1594 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1595 if (!spi_controller_is_slave(controller))
1596 tmp |= SSCR0_SCR(2);
1597 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1598 break;
1599 }
1600
1601 if (!pxa25x_ssp_comp(drv_data))
1602 pxa2xx_spi_write(drv_data, SSTO, 0);
1603
1604 if (!is_quark_x1000_ssp(drv_data))
1605 pxa2xx_spi_write(drv_data, SSPSP, 0);
1606
1607 if (is_lpss_ssp(drv_data)) {
1608 lpss_ssp_setup(drv_data);
1609 config = lpss_get_config(drv_data);
1610 if (config->reg_capabilities >= 0) {
1611 tmp = __lpss_ssp_read_priv(drv_data,
1612 config->reg_capabilities);
1613 tmp &= LPSS_CAPS_CS_EN_MASK;
1614 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1615 platform_info->num_chipselect = ffz(tmp);
1616 } else if (config->cs_num) {
1617 platform_info->num_chipselect = config->cs_num;
1618 }
1619 }
1620 controller->num_chipselect = platform_info->num_chipselect;
1621 controller->use_gpio_descriptors = true;
1622
1623 if (platform_info->is_slave) {
1624 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1625 "ready", GPIOD_OUT_LOW);
1626 if (IS_ERR(drv_data->gpiod_ready)) {
1627 status = PTR_ERR(drv_data->gpiod_ready);
1628 goto out_error_clock_enabled;
1629 }
1630 }
1631
1632 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1633 pm_runtime_use_autosuspend(&pdev->dev);
1634 pm_runtime_set_active(&pdev->dev);
1635 pm_runtime_enable(&pdev->dev);
1636
1637 /* Register with the SPI framework */
1638 platform_set_drvdata(pdev, drv_data);
1639 status = spi_register_controller(controller);
1640 if (status) {
1641 dev_err(&pdev->dev, "problem registering SPI controller\n");
1642 goto out_error_pm_runtime_enabled;
1643 }
1644
1645 return status;
1646
1647out_error_pm_runtime_enabled:
1648 pm_runtime_disable(&pdev->dev);
1649
1650out_error_clock_enabled:
1651 clk_disable_unprepare(ssp->clk);
1652
1653out_error_dma_irq_alloc:
1654 pxa2xx_spi_dma_release(drv_data);
1655 free_irq(ssp->irq, drv_data);
1656
1657out_error_controller_alloc:
1658 pxa_ssp_free(ssp);
1659 return status;
1660}
1661
1662static int pxa2xx_spi_remove(struct platform_device *pdev)
1663{
1664 struct driver_data *drv_data = platform_get_drvdata(pdev);
1665 struct ssp_device *ssp = drv_data->ssp;
1666
1667 pm_runtime_get_sync(&pdev->dev);
1668
1669 spi_unregister_controller(drv_data->controller);
1670
1671 /* Disable the SSP at the peripheral and SOC level */
1672 pxa_ssp_disable(ssp);
1673 clk_disable_unprepare(ssp->clk);
1674
1675 /* Release DMA */
1676 if (drv_data->controller_info->enable_dma)
1677 pxa2xx_spi_dma_release(drv_data);
1678
1679 pm_runtime_put_noidle(&pdev->dev);
1680 pm_runtime_disable(&pdev->dev);
1681
1682 /* Release IRQ */
1683 free_irq(ssp->irq, drv_data);
1684
1685 /* Release SSP */
1686 pxa_ssp_free(ssp);
1687
1688 return 0;
1689}
1690
1691static int pxa2xx_spi_suspend(struct device *dev)
1692{
1693 struct driver_data *drv_data = dev_get_drvdata(dev);
1694 struct ssp_device *ssp = drv_data->ssp;
1695 int status;
1696
1697 status = spi_controller_suspend(drv_data->controller);
1698 if (status)
1699 return status;
1700
1701 pxa_ssp_disable(ssp);
1702
1703 if (!pm_runtime_suspended(dev))
1704 clk_disable_unprepare(ssp->clk);
1705
1706 return 0;
1707}
1708
1709static int pxa2xx_spi_resume(struct device *dev)
1710{
1711 struct driver_data *drv_data = dev_get_drvdata(dev);
1712 struct ssp_device *ssp = drv_data->ssp;
1713 int status;
1714
1715 /* Enable the SSP clock */
1716 if (!pm_runtime_suspended(dev)) {
1717 status = clk_prepare_enable(ssp->clk);
1718 if (status)
1719 return status;
1720 }
1721
1722 /* Start the queue running */
1723 return spi_controller_resume(drv_data->controller);
1724}
1725
1726static int pxa2xx_spi_runtime_suspend(struct device *dev)
1727{
1728 struct driver_data *drv_data = dev_get_drvdata(dev);
1729
1730 clk_disable_unprepare(drv_data->ssp->clk);
1731 return 0;
1732}
1733
1734static int pxa2xx_spi_runtime_resume(struct device *dev)
1735{
1736 struct driver_data *drv_data = dev_get_drvdata(dev);
1737
1738 return clk_prepare_enable(drv_data->ssp->clk);
1739}
1740
1741static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1742 SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1743 RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1744};
1745
1746#ifdef CONFIG_ACPI
1747static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1748 { "80860F0E", LPSS_BYT_SSP },
1749 { "8086228E", LPSS_BSW_SSP },
1750 { "INT33C0", LPSS_LPT_SSP },
1751 { "INT33C1", LPSS_LPT_SSP },
1752 { "INT3430", LPSS_LPT_SSP },
1753 { "INT3431", LPSS_LPT_SSP },
1754 {}
1755};
1756MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1757#endif
1758
1759static const struct of_device_id pxa2xx_spi_of_match[] = {
1760 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1761 {}
1762};
1763MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1764
1765static struct platform_driver driver = {
1766 .driver = {
1767 .name = "pxa2xx-spi",
1768 .pm = pm_ptr(&pxa2xx_spi_pm_ops),
1769 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1770 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1771 },
1772 .probe = pxa2xx_spi_probe,
1773 .remove = pxa2xx_spi_remove,
1774};
1775
1776static int __init pxa2xx_spi_init(void)
1777{
1778 return platform_driver_register(&driver);
1779}
1780subsys_initcall(pxa2xx_spi_init);
1781
1782static void __exit pxa2xx_spi_exit(void)
1783{
1784 platform_driver_unregister(&driver);
1785}
1786module_exit(pxa2xx_spi_exit);
1787
1788MODULE_SOFTDEP("pre: dw_dmac");
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/bitops.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/ioport.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
25#include <linux/pci.h>
26#include <linux/platform_device.h>
27#include <linux/spi/pxa2xx_spi.h>
28#include <linux/spi/spi.h>
29#include <linux/delay.h>
30#include <linux/gpio.h>
31#include <linux/slab.h>
32#include <linux/clk.h>
33#include <linux/pm_runtime.h>
34#include <linux/acpi.h>
35
36#include "spi-pxa2xx.h"
37
38MODULE_AUTHOR("Stephen Street");
39MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40MODULE_LICENSE("GPL");
41MODULE_ALIAS("platform:pxa2xx-spi");
42
43#define TIMOUT_DFLT 1000
44
45/*
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
51 */
52#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
58
59#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
65#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66#define LPSS_CS_CONTROL_SW_MODE BIT(0)
67#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68#define LPSS_CAPS_CS_EN_SHIFT 9
69#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
70
71struct lpss_config {
72 /* LPSS offset from drv_data->ioaddr */
73 unsigned offset;
74 /* Register offsets from drv_data->lpss_base or -1 */
75 int reg_general;
76 int reg_ssp;
77 int reg_cs_ctrl;
78 int reg_capabilities;
79 /* FIFO thresholds */
80 u32 rx_threshold;
81 u32 tx_threshold_lo;
82 u32 tx_threshold_hi;
83 /* Chip select control */
84 unsigned cs_sel_shift;
85 unsigned cs_sel_mask;
86 unsigned cs_num;
87};
88
89/* Keep these sorted with enum pxa_ssp_type */
90static const struct lpss_config lpss_platforms[] = {
91 { /* LPSS_LPT_SSP */
92 .offset = 0x800,
93 .reg_general = 0x08,
94 .reg_ssp = 0x0c,
95 .reg_cs_ctrl = 0x18,
96 .reg_capabilities = -1,
97 .rx_threshold = 64,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
100 },
101 { /* LPSS_BYT_SSP */
102 .offset = 0x400,
103 .reg_general = 0x08,
104 .reg_ssp = 0x0c,
105 .reg_cs_ctrl = 0x18,
106 .reg_capabilities = -1,
107 .rx_threshold = 64,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
110 },
111 { /* LPSS_BSW_SSP */
112 .offset = 0x400,
113 .reg_general = 0x08,
114 .reg_ssp = 0x0c,
115 .reg_cs_ctrl = 0x18,
116 .reg_capabilities = -1,
117 .rx_threshold = 64,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
120 .cs_sel_shift = 2,
121 .cs_sel_mask = 1 << 2,
122 .cs_num = 2,
123 },
124 { /* LPSS_SPT_SSP */
125 .offset = 0x200,
126 .reg_general = -1,
127 .reg_ssp = 0x20,
128 .reg_cs_ctrl = 0x24,
129 .reg_capabilities = -1,
130 .rx_threshold = 1,
131 .tx_threshold_lo = 32,
132 .tx_threshold_hi = 56,
133 },
134 { /* LPSS_BXT_SSP */
135 .offset = 0x200,
136 .reg_general = -1,
137 .reg_ssp = 0x20,
138 .reg_cs_ctrl = 0x24,
139 .reg_capabilities = 0xfc,
140 .rx_threshold = 1,
141 .tx_threshold_lo = 16,
142 .tx_threshold_hi = 48,
143 .cs_sel_shift = 8,
144 .cs_sel_mask = 3 << 8,
145 },
146};
147
148static inline const struct lpss_config
149*lpss_get_config(const struct driver_data *drv_data)
150{
151 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
152}
153
154static bool is_lpss_ssp(const struct driver_data *drv_data)
155{
156 switch (drv_data->ssp_type) {
157 case LPSS_LPT_SSP:
158 case LPSS_BYT_SSP:
159 case LPSS_BSW_SSP:
160 case LPSS_SPT_SSP:
161 case LPSS_BXT_SSP:
162 return true;
163 default:
164 return false;
165 }
166}
167
168static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
169{
170 return drv_data->ssp_type == QUARK_X1000_SSP;
171}
172
173static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
174{
175 switch (drv_data->ssp_type) {
176 case QUARK_X1000_SSP:
177 return QUARK_X1000_SSCR1_CHANGE_MASK;
178 default:
179 return SSCR1_CHANGE_MASK;
180 }
181}
182
183static u32
184pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
185{
186 switch (drv_data->ssp_type) {
187 case QUARK_X1000_SSP:
188 return RX_THRESH_QUARK_X1000_DFLT;
189 default:
190 return RX_THRESH_DFLT;
191 }
192}
193
194static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
195{
196 u32 mask;
197
198 switch (drv_data->ssp_type) {
199 case QUARK_X1000_SSP:
200 mask = QUARK_X1000_SSSR_TFL_MASK;
201 break;
202 default:
203 mask = SSSR_TFL_MASK;
204 break;
205 }
206
207 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
208}
209
210static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
211 u32 *sccr1_reg)
212{
213 u32 mask;
214
215 switch (drv_data->ssp_type) {
216 case QUARK_X1000_SSP:
217 mask = QUARK_X1000_SSCR1_RFT;
218 break;
219 default:
220 mask = SSCR1_RFT;
221 break;
222 }
223 *sccr1_reg &= ~mask;
224}
225
226static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
227 u32 *sccr1_reg, u32 threshold)
228{
229 switch (drv_data->ssp_type) {
230 case QUARK_X1000_SSP:
231 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
232 break;
233 default:
234 *sccr1_reg |= SSCR1_RxTresh(threshold);
235 break;
236 }
237}
238
239static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
240 u32 clk_div, u8 bits)
241{
242 switch (drv_data->ssp_type) {
243 case QUARK_X1000_SSP:
244 return clk_div
245 | QUARK_X1000_SSCR0_Motorola
246 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
247 | SSCR0_SSE;
248 default:
249 return clk_div
250 | SSCR0_Motorola
251 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
252 | SSCR0_SSE
253 | (bits > 16 ? SSCR0_EDSS : 0);
254 }
255}
256
257/*
258 * Read and write LPSS SSP private registers. Caller must first check that
259 * is_lpss_ssp() returns true before these can be called.
260 */
261static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
262{
263 WARN_ON(!drv_data->lpss_base);
264 return readl(drv_data->lpss_base + offset);
265}
266
267static void __lpss_ssp_write_priv(struct driver_data *drv_data,
268 unsigned offset, u32 value)
269{
270 WARN_ON(!drv_data->lpss_base);
271 writel(value, drv_data->lpss_base + offset);
272}
273
274/*
275 * lpss_ssp_setup - perform LPSS SSP specific setup
276 * @drv_data: pointer to the driver private data
277 *
278 * Perform LPSS SSP specific setup. This function must be called first if
279 * one is going to use LPSS SSP private registers.
280 */
281static void lpss_ssp_setup(struct driver_data *drv_data)
282{
283 const struct lpss_config *config;
284 u32 value;
285
286 config = lpss_get_config(drv_data);
287 drv_data->lpss_base = drv_data->ioaddr + config->offset;
288
289 /* Enable software chip select control */
290 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
291 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
292 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
293 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
294
295 /* Enable multiblock DMA transfers */
296 if (drv_data->master_info->enable_dma) {
297 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
298
299 if (config->reg_general >= 0) {
300 value = __lpss_ssp_read_priv(drv_data,
301 config->reg_general);
302 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
303 __lpss_ssp_write_priv(drv_data,
304 config->reg_general, value);
305 }
306 }
307}
308
309static void lpss_ssp_select_cs(struct driver_data *drv_data,
310 const struct lpss_config *config)
311{
312 u32 value, cs;
313
314 if (!config->cs_sel_mask)
315 return;
316
317 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
318
319 cs = drv_data->cur_msg->spi->chip_select;
320 cs <<= config->cs_sel_shift;
321 if (cs != (value & config->cs_sel_mask)) {
322 /*
323 * When switching another chip select output active the
324 * output must be selected first and wait 2 ssp_clk cycles
325 * before changing state to active. Otherwise a short
326 * glitch will occur on the previous chip select since
327 * output select is latched but state control is not.
328 */
329 value &= ~config->cs_sel_mask;
330 value |= cs;
331 __lpss_ssp_write_priv(drv_data,
332 config->reg_cs_ctrl, value);
333 ndelay(1000000000 /
334 (drv_data->master->max_speed_hz / 2));
335 }
336}
337
338static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
339{
340 const struct lpss_config *config;
341 u32 value;
342
343 config = lpss_get_config(drv_data);
344
345 if (enable)
346 lpss_ssp_select_cs(drv_data, config);
347
348 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
349 if (enable)
350 value &= ~LPSS_CS_CONTROL_CS_HIGH;
351 else
352 value |= LPSS_CS_CONTROL_CS_HIGH;
353 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
354}
355
356static void cs_assert(struct driver_data *drv_data)
357{
358 struct chip_data *chip = drv_data->cur_chip;
359
360 if (drv_data->ssp_type == CE4100_SSP) {
361 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
362 return;
363 }
364
365 if (chip->cs_control) {
366 chip->cs_control(PXA2XX_CS_ASSERT);
367 return;
368 }
369
370 if (gpio_is_valid(chip->gpio_cs)) {
371 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
372 return;
373 }
374
375 if (is_lpss_ssp(drv_data))
376 lpss_ssp_cs_control(drv_data, true);
377}
378
379static void cs_deassert(struct driver_data *drv_data)
380{
381 struct chip_data *chip = drv_data->cur_chip;
382
383 if (drv_data->ssp_type == CE4100_SSP)
384 return;
385
386 if (chip->cs_control) {
387 chip->cs_control(PXA2XX_CS_DEASSERT);
388 return;
389 }
390
391 if (gpio_is_valid(chip->gpio_cs)) {
392 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
393 return;
394 }
395
396 if (is_lpss_ssp(drv_data))
397 lpss_ssp_cs_control(drv_data, false);
398}
399
400int pxa2xx_spi_flush(struct driver_data *drv_data)
401{
402 unsigned long limit = loops_per_jiffy << 1;
403
404 do {
405 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
406 pxa2xx_spi_read(drv_data, SSDR);
407 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
408 write_SSSR_CS(drv_data, SSSR_ROR);
409
410 return limit;
411}
412
413static int null_writer(struct driver_data *drv_data)
414{
415 u8 n_bytes = drv_data->n_bytes;
416
417 if (pxa2xx_spi_txfifo_full(drv_data)
418 || (drv_data->tx == drv_data->tx_end))
419 return 0;
420
421 pxa2xx_spi_write(drv_data, SSDR, 0);
422 drv_data->tx += n_bytes;
423
424 return 1;
425}
426
427static int null_reader(struct driver_data *drv_data)
428{
429 u8 n_bytes = drv_data->n_bytes;
430
431 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
432 && (drv_data->rx < drv_data->rx_end)) {
433 pxa2xx_spi_read(drv_data, SSDR);
434 drv_data->rx += n_bytes;
435 }
436
437 return drv_data->rx == drv_data->rx_end;
438}
439
440static int u8_writer(struct driver_data *drv_data)
441{
442 if (pxa2xx_spi_txfifo_full(drv_data)
443 || (drv_data->tx == drv_data->tx_end))
444 return 0;
445
446 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
447 ++drv_data->tx;
448
449 return 1;
450}
451
452static int u8_reader(struct driver_data *drv_data)
453{
454 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
455 && (drv_data->rx < drv_data->rx_end)) {
456 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
457 ++drv_data->rx;
458 }
459
460 return drv_data->rx == drv_data->rx_end;
461}
462
463static int u16_writer(struct driver_data *drv_data)
464{
465 if (pxa2xx_spi_txfifo_full(drv_data)
466 || (drv_data->tx == drv_data->tx_end))
467 return 0;
468
469 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
470 drv_data->tx += 2;
471
472 return 1;
473}
474
475static int u16_reader(struct driver_data *drv_data)
476{
477 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
478 && (drv_data->rx < drv_data->rx_end)) {
479 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
480 drv_data->rx += 2;
481 }
482
483 return drv_data->rx == drv_data->rx_end;
484}
485
486static int u32_writer(struct driver_data *drv_data)
487{
488 if (pxa2xx_spi_txfifo_full(drv_data)
489 || (drv_data->tx == drv_data->tx_end))
490 return 0;
491
492 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
493 drv_data->tx += 4;
494
495 return 1;
496}
497
498static int u32_reader(struct driver_data *drv_data)
499{
500 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
501 && (drv_data->rx < drv_data->rx_end)) {
502 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
503 drv_data->rx += 4;
504 }
505
506 return drv_data->rx == drv_data->rx_end;
507}
508
509void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
510{
511 struct spi_message *msg = drv_data->cur_msg;
512 struct spi_transfer *trans = drv_data->cur_transfer;
513
514 /* Move to next transfer */
515 if (trans->transfer_list.next != &msg->transfers) {
516 drv_data->cur_transfer =
517 list_entry(trans->transfer_list.next,
518 struct spi_transfer,
519 transfer_list);
520 return RUNNING_STATE;
521 } else
522 return DONE_STATE;
523}
524
525/* caller already set message->status; dma and pio irqs are blocked */
526static void giveback(struct driver_data *drv_data)
527{
528 struct spi_transfer* last_transfer;
529 struct spi_message *msg;
530 unsigned long timeout;
531
532 msg = drv_data->cur_msg;
533 drv_data->cur_msg = NULL;
534 drv_data->cur_transfer = NULL;
535
536 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
537 transfer_list);
538
539 /* Delay if requested before any change in chip select */
540 if (last_transfer->delay_usecs)
541 udelay(last_transfer->delay_usecs);
542
543 /* Wait until SSP becomes idle before deasserting the CS */
544 timeout = jiffies + msecs_to_jiffies(10);
545 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
546 !time_after(jiffies, timeout))
547 cpu_relax();
548
549 /* Drop chip select UNLESS cs_change is true or we are returning
550 * a message with an error, or next message is for another chip
551 */
552 if (!last_transfer->cs_change)
553 cs_deassert(drv_data);
554 else {
555 struct spi_message *next_msg;
556
557 /* Holding of cs was hinted, but we need to make sure
558 * the next message is for the same chip. Don't waste
559 * time with the following tests unless this was hinted.
560 *
561 * We cannot postpone this until pump_messages, because
562 * after calling msg->complete (below) the driver that
563 * sent the current message could be unloaded, which
564 * could invalidate the cs_control() callback...
565 */
566
567 /* get a pointer to the next message, if any */
568 next_msg = spi_get_next_queued_message(drv_data->master);
569
570 /* see if the next and current messages point
571 * to the same chip
572 */
573 if (next_msg && next_msg->spi != msg->spi)
574 next_msg = NULL;
575 if (!next_msg || msg->state == ERROR_STATE)
576 cs_deassert(drv_data);
577 }
578
579 drv_data->cur_chip = NULL;
580 spi_finalize_current_message(drv_data->master);
581}
582
583static void reset_sccr1(struct driver_data *drv_data)
584{
585 struct chip_data *chip = drv_data->cur_chip;
586 u32 sccr1_reg;
587
588 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
589 sccr1_reg &= ~SSCR1_RFT;
590 sccr1_reg |= chip->threshold;
591 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
592}
593
594static void int_error_stop(struct driver_data *drv_data, const char* msg)
595{
596 /* Stop and reset SSP */
597 write_SSSR_CS(drv_data, drv_data->clear_sr);
598 reset_sccr1(drv_data);
599 if (!pxa25x_ssp_comp(drv_data))
600 pxa2xx_spi_write(drv_data, SSTO, 0);
601 pxa2xx_spi_flush(drv_data);
602 pxa2xx_spi_write(drv_data, SSCR0,
603 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
604
605 dev_err(&drv_data->pdev->dev, "%s\n", msg);
606
607 drv_data->cur_msg->state = ERROR_STATE;
608 tasklet_schedule(&drv_data->pump_transfers);
609}
610
611static void int_transfer_complete(struct driver_data *drv_data)
612{
613 /* Clear and disable interrupts */
614 write_SSSR_CS(drv_data, drv_data->clear_sr);
615 reset_sccr1(drv_data);
616 if (!pxa25x_ssp_comp(drv_data))
617 pxa2xx_spi_write(drv_data, SSTO, 0);
618
619 /* Update total byte transferred return count actual bytes read */
620 drv_data->cur_msg->actual_length += drv_data->len -
621 (drv_data->rx_end - drv_data->rx);
622
623 /* Transfer delays and chip select release are
624 * handled in pump_transfers or giveback
625 */
626
627 /* Move to next transfer */
628 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
629
630 /* Schedule transfer tasklet */
631 tasklet_schedule(&drv_data->pump_transfers);
632}
633
634static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
635{
636 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
637 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
638
639 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
640
641 if (irq_status & SSSR_ROR) {
642 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
643 return IRQ_HANDLED;
644 }
645
646 if (irq_status & SSSR_TINT) {
647 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
648 if (drv_data->read(drv_data)) {
649 int_transfer_complete(drv_data);
650 return IRQ_HANDLED;
651 }
652 }
653
654 /* Drain rx fifo, Fill tx fifo and prevent overruns */
655 do {
656 if (drv_data->read(drv_data)) {
657 int_transfer_complete(drv_data);
658 return IRQ_HANDLED;
659 }
660 } while (drv_data->write(drv_data));
661
662 if (drv_data->read(drv_data)) {
663 int_transfer_complete(drv_data);
664 return IRQ_HANDLED;
665 }
666
667 if (drv_data->tx == drv_data->tx_end) {
668 u32 bytes_left;
669 u32 sccr1_reg;
670
671 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
672 sccr1_reg &= ~SSCR1_TIE;
673
674 /*
675 * PXA25x_SSP has no timeout, set up rx threshould for the
676 * remaining RX bytes.
677 */
678 if (pxa25x_ssp_comp(drv_data)) {
679 u32 rx_thre;
680
681 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
682
683 bytes_left = drv_data->rx_end - drv_data->rx;
684 switch (drv_data->n_bytes) {
685 case 4:
686 bytes_left >>= 1;
687 case 2:
688 bytes_left >>= 1;
689 }
690
691 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
692 if (rx_thre > bytes_left)
693 rx_thre = bytes_left;
694
695 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
696 }
697 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
698 }
699
700 /* We did something */
701 return IRQ_HANDLED;
702}
703
704static irqreturn_t ssp_int(int irq, void *dev_id)
705{
706 struct driver_data *drv_data = dev_id;
707 u32 sccr1_reg;
708 u32 mask = drv_data->mask_sr;
709 u32 status;
710
711 /*
712 * The IRQ might be shared with other peripherals so we must first
713 * check that are we RPM suspended or not. If we are we assume that
714 * the IRQ was not for us (we shouldn't be RPM suspended when the
715 * interrupt is enabled).
716 */
717 if (pm_runtime_suspended(&drv_data->pdev->dev))
718 return IRQ_NONE;
719
720 /*
721 * If the device is not yet in RPM suspended state and we get an
722 * interrupt that is meant for another device, check if status bits
723 * are all set to one. That means that the device is already
724 * powered off.
725 */
726 status = pxa2xx_spi_read(drv_data, SSSR);
727 if (status == ~0)
728 return IRQ_NONE;
729
730 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
731
732 /* Ignore possible writes if we don't need to write */
733 if (!(sccr1_reg & SSCR1_TIE))
734 mask &= ~SSSR_TFS;
735
736 /* Ignore RX timeout interrupt if it is disabled */
737 if (!(sccr1_reg & SSCR1_TINTE))
738 mask &= ~SSSR_TINT;
739
740 if (!(status & mask))
741 return IRQ_NONE;
742
743 if (!drv_data->cur_msg) {
744
745 pxa2xx_spi_write(drv_data, SSCR0,
746 pxa2xx_spi_read(drv_data, SSCR0)
747 & ~SSCR0_SSE);
748 pxa2xx_spi_write(drv_data, SSCR1,
749 pxa2xx_spi_read(drv_data, SSCR1)
750 & ~drv_data->int_cr1);
751 if (!pxa25x_ssp_comp(drv_data))
752 pxa2xx_spi_write(drv_data, SSTO, 0);
753 write_SSSR_CS(drv_data, drv_data->clear_sr);
754
755 dev_err(&drv_data->pdev->dev,
756 "bad message state in interrupt handler\n");
757
758 /* Never fail */
759 return IRQ_HANDLED;
760 }
761
762 return drv_data->transfer_handler(drv_data);
763}
764
765/*
766 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
767 * input frequency by fractions of 2^24. It also has a divider by 5.
768 *
769 * There are formulas to get baud rate value for given input frequency and
770 * divider parameters, such as DDS_CLK_RATE and SCR:
771 *
772 * Fsys = 200MHz
773 *
774 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
775 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
776 *
777 * DDS_CLK_RATE either 2^n or 2^n / 5.
778 * SCR is in range 0 .. 255
779 *
780 * Divisor = 5^i * 2^j * 2 * k
781 * i = [0, 1] i = 1 iff j = 0 or j > 3
782 * j = [0, 23] j = 0 iff i = 1
783 * k = [1, 256]
784 * Special case: j = 0, i = 1: Divisor = 2 / 5
785 *
786 * Accordingly to the specification the recommended values for DDS_CLK_RATE
787 * are:
788 * Case 1: 2^n, n = [0, 23]
789 * Case 2: 2^24 * 2 / 5 (0x666666)
790 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
791 *
792 * In all cases the lowest possible value is better.
793 *
794 * The function calculates parameters for all cases and chooses the one closest
795 * to the asked baud rate.
796 */
797static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
798{
799 unsigned long xtal = 200000000;
800 unsigned long fref = xtal / 2; /* mandatory division by 2,
801 see (2) */
802 /* case 3 */
803 unsigned long fref1 = fref / 2; /* case 1 */
804 unsigned long fref2 = fref * 2 / 5; /* case 2 */
805 unsigned long scale;
806 unsigned long q, q1, q2;
807 long r, r1, r2;
808 u32 mul;
809
810 /* Case 1 */
811
812 /* Set initial value for DDS_CLK_RATE */
813 mul = (1 << 24) >> 1;
814
815 /* Calculate initial quot */
816 q1 = DIV_ROUND_UP(fref1, rate);
817
818 /* Scale q1 if it's too big */
819 if (q1 > 256) {
820 /* Scale q1 to range [1, 512] */
821 scale = fls_long(q1 - 1);
822 if (scale > 9) {
823 q1 >>= scale - 9;
824 mul >>= scale - 9;
825 }
826
827 /* Round the result if we have a remainder */
828 q1 += q1 & 1;
829 }
830
831 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
832 scale = __ffs(q1);
833 q1 >>= scale;
834 mul >>= scale;
835
836 /* Get the remainder */
837 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
838
839 /* Case 2 */
840
841 q2 = DIV_ROUND_UP(fref2, rate);
842 r2 = abs(fref2 / q2 - rate);
843
844 /*
845 * Choose the best between two: less remainder we have the better. We
846 * can't go case 2 if q2 is greater than 256 since SCR register can
847 * hold only values 0 .. 255.
848 */
849 if (r2 >= r1 || q2 > 256) {
850 /* case 1 is better */
851 r = r1;
852 q = q1;
853 } else {
854 /* case 2 is better */
855 r = r2;
856 q = q2;
857 mul = (1 << 24) * 2 / 5;
858 }
859
860 /* Check case 3 only if the divisor is big enough */
861 if (fref / rate >= 80) {
862 u64 fssp;
863 u32 m;
864
865 /* Calculate initial quot */
866 q1 = DIV_ROUND_UP(fref, rate);
867 m = (1 << 24) / q1;
868
869 /* Get the remainder */
870 fssp = (u64)fref * m;
871 do_div(fssp, 1 << 24);
872 r1 = abs(fssp - rate);
873
874 /* Choose this one if it suits better */
875 if (r1 < r) {
876 /* case 3 is better */
877 q = 1;
878 mul = m;
879 }
880 }
881
882 *dds = mul;
883 return q - 1;
884}
885
886static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
887{
888 unsigned long ssp_clk = drv_data->master->max_speed_hz;
889 const struct ssp_device *ssp = drv_data->ssp;
890
891 rate = min_t(int, ssp_clk, rate);
892
893 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
894 return (ssp_clk / (2 * rate) - 1) & 0xff;
895 else
896 return (ssp_clk / rate - 1) & 0xfff;
897}
898
899static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
900 int rate)
901{
902 struct chip_data *chip = drv_data->cur_chip;
903 unsigned int clk_div;
904
905 switch (drv_data->ssp_type) {
906 case QUARK_X1000_SSP:
907 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
908 break;
909 default:
910 clk_div = ssp_get_clk_div(drv_data, rate);
911 break;
912 }
913 return clk_div << 8;
914}
915
916static void pump_transfers(unsigned long data)
917{
918 struct driver_data *drv_data = (struct driver_data *)data;
919 struct spi_message *message = NULL;
920 struct spi_transfer *transfer = NULL;
921 struct spi_transfer *previous = NULL;
922 struct chip_data *chip = NULL;
923 u32 clk_div = 0;
924 u8 bits = 0;
925 u32 speed = 0;
926 u32 cr0;
927 u32 cr1;
928 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
929 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
930 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
931
932 /* Get current state information */
933 message = drv_data->cur_msg;
934 transfer = drv_data->cur_transfer;
935 chip = drv_data->cur_chip;
936
937 /* Handle for abort */
938 if (message->state == ERROR_STATE) {
939 message->status = -EIO;
940 giveback(drv_data);
941 return;
942 }
943
944 /* Handle end of message */
945 if (message->state == DONE_STATE) {
946 message->status = 0;
947 giveback(drv_data);
948 return;
949 }
950
951 /* Delay if requested at end of transfer before CS change */
952 if (message->state == RUNNING_STATE) {
953 previous = list_entry(transfer->transfer_list.prev,
954 struct spi_transfer,
955 transfer_list);
956 if (previous->delay_usecs)
957 udelay(previous->delay_usecs);
958
959 /* Drop chip select only if cs_change is requested */
960 if (previous->cs_change)
961 cs_deassert(drv_data);
962 }
963
964 /* Check if we can DMA this transfer */
965 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
966
967 /* reject already-mapped transfers; PIO won't always work */
968 if (message->is_dma_mapped
969 || transfer->rx_dma || transfer->tx_dma) {
970 dev_err(&drv_data->pdev->dev,
971 "pump_transfers: mapped transfer length of "
972 "%u is greater than %d\n",
973 transfer->len, MAX_DMA_LEN);
974 message->status = -EINVAL;
975 giveback(drv_data);
976 return;
977 }
978
979 /* warn ... we force this to PIO mode */
980 dev_warn_ratelimited(&message->spi->dev,
981 "pump_transfers: DMA disabled for transfer length %ld "
982 "greater than %d\n",
983 (long)drv_data->len, MAX_DMA_LEN);
984 }
985
986 /* Setup the transfer state based on the type of transfer */
987 if (pxa2xx_spi_flush(drv_data) == 0) {
988 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
989 message->status = -EIO;
990 giveback(drv_data);
991 return;
992 }
993 drv_data->n_bytes = chip->n_bytes;
994 drv_data->tx = (void *)transfer->tx_buf;
995 drv_data->tx_end = drv_data->tx + transfer->len;
996 drv_data->rx = transfer->rx_buf;
997 drv_data->rx_end = drv_data->rx + transfer->len;
998 drv_data->len = transfer->len;
999 drv_data->write = drv_data->tx ? chip->write : null_writer;
1000 drv_data->read = drv_data->rx ? chip->read : null_reader;
1001
1002 /* Change speed and bit per word on a per transfer */
1003 bits = transfer->bits_per_word;
1004 speed = transfer->speed_hz;
1005
1006 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1007
1008 if (bits <= 8) {
1009 drv_data->n_bytes = 1;
1010 drv_data->read = drv_data->read != null_reader ?
1011 u8_reader : null_reader;
1012 drv_data->write = drv_data->write != null_writer ?
1013 u8_writer : null_writer;
1014 } else if (bits <= 16) {
1015 drv_data->n_bytes = 2;
1016 drv_data->read = drv_data->read != null_reader ?
1017 u16_reader : null_reader;
1018 drv_data->write = drv_data->write != null_writer ?
1019 u16_writer : null_writer;
1020 } else if (bits <= 32) {
1021 drv_data->n_bytes = 4;
1022 drv_data->read = drv_data->read != null_reader ?
1023 u32_reader : null_reader;
1024 drv_data->write = drv_data->write != null_writer ?
1025 u32_writer : null_writer;
1026 }
1027 /*
1028 * if bits/word is changed in dma mode, then must check the
1029 * thresholds and burst also
1030 */
1031 if (chip->enable_dma) {
1032 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1033 message->spi,
1034 bits, &dma_burst,
1035 &dma_thresh))
1036 dev_warn_ratelimited(&message->spi->dev,
1037 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1038 }
1039
1040 message->state = RUNNING_STATE;
1041
1042 drv_data->dma_mapped = 0;
1043 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1044 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1045 if (drv_data->dma_mapped) {
1046
1047 /* Ensure we have the correct interrupt handler */
1048 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1049
1050 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1051
1052 /* Clear status and start DMA engine */
1053 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1054 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1055
1056 pxa2xx_spi_dma_start(drv_data);
1057 } else {
1058 /* Ensure we have the correct interrupt handler */
1059 drv_data->transfer_handler = interrupt_transfer;
1060
1061 /* Clear status */
1062 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1063 write_SSSR_CS(drv_data, drv_data->clear_sr);
1064 }
1065
1066 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1067 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1068 if (!pxa25x_ssp_comp(drv_data))
1069 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1070 drv_data->master->max_speed_hz
1071 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1072 drv_data->dma_mapped ? "DMA" : "PIO");
1073 else
1074 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1075 drv_data->master->max_speed_hz / 2
1076 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1077 drv_data->dma_mapped ? "DMA" : "PIO");
1078
1079 if (is_lpss_ssp(drv_data)) {
1080 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1081 != chip->lpss_rx_threshold)
1082 pxa2xx_spi_write(drv_data, SSIRF,
1083 chip->lpss_rx_threshold);
1084 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1085 != chip->lpss_tx_threshold)
1086 pxa2xx_spi_write(drv_data, SSITF,
1087 chip->lpss_tx_threshold);
1088 }
1089
1090 if (is_quark_x1000_ssp(drv_data) &&
1091 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1092 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1093
1094 /* see if we need to reload the config registers */
1095 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1096 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1097 != (cr1 & change_mask)) {
1098 /* stop the SSP, and update the other bits */
1099 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1100 if (!pxa25x_ssp_comp(drv_data))
1101 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1102 /* first set CR1 without interrupt and service enables */
1103 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1104 /* restart the SSP */
1105 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1106
1107 } else {
1108 if (!pxa25x_ssp_comp(drv_data))
1109 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1110 }
1111
1112 cs_assert(drv_data);
1113
1114 /* after chip select, release the data by enabling service
1115 * requests and interrupts, without changing any mode bits */
1116 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1117}
1118
1119static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1120 struct spi_message *msg)
1121{
1122 struct driver_data *drv_data = spi_master_get_devdata(master);
1123
1124 drv_data->cur_msg = msg;
1125 /* Initial message state*/
1126 drv_data->cur_msg->state = START_STATE;
1127 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1128 struct spi_transfer,
1129 transfer_list);
1130
1131 /* prepare to setup the SSP, in pump_transfers, using the per
1132 * chip configuration */
1133 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1134
1135 /* Mark as busy and launch transfers */
1136 tasklet_schedule(&drv_data->pump_transfers);
1137 return 0;
1138}
1139
1140static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1141{
1142 struct driver_data *drv_data = spi_master_get_devdata(master);
1143
1144 /* Disable the SSP now */
1145 pxa2xx_spi_write(drv_data, SSCR0,
1146 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1147
1148 return 0;
1149}
1150
1151static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1152 struct pxa2xx_spi_chip *chip_info)
1153{
1154 int err = 0;
1155
1156 if (chip == NULL || chip_info == NULL)
1157 return 0;
1158
1159 /* NOTE: setup() can be called multiple times, possibly with
1160 * different chip_info, release previously requested GPIO
1161 */
1162 if (gpio_is_valid(chip->gpio_cs))
1163 gpio_free(chip->gpio_cs);
1164
1165 /* If (*cs_control) is provided, ignore GPIO chip select */
1166 if (chip_info->cs_control) {
1167 chip->cs_control = chip_info->cs_control;
1168 return 0;
1169 }
1170
1171 if (gpio_is_valid(chip_info->gpio_cs)) {
1172 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1173 if (err) {
1174 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1175 chip_info->gpio_cs);
1176 return err;
1177 }
1178
1179 chip->gpio_cs = chip_info->gpio_cs;
1180 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1181
1182 err = gpio_direction_output(chip->gpio_cs,
1183 !chip->gpio_cs_inverted);
1184 }
1185
1186 return err;
1187}
1188
1189static int setup(struct spi_device *spi)
1190{
1191 struct pxa2xx_spi_chip *chip_info = NULL;
1192 struct chip_data *chip;
1193 const struct lpss_config *config;
1194 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1195 uint tx_thres, tx_hi_thres, rx_thres;
1196
1197 switch (drv_data->ssp_type) {
1198 case QUARK_X1000_SSP:
1199 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1200 tx_hi_thres = 0;
1201 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1202 break;
1203 case LPSS_LPT_SSP:
1204 case LPSS_BYT_SSP:
1205 case LPSS_BSW_SSP:
1206 case LPSS_SPT_SSP:
1207 case LPSS_BXT_SSP:
1208 config = lpss_get_config(drv_data);
1209 tx_thres = config->tx_threshold_lo;
1210 tx_hi_thres = config->tx_threshold_hi;
1211 rx_thres = config->rx_threshold;
1212 break;
1213 default:
1214 tx_thres = TX_THRESH_DFLT;
1215 tx_hi_thres = 0;
1216 rx_thres = RX_THRESH_DFLT;
1217 break;
1218 }
1219
1220 /* Only alloc on first setup */
1221 chip = spi_get_ctldata(spi);
1222 if (!chip) {
1223 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1224 if (!chip)
1225 return -ENOMEM;
1226
1227 if (drv_data->ssp_type == CE4100_SSP) {
1228 if (spi->chip_select > 4) {
1229 dev_err(&spi->dev,
1230 "failed setup: cs number must not be > 4.\n");
1231 kfree(chip);
1232 return -EINVAL;
1233 }
1234
1235 chip->frm = spi->chip_select;
1236 } else
1237 chip->gpio_cs = -1;
1238 chip->enable_dma = 0;
1239 chip->timeout = TIMOUT_DFLT;
1240 }
1241
1242 /* protocol drivers may change the chip settings, so...
1243 * if chip_info exists, use it */
1244 chip_info = spi->controller_data;
1245
1246 /* chip_info isn't always needed */
1247 chip->cr1 = 0;
1248 if (chip_info) {
1249 if (chip_info->timeout)
1250 chip->timeout = chip_info->timeout;
1251 if (chip_info->tx_threshold)
1252 tx_thres = chip_info->tx_threshold;
1253 if (chip_info->tx_hi_threshold)
1254 tx_hi_thres = chip_info->tx_hi_threshold;
1255 if (chip_info->rx_threshold)
1256 rx_thres = chip_info->rx_threshold;
1257 chip->enable_dma = drv_data->master_info->enable_dma;
1258 chip->dma_threshold = 0;
1259 if (chip_info->enable_loopback)
1260 chip->cr1 = SSCR1_LBM;
1261 } else if (ACPI_HANDLE(&spi->dev)) {
1262 /*
1263 * Slave devices enumerated from ACPI namespace don't
1264 * usually have chip_info but we still might want to use
1265 * DMA with them.
1266 */
1267 chip->enable_dma = drv_data->master_info->enable_dma;
1268 }
1269
1270 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1271 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1272 | SSITF_TxHiThresh(tx_hi_thres);
1273
1274 /* set dma burst and threshold outside of chip_info path so that if
1275 * chip_info goes away after setting chip->enable_dma, the
1276 * burst and threshold can still respond to changes in bits_per_word */
1277 if (chip->enable_dma) {
1278 /* set up legal burst and threshold for dma */
1279 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1280 spi->bits_per_word,
1281 &chip->dma_burst_size,
1282 &chip->dma_threshold)) {
1283 dev_warn(&spi->dev,
1284 "in setup: DMA burst size reduced to match bits_per_word\n");
1285 }
1286 }
1287
1288 switch (drv_data->ssp_type) {
1289 case QUARK_X1000_SSP:
1290 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1291 & QUARK_X1000_SSCR1_RFT)
1292 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1293 & QUARK_X1000_SSCR1_TFT);
1294 break;
1295 default:
1296 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1297 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1298 break;
1299 }
1300
1301 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1302 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1303 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1304
1305 if (spi->mode & SPI_LOOP)
1306 chip->cr1 |= SSCR1_LBM;
1307
1308 if (spi->bits_per_word <= 8) {
1309 chip->n_bytes = 1;
1310 chip->read = u8_reader;
1311 chip->write = u8_writer;
1312 } else if (spi->bits_per_word <= 16) {
1313 chip->n_bytes = 2;
1314 chip->read = u16_reader;
1315 chip->write = u16_writer;
1316 } else if (spi->bits_per_word <= 32) {
1317 chip->n_bytes = 4;
1318 chip->read = u32_reader;
1319 chip->write = u32_writer;
1320 }
1321
1322 spi_set_ctldata(spi, chip);
1323
1324 if (drv_data->ssp_type == CE4100_SSP)
1325 return 0;
1326
1327 return setup_cs(spi, chip, chip_info);
1328}
1329
1330static void cleanup(struct spi_device *spi)
1331{
1332 struct chip_data *chip = spi_get_ctldata(spi);
1333 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1334
1335 if (!chip)
1336 return;
1337
1338 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1339 gpio_free(chip->gpio_cs);
1340
1341 kfree(chip);
1342}
1343
1344#ifdef CONFIG_PCI
1345#ifdef CONFIG_ACPI
1346
1347static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1348 { "INT33C0", LPSS_LPT_SSP },
1349 { "INT33C1", LPSS_LPT_SSP },
1350 { "INT3430", LPSS_LPT_SSP },
1351 { "INT3431", LPSS_LPT_SSP },
1352 { "80860F0E", LPSS_BYT_SSP },
1353 { "8086228E", LPSS_BSW_SSP },
1354 { },
1355};
1356MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1357
1358static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1359{
1360 unsigned int devid;
1361 int port_id = -1;
1362
1363 if (adev && adev->pnp.unique_id &&
1364 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1365 port_id = devid;
1366 return port_id;
1367}
1368#else /* !CONFIG_ACPI */
1369static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1370{
1371 return -1;
1372}
1373#endif
1374
1375/*
1376 * PCI IDs of compound devices that integrate both host controller and private
1377 * integrated DMA engine. Please note these are not used in module
1378 * autoloading and probing in this module but matching the LPSS SSP type.
1379 */
1380static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1381 /* SPT-LP */
1382 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1383 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1384 /* SPT-H */
1385 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1386 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1387 /* BXT A-Step */
1388 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1389 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1390 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1391 /* BXT B-Step */
1392 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1393 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1394 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1395 /* APL */
1396 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1397 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1398 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1399 { },
1400};
1401
1402static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1403{
1404 struct device *dev = param;
1405
1406 if (dev != chan->device->dev->parent)
1407 return false;
1408
1409 return true;
1410}
1411
1412static struct pxa2xx_spi_master *
1413pxa2xx_spi_init_pdata(struct platform_device *pdev)
1414{
1415 struct pxa2xx_spi_master *pdata;
1416 struct acpi_device *adev;
1417 struct ssp_device *ssp;
1418 struct resource *res;
1419 const struct acpi_device_id *adev_id = NULL;
1420 const struct pci_device_id *pcidev_id = NULL;
1421 int type;
1422
1423 adev = ACPI_COMPANION(&pdev->dev);
1424
1425 if (dev_is_pci(pdev->dev.parent))
1426 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1427 to_pci_dev(pdev->dev.parent));
1428 else if (adev)
1429 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1430 &pdev->dev);
1431 else
1432 return NULL;
1433
1434 if (adev_id)
1435 type = (int)adev_id->driver_data;
1436 else if (pcidev_id)
1437 type = (int)pcidev_id->driver_data;
1438 else
1439 return NULL;
1440
1441 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1442 if (!pdata)
1443 return NULL;
1444
1445 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1446 if (!res)
1447 return NULL;
1448
1449 ssp = &pdata->ssp;
1450
1451 ssp->phys_base = res->start;
1452 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1453 if (IS_ERR(ssp->mmio_base))
1454 return NULL;
1455
1456 if (pcidev_id) {
1457 pdata->tx_param = pdev->dev.parent;
1458 pdata->rx_param = pdev->dev.parent;
1459 pdata->dma_filter = pxa2xx_spi_idma_filter;
1460 }
1461
1462 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1463 ssp->irq = platform_get_irq(pdev, 0);
1464 ssp->type = type;
1465 ssp->pdev = pdev;
1466 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1467
1468 pdata->num_chipselect = 1;
1469 pdata->enable_dma = true;
1470
1471 return pdata;
1472}
1473
1474#else /* !CONFIG_PCI */
1475static inline struct pxa2xx_spi_master *
1476pxa2xx_spi_init_pdata(struct platform_device *pdev)
1477{
1478 return NULL;
1479}
1480#endif
1481
1482static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1483{
1484 struct driver_data *drv_data = spi_master_get_devdata(master);
1485
1486 if (has_acpi_companion(&drv_data->pdev->dev)) {
1487 switch (drv_data->ssp_type) {
1488 /*
1489 * For Atoms the ACPI DeviceSelection used by the Windows
1490 * driver starts from 1 instead of 0 so translate it here
1491 * to match what Linux expects.
1492 */
1493 case LPSS_BYT_SSP:
1494 case LPSS_BSW_SSP:
1495 return cs - 1;
1496
1497 default:
1498 break;
1499 }
1500 }
1501
1502 return cs;
1503}
1504
1505static int pxa2xx_spi_probe(struct platform_device *pdev)
1506{
1507 struct device *dev = &pdev->dev;
1508 struct pxa2xx_spi_master *platform_info;
1509 struct spi_master *master;
1510 struct driver_data *drv_data;
1511 struct ssp_device *ssp;
1512 const struct lpss_config *config;
1513 int status;
1514 u32 tmp;
1515
1516 platform_info = dev_get_platdata(dev);
1517 if (!platform_info) {
1518 platform_info = pxa2xx_spi_init_pdata(pdev);
1519 if (!platform_info) {
1520 dev_err(&pdev->dev, "missing platform data\n");
1521 return -ENODEV;
1522 }
1523 }
1524
1525 ssp = pxa_ssp_request(pdev->id, pdev->name);
1526 if (!ssp)
1527 ssp = &platform_info->ssp;
1528
1529 if (!ssp->mmio_base) {
1530 dev_err(&pdev->dev, "failed to get ssp\n");
1531 return -ENODEV;
1532 }
1533
1534 master = spi_alloc_master(dev, sizeof(struct driver_data));
1535 if (!master) {
1536 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1537 pxa_ssp_free(ssp);
1538 return -ENOMEM;
1539 }
1540 drv_data = spi_master_get_devdata(master);
1541 drv_data->master = master;
1542 drv_data->master_info = platform_info;
1543 drv_data->pdev = pdev;
1544 drv_data->ssp = ssp;
1545
1546 master->dev.parent = &pdev->dev;
1547 master->dev.of_node = pdev->dev.of_node;
1548 /* the spi->mode bits understood by this driver: */
1549 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1550
1551 master->bus_num = ssp->port_id;
1552 master->dma_alignment = DMA_ALIGNMENT;
1553 master->cleanup = cleanup;
1554 master->setup = setup;
1555 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1556 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1557 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1558 master->auto_runtime_pm = true;
1559
1560 drv_data->ssp_type = ssp->type;
1561
1562 drv_data->ioaddr = ssp->mmio_base;
1563 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1564 if (pxa25x_ssp_comp(drv_data)) {
1565 switch (drv_data->ssp_type) {
1566 case QUARK_X1000_SSP:
1567 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1568 break;
1569 default:
1570 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1571 break;
1572 }
1573
1574 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1575 drv_data->dma_cr1 = 0;
1576 drv_data->clear_sr = SSSR_ROR;
1577 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1578 } else {
1579 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1580 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1581 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1582 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1583 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1584 }
1585
1586 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1587 drv_data);
1588 if (status < 0) {
1589 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1590 goto out_error_master_alloc;
1591 }
1592
1593 /* Setup DMA if requested */
1594 if (platform_info->enable_dma) {
1595 status = pxa2xx_spi_dma_setup(drv_data);
1596 if (status) {
1597 dev_dbg(dev, "no DMA channels available, using PIO\n");
1598 platform_info->enable_dma = false;
1599 }
1600 }
1601
1602 /* Enable SOC clock */
1603 clk_prepare_enable(ssp->clk);
1604
1605 master->max_speed_hz = clk_get_rate(ssp->clk);
1606
1607 /* Load default SSP configuration */
1608 pxa2xx_spi_write(drv_data, SSCR0, 0);
1609 switch (drv_data->ssp_type) {
1610 case QUARK_X1000_SSP:
1611 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1612 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1613 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1614
1615 /* using the Motorola SPI protocol and use 8 bit frame */
1616 pxa2xx_spi_write(drv_data, SSCR0,
1617 QUARK_X1000_SSCR0_Motorola
1618 | QUARK_X1000_SSCR0_DataSize(8));
1619 break;
1620 default:
1621 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1622 SSCR1_TxTresh(TX_THRESH_DFLT);
1623 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1624 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1625 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1626 break;
1627 }
1628
1629 if (!pxa25x_ssp_comp(drv_data))
1630 pxa2xx_spi_write(drv_data, SSTO, 0);
1631
1632 if (!is_quark_x1000_ssp(drv_data))
1633 pxa2xx_spi_write(drv_data, SSPSP, 0);
1634
1635 if (is_lpss_ssp(drv_data)) {
1636 lpss_ssp_setup(drv_data);
1637 config = lpss_get_config(drv_data);
1638 if (config->reg_capabilities >= 0) {
1639 tmp = __lpss_ssp_read_priv(drv_data,
1640 config->reg_capabilities);
1641 tmp &= LPSS_CAPS_CS_EN_MASK;
1642 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1643 platform_info->num_chipselect = ffz(tmp);
1644 } else if (config->cs_num) {
1645 platform_info->num_chipselect = config->cs_num;
1646 }
1647 }
1648 master->num_chipselect = platform_info->num_chipselect;
1649
1650 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1651 (unsigned long)drv_data);
1652
1653 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1654 pm_runtime_use_autosuspend(&pdev->dev);
1655 pm_runtime_set_active(&pdev->dev);
1656 pm_runtime_enable(&pdev->dev);
1657
1658 /* Register with the SPI framework */
1659 platform_set_drvdata(pdev, drv_data);
1660 status = devm_spi_register_master(&pdev->dev, master);
1661 if (status != 0) {
1662 dev_err(&pdev->dev, "problem registering spi master\n");
1663 goto out_error_clock_enabled;
1664 }
1665
1666 return status;
1667
1668out_error_clock_enabled:
1669 clk_disable_unprepare(ssp->clk);
1670 pxa2xx_spi_dma_release(drv_data);
1671 free_irq(ssp->irq, drv_data);
1672
1673out_error_master_alloc:
1674 spi_master_put(master);
1675 pxa_ssp_free(ssp);
1676 return status;
1677}
1678
1679static int pxa2xx_spi_remove(struct platform_device *pdev)
1680{
1681 struct driver_data *drv_data = platform_get_drvdata(pdev);
1682 struct ssp_device *ssp;
1683
1684 if (!drv_data)
1685 return 0;
1686 ssp = drv_data->ssp;
1687
1688 pm_runtime_get_sync(&pdev->dev);
1689
1690 /* Disable the SSP at the peripheral and SOC level */
1691 pxa2xx_spi_write(drv_data, SSCR0, 0);
1692 clk_disable_unprepare(ssp->clk);
1693
1694 /* Release DMA */
1695 if (drv_data->master_info->enable_dma)
1696 pxa2xx_spi_dma_release(drv_data);
1697
1698 pm_runtime_put_noidle(&pdev->dev);
1699 pm_runtime_disable(&pdev->dev);
1700
1701 /* Release IRQ */
1702 free_irq(ssp->irq, drv_data);
1703
1704 /* Release SSP */
1705 pxa_ssp_free(ssp);
1706
1707 return 0;
1708}
1709
1710static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1711{
1712 int status = 0;
1713
1714 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1715 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1716}
1717
1718#ifdef CONFIG_PM_SLEEP
1719static int pxa2xx_spi_suspend(struct device *dev)
1720{
1721 struct driver_data *drv_data = dev_get_drvdata(dev);
1722 struct ssp_device *ssp = drv_data->ssp;
1723 int status = 0;
1724
1725 status = spi_master_suspend(drv_data->master);
1726 if (status != 0)
1727 return status;
1728 pxa2xx_spi_write(drv_data, SSCR0, 0);
1729
1730 if (!pm_runtime_suspended(dev))
1731 clk_disable_unprepare(ssp->clk);
1732
1733 return 0;
1734}
1735
1736static int pxa2xx_spi_resume(struct device *dev)
1737{
1738 struct driver_data *drv_data = dev_get_drvdata(dev);
1739 struct ssp_device *ssp = drv_data->ssp;
1740 int status = 0;
1741
1742 /* Enable the SSP clock */
1743 if (!pm_runtime_suspended(dev))
1744 clk_prepare_enable(ssp->clk);
1745
1746 /* Restore LPSS private register bits */
1747 if (is_lpss_ssp(drv_data))
1748 lpss_ssp_setup(drv_data);
1749
1750 /* Start the queue running */
1751 status = spi_master_resume(drv_data->master);
1752 if (status != 0) {
1753 dev_err(dev, "problem starting queue (%d)\n", status);
1754 return status;
1755 }
1756
1757 return 0;
1758}
1759#endif
1760
1761#ifdef CONFIG_PM
1762static int pxa2xx_spi_runtime_suspend(struct device *dev)
1763{
1764 struct driver_data *drv_data = dev_get_drvdata(dev);
1765
1766 clk_disable_unprepare(drv_data->ssp->clk);
1767 return 0;
1768}
1769
1770static int pxa2xx_spi_runtime_resume(struct device *dev)
1771{
1772 struct driver_data *drv_data = dev_get_drvdata(dev);
1773
1774 clk_prepare_enable(drv_data->ssp->clk);
1775 return 0;
1776}
1777#endif
1778
1779static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1780 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1781 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1782 pxa2xx_spi_runtime_resume, NULL)
1783};
1784
1785static struct platform_driver driver = {
1786 .driver = {
1787 .name = "pxa2xx-spi",
1788 .pm = &pxa2xx_spi_pm_ops,
1789 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1790 },
1791 .probe = pxa2xx_spi_probe,
1792 .remove = pxa2xx_spi_remove,
1793 .shutdown = pxa2xx_spi_shutdown,
1794};
1795
1796static int __init pxa2xx_spi_init(void)
1797{
1798 return platform_driver_register(&driver);
1799}
1800subsys_initcall(pxa2xx_spi_init);
1801
1802static void __exit pxa2xx_spi_exit(void)
1803{
1804 platform_driver_unregister(&driver);
1805}
1806module_exit(pxa2xx_spi_exit);