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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#define pr_fmt(fmt) "SVM: " fmt
19
20#include <linux/kvm_host.h>
21
22#include "irq.h"
23#include "mmu.h"
24#include "kvm_cache_regs.h"
25#include "x86.h"
26#include "cpuid.h"
27#include "pmu.h"
28
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/kernel.h>
32#include <linux/vmalloc.h>
33#include <linux/highmem.h>
34#include <linux/sched.h>
35#include <linux/trace_events.h>
36#include <linux/slab.h>
37#include <linux/amd-iommu.h>
38#include <linux/hashtable.h>
39
40#include <asm/apic.h>
41#include <asm/perf_event.h>
42#include <asm/tlbflush.h>
43#include <asm/desc.h>
44#include <asm/debugreg.h>
45#include <asm/kvm_para.h>
46#include <asm/irq_remapping.h>
47
48#include <asm/virtext.h>
49#include "trace.h"
50
51#define __ex(x) __kvm_handle_fault_on_reboot(x)
52
53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
56static const struct x86_cpu_id svm_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_SVM),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
61
62#define IOPM_ALLOC_ORDER 2
63#define MSRPM_ALLOC_ORDER 1
64
65#define SEG_TYPE_LDT 2
66#define SEG_TYPE_BUSY_TSS16 3
67
68#define SVM_FEATURE_NPT (1 << 0)
69#define SVM_FEATURE_LBRV (1 << 1)
70#define SVM_FEATURE_SVML (1 << 2)
71#define SVM_FEATURE_NRIP (1 << 3)
72#define SVM_FEATURE_TSC_RATE (1 << 4)
73#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
74#define SVM_FEATURE_FLUSH_ASID (1 << 6)
75#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
76#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
77
78#define SVM_AVIC_DOORBELL 0xc001011b
79
80#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
81#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
82#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
83
84#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
85
86#define TSC_RATIO_RSVD 0xffffff0000000000ULL
87#define TSC_RATIO_MIN 0x0000000000000001ULL
88#define TSC_RATIO_MAX 0x000000ffffffffffULL
89
90#define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
91
92/*
93 * 0xff is broadcast, so the max index allowed for physical APIC ID
94 * table is 0xfe. APIC IDs above 0xff are reserved.
95 */
96#define AVIC_MAX_PHYSICAL_ID_COUNT 255
97
98#define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
99#define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
100#define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
101
102/* AVIC GATAG is encoded using VM and VCPU IDs */
103#define AVIC_VCPU_ID_BITS 8
104#define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
105
106#define AVIC_VM_ID_BITS 24
107#define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
108#define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
109
110#define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
111 (y & AVIC_VCPU_ID_MASK))
112#define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
113#define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
114
115static bool erratum_383_found __read_mostly;
116
117static const u32 host_save_user_msrs[] = {
118#ifdef CONFIG_X86_64
119 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
120 MSR_FS_BASE,
121#endif
122 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
123 MSR_TSC_AUX,
124};
125
126#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
127
128struct kvm_vcpu;
129
130struct nested_state {
131 struct vmcb *hsave;
132 u64 hsave_msr;
133 u64 vm_cr_msr;
134 u64 vmcb;
135
136 /* These are the merged vectors */
137 u32 *msrpm;
138
139 /* gpa pointers to the real vectors */
140 u64 vmcb_msrpm;
141 u64 vmcb_iopm;
142
143 /* A VMEXIT is required but not yet emulated */
144 bool exit_required;
145
146 /* cache for intercepts of the guest */
147 u32 intercept_cr;
148 u32 intercept_dr;
149 u32 intercept_exceptions;
150 u64 intercept;
151
152 /* Nested Paging related state */
153 u64 nested_cr3;
154};
155
156#define MSRPM_OFFSETS 16
157static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
158
159/*
160 * Set osvw_len to higher value when updated Revision Guides
161 * are published and we know what the new status bits are
162 */
163static uint64_t osvw_len = 4, osvw_status;
164
165struct vcpu_svm {
166 struct kvm_vcpu vcpu;
167 struct vmcb *vmcb;
168 unsigned long vmcb_pa;
169 struct svm_cpu_data *svm_data;
170 uint64_t asid_generation;
171 uint64_t sysenter_esp;
172 uint64_t sysenter_eip;
173 uint64_t tsc_aux;
174
175 u64 next_rip;
176
177 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
178 struct {
179 u16 fs;
180 u16 gs;
181 u16 ldt;
182 u64 gs_base;
183 } host;
184
185 u32 *msrpm;
186
187 ulong nmi_iret_rip;
188
189 struct nested_state nested;
190
191 bool nmi_singlestep;
192
193 unsigned int3_injected;
194 unsigned long int3_rip;
195 u32 apf_reason;
196
197 /* cached guest cpuid flags for faster access */
198 bool nrips_enabled : 1;
199
200 u32 ldr_reg;
201 struct page *avic_backing_page;
202 u64 *avic_physical_id_cache;
203 bool avic_is_running;
204
205 /*
206 * Per-vcpu list of struct amd_svm_iommu_ir:
207 * This is used mainly to store interrupt remapping information used
208 * when update the vcpu affinity. This avoids the need to scan for
209 * IRTE and try to match ga_tag in the IOMMU driver.
210 */
211 struct list_head ir_list;
212 spinlock_t ir_list_lock;
213};
214
215/*
216 * This is a wrapper of struct amd_iommu_ir_data.
217 */
218struct amd_svm_iommu_ir {
219 struct list_head node; /* Used by SVM for per-vcpu ir_list */
220 void *data; /* Storing pointer to struct amd_ir_data */
221};
222
223#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
224#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
225
226#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
227#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
228#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
229#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
230
231static DEFINE_PER_CPU(u64, current_tsc_ratio);
232#define TSC_RATIO_DEFAULT 0x0100000000ULL
233
234#define MSR_INVALID 0xffffffffU
235
236static const struct svm_direct_access_msrs {
237 u32 index; /* Index of the MSR */
238 bool always; /* True if intercept is always on */
239} direct_access_msrs[] = {
240 { .index = MSR_STAR, .always = true },
241 { .index = MSR_IA32_SYSENTER_CS, .always = true },
242#ifdef CONFIG_X86_64
243 { .index = MSR_GS_BASE, .always = true },
244 { .index = MSR_FS_BASE, .always = true },
245 { .index = MSR_KERNEL_GS_BASE, .always = true },
246 { .index = MSR_LSTAR, .always = true },
247 { .index = MSR_CSTAR, .always = true },
248 { .index = MSR_SYSCALL_MASK, .always = true },
249#endif
250 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
251 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
252 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
253 { .index = MSR_IA32_LASTINTTOIP, .always = false },
254 { .index = MSR_INVALID, .always = false },
255};
256
257/* enable NPT for AMD64 and X86 with PAE */
258#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
259static bool npt_enabled = true;
260#else
261static bool npt_enabled;
262#endif
263
264/* allow nested paging (virtualized MMU) for all guests */
265static int npt = true;
266module_param(npt, int, S_IRUGO);
267
268/* allow nested virtualization in KVM/SVM */
269static int nested = true;
270module_param(nested, int, S_IRUGO);
271
272/* enable / disable AVIC */
273static int avic;
274#ifdef CONFIG_X86_LOCAL_APIC
275module_param(avic, int, S_IRUGO);
276#endif
277
278/* AVIC VM ID bit masks and lock */
279static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
280static DEFINE_SPINLOCK(avic_vm_id_lock);
281
282static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
283static void svm_flush_tlb(struct kvm_vcpu *vcpu);
284static void svm_complete_interrupts(struct vcpu_svm *svm);
285
286static int nested_svm_exit_handled(struct vcpu_svm *svm);
287static int nested_svm_intercept(struct vcpu_svm *svm);
288static int nested_svm_vmexit(struct vcpu_svm *svm);
289static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
290 bool has_error_code, u32 error_code);
291
292enum {
293 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
294 pause filter count */
295 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
296 VMCB_ASID, /* ASID */
297 VMCB_INTR, /* int_ctl, int_vector */
298 VMCB_NPT, /* npt_en, nCR3, gPAT */
299 VMCB_CR, /* CR0, CR3, CR4, EFER */
300 VMCB_DR, /* DR6, DR7 */
301 VMCB_DT, /* GDT, IDT */
302 VMCB_SEG, /* CS, DS, SS, ES, CPL */
303 VMCB_CR2, /* CR2 only */
304 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
305 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
306 * AVIC PHYSICAL_TABLE pointer,
307 * AVIC LOGICAL_TABLE pointer
308 */
309 VMCB_DIRTY_MAX,
310};
311
312/* TPR and CR2 are always written before VMRUN */
313#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
314
315#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
316
317static inline void mark_all_dirty(struct vmcb *vmcb)
318{
319 vmcb->control.clean = 0;
320}
321
322static inline void mark_all_clean(struct vmcb *vmcb)
323{
324 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
325 & ~VMCB_ALWAYS_DIRTY_MASK;
326}
327
328static inline void mark_dirty(struct vmcb *vmcb, int bit)
329{
330 vmcb->control.clean &= ~(1 << bit);
331}
332
333static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
334{
335 return container_of(vcpu, struct vcpu_svm, vcpu);
336}
337
338static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
339{
340 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
341 mark_dirty(svm->vmcb, VMCB_AVIC);
342}
343
344static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
345{
346 struct vcpu_svm *svm = to_svm(vcpu);
347 u64 *entry = svm->avic_physical_id_cache;
348
349 if (!entry)
350 return false;
351
352 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
353}
354
355static void recalc_intercepts(struct vcpu_svm *svm)
356{
357 struct vmcb_control_area *c, *h;
358 struct nested_state *g;
359
360 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
361
362 if (!is_guest_mode(&svm->vcpu))
363 return;
364
365 c = &svm->vmcb->control;
366 h = &svm->nested.hsave->control;
367 g = &svm->nested;
368
369 c->intercept_cr = h->intercept_cr | g->intercept_cr;
370 c->intercept_dr = h->intercept_dr | g->intercept_dr;
371 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
372 c->intercept = h->intercept | g->intercept;
373}
374
375static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
376{
377 if (is_guest_mode(&svm->vcpu))
378 return svm->nested.hsave;
379 else
380 return svm->vmcb;
381}
382
383static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
384{
385 struct vmcb *vmcb = get_host_vmcb(svm);
386
387 vmcb->control.intercept_cr |= (1U << bit);
388
389 recalc_intercepts(svm);
390}
391
392static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
393{
394 struct vmcb *vmcb = get_host_vmcb(svm);
395
396 vmcb->control.intercept_cr &= ~(1U << bit);
397
398 recalc_intercepts(svm);
399}
400
401static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
402{
403 struct vmcb *vmcb = get_host_vmcb(svm);
404
405 return vmcb->control.intercept_cr & (1U << bit);
406}
407
408static inline void set_dr_intercepts(struct vcpu_svm *svm)
409{
410 struct vmcb *vmcb = get_host_vmcb(svm);
411
412 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
413 | (1 << INTERCEPT_DR1_READ)
414 | (1 << INTERCEPT_DR2_READ)
415 | (1 << INTERCEPT_DR3_READ)
416 | (1 << INTERCEPT_DR4_READ)
417 | (1 << INTERCEPT_DR5_READ)
418 | (1 << INTERCEPT_DR6_READ)
419 | (1 << INTERCEPT_DR7_READ)
420 | (1 << INTERCEPT_DR0_WRITE)
421 | (1 << INTERCEPT_DR1_WRITE)
422 | (1 << INTERCEPT_DR2_WRITE)
423 | (1 << INTERCEPT_DR3_WRITE)
424 | (1 << INTERCEPT_DR4_WRITE)
425 | (1 << INTERCEPT_DR5_WRITE)
426 | (1 << INTERCEPT_DR6_WRITE)
427 | (1 << INTERCEPT_DR7_WRITE);
428
429 recalc_intercepts(svm);
430}
431
432static inline void clr_dr_intercepts(struct vcpu_svm *svm)
433{
434 struct vmcb *vmcb = get_host_vmcb(svm);
435
436 vmcb->control.intercept_dr = 0;
437
438 recalc_intercepts(svm);
439}
440
441static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
442{
443 struct vmcb *vmcb = get_host_vmcb(svm);
444
445 vmcb->control.intercept_exceptions |= (1U << bit);
446
447 recalc_intercepts(svm);
448}
449
450static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
451{
452 struct vmcb *vmcb = get_host_vmcb(svm);
453
454 vmcb->control.intercept_exceptions &= ~(1U << bit);
455
456 recalc_intercepts(svm);
457}
458
459static inline void set_intercept(struct vcpu_svm *svm, int bit)
460{
461 struct vmcb *vmcb = get_host_vmcb(svm);
462
463 vmcb->control.intercept |= (1ULL << bit);
464
465 recalc_intercepts(svm);
466}
467
468static inline void clr_intercept(struct vcpu_svm *svm, int bit)
469{
470 struct vmcb *vmcb = get_host_vmcb(svm);
471
472 vmcb->control.intercept &= ~(1ULL << bit);
473
474 recalc_intercepts(svm);
475}
476
477static inline void enable_gif(struct vcpu_svm *svm)
478{
479 svm->vcpu.arch.hflags |= HF_GIF_MASK;
480}
481
482static inline void disable_gif(struct vcpu_svm *svm)
483{
484 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
485}
486
487static inline bool gif_set(struct vcpu_svm *svm)
488{
489 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
490}
491
492static unsigned long iopm_base;
493
494struct kvm_ldttss_desc {
495 u16 limit0;
496 u16 base0;
497 unsigned base1:8, type:5, dpl:2, p:1;
498 unsigned limit1:4, zero0:3, g:1, base2:8;
499 u32 base3;
500 u32 zero1;
501} __attribute__((packed));
502
503struct svm_cpu_data {
504 int cpu;
505
506 u64 asid_generation;
507 u32 max_asid;
508 u32 next_asid;
509 struct kvm_ldttss_desc *tss_desc;
510
511 struct page *save_area;
512};
513
514static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
515
516struct svm_init_data {
517 int cpu;
518 int r;
519};
520
521static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
522
523#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
524#define MSRS_RANGE_SIZE 2048
525#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
526
527static u32 svm_msrpm_offset(u32 msr)
528{
529 u32 offset;
530 int i;
531
532 for (i = 0; i < NUM_MSR_MAPS; i++) {
533 if (msr < msrpm_ranges[i] ||
534 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
535 continue;
536
537 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
538 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
539
540 /* Now we have the u8 offset - but need the u32 offset */
541 return offset / 4;
542 }
543
544 /* MSR not in any range */
545 return MSR_INVALID;
546}
547
548#define MAX_INST_SIZE 15
549
550static inline void clgi(void)
551{
552 asm volatile (__ex(SVM_CLGI));
553}
554
555static inline void stgi(void)
556{
557 asm volatile (__ex(SVM_STGI));
558}
559
560static inline void invlpga(unsigned long addr, u32 asid)
561{
562 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
563}
564
565static int get_npt_level(void)
566{
567#ifdef CONFIG_X86_64
568 return PT64_ROOT_LEVEL;
569#else
570 return PT32E_ROOT_LEVEL;
571#endif
572}
573
574static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
575{
576 vcpu->arch.efer = efer;
577 if (!npt_enabled && !(efer & EFER_LMA))
578 efer &= ~EFER_LME;
579
580 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
581 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
582}
583
584static int is_external_interrupt(u32 info)
585{
586 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
587 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
588}
589
590static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
591{
592 struct vcpu_svm *svm = to_svm(vcpu);
593 u32 ret = 0;
594
595 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
596 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
597 return ret;
598}
599
600static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
601{
602 struct vcpu_svm *svm = to_svm(vcpu);
603
604 if (mask == 0)
605 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
606 else
607 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
608
609}
610
611static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
612{
613 struct vcpu_svm *svm = to_svm(vcpu);
614
615 if (svm->vmcb->control.next_rip != 0) {
616 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
617 svm->next_rip = svm->vmcb->control.next_rip;
618 }
619
620 if (!svm->next_rip) {
621 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
622 EMULATE_DONE)
623 printk(KERN_DEBUG "%s: NOP\n", __func__);
624 return;
625 }
626 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
627 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
628 __func__, kvm_rip_read(vcpu), svm->next_rip);
629
630 kvm_rip_write(vcpu, svm->next_rip);
631 svm_set_interrupt_shadow(vcpu, 0);
632}
633
634static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
635 bool has_error_code, u32 error_code,
636 bool reinject)
637{
638 struct vcpu_svm *svm = to_svm(vcpu);
639
640 /*
641 * If we are within a nested VM we'd better #VMEXIT and let the guest
642 * handle the exception
643 */
644 if (!reinject &&
645 nested_svm_check_exception(svm, nr, has_error_code, error_code))
646 return;
647
648 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
649 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
650
651 /*
652 * For guest debugging where we have to reinject #BP if some
653 * INT3 is guest-owned:
654 * Emulate nRIP by moving RIP forward. Will fail if injection
655 * raises a fault that is not intercepted. Still better than
656 * failing in all cases.
657 */
658 skip_emulated_instruction(&svm->vcpu);
659 rip = kvm_rip_read(&svm->vcpu);
660 svm->int3_rip = rip + svm->vmcb->save.cs.base;
661 svm->int3_injected = rip - old_rip;
662 }
663
664 svm->vmcb->control.event_inj = nr
665 | SVM_EVTINJ_VALID
666 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
667 | SVM_EVTINJ_TYPE_EXEPT;
668 svm->vmcb->control.event_inj_err = error_code;
669}
670
671static void svm_init_erratum_383(void)
672{
673 u32 low, high;
674 int err;
675 u64 val;
676
677 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
678 return;
679
680 /* Use _safe variants to not break nested virtualization */
681 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
682 if (err)
683 return;
684
685 val |= (1ULL << 47);
686
687 low = lower_32_bits(val);
688 high = upper_32_bits(val);
689
690 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
691
692 erratum_383_found = true;
693}
694
695static void svm_init_osvw(struct kvm_vcpu *vcpu)
696{
697 /*
698 * Guests should see errata 400 and 415 as fixed (assuming that
699 * HLT and IO instructions are intercepted).
700 */
701 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
702 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
703
704 /*
705 * By increasing VCPU's osvw.length to 3 we are telling the guest that
706 * all osvw.status bits inside that length, including bit 0 (which is
707 * reserved for erratum 298), are valid. However, if host processor's
708 * osvw_len is 0 then osvw_status[0] carries no information. We need to
709 * be conservative here and therefore we tell the guest that erratum 298
710 * is present (because we really don't know).
711 */
712 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
713 vcpu->arch.osvw.status |= 1;
714}
715
716static int has_svm(void)
717{
718 const char *msg;
719
720 if (!cpu_has_svm(&msg)) {
721 printk(KERN_INFO "has_svm: %s\n", msg);
722 return 0;
723 }
724
725 return 1;
726}
727
728static void svm_hardware_disable(void)
729{
730 /* Make sure we clean up behind us */
731 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
732 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
733
734 cpu_svm_disable();
735
736 amd_pmu_disable_virt();
737}
738
739static int svm_hardware_enable(void)
740{
741
742 struct svm_cpu_data *sd;
743 uint64_t efer;
744 struct desc_ptr gdt_descr;
745 struct desc_struct *gdt;
746 int me = raw_smp_processor_id();
747
748 rdmsrl(MSR_EFER, efer);
749 if (efer & EFER_SVME)
750 return -EBUSY;
751
752 if (!has_svm()) {
753 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
754 return -EINVAL;
755 }
756 sd = per_cpu(svm_data, me);
757 if (!sd) {
758 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
759 return -EINVAL;
760 }
761
762 sd->asid_generation = 1;
763 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
764 sd->next_asid = sd->max_asid + 1;
765
766 native_store_gdt(&gdt_descr);
767 gdt = (struct desc_struct *)gdt_descr.address;
768 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
769
770 wrmsrl(MSR_EFER, efer | EFER_SVME);
771
772 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
773
774 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
775 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
776 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
777 }
778
779
780 /*
781 * Get OSVW bits.
782 *
783 * Note that it is possible to have a system with mixed processor
784 * revisions and therefore different OSVW bits. If bits are not the same
785 * on different processors then choose the worst case (i.e. if erratum
786 * is present on one processor and not on another then assume that the
787 * erratum is present everywhere).
788 */
789 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
790 uint64_t len, status = 0;
791 int err;
792
793 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
794 if (!err)
795 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
796 &err);
797
798 if (err)
799 osvw_status = osvw_len = 0;
800 else {
801 if (len < osvw_len)
802 osvw_len = len;
803 osvw_status |= status;
804 osvw_status &= (1ULL << osvw_len) - 1;
805 }
806 } else
807 osvw_status = osvw_len = 0;
808
809 svm_init_erratum_383();
810
811 amd_pmu_enable_virt();
812
813 return 0;
814}
815
816static void svm_cpu_uninit(int cpu)
817{
818 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
819
820 if (!sd)
821 return;
822
823 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
824 __free_page(sd->save_area);
825 kfree(sd);
826}
827
828static int svm_cpu_init(int cpu)
829{
830 struct svm_cpu_data *sd;
831 int r;
832
833 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
834 if (!sd)
835 return -ENOMEM;
836 sd->cpu = cpu;
837 sd->save_area = alloc_page(GFP_KERNEL);
838 r = -ENOMEM;
839 if (!sd->save_area)
840 goto err_1;
841
842 per_cpu(svm_data, cpu) = sd;
843
844 return 0;
845
846err_1:
847 kfree(sd);
848 return r;
849
850}
851
852static bool valid_msr_intercept(u32 index)
853{
854 int i;
855
856 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
857 if (direct_access_msrs[i].index == index)
858 return true;
859
860 return false;
861}
862
863static void set_msr_interception(u32 *msrpm, unsigned msr,
864 int read, int write)
865{
866 u8 bit_read, bit_write;
867 unsigned long tmp;
868 u32 offset;
869
870 /*
871 * If this warning triggers extend the direct_access_msrs list at the
872 * beginning of the file
873 */
874 WARN_ON(!valid_msr_intercept(msr));
875
876 offset = svm_msrpm_offset(msr);
877 bit_read = 2 * (msr & 0x0f);
878 bit_write = 2 * (msr & 0x0f) + 1;
879 tmp = msrpm[offset];
880
881 BUG_ON(offset == MSR_INVALID);
882
883 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
884 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
885
886 msrpm[offset] = tmp;
887}
888
889static void svm_vcpu_init_msrpm(u32 *msrpm)
890{
891 int i;
892
893 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
894
895 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
896 if (!direct_access_msrs[i].always)
897 continue;
898
899 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
900 }
901}
902
903static void add_msr_offset(u32 offset)
904{
905 int i;
906
907 for (i = 0; i < MSRPM_OFFSETS; ++i) {
908
909 /* Offset already in list? */
910 if (msrpm_offsets[i] == offset)
911 return;
912
913 /* Slot used by another offset? */
914 if (msrpm_offsets[i] != MSR_INVALID)
915 continue;
916
917 /* Add offset to list */
918 msrpm_offsets[i] = offset;
919
920 return;
921 }
922
923 /*
924 * If this BUG triggers the msrpm_offsets table has an overflow. Just
925 * increase MSRPM_OFFSETS in this case.
926 */
927 BUG();
928}
929
930static void init_msrpm_offsets(void)
931{
932 int i;
933
934 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
935
936 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
937 u32 offset;
938
939 offset = svm_msrpm_offset(direct_access_msrs[i].index);
940 BUG_ON(offset == MSR_INVALID);
941
942 add_msr_offset(offset);
943 }
944}
945
946static void svm_enable_lbrv(struct vcpu_svm *svm)
947{
948 u32 *msrpm = svm->msrpm;
949
950 svm->vmcb->control.lbr_ctl = 1;
951 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
952 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
953 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
954 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
955}
956
957static void svm_disable_lbrv(struct vcpu_svm *svm)
958{
959 u32 *msrpm = svm->msrpm;
960
961 svm->vmcb->control.lbr_ctl = 0;
962 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
963 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
964 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
965 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
966}
967
968/* Note:
969 * This hash table is used to map VM_ID to a struct kvm_arch,
970 * when handling AMD IOMMU GALOG notification to schedule in
971 * a particular vCPU.
972 */
973#define SVM_VM_DATA_HASH_BITS 8
974DECLARE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
975static spinlock_t svm_vm_data_hash_lock;
976
977/* Note:
978 * This function is called from IOMMU driver to notify
979 * SVM to schedule in a particular vCPU of a particular VM.
980 */
981static int avic_ga_log_notifier(u32 ga_tag)
982{
983 unsigned long flags;
984 struct kvm_arch *ka = NULL;
985 struct kvm_vcpu *vcpu = NULL;
986 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
987 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
988
989 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
990
991 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
992 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
993 struct kvm *kvm = container_of(ka, struct kvm, arch);
994 struct kvm_arch *vm_data = &kvm->arch;
995
996 if (vm_data->avic_vm_id != vm_id)
997 continue;
998 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
999 break;
1000 }
1001 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1002
1003 if (!vcpu)
1004 return 0;
1005
1006 /* Note:
1007 * At this point, the IOMMU should have already set the pending
1008 * bit in the vAPIC backing page. So, we just need to schedule
1009 * in the vcpu.
1010 */
1011 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1012 kvm_vcpu_wake_up(vcpu);
1013
1014 return 0;
1015}
1016
1017static __init int svm_hardware_setup(void)
1018{
1019 int cpu;
1020 struct page *iopm_pages;
1021 void *iopm_va;
1022 int r;
1023
1024 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1025
1026 if (!iopm_pages)
1027 return -ENOMEM;
1028
1029 iopm_va = page_address(iopm_pages);
1030 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1031 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1032
1033 init_msrpm_offsets();
1034
1035 if (boot_cpu_has(X86_FEATURE_NX))
1036 kvm_enable_efer_bits(EFER_NX);
1037
1038 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1039 kvm_enable_efer_bits(EFER_FFXSR);
1040
1041 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1042 kvm_has_tsc_control = true;
1043 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1044 kvm_tsc_scaling_ratio_frac_bits = 32;
1045 }
1046
1047 if (nested) {
1048 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1049 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1050 }
1051
1052 for_each_possible_cpu(cpu) {
1053 r = svm_cpu_init(cpu);
1054 if (r)
1055 goto err;
1056 }
1057
1058 if (!boot_cpu_has(X86_FEATURE_NPT))
1059 npt_enabled = false;
1060
1061 if (npt_enabled && !npt) {
1062 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1063 npt_enabled = false;
1064 }
1065
1066 if (npt_enabled) {
1067 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1068 kvm_enable_tdp();
1069 } else
1070 kvm_disable_tdp();
1071
1072 if (avic) {
1073 if (!npt_enabled ||
1074 !boot_cpu_has(X86_FEATURE_AVIC) ||
1075 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1076 avic = false;
1077 } else {
1078 pr_info("AVIC enabled\n");
1079
1080 hash_init(svm_vm_data_hash);
1081 spin_lock_init(&svm_vm_data_hash_lock);
1082 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1083 }
1084 }
1085
1086 return 0;
1087
1088err:
1089 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1090 iopm_base = 0;
1091 return r;
1092}
1093
1094static __exit void svm_hardware_unsetup(void)
1095{
1096 int cpu;
1097
1098 for_each_possible_cpu(cpu)
1099 svm_cpu_uninit(cpu);
1100
1101 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1102 iopm_base = 0;
1103}
1104
1105static void init_seg(struct vmcb_seg *seg)
1106{
1107 seg->selector = 0;
1108 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1109 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1110 seg->limit = 0xffff;
1111 seg->base = 0;
1112}
1113
1114static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1115{
1116 seg->selector = 0;
1117 seg->attrib = SVM_SELECTOR_P_MASK | type;
1118 seg->limit = 0xffff;
1119 seg->base = 0;
1120}
1121
1122static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1123{
1124 struct vcpu_svm *svm = to_svm(vcpu);
1125 u64 g_tsc_offset = 0;
1126
1127 if (is_guest_mode(vcpu)) {
1128 g_tsc_offset = svm->vmcb->control.tsc_offset -
1129 svm->nested.hsave->control.tsc_offset;
1130 svm->nested.hsave->control.tsc_offset = offset;
1131 } else
1132 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1133 svm->vmcb->control.tsc_offset,
1134 offset);
1135
1136 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1137
1138 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1139}
1140
1141static void avic_init_vmcb(struct vcpu_svm *svm)
1142{
1143 struct vmcb *vmcb = svm->vmcb;
1144 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1145 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1146 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1147 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1148
1149 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1150 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1151 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1152 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1153 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1154 svm->vcpu.arch.apicv_active = true;
1155}
1156
1157static void init_vmcb(struct vcpu_svm *svm)
1158{
1159 struct vmcb_control_area *control = &svm->vmcb->control;
1160 struct vmcb_save_area *save = &svm->vmcb->save;
1161
1162 svm->vcpu.fpu_active = 1;
1163 svm->vcpu.arch.hflags = 0;
1164
1165 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1166 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1167 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1168 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1169 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1170 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1171 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1172 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1173
1174 set_dr_intercepts(svm);
1175
1176 set_exception_intercept(svm, PF_VECTOR);
1177 set_exception_intercept(svm, UD_VECTOR);
1178 set_exception_intercept(svm, MC_VECTOR);
1179 set_exception_intercept(svm, AC_VECTOR);
1180 set_exception_intercept(svm, DB_VECTOR);
1181
1182 set_intercept(svm, INTERCEPT_INTR);
1183 set_intercept(svm, INTERCEPT_NMI);
1184 set_intercept(svm, INTERCEPT_SMI);
1185 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1186 set_intercept(svm, INTERCEPT_RDPMC);
1187 set_intercept(svm, INTERCEPT_CPUID);
1188 set_intercept(svm, INTERCEPT_INVD);
1189 set_intercept(svm, INTERCEPT_HLT);
1190 set_intercept(svm, INTERCEPT_INVLPG);
1191 set_intercept(svm, INTERCEPT_INVLPGA);
1192 set_intercept(svm, INTERCEPT_IOIO_PROT);
1193 set_intercept(svm, INTERCEPT_MSR_PROT);
1194 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1195 set_intercept(svm, INTERCEPT_SHUTDOWN);
1196 set_intercept(svm, INTERCEPT_VMRUN);
1197 set_intercept(svm, INTERCEPT_VMMCALL);
1198 set_intercept(svm, INTERCEPT_VMLOAD);
1199 set_intercept(svm, INTERCEPT_VMSAVE);
1200 set_intercept(svm, INTERCEPT_STGI);
1201 set_intercept(svm, INTERCEPT_CLGI);
1202 set_intercept(svm, INTERCEPT_SKINIT);
1203 set_intercept(svm, INTERCEPT_WBINVD);
1204 set_intercept(svm, INTERCEPT_MONITOR);
1205 set_intercept(svm, INTERCEPT_MWAIT);
1206 set_intercept(svm, INTERCEPT_XSETBV);
1207
1208 control->iopm_base_pa = iopm_base;
1209 control->msrpm_base_pa = __pa(svm->msrpm);
1210 control->int_ctl = V_INTR_MASKING_MASK;
1211
1212 init_seg(&save->es);
1213 init_seg(&save->ss);
1214 init_seg(&save->ds);
1215 init_seg(&save->fs);
1216 init_seg(&save->gs);
1217
1218 save->cs.selector = 0xf000;
1219 save->cs.base = 0xffff0000;
1220 /* Executable/Readable Code Segment */
1221 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1222 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1223 save->cs.limit = 0xffff;
1224
1225 save->gdtr.limit = 0xffff;
1226 save->idtr.limit = 0xffff;
1227
1228 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1229 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1230
1231 svm_set_efer(&svm->vcpu, 0);
1232 save->dr6 = 0xffff0ff0;
1233 kvm_set_rflags(&svm->vcpu, 2);
1234 save->rip = 0x0000fff0;
1235 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1236
1237 /*
1238 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1239 * It also updates the guest-visible cr0 value.
1240 */
1241 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1242 kvm_mmu_reset_context(&svm->vcpu);
1243
1244 save->cr4 = X86_CR4_PAE;
1245 /* rdx = ?? */
1246
1247 if (npt_enabled) {
1248 /* Setup VMCB for Nested Paging */
1249 control->nested_ctl = 1;
1250 clr_intercept(svm, INTERCEPT_INVLPG);
1251 clr_exception_intercept(svm, PF_VECTOR);
1252 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1253 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1254 save->g_pat = svm->vcpu.arch.pat;
1255 save->cr3 = 0;
1256 save->cr4 = 0;
1257 }
1258 svm->asid_generation = 0;
1259
1260 svm->nested.vmcb = 0;
1261 svm->vcpu.arch.hflags = 0;
1262
1263 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1264 control->pause_filter_count = 3000;
1265 set_intercept(svm, INTERCEPT_PAUSE);
1266 }
1267
1268 if (avic)
1269 avic_init_vmcb(svm);
1270
1271 mark_all_dirty(svm->vmcb);
1272
1273 enable_gif(svm);
1274
1275}
1276
1277static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1278{
1279 u64 *avic_physical_id_table;
1280 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1281
1282 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1283 return NULL;
1284
1285 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1286
1287 return &avic_physical_id_table[index];
1288}
1289
1290/**
1291 * Note:
1292 * AVIC hardware walks the nested page table to check permissions,
1293 * but does not use the SPA address specified in the leaf page
1294 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1295 * field of the VMCB. Therefore, we set up the
1296 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1297 */
1298static int avic_init_access_page(struct kvm_vcpu *vcpu)
1299{
1300 struct kvm *kvm = vcpu->kvm;
1301 int ret;
1302
1303 if (kvm->arch.apic_access_page_done)
1304 return 0;
1305
1306 ret = x86_set_memory_region(kvm,
1307 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1308 APIC_DEFAULT_PHYS_BASE,
1309 PAGE_SIZE);
1310 if (ret)
1311 return ret;
1312
1313 kvm->arch.apic_access_page_done = true;
1314 return 0;
1315}
1316
1317static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1318{
1319 int ret;
1320 u64 *entry, new_entry;
1321 int id = vcpu->vcpu_id;
1322 struct vcpu_svm *svm = to_svm(vcpu);
1323
1324 ret = avic_init_access_page(vcpu);
1325 if (ret)
1326 return ret;
1327
1328 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1329 return -EINVAL;
1330
1331 if (!svm->vcpu.arch.apic->regs)
1332 return -EINVAL;
1333
1334 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1335
1336 /* Setting AVIC backing page address in the phy APIC ID table */
1337 entry = avic_get_physical_id_entry(vcpu, id);
1338 if (!entry)
1339 return -EINVAL;
1340
1341 new_entry = READ_ONCE(*entry);
1342 new_entry = (page_to_phys(svm->avic_backing_page) &
1343 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1344 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1345 WRITE_ONCE(*entry, new_entry);
1346
1347 svm->avic_physical_id_cache = entry;
1348
1349 return 0;
1350}
1351
1352static inline int avic_get_next_vm_id(void)
1353{
1354 int id;
1355
1356 spin_lock(&avic_vm_id_lock);
1357
1358 /* AVIC VM ID is one-based. */
1359 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1360 if (id <= AVIC_VM_ID_MASK)
1361 __set_bit(id, avic_vm_id_bitmap);
1362 else
1363 id = -EAGAIN;
1364
1365 spin_unlock(&avic_vm_id_lock);
1366 return id;
1367}
1368
1369static inline int avic_free_vm_id(int id)
1370{
1371 if (id <= 0 || id > AVIC_VM_ID_MASK)
1372 return -EINVAL;
1373
1374 spin_lock(&avic_vm_id_lock);
1375 __clear_bit(id, avic_vm_id_bitmap);
1376 spin_unlock(&avic_vm_id_lock);
1377 return 0;
1378}
1379
1380static void avic_vm_destroy(struct kvm *kvm)
1381{
1382 unsigned long flags;
1383 struct kvm_arch *vm_data = &kvm->arch;
1384
1385 avic_free_vm_id(vm_data->avic_vm_id);
1386
1387 if (vm_data->avic_logical_id_table_page)
1388 __free_page(vm_data->avic_logical_id_table_page);
1389 if (vm_data->avic_physical_id_table_page)
1390 __free_page(vm_data->avic_physical_id_table_page);
1391
1392 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1393 hash_del(&vm_data->hnode);
1394 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1395}
1396
1397static int avic_vm_init(struct kvm *kvm)
1398{
1399 unsigned long flags;
1400 int vm_id, err = -ENOMEM;
1401 struct kvm_arch *vm_data = &kvm->arch;
1402 struct page *p_page;
1403 struct page *l_page;
1404
1405 if (!avic)
1406 return 0;
1407
1408 vm_id = avic_get_next_vm_id();
1409 if (vm_id < 0)
1410 return vm_id;
1411 vm_data->avic_vm_id = (u32)vm_id;
1412
1413 /* Allocating physical APIC ID table (4KB) */
1414 p_page = alloc_page(GFP_KERNEL);
1415 if (!p_page)
1416 goto free_avic;
1417
1418 vm_data->avic_physical_id_table_page = p_page;
1419 clear_page(page_address(p_page));
1420
1421 /* Allocating logical APIC ID table (4KB) */
1422 l_page = alloc_page(GFP_KERNEL);
1423 if (!l_page)
1424 goto free_avic;
1425
1426 vm_data->avic_logical_id_table_page = l_page;
1427 clear_page(page_address(l_page));
1428
1429 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1430 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1431 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1432
1433 return 0;
1434
1435free_avic:
1436 avic_vm_destroy(kvm);
1437 return err;
1438}
1439
1440static inline int
1441avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1442{
1443 int ret = 0;
1444 unsigned long flags;
1445 struct amd_svm_iommu_ir *ir;
1446 struct vcpu_svm *svm = to_svm(vcpu);
1447
1448 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1449 return 0;
1450
1451 /*
1452 * Here, we go through the per-vcpu ir_list to update all existing
1453 * interrupt remapping table entry targeting this vcpu.
1454 */
1455 spin_lock_irqsave(&svm->ir_list_lock, flags);
1456
1457 if (list_empty(&svm->ir_list))
1458 goto out;
1459
1460 list_for_each_entry(ir, &svm->ir_list, node) {
1461 ret = amd_iommu_update_ga(cpu, r, ir->data);
1462 if (ret)
1463 break;
1464 }
1465out:
1466 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1467 return ret;
1468}
1469
1470static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1471{
1472 u64 entry;
1473 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1474 int h_physical_id = kvm_cpu_get_apicid(cpu);
1475 struct vcpu_svm *svm = to_svm(vcpu);
1476
1477 if (!kvm_vcpu_apicv_active(vcpu))
1478 return;
1479
1480 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1481 return;
1482
1483 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1484 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1485
1486 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1487 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1488
1489 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1490 if (svm->avic_is_running)
1491 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1492
1493 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1494 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1495 svm->avic_is_running);
1496}
1497
1498static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1499{
1500 u64 entry;
1501 struct vcpu_svm *svm = to_svm(vcpu);
1502
1503 if (!kvm_vcpu_apicv_active(vcpu))
1504 return;
1505
1506 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1507 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1508 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1509
1510 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1511 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1512}
1513
1514/**
1515 * This function is called during VCPU halt/unhalt.
1516 */
1517static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1518{
1519 struct vcpu_svm *svm = to_svm(vcpu);
1520
1521 svm->avic_is_running = is_run;
1522 if (is_run)
1523 avic_vcpu_load(vcpu, vcpu->cpu);
1524 else
1525 avic_vcpu_put(vcpu);
1526}
1527
1528static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1529{
1530 struct vcpu_svm *svm = to_svm(vcpu);
1531 u32 dummy;
1532 u32 eax = 1;
1533
1534 if (!init_event) {
1535 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1536 MSR_IA32_APICBASE_ENABLE;
1537 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1538 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1539 }
1540 init_vmcb(svm);
1541
1542 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1543 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1544
1545 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1546 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1547}
1548
1549static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1550{
1551 struct vcpu_svm *svm;
1552 struct page *page;
1553 struct page *msrpm_pages;
1554 struct page *hsave_page;
1555 struct page *nested_msrpm_pages;
1556 int err;
1557
1558 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1559 if (!svm) {
1560 err = -ENOMEM;
1561 goto out;
1562 }
1563
1564 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1565 if (err)
1566 goto free_svm;
1567
1568 err = -ENOMEM;
1569 page = alloc_page(GFP_KERNEL);
1570 if (!page)
1571 goto uninit;
1572
1573 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1574 if (!msrpm_pages)
1575 goto free_page1;
1576
1577 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1578 if (!nested_msrpm_pages)
1579 goto free_page2;
1580
1581 hsave_page = alloc_page(GFP_KERNEL);
1582 if (!hsave_page)
1583 goto free_page3;
1584
1585 if (avic) {
1586 err = avic_init_backing_page(&svm->vcpu);
1587 if (err)
1588 goto free_page4;
1589
1590 INIT_LIST_HEAD(&svm->ir_list);
1591 spin_lock_init(&svm->ir_list_lock);
1592 }
1593
1594 /* We initialize this flag to true to make sure that the is_running
1595 * bit would be set the first time the vcpu is loaded.
1596 */
1597 svm->avic_is_running = true;
1598
1599 svm->nested.hsave = page_address(hsave_page);
1600
1601 svm->msrpm = page_address(msrpm_pages);
1602 svm_vcpu_init_msrpm(svm->msrpm);
1603
1604 svm->nested.msrpm = page_address(nested_msrpm_pages);
1605 svm_vcpu_init_msrpm(svm->nested.msrpm);
1606
1607 svm->vmcb = page_address(page);
1608 clear_page(svm->vmcb);
1609 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1610 svm->asid_generation = 0;
1611 init_vmcb(svm);
1612
1613 svm_init_osvw(&svm->vcpu);
1614
1615 return &svm->vcpu;
1616
1617free_page4:
1618 __free_page(hsave_page);
1619free_page3:
1620 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1621free_page2:
1622 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1623free_page1:
1624 __free_page(page);
1625uninit:
1626 kvm_vcpu_uninit(&svm->vcpu);
1627free_svm:
1628 kmem_cache_free(kvm_vcpu_cache, svm);
1629out:
1630 return ERR_PTR(err);
1631}
1632
1633static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1634{
1635 struct vcpu_svm *svm = to_svm(vcpu);
1636
1637 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1638 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1639 __free_page(virt_to_page(svm->nested.hsave));
1640 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1641 kvm_vcpu_uninit(vcpu);
1642 kmem_cache_free(kvm_vcpu_cache, svm);
1643}
1644
1645static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1646{
1647 struct vcpu_svm *svm = to_svm(vcpu);
1648 int i;
1649
1650 if (unlikely(cpu != vcpu->cpu)) {
1651 svm->asid_generation = 0;
1652 mark_all_dirty(svm->vmcb);
1653 }
1654
1655#ifdef CONFIG_X86_64
1656 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1657#endif
1658 savesegment(fs, svm->host.fs);
1659 savesegment(gs, svm->host.gs);
1660 svm->host.ldt = kvm_read_ldt();
1661
1662 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1663 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1664
1665 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1666 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1667 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1668 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1669 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1670 }
1671 }
1672 /* This assumes that the kernel never uses MSR_TSC_AUX */
1673 if (static_cpu_has(X86_FEATURE_RDTSCP))
1674 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1675
1676 avic_vcpu_load(vcpu, cpu);
1677}
1678
1679static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1680{
1681 struct vcpu_svm *svm = to_svm(vcpu);
1682 int i;
1683
1684 avic_vcpu_put(vcpu);
1685
1686 ++vcpu->stat.host_state_reload;
1687 kvm_load_ldt(svm->host.ldt);
1688#ifdef CONFIG_X86_64
1689 loadsegment(fs, svm->host.fs);
1690 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1691 load_gs_index(svm->host.gs);
1692#else
1693#ifdef CONFIG_X86_32_LAZY_GS
1694 loadsegment(gs, svm->host.gs);
1695#endif
1696#endif
1697 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1698 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1699}
1700
1701static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1702{
1703 avic_set_running(vcpu, false);
1704}
1705
1706static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1707{
1708 avic_set_running(vcpu, true);
1709}
1710
1711static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1712{
1713 return to_svm(vcpu)->vmcb->save.rflags;
1714}
1715
1716static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1717{
1718 /*
1719 * Any change of EFLAGS.VM is accompanied by a reload of SS
1720 * (caused by either a task switch or an inter-privilege IRET),
1721 * so we do not need to update the CPL here.
1722 */
1723 to_svm(vcpu)->vmcb->save.rflags = rflags;
1724}
1725
1726static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1727{
1728 return 0;
1729}
1730
1731static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1732{
1733 switch (reg) {
1734 case VCPU_EXREG_PDPTR:
1735 BUG_ON(!npt_enabled);
1736 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1737 break;
1738 default:
1739 BUG();
1740 }
1741}
1742
1743static void svm_set_vintr(struct vcpu_svm *svm)
1744{
1745 set_intercept(svm, INTERCEPT_VINTR);
1746}
1747
1748static void svm_clear_vintr(struct vcpu_svm *svm)
1749{
1750 clr_intercept(svm, INTERCEPT_VINTR);
1751}
1752
1753static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1754{
1755 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1756
1757 switch (seg) {
1758 case VCPU_SREG_CS: return &save->cs;
1759 case VCPU_SREG_DS: return &save->ds;
1760 case VCPU_SREG_ES: return &save->es;
1761 case VCPU_SREG_FS: return &save->fs;
1762 case VCPU_SREG_GS: return &save->gs;
1763 case VCPU_SREG_SS: return &save->ss;
1764 case VCPU_SREG_TR: return &save->tr;
1765 case VCPU_SREG_LDTR: return &save->ldtr;
1766 }
1767 BUG();
1768 return NULL;
1769}
1770
1771static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1772{
1773 struct vmcb_seg *s = svm_seg(vcpu, seg);
1774
1775 return s->base;
1776}
1777
1778static void svm_get_segment(struct kvm_vcpu *vcpu,
1779 struct kvm_segment *var, int seg)
1780{
1781 struct vmcb_seg *s = svm_seg(vcpu, seg);
1782
1783 var->base = s->base;
1784 var->limit = s->limit;
1785 var->selector = s->selector;
1786 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1787 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1788 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1789 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1790 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1791 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1792 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1793
1794 /*
1795 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1796 * However, the SVM spec states that the G bit is not observed by the
1797 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1798 * So let's synthesize a legal G bit for all segments, this helps
1799 * running KVM nested. It also helps cross-vendor migration, because
1800 * Intel's vmentry has a check on the 'G' bit.
1801 */
1802 var->g = s->limit > 0xfffff;
1803
1804 /*
1805 * AMD's VMCB does not have an explicit unusable field, so emulate it
1806 * for cross vendor migration purposes by "not present"
1807 */
1808 var->unusable = !var->present || (var->type == 0);
1809
1810 switch (seg) {
1811 case VCPU_SREG_TR:
1812 /*
1813 * Work around a bug where the busy flag in the tr selector
1814 * isn't exposed
1815 */
1816 var->type |= 0x2;
1817 break;
1818 case VCPU_SREG_DS:
1819 case VCPU_SREG_ES:
1820 case VCPU_SREG_FS:
1821 case VCPU_SREG_GS:
1822 /*
1823 * The accessed bit must always be set in the segment
1824 * descriptor cache, although it can be cleared in the
1825 * descriptor, the cached bit always remains at 1. Since
1826 * Intel has a check on this, set it here to support
1827 * cross-vendor migration.
1828 */
1829 if (!var->unusable)
1830 var->type |= 0x1;
1831 break;
1832 case VCPU_SREG_SS:
1833 /*
1834 * On AMD CPUs sometimes the DB bit in the segment
1835 * descriptor is left as 1, although the whole segment has
1836 * been made unusable. Clear it here to pass an Intel VMX
1837 * entry check when cross vendor migrating.
1838 */
1839 if (var->unusable)
1840 var->db = 0;
1841 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1842 break;
1843 }
1844}
1845
1846static int svm_get_cpl(struct kvm_vcpu *vcpu)
1847{
1848 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1849
1850 return save->cpl;
1851}
1852
1853static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1854{
1855 struct vcpu_svm *svm = to_svm(vcpu);
1856
1857 dt->size = svm->vmcb->save.idtr.limit;
1858 dt->address = svm->vmcb->save.idtr.base;
1859}
1860
1861static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1862{
1863 struct vcpu_svm *svm = to_svm(vcpu);
1864
1865 svm->vmcb->save.idtr.limit = dt->size;
1866 svm->vmcb->save.idtr.base = dt->address ;
1867 mark_dirty(svm->vmcb, VMCB_DT);
1868}
1869
1870static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1871{
1872 struct vcpu_svm *svm = to_svm(vcpu);
1873
1874 dt->size = svm->vmcb->save.gdtr.limit;
1875 dt->address = svm->vmcb->save.gdtr.base;
1876}
1877
1878static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1879{
1880 struct vcpu_svm *svm = to_svm(vcpu);
1881
1882 svm->vmcb->save.gdtr.limit = dt->size;
1883 svm->vmcb->save.gdtr.base = dt->address ;
1884 mark_dirty(svm->vmcb, VMCB_DT);
1885}
1886
1887static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1888{
1889}
1890
1891static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1892{
1893}
1894
1895static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1896{
1897}
1898
1899static void update_cr0_intercept(struct vcpu_svm *svm)
1900{
1901 ulong gcr0 = svm->vcpu.arch.cr0;
1902 u64 *hcr0 = &svm->vmcb->save.cr0;
1903
1904 if (!svm->vcpu.fpu_active)
1905 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1906 else
1907 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1908 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1909
1910 mark_dirty(svm->vmcb, VMCB_CR);
1911
1912 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1913 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1914 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1915 } else {
1916 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1917 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1918 }
1919}
1920
1921static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1922{
1923 struct vcpu_svm *svm = to_svm(vcpu);
1924
1925#ifdef CONFIG_X86_64
1926 if (vcpu->arch.efer & EFER_LME) {
1927 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1928 vcpu->arch.efer |= EFER_LMA;
1929 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1930 }
1931
1932 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1933 vcpu->arch.efer &= ~EFER_LMA;
1934 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1935 }
1936 }
1937#endif
1938 vcpu->arch.cr0 = cr0;
1939
1940 if (!npt_enabled)
1941 cr0 |= X86_CR0_PG | X86_CR0_WP;
1942
1943 if (!vcpu->fpu_active)
1944 cr0 |= X86_CR0_TS;
1945 /*
1946 * re-enable caching here because the QEMU bios
1947 * does not do it - this results in some delay at
1948 * reboot
1949 */
1950 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1951 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1952 svm->vmcb->save.cr0 = cr0;
1953 mark_dirty(svm->vmcb, VMCB_CR);
1954 update_cr0_intercept(svm);
1955}
1956
1957static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1958{
1959 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1960 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1961
1962 if (cr4 & X86_CR4_VMXE)
1963 return 1;
1964
1965 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1966 svm_flush_tlb(vcpu);
1967
1968 vcpu->arch.cr4 = cr4;
1969 if (!npt_enabled)
1970 cr4 |= X86_CR4_PAE;
1971 cr4 |= host_cr4_mce;
1972 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1973 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1974 return 0;
1975}
1976
1977static void svm_set_segment(struct kvm_vcpu *vcpu,
1978 struct kvm_segment *var, int seg)
1979{
1980 struct vcpu_svm *svm = to_svm(vcpu);
1981 struct vmcb_seg *s = svm_seg(vcpu, seg);
1982
1983 s->base = var->base;
1984 s->limit = var->limit;
1985 s->selector = var->selector;
1986 if (var->unusable)
1987 s->attrib = 0;
1988 else {
1989 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1990 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1991 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1992 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1993 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1994 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1995 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1996 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1997 }
1998
1999 /*
2000 * This is always accurate, except if SYSRET returned to a segment
2001 * with SS.DPL != 3. Intel does not have this quirk, and always
2002 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2003 * would entail passing the CPL to userspace and back.
2004 */
2005 if (seg == VCPU_SREG_SS)
2006 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2007
2008 mark_dirty(svm->vmcb, VMCB_SEG);
2009}
2010
2011static void update_bp_intercept(struct kvm_vcpu *vcpu)
2012{
2013 struct vcpu_svm *svm = to_svm(vcpu);
2014
2015 clr_exception_intercept(svm, BP_VECTOR);
2016
2017 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2018 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2019 set_exception_intercept(svm, BP_VECTOR);
2020 } else
2021 vcpu->guest_debug = 0;
2022}
2023
2024static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2025{
2026 if (sd->next_asid > sd->max_asid) {
2027 ++sd->asid_generation;
2028 sd->next_asid = 1;
2029 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2030 }
2031
2032 svm->asid_generation = sd->asid_generation;
2033 svm->vmcb->control.asid = sd->next_asid++;
2034
2035 mark_dirty(svm->vmcb, VMCB_ASID);
2036}
2037
2038static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2039{
2040 return to_svm(vcpu)->vmcb->save.dr6;
2041}
2042
2043static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2044{
2045 struct vcpu_svm *svm = to_svm(vcpu);
2046
2047 svm->vmcb->save.dr6 = value;
2048 mark_dirty(svm->vmcb, VMCB_DR);
2049}
2050
2051static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2052{
2053 struct vcpu_svm *svm = to_svm(vcpu);
2054
2055 get_debugreg(vcpu->arch.db[0], 0);
2056 get_debugreg(vcpu->arch.db[1], 1);
2057 get_debugreg(vcpu->arch.db[2], 2);
2058 get_debugreg(vcpu->arch.db[3], 3);
2059 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2060 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2061
2062 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2063 set_dr_intercepts(svm);
2064}
2065
2066static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2067{
2068 struct vcpu_svm *svm = to_svm(vcpu);
2069
2070 svm->vmcb->save.dr7 = value;
2071 mark_dirty(svm->vmcb, VMCB_DR);
2072}
2073
2074static int pf_interception(struct vcpu_svm *svm)
2075{
2076 u64 fault_address = svm->vmcb->control.exit_info_2;
2077 u64 error_code;
2078 int r = 1;
2079
2080 switch (svm->apf_reason) {
2081 default:
2082 error_code = svm->vmcb->control.exit_info_1;
2083
2084 trace_kvm_page_fault(fault_address, error_code);
2085 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2086 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2087 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2088 svm->vmcb->control.insn_bytes,
2089 svm->vmcb->control.insn_len);
2090 break;
2091 case KVM_PV_REASON_PAGE_NOT_PRESENT:
2092 svm->apf_reason = 0;
2093 local_irq_disable();
2094 kvm_async_pf_task_wait(fault_address);
2095 local_irq_enable();
2096 break;
2097 case KVM_PV_REASON_PAGE_READY:
2098 svm->apf_reason = 0;
2099 local_irq_disable();
2100 kvm_async_pf_task_wake(fault_address);
2101 local_irq_enable();
2102 break;
2103 }
2104 return r;
2105}
2106
2107static int db_interception(struct vcpu_svm *svm)
2108{
2109 struct kvm_run *kvm_run = svm->vcpu.run;
2110
2111 if (!(svm->vcpu.guest_debug &
2112 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2113 !svm->nmi_singlestep) {
2114 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2115 return 1;
2116 }
2117
2118 if (svm->nmi_singlestep) {
2119 svm->nmi_singlestep = false;
2120 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2121 svm->vmcb->save.rflags &=
2122 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2123 }
2124
2125 if (svm->vcpu.guest_debug &
2126 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2127 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2128 kvm_run->debug.arch.pc =
2129 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2130 kvm_run->debug.arch.exception = DB_VECTOR;
2131 return 0;
2132 }
2133
2134 return 1;
2135}
2136
2137static int bp_interception(struct vcpu_svm *svm)
2138{
2139 struct kvm_run *kvm_run = svm->vcpu.run;
2140
2141 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2142 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2143 kvm_run->debug.arch.exception = BP_VECTOR;
2144 return 0;
2145}
2146
2147static int ud_interception(struct vcpu_svm *svm)
2148{
2149 int er;
2150
2151 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2152 if (er != EMULATE_DONE)
2153 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2154 return 1;
2155}
2156
2157static int ac_interception(struct vcpu_svm *svm)
2158{
2159 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2160 return 1;
2161}
2162
2163static void svm_fpu_activate(struct kvm_vcpu *vcpu)
2164{
2165 struct vcpu_svm *svm = to_svm(vcpu);
2166
2167 clr_exception_intercept(svm, NM_VECTOR);
2168
2169 svm->vcpu.fpu_active = 1;
2170 update_cr0_intercept(svm);
2171}
2172
2173static int nm_interception(struct vcpu_svm *svm)
2174{
2175 svm_fpu_activate(&svm->vcpu);
2176 return 1;
2177}
2178
2179static bool is_erratum_383(void)
2180{
2181 int err, i;
2182 u64 value;
2183
2184 if (!erratum_383_found)
2185 return false;
2186
2187 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2188 if (err)
2189 return false;
2190
2191 /* Bit 62 may or may not be set for this mce */
2192 value &= ~(1ULL << 62);
2193
2194 if (value != 0xb600000000010015ULL)
2195 return false;
2196
2197 /* Clear MCi_STATUS registers */
2198 for (i = 0; i < 6; ++i)
2199 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2200
2201 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2202 if (!err) {
2203 u32 low, high;
2204
2205 value &= ~(1ULL << 2);
2206 low = lower_32_bits(value);
2207 high = upper_32_bits(value);
2208
2209 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2210 }
2211
2212 /* Flush tlb to evict multi-match entries */
2213 __flush_tlb_all();
2214
2215 return true;
2216}
2217
2218static void svm_handle_mce(struct vcpu_svm *svm)
2219{
2220 if (is_erratum_383()) {
2221 /*
2222 * Erratum 383 triggered. Guest state is corrupt so kill the
2223 * guest.
2224 */
2225 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2226
2227 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2228
2229 return;
2230 }
2231
2232 /*
2233 * On an #MC intercept the MCE handler is not called automatically in
2234 * the host. So do it by hand here.
2235 */
2236 asm volatile (
2237 "int $0x12\n");
2238 /* not sure if we ever come back to this point */
2239
2240 return;
2241}
2242
2243static int mc_interception(struct vcpu_svm *svm)
2244{
2245 return 1;
2246}
2247
2248static int shutdown_interception(struct vcpu_svm *svm)
2249{
2250 struct kvm_run *kvm_run = svm->vcpu.run;
2251
2252 /*
2253 * VMCB is undefined after a SHUTDOWN intercept
2254 * so reinitialize it.
2255 */
2256 clear_page(svm->vmcb);
2257 init_vmcb(svm);
2258
2259 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2260 return 0;
2261}
2262
2263static int io_interception(struct vcpu_svm *svm)
2264{
2265 struct kvm_vcpu *vcpu = &svm->vcpu;
2266 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2267 int size, in, string;
2268 unsigned port;
2269
2270 ++svm->vcpu.stat.io_exits;
2271 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2272 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2273 if (string)
2274 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2275
2276 port = io_info >> 16;
2277 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2278 svm->next_rip = svm->vmcb->control.exit_info_2;
2279 skip_emulated_instruction(&svm->vcpu);
2280
2281 return in ? kvm_fast_pio_in(vcpu, size, port)
2282 : kvm_fast_pio_out(vcpu, size, port);
2283}
2284
2285static int nmi_interception(struct vcpu_svm *svm)
2286{
2287 return 1;
2288}
2289
2290static int intr_interception(struct vcpu_svm *svm)
2291{
2292 ++svm->vcpu.stat.irq_exits;
2293 return 1;
2294}
2295
2296static int nop_on_interception(struct vcpu_svm *svm)
2297{
2298 return 1;
2299}
2300
2301static int halt_interception(struct vcpu_svm *svm)
2302{
2303 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2304 return kvm_emulate_halt(&svm->vcpu);
2305}
2306
2307static int vmmcall_interception(struct vcpu_svm *svm)
2308{
2309 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2310 return kvm_emulate_hypercall(&svm->vcpu);
2311}
2312
2313static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2314{
2315 struct vcpu_svm *svm = to_svm(vcpu);
2316
2317 return svm->nested.nested_cr3;
2318}
2319
2320static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2321{
2322 struct vcpu_svm *svm = to_svm(vcpu);
2323 u64 cr3 = svm->nested.nested_cr3;
2324 u64 pdpte;
2325 int ret;
2326
2327 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2328 offset_in_page(cr3) + index * 8, 8);
2329 if (ret)
2330 return 0;
2331 return pdpte;
2332}
2333
2334static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2335 unsigned long root)
2336{
2337 struct vcpu_svm *svm = to_svm(vcpu);
2338
2339 svm->vmcb->control.nested_cr3 = root;
2340 mark_dirty(svm->vmcb, VMCB_NPT);
2341 svm_flush_tlb(vcpu);
2342}
2343
2344static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2345 struct x86_exception *fault)
2346{
2347 struct vcpu_svm *svm = to_svm(vcpu);
2348
2349 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2350 /*
2351 * TODO: track the cause of the nested page fault, and
2352 * correctly fill in the high bits of exit_info_1.
2353 */
2354 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2355 svm->vmcb->control.exit_code_hi = 0;
2356 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2357 svm->vmcb->control.exit_info_2 = fault->address;
2358 }
2359
2360 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2361 svm->vmcb->control.exit_info_1 |= fault->error_code;
2362
2363 /*
2364 * The present bit is always zero for page structure faults on real
2365 * hardware.
2366 */
2367 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2368 svm->vmcb->control.exit_info_1 &= ~1;
2369
2370 nested_svm_vmexit(svm);
2371}
2372
2373static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2374{
2375 WARN_ON(mmu_is_nested(vcpu));
2376 kvm_init_shadow_mmu(vcpu);
2377 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2378 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2379 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2380 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2381 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2382 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2383 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2384}
2385
2386static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2387{
2388 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2389}
2390
2391static int nested_svm_check_permissions(struct vcpu_svm *svm)
2392{
2393 if (!(svm->vcpu.arch.efer & EFER_SVME)
2394 || !is_paging(&svm->vcpu)) {
2395 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2396 return 1;
2397 }
2398
2399 if (svm->vmcb->save.cpl) {
2400 kvm_inject_gp(&svm->vcpu, 0);
2401 return 1;
2402 }
2403
2404 return 0;
2405}
2406
2407static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2408 bool has_error_code, u32 error_code)
2409{
2410 int vmexit;
2411
2412 if (!is_guest_mode(&svm->vcpu))
2413 return 0;
2414
2415 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2416 svm->vmcb->control.exit_code_hi = 0;
2417 svm->vmcb->control.exit_info_1 = error_code;
2418 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2419
2420 vmexit = nested_svm_intercept(svm);
2421 if (vmexit == NESTED_EXIT_DONE)
2422 svm->nested.exit_required = true;
2423
2424 return vmexit;
2425}
2426
2427/* This function returns true if it is save to enable the irq window */
2428static inline bool nested_svm_intr(struct vcpu_svm *svm)
2429{
2430 if (!is_guest_mode(&svm->vcpu))
2431 return true;
2432
2433 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2434 return true;
2435
2436 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2437 return false;
2438
2439 /*
2440 * if vmexit was already requested (by intercepted exception
2441 * for instance) do not overwrite it with "external interrupt"
2442 * vmexit.
2443 */
2444 if (svm->nested.exit_required)
2445 return false;
2446
2447 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2448 svm->vmcb->control.exit_info_1 = 0;
2449 svm->vmcb->control.exit_info_2 = 0;
2450
2451 if (svm->nested.intercept & 1ULL) {
2452 /*
2453 * The #vmexit can't be emulated here directly because this
2454 * code path runs with irqs and preemption disabled. A
2455 * #vmexit emulation might sleep. Only signal request for
2456 * the #vmexit here.
2457 */
2458 svm->nested.exit_required = true;
2459 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2460 return false;
2461 }
2462
2463 return true;
2464}
2465
2466/* This function returns true if it is save to enable the nmi window */
2467static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2468{
2469 if (!is_guest_mode(&svm->vcpu))
2470 return true;
2471
2472 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2473 return true;
2474
2475 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2476 svm->nested.exit_required = true;
2477
2478 return false;
2479}
2480
2481static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2482{
2483 struct page *page;
2484
2485 might_sleep();
2486
2487 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2488 if (is_error_page(page))
2489 goto error;
2490
2491 *_page = page;
2492
2493 return kmap(page);
2494
2495error:
2496 kvm_inject_gp(&svm->vcpu, 0);
2497
2498 return NULL;
2499}
2500
2501static void nested_svm_unmap(struct page *page)
2502{
2503 kunmap(page);
2504 kvm_release_page_dirty(page);
2505}
2506
2507static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2508{
2509 unsigned port, size, iopm_len;
2510 u16 val, mask;
2511 u8 start_bit;
2512 u64 gpa;
2513
2514 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2515 return NESTED_EXIT_HOST;
2516
2517 port = svm->vmcb->control.exit_info_1 >> 16;
2518 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2519 SVM_IOIO_SIZE_SHIFT;
2520 gpa = svm->nested.vmcb_iopm + (port / 8);
2521 start_bit = port % 8;
2522 iopm_len = (start_bit + size > 8) ? 2 : 1;
2523 mask = (0xf >> (4 - size)) << start_bit;
2524 val = 0;
2525
2526 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2527 return NESTED_EXIT_DONE;
2528
2529 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2530}
2531
2532static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2533{
2534 u32 offset, msr, value;
2535 int write, mask;
2536
2537 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2538 return NESTED_EXIT_HOST;
2539
2540 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2541 offset = svm_msrpm_offset(msr);
2542 write = svm->vmcb->control.exit_info_1 & 1;
2543 mask = 1 << ((2 * (msr & 0xf)) + write);
2544
2545 if (offset == MSR_INVALID)
2546 return NESTED_EXIT_DONE;
2547
2548 /* Offset is in 32 bit units but need in 8 bit units */
2549 offset *= 4;
2550
2551 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2552 return NESTED_EXIT_DONE;
2553
2554 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2555}
2556
2557static int nested_svm_exit_special(struct vcpu_svm *svm)
2558{
2559 u32 exit_code = svm->vmcb->control.exit_code;
2560
2561 switch (exit_code) {
2562 case SVM_EXIT_INTR:
2563 case SVM_EXIT_NMI:
2564 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2565 return NESTED_EXIT_HOST;
2566 case SVM_EXIT_NPF:
2567 /* For now we are always handling NPFs when using them */
2568 if (npt_enabled)
2569 return NESTED_EXIT_HOST;
2570 break;
2571 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2572 /* When we're shadowing, trap PFs, but not async PF */
2573 if (!npt_enabled && svm->apf_reason == 0)
2574 return NESTED_EXIT_HOST;
2575 break;
2576 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2577 nm_interception(svm);
2578 break;
2579 default:
2580 break;
2581 }
2582
2583 return NESTED_EXIT_CONTINUE;
2584}
2585
2586/*
2587 * If this function returns true, this #vmexit was already handled
2588 */
2589static int nested_svm_intercept(struct vcpu_svm *svm)
2590{
2591 u32 exit_code = svm->vmcb->control.exit_code;
2592 int vmexit = NESTED_EXIT_HOST;
2593
2594 switch (exit_code) {
2595 case SVM_EXIT_MSR:
2596 vmexit = nested_svm_exit_handled_msr(svm);
2597 break;
2598 case SVM_EXIT_IOIO:
2599 vmexit = nested_svm_intercept_ioio(svm);
2600 break;
2601 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2602 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2603 if (svm->nested.intercept_cr & bit)
2604 vmexit = NESTED_EXIT_DONE;
2605 break;
2606 }
2607 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2608 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2609 if (svm->nested.intercept_dr & bit)
2610 vmexit = NESTED_EXIT_DONE;
2611 break;
2612 }
2613 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2614 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2615 if (svm->nested.intercept_exceptions & excp_bits)
2616 vmexit = NESTED_EXIT_DONE;
2617 /* async page fault always cause vmexit */
2618 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2619 svm->apf_reason != 0)
2620 vmexit = NESTED_EXIT_DONE;
2621 break;
2622 }
2623 case SVM_EXIT_ERR: {
2624 vmexit = NESTED_EXIT_DONE;
2625 break;
2626 }
2627 default: {
2628 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2629 if (svm->nested.intercept & exit_bits)
2630 vmexit = NESTED_EXIT_DONE;
2631 }
2632 }
2633
2634 return vmexit;
2635}
2636
2637static int nested_svm_exit_handled(struct vcpu_svm *svm)
2638{
2639 int vmexit;
2640
2641 vmexit = nested_svm_intercept(svm);
2642
2643 if (vmexit == NESTED_EXIT_DONE)
2644 nested_svm_vmexit(svm);
2645
2646 return vmexit;
2647}
2648
2649static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2650{
2651 struct vmcb_control_area *dst = &dst_vmcb->control;
2652 struct vmcb_control_area *from = &from_vmcb->control;
2653
2654 dst->intercept_cr = from->intercept_cr;
2655 dst->intercept_dr = from->intercept_dr;
2656 dst->intercept_exceptions = from->intercept_exceptions;
2657 dst->intercept = from->intercept;
2658 dst->iopm_base_pa = from->iopm_base_pa;
2659 dst->msrpm_base_pa = from->msrpm_base_pa;
2660 dst->tsc_offset = from->tsc_offset;
2661 dst->asid = from->asid;
2662 dst->tlb_ctl = from->tlb_ctl;
2663 dst->int_ctl = from->int_ctl;
2664 dst->int_vector = from->int_vector;
2665 dst->int_state = from->int_state;
2666 dst->exit_code = from->exit_code;
2667 dst->exit_code_hi = from->exit_code_hi;
2668 dst->exit_info_1 = from->exit_info_1;
2669 dst->exit_info_2 = from->exit_info_2;
2670 dst->exit_int_info = from->exit_int_info;
2671 dst->exit_int_info_err = from->exit_int_info_err;
2672 dst->nested_ctl = from->nested_ctl;
2673 dst->event_inj = from->event_inj;
2674 dst->event_inj_err = from->event_inj_err;
2675 dst->nested_cr3 = from->nested_cr3;
2676 dst->lbr_ctl = from->lbr_ctl;
2677}
2678
2679static int nested_svm_vmexit(struct vcpu_svm *svm)
2680{
2681 struct vmcb *nested_vmcb;
2682 struct vmcb *hsave = svm->nested.hsave;
2683 struct vmcb *vmcb = svm->vmcb;
2684 struct page *page;
2685
2686 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2687 vmcb->control.exit_info_1,
2688 vmcb->control.exit_info_2,
2689 vmcb->control.exit_int_info,
2690 vmcb->control.exit_int_info_err,
2691 KVM_ISA_SVM);
2692
2693 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2694 if (!nested_vmcb)
2695 return 1;
2696
2697 /* Exit Guest-Mode */
2698 leave_guest_mode(&svm->vcpu);
2699 svm->nested.vmcb = 0;
2700
2701 /* Give the current vmcb to the guest */
2702 disable_gif(svm);
2703
2704 nested_vmcb->save.es = vmcb->save.es;
2705 nested_vmcb->save.cs = vmcb->save.cs;
2706 nested_vmcb->save.ss = vmcb->save.ss;
2707 nested_vmcb->save.ds = vmcb->save.ds;
2708 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2709 nested_vmcb->save.idtr = vmcb->save.idtr;
2710 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2711 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2712 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2713 nested_vmcb->save.cr2 = vmcb->save.cr2;
2714 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2715 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2716 nested_vmcb->save.rip = vmcb->save.rip;
2717 nested_vmcb->save.rsp = vmcb->save.rsp;
2718 nested_vmcb->save.rax = vmcb->save.rax;
2719 nested_vmcb->save.dr7 = vmcb->save.dr7;
2720 nested_vmcb->save.dr6 = vmcb->save.dr6;
2721 nested_vmcb->save.cpl = vmcb->save.cpl;
2722
2723 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2724 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2725 nested_vmcb->control.int_state = vmcb->control.int_state;
2726 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2727 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2728 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2729 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2730 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2731 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2732
2733 if (svm->nrips_enabled)
2734 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2735
2736 /*
2737 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2738 * to make sure that we do not lose injected events. So check event_inj
2739 * here and copy it to exit_int_info if it is valid.
2740 * Exit_int_info and event_inj can't be both valid because the case
2741 * below only happens on a VMRUN instruction intercept which has
2742 * no valid exit_int_info set.
2743 */
2744 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2745 struct vmcb_control_area *nc = &nested_vmcb->control;
2746
2747 nc->exit_int_info = vmcb->control.event_inj;
2748 nc->exit_int_info_err = vmcb->control.event_inj_err;
2749 }
2750
2751 nested_vmcb->control.tlb_ctl = 0;
2752 nested_vmcb->control.event_inj = 0;
2753 nested_vmcb->control.event_inj_err = 0;
2754
2755 /* We always set V_INTR_MASKING and remember the old value in hflags */
2756 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2757 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2758
2759 /* Restore the original control entries */
2760 copy_vmcb_control_area(vmcb, hsave);
2761
2762 kvm_clear_exception_queue(&svm->vcpu);
2763 kvm_clear_interrupt_queue(&svm->vcpu);
2764
2765 svm->nested.nested_cr3 = 0;
2766
2767 /* Restore selected save entries */
2768 svm->vmcb->save.es = hsave->save.es;
2769 svm->vmcb->save.cs = hsave->save.cs;
2770 svm->vmcb->save.ss = hsave->save.ss;
2771 svm->vmcb->save.ds = hsave->save.ds;
2772 svm->vmcb->save.gdtr = hsave->save.gdtr;
2773 svm->vmcb->save.idtr = hsave->save.idtr;
2774 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2775 svm_set_efer(&svm->vcpu, hsave->save.efer);
2776 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2777 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2778 if (npt_enabled) {
2779 svm->vmcb->save.cr3 = hsave->save.cr3;
2780 svm->vcpu.arch.cr3 = hsave->save.cr3;
2781 } else {
2782 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2783 }
2784 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2785 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2786 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2787 svm->vmcb->save.dr7 = 0;
2788 svm->vmcb->save.cpl = 0;
2789 svm->vmcb->control.exit_int_info = 0;
2790
2791 mark_all_dirty(svm->vmcb);
2792
2793 nested_svm_unmap(page);
2794
2795 nested_svm_uninit_mmu_context(&svm->vcpu);
2796 kvm_mmu_reset_context(&svm->vcpu);
2797 kvm_mmu_load(&svm->vcpu);
2798
2799 return 0;
2800}
2801
2802static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2803{
2804 /*
2805 * This function merges the msr permission bitmaps of kvm and the
2806 * nested vmcb. It is optimized in that it only merges the parts where
2807 * the kvm msr permission bitmap may contain zero bits
2808 */
2809 int i;
2810
2811 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2812 return true;
2813
2814 for (i = 0; i < MSRPM_OFFSETS; i++) {
2815 u32 value, p;
2816 u64 offset;
2817
2818 if (msrpm_offsets[i] == 0xffffffff)
2819 break;
2820
2821 p = msrpm_offsets[i];
2822 offset = svm->nested.vmcb_msrpm + (p * 4);
2823
2824 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2825 return false;
2826
2827 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2828 }
2829
2830 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2831
2832 return true;
2833}
2834
2835static bool nested_vmcb_checks(struct vmcb *vmcb)
2836{
2837 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2838 return false;
2839
2840 if (vmcb->control.asid == 0)
2841 return false;
2842
2843 if (vmcb->control.nested_ctl && !npt_enabled)
2844 return false;
2845
2846 return true;
2847}
2848
2849static bool nested_svm_vmrun(struct vcpu_svm *svm)
2850{
2851 struct vmcb *nested_vmcb;
2852 struct vmcb *hsave = svm->nested.hsave;
2853 struct vmcb *vmcb = svm->vmcb;
2854 struct page *page;
2855 u64 vmcb_gpa;
2856
2857 vmcb_gpa = svm->vmcb->save.rax;
2858
2859 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2860 if (!nested_vmcb)
2861 return false;
2862
2863 if (!nested_vmcb_checks(nested_vmcb)) {
2864 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2865 nested_vmcb->control.exit_code_hi = 0;
2866 nested_vmcb->control.exit_info_1 = 0;
2867 nested_vmcb->control.exit_info_2 = 0;
2868
2869 nested_svm_unmap(page);
2870
2871 return false;
2872 }
2873
2874 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2875 nested_vmcb->save.rip,
2876 nested_vmcb->control.int_ctl,
2877 nested_vmcb->control.event_inj,
2878 nested_vmcb->control.nested_ctl);
2879
2880 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2881 nested_vmcb->control.intercept_cr >> 16,
2882 nested_vmcb->control.intercept_exceptions,
2883 nested_vmcb->control.intercept);
2884
2885 /* Clear internal status */
2886 kvm_clear_exception_queue(&svm->vcpu);
2887 kvm_clear_interrupt_queue(&svm->vcpu);
2888
2889 /*
2890 * Save the old vmcb, so we don't need to pick what we save, but can
2891 * restore everything when a VMEXIT occurs
2892 */
2893 hsave->save.es = vmcb->save.es;
2894 hsave->save.cs = vmcb->save.cs;
2895 hsave->save.ss = vmcb->save.ss;
2896 hsave->save.ds = vmcb->save.ds;
2897 hsave->save.gdtr = vmcb->save.gdtr;
2898 hsave->save.idtr = vmcb->save.idtr;
2899 hsave->save.efer = svm->vcpu.arch.efer;
2900 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2901 hsave->save.cr4 = svm->vcpu.arch.cr4;
2902 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2903 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2904 hsave->save.rsp = vmcb->save.rsp;
2905 hsave->save.rax = vmcb->save.rax;
2906 if (npt_enabled)
2907 hsave->save.cr3 = vmcb->save.cr3;
2908 else
2909 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2910
2911 copy_vmcb_control_area(hsave, vmcb);
2912
2913 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2914 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2915 else
2916 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2917
2918 if (nested_vmcb->control.nested_ctl) {
2919 kvm_mmu_unload(&svm->vcpu);
2920 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2921 nested_svm_init_mmu_context(&svm->vcpu);
2922 }
2923
2924 /* Load the nested guest state */
2925 svm->vmcb->save.es = nested_vmcb->save.es;
2926 svm->vmcb->save.cs = nested_vmcb->save.cs;
2927 svm->vmcb->save.ss = nested_vmcb->save.ss;
2928 svm->vmcb->save.ds = nested_vmcb->save.ds;
2929 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2930 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2931 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2932 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2933 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2934 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2935 if (npt_enabled) {
2936 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2937 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2938 } else
2939 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2940
2941 /* Guest paging mode is active - reset mmu */
2942 kvm_mmu_reset_context(&svm->vcpu);
2943
2944 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2945 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2946 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2947 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2948
2949 /* In case we don't even reach vcpu_run, the fields are not updated */
2950 svm->vmcb->save.rax = nested_vmcb->save.rax;
2951 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2952 svm->vmcb->save.rip = nested_vmcb->save.rip;
2953 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2954 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2955 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2956
2957 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2958 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2959
2960 /* cache intercepts */
2961 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2962 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2963 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2964 svm->nested.intercept = nested_vmcb->control.intercept;
2965
2966 svm_flush_tlb(&svm->vcpu);
2967 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2968 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2969 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2970 else
2971 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2972
2973 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2974 /* We only want the cr8 intercept bits of the guest */
2975 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2976 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2977 }
2978
2979 /* We don't want to see VMMCALLs from a nested guest */
2980 clr_intercept(svm, INTERCEPT_VMMCALL);
2981
2982 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2983 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2984 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2985 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2986 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2987 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2988
2989 nested_svm_unmap(page);
2990
2991 /* Enter Guest-Mode */
2992 enter_guest_mode(&svm->vcpu);
2993
2994 /*
2995 * Merge guest and host intercepts - must be called with vcpu in
2996 * guest-mode to take affect here
2997 */
2998 recalc_intercepts(svm);
2999
3000 svm->nested.vmcb = vmcb_gpa;
3001
3002 enable_gif(svm);
3003
3004 mark_all_dirty(svm->vmcb);
3005
3006 return true;
3007}
3008
3009static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3010{
3011 to_vmcb->save.fs = from_vmcb->save.fs;
3012 to_vmcb->save.gs = from_vmcb->save.gs;
3013 to_vmcb->save.tr = from_vmcb->save.tr;
3014 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3015 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3016 to_vmcb->save.star = from_vmcb->save.star;
3017 to_vmcb->save.lstar = from_vmcb->save.lstar;
3018 to_vmcb->save.cstar = from_vmcb->save.cstar;
3019 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3020 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3021 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3022 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3023}
3024
3025static int vmload_interception(struct vcpu_svm *svm)
3026{
3027 struct vmcb *nested_vmcb;
3028 struct page *page;
3029
3030 if (nested_svm_check_permissions(svm))
3031 return 1;
3032
3033 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3034 if (!nested_vmcb)
3035 return 1;
3036
3037 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3038 skip_emulated_instruction(&svm->vcpu);
3039
3040 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3041 nested_svm_unmap(page);
3042
3043 return 1;
3044}
3045
3046static int vmsave_interception(struct vcpu_svm *svm)
3047{
3048 struct vmcb *nested_vmcb;
3049 struct page *page;
3050
3051 if (nested_svm_check_permissions(svm))
3052 return 1;
3053
3054 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3055 if (!nested_vmcb)
3056 return 1;
3057
3058 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3059 skip_emulated_instruction(&svm->vcpu);
3060
3061 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3062 nested_svm_unmap(page);
3063
3064 return 1;
3065}
3066
3067static int vmrun_interception(struct vcpu_svm *svm)
3068{
3069 if (nested_svm_check_permissions(svm))
3070 return 1;
3071
3072 /* Save rip after vmrun instruction */
3073 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3074
3075 if (!nested_svm_vmrun(svm))
3076 return 1;
3077
3078 if (!nested_svm_vmrun_msrpm(svm))
3079 goto failed;
3080
3081 return 1;
3082
3083failed:
3084
3085 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3086 svm->vmcb->control.exit_code_hi = 0;
3087 svm->vmcb->control.exit_info_1 = 0;
3088 svm->vmcb->control.exit_info_2 = 0;
3089
3090 nested_svm_vmexit(svm);
3091
3092 return 1;
3093}
3094
3095static int stgi_interception(struct vcpu_svm *svm)
3096{
3097 if (nested_svm_check_permissions(svm))
3098 return 1;
3099
3100 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3101 skip_emulated_instruction(&svm->vcpu);
3102 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3103
3104 enable_gif(svm);
3105
3106 return 1;
3107}
3108
3109static int clgi_interception(struct vcpu_svm *svm)
3110{
3111 if (nested_svm_check_permissions(svm))
3112 return 1;
3113
3114 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3115 skip_emulated_instruction(&svm->vcpu);
3116
3117 disable_gif(svm);
3118
3119 /* After a CLGI no interrupts should come */
3120 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3121 svm_clear_vintr(svm);
3122 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3123 mark_dirty(svm->vmcb, VMCB_INTR);
3124 }
3125
3126 return 1;
3127}
3128
3129static int invlpga_interception(struct vcpu_svm *svm)
3130{
3131 struct kvm_vcpu *vcpu = &svm->vcpu;
3132
3133 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3134 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3135
3136 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3137 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3138
3139 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3140 skip_emulated_instruction(&svm->vcpu);
3141 return 1;
3142}
3143
3144static int skinit_interception(struct vcpu_svm *svm)
3145{
3146 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3147
3148 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3149 return 1;
3150}
3151
3152static int wbinvd_interception(struct vcpu_svm *svm)
3153{
3154 return kvm_emulate_wbinvd(&svm->vcpu);
3155}
3156
3157static int xsetbv_interception(struct vcpu_svm *svm)
3158{
3159 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3160 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3161
3162 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3163 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3164 skip_emulated_instruction(&svm->vcpu);
3165 }
3166
3167 return 1;
3168}
3169
3170static int task_switch_interception(struct vcpu_svm *svm)
3171{
3172 u16 tss_selector;
3173 int reason;
3174 int int_type = svm->vmcb->control.exit_int_info &
3175 SVM_EXITINTINFO_TYPE_MASK;
3176 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3177 uint32_t type =
3178 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3179 uint32_t idt_v =
3180 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3181 bool has_error_code = false;
3182 u32 error_code = 0;
3183
3184 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3185
3186 if (svm->vmcb->control.exit_info_2 &
3187 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3188 reason = TASK_SWITCH_IRET;
3189 else if (svm->vmcb->control.exit_info_2 &
3190 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3191 reason = TASK_SWITCH_JMP;
3192 else if (idt_v)
3193 reason = TASK_SWITCH_GATE;
3194 else
3195 reason = TASK_SWITCH_CALL;
3196
3197 if (reason == TASK_SWITCH_GATE) {
3198 switch (type) {
3199 case SVM_EXITINTINFO_TYPE_NMI:
3200 svm->vcpu.arch.nmi_injected = false;
3201 break;
3202 case SVM_EXITINTINFO_TYPE_EXEPT:
3203 if (svm->vmcb->control.exit_info_2 &
3204 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3205 has_error_code = true;
3206 error_code =
3207 (u32)svm->vmcb->control.exit_info_2;
3208 }
3209 kvm_clear_exception_queue(&svm->vcpu);
3210 break;
3211 case SVM_EXITINTINFO_TYPE_INTR:
3212 kvm_clear_interrupt_queue(&svm->vcpu);
3213 break;
3214 default:
3215 break;
3216 }
3217 }
3218
3219 if (reason != TASK_SWITCH_GATE ||
3220 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3221 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3222 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3223 skip_emulated_instruction(&svm->vcpu);
3224
3225 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3226 int_vec = -1;
3227
3228 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3229 has_error_code, error_code) == EMULATE_FAIL) {
3230 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3231 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3232 svm->vcpu.run->internal.ndata = 0;
3233 return 0;
3234 }
3235 return 1;
3236}
3237
3238static int cpuid_interception(struct vcpu_svm *svm)
3239{
3240 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3241 return kvm_emulate_cpuid(&svm->vcpu);
3242}
3243
3244static int iret_interception(struct vcpu_svm *svm)
3245{
3246 ++svm->vcpu.stat.nmi_window_exits;
3247 clr_intercept(svm, INTERCEPT_IRET);
3248 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3249 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3250 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3251 return 1;
3252}
3253
3254static int invlpg_interception(struct vcpu_svm *svm)
3255{
3256 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3257 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3258
3259 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3260 skip_emulated_instruction(&svm->vcpu);
3261 return 1;
3262}
3263
3264static int emulate_on_interception(struct vcpu_svm *svm)
3265{
3266 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3267}
3268
3269static int rdpmc_interception(struct vcpu_svm *svm)
3270{
3271 int err;
3272
3273 if (!static_cpu_has(X86_FEATURE_NRIPS))
3274 return emulate_on_interception(svm);
3275
3276 err = kvm_rdpmc(&svm->vcpu);
3277 return kvm_complete_insn_gp(&svm->vcpu, err);
3278}
3279
3280static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3281 unsigned long val)
3282{
3283 unsigned long cr0 = svm->vcpu.arch.cr0;
3284 bool ret = false;
3285 u64 intercept;
3286
3287 intercept = svm->nested.intercept;
3288
3289 if (!is_guest_mode(&svm->vcpu) ||
3290 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3291 return false;
3292
3293 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3294 val &= ~SVM_CR0_SELECTIVE_MASK;
3295
3296 if (cr0 ^ val) {
3297 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3298 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3299 }
3300
3301 return ret;
3302}
3303
3304#define CR_VALID (1ULL << 63)
3305
3306static int cr_interception(struct vcpu_svm *svm)
3307{
3308 int reg, cr;
3309 unsigned long val;
3310 int err;
3311
3312 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3313 return emulate_on_interception(svm);
3314
3315 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3316 return emulate_on_interception(svm);
3317
3318 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3319 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3320 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3321 else
3322 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3323
3324 err = 0;
3325 if (cr >= 16) { /* mov to cr */
3326 cr -= 16;
3327 val = kvm_register_read(&svm->vcpu, reg);
3328 switch (cr) {
3329 case 0:
3330 if (!check_selective_cr0_intercepted(svm, val))
3331 err = kvm_set_cr0(&svm->vcpu, val);
3332 else
3333 return 1;
3334
3335 break;
3336 case 3:
3337 err = kvm_set_cr3(&svm->vcpu, val);
3338 break;
3339 case 4:
3340 err = kvm_set_cr4(&svm->vcpu, val);
3341 break;
3342 case 8:
3343 err = kvm_set_cr8(&svm->vcpu, val);
3344 break;
3345 default:
3346 WARN(1, "unhandled write to CR%d", cr);
3347 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3348 return 1;
3349 }
3350 } else { /* mov from cr */
3351 switch (cr) {
3352 case 0:
3353 val = kvm_read_cr0(&svm->vcpu);
3354 break;
3355 case 2:
3356 val = svm->vcpu.arch.cr2;
3357 break;
3358 case 3:
3359 val = kvm_read_cr3(&svm->vcpu);
3360 break;
3361 case 4:
3362 val = kvm_read_cr4(&svm->vcpu);
3363 break;
3364 case 8:
3365 val = kvm_get_cr8(&svm->vcpu);
3366 break;
3367 default:
3368 WARN(1, "unhandled read from CR%d", cr);
3369 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3370 return 1;
3371 }
3372 kvm_register_write(&svm->vcpu, reg, val);
3373 }
3374 return kvm_complete_insn_gp(&svm->vcpu, err);
3375}
3376
3377static int dr_interception(struct vcpu_svm *svm)
3378{
3379 int reg, dr;
3380 unsigned long val;
3381
3382 if (svm->vcpu.guest_debug == 0) {
3383 /*
3384 * No more DR vmexits; force a reload of the debug registers
3385 * and reenter on this instruction. The next vmexit will
3386 * retrieve the full state of the debug registers.
3387 */
3388 clr_dr_intercepts(svm);
3389 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3390 return 1;
3391 }
3392
3393 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3394 return emulate_on_interception(svm);
3395
3396 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3397 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3398
3399 if (dr >= 16) { /* mov to DRn */
3400 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3401 return 1;
3402 val = kvm_register_read(&svm->vcpu, reg);
3403 kvm_set_dr(&svm->vcpu, dr - 16, val);
3404 } else {
3405 if (!kvm_require_dr(&svm->vcpu, dr))
3406 return 1;
3407 kvm_get_dr(&svm->vcpu, dr, &val);
3408 kvm_register_write(&svm->vcpu, reg, val);
3409 }
3410
3411 skip_emulated_instruction(&svm->vcpu);
3412
3413 return 1;
3414}
3415
3416static int cr8_write_interception(struct vcpu_svm *svm)
3417{
3418 struct kvm_run *kvm_run = svm->vcpu.run;
3419 int r;
3420
3421 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3422 /* instruction emulation calls kvm_set_cr8() */
3423 r = cr_interception(svm);
3424 if (lapic_in_kernel(&svm->vcpu))
3425 return r;
3426 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3427 return r;
3428 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3429 return 0;
3430}
3431
3432static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3433{
3434 struct vcpu_svm *svm = to_svm(vcpu);
3435
3436 switch (msr_info->index) {
3437 case MSR_IA32_TSC: {
3438 msr_info->data = svm->vmcb->control.tsc_offset +
3439 kvm_scale_tsc(vcpu, rdtsc());
3440
3441 break;
3442 }
3443 case MSR_STAR:
3444 msr_info->data = svm->vmcb->save.star;
3445 break;
3446#ifdef CONFIG_X86_64
3447 case MSR_LSTAR:
3448 msr_info->data = svm->vmcb->save.lstar;
3449 break;
3450 case MSR_CSTAR:
3451 msr_info->data = svm->vmcb->save.cstar;
3452 break;
3453 case MSR_KERNEL_GS_BASE:
3454 msr_info->data = svm->vmcb->save.kernel_gs_base;
3455 break;
3456 case MSR_SYSCALL_MASK:
3457 msr_info->data = svm->vmcb->save.sfmask;
3458 break;
3459#endif
3460 case MSR_IA32_SYSENTER_CS:
3461 msr_info->data = svm->vmcb->save.sysenter_cs;
3462 break;
3463 case MSR_IA32_SYSENTER_EIP:
3464 msr_info->data = svm->sysenter_eip;
3465 break;
3466 case MSR_IA32_SYSENTER_ESP:
3467 msr_info->data = svm->sysenter_esp;
3468 break;
3469 case MSR_TSC_AUX:
3470 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3471 return 1;
3472 msr_info->data = svm->tsc_aux;
3473 break;
3474 /*
3475 * Nobody will change the following 5 values in the VMCB so we can
3476 * safely return them on rdmsr. They will always be 0 until LBRV is
3477 * implemented.
3478 */
3479 case MSR_IA32_DEBUGCTLMSR:
3480 msr_info->data = svm->vmcb->save.dbgctl;
3481 break;
3482 case MSR_IA32_LASTBRANCHFROMIP:
3483 msr_info->data = svm->vmcb->save.br_from;
3484 break;
3485 case MSR_IA32_LASTBRANCHTOIP:
3486 msr_info->data = svm->vmcb->save.br_to;
3487 break;
3488 case MSR_IA32_LASTINTFROMIP:
3489 msr_info->data = svm->vmcb->save.last_excp_from;
3490 break;
3491 case MSR_IA32_LASTINTTOIP:
3492 msr_info->data = svm->vmcb->save.last_excp_to;
3493 break;
3494 case MSR_VM_HSAVE_PA:
3495 msr_info->data = svm->nested.hsave_msr;
3496 break;
3497 case MSR_VM_CR:
3498 msr_info->data = svm->nested.vm_cr_msr;
3499 break;
3500 case MSR_IA32_UCODE_REV:
3501 msr_info->data = 0x01000065;
3502 break;
3503 case MSR_F15H_IC_CFG: {
3504
3505 int family, model;
3506
3507 family = guest_cpuid_family(vcpu);
3508 model = guest_cpuid_model(vcpu);
3509
3510 if (family < 0 || model < 0)
3511 return kvm_get_msr_common(vcpu, msr_info);
3512
3513 msr_info->data = 0;
3514
3515 if (family == 0x15 &&
3516 (model >= 0x2 && model < 0x20))
3517 msr_info->data = 0x1E;
3518 }
3519 break;
3520 default:
3521 return kvm_get_msr_common(vcpu, msr_info);
3522 }
3523 return 0;
3524}
3525
3526static int rdmsr_interception(struct vcpu_svm *svm)
3527{
3528 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3529 struct msr_data msr_info;
3530
3531 msr_info.index = ecx;
3532 msr_info.host_initiated = false;
3533 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3534 trace_kvm_msr_read_ex(ecx);
3535 kvm_inject_gp(&svm->vcpu, 0);
3536 } else {
3537 trace_kvm_msr_read(ecx, msr_info.data);
3538
3539 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3540 msr_info.data & 0xffffffff);
3541 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3542 msr_info.data >> 32);
3543 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3544 skip_emulated_instruction(&svm->vcpu);
3545 }
3546 return 1;
3547}
3548
3549static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3550{
3551 struct vcpu_svm *svm = to_svm(vcpu);
3552 int svm_dis, chg_mask;
3553
3554 if (data & ~SVM_VM_CR_VALID_MASK)
3555 return 1;
3556
3557 chg_mask = SVM_VM_CR_VALID_MASK;
3558
3559 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3560 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3561
3562 svm->nested.vm_cr_msr &= ~chg_mask;
3563 svm->nested.vm_cr_msr |= (data & chg_mask);
3564
3565 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3566
3567 /* check for svm_disable while efer.svme is set */
3568 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3569 return 1;
3570
3571 return 0;
3572}
3573
3574static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3575{
3576 struct vcpu_svm *svm = to_svm(vcpu);
3577
3578 u32 ecx = msr->index;
3579 u64 data = msr->data;
3580 switch (ecx) {
3581 case MSR_IA32_TSC:
3582 kvm_write_tsc(vcpu, msr);
3583 break;
3584 case MSR_STAR:
3585 svm->vmcb->save.star = data;
3586 break;
3587#ifdef CONFIG_X86_64
3588 case MSR_LSTAR:
3589 svm->vmcb->save.lstar = data;
3590 break;
3591 case MSR_CSTAR:
3592 svm->vmcb->save.cstar = data;
3593 break;
3594 case MSR_KERNEL_GS_BASE:
3595 svm->vmcb->save.kernel_gs_base = data;
3596 break;
3597 case MSR_SYSCALL_MASK:
3598 svm->vmcb->save.sfmask = data;
3599 break;
3600#endif
3601 case MSR_IA32_SYSENTER_CS:
3602 svm->vmcb->save.sysenter_cs = data;
3603 break;
3604 case MSR_IA32_SYSENTER_EIP:
3605 svm->sysenter_eip = data;
3606 svm->vmcb->save.sysenter_eip = data;
3607 break;
3608 case MSR_IA32_SYSENTER_ESP:
3609 svm->sysenter_esp = data;
3610 svm->vmcb->save.sysenter_esp = data;
3611 break;
3612 case MSR_TSC_AUX:
3613 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3614 return 1;
3615
3616 /*
3617 * This is rare, so we update the MSR here instead of using
3618 * direct_access_msrs. Doing that would require a rdmsr in
3619 * svm_vcpu_put.
3620 */
3621 svm->tsc_aux = data;
3622 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3623 break;
3624 case MSR_IA32_DEBUGCTLMSR:
3625 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3626 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3627 __func__, data);
3628 break;
3629 }
3630 if (data & DEBUGCTL_RESERVED_BITS)
3631 return 1;
3632
3633 svm->vmcb->save.dbgctl = data;
3634 mark_dirty(svm->vmcb, VMCB_LBR);
3635 if (data & (1ULL<<0))
3636 svm_enable_lbrv(svm);
3637 else
3638 svm_disable_lbrv(svm);
3639 break;
3640 case MSR_VM_HSAVE_PA:
3641 svm->nested.hsave_msr = data;
3642 break;
3643 case MSR_VM_CR:
3644 return svm_set_vm_cr(vcpu, data);
3645 case MSR_VM_IGNNE:
3646 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3647 break;
3648 case MSR_IA32_APICBASE:
3649 if (kvm_vcpu_apicv_active(vcpu))
3650 avic_update_vapic_bar(to_svm(vcpu), data);
3651 /* Follow through */
3652 default:
3653 return kvm_set_msr_common(vcpu, msr);
3654 }
3655 return 0;
3656}
3657
3658static int wrmsr_interception(struct vcpu_svm *svm)
3659{
3660 struct msr_data msr;
3661 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3662 u64 data = kvm_read_edx_eax(&svm->vcpu);
3663
3664 msr.data = data;
3665 msr.index = ecx;
3666 msr.host_initiated = false;
3667
3668 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3669 if (kvm_set_msr(&svm->vcpu, &msr)) {
3670 trace_kvm_msr_write_ex(ecx, data);
3671 kvm_inject_gp(&svm->vcpu, 0);
3672 } else {
3673 trace_kvm_msr_write(ecx, data);
3674 skip_emulated_instruction(&svm->vcpu);
3675 }
3676 return 1;
3677}
3678
3679static int msr_interception(struct vcpu_svm *svm)
3680{
3681 if (svm->vmcb->control.exit_info_1)
3682 return wrmsr_interception(svm);
3683 else
3684 return rdmsr_interception(svm);
3685}
3686
3687static int interrupt_window_interception(struct vcpu_svm *svm)
3688{
3689 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3690 svm_clear_vintr(svm);
3691 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3692 mark_dirty(svm->vmcb, VMCB_INTR);
3693 ++svm->vcpu.stat.irq_window_exits;
3694 return 1;
3695}
3696
3697static int pause_interception(struct vcpu_svm *svm)
3698{
3699 kvm_vcpu_on_spin(&(svm->vcpu));
3700 return 1;
3701}
3702
3703static int nop_interception(struct vcpu_svm *svm)
3704{
3705 skip_emulated_instruction(&(svm->vcpu));
3706 return 1;
3707}
3708
3709static int monitor_interception(struct vcpu_svm *svm)
3710{
3711 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3712 return nop_interception(svm);
3713}
3714
3715static int mwait_interception(struct vcpu_svm *svm)
3716{
3717 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3718 return nop_interception(svm);
3719}
3720
3721enum avic_ipi_failure_cause {
3722 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3723 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3724 AVIC_IPI_FAILURE_INVALID_TARGET,
3725 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3726};
3727
3728static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3729{
3730 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3731 u32 icrl = svm->vmcb->control.exit_info_1;
3732 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3733 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3734 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3735
3736 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3737
3738 switch (id) {
3739 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3740 /*
3741 * AVIC hardware handles the generation of
3742 * IPIs when the specified Message Type is Fixed
3743 * (also known as fixed delivery mode) and
3744 * the Trigger Mode is edge-triggered. The hardware
3745 * also supports self and broadcast delivery modes
3746 * specified via the Destination Shorthand(DSH)
3747 * field of the ICRL. Logical and physical APIC ID
3748 * formats are supported. All other IPI types cause
3749 * a #VMEXIT, which needs to emulated.
3750 */
3751 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3752 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3753 break;
3754 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3755 int i;
3756 struct kvm_vcpu *vcpu;
3757 struct kvm *kvm = svm->vcpu.kvm;
3758 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3759
3760 /*
3761 * At this point, we expect that the AVIC HW has already
3762 * set the appropriate IRR bits on the valid target
3763 * vcpus. So, we just need to kick the appropriate vcpu.
3764 */
3765 kvm_for_each_vcpu(i, vcpu, kvm) {
3766 bool m = kvm_apic_match_dest(vcpu, apic,
3767 icrl & KVM_APIC_SHORT_MASK,
3768 GET_APIC_DEST_FIELD(icrh),
3769 icrl & KVM_APIC_DEST_MASK);
3770
3771 if (m && !avic_vcpu_is_running(vcpu))
3772 kvm_vcpu_wake_up(vcpu);
3773 }
3774 break;
3775 }
3776 case AVIC_IPI_FAILURE_INVALID_TARGET:
3777 break;
3778 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3779 WARN_ONCE(1, "Invalid backing page\n");
3780 break;
3781 default:
3782 pr_err("Unknown IPI interception\n");
3783 }
3784
3785 return 1;
3786}
3787
3788static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3789{
3790 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3791 int index;
3792 u32 *logical_apic_id_table;
3793 int dlid = GET_APIC_LOGICAL_ID(ldr);
3794
3795 if (!dlid)
3796 return NULL;
3797
3798 if (flat) { /* flat */
3799 index = ffs(dlid) - 1;
3800 if (index > 7)
3801 return NULL;
3802 } else { /* cluster */
3803 int cluster = (dlid & 0xf0) >> 4;
3804 int apic = ffs(dlid & 0x0f) - 1;
3805
3806 if ((apic < 0) || (apic > 7) ||
3807 (cluster >= 0xf))
3808 return NULL;
3809 index = (cluster << 2) + apic;
3810 }
3811
3812 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3813
3814 return &logical_apic_id_table[index];
3815}
3816
3817static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3818 bool valid)
3819{
3820 bool flat;
3821 u32 *entry, new_entry;
3822
3823 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3824 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3825 if (!entry)
3826 return -EINVAL;
3827
3828 new_entry = READ_ONCE(*entry);
3829 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3830 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3831 if (valid)
3832 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3833 else
3834 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3835 WRITE_ONCE(*entry, new_entry);
3836
3837 return 0;
3838}
3839
3840static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3841{
3842 int ret;
3843 struct vcpu_svm *svm = to_svm(vcpu);
3844 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3845
3846 if (!ldr)
3847 return 1;
3848
3849 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3850 if (ret && svm->ldr_reg) {
3851 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3852 svm->ldr_reg = 0;
3853 } else {
3854 svm->ldr_reg = ldr;
3855 }
3856 return ret;
3857}
3858
3859static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3860{
3861 u64 *old, *new;
3862 struct vcpu_svm *svm = to_svm(vcpu);
3863 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3864 u32 id = (apic_id_reg >> 24) & 0xff;
3865
3866 if (vcpu->vcpu_id == id)
3867 return 0;
3868
3869 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3870 new = avic_get_physical_id_entry(vcpu, id);
3871 if (!new || !old)
3872 return 1;
3873
3874 /* We need to move physical_id_entry to new offset */
3875 *new = *old;
3876 *old = 0ULL;
3877 to_svm(vcpu)->avic_physical_id_cache = new;
3878
3879 /*
3880 * Also update the guest physical APIC ID in the logical
3881 * APIC ID table entry if already setup the LDR.
3882 */
3883 if (svm->ldr_reg)
3884 avic_handle_ldr_update(vcpu);
3885
3886 return 0;
3887}
3888
3889static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3890{
3891 struct vcpu_svm *svm = to_svm(vcpu);
3892 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3893 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3894 u32 mod = (dfr >> 28) & 0xf;
3895
3896 /*
3897 * We assume that all local APICs are using the same type.
3898 * If this changes, we need to flush the AVIC logical
3899 * APID id table.
3900 */
3901 if (vm_data->ldr_mode == mod)
3902 return 0;
3903
3904 clear_page(page_address(vm_data->avic_logical_id_table_page));
3905 vm_data->ldr_mode = mod;
3906
3907 if (svm->ldr_reg)
3908 avic_handle_ldr_update(vcpu);
3909 return 0;
3910}
3911
3912static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3913{
3914 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3915 u32 offset = svm->vmcb->control.exit_info_1 &
3916 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3917
3918 switch (offset) {
3919 case APIC_ID:
3920 if (avic_handle_apic_id_update(&svm->vcpu))
3921 return 0;
3922 break;
3923 case APIC_LDR:
3924 if (avic_handle_ldr_update(&svm->vcpu))
3925 return 0;
3926 break;
3927 case APIC_DFR:
3928 avic_handle_dfr_update(&svm->vcpu);
3929 break;
3930 default:
3931 break;
3932 }
3933
3934 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3935
3936 return 1;
3937}
3938
3939static bool is_avic_unaccelerated_access_trap(u32 offset)
3940{
3941 bool ret = false;
3942
3943 switch (offset) {
3944 case APIC_ID:
3945 case APIC_EOI:
3946 case APIC_RRR:
3947 case APIC_LDR:
3948 case APIC_DFR:
3949 case APIC_SPIV:
3950 case APIC_ESR:
3951 case APIC_ICR:
3952 case APIC_LVTT:
3953 case APIC_LVTTHMR:
3954 case APIC_LVTPC:
3955 case APIC_LVT0:
3956 case APIC_LVT1:
3957 case APIC_LVTERR:
3958 case APIC_TMICT:
3959 case APIC_TDCR:
3960 ret = true;
3961 break;
3962 default:
3963 break;
3964 }
3965 return ret;
3966}
3967
3968static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3969{
3970 int ret = 0;
3971 u32 offset = svm->vmcb->control.exit_info_1 &
3972 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3973 u32 vector = svm->vmcb->control.exit_info_2 &
3974 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3975 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3976 AVIC_UNACCEL_ACCESS_WRITE_MASK;
3977 bool trap = is_avic_unaccelerated_access_trap(offset);
3978
3979 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3980 trap, write, vector);
3981 if (trap) {
3982 /* Handling Trap */
3983 WARN_ONCE(!write, "svm: Handling trap read.\n");
3984 ret = avic_unaccel_trap_write(svm);
3985 } else {
3986 /* Handling Fault */
3987 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3988 }
3989
3990 return ret;
3991}
3992
3993static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3994 [SVM_EXIT_READ_CR0] = cr_interception,
3995 [SVM_EXIT_READ_CR3] = cr_interception,
3996 [SVM_EXIT_READ_CR4] = cr_interception,
3997 [SVM_EXIT_READ_CR8] = cr_interception,
3998 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3999 [SVM_EXIT_WRITE_CR0] = cr_interception,
4000 [SVM_EXIT_WRITE_CR3] = cr_interception,
4001 [SVM_EXIT_WRITE_CR4] = cr_interception,
4002 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4003 [SVM_EXIT_READ_DR0] = dr_interception,
4004 [SVM_EXIT_READ_DR1] = dr_interception,
4005 [SVM_EXIT_READ_DR2] = dr_interception,
4006 [SVM_EXIT_READ_DR3] = dr_interception,
4007 [SVM_EXIT_READ_DR4] = dr_interception,
4008 [SVM_EXIT_READ_DR5] = dr_interception,
4009 [SVM_EXIT_READ_DR6] = dr_interception,
4010 [SVM_EXIT_READ_DR7] = dr_interception,
4011 [SVM_EXIT_WRITE_DR0] = dr_interception,
4012 [SVM_EXIT_WRITE_DR1] = dr_interception,
4013 [SVM_EXIT_WRITE_DR2] = dr_interception,
4014 [SVM_EXIT_WRITE_DR3] = dr_interception,
4015 [SVM_EXIT_WRITE_DR4] = dr_interception,
4016 [SVM_EXIT_WRITE_DR5] = dr_interception,
4017 [SVM_EXIT_WRITE_DR6] = dr_interception,
4018 [SVM_EXIT_WRITE_DR7] = dr_interception,
4019 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4020 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4021 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4022 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4023 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
4024 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4025 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4026 [SVM_EXIT_INTR] = intr_interception,
4027 [SVM_EXIT_NMI] = nmi_interception,
4028 [SVM_EXIT_SMI] = nop_on_interception,
4029 [SVM_EXIT_INIT] = nop_on_interception,
4030 [SVM_EXIT_VINTR] = interrupt_window_interception,
4031 [SVM_EXIT_RDPMC] = rdpmc_interception,
4032 [SVM_EXIT_CPUID] = cpuid_interception,
4033 [SVM_EXIT_IRET] = iret_interception,
4034 [SVM_EXIT_INVD] = emulate_on_interception,
4035 [SVM_EXIT_PAUSE] = pause_interception,
4036 [SVM_EXIT_HLT] = halt_interception,
4037 [SVM_EXIT_INVLPG] = invlpg_interception,
4038 [SVM_EXIT_INVLPGA] = invlpga_interception,
4039 [SVM_EXIT_IOIO] = io_interception,
4040 [SVM_EXIT_MSR] = msr_interception,
4041 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4042 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4043 [SVM_EXIT_VMRUN] = vmrun_interception,
4044 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4045 [SVM_EXIT_VMLOAD] = vmload_interception,
4046 [SVM_EXIT_VMSAVE] = vmsave_interception,
4047 [SVM_EXIT_STGI] = stgi_interception,
4048 [SVM_EXIT_CLGI] = clgi_interception,
4049 [SVM_EXIT_SKINIT] = skinit_interception,
4050 [SVM_EXIT_WBINVD] = wbinvd_interception,
4051 [SVM_EXIT_MONITOR] = monitor_interception,
4052 [SVM_EXIT_MWAIT] = mwait_interception,
4053 [SVM_EXIT_XSETBV] = xsetbv_interception,
4054 [SVM_EXIT_NPF] = pf_interception,
4055 [SVM_EXIT_RSM] = emulate_on_interception,
4056 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4057 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4058};
4059
4060static void dump_vmcb(struct kvm_vcpu *vcpu)
4061{
4062 struct vcpu_svm *svm = to_svm(vcpu);
4063 struct vmcb_control_area *control = &svm->vmcb->control;
4064 struct vmcb_save_area *save = &svm->vmcb->save;
4065
4066 pr_err("VMCB Control Area:\n");
4067 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4068 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4069 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4070 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4071 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4072 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4073 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4074 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4075 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4076 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4077 pr_err("%-20s%d\n", "asid:", control->asid);
4078 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4079 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4080 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4081 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4082 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4083 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4084 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4085 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4086 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4087 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4088 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4089 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4090 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4091 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4092 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4093 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4094 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4095 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4096 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4097 pr_err("VMCB State Save Area:\n");
4098 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4099 "es:",
4100 save->es.selector, save->es.attrib,
4101 save->es.limit, save->es.base);
4102 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4103 "cs:",
4104 save->cs.selector, save->cs.attrib,
4105 save->cs.limit, save->cs.base);
4106 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4107 "ss:",
4108 save->ss.selector, save->ss.attrib,
4109 save->ss.limit, save->ss.base);
4110 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4111 "ds:",
4112 save->ds.selector, save->ds.attrib,
4113 save->ds.limit, save->ds.base);
4114 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4115 "fs:",
4116 save->fs.selector, save->fs.attrib,
4117 save->fs.limit, save->fs.base);
4118 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4119 "gs:",
4120 save->gs.selector, save->gs.attrib,
4121 save->gs.limit, save->gs.base);
4122 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4123 "gdtr:",
4124 save->gdtr.selector, save->gdtr.attrib,
4125 save->gdtr.limit, save->gdtr.base);
4126 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4127 "ldtr:",
4128 save->ldtr.selector, save->ldtr.attrib,
4129 save->ldtr.limit, save->ldtr.base);
4130 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4131 "idtr:",
4132 save->idtr.selector, save->idtr.attrib,
4133 save->idtr.limit, save->idtr.base);
4134 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4135 "tr:",
4136 save->tr.selector, save->tr.attrib,
4137 save->tr.limit, save->tr.base);
4138 pr_err("cpl: %d efer: %016llx\n",
4139 save->cpl, save->efer);
4140 pr_err("%-15s %016llx %-13s %016llx\n",
4141 "cr0:", save->cr0, "cr2:", save->cr2);
4142 pr_err("%-15s %016llx %-13s %016llx\n",
4143 "cr3:", save->cr3, "cr4:", save->cr4);
4144 pr_err("%-15s %016llx %-13s %016llx\n",
4145 "dr6:", save->dr6, "dr7:", save->dr7);
4146 pr_err("%-15s %016llx %-13s %016llx\n",
4147 "rip:", save->rip, "rflags:", save->rflags);
4148 pr_err("%-15s %016llx %-13s %016llx\n",
4149 "rsp:", save->rsp, "rax:", save->rax);
4150 pr_err("%-15s %016llx %-13s %016llx\n",
4151 "star:", save->star, "lstar:", save->lstar);
4152 pr_err("%-15s %016llx %-13s %016llx\n",
4153 "cstar:", save->cstar, "sfmask:", save->sfmask);
4154 pr_err("%-15s %016llx %-13s %016llx\n",
4155 "kernel_gs_base:", save->kernel_gs_base,
4156 "sysenter_cs:", save->sysenter_cs);
4157 pr_err("%-15s %016llx %-13s %016llx\n",
4158 "sysenter_esp:", save->sysenter_esp,
4159 "sysenter_eip:", save->sysenter_eip);
4160 pr_err("%-15s %016llx %-13s %016llx\n",
4161 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4162 pr_err("%-15s %016llx %-13s %016llx\n",
4163 "br_from:", save->br_from, "br_to:", save->br_to);
4164 pr_err("%-15s %016llx %-13s %016llx\n",
4165 "excp_from:", save->last_excp_from,
4166 "excp_to:", save->last_excp_to);
4167}
4168
4169static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4170{
4171 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4172
4173 *info1 = control->exit_info_1;
4174 *info2 = control->exit_info_2;
4175}
4176
4177static int handle_exit(struct kvm_vcpu *vcpu)
4178{
4179 struct vcpu_svm *svm = to_svm(vcpu);
4180 struct kvm_run *kvm_run = vcpu->run;
4181 u32 exit_code = svm->vmcb->control.exit_code;
4182
4183 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4184
4185 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4186 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4187 if (npt_enabled)
4188 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4189
4190 if (unlikely(svm->nested.exit_required)) {
4191 nested_svm_vmexit(svm);
4192 svm->nested.exit_required = false;
4193
4194 return 1;
4195 }
4196
4197 if (is_guest_mode(vcpu)) {
4198 int vmexit;
4199
4200 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4201 svm->vmcb->control.exit_info_1,
4202 svm->vmcb->control.exit_info_2,
4203 svm->vmcb->control.exit_int_info,
4204 svm->vmcb->control.exit_int_info_err,
4205 KVM_ISA_SVM);
4206
4207 vmexit = nested_svm_exit_special(svm);
4208
4209 if (vmexit == NESTED_EXIT_CONTINUE)
4210 vmexit = nested_svm_exit_handled(svm);
4211
4212 if (vmexit == NESTED_EXIT_DONE)
4213 return 1;
4214 }
4215
4216 svm_complete_interrupts(svm);
4217
4218 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4219 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4220 kvm_run->fail_entry.hardware_entry_failure_reason
4221 = svm->vmcb->control.exit_code;
4222 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4223 dump_vmcb(vcpu);
4224 return 0;
4225 }
4226
4227 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4228 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4229 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4230 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4231 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4232 "exit_code 0x%x\n",
4233 __func__, svm->vmcb->control.exit_int_info,
4234 exit_code);
4235
4236 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4237 || !svm_exit_handlers[exit_code]) {
4238 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4239 kvm_queue_exception(vcpu, UD_VECTOR);
4240 return 1;
4241 }
4242
4243 return svm_exit_handlers[exit_code](svm);
4244}
4245
4246static void reload_tss(struct kvm_vcpu *vcpu)
4247{
4248 int cpu = raw_smp_processor_id();
4249
4250 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4251 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4252 load_TR_desc();
4253}
4254
4255static void pre_svm_run(struct vcpu_svm *svm)
4256{
4257 int cpu = raw_smp_processor_id();
4258
4259 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4260
4261 /* FIXME: handle wraparound of asid_generation */
4262 if (svm->asid_generation != sd->asid_generation)
4263 new_asid(svm, sd);
4264}
4265
4266static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4267{
4268 struct vcpu_svm *svm = to_svm(vcpu);
4269
4270 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4271 vcpu->arch.hflags |= HF_NMI_MASK;
4272 set_intercept(svm, INTERCEPT_IRET);
4273 ++vcpu->stat.nmi_injections;
4274}
4275
4276static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4277{
4278 struct vmcb_control_area *control;
4279
4280 /* The following fields are ignored when AVIC is enabled */
4281 control = &svm->vmcb->control;
4282 control->int_vector = irq;
4283 control->int_ctl &= ~V_INTR_PRIO_MASK;
4284 control->int_ctl |= V_IRQ_MASK |
4285 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4286 mark_dirty(svm->vmcb, VMCB_INTR);
4287}
4288
4289static void svm_set_irq(struct kvm_vcpu *vcpu)
4290{
4291 struct vcpu_svm *svm = to_svm(vcpu);
4292
4293 BUG_ON(!(gif_set(svm)));
4294
4295 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4296 ++vcpu->stat.irq_injections;
4297
4298 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4299 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4300}
4301
4302static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4303{
4304 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4305}
4306
4307static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4308{
4309 struct vcpu_svm *svm = to_svm(vcpu);
4310
4311 if (svm_nested_virtualize_tpr(vcpu) ||
4312 kvm_vcpu_apicv_active(vcpu))
4313 return;
4314
4315 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4316
4317 if (irr == -1)
4318 return;
4319
4320 if (tpr >= irr)
4321 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4322}
4323
4324static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4325{
4326 return;
4327}
4328
4329static bool svm_get_enable_apicv(void)
4330{
4331 return avic;
4332}
4333
4334static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4335{
4336}
4337
4338static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4339{
4340}
4341
4342/* Note: Currently only used by Hyper-V. */
4343static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4344{
4345 struct vcpu_svm *svm = to_svm(vcpu);
4346 struct vmcb *vmcb = svm->vmcb;
4347
4348 if (!avic)
4349 return;
4350
4351 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4352 mark_dirty(vmcb, VMCB_INTR);
4353}
4354
4355static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4356{
4357 return;
4358}
4359
4360static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4361{
4362 return;
4363}
4364
4365static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4366{
4367 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4368 smp_mb__after_atomic();
4369
4370 if (avic_vcpu_is_running(vcpu))
4371 wrmsrl(SVM_AVIC_DOORBELL,
4372 kvm_cpu_get_apicid(vcpu->cpu));
4373 else
4374 kvm_vcpu_wake_up(vcpu);
4375}
4376
4377static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4378{
4379 unsigned long flags;
4380 struct amd_svm_iommu_ir *cur;
4381
4382 spin_lock_irqsave(&svm->ir_list_lock, flags);
4383 list_for_each_entry(cur, &svm->ir_list, node) {
4384 if (cur->data != pi->ir_data)
4385 continue;
4386 list_del(&cur->node);
4387 kfree(cur);
4388 break;
4389 }
4390 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4391}
4392
4393static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4394{
4395 int ret = 0;
4396 unsigned long flags;
4397 struct amd_svm_iommu_ir *ir;
4398
4399 /**
4400 * In some cases, the existing irte is updaed and re-set,
4401 * so we need to check here if it's already been * added
4402 * to the ir_list.
4403 */
4404 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4405 struct kvm *kvm = svm->vcpu.kvm;
4406 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4407 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4408 struct vcpu_svm *prev_svm;
4409
4410 if (!prev_vcpu) {
4411 ret = -EINVAL;
4412 goto out;
4413 }
4414
4415 prev_svm = to_svm(prev_vcpu);
4416 svm_ir_list_del(prev_svm, pi);
4417 }
4418
4419 /**
4420 * Allocating new amd_iommu_pi_data, which will get
4421 * add to the per-vcpu ir_list.
4422 */
4423 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4424 if (!ir) {
4425 ret = -ENOMEM;
4426 goto out;
4427 }
4428 ir->data = pi->ir_data;
4429
4430 spin_lock_irqsave(&svm->ir_list_lock, flags);
4431 list_add(&ir->node, &svm->ir_list);
4432 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4433out:
4434 return ret;
4435}
4436
4437/**
4438 * Note:
4439 * The HW cannot support posting multicast/broadcast
4440 * interrupts to a vCPU. So, we still use legacy interrupt
4441 * remapping for these kind of interrupts.
4442 *
4443 * For lowest-priority interrupts, we only support
4444 * those with single CPU as the destination, e.g. user
4445 * configures the interrupts via /proc/irq or uses
4446 * irqbalance to make the interrupts single-CPU.
4447 */
4448static int
4449get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4450 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4451{
4452 struct kvm_lapic_irq irq;
4453 struct kvm_vcpu *vcpu = NULL;
4454
4455 kvm_set_msi_irq(kvm, e, &irq);
4456
4457 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4458 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4459 __func__, irq.vector);
4460 return -1;
4461 }
4462
4463 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4464 irq.vector);
4465 *svm = to_svm(vcpu);
4466 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4467 vcpu_info->vector = irq.vector;
4468
4469 return 0;
4470}
4471
4472/*
4473 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4474 *
4475 * @kvm: kvm
4476 * @host_irq: host irq of the interrupt
4477 * @guest_irq: gsi of the interrupt
4478 * @set: set or unset PI
4479 * returns 0 on success, < 0 on failure
4480 */
4481static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4482 uint32_t guest_irq, bool set)
4483{
4484 struct kvm_kernel_irq_routing_entry *e;
4485 struct kvm_irq_routing_table *irq_rt;
4486 int idx, ret = -EINVAL;
4487
4488 if (!kvm_arch_has_assigned_device(kvm) ||
4489 !irq_remapping_cap(IRQ_POSTING_CAP))
4490 return 0;
4491
4492 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4493 __func__, host_irq, guest_irq, set);
4494
4495 idx = srcu_read_lock(&kvm->irq_srcu);
4496 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4497 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4498
4499 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4500 struct vcpu_data vcpu_info;
4501 struct vcpu_svm *svm = NULL;
4502
4503 if (e->type != KVM_IRQ_ROUTING_MSI)
4504 continue;
4505
4506 /**
4507 * Here, we setup with legacy mode in the following cases:
4508 * 1. When cannot target interrupt to a specific vcpu.
4509 * 2. Unsetting posted interrupt.
4510 * 3. APIC virtialization is disabled for the vcpu.
4511 */
4512 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4513 kvm_vcpu_apicv_active(&svm->vcpu)) {
4514 struct amd_iommu_pi_data pi;
4515
4516 /* Try to enable guest_mode in IRTE */
4517 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4518 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4519 svm->vcpu.vcpu_id);
4520 pi.is_guest_mode = true;
4521 pi.vcpu_data = &vcpu_info;
4522 ret = irq_set_vcpu_affinity(host_irq, &pi);
4523
4524 /**
4525 * Here, we successfully setting up vcpu affinity in
4526 * IOMMU guest mode. Now, we need to store the posted
4527 * interrupt information in a per-vcpu ir_list so that
4528 * we can reference to them directly when we update vcpu
4529 * scheduling information in IOMMU irte.
4530 */
4531 if (!ret && pi.is_guest_mode)
4532 svm_ir_list_add(svm, &pi);
4533 } else {
4534 /* Use legacy mode in IRTE */
4535 struct amd_iommu_pi_data pi;
4536
4537 /**
4538 * Here, pi is used to:
4539 * - Tell IOMMU to use legacy mode for this interrupt.
4540 * - Retrieve ga_tag of prior interrupt remapping data.
4541 */
4542 pi.is_guest_mode = false;
4543 ret = irq_set_vcpu_affinity(host_irq, &pi);
4544
4545 /**
4546 * Check if the posted interrupt was previously
4547 * setup with the guest_mode by checking if the ga_tag
4548 * was cached. If so, we need to clean up the per-vcpu
4549 * ir_list.
4550 */
4551 if (!ret && pi.prev_ga_tag) {
4552 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4553 struct kvm_vcpu *vcpu;
4554
4555 vcpu = kvm_get_vcpu_by_id(kvm, id);
4556 if (vcpu)
4557 svm_ir_list_del(to_svm(vcpu), &pi);
4558 }
4559 }
4560
4561 if (!ret && svm) {
4562 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4563 host_irq, e->gsi,
4564 vcpu_info.vector,
4565 vcpu_info.pi_desc_addr, set);
4566 }
4567
4568 if (ret < 0) {
4569 pr_err("%s: failed to update PI IRTE\n", __func__);
4570 goto out;
4571 }
4572 }
4573
4574 ret = 0;
4575out:
4576 srcu_read_unlock(&kvm->irq_srcu, idx);
4577 return ret;
4578}
4579
4580static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4581{
4582 struct vcpu_svm *svm = to_svm(vcpu);
4583 struct vmcb *vmcb = svm->vmcb;
4584 int ret;
4585 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4586 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4587 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4588
4589 return ret;
4590}
4591
4592static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4593{
4594 struct vcpu_svm *svm = to_svm(vcpu);
4595
4596 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4597}
4598
4599static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4600{
4601 struct vcpu_svm *svm = to_svm(vcpu);
4602
4603 if (masked) {
4604 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4605 set_intercept(svm, INTERCEPT_IRET);
4606 } else {
4607 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4608 clr_intercept(svm, INTERCEPT_IRET);
4609 }
4610}
4611
4612static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4613{
4614 struct vcpu_svm *svm = to_svm(vcpu);
4615 struct vmcb *vmcb = svm->vmcb;
4616 int ret;
4617
4618 if (!gif_set(svm) ||
4619 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4620 return 0;
4621
4622 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4623
4624 if (is_guest_mode(vcpu))
4625 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4626
4627 return ret;
4628}
4629
4630static void enable_irq_window(struct kvm_vcpu *vcpu)
4631{
4632 struct vcpu_svm *svm = to_svm(vcpu);
4633
4634 if (kvm_vcpu_apicv_active(vcpu))
4635 return;
4636
4637 /*
4638 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4639 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4640 * get that intercept, this function will be called again though and
4641 * we'll get the vintr intercept.
4642 */
4643 if (gif_set(svm) && nested_svm_intr(svm)) {
4644 svm_set_vintr(svm);
4645 svm_inject_irq(svm, 0x0);
4646 }
4647}
4648
4649static void enable_nmi_window(struct kvm_vcpu *vcpu)
4650{
4651 struct vcpu_svm *svm = to_svm(vcpu);
4652
4653 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4654 == HF_NMI_MASK)
4655 return; /* IRET will cause a vm exit */
4656
4657 /*
4658 * Something prevents NMI from been injected. Single step over possible
4659 * problem (IRET or exception injection or interrupt shadow)
4660 */
4661 svm->nmi_singlestep = true;
4662 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4663}
4664
4665static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4666{
4667 return 0;
4668}
4669
4670static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4671{
4672 struct vcpu_svm *svm = to_svm(vcpu);
4673
4674 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4675 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4676 else
4677 svm->asid_generation--;
4678}
4679
4680static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4681{
4682}
4683
4684static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4685{
4686 struct vcpu_svm *svm = to_svm(vcpu);
4687
4688 if (svm_nested_virtualize_tpr(vcpu))
4689 return;
4690
4691 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4692 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4693 kvm_set_cr8(vcpu, cr8);
4694 }
4695}
4696
4697static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4698{
4699 struct vcpu_svm *svm = to_svm(vcpu);
4700 u64 cr8;
4701
4702 if (svm_nested_virtualize_tpr(vcpu) ||
4703 kvm_vcpu_apicv_active(vcpu))
4704 return;
4705
4706 cr8 = kvm_get_cr8(vcpu);
4707 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4708 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4709}
4710
4711static void svm_complete_interrupts(struct vcpu_svm *svm)
4712{
4713 u8 vector;
4714 int type;
4715 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4716 unsigned int3_injected = svm->int3_injected;
4717
4718 svm->int3_injected = 0;
4719
4720 /*
4721 * If we've made progress since setting HF_IRET_MASK, we've
4722 * executed an IRET and can allow NMI injection.
4723 */
4724 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4725 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4726 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4727 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4728 }
4729
4730 svm->vcpu.arch.nmi_injected = false;
4731 kvm_clear_exception_queue(&svm->vcpu);
4732 kvm_clear_interrupt_queue(&svm->vcpu);
4733
4734 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4735 return;
4736
4737 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4738
4739 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4740 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4741
4742 switch (type) {
4743 case SVM_EXITINTINFO_TYPE_NMI:
4744 svm->vcpu.arch.nmi_injected = true;
4745 break;
4746 case SVM_EXITINTINFO_TYPE_EXEPT:
4747 /*
4748 * In case of software exceptions, do not reinject the vector,
4749 * but re-execute the instruction instead. Rewind RIP first
4750 * if we emulated INT3 before.
4751 */
4752 if (kvm_exception_is_soft(vector)) {
4753 if (vector == BP_VECTOR && int3_injected &&
4754 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4755 kvm_rip_write(&svm->vcpu,
4756 kvm_rip_read(&svm->vcpu) -
4757 int3_injected);
4758 break;
4759 }
4760 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4761 u32 err = svm->vmcb->control.exit_int_info_err;
4762 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4763
4764 } else
4765 kvm_requeue_exception(&svm->vcpu, vector);
4766 break;
4767 case SVM_EXITINTINFO_TYPE_INTR:
4768 kvm_queue_interrupt(&svm->vcpu, vector, false);
4769 break;
4770 default:
4771 break;
4772 }
4773}
4774
4775static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4776{
4777 struct vcpu_svm *svm = to_svm(vcpu);
4778 struct vmcb_control_area *control = &svm->vmcb->control;
4779
4780 control->exit_int_info = control->event_inj;
4781 control->exit_int_info_err = control->event_inj_err;
4782 control->event_inj = 0;
4783 svm_complete_interrupts(svm);
4784}
4785
4786static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4787{
4788 struct vcpu_svm *svm = to_svm(vcpu);
4789
4790 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4791 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4792 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4793
4794 /*
4795 * A vmexit emulation is required before the vcpu can be executed
4796 * again.
4797 */
4798 if (unlikely(svm->nested.exit_required))
4799 return;
4800
4801 pre_svm_run(svm);
4802
4803 sync_lapic_to_cr8(vcpu);
4804
4805 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4806
4807 clgi();
4808
4809 local_irq_enable();
4810
4811 asm volatile (
4812 "push %%" _ASM_BP "; \n\t"
4813 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4814 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4815 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4816 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4817 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4818 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4819#ifdef CONFIG_X86_64
4820 "mov %c[r8](%[svm]), %%r8 \n\t"
4821 "mov %c[r9](%[svm]), %%r9 \n\t"
4822 "mov %c[r10](%[svm]), %%r10 \n\t"
4823 "mov %c[r11](%[svm]), %%r11 \n\t"
4824 "mov %c[r12](%[svm]), %%r12 \n\t"
4825 "mov %c[r13](%[svm]), %%r13 \n\t"
4826 "mov %c[r14](%[svm]), %%r14 \n\t"
4827 "mov %c[r15](%[svm]), %%r15 \n\t"
4828#endif
4829
4830 /* Enter guest mode */
4831 "push %%" _ASM_AX " \n\t"
4832 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4833 __ex(SVM_VMLOAD) "\n\t"
4834 __ex(SVM_VMRUN) "\n\t"
4835 __ex(SVM_VMSAVE) "\n\t"
4836 "pop %%" _ASM_AX " \n\t"
4837
4838 /* Save guest registers, load host registers */
4839 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4840 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4841 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4842 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4843 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4844 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4845#ifdef CONFIG_X86_64
4846 "mov %%r8, %c[r8](%[svm]) \n\t"
4847 "mov %%r9, %c[r9](%[svm]) \n\t"
4848 "mov %%r10, %c[r10](%[svm]) \n\t"
4849 "mov %%r11, %c[r11](%[svm]) \n\t"
4850 "mov %%r12, %c[r12](%[svm]) \n\t"
4851 "mov %%r13, %c[r13](%[svm]) \n\t"
4852 "mov %%r14, %c[r14](%[svm]) \n\t"
4853 "mov %%r15, %c[r15](%[svm]) \n\t"
4854#endif
4855 "pop %%" _ASM_BP
4856 :
4857 : [svm]"a"(svm),
4858 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4859 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4860 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4861 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4862 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4863 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4864 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4865#ifdef CONFIG_X86_64
4866 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4867 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4868 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4869 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4870 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4871 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4872 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4873 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4874#endif
4875 : "cc", "memory"
4876#ifdef CONFIG_X86_64
4877 , "rbx", "rcx", "rdx", "rsi", "rdi"
4878 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4879#else
4880 , "ebx", "ecx", "edx", "esi", "edi"
4881#endif
4882 );
4883
4884#ifdef CONFIG_X86_64
4885 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4886#else
4887 loadsegment(fs, svm->host.fs);
4888#ifndef CONFIG_X86_32_LAZY_GS
4889 loadsegment(gs, svm->host.gs);
4890#endif
4891#endif
4892
4893 reload_tss(vcpu);
4894
4895 local_irq_disable();
4896
4897 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4898 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4899 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4900 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4901
4902 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4903 kvm_before_handle_nmi(&svm->vcpu);
4904
4905 stgi();
4906
4907 /* Any pending NMI will happen here */
4908
4909 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4910 kvm_after_handle_nmi(&svm->vcpu);
4911
4912 sync_cr8_to_lapic(vcpu);
4913
4914 svm->next_rip = 0;
4915
4916 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4917
4918 /* if exit due to PF check for async PF */
4919 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4920 svm->apf_reason = kvm_read_and_reset_pf_reason();
4921
4922 if (npt_enabled) {
4923 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4924 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4925 }
4926
4927 /*
4928 * We need to handle MC intercepts here before the vcpu has a chance to
4929 * change the physical cpu
4930 */
4931 if (unlikely(svm->vmcb->control.exit_code ==
4932 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4933 svm_handle_mce(svm);
4934
4935 mark_all_clean(svm->vmcb);
4936}
4937
4938static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4939{
4940 struct vcpu_svm *svm = to_svm(vcpu);
4941
4942 svm->vmcb->save.cr3 = root;
4943 mark_dirty(svm->vmcb, VMCB_CR);
4944 svm_flush_tlb(vcpu);
4945}
4946
4947static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4948{
4949 struct vcpu_svm *svm = to_svm(vcpu);
4950
4951 svm->vmcb->control.nested_cr3 = root;
4952 mark_dirty(svm->vmcb, VMCB_NPT);
4953
4954 /* Also sync guest cr3 here in case we live migrate */
4955 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4956 mark_dirty(svm->vmcb, VMCB_CR);
4957
4958 svm_flush_tlb(vcpu);
4959}
4960
4961static int is_disabled(void)
4962{
4963 u64 vm_cr;
4964
4965 rdmsrl(MSR_VM_CR, vm_cr);
4966 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4967 return 1;
4968
4969 return 0;
4970}
4971
4972static void
4973svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4974{
4975 /*
4976 * Patch in the VMMCALL instruction:
4977 */
4978 hypercall[0] = 0x0f;
4979 hypercall[1] = 0x01;
4980 hypercall[2] = 0xd9;
4981}
4982
4983static void svm_check_processor_compat(void *rtn)
4984{
4985 *(int *)rtn = 0;
4986}
4987
4988static bool svm_cpu_has_accelerated_tpr(void)
4989{
4990 return false;
4991}
4992
4993static bool svm_has_high_real_mode_segbase(void)
4994{
4995 return true;
4996}
4997
4998static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4999{
5000 return 0;
5001}
5002
5003static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5004{
5005 struct vcpu_svm *svm = to_svm(vcpu);
5006 struct kvm_cpuid_entry2 *entry;
5007
5008 /* Update nrips enabled cache */
5009 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5010
5011 if (!kvm_vcpu_apicv_active(vcpu))
5012 return;
5013
5014 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5015 if (entry)
5016 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5017}
5018
5019static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5020{
5021 switch (func) {
5022 case 0x1:
5023 if (avic)
5024 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5025 break;
5026 case 0x80000001:
5027 if (nested)
5028 entry->ecx |= (1 << 2); /* Set SVM bit */
5029 break;
5030 case 0x8000000A:
5031 entry->eax = 1; /* SVM revision 1 */
5032 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5033 ASID emulation to nested SVM */
5034 entry->ecx = 0; /* Reserved */
5035 entry->edx = 0; /* Per default do not support any
5036 additional features */
5037
5038 /* Support next_rip if host supports it */
5039 if (boot_cpu_has(X86_FEATURE_NRIPS))
5040 entry->edx |= SVM_FEATURE_NRIP;
5041
5042 /* Support NPT for the guest if enabled */
5043 if (npt_enabled)
5044 entry->edx |= SVM_FEATURE_NPT;
5045
5046 break;
5047 }
5048}
5049
5050static int svm_get_lpage_level(void)
5051{
5052 return PT_PDPE_LEVEL;
5053}
5054
5055static bool svm_rdtscp_supported(void)
5056{
5057 return boot_cpu_has(X86_FEATURE_RDTSCP);
5058}
5059
5060static bool svm_invpcid_supported(void)
5061{
5062 return false;
5063}
5064
5065static bool svm_mpx_supported(void)
5066{
5067 return false;
5068}
5069
5070static bool svm_xsaves_supported(void)
5071{
5072 return false;
5073}
5074
5075static bool svm_has_wbinvd_exit(void)
5076{
5077 return true;
5078}
5079
5080static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
5081{
5082 struct vcpu_svm *svm = to_svm(vcpu);
5083
5084 set_exception_intercept(svm, NM_VECTOR);
5085 update_cr0_intercept(svm);
5086}
5087
5088#define PRE_EX(exit) { .exit_code = (exit), \
5089 .stage = X86_ICPT_PRE_EXCEPT, }
5090#define POST_EX(exit) { .exit_code = (exit), \
5091 .stage = X86_ICPT_POST_EXCEPT, }
5092#define POST_MEM(exit) { .exit_code = (exit), \
5093 .stage = X86_ICPT_POST_MEMACCESS, }
5094
5095static const struct __x86_intercept {
5096 u32 exit_code;
5097 enum x86_intercept_stage stage;
5098} x86_intercept_map[] = {
5099 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5100 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5101 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5102 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5103 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5104 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5105 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5106 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5107 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5108 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5109 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5110 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5111 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5112 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5113 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5114 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5115 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5116 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5117 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5118 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5119 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5120 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5121 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5122 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5123 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5124 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5125 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5126 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5127 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5128 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5129 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5130 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5131 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5132 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5133 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5134 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5135 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5136 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5137 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5138 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5139 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5140 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5141 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5142 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5143 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5144 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5145};
5146
5147#undef PRE_EX
5148#undef POST_EX
5149#undef POST_MEM
5150
5151static int svm_check_intercept(struct kvm_vcpu *vcpu,
5152 struct x86_instruction_info *info,
5153 enum x86_intercept_stage stage)
5154{
5155 struct vcpu_svm *svm = to_svm(vcpu);
5156 int vmexit, ret = X86EMUL_CONTINUE;
5157 struct __x86_intercept icpt_info;
5158 struct vmcb *vmcb = svm->vmcb;
5159
5160 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5161 goto out;
5162
5163 icpt_info = x86_intercept_map[info->intercept];
5164
5165 if (stage != icpt_info.stage)
5166 goto out;
5167
5168 switch (icpt_info.exit_code) {
5169 case SVM_EXIT_READ_CR0:
5170 if (info->intercept == x86_intercept_cr_read)
5171 icpt_info.exit_code += info->modrm_reg;
5172 break;
5173 case SVM_EXIT_WRITE_CR0: {
5174 unsigned long cr0, val;
5175 u64 intercept;
5176
5177 if (info->intercept == x86_intercept_cr_write)
5178 icpt_info.exit_code += info->modrm_reg;
5179
5180 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5181 info->intercept == x86_intercept_clts)
5182 break;
5183
5184 intercept = svm->nested.intercept;
5185
5186 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5187 break;
5188
5189 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5190 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5191
5192 if (info->intercept == x86_intercept_lmsw) {
5193 cr0 &= 0xfUL;
5194 val &= 0xfUL;
5195 /* lmsw can't clear PE - catch this here */
5196 if (cr0 & X86_CR0_PE)
5197 val |= X86_CR0_PE;
5198 }
5199
5200 if (cr0 ^ val)
5201 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5202
5203 break;
5204 }
5205 case SVM_EXIT_READ_DR0:
5206 case SVM_EXIT_WRITE_DR0:
5207 icpt_info.exit_code += info->modrm_reg;
5208 break;
5209 case SVM_EXIT_MSR:
5210 if (info->intercept == x86_intercept_wrmsr)
5211 vmcb->control.exit_info_1 = 1;
5212 else
5213 vmcb->control.exit_info_1 = 0;
5214 break;
5215 case SVM_EXIT_PAUSE:
5216 /*
5217 * We get this for NOP only, but pause
5218 * is rep not, check this here
5219 */
5220 if (info->rep_prefix != REPE_PREFIX)
5221 goto out;
5222 case SVM_EXIT_IOIO: {
5223 u64 exit_info;
5224 u32 bytes;
5225
5226 if (info->intercept == x86_intercept_in ||
5227 info->intercept == x86_intercept_ins) {
5228 exit_info = ((info->src_val & 0xffff) << 16) |
5229 SVM_IOIO_TYPE_MASK;
5230 bytes = info->dst_bytes;
5231 } else {
5232 exit_info = (info->dst_val & 0xffff) << 16;
5233 bytes = info->src_bytes;
5234 }
5235
5236 if (info->intercept == x86_intercept_outs ||
5237 info->intercept == x86_intercept_ins)
5238 exit_info |= SVM_IOIO_STR_MASK;
5239
5240 if (info->rep_prefix)
5241 exit_info |= SVM_IOIO_REP_MASK;
5242
5243 bytes = min(bytes, 4u);
5244
5245 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5246
5247 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5248
5249 vmcb->control.exit_info_1 = exit_info;
5250 vmcb->control.exit_info_2 = info->next_rip;
5251
5252 break;
5253 }
5254 default:
5255 break;
5256 }
5257
5258 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5259 if (static_cpu_has(X86_FEATURE_NRIPS))
5260 vmcb->control.next_rip = info->next_rip;
5261 vmcb->control.exit_code = icpt_info.exit_code;
5262 vmexit = nested_svm_exit_handled(svm);
5263
5264 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5265 : X86EMUL_CONTINUE;
5266
5267out:
5268 return ret;
5269}
5270
5271static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5272{
5273 local_irq_enable();
5274 /*
5275 * We must have an instruction with interrupts enabled, so
5276 * the timer interrupt isn't delayed by the interrupt shadow.
5277 */
5278 asm("nop");
5279 local_irq_disable();
5280}
5281
5282static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5283{
5284}
5285
5286static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5287{
5288 if (avic_handle_apic_id_update(vcpu) != 0)
5289 return;
5290 if (avic_handle_dfr_update(vcpu) != 0)
5291 return;
5292 avic_handle_ldr_update(vcpu);
5293}
5294
5295static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5296 .cpu_has_kvm_support = has_svm,
5297 .disabled_by_bios = is_disabled,
5298 .hardware_setup = svm_hardware_setup,
5299 .hardware_unsetup = svm_hardware_unsetup,
5300 .check_processor_compatibility = svm_check_processor_compat,
5301 .hardware_enable = svm_hardware_enable,
5302 .hardware_disable = svm_hardware_disable,
5303 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5304 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5305
5306 .vcpu_create = svm_create_vcpu,
5307 .vcpu_free = svm_free_vcpu,
5308 .vcpu_reset = svm_vcpu_reset,
5309
5310 .vm_init = avic_vm_init,
5311 .vm_destroy = avic_vm_destroy,
5312
5313 .prepare_guest_switch = svm_prepare_guest_switch,
5314 .vcpu_load = svm_vcpu_load,
5315 .vcpu_put = svm_vcpu_put,
5316 .vcpu_blocking = svm_vcpu_blocking,
5317 .vcpu_unblocking = svm_vcpu_unblocking,
5318
5319 .update_bp_intercept = update_bp_intercept,
5320 .get_msr = svm_get_msr,
5321 .set_msr = svm_set_msr,
5322 .get_segment_base = svm_get_segment_base,
5323 .get_segment = svm_get_segment,
5324 .set_segment = svm_set_segment,
5325 .get_cpl = svm_get_cpl,
5326 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5327 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5328 .decache_cr3 = svm_decache_cr3,
5329 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5330 .set_cr0 = svm_set_cr0,
5331 .set_cr3 = svm_set_cr3,
5332 .set_cr4 = svm_set_cr4,
5333 .set_efer = svm_set_efer,
5334 .get_idt = svm_get_idt,
5335 .set_idt = svm_set_idt,
5336 .get_gdt = svm_get_gdt,
5337 .set_gdt = svm_set_gdt,
5338 .get_dr6 = svm_get_dr6,
5339 .set_dr6 = svm_set_dr6,
5340 .set_dr7 = svm_set_dr7,
5341 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5342 .cache_reg = svm_cache_reg,
5343 .get_rflags = svm_get_rflags,
5344 .set_rflags = svm_set_rflags,
5345
5346 .get_pkru = svm_get_pkru,
5347
5348 .fpu_activate = svm_fpu_activate,
5349 .fpu_deactivate = svm_fpu_deactivate,
5350
5351 .tlb_flush = svm_flush_tlb,
5352
5353 .run = svm_vcpu_run,
5354 .handle_exit = handle_exit,
5355 .skip_emulated_instruction = skip_emulated_instruction,
5356 .set_interrupt_shadow = svm_set_interrupt_shadow,
5357 .get_interrupt_shadow = svm_get_interrupt_shadow,
5358 .patch_hypercall = svm_patch_hypercall,
5359 .set_irq = svm_set_irq,
5360 .set_nmi = svm_inject_nmi,
5361 .queue_exception = svm_queue_exception,
5362 .cancel_injection = svm_cancel_injection,
5363 .interrupt_allowed = svm_interrupt_allowed,
5364 .nmi_allowed = svm_nmi_allowed,
5365 .get_nmi_mask = svm_get_nmi_mask,
5366 .set_nmi_mask = svm_set_nmi_mask,
5367 .enable_nmi_window = enable_nmi_window,
5368 .enable_irq_window = enable_irq_window,
5369 .update_cr8_intercept = update_cr8_intercept,
5370 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5371 .get_enable_apicv = svm_get_enable_apicv,
5372 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5373 .load_eoi_exitmap = svm_load_eoi_exitmap,
5374 .sync_pir_to_irr = svm_sync_pir_to_irr,
5375 .hwapic_irr_update = svm_hwapic_irr_update,
5376 .hwapic_isr_update = svm_hwapic_isr_update,
5377 .apicv_post_state_restore = avic_post_state_restore,
5378
5379 .set_tss_addr = svm_set_tss_addr,
5380 .get_tdp_level = get_npt_level,
5381 .get_mt_mask = svm_get_mt_mask,
5382
5383 .get_exit_info = svm_get_exit_info,
5384
5385 .get_lpage_level = svm_get_lpage_level,
5386
5387 .cpuid_update = svm_cpuid_update,
5388
5389 .rdtscp_supported = svm_rdtscp_supported,
5390 .invpcid_supported = svm_invpcid_supported,
5391 .mpx_supported = svm_mpx_supported,
5392 .xsaves_supported = svm_xsaves_supported,
5393
5394 .set_supported_cpuid = svm_set_supported_cpuid,
5395
5396 .has_wbinvd_exit = svm_has_wbinvd_exit,
5397
5398 .write_tsc_offset = svm_write_tsc_offset,
5399
5400 .set_tdp_cr3 = set_tdp_cr3,
5401
5402 .check_intercept = svm_check_intercept,
5403 .handle_external_intr = svm_handle_external_intr,
5404
5405 .sched_in = svm_sched_in,
5406
5407 .pmu_ops = &amd_pmu_ops,
5408 .deliver_posted_interrupt = svm_deliver_avic_intr,
5409 .update_pi_irte = svm_update_pi_irte,
5410};
5411
5412static int __init svm_init(void)
5413{
5414 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5415 __alignof__(struct vcpu_svm), THIS_MODULE);
5416}
5417
5418static void __exit svm_exit(void)
5419{
5420 kvm_exit();
5421}
5422
5423module_init(svm_init)
5424module_exit(svm_exit)