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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17#include <linux/kvm_host.h>
18
19#include "irq.h"
20#include "mmu.h"
21#include "kvm_cache_regs.h"
22#include "x86.h"
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
28#include <linux/sched.h>
29#include <linux/ftrace_event.h>
30#include <linux/slab.h>
31
32#include <asm/tlbflush.h>
33#include <asm/desc.h>
34#include <asm/kvm_para.h>
35
36#include <asm/virtext.h>
37#include "trace.h"
38
39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_TSC_RATE (1 << 4)
55#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56#define SVM_FEATURE_FLUSH_ASID (1 << 6)
57#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
59
60#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
63
64#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
65
66#define TSC_RATIO_RSVD 0xffffff0000000000ULL
67#define TSC_RATIO_MIN 0x0000000000000001ULL
68#define TSC_RATIO_MAX 0x000000ffffffffffULL
69
70static bool erratum_383_found __read_mostly;
71
72static const u32 host_save_user_msrs[] = {
73#ifdef CONFIG_X86_64
74 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
75 MSR_FS_BASE,
76#endif
77 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
78};
79
80#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
81
82struct kvm_vcpu;
83
84struct nested_state {
85 struct vmcb *hsave;
86 u64 hsave_msr;
87 u64 vm_cr_msr;
88 u64 vmcb;
89
90 /* These are the merged vectors */
91 u32 *msrpm;
92
93 /* gpa pointers to the real vectors */
94 u64 vmcb_msrpm;
95 u64 vmcb_iopm;
96
97 /* A VMEXIT is required but not yet emulated */
98 bool exit_required;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108};
109
110#define MSRPM_OFFSETS 16
111static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 ulong nmi_iret_rip;
135
136 struct nested_state nested;
137
138 bool nmi_singlestep;
139
140 unsigned int3_injected;
141 unsigned long int3_rip;
142 u32 apf_reason;
143
144 u64 tsc_ratio;
145};
146
147static DEFINE_PER_CPU(u64, current_tsc_ratio);
148#define TSC_RATIO_DEFAULT 0x0100000000ULL
149
150#define MSR_INVALID 0xffffffffU
151
152static struct svm_direct_access_msrs {
153 u32 index; /* Index of the MSR */
154 bool always; /* True if intercept is always on */
155} direct_access_msrs[] = {
156 { .index = MSR_STAR, .always = true },
157 { .index = MSR_IA32_SYSENTER_CS, .always = true },
158#ifdef CONFIG_X86_64
159 { .index = MSR_GS_BASE, .always = true },
160 { .index = MSR_FS_BASE, .always = true },
161 { .index = MSR_KERNEL_GS_BASE, .always = true },
162 { .index = MSR_LSTAR, .always = true },
163 { .index = MSR_CSTAR, .always = true },
164 { .index = MSR_SYSCALL_MASK, .always = true },
165#endif
166 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
167 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
168 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
169 { .index = MSR_IA32_LASTINTTOIP, .always = false },
170 { .index = MSR_INVALID, .always = false },
171};
172
173/* enable NPT for AMD64 and X86 with PAE */
174#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
175static bool npt_enabled = true;
176#else
177static bool npt_enabled;
178#endif
179static int npt = 1;
180
181module_param(npt, int, S_IRUGO);
182
183static int nested = 1;
184module_param(nested, int, S_IRUGO);
185
186static void svm_flush_tlb(struct kvm_vcpu *vcpu);
187static void svm_complete_interrupts(struct vcpu_svm *svm);
188
189static int nested_svm_exit_handled(struct vcpu_svm *svm);
190static int nested_svm_intercept(struct vcpu_svm *svm);
191static int nested_svm_vmexit(struct vcpu_svm *svm);
192static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
193 bool has_error_code, u32 error_code);
194static u64 __scale_tsc(u64 ratio, u64 tsc);
195
196enum {
197 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
198 pause filter count */
199 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
200 VMCB_ASID, /* ASID */
201 VMCB_INTR, /* int_ctl, int_vector */
202 VMCB_NPT, /* npt_en, nCR3, gPAT */
203 VMCB_CR, /* CR0, CR3, CR4, EFER */
204 VMCB_DR, /* DR6, DR7 */
205 VMCB_DT, /* GDT, IDT */
206 VMCB_SEG, /* CS, DS, SS, ES, CPL */
207 VMCB_CR2, /* CR2 only */
208 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
209 VMCB_DIRTY_MAX,
210};
211
212/* TPR and CR2 are always written before VMRUN */
213#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
214
215static inline void mark_all_dirty(struct vmcb *vmcb)
216{
217 vmcb->control.clean = 0;
218}
219
220static inline void mark_all_clean(struct vmcb *vmcb)
221{
222 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
223 & ~VMCB_ALWAYS_DIRTY_MASK;
224}
225
226static inline void mark_dirty(struct vmcb *vmcb, int bit)
227{
228 vmcb->control.clean &= ~(1 << bit);
229}
230
231static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
232{
233 return container_of(vcpu, struct vcpu_svm, vcpu);
234}
235
236static void recalc_intercepts(struct vcpu_svm *svm)
237{
238 struct vmcb_control_area *c, *h;
239 struct nested_state *g;
240
241 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
242
243 if (!is_guest_mode(&svm->vcpu))
244 return;
245
246 c = &svm->vmcb->control;
247 h = &svm->nested.hsave->control;
248 g = &svm->nested;
249
250 c->intercept_cr = h->intercept_cr | g->intercept_cr;
251 c->intercept_dr = h->intercept_dr | g->intercept_dr;
252 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
253 c->intercept = h->intercept | g->intercept;
254}
255
256static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
257{
258 if (is_guest_mode(&svm->vcpu))
259 return svm->nested.hsave;
260 else
261 return svm->vmcb;
262}
263
264static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
265{
266 struct vmcb *vmcb = get_host_vmcb(svm);
267
268 vmcb->control.intercept_cr |= (1U << bit);
269
270 recalc_intercepts(svm);
271}
272
273static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
274{
275 struct vmcb *vmcb = get_host_vmcb(svm);
276
277 vmcb->control.intercept_cr &= ~(1U << bit);
278
279 recalc_intercepts(svm);
280}
281
282static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
283{
284 struct vmcb *vmcb = get_host_vmcb(svm);
285
286 return vmcb->control.intercept_cr & (1U << bit);
287}
288
289static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
290{
291 struct vmcb *vmcb = get_host_vmcb(svm);
292
293 vmcb->control.intercept_dr |= (1U << bit);
294
295 recalc_intercepts(svm);
296}
297
298static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
299{
300 struct vmcb *vmcb = get_host_vmcb(svm);
301
302 vmcb->control.intercept_dr &= ~(1U << bit);
303
304 recalc_intercepts(svm);
305}
306
307static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
308{
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept_exceptions |= (1U << bit);
312
313 recalc_intercepts(svm);
314}
315
316static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
317{
318 struct vmcb *vmcb = get_host_vmcb(svm);
319
320 vmcb->control.intercept_exceptions &= ~(1U << bit);
321
322 recalc_intercepts(svm);
323}
324
325static inline void set_intercept(struct vcpu_svm *svm, int bit)
326{
327 struct vmcb *vmcb = get_host_vmcb(svm);
328
329 vmcb->control.intercept |= (1ULL << bit);
330
331 recalc_intercepts(svm);
332}
333
334static inline void clr_intercept(struct vcpu_svm *svm, int bit)
335{
336 struct vmcb *vmcb = get_host_vmcb(svm);
337
338 vmcb->control.intercept &= ~(1ULL << bit);
339
340 recalc_intercepts(svm);
341}
342
343static inline void enable_gif(struct vcpu_svm *svm)
344{
345 svm->vcpu.arch.hflags |= HF_GIF_MASK;
346}
347
348static inline void disable_gif(struct vcpu_svm *svm)
349{
350 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
351}
352
353static inline bool gif_set(struct vcpu_svm *svm)
354{
355 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
356}
357
358static unsigned long iopm_base;
359
360struct kvm_ldttss_desc {
361 u16 limit0;
362 u16 base0;
363 unsigned base1:8, type:5, dpl:2, p:1;
364 unsigned limit1:4, zero0:3, g:1, base2:8;
365 u32 base3;
366 u32 zero1;
367} __attribute__((packed));
368
369struct svm_cpu_data {
370 int cpu;
371
372 u64 asid_generation;
373 u32 max_asid;
374 u32 next_asid;
375 struct kvm_ldttss_desc *tss_desc;
376
377 struct page *save_area;
378};
379
380static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
381
382struct svm_init_data {
383 int cpu;
384 int r;
385};
386
387static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
388
389#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
390#define MSRS_RANGE_SIZE 2048
391#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
392
393static u32 svm_msrpm_offset(u32 msr)
394{
395 u32 offset;
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr < msrpm_ranges[i] ||
400 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
401 continue;
402
403 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
404 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
405
406 /* Now we have the u8 offset - but need the u32 offset */
407 return offset / 4;
408 }
409
410 /* MSR not in any range */
411 return MSR_INVALID;
412}
413
414#define MAX_INST_SIZE 15
415
416static inline void clgi(void)
417{
418 asm volatile (__ex(SVM_CLGI));
419}
420
421static inline void stgi(void)
422{
423 asm volatile (__ex(SVM_STGI));
424}
425
426static inline void invlpga(unsigned long addr, u32 asid)
427{
428 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
429}
430
431static int get_npt_level(void)
432{
433#ifdef CONFIG_X86_64
434 return PT64_ROOT_LEVEL;
435#else
436 return PT32E_ROOT_LEVEL;
437#endif
438}
439
440static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
441{
442 vcpu->arch.efer = efer;
443 if (!npt_enabled && !(efer & EFER_LMA))
444 efer &= ~EFER_LME;
445
446 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
447 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
448}
449
450static int is_external_interrupt(u32 info)
451{
452 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
453 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
454}
455
456static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
457{
458 struct vcpu_svm *svm = to_svm(vcpu);
459 u32 ret = 0;
460
461 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
462 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
463 return ret & mask;
464}
465
466static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
467{
468 struct vcpu_svm *svm = to_svm(vcpu);
469
470 if (mask == 0)
471 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
472 else
473 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
474
475}
476
477static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
478{
479 struct vcpu_svm *svm = to_svm(vcpu);
480
481 if (svm->vmcb->control.next_rip != 0)
482 svm->next_rip = svm->vmcb->control.next_rip;
483
484 if (!svm->next_rip) {
485 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
486 EMULATE_DONE)
487 printk(KERN_DEBUG "%s: NOP\n", __func__);
488 return;
489 }
490 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
491 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
492 __func__, kvm_rip_read(vcpu), svm->next_rip);
493
494 kvm_rip_write(vcpu, svm->next_rip);
495 svm_set_interrupt_shadow(vcpu, 0);
496}
497
498static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
499 bool has_error_code, u32 error_code,
500 bool reinject)
501{
502 struct vcpu_svm *svm = to_svm(vcpu);
503
504 /*
505 * If we are within a nested VM we'd better #VMEXIT and let the guest
506 * handle the exception
507 */
508 if (!reinject &&
509 nested_svm_check_exception(svm, nr, has_error_code, error_code))
510 return;
511
512 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
513 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
514
515 /*
516 * For guest debugging where we have to reinject #BP if some
517 * INT3 is guest-owned:
518 * Emulate nRIP by moving RIP forward. Will fail if injection
519 * raises a fault that is not intercepted. Still better than
520 * failing in all cases.
521 */
522 skip_emulated_instruction(&svm->vcpu);
523 rip = kvm_rip_read(&svm->vcpu);
524 svm->int3_rip = rip + svm->vmcb->save.cs.base;
525 svm->int3_injected = rip - old_rip;
526 }
527
528 svm->vmcb->control.event_inj = nr
529 | SVM_EVTINJ_VALID
530 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
531 | SVM_EVTINJ_TYPE_EXEPT;
532 svm->vmcb->control.event_inj_err = error_code;
533}
534
535static void svm_init_erratum_383(void)
536{
537 u32 low, high;
538 int err;
539 u64 val;
540
541 if (!cpu_has_amd_erratum(amd_erratum_383))
542 return;
543
544 /* Use _safe variants to not break nested virtualization */
545 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
546 if (err)
547 return;
548
549 val |= (1ULL << 47);
550
551 low = lower_32_bits(val);
552 high = upper_32_bits(val);
553
554 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
555
556 erratum_383_found = true;
557}
558
559static int has_svm(void)
560{
561 const char *msg;
562
563 if (!cpu_has_svm(&msg)) {
564 printk(KERN_INFO "has_svm: %s\n", msg);
565 return 0;
566 }
567
568 return 1;
569}
570
571static void svm_hardware_disable(void *garbage)
572{
573 /* Make sure we clean up behind us */
574 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
575 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
576
577 cpu_svm_disable();
578}
579
580static int svm_hardware_enable(void *garbage)
581{
582
583 struct svm_cpu_data *sd;
584 uint64_t efer;
585 struct desc_ptr gdt_descr;
586 struct desc_struct *gdt;
587 int me = raw_smp_processor_id();
588
589 rdmsrl(MSR_EFER, efer);
590 if (efer & EFER_SVME)
591 return -EBUSY;
592
593 if (!has_svm()) {
594 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
595 me);
596 return -EINVAL;
597 }
598 sd = per_cpu(svm_data, me);
599
600 if (!sd) {
601 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
602 me);
603 return -EINVAL;
604 }
605
606 sd->asid_generation = 1;
607 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
608 sd->next_asid = sd->max_asid + 1;
609
610 native_store_gdt(&gdt_descr);
611 gdt = (struct desc_struct *)gdt_descr.address;
612 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
613
614 wrmsrl(MSR_EFER, efer | EFER_SVME);
615
616 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
617
618 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
619 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
620 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
621 }
622
623 svm_init_erratum_383();
624
625 return 0;
626}
627
628static void svm_cpu_uninit(int cpu)
629{
630 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
631
632 if (!sd)
633 return;
634
635 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
636 __free_page(sd->save_area);
637 kfree(sd);
638}
639
640static int svm_cpu_init(int cpu)
641{
642 struct svm_cpu_data *sd;
643 int r;
644
645 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
646 if (!sd)
647 return -ENOMEM;
648 sd->cpu = cpu;
649 sd->save_area = alloc_page(GFP_KERNEL);
650 r = -ENOMEM;
651 if (!sd->save_area)
652 goto err_1;
653
654 per_cpu(svm_data, cpu) = sd;
655
656 return 0;
657
658err_1:
659 kfree(sd);
660 return r;
661
662}
663
664static bool valid_msr_intercept(u32 index)
665{
666 int i;
667
668 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
669 if (direct_access_msrs[i].index == index)
670 return true;
671
672 return false;
673}
674
675static void set_msr_interception(u32 *msrpm, unsigned msr,
676 int read, int write)
677{
678 u8 bit_read, bit_write;
679 unsigned long tmp;
680 u32 offset;
681
682 /*
683 * If this warning triggers extend the direct_access_msrs list at the
684 * beginning of the file
685 */
686 WARN_ON(!valid_msr_intercept(msr));
687
688 offset = svm_msrpm_offset(msr);
689 bit_read = 2 * (msr & 0x0f);
690 bit_write = 2 * (msr & 0x0f) + 1;
691 tmp = msrpm[offset];
692
693 BUG_ON(offset == MSR_INVALID);
694
695 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
696 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
697
698 msrpm[offset] = tmp;
699}
700
701static void svm_vcpu_init_msrpm(u32 *msrpm)
702{
703 int i;
704
705 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
706
707 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
708 if (!direct_access_msrs[i].always)
709 continue;
710
711 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
712 }
713}
714
715static void add_msr_offset(u32 offset)
716{
717 int i;
718
719 for (i = 0; i < MSRPM_OFFSETS; ++i) {
720
721 /* Offset already in list? */
722 if (msrpm_offsets[i] == offset)
723 return;
724
725 /* Slot used by another offset? */
726 if (msrpm_offsets[i] != MSR_INVALID)
727 continue;
728
729 /* Add offset to list */
730 msrpm_offsets[i] = offset;
731
732 return;
733 }
734
735 /*
736 * If this BUG triggers the msrpm_offsets table has an overflow. Just
737 * increase MSRPM_OFFSETS in this case.
738 */
739 BUG();
740}
741
742static void init_msrpm_offsets(void)
743{
744 int i;
745
746 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
747
748 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
749 u32 offset;
750
751 offset = svm_msrpm_offset(direct_access_msrs[i].index);
752 BUG_ON(offset == MSR_INVALID);
753
754 add_msr_offset(offset);
755 }
756}
757
758static void svm_enable_lbrv(struct vcpu_svm *svm)
759{
760 u32 *msrpm = svm->msrpm;
761
762 svm->vmcb->control.lbr_ctl = 1;
763 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
764 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
765 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
766 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
767}
768
769static void svm_disable_lbrv(struct vcpu_svm *svm)
770{
771 u32 *msrpm = svm->msrpm;
772
773 svm->vmcb->control.lbr_ctl = 0;
774 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
775 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
776 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
777 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
778}
779
780static __init int svm_hardware_setup(void)
781{
782 int cpu;
783 struct page *iopm_pages;
784 void *iopm_va;
785 int r;
786
787 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
788
789 if (!iopm_pages)
790 return -ENOMEM;
791
792 iopm_va = page_address(iopm_pages);
793 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
794 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
795
796 init_msrpm_offsets();
797
798 if (boot_cpu_has(X86_FEATURE_NX))
799 kvm_enable_efer_bits(EFER_NX);
800
801 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
802 kvm_enable_efer_bits(EFER_FFXSR);
803
804 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
805 u64 max;
806
807 kvm_has_tsc_control = true;
808
809 /*
810 * Make sure the user can only configure tsc_khz values that
811 * fit into a signed integer.
812 * A min value is not calculated needed because it will always
813 * be 1 on all machines and a value of 0 is used to disable
814 * tsc-scaling for the vcpu.
815 */
816 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
817
818 kvm_max_guest_tsc_khz = max;
819 }
820
821 if (nested) {
822 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
823 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
824 }
825
826 for_each_possible_cpu(cpu) {
827 r = svm_cpu_init(cpu);
828 if (r)
829 goto err;
830 }
831
832 if (!boot_cpu_has(X86_FEATURE_NPT))
833 npt_enabled = false;
834
835 if (npt_enabled && !npt) {
836 printk(KERN_INFO "kvm: Nested Paging disabled\n");
837 npt_enabled = false;
838 }
839
840 if (npt_enabled) {
841 printk(KERN_INFO "kvm: Nested Paging enabled\n");
842 kvm_enable_tdp();
843 } else
844 kvm_disable_tdp();
845
846 return 0;
847
848err:
849 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
850 iopm_base = 0;
851 return r;
852}
853
854static __exit void svm_hardware_unsetup(void)
855{
856 int cpu;
857
858 for_each_possible_cpu(cpu)
859 svm_cpu_uninit(cpu);
860
861 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
862 iopm_base = 0;
863}
864
865static void init_seg(struct vmcb_seg *seg)
866{
867 seg->selector = 0;
868 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
869 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
870 seg->limit = 0xffff;
871 seg->base = 0;
872}
873
874static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
875{
876 seg->selector = 0;
877 seg->attrib = SVM_SELECTOR_P_MASK | type;
878 seg->limit = 0xffff;
879 seg->base = 0;
880}
881
882static u64 __scale_tsc(u64 ratio, u64 tsc)
883{
884 u64 mult, frac, _tsc;
885
886 mult = ratio >> 32;
887 frac = ratio & ((1ULL << 32) - 1);
888
889 _tsc = tsc;
890 _tsc *= mult;
891 _tsc += (tsc >> 32) * frac;
892 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
893
894 return _tsc;
895}
896
897static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
898{
899 struct vcpu_svm *svm = to_svm(vcpu);
900 u64 _tsc = tsc;
901
902 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
903 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
904
905 return _tsc;
906}
907
908static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
909{
910 struct vcpu_svm *svm = to_svm(vcpu);
911 u64 ratio;
912 u64 khz;
913
914 /* TSC scaling supported? */
915 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
916 return;
917
918 /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
919 if (user_tsc_khz == 0) {
920 vcpu->arch.virtual_tsc_khz = 0;
921 svm->tsc_ratio = TSC_RATIO_DEFAULT;
922 return;
923 }
924
925 khz = user_tsc_khz;
926
927 /* TSC scaling required - calculate ratio */
928 ratio = khz << 32;
929 do_div(ratio, tsc_khz);
930
931 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
932 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
933 user_tsc_khz);
934 return;
935 }
936 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
937 svm->tsc_ratio = ratio;
938}
939
940static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
941{
942 struct vcpu_svm *svm = to_svm(vcpu);
943 u64 g_tsc_offset = 0;
944
945 if (is_guest_mode(vcpu)) {
946 g_tsc_offset = svm->vmcb->control.tsc_offset -
947 svm->nested.hsave->control.tsc_offset;
948 svm->nested.hsave->control.tsc_offset = offset;
949 }
950
951 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
952
953 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
954}
955
956static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
957{
958 struct vcpu_svm *svm = to_svm(vcpu);
959
960 svm->vmcb->control.tsc_offset += adjustment;
961 if (is_guest_mode(vcpu))
962 svm->nested.hsave->control.tsc_offset += adjustment;
963 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
964}
965
966static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
967{
968 u64 tsc;
969
970 tsc = svm_scale_tsc(vcpu, native_read_tsc());
971
972 return target_tsc - tsc;
973}
974
975static void init_vmcb(struct vcpu_svm *svm)
976{
977 struct vmcb_control_area *control = &svm->vmcb->control;
978 struct vmcb_save_area *save = &svm->vmcb->save;
979
980 svm->vcpu.fpu_active = 1;
981 svm->vcpu.arch.hflags = 0;
982
983 set_cr_intercept(svm, INTERCEPT_CR0_READ);
984 set_cr_intercept(svm, INTERCEPT_CR3_READ);
985 set_cr_intercept(svm, INTERCEPT_CR4_READ);
986 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
987 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
988 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
989 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
990
991 set_dr_intercept(svm, INTERCEPT_DR0_READ);
992 set_dr_intercept(svm, INTERCEPT_DR1_READ);
993 set_dr_intercept(svm, INTERCEPT_DR2_READ);
994 set_dr_intercept(svm, INTERCEPT_DR3_READ);
995 set_dr_intercept(svm, INTERCEPT_DR4_READ);
996 set_dr_intercept(svm, INTERCEPT_DR5_READ);
997 set_dr_intercept(svm, INTERCEPT_DR6_READ);
998 set_dr_intercept(svm, INTERCEPT_DR7_READ);
999
1000 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1001 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1002 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1003 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1004 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1005 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1006 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1007 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1008
1009 set_exception_intercept(svm, PF_VECTOR);
1010 set_exception_intercept(svm, UD_VECTOR);
1011 set_exception_intercept(svm, MC_VECTOR);
1012
1013 set_intercept(svm, INTERCEPT_INTR);
1014 set_intercept(svm, INTERCEPT_NMI);
1015 set_intercept(svm, INTERCEPT_SMI);
1016 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1017 set_intercept(svm, INTERCEPT_CPUID);
1018 set_intercept(svm, INTERCEPT_INVD);
1019 set_intercept(svm, INTERCEPT_HLT);
1020 set_intercept(svm, INTERCEPT_INVLPG);
1021 set_intercept(svm, INTERCEPT_INVLPGA);
1022 set_intercept(svm, INTERCEPT_IOIO_PROT);
1023 set_intercept(svm, INTERCEPT_MSR_PROT);
1024 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1025 set_intercept(svm, INTERCEPT_SHUTDOWN);
1026 set_intercept(svm, INTERCEPT_VMRUN);
1027 set_intercept(svm, INTERCEPT_VMMCALL);
1028 set_intercept(svm, INTERCEPT_VMLOAD);
1029 set_intercept(svm, INTERCEPT_VMSAVE);
1030 set_intercept(svm, INTERCEPT_STGI);
1031 set_intercept(svm, INTERCEPT_CLGI);
1032 set_intercept(svm, INTERCEPT_SKINIT);
1033 set_intercept(svm, INTERCEPT_WBINVD);
1034 set_intercept(svm, INTERCEPT_MONITOR);
1035 set_intercept(svm, INTERCEPT_MWAIT);
1036 set_intercept(svm, INTERCEPT_XSETBV);
1037
1038 control->iopm_base_pa = iopm_base;
1039 control->msrpm_base_pa = __pa(svm->msrpm);
1040 control->int_ctl = V_INTR_MASKING_MASK;
1041
1042 init_seg(&save->es);
1043 init_seg(&save->ss);
1044 init_seg(&save->ds);
1045 init_seg(&save->fs);
1046 init_seg(&save->gs);
1047
1048 save->cs.selector = 0xf000;
1049 /* Executable/Readable Code Segment */
1050 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1051 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1052 save->cs.limit = 0xffff;
1053 /*
1054 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1055 * be consistent with it.
1056 *
1057 * Replace when we have real mode working for vmx.
1058 */
1059 save->cs.base = 0xf0000;
1060
1061 save->gdtr.limit = 0xffff;
1062 save->idtr.limit = 0xffff;
1063
1064 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1065 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1066
1067 svm_set_efer(&svm->vcpu, 0);
1068 save->dr6 = 0xffff0ff0;
1069 save->dr7 = 0x400;
1070 kvm_set_rflags(&svm->vcpu, 2);
1071 save->rip = 0x0000fff0;
1072 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1073
1074 /*
1075 * This is the guest-visible cr0 value.
1076 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1077 */
1078 svm->vcpu.arch.cr0 = 0;
1079 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1080
1081 save->cr4 = X86_CR4_PAE;
1082 /* rdx = ?? */
1083
1084 if (npt_enabled) {
1085 /* Setup VMCB for Nested Paging */
1086 control->nested_ctl = 1;
1087 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
1088 clr_intercept(svm, INTERCEPT_INVLPG);
1089 clr_exception_intercept(svm, PF_VECTOR);
1090 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1091 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1092 save->g_pat = 0x0007040600070406ULL;
1093 save->cr3 = 0;
1094 save->cr4 = 0;
1095 }
1096 svm->asid_generation = 0;
1097
1098 svm->nested.vmcb = 0;
1099 svm->vcpu.arch.hflags = 0;
1100
1101 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1102 control->pause_filter_count = 3000;
1103 set_intercept(svm, INTERCEPT_PAUSE);
1104 }
1105
1106 mark_all_dirty(svm->vmcb);
1107
1108 enable_gif(svm);
1109}
1110
1111static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1112{
1113 struct vcpu_svm *svm = to_svm(vcpu);
1114
1115 init_vmcb(svm);
1116
1117 if (!kvm_vcpu_is_bsp(vcpu)) {
1118 kvm_rip_write(vcpu, 0);
1119 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1120 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1121 }
1122 vcpu->arch.regs_avail = ~0;
1123 vcpu->arch.regs_dirty = ~0;
1124
1125 return 0;
1126}
1127
1128static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1129{
1130 struct vcpu_svm *svm;
1131 struct page *page;
1132 struct page *msrpm_pages;
1133 struct page *hsave_page;
1134 struct page *nested_msrpm_pages;
1135 int err;
1136
1137 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1138 if (!svm) {
1139 err = -ENOMEM;
1140 goto out;
1141 }
1142
1143 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1144
1145 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1146 if (err)
1147 goto free_svm;
1148
1149 err = -ENOMEM;
1150 page = alloc_page(GFP_KERNEL);
1151 if (!page)
1152 goto uninit;
1153
1154 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1155 if (!msrpm_pages)
1156 goto free_page1;
1157
1158 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1159 if (!nested_msrpm_pages)
1160 goto free_page2;
1161
1162 hsave_page = alloc_page(GFP_KERNEL);
1163 if (!hsave_page)
1164 goto free_page3;
1165
1166 svm->nested.hsave = page_address(hsave_page);
1167
1168 svm->msrpm = page_address(msrpm_pages);
1169 svm_vcpu_init_msrpm(svm->msrpm);
1170
1171 svm->nested.msrpm = page_address(nested_msrpm_pages);
1172 svm_vcpu_init_msrpm(svm->nested.msrpm);
1173
1174 svm->vmcb = page_address(page);
1175 clear_page(svm->vmcb);
1176 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1177 svm->asid_generation = 0;
1178 init_vmcb(svm);
1179 kvm_write_tsc(&svm->vcpu, 0);
1180
1181 err = fx_init(&svm->vcpu);
1182 if (err)
1183 goto free_page4;
1184
1185 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1186 if (kvm_vcpu_is_bsp(&svm->vcpu))
1187 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1188
1189 return &svm->vcpu;
1190
1191free_page4:
1192 __free_page(hsave_page);
1193free_page3:
1194 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1195free_page2:
1196 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1197free_page1:
1198 __free_page(page);
1199uninit:
1200 kvm_vcpu_uninit(&svm->vcpu);
1201free_svm:
1202 kmem_cache_free(kvm_vcpu_cache, svm);
1203out:
1204 return ERR_PTR(err);
1205}
1206
1207static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1208{
1209 struct vcpu_svm *svm = to_svm(vcpu);
1210
1211 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1212 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1213 __free_page(virt_to_page(svm->nested.hsave));
1214 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1215 kvm_vcpu_uninit(vcpu);
1216 kmem_cache_free(kvm_vcpu_cache, svm);
1217}
1218
1219static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1220{
1221 struct vcpu_svm *svm = to_svm(vcpu);
1222 int i;
1223
1224 if (unlikely(cpu != vcpu->cpu)) {
1225 svm->asid_generation = 0;
1226 mark_all_dirty(svm->vmcb);
1227 }
1228
1229#ifdef CONFIG_X86_64
1230 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1231#endif
1232 savesegment(fs, svm->host.fs);
1233 savesegment(gs, svm->host.gs);
1234 svm->host.ldt = kvm_read_ldt();
1235
1236 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1237 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1238
1239 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1240 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1241 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1242 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1243 }
1244}
1245
1246static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1247{
1248 struct vcpu_svm *svm = to_svm(vcpu);
1249 int i;
1250
1251 ++vcpu->stat.host_state_reload;
1252 kvm_load_ldt(svm->host.ldt);
1253#ifdef CONFIG_X86_64
1254 loadsegment(fs, svm->host.fs);
1255 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1256 load_gs_index(svm->host.gs);
1257#else
1258#ifdef CONFIG_X86_32_LAZY_GS
1259 loadsegment(gs, svm->host.gs);
1260#endif
1261#endif
1262 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1263 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1264}
1265
1266static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1267{
1268 return to_svm(vcpu)->vmcb->save.rflags;
1269}
1270
1271static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1272{
1273 to_svm(vcpu)->vmcb->save.rflags = rflags;
1274}
1275
1276static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1277{
1278 switch (reg) {
1279 case VCPU_EXREG_PDPTR:
1280 BUG_ON(!npt_enabled);
1281 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1282 break;
1283 default:
1284 BUG();
1285 }
1286}
1287
1288static void svm_set_vintr(struct vcpu_svm *svm)
1289{
1290 set_intercept(svm, INTERCEPT_VINTR);
1291}
1292
1293static void svm_clear_vintr(struct vcpu_svm *svm)
1294{
1295 clr_intercept(svm, INTERCEPT_VINTR);
1296}
1297
1298static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1299{
1300 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1301
1302 switch (seg) {
1303 case VCPU_SREG_CS: return &save->cs;
1304 case VCPU_SREG_DS: return &save->ds;
1305 case VCPU_SREG_ES: return &save->es;
1306 case VCPU_SREG_FS: return &save->fs;
1307 case VCPU_SREG_GS: return &save->gs;
1308 case VCPU_SREG_SS: return &save->ss;
1309 case VCPU_SREG_TR: return &save->tr;
1310 case VCPU_SREG_LDTR: return &save->ldtr;
1311 }
1312 BUG();
1313 return NULL;
1314}
1315
1316static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1317{
1318 struct vmcb_seg *s = svm_seg(vcpu, seg);
1319
1320 return s->base;
1321}
1322
1323static void svm_get_segment(struct kvm_vcpu *vcpu,
1324 struct kvm_segment *var, int seg)
1325{
1326 struct vmcb_seg *s = svm_seg(vcpu, seg);
1327
1328 var->base = s->base;
1329 var->limit = s->limit;
1330 var->selector = s->selector;
1331 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1332 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1333 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1334 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1335 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1336 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1337 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1338 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1339
1340 /*
1341 * AMD's VMCB does not have an explicit unusable field, so emulate it
1342 * for cross vendor migration purposes by "not present"
1343 */
1344 var->unusable = !var->present || (var->type == 0);
1345
1346 switch (seg) {
1347 case VCPU_SREG_CS:
1348 /*
1349 * SVM always stores 0 for the 'G' bit in the CS selector in
1350 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1351 * Intel's VMENTRY has a check on the 'G' bit.
1352 */
1353 var->g = s->limit > 0xfffff;
1354 break;
1355 case VCPU_SREG_TR:
1356 /*
1357 * Work around a bug where the busy flag in the tr selector
1358 * isn't exposed
1359 */
1360 var->type |= 0x2;
1361 break;
1362 case VCPU_SREG_DS:
1363 case VCPU_SREG_ES:
1364 case VCPU_SREG_FS:
1365 case VCPU_SREG_GS:
1366 /*
1367 * The accessed bit must always be set in the segment
1368 * descriptor cache, although it can be cleared in the
1369 * descriptor, the cached bit always remains at 1. Since
1370 * Intel has a check on this, set it here to support
1371 * cross-vendor migration.
1372 */
1373 if (!var->unusable)
1374 var->type |= 0x1;
1375 break;
1376 case VCPU_SREG_SS:
1377 /*
1378 * On AMD CPUs sometimes the DB bit in the segment
1379 * descriptor is left as 1, although the whole segment has
1380 * been made unusable. Clear it here to pass an Intel VMX
1381 * entry check when cross vendor migrating.
1382 */
1383 if (var->unusable)
1384 var->db = 0;
1385 break;
1386 }
1387}
1388
1389static int svm_get_cpl(struct kvm_vcpu *vcpu)
1390{
1391 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1392
1393 return save->cpl;
1394}
1395
1396static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1397{
1398 struct vcpu_svm *svm = to_svm(vcpu);
1399
1400 dt->size = svm->vmcb->save.idtr.limit;
1401 dt->address = svm->vmcb->save.idtr.base;
1402}
1403
1404static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1405{
1406 struct vcpu_svm *svm = to_svm(vcpu);
1407
1408 svm->vmcb->save.idtr.limit = dt->size;
1409 svm->vmcb->save.idtr.base = dt->address ;
1410 mark_dirty(svm->vmcb, VMCB_DT);
1411}
1412
1413static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1414{
1415 struct vcpu_svm *svm = to_svm(vcpu);
1416
1417 dt->size = svm->vmcb->save.gdtr.limit;
1418 dt->address = svm->vmcb->save.gdtr.base;
1419}
1420
1421static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1422{
1423 struct vcpu_svm *svm = to_svm(vcpu);
1424
1425 svm->vmcb->save.gdtr.limit = dt->size;
1426 svm->vmcb->save.gdtr.base = dt->address ;
1427 mark_dirty(svm->vmcb, VMCB_DT);
1428}
1429
1430static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1431{
1432}
1433
1434static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1435{
1436}
1437
1438static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1439{
1440}
1441
1442static void update_cr0_intercept(struct vcpu_svm *svm)
1443{
1444 ulong gcr0 = svm->vcpu.arch.cr0;
1445 u64 *hcr0 = &svm->vmcb->save.cr0;
1446
1447 if (!svm->vcpu.fpu_active)
1448 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1449 else
1450 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1451 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1452
1453 mark_dirty(svm->vmcb, VMCB_CR);
1454
1455 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1456 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1457 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1458 } else {
1459 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1460 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1461 }
1462}
1463
1464static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1465{
1466 struct vcpu_svm *svm = to_svm(vcpu);
1467
1468#ifdef CONFIG_X86_64
1469 if (vcpu->arch.efer & EFER_LME) {
1470 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1471 vcpu->arch.efer |= EFER_LMA;
1472 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1473 }
1474
1475 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1476 vcpu->arch.efer &= ~EFER_LMA;
1477 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1478 }
1479 }
1480#endif
1481 vcpu->arch.cr0 = cr0;
1482
1483 if (!npt_enabled)
1484 cr0 |= X86_CR0_PG | X86_CR0_WP;
1485
1486 if (!vcpu->fpu_active)
1487 cr0 |= X86_CR0_TS;
1488 /*
1489 * re-enable caching here because the QEMU bios
1490 * does not do it - this results in some delay at
1491 * reboot
1492 */
1493 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1494 svm->vmcb->save.cr0 = cr0;
1495 mark_dirty(svm->vmcb, VMCB_CR);
1496 update_cr0_intercept(svm);
1497}
1498
1499static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1500{
1501 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1502 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1503
1504 if (cr4 & X86_CR4_VMXE)
1505 return 1;
1506
1507 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1508 svm_flush_tlb(vcpu);
1509
1510 vcpu->arch.cr4 = cr4;
1511 if (!npt_enabled)
1512 cr4 |= X86_CR4_PAE;
1513 cr4 |= host_cr4_mce;
1514 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1515 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1516 return 0;
1517}
1518
1519static void svm_set_segment(struct kvm_vcpu *vcpu,
1520 struct kvm_segment *var, int seg)
1521{
1522 struct vcpu_svm *svm = to_svm(vcpu);
1523 struct vmcb_seg *s = svm_seg(vcpu, seg);
1524
1525 s->base = var->base;
1526 s->limit = var->limit;
1527 s->selector = var->selector;
1528 if (var->unusable)
1529 s->attrib = 0;
1530 else {
1531 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1532 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1533 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1534 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1535 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1536 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1537 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1538 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1539 }
1540 if (seg == VCPU_SREG_CS)
1541 svm->vmcb->save.cpl
1542 = (svm->vmcb->save.cs.attrib
1543 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1544
1545 mark_dirty(svm->vmcb, VMCB_SEG);
1546}
1547
1548static void update_db_intercept(struct kvm_vcpu *vcpu)
1549{
1550 struct vcpu_svm *svm = to_svm(vcpu);
1551
1552 clr_exception_intercept(svm, DB_VECTOR);
1553 clr_exception_intercept(svm, BP_VECTOR);
1554
1555 if (svm->nmi_singlestep)
1556 set_exception_intercept(svm, DB_VECTOR);
1557
1558 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1559 if (vcpu->guest_debug &
1560 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1561 set_exception_intercept(svm, DB_VECTOR);
1562 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1563 set_exception_intercept(svm, BP_VECTOR);
1564 } else
1565 vcpu->guest_debug = 0;
1566}
1567
1568static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1569{
1570 struct vcpu_svm *svm = to_svm(vcpu);
1571
1572 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1573 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1574 else
1575 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1576
1577 mark_dirty(svm->vmcb, VMCB_DR);
1578
1579 update_db_intercept(vcpu);
1580}
1581
1582static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1583{
1584 if (sd->next_asid > sd->max_asid) {
1585 ++sd->asid_generation;
1586 sd->next_asid = 1;
1587 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1588 }
1589
1590 svm->asid_generation = sd->asid_generation;
1591 svm->vmcb->control.asid = sd->next_asid++;
1592
1593 mark_dirty(svm->vmcb, VMCB_ASID);
1594}
1595
1596static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1597{
1598 struct vcpu_svm *svm = to_svm(vcpu);
1599
1600 svm->vmcb->save.dr7 = value;
1601 mark_dirty(svm->vmcb, VMCB_DR);
1602}
1603
1604static int pf_interception(struct vcpu_svm *svm)
1605{
1606 u64 fault_address = svm->vmcb->control.exit_info_2;
1607 u32 error_code;
1608 int r = 1;
1609
1610 switch (svm->apf_reason) {
1611 default:
1612 error_code = svm->vmcb->control.exit_info_1;
1613
1614 trace_kvm_page_fault(fault_address, error_code);
1615 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1616 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1617 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1618 svm->vmcb->control.insn_bytes,
1619 svm->vmcb->control.insn_len);
1620 break;
1621 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1622 svm->apf_reason = 0;
1623 local_irq_disable();
1624 kvm_async_pf_task_wait(fault_address);
1625 local_irq_enable();
1626 break;
1627 case KVM_PV_REASON_PAGE_READY:
1628 svm->apf_reason = 0;
1629 local_irq_disable();
1630 kvm_async_pf_task_wake(fault_address);
1631 local_irq_enable();
1632 break;
1633 }
1634 return r;
1635}
1636
1637static int db_interception(struct vcpu_svm *svm)
1638{
1639 struct kvm_run *kvm_run = svm->vcpu.run;
1640
1641 if (!(svm->vcpu.guest_debug &
1642 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1643 !svm->nmi_singlestep) {
1644 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1645 return 1;
1646 }
1647
1648 if (svm->nmi_singlestep) {
1649 svm->nmi_singlestep = false;
1650 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1651 svm->vmcb->save.rflags &=
1652 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1653 update_db_intercept(&svm->vcpu);
1654 }
1655
1656 if (svm->vcpu.guest_debug &
1657 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1658 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1659 kvm_run->debug.arch.pc =
1660 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1661 kvm_run->debug.arch.exception = DB_VECTOR;
1662 return 0;
1663 }
1664
1665 return 1;
1666}
1667
1668static int bp_interception(struct vcpu_svm *svm)
1669{
1670 struct kvm_run *kvm_run = svm->vcpu.run;
1671
1672 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1673 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1674 kvm_run->debug.arch.exception = BP_VECTOR;
1675 return 0;
1676}
1677
1678static int ud_interception(struct vcpu_svm *svm)
1679{
1680 int er;
1681
1682 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1683 if (er != EMULATE_DONE)
1684 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1685 return 1;
1686}
1687
1688static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1689{
1690 struct vcpu_svm *svm = to_svm(vcpu);
1691
1692 clr_exception_intercept(svm, NM_VECTOR);
1693
1694 svm->vcpu.fpu_active = 1;
1695 update_cr0_intercept(svm);
1696}
1697
1698static int nm_interception(struct vcpu_svm *svm)
1699{
1700 svm_fpu_activate(&svm->vcpu);
1701 return 1;
1702}
1703
1704static bool is_erratum_383(void)
1705{
1706 int err, i;
1707 u64 value;
1708
1709 if (!erratum_383_found)
1710 return false;
1711
1712 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1713 if (err)
1714 return false;
1715
1716 /* Bit 62 may or may not be set for this mce */
1717 value &= ~(1ULL << 62);
1718
1719 if (value != 0xb600000000010015ULL)
1720 return false;
1721
1722 /* Clear MCi_STATUS registers */
1723 for (i = 0; i < 6; ++i)
1724 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1725
1726 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1727 if (!err) {
1728 u32 low, high;
1729
1730 value &= ~(1ULL << 2);
1731 low = lower_32_bits(value);
1732 high = upper_32_bits(value);
1733
1734 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1735 }
1736
1737 /* Flush tlb to evict multi-match entries */
1738 __flush_tlb_all();
1739
1740 return true;
1741}
1742
1743static void svm_handle_mce(struct vcpu_svm *svm)
1744{
1745 if (is_erratum_383()) {
1746 /*
1747 * Erratum 383 triggered. Guest state is corrupt so kill the
1748 * guest.
1749 */
1750 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1751
1752 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1753
1754 return;
1755 }
1756
1757 /*
1758 * On an #MC intercept the MCE handler is not called automatically in
1759 * the host. So do it by hand here.
1760 */
1761 asm volatile (
1762 "int $0x12\n");
1763 /* not sure if we ever come back to this point */
1764
1765 return;
1766}
1767
1768static int mc_interception(struct vcpu_svm *svm)
1769{
1770 return 1;
1771}
1772
1773static int shutdown_interception(struct vcpu_svm *svm)
1774{
1775 struct kvm_run *kvm_run = svm->vcpu.run;
1776
1777 /*
1778 * VMCB is undefined after a SHUTDOWN intercept
1779 * so reinitialize it.
1780 */
1781 clear_page(svm->vmcb);
1782 init_vmcb(svm);
1783
1784 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1785 return 0;
1786}
1787
1788static int io_interception(struct vcpu_svm *svm)
1789{
1790 struct kvm_vcpu *vcpu = &svm->vcpu;
1791 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1792 int size, in, string;
1793 unsigned port;
1794
1795 ++svm->vcpu.stat.io_exits;
1796 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1797 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1798 if (string || in)
1799 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1800
1801 port = io_info >> 16;
1802 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1803 svm->next_rip = svm->vmcb->control.exit_info_2;
1804 skip_emulated_instruction(&svm->vcpu);
1805
1806 return kvm_fast_pio_out(vcpu, size, port);
1807}
1808
1809static int nmi_interception(struct vcpu_svm *svm)
1810{
1811 return 1;
1812}
1813
1814static int intr_interception(struct vcpu_svm *svm)
1815{
1816 ++svm->vcpu.stat.irq_exits;
1817 return 1;
1818}
1819
1820static int nop_on_interception(struct vcpu_svm *svm)
1821{
1822 return 1;
1823}
1824
1825static int halt_interception(struct vcpu_svm *svm)
1826{
1827 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1828 skip_emulated_instruction(&svm->vcpu);
1829 return kvm_emulate_halt(&svm->vcpu);
1830}
1831
1832static int vmmcall_interception(struct vcpu_svm *svm)
1833{
1834 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1835 skip_emulated_instruction(&svm->vcpu);
1836 kvm_emulate_hypercall(&svm->vcpu);
1837 return 1;
1838}
1839
1840static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1841{
1842 struct vcpu_svm *svm = to_svm(vcpu);
1843
1844 return svm->nested.nested_cr3;
1845}
1846
1847static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1848 unsigned long root)
1849{
1850 struct vcpu_svm *svm = to_svm(vcpu);
1851
1852 svm->vmcb->control.nested_cr3 = root;
1853 mark_dirty(svm->vmcb, VMCB_NPT);
1854 svm_flush_tlb(vcpu);
1855}
1856
1857static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1858 struct x86_exception *fault)
1859{
1860 struct vcpu_svm *svm = to_svm(vcpu);
1861
1862 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1863 svm->vmcb->control.exit_code_hi = 0;
1864 svm->vmcb->control.exit_info_1 = fault->error_code;
1865 svm->vmcb->control.exit_info_2 = fault->address;
1866
1867 nested_svm_vmexit(svm);
1868}
1869
1870static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1871{
1872 int r;
1873
1874 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1875
1876 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1877 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1878 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1879 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1880 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1881
1882 return r;
1883}
1884
1885static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1886{
1887 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1888}
1889
1890static int nested_svm_check_permissions(struct vcpu_svm *svm)
1891{
1892 if (!(svm->vcpu.arch.efer & EFER_SVME)
1893 || !is_paging(&svm->vcpu)) {
1894 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1895 return 1;
1896 }
1897
1898 if (svm->vmcb->save.cpl) {
1899 kvm_inject_gp(&svm->vcpu, 0);
1900 return 1;
1901 }
1902
1903 return 0;
1904}
1905
1906static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1907 bool has_error_code, u32 error_code)
1908{
1909 int vmexit;
1910
1911 if (!is_guest_mode(&svm->vcpu))
1912 return 0;
1913
1914 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1915 svm->vmcb->control.exit_code_hi = 0;
1916 svm->vmcb->control.exit_info_1 = error_code;
1917 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1918
1919 vmexit = nested_svm_intercept(svm);
1920 if (vmexit == NESTED_EXIT_DONE)
1921 svm->nested.exit_required = true;
1922
1923 return vmexit;
1924}
1925
1926/* This function returns true if it is save to enable the irq window */
1927static inline bool nested_svm_intr(struct vcpu_svm *svm)
1928{
1929 if (!is_guest_mode(&svm->vcpu))
1930 return true;
1931
1932 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1933 return true;
1934
1935 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1936 return false;
1937
1938 /*
1939 * if vmexit was already requested (by intercepted exception
1940 * for instance) do not overwrite it with "external interrupt"
1941 * vmexit.
1942 */
1943 if (svm->nested.exit_required)
1944 return false;
1945
1946 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1947 svm->vmcb->control.exit_info_1 = 0;
1948 svm->vmcb->control.exit_info_2 = 0;
1949
1950 if (svm->nested.intercept & 1ULL) {
1951 /*
1952 * The #vmexit can't be emulated here directly because this
1953 * code path runs with irqs and preemtion disabled. A
1954 * #vmexit emulation might sleep. Only signal request for
1955 * the #vmexit here.
1956 */
1957 svm->nested.exit_required = true;
1958 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1959 return false;
1960 }
1961
1962 return true;
1963}
1964
1965/* This function returns true if it is save to enable the nmi window */
1966static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1967{
1968 if (!is_guest_mode(&svm->vcpu))
1969 return true;
1970
1971 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1972 return true;
1973
1974 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1975 svm->nested.exit_required = true;
1976
1977 return false;
1978}
1979
1980static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1981{
1982 struct page *page;
1983
1984 might_sleep();
1985
1986 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1987 if (is_error_page(page))
1988 goto error;
1989
1990 *_page = page;
1991
1992 return kmap(page);
1993
1994error:
1995 kvm_release_page_clean(page);
1996 kvm_inject_gp(&svm->vcpu, 0);
1997
1998 return NULL;
1999}
2000
2001static void nested_svm_unmap(struct page *page)
2002{
2003 kunmap(page);
2004 kvm_release_page_dirty(page);
2005}
2006
2007static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2008{
2009 unsigned port;
2010 u8 val, bit;
2011 u64 gpa;
2012
2013 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2014 return NESTED_EXIT_HOST;
2015
2016 port = svm->vmcb->control.exit_info_1 >> 16;
2017 gpa = svm->nested.vmcb_iopm + (port / 8);
2018 bit = port % 8;
2019 val = 0;
2020
2021 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2022 val &= (1 << bit);
2023
2024 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2025}
2026
2027static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2028{
2029 u32 offset, msr, value;
2030 int write, mask;
2031
2032 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2033 return NESTED_EXIT_HOST;
2034
2035 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2036 offset = svm_msrpm_offset(msr);
2037 write = svm->vmcb->control.exit_info_1 & 1;
2038 mask = 1 << ((2 * (msr & 0xf)) + write);
2039
2040 if (offset == MSR_INVALID)
2041 return NESTED_EXIT_DONE;
2042
2043 /* Offset is in 32 bit units but need in 8 bit units */
2044 offset *= 4;
2045
2046 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2047 return NESTED_EXIT_DONE;
2048
2049 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2050}
2051
2052static int nested_svm_exit_special(struct vcpu_svm *svm)
2053{
2054 u32 exit_code = svm->vmcb->control.exit_code;
2055
2056 switch (exit_code) {
2057 case SVM_EXIT_INTR:
2058 case SVM_EXIT_NMI:
2059 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2060 return NESTED_EXIT_HOST;
2061 case SVM_EXIT_NPF:
2062 /* For now we are always handling NPFs when using them */
2063 if (npt_enabled)
2064 return NESTED_EXIT_HOST;
2065 break;
2066 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2067 /* When we're shadowing, trap PFs, but not async PF */
2068 if (!npt_enabled && svm->apf_reason == 0)
2069 return NESTED_EXIT_HOST;
2070 break;
2071 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2072 nm_interception(svm);
2073 break;
2074 default:
2075 break;
2076 }
2077
2078 return NESTED_EXIT_CONTINUE;
2079}
2080
2081/*
2082 * If this function returns true, this #vmexit was already handled
2083 */
2084static int nested_svm_intercept(struct vcpu_svm *svm)
2085{
2086 u32 exit_code = svm->vmcb->control.exit_code;
2087 int vmexit = NESTED_EXIT_HOST;
2088
2089 switch (exit_code) {
2090 case SVM_EXIT_MSR:
2091 vmexit = nested_svm_exit_handled_msr(svm);
2092 break;
2093 case SVM_EXIT_IOIO:
2094 vmexit = nested_svm_intercept_ioio(svm);
2095 break;
2096 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2097 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2098 if (svm->nested.intercept_cr & bit)
2099 vmexit = NESTED_EXIT_DONE;
2100 break;
2101 }
2102 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2103 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2104 if (svm->nested.intercept_dr & bit)
2105 vmexit = NESTED_EXIT_DONE;
2106 break;
2107 }
2108 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2109 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2110 if (svm->nested.intercept_exceptions & excp_bits)
2111 vmexit = NESTED_EXIT_DONE;
2112 /* async page fault always cause vmexit */
2113 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2114 svm->apf_reason != 0)
2115 vmexit = NESTED_EXIT_DONE;
2116 break;
2117 }
2118 case SVM_EXIT_ERR: {
2119 vmexit = NESTED_EXIT_DONE;
2120 break;
2121 }
2122 default: {
2123 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2124 if (svm->nested.intercept & exit_bits)
2125 vmexit = NESTED_EXIT_DONE;
2126 }
2127 }
2128
2129 return vmexit;
2130}
2131
2132static int nested_svm_exit_handled(struct vcpu_svm *svm)
2133{
2134 int vmexit;
2135
2136 vmexit = nested_svm_intercept(svm);
2137
2138 if (vmexit == NESTED_EXIT_DONE)
2139 nested_svm_vmexit(svm);
2140
2141 return vmexit;
2142}
2143
2144static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2145{
2146 struct vmcb_control_area *dst = &dst_vmcb->control;
2147 struct vmcb_control_area *from = &from_vmcb->control;
2148
2149 dst->intercept_cr = from->intercept_cr;
2150 dst->intercept_dr = from->intercept_dr;
2151 dst->intercept_exceptions = from->intercept_exceptions;
2152 dst->intercept = from->intercept;
2153 dst->iopm_base_pa = from->iopm_base_pa;
2154 dst->msrpm_base_pa = from->msrpm_base_pa;
2155 dst->tsc_offset = from->tsc_offset;
2156 dst->asid = from->asid;
2157 dst->tlb_ctl = from->tlb_ctl;
2158 dst->int_ctl = from->int_ctl;
2159 dst->int_vector = from->int_vector;
2160 dst->int_state = from->int_state;
2161 dst->exit_code = from->exit_code;
2162 dst->exit_code_hi = from->exit_code_hi;
2163 dst->exit_info_1 = from->exit_info_1;
2164 dst->exit_info_2 = from->exit_info_2;
2165 dst->exit_int_info = from->exit_int_info;
2166 dst->exit_int_info_err = from->exit_int_info_err;
2167 dst->nested_ctl = from->nested_ctl;
2168 dst->event_inj = from->event_inj;
2169 dst->event_inj_err = from->event_inj_err;
2170 dst->nested_cr3 = from->nested_cr3;
2171 dst->lbr_ctl = from->lbr_ctl;
2172}
2173
2174static int nested_svm_vmexit(struct vcpu_svm *svm)
2175{
2176 struct vmcb *nested_vmcb;
2177 struct vmcb *hsave = svm->nested.hsave;
2178 struct vmcb *vmcb = svm->vmcb;
2179 struct page *page;
2180
2181 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2182 vmcb->control.exit_info_1,
2183 vmcb->control.exit_info_2,
2184 vmcb->control.exit_int_info,
2185 vmcb->control.exit_int_info_err);
2186
2187 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2188 if (!nested_vmcb)
2189 return 1;
2190
2191 /* Exit Guest-Mode */
2192 leave_guest_mode(&svm->vcpu);
2193 svm->nested.vmcb = 0;
2194
2195 /* Give the current vmcb to the guest */
2196 disable_gif(svm);
2197
2198 nested_vmcb->save.es = vmcb->save.es;
2199 nested_vmcb->save.cs = vmcb->save.cs;
2200 nested_vmcb->save.ss = vmcb->save.ss;
2201 nested_vmcb->save.ds = vmcb->save.ds;
2202 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2203 nested_vmcb->save.idtr = vmcb->save.idtr;
2204 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2205 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2206 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2207 nested_vmcb->save.cr2 = vmcb->save.cr2;
2208 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2209 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2210 nested_vmcb->save.rip = vmcb->save.rip;
2211 nested_vmcb->save.rsp = vmcb->save.rsp;
2212 nested_vmcb->save.rax = vmcb->save.rax;
2213 nested_vmcb->save.dr7 = vmcb->save.dr7;
2214 nested_vmcb->save.dr6 = vmcb->save.dr6;
2215 nested_vmcb->save.cpl = vmcb->save.cpl;
2216
2217 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2218 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2219 nested_vmcb->control.int_state = vmcb->control.int_state;
2220 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2221 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2222 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2223 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2224 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2225 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2226 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2227
2228 /*
2229 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2230 * to make sure that we do not lose injected events. So check event_inj
2231 * here and copy it to exit_int_info if it is valid.
2232 * Exit_int_info and event_inj can't be both valid because the case
2233 * below only happens on a VMRUN instruction intercept which has
2234 * no valid exit_int_info set.
2235 */
2236 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2237 struct vmcb_control_area *nc = &nested_vmcb->control;
2238
2239 nc->exit_int_info = vmcb->control.event_inj;
2240 nc->exit_int_info_err = vmcb->control.event_inj_err;
2241 }
2242
2243 nested_vmcb->control.tlb_ctl = 0;
2244 nested_vmcb->control.event_inj = 0;
2245 nested_vmcb->control.event_inj_err = 0;
2246
2247 /* We always set V_INTR_MASKING and remember the old value in hflags */
2248 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2249 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2250
2251 /* Restore the original control entries */
2252 copy_vmcb_control_area(vmcb, hsave);
2253
2254 kvm_clear_exception_queue(&svm->vcpu);
2255 kvm_clear_interrupt_queue(&svm->vcpu);
2256
2257 svm->nested.nested_cr3 = 0;
2258
2259 /* Restore selected save entries */
2260 svm->vmcb->save.es = hsave->save.es;
2261 svm->vmcb->save.cs = hsave->save.cs;
2262 svm->vmcb->save.ss = hsave->save.ss;
2263 svm->vmcb->save.ds = hsave->save.ds;
2264 svm->vmcb->save.gdtr = hsave->save.gdtr;
2265 svm->vmcb->save.idtr = hsave->save.idtr;
2266 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2267 svm_set_efer(&svm->vcpu, hsave->save.efer);
2268 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2269 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2270 if (npt_enabled) {
2271 svm->vmcb->save.cr3 = hsave->save.cr3;
2272 svm->vcpu.arch.cr3 = hsave->save.cr3;
2273 } else {
2274 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2275 }
2276 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2277 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2278 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2279 svm->vmcb->save.dr7 = 0;
2280 svm->vmcb->save.cpl = 0;
2281 svm->vmcb->control.exit_int_info = 0;
2282
2283 mark_all_dirty(svm->vmcb);
2284
2285 nested_svm_unmap(page);
2286
2287 nested_svm_uninit_mmu_context(&svm->vcpu);
2288 kvm_mmu_reset_context(&svm->vcpu);
2289 kvm_mmu_load(&svm->vcpu);
2290
2291 return 0;
2292}
2293
2294static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2295{
2296 /*
2297 * This function merges the msr permission bitmaps of kvm and the
2298 * nested vmcb. It is omptimized in that it only merges the parts where
2299 * the kvm msr permission bitmap may contain zero bits
2300 */
2301 int i;
2302
2303 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2304 return true;
2305
2306 for (i = 0; i < MSRPM_OFFSETS; i++) {
2307 u32 value, p;
2308 u64 offset;
2309
2310 if (msrpm_offsets[i] == 0xffffffff)
2311 break;
2312
2313 p = msrpm_offsets[i];
2314 offset = svm->nested.vmcb_msrpm + (p * 4);
2315
2316 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2317 return false;
2318
2319 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2320 }
2321
2322 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2323
2324 return true;
2325}
2326
2327static bool nested_vmcb_checks(struct vmcb *vmcb)
2328{
2329 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2330 return false;
2331
2332 if (vmcb->control.asid == 0)
2333 return false;
2334
2335 if (vmcb->control.nested_ctl && !npt_enabled)
2336 return false;
2337
2338 return true;
2339}
2340
2341static bool nested_svm_vmrun(struct vcpu_svm *svm)
2342{
2343 struct vmcb *nested_vmcb;
2344 struct vmcb *hsave = svm->nested.hsave;
2345 struct vmcb *vmcb = svm->vmcb;
2346 struct page *page;
2347 u64 vmcb_gpa;
2348
2349 vmcb_gpa = svm->vmcb->save.rax;
2350
2351 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2352 if (!nested_vmcb)
2353 return false;
2354
2355 if (!nested_vmcb_checks(nested_vmcb)) {
2356 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2357 nested_vmcb->control.exit_code_hi = 0;
2358 nested_vmcb->control.exit_info_1 = 0;
2359 nested_vmcb->control.exit_info_2 = 0;
2360
2361 nested_svm_unmap(page);
2362
2363 return false;
2364 }
2365
2366 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2367 nested_vmcb->save.rip,
2368 nested_vmcb->control.int_ctl,
2369 nested_vmcb->control.event_inj,
2370 nested_vmcb->control.nested_ctl);
2371
2372 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2373 nested_vmcb->control.intercept_cr >> 16,
2374 nested_vmcb->control.intercept_exceptions,
2375 nested_vmcb->control.intercept);
2376
2377 /* Clear internal status */
2378 kvm_clear_exception_queue(&svm->vcpu);
2379 kvm_clear_interrupt_queue(&svm->vcpu);
2380
2381 /*
2382 * Save the old vmcb, so we don't need to pick what we save, but can
2383 * restore everything when a VMEXIT occurs
2384 */
2385 hsave->save.es = vmcb->save.es;
2386 hsave->save.cs = vmcb->save.cs;
2387 hsave->save.ss = vmcb->save.ss;
2388 hsave->save.ds = vmcb->save.ds;
2389 hsave->save.gdtr = vmcb->save.gdtr;
2390 hsave->save.idtr = vmcb->save.idtr;
2391 hsave->save.efer = svm->vcpu.arch.efer;
2392 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2393 hsave->save.cr4 = svm->vcpu.arch.cr4;
2394 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2395 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2396 hsave->save.rsp = vmcb->save.rsp;
2397 hsave->save.rax = vmcb->save.rax;
2398 if (npt_enabled)
2399 hsave->save.cr3 = vmcb->save.cr3;
2400 else
2401 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2402
2403 copy_vmcb_control_area(hsave, vmcb);
2404
2405 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2406 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2407 else
2408 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2409
2410 if (nested_vmcb->control.nested_ctl) {
2411 kvm_mmu_unload(&svm->vcpu);
2412 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2413 nested_svm_init_mmu_context(&svm->vcpu);
2414 }
2415
2416 /* Load the nested guest state */
2417 svm->vmcb->save.es = nested_vmcb->save.es;
2418 svm->vmcb->save.cs = nested_vmcb->save.cs;
2419 svm->vmcb->save.ss = nested_vmcb->save.ss;
2420 svm->vmcb->save.ds = nested_vmcb->save.ds;
2421 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2422 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2423 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2424 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2425 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2426 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2427 if (npt_enabled) {
2428 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2429 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2430 } else
2431 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2432
2433 /* Guest paging mode is active - reset mmu */
2434 kvm_mmu_reset_context(&svm->vcpu);
2435
2436 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2437 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2438 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2439 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2440
2441 /* In case we don't even reach vcpu_run, the fields are not updated */
2442 svm->vmcb->save.rax = nested_vmcb->save.rax;
2443 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2444 svm->vmcb->save.rip = nested_vmcb->save.rip;
2445 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2446 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2447 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2448
2449 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2450 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2451
2452 /* cache intercepts */
2453 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2454 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2455 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2456 svm->nested.intercept = nested_vmcb->control.intercept;
2457
2458 svm_flush_tlb(&svm->vcpu);
2459 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2460 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2461 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2462 else
2463 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2464
2465 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2466 /* We only want the cr8 intercept bits of the guest */
2467 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2468 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2469 }
2470
2471 /* We don't want to see VMMCALLs from a nested guest */
2472 clr_intercept(svm, INTERCEPT_VMMCALL);
2473
2474 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2475 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2476 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2477 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2478 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2479 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2480
2481 nested_svm_unmap(page);
2482
2483 /* Enter Guest-Mode */
2484 enter_guest_mode(&svm->vcpu);
2485
2486 /*
2487 * Merge guest and host intercepts - must be called with vcpu in
2488 * guest-mode to take affect here
2489 */
2490 recalc_intercepts(svm);
2491
2492 svm->nested.vmcb = vmcb_gpa;
2493
2494 enable_gif(svm);
2495
2496 mark_all_dirty(svm->vmcb);
2497
2498 return true;
2499}
2500
2501static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2502{
2503 to_vmcb->save.fs = from_vmcb->save.fs;
2504 to_vmcb->save.gs = from_vmcb->save.gs;
2505 to_vmcb->save.tr = from_vmcb->save.tr;
2506 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2507 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2508 to_vmcb->save.star = from_vmcb->save.star;
2509 to_vmcb->save.lstar = from_vmcb->save.lstar;
2510 to_vmcb->save.cstar = from_vmcb->save.cstar;
2511 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2512 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2513 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2514 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2515}
2516
2517static int vmload_interception(struct vcpu_svm *svm)
2518{
2519 struct vmcb *nested_vmcb;
2520 struct page *page;
2521
2522 if (nested_svm_check_permissions(svm))
2523 return 1;
2524
2525 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2526 if (!nested_vmcb)
2527 return 1;
2528
2529 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2530 skip_emulated_instruction(&svm->vcpu);
2531
2532 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2533 nested_svm_unmap(page);
2534
2535 return 1;
2536}
2537
2538static int vmsave_interception(struct vcpu_svm *svm)
2539{
2540 struct vmcb *nested_vmcb;
2541 struct page *page;
2542
2543 if (nested_svm_check_permissions(svm))
2544 return 1;
2545
2546 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2547 if (!nested_vmcb)
2548 return 1;
2549
2550 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2551 skip_emulated_instruction(&svm->vcpu);
2552
2553 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2554 nested_svm_unmap(page);
2555
2556 return 1;
2557}
2558
2559static int vmrun_interception(struct vcpu_svm *svm)
2560{
2561 if (nested_svm_check_permissions(svm))
2562 return 1;
2563
2564 /* Save rip after vmrun instruction */
2565 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2566
2567 if (!nested_svm_vmrun(svm))
2568 return 1;
2569
2570 if (!nested_svm_vmrun_msrpm(svm))
2571 goto failed;
2572
2573 return 1;
2574
2575failed:
2576
2577 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2578 svm->vmcb->control.exit_code_hi = 0;
2579 svm->vmcb->control.exit_info_1 = 0;
2580 svm->vmcb->control.exit_info_2 = 0;
2581
2582 nested_svm_vmexit(svm);
2583
2584 return 1;
2585}
2586
2587static int stgi_interception(struct vcpu_svm *svm)
2588{
2589 if (nested_svm_check_permissions(svm))
2590 return 1;
2591
2592 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2593 skip_emulated_instruction(&svm->vcpu);
2594 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2595
2596 enable_gif(svm);
2597
2598 return 1;
2599}
2600
2601static int clgi_interception(struct vcpu_svm *svm)
2602{
2603 if (nested_svm_check_permissions(svm))
2604 return 1;
2605
2606 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2607 skip_emulated_instruction(&svm->vcpu);
2608
2609 disable_gif(svm);
2610
2611 /* After a CLGI no interrupts should come */
2612 svm_clear_vintr(svm);
2613 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2614
2615 mark_dirty(svm->vmcb, VMCB_INTR);
2616
2617 return 1;
2618}
2619
2620static int invlpga_interception(struct vcpu_svm *svm)
2621{
2622 struct kvm_vcpu *vcpu = &svm->vcpu;
2623
2624 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2625 vcpu->arch.regs[VCPU_REGS_RAX]);
2626
2627 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2628 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2629
2630 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2631 skip_emulated_instruction(&svm->vcpu);
2632 return 1;
2633}
2634
2635static int skinit_interception(struct vcpu_svm *svm)
2636{
2637 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2638
2639 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2640 return 1;
2641}
2642
2643static int xsetbv_interception(struct vcpu_svm *svm)
2644{
2645 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2646 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2647
2648 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2649 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2650 skip_emulated_instruction(&svm->vcpu);
2651 }
2652
2653 return 1;
2654}
2655
2656static int invalid_op_interception(struct vcpu_svm *svm)
2657{
2658 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2659 return 1;
2660}
2661
2662static int task_switch_interception(struct vcpu_svm *svm)
2663{
2664 u16 tss_selector;
2665 int reason;
2666 int int_type = svm->vmcb->control.exit_int_info &
2667 SVM_EXITINTINFO_TYPE_MASK;
2668 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2669 uint32_t type =
2670 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2671 uint32_t idt_v =
2672 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2673 bool has_error_code = false;
2674 u32 error_code = 0;
2675
2676 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2677
2678 if (svm->vmcb->control.exit_info_2 &
2679 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2680 reason = TASK_SWITCH_IRET;
2681 else if (svm->vmcb->control.exit_info_2 &
2682 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2683 reason = TASK_SWITCH_JMP;
2684 else if (idt_v)
2685 reason = TASK_SWITCH_GATE;
2686 else
2687 reason = TASK_SWITCH_CALL;
2688
2689 if (reason == TASK_SWITCH_GATE) {
2690 switch (type) {
2691 case SVM_EXITINTINFO_TYPE_NMI:
2692 svm->vcpu.arch.nmi_injected = false;
2693 break;
2694 case SVM_EXITINTINFO_TYPE_EXEPT:
2695 if (svm->vmcb->control.exit_info_2 &
2696 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2697 has_error_code = true;
2698 error_code =
2699 (u32)svm->vmcb->control.exit_info_2;
2700 }
2701 kvm_clear_exception_queue(&svm->vcpu);
2702 break;
2703 case SVM_EXITINTINFO_TYPE_INTR:
2704 kvm_clear_interrupt_queue(&svm->vcpu);
2705 break;
2706 default:
2707 break;
2708 }
2709 }
2710
2711 if (reason != TASK_SWITCH_GATE ||
2712 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2713 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2714 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2715 skip_emulated_instruction(&svm->vcpu);
2716
2717 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2718 has_error_code, error_code) == EMULATE_FAIL) {
2719 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2720 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2721 svm->vcpu.run->internal.ndata = 0;
2722 return 0;
2723 }
2724 return 1;
2725}
2726
2727static int cpuid_interception(struct vcpu_svm *svm)
2728{
2729 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2730 kvm_emulate_cpuid(&svm->vcpu);
2731 return 1;
2732}
2733
2734static int iret_interception(struct vcpu_svm *svm)
2735{
2736 ++svm->vcpu.stat.nmi_window_exits;
2737 clr_intercept(svm, INTERCEPT_IRET);
2738 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2739 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2740 return 1;
2741}
2742
2743static int invlpg_interception(struct vcpu_svm *svm)
2744{
2745 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2746 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2747
2748 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2749 skip_emulated_instruction(&svm->vcpu);
2750 return 1;
2751}
2752
2753static int emulate_on_interception(struct vcpu_svm *svm)
2754{
2755 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2756}
2757
2758bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2759{
2760 unsigned long cr0 = svm->vcpu.arch.cr0;
2761 bool ret = false;
2762 u64 intercept;
2763
2764 intercept = svm->nested.intercept;
2765
2766 if (!is_guest_mode(&svm->vcpu) ||
2767 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2768 return false;
2769
2770 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2771 val &= ~SVM_CR0_SELECTIVE_MASK;
2772
2773 if (cr0 ^ val) {
2774 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2775 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2776 }
2777
2778 return ret;
2779}
2780
2781#define CR_VALID (1ULL << 63)
2782
2783static int cr_interception(struct vcpu_svm *svm)
2784{
2785 int reg, cr;
2786 unsigned long val;
2787 int err;
2788
2789 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2790 return emulate_on_interception(svm);
2791
2792 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2793 return emulate_on_interception(svm);
2794
2795 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2796 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2797
2798 err = 0;
2799 if (cr >= 16) { /* mov to cr */
2800 cr -= 16;
2801 val = kvm_register_read(&svm->vcpu, reg);
2802 switch (cr) {
2803 case 0:
2804 if (!check_selective_cr0_intercepted(svm, val))
2805 err = kvm_set_cr0(&svm->vcpu, val);
2806 else
2807 return 1;
2808
2809 break;
2810 case 3:
2811 err = kvm_set_cr3(&svm->vcpu, val);
2812 break;
2813 case 4:
2814 err = kvm_set_cr4(&svm->vcpu, val);
2815 break;
2816 case 8:
2817 err = kvm_set_cr8(&svm->vcpu, val);
2818 break;
2819 default:
2820 WARN(1, "unhandled write to CR%d", cr);
2821 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2822 return 1;
2823 }
2824 } else { /* mov from cr */
2825 switch (cr) {
2826 case 0:
2827 val = kvm_read_cr0(&svm->vcpu);
2828 break;
2829 case 2:
2830 val = svm->vcpu.arch.cr2;
2831 break;
2832 case 3:
2833 val = kvm_read_cr3(&svm->vcpu);
2834 break;
2835 case 4:
2836 val = kvm_read_cr4(&svm->vcpu);
2837 break;
2838 case 8:
2839 val = kvm_get_cr8(&svm->vcpu);
2840 break;
2841 default:
2842 WARN(1, "unhandled read from CR%d", cr);
2843 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2844 return 1;
2845 }
2846 kvm_register_write(&svm->vcpu, reg, val);
2847 }
2848 kvm_complete_insn_gp(&svm->vcpu, err);
2849
2850 return 1;
2851}
2852
2853static int dr_interception(struct vcpu_svm *svm)
2854{
2855 int reg, dr;
2856 unsigned long val;
2857 int err;
2858
2859 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2860 return emulate_on_interception(svm);
2861
2862 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2863 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2864
2865 if (dr >= 16) { /* mov to DRn */
2866 val = kvm_register_read(&svm->vcpu, reg);
2867 kvm_set_dr(&svm->vcpu, dr - 16, val);
2868 } else {
2869 err = kvm_get_dr(&svm->vcpu, dr, &val);
2870 if (!err)
2871 kvm_register_write(&svm->vcpu, reg, val);
2872 }
2873
2874 skip_emulated_instruction(&svm->vcpu);
2875
2876 return 1;
2877}
2878
2879static int cr8_write_interception(struct vcpu_svm *svm)
2880{
2881 struct kvm_run *kvm_run = svm->vcpu.run;
2882 int r;
2883
2884 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2885 /* instruction emulation calls kvm_set_cr8() */
2886 r = cr_interception(svm);
2887 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2888 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2889 return r;
2890 }
2891 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2892 return r;
2893 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2894 return 0;
2895}
2896
2897static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2898{
2899 struct vcpu_svm *svm = to_svm(vcpu);
2900
2901 switch (ecx) {
2902 case MSR_IA32_TSC: {
2903 struct vmcb *vmcb = get_host_vmcb(svm);
2904
2905 *data = vmcb->control.tsc_offset +
2906 svm_scale_tsc(vcpu, native_read_tsc());
2907
2908 break;
2909 }
2910 case MSR_STAR:
2911 *data = svm->vmcb->save.star;
2912 break;
2913#ifdef CONFIG_X86_64
2914 case MSR_LSTAR:
2915 *data = svm->vmcb->save.lstar;
2916 break;
2917 case MSR_CSTAR:
2918 *data = svm->vmcb->save.cstar;
2919 break;
2920 case MSR_KERNEL_GS_BASE:
2921 *data = svm->vmcb->save.kernel_gs_base;
2922 break;
2923 case MSR_SYSCALL_MASK:
2924 *data = svm->vmcb->save.sfmask;
2925 break;
2926#endif
2927 case MSR_IA32_SYSENTER_CS:
2928 *data = svm->vmcb->save.sysenter_cs;
2929 break;
2930 case MSR_IA32_SYSENTER_EIP:
2931 *data = svm->sysenter_eip;
2932 break;
2933 case MSR_IA32_SYSENTER_ESP:
2934 *data = svm->sysenter_esp;
2935 break;
2936 /*
2937 * Nobody will change the following 5 values in the VMCB so we can
2938 * safely return them on rdmsr. They will always be 0 until LBRV is
2939 * implemented.
2940 */
2941 case MSR_IA32_DEBUGCTLMSR:
2942 *data = svm->vmcb->save.dbgctl;
2943 break;
2944 case MSR_IA32_LASTBRANCHFROMIP:
2945 *data = svm->vmcb->save.br_from;
2946 break;
2947 case MSR_IA32_LASTBRANCHTOIP:
2948 *data = svm->vmcb->save.br_to;
2949 break;
2950 case MSR_IA32_LASTINTFROMIP:
2951 *data = svm->vmcb->save.last_excp_from;
2952 break;
2953 case MSR_IA32_LASTINTTOIP:
2954 *data = svm->vmcb->save.last_excp_to;
2955 break;
2956 case MSR_VM_HSAVE_PA:
2957 *data = svm->nested.hsave_msr;
2958 break;
2959 case MSR_VM_CR:
2960 *data = svm->nested.vm_cr_msr;
2961 break;
2962 case MSR_IA32_UCODE_REV:
2963 *data = 0x01000065;
2964 break;
2965 default:
2966 return kvm_get_msr_common(vcpu, ecx, data);
2967 }
2968 return 0;
2969}
2970
2971static int rdmsr_interception(struct vcpu_svm *svm)
2972{
2973 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2974 u64 data;
2975
2976 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2977 trace_kvm_msr_read_ex(ecx);
2978 kvm_inject_gp(&svm->vcpu, 0);
2979 } else {
2980 trace_kvm_msr_read(ecx, data);
2981
2982 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2983 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2984 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2985 skip_emulated_instruction(&svm->vcpu);
2986 }
2987 return 1;
2988}
2989
2990static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2991{
2992 struct vcpu_svm *svm = to_svm(vcpu);
2993 int svm_dis, chg_mask;
2994
2995 if (data & ~SVM_VM_CR_VALID_MASK)
2996 return 1;
2997
2998 chg_mask = SVM_VM_CR_VALID_MASK;
2999
3000 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3001 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3002
3003 svm->nested.vm_cr_msr &= ~chg_mask;
3004 svm->nested.vm_cr_msr |= (data & chg_mask);
3005
3006 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3007
3008 /* check for svm_disable while efer.svme is set */
3009 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3010 return 1;
3011
3012 return 0;
3013}
3014
3015static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3016{
3017 struct vcpu_svm *svm = to_svm(vcpu);
3018
3019 switch (ecx) {
3020 case MSR_IA32_TSC:
3021 kvm_write_tsc(vcpu, data);
3022 break;
3023 case MSR_STAR:
3024 svm->vmcb->save.star = data;
3025 break;
3026#ifdef CONFIG_X86_64
3027 case MSR_LSTAR:
3028 svm->vmcb->save.lstar = data;
3029 break;
3030 case MSR_CSTAR:
3031 svm->vmcb->save.cstar = data;
3032 break;
3033 case MSR_KERNEL_GS_BASE:
3034 svm->vmcb->save.kernel_gs_base = data;
3035 break;
3036 case MSR_SYSCALL_MASK:
3037 svm->vmcb->save.sfmask = data;
3038 break;
3039#endif
3040 case MSR_IA32_SYSENTER_CS:
3041 svm->vmcb->save.sysenter_cs = data;
3042 break;
3043 case MSR_IA32_SYSENTER_EIP:
3044 svm->sysenter_eip = data;
3045 svm->vmcb->save.sysenter_eip = data;
3046 break;
3047 case MSR_IA32_SYSENTER_ESP:
3048 svm->sysenter_esp = data;
3049 svm->vmcb->save.sysenter_esp = data;
3050 break;
3051 case MSR_IA32_DEBUGCTLMSR:
3052 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3053 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3054 __func__, data);
3055 break;
3056 }
3057 if (data & DEBUGCTL_RESERVED_BITS)
3058 return 1;
3059
3060 svm->vmcb->save.dbgctl = data;
3061 mark_dirty(svm->vmcb, VMCB_LBR);
3062 if (data & (1ULL<<0))
3063 svm_enable_lbrv(svm);
3064 else
3065 svm_disable_lbrv(svm);
3066 break;
3067 case MSR_VM_HSAVE_PA:
3068 svm->nested.hsave_msr = data;
3069 break;
3070 case MSR_VM_CR:
3071 return svm_set_vm_cr(vcpu, data);
3072 case MSR_VM_IGNNE:
3073 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3074 break;
3075 default:
3076 return kvm_set_msr_common(vcpu, ecx, data);
3077 }
3078 return 0;
3079}
3080
3081static int wrmsr_interception(struct vcpu_svm *svm)
3082{
3083 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3084 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3085 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3086
3087
3088 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3089 if (svm_set_msr(&svm->vcpu, ecx, data)) {
3090 trace_kvm_msr_write_ex(ecx, data);
3091 kvm_inject_gp(&svm->vcpu, 0);
3092 } else {
3093 trace_kvm_msr_write(ecx, data);
3094 skip_emulated_instruction(&svm->vcpu);
3095 }
3096 return 1;
3097}
3098
3099static int msr_interception(struct vcpu_svm *svm)
3100{
3101 if (svm->vmcb->control.exit_info_1)
3102 return wrmsr_interception(svm);
3103 else
3104 return rdmsr_interception(svm);
3105}
3106
3107static int interrupt_window_interception(struct vcpu_svm *svm)
3108{
3109 struct kvm_run *kvm_run = svm->vcpu.run;
3110
3111 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3112 svm_clear_vintr(svm);
3113 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3114 mark_dirty(svm->vmcb, VMCB_INTR);
3115 /*
3116 * If the user space waits to inject interrupts, exit as soon as
3117 * possible
3118 */
3119 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3120 kvm_run->request_interrupt_window &&
3121 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3122 ++svm->vcpu.stat.irq_window_exits;
3123 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3124 return 0;
3125 }
3126
3127 return 1;
3128}
3129
3130static int pause_interception(struct vcpu_svm *svm)
3131{
3132 kvm_vcpu_on_spin(&(svm->vcpu));
3133 return 1;
3134}
3135
3136static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3137 [SVM_EXIT_READ_CR0] = cr_interception,
3138 [SVM_EXIT_READ_CR3] = cr_interception,
3139 [SVM_EXIT_READ_CR4] = cr_interception,
3140 [SVM_EXIT_READ_CR8] = cr_interception,
3141 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3142 [SVM_EXIT_WRITE_CR0] = cr_interception,
3143 [SVM_EXIT_WRITE_CR3] = cr_interception,
3144 [SVM_EXIT_WRITE_CR4] = cr_interception,
3145 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3146 [SVM_EXIT_READ_DR0] = dr_interception,
3147 [SVM_EXIT_READ_DR1] = dr_interception,
3148 [SVM_EXIT_READ_DR2] = dr_interception,
3149 [SVM_EXIT_READ_DR3] = dr_interception,
3150 [SVM_EXIT_READ_DR4] = dr_interception,
3151 [SVM_EXIT_READ_DR5] = dr_interception,
3152 [SVM_EXIT_READ_DR6] = dr_interception,
3153 [SVM_EXIT_READ_DR7] = dr_interception,
3154 [SVM_EXIT_WRITE_DR0] = dr_interception,
3155 [SVM_EXIT_WRITE_DR1] = dr_interception,
3156 [SVM_EXIT_WRITE_DR2] = dr_interception,
3157 [SVM_EXIT_WRITE_DR3] = dr_interception,
3158 [SVM_EXIT_WRITE_DR4] = dr_interception,
3159 [SVM_EXIT_WRITE_DR5] = dr_interception,
3160 [SVM_EXIT_WRITE_DR6] = dr_interception,
3161 [SVM_EXIT_WRITE_DR7] = dr_interception,
3162 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3163 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3164 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3165 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3166 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3167 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3168 [SVM_EXIT_INTR] = intr_interception,
3169 [SVM_EXIT_NMI] = nmi_interception,
3170 [SVM_EXIT_SMI] = nop_on_interception,
3171 [SVM_EXIT_INIT] = nop_on_interception,
3172 [SVM_EXIT_VINTR] = interrupt_window_interception,
3173 [SVM_EXIT_CPUID] = cpuid_interception,
3174 [SVM_EXIT_IRET] = iret_interception,
3175 [SVM_EXIT_INVD] = emulate_on_interception,
3176 [SVM_EXIT_PAUSE] = pause_interception,
3177 [SVM_EXIT_HLT] = halt_interception,
3178 [SVM_EXIT_INVLPG] = invlpg_interception,
3179 [SVM_EXIT_INVLPGA] = invlpga_interception,
3180 [SVM_EXIT_IOIO] = io_interception,
3181 [SVM_EXIT_MSR] = msr_interception,
3182 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3183 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3184 [SVM_EXIT_VMRUN] = vmrun_interception,
3185 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3186 [SVM_EXIT_VMLOAD] = vmload_interception,
3187 [SVM_EXIT_VMSAVE] = vmsave_interception,
3188 [SVM_EXIT_STGI] = stgi_interception,
3189 [SVM_EXIT_CLGI] = clgi_interception,
3190 [SVM_EXIT_SKINIT] = skinit_interception,
3191 [SVM_EXIT_WBINVD] = emulate_on_interception,
3192 [SVM_EXIT_MONITOR] = invalid_op_interception,
3193 [SVM_EXIT_MWAIT] = invalid_op_interception,
3194 [SVM_EXIT_XSETBV] = xsetbv_interception,
3195 [SVM_EXIT_NPF] = pf_interception,
3196};
3197
3198static void dump_vmcb(struct kvm_vcpu *vcpu)
3199{
3200 struct vcpu_svm *svm = to_svm(vcpu);
3201 struct vmcb_control_area *control = &svm->vmcb->control;
3202 struct vmcb_save_area *save = &svm->vmcb->save;
3203
3204 pr_err("VMCB Control Area:\n");
3205 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3206 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3207 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3208 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3209 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3210 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3211 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3212 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3213 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3214 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3215 pr_err("%-20s%d\n", "asid:", control->asid);
3216 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3217 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3218 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3219 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3220 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3221 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3222 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3223 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3224 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3225 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3226 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3227 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3228 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3229 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3230 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3231 pr_err("VMCB State Save Area:\n");
3232 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3233 "es:",
3234 save->es.selector, save->es.attrib,
3235 save->es.limit, save->es.base);
3236 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3237 "cs:",
3238 save->cs.selector, save->cs.attrib,
3239 save->cs.limit, save->cs.base);
3240 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3241 "ss:",
3242 save->ss.selector, save->ss.attrib,
3243 save->ss.limit, save->ss.base);
3244 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3245 "ds:",
3246 save->ds.selector, save->ds.attrib,
3247 save->ds.limit, save->ds.base);
3248 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3249 "fs:",
3250 save->fs.selector, save->fs.attrib,
3251 save->fs.limit, save->fs.base);
3252 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3253 "gs:",
3254 save->gs.selector, save->gs.attrib,
3255 save->gs.limit, save->gs.base);
3256 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3257 "gdtr:",
3258 save->gdtr.selector, save->gdtr.attrib,
3259 save->gdtr.limit, save->gdtr.base);
3260 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3261 "ldtr:",
3262 save->ldtr.selector, save->ldtr.attrib,
3263 save->ldtr.limit, save->ldtr.base);
3264 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3265 "idtr:",
3266 save->idtr.selector, save->idtr.attrib,
3267 save->idtr.limit, save->idtr.base);
3268 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3269 "tr:",
3270 save->tr.selector, save->tr.attrib,
3271 save->tr.limit, save->tr.base);
3272 pr_err("cpl: %d efer: %016llx\n",
3273 save->cpl, save->efer);
3274 pr_err("%-15s %016llx %-13s %016llx\n",
3275 "cr0:", save->cr0, "cr2:", save->cr2);
3276 pr_err("%-15s %016llx %-13s %016llx\n",
3277 "cr3:", save->cr3, "cr4:", save->cr4);
3278 pr_err("%-15s %016llx %-13s %016llx\n",
3279 "dr6:", save->dr6, "dr7:", save->dr7);
3280 pr_err("%-15s %016llx %-13s %016llx\n",
3281 "rip:", save->rip, "rflags:", save->rflags);
3282 pr_err("%-15s %016llx %-13s %016llx\n",
3283 "rsp:", save->rsp, "rax:", save->rax);
3284 pr_err("%-15s %016llx %-13s %016llx\n",
3285 "star:", save->star, "lstar:", save->lstar);
3286 pr_err("%-15s %016llx %-13s %016llx\n",
3287 "cstar:", save->cstar, "sfmask:", save->sfmask);
3288 pr_err("%-15s %016llx %-13s %016llx\n",
3289 "kernel_gs_base:", save->kernel_gs_base,
3290 "sysenter_cs:", save->sysenter_cs);
3291 pr_err("%-15s %016llx %-13s %016llx\n",
3292 "sysenter_esp:", save->sysenter_esp,
3293 "sysenter_eip:", save->sysenter_eip);
3294 pr_err("%-15s %016llx %-13s %016llx\n",
3295 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3296 pr_err("%-15s %016llx %-13s %016llx\n",
3297 "br_from:", save->br_from, "br_to:", save->br_to);
3298 pr_err("%-15s %016llx %-13s %016llx\n",
3299 "excp_from:", save->last_excp_from,
3300 "excp_to:", save->last_excp_to);
3301}
3302
3303static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3304{
3305 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3306
3307 *info1 = control->exit_info_1;
3308 *info2 = control->exit_info_2;
3309}
3310
3311static int handle_exit(struct kvm_vcpu *vcpu)
3312{
3313 struct vcpu_svm *svm = to_svm(vcpu);
3314 struct kvm_run *kvm_run = vcpu->run;
3315 u32 exit_code = svm->vmcb->control.exit_code;
3316
3317 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3318
3319 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3320 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3321 if (npt_enabled)
3322 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3323
3324 if (unlikely(svm->nested.exit_required)) {
3325 nested_svm_vmexit(svm);
3326 svm->nested.exit_required = false;
3327
3328 return 1;
3329 }
3330
3331 if (is_guest_mode(vcpu)) {
3332 int vmexit;
3333
3334 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3335 svm->vmcb->control.exit_info_1,
3336 svm->vmcb->control.exit_info_2,
3337 svm->vmcb->control.exit_int_info,
3338 svm->vmcb->control.exit_int_info_err);
3339
3340 vmexit = nested_svm_exit_special(svm);
3341
3342 if (vmexit == NESTED_EXIT_CONTINUE)
3343 vmexit = nested_svm_exit_handled(svm);
3344
3345 if (vmexit == NESTED_EXIT_DONE)
3346 return 1;
3347 }
3348
3349 svm_complete_interrupts(svm);
3350
3351 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3352 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3353 kvm_run->fail_entry.hardware_entry_failure_reason
3354 = svm->vmcb->control.exit_code;
3355 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3356 dump_vmcb(vcpu);
3357 return 0;
3358 }
3359
3360 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3361 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3362 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3363 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3364 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3365 "exit_code 0x%x\n",
3366 __func__, svm->vmcb->control.exit_int_info,
3367 exit_code);
3368
3369 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3370 || !svm_exit_handlers[exit_code]) {
3371 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3372 kvm_run->hw.hardware_exit_reason = exit_code;
3373 return 0;
3374 }
3375
3376 return svm_exit_handlers[exit_code](svm);
3377}
3378
3379static void reload_tss(struct kvm_vcpu *vcpu)
3380{
3381 int cpu = raw_smp_processor_id();
3382
3383 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3384 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3385 load_TR_desc();
3386}
3387
3388static void pre_svm_run(struct vcpu_svm *svm)
3389{
3390 int cpu = raw_smp_processor_id();
3391
3392 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3393
3394 /* FIXME: handle wraparound of asid_generation */
3395 if (svm->asid_generation != sd->asid_generation)
3396 new_asid(svm, sd);
3397}
3398
3399static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3400{
3401 struct vcpu_svm *svm = to_svm(vcpu);
3402
3403 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3404 vcpu->arch.hflags |= HF_NMI_MASK;
3405 set_intercept(svm, INTERCEPT_IRET);
3406 ++vcpu->stat.nmi_injections;
3407}
3408
3409static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3410{
3411 struct vmcb_control_area *control;
3412
3413 control = &svm->vmcb->control;
3414 control->int_vector = irq;
3415 control->int_ctl &= ~V_INTR_PRIO_MASK;
3416 control->int_ctl |= V_IRQ_MASK |
3417 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3418 mark_dirty(svm->vmcb, VMCB_INTR);
3419}
3420
3421static void svm_set_irq(struct kvm_vcpu *vcpu)
3422{
3423 struct vcpu_svm *svm = to_svm(vcpu);
3424
3425 BUG_ON(!(gif_set(svm)));
3426
3427 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3428 ++vcpu->stat.irq_injections;
3429
3430 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3431 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3432}
3433
3434static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3435{
3436 struct vcpu_svm *svm = to_svm(vcpu);
3437
3438 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3439 return;
3440
3441 if (irr == -1)
3442 return;
3443
3444 if (tpr >= irr)
3445 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3446}
3447
3448static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3449{
3450 struct vcpu_svm *svm = to_svm(vcpu);
3451 struct vmcb *vmcb = svm->vmcb;
3452 int ret;
3453 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3454 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3455 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3456
3457 return ret;
3458}
3459
3460static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3461{
3462 struct vcpu_svm *svm = to_svm(vcpu);
3463
3464 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3465}
3466
3467static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3468{
3469 struct vcpu_svm *svm = to_svm(vcpu);
3470
3471 if (masked) {
3472 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3473 set_intercept(svm, INTERCEPT_IRET);
3474 } else {
3475 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3476 clr_intercept(svm, INTERCEPT_IRET);
3477 }
3478}
3479
3480static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3481{
3482 struct vcpu_svm *svm = to_svm(vcpu);
3483 struct vmcb *vmcb = svm->vmcb;
3484 int ret;
3485
3486 if (!gif_set(svm) ||
3487 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3488 return 0;
3489
3490 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3491
3492 if (is_guest_mode(vcpu))
3493 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3494
3495 return ret;
3496}
3497
3498static void enable_irq_window(struct kvm_vcpu *vcpu)
3499{
3500 struct vcpu_svm *svm = to_svm(vcpu);
3501
3502 /*
3503 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3504 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3505 * get that intercept, this function will be called again though and
3506 * we'll get the vintr intercept.
3507 */
3508 if (gif_set(svm) && nested_svm_intr(svm)) {
3509 svm_set_vintr(svm);
3510 svm_inject_irq(svm, 0x0);
3511 }
3512}
3513
3514static void enable_nmi_window(struct kvm_vcpu *vcpu)
3515{
3516 struct vcpu_svm *svm = to_svm(vcpu);
3517
3518 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3519 == HF_NMI_MASK)
3520 return; /* IRET will cause a vm exit */
3521
3522 /*
3523 * Something prevents NMI from been injected. Single step over possible
3524 * problem (IRET or exception injection or interrupt shadow)
3525 */
3526 svm->nmi_singlestep = true;
3527 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3528 update_db_intercept(vcpu);
3529}
3530
3531static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3532{
3533 return 0;
3534}
3535
3536static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3537{
3538 struct vcpu_svm *svm = to_svm(vcpu);
3539
3540 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3541 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3542 else
3543 svm->asid_generation--;
3544}
3545
3546static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3547{
3548}
3549
3550static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3551{
3552 struct vcpu_svm *svm = to_svm(vcpu);
3553
3554 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3555 return;
3556
3557 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3558 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3559 kvm_set_cr8(vcpu, cr8);
3560 }
3561}
3562
3563static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3564{
3565 struct vcpu_svm *svm = to_svm(vcpu);
3566 u64 cr8;
3567
3568 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3569 return;
3570
3571 cr8 = kvm_get_cr8(vcpu);
3572 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3573 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3574}
3575
3576static void svm_complete_interrupts(struct vcpu_svm *svm)
3577{
3578 u8 vector;
3579 int type;
3580 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3581 unsigned int3_injected = svm->int3_injected;
3582
3583 svm->int3_injected = 0;
3584
3585 /*
3586 * If we've made progress since setting HF_IRET_MASK, we've
3587 * executed an IRET and can allow NMI injection.
3588 */
3589 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3590 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3591 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3592 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3593 }
3594
3595 svm->vcpu.arch.nmi_injected = false;
3596 kvm_clear_exception_queue(&svm->vcpu);
3597 kvm_clear_interrupt_queue(&svm->vcpu);
3598
3599 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3600 return;
3601
3602 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3603
3604 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3605 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3606
3607 switch (type) {
3608 case SVM_EXITINTINFO_TYPE_NMI:
3609 svm->vcpu.arch.nmi_injected = true;
3610 break;
3611 case SVM_EXITINTINFO_TYPE_EXEPT:
3612 /*
3613 * In case of software exceptions, do not reinject the vector,
3614 * but re-execute the instruction instead. Rewind RIP first
3615 * if we emulated INT3 before.
3616 */
3617 if (kvm_exception_is_soft(vector)) {
3618 if (vector == BP_VECTOR && int3_injected &&
3619 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3620 kvm_rip_write(&svm->vcpu,
3621 kvm_rip_read(&svm->vcpu) -
3622 int3_injected);
3623 break;
3624 }
3625 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3626 u32 err = svm->vmcb->control.exit_int_info_err;
3627 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3628
3629 } else
3630 kvm_requeue_exception(&svm->vcpu, vector);
3631 break;
3632 case SVM_EXITINTINFO_TYPE_INTR:
3633 kvm_queue_interrupt(&svm->vcpu, vector, false);
3634 break;
3635 default:
3636 break;
3637 }
3638}
3639
3640static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3641{
3642 struct vcpu_svm *svm = to_svm(vcpu);
3643 struct vmcb_control_area *control = &svm->vmcb->control;
3644
3645 control->exit_int_info = control->event_inj;
3646 control->exit_int_info_err = control->event_inj_err;
3647 control->event_inj = 0;
3648 svm_complete_interrupts(svm);
3649}
3650
3651#ifdef CONFIG_X86_64
3652#define R "r"
3653#else
3654#define R "e"
3655#endif
3656
3657static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3658{
3659 struct vcpu_svm *svm = to_svm(vcpu);
3660
3661 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3662 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3663 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3664
3665 /*
3666 * A vmexit emulation is required before the vcpu can be executed
3667 * again.
3668 */
3669 if (unlikely(svm->nested.exit_required))
3670 return;
3671
3672 pre_svm_run(svm);
3673
3674 sync_lapic_to_cr8(vcpu);
3675
3676 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3677
3678 clgi();
3679
3680 local_irq_enable();
3681
3682 asm volatile (
3683 "push %%"R"bp; \n\t"
3684 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3685 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3686 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3687 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3688 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3689 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3690#ifdef CONFIG_X86_64
3691 "mov %c[r8](%[svm]), %%r8 \n\t"
3692 "mov %c[r9](%[svm]), %%r9 \n\t"
3693 "mov %c[r10](%[svm]), %%r10 \n\t"
3694 "mov %c[r11](%[svm]), %%r11 \n\t"
3695 "mov %c[r12](%[svm]), %%r12 \n\t"
3696 "mov %c[r13](%[svm]), %%r13 \n\t"
3697 "mov %c[r14](%[svm]), %%r14 \n\t"
3698 "mov %c[r15](%[svm]), %%r15 \n\t"
3699#endif
3700
3701 /* Enter guest mode */
3702 "push %%"R"ax \n\t"
3703 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3704 __ex(SVM_VMLOAD) "\n\t"
3705 __ex(SVM_VMRUN) "\n\t"
3706 __ex(SVM_VMSAVE) "\n\t"
3707 "pop %%"R"ax \n\t"
3708
3709 /* Save guest registers, load host registers */
3710 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3711 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3712 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3713 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3714 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3715 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3716#ifdef CONFIG_X86_64
3717 "mov %%r8, %c[r8](%[svm]) \n\t"
3718 "mov %%r9, %c[r9](%[svm]) \n\t"
3719 "mov %%r10, %c[r10](%[svm]) \n\t"
3720 "mov %%r11, %c[r11](%[svm]) \n\t"
3721 "mov %%r12, %c[r12](%[svm]) \n\t"
3722 "mov %%r13, %c[r13](%[svm]) \n\t"
3723 "mov %%r14, %c[r14](%[svm]) \n\t"
3724 "mov %%r15, %c[r15](%[svm]) \n\t"
3725#endif
3726 "pop %%"R"bp"
3727 :
3728 : [svm]"a"(svm),
3729 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3730 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3731 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3732 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3733 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3734 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3735 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3736#ifdef CONFIG_X86_64
3737 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3738 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3739 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3740 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3741 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3742 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3743 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3744 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3745#endif
3746 : "cc", "memory"
3747 , R"bx", R"cx", R"dx", R"si", R"di"
3748#ifdef CONFIG_X86_64
3749 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3750#endif
3751 );
3752
3753#ifdef CONFIG_X86_64
3754 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3755#else
3756 loadsegment(fs, svm->host.fs);
3757#ifndef CONFIG_X86_32_LAZY_GS
3758 loadsegment(gs, svm->host.gs);
3759#endif
3760#endif
3761
3762 reload_tss(vcpu);
3763
3764 local_irq_disable();
3765
3766 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3767 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3768 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3769 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3770
3771 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3772 kvm_before_handle_nmi(&svm->vcpu);
3773
3774 stgi();
3775
3776 /* Any pending NMI will happen here */
3777
3778 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3779 kvm_after_handle_nmi(&svm->vcpu);
3780
3781 sync_cr8_to_lapic(vcpu);
3782
3783 svm->next_rip = 0;
3784
3785 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3786
3787 /* if exit due to PF check for async PF */
3788 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3789 svm->apf_reason = kvm_read_and_reset_pf_reason();
3790
3791 if (npt_enabled) {
3792 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3793 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3794 }
3795
3796 /*
3797 * We need to handle MC intercepts here before the vcpu has a chance to
3798 * change the physical cpu
3799 */
3800 if (unlikely(svm->vmcb->control.exit_code ==
3801 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3802 svm_handle_mce(svm);
3803
3804 mark_all_clean(svm->vmcb);
3805}
3806
3807#undef R
3808
3809static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3810{
3811 struct vcpu_svm *svm = to_svm(vcpu);
3812
3813 svm->vmcb->save.cr3 = root;
3814 mark_dirty(svm->vmcb, VMCB_CR);
3815 svm_flush_tlb(vcpu);
3816}
3817
3818static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3819{
3820 struct vcpu_svm *svm = to_svm(vcpu);
3821
3822 svm->vmcb->control.nested_cr3 = root;
3823 mark_dirty(svm->vmcb, VMCB_NPT);
3824
3825 /* Also sync guest cr3 here in case we live migrate */
3826 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3827 mark_dirty(svm->vmcb, VMCB_CR);
3828
3829 svm_flush_tlb(vcpu);
3830}
3831
3832static int is_disabled(void)
3833{
3834 u64 vm_cr;
3835
3836 rdmsrl(MSR_VM_CR, vm_cr);
3837 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3838 return 1;
3839
3840 return 0;
3841}
3842
3843static void
3844svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3845{
3846 /*
3847 * Patch in the VMMCALL instruction:
3848 */
3849 hypercall[0] = 0x0f;
3850 hypercall[1] = 0x01;
3851 hypercall[2] = 0xd9;
3852}
3853
3854static void svm_check_processor_compat(void *rtn)
3855{
3856 *(int *)rtn = 0;
3857}
3858
3859static bool svm_cpu_has_accelerated_tpr(void)
3860{
3861 return false;
3862}
3863
3864static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3865{
3866 return 0;
3867}
3868
3869static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3870{
3871}
3872
3873static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3874{
3875 switch (func) {
3876 case 0x80000001:
3877 if (nested)
3878 entry->ecx |= (1 << 2); /* Set SVM bit */
3879 break;
3880 case 0x8000000A:
3881 entry->eax = 1; /* SVM revision 1 */
3882 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3883 ASID emulation to nested SVM */
3884 entry->ecx = 0; /* Reserved */
3885 entry->edx = 0; /* Per default do not support any
3886 additional features */
3887
3888 /* Support next_rip if host supports it */
3889 if (boot_cpu_has(X86_FEATURE_NRIPS))
3890 entry->edx |= SVM_FEATURE_NRIP;
3891
3892 /* Support NPT for the guest if enabled */
3893 if (npt_enabled)
3894 entry->edx |= SVM_FEATURE_NPT;
3895
3896 break;
3897 }
3898}
3899
3900static const struct trace_print_flags svm_exit_reasons_str[] = {
3901 { SVM_EXIT_READ_CR0, "read_cr0" },
3902 { SVM_EXIT_READ_CR3, "read_cr3" },
3903 { SVM_EXIT_READ_CR4, "read_cr4" },
3904 { SVM_EXIT_READ_CR8, "read_cr8" },
3905 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3906 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3907 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3908 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3909 { SVM_EXIT_READ_DR0, "read_dr0" },
3910 { SVM_EXIT_READ_DR1, "read_dr1" },
3911 { SVM_EXIT_READ_DR2, "read_dr2" },
3912 { SVM_EXIT_READ_DR3, "read_dr3" },
3913 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3914 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3915 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3916 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3917 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3918 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3919 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3920 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3921 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3922 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3923 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3924 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3925 { SVM_EXIT_INTR, "interrupt" },
3926 { SVM_EXIT_NMI, "nmi" },
3927 { SVM_EXIT_SMI, "smi" },
3928 { SVM_EXIT_INIT, "init" },
3929 { SVM_EXIT_VINTR, "vintr" },
3930 { SVM_EXIT_CPUID, "cpuid" },
3931 { SVM_EXIT_INVD, "invd" },
3932 { SVM_EXIT_HLT, "hlt" },
3933 { SVM_EXIT_INVLPG, "invlpg" },
3934 { SVM_EXIT_INVLPGA, "invlpga" },
3935 { SVM_EXIT_IOIO, "io" },
3936 { SVM_EXIT_MSR, "msr" },
3937 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3938 { SVM_EXIT_SHUTDOWN, "shutdown" },
3939 { SVM_EXIT_VMRUN, "vmrun" },
3940 { SVM_EXIT_VMMCALL, "hypercall" },
3941 { SVM_EXIT_VMLOAD, "vmload" },
3942 { SVM_EXIT_VMSAVE, "vmsave" },
3943 { SVM_EXIT_STGI, "stgi" },
3944 { SVM_EXIT_CLGI, "clgi" },
3945 { SVM_EXIT_SKINIT, "skinit" },
3946 { SVM_EXIT_WBINVD, "wbinvd" },
3947 { SVM_EXIT_MONITOR, "monitor" },
3948 { SVM_EXIT_MWAIT, "mwait" },
3949 { SVM_EXIT_XSETBV, "xsetbv" },
3950 { SVM_EXIT_NPF, "npf" },
3951 { -1, NULL }
3952};
3953
3954static int svm_get_lpage_level(void)
3955{
3956 return PT_PDPE_LEVEL;
3957}
3958
3959static bool svm_rdtscp_supported(void)
3960{
3961 return false;
3962}
3963
3964static bool svm_has_wbinvd_exit(void)
3965{
3966 return true;
3967}
3968
3969static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3970{
3971 struct vcpu_svm *svm = to_svm(vcpu);
3972
3973 set_exception_intercept(svm, NM_VECTOR);
3974 update_cr0_intercept(svm);
3975}
3976
3977#define PRE_EX(exit) { .exit_code = (exit), \
3978 .stage = X86_ICPT_PRE_EXCEPT, }
3979#define POST_EX(exit) { .exit_code = (exit), \
3980 .stage = X86_ICPT_POST_EXCEPT, }
3981#define POST_MEM(exit) { .exit_code = (exit), \
3982 .stage = X86_ICPT_POST_MEMACCESS, }
3983
3984static struct __x86_intercept {
3985 u32 exit_code;
3986 enum x86_intercept_stage stage;
3987} x86_intercept_map[] = {
3988 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3989 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3990 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3991 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3992 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3993 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3994 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
3995 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3996 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3997 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3998 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3999 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4000 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4001 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4002 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4003 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4004 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4005 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4006 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4007 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4008 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4009 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4010 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4011 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4012 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4013 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4014 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4015 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4016 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4017 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4018 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4019 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4020 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4021 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4022 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4023 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4024 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4025 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4026 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4027 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4028 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4029 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4030 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4031 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4032 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4033 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4034};
4035
4036#undef PRE_EX
4037#undef POST_EX
4038#undef POST_MEM
4039
4040static int svm_check_intercept(struct kvm_vcpu *vcpu,
4041 struct x86_instruction_info *info,
4042 enum x86_intercept_stage stage)
4043{
4044 struct vcpu_svm *svm = to_svm(vcpu);
4045 int vmexit, ret = X86EMUL_CONTINUE;
4046 struct __x86_intercept icpt_info;
4047 struct vmcb *vmcb = svm->vmcb;
4048
4049 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4050 goto out;
4051
4052 icpt_info = x86_intercept_map[info->intercept];
4053
4054 if (stage != icpt_info.stage)
4055 goto out;
4056
4057 switch (icpt_info.exit_code) {
4058 case SVM_EXIT_READ_CR0:
4059 if (info->intercept == x86_intercept_cr_read)
4060 icpt_info.exit_code += info->modrm_reg;
4061 break;
4062 case SVM_EXIT_WRITE_CR0: {
4063 unsigned long cr0, val;
4064 u64 intercept;
4065
4066 if (info->intercept == x86_intercept_cr_write)
4067 icpt_info.exit_code += info->modrm_reg;
4068
4069 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4070 break;
4071
4072 intercept = svm->nested.intercept;
4073
4074 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4075 break;
4076
4077 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4078 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4079
4080 if (info->intercept == x86_intercept_lmsw) {
4081 cr0 &= 0xfUL;
4082 val &= 0xfUL;
4083 /* lmsw can't clear PE - catch this here */
4084 if (cr0 & X86_CR0_PE)
4085 val |= X86_CR0_PE;
4086 }
4087
4088 if (cr0 ^ val)
4089 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4090
4091 break;
4092 }
4093 case SVM_EXIT_READ_DR0:
4094 case SVM_EXIT_WRITE_DR0:
4095 icpt_info.exit_code += info->modrm_reg;
4096 break;
4097 case SVM_EXIT_MSR:
4098 if (info->intercept == x86_intercept_wrmsr)
4099 vmcb->control.exit_info_1 = 1;
4100 else
4101 vmcb->control.exit_info_1 = 0;
4102 break;
4103 case SVM_EXIT_PAUSE:
4104 /*
4105 * We get this for NOP only, but pause
4106 * is rep not, check this here
4107 */
4108 if (info->rep_prefix != REPE_PREFIX)
4109 goto out;
4110 case SVM_EXIT_IOIO: {
4111 u64 exit_info;
4112 u32 bytes;
4113
4114 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4115
4116 if (info->intercept == x86_intercept_in ||
4117 info->intercept == x86_intercept_ins) {
4118 exit_info |= SVM_IOIO_TYPE_MASK;
4119 bytes = info->src_bytes;
4120 } else {
4121 bytes = info->dst_bytes;
4122 }
4123
4124 if (info->intercept == x86_intercept_outs ||
4125 info->intercept == x86_intercept_ins)
4126 exit_info |= SVM_IOIO_STR_MASK;
4127
4128 if (info->rep_prefix)
4129 exit_info |= SVM_IOIO_REP_MASK;
4130
4131 bytes = min(bytes, 4u);
4132
4133 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4134
4135 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4136
4137 vmcb->control.exit_info_1 = exit_info;
4138 vmcb->control.exit_info_2 = info->next_rip;
4139
4140 break;
4141 }
4142 default:
4143 break;
4144 }
4145
4146 vmcb->control.next_rip = info->next_rip;
4147 vmcb->control.exit_code = icpt_info.exit_code;
4148 vmexit = nested_svm_exit_handled(svm);
4149
4150 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4151 : X86EMUL_CONTINUE;
4152
4153out:
4154 return ret;
4155}
4156
4157static struct kvm_x86_ops svm_x86_ops = {
4158 .cpu_has_kvm_support = has_svm,
4159 .disabled_by_bios = is_disabled,
4160 .hardware_setup = svm_hardware_setup,
4161 .hardware_unsetup = svm_hardware_unsetup,
4162 .check_processor_compatibility = svm_check_processor_compat,
4163 .hardware_enable = svm_hardware_enable,
4164 .hardware_disable = svm_hardware_disable,
4165 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4166
4167 .vcpu_create = svm_create_vcpu,
4168 .vcpu_free = svm_free_vcpu,
4169 .vcpu_reset = svm_vcpu_reset,
4170
4171 .prepare_guest_switch = svm_prepare_guest_switch,
4172 .vcpu_load = svm_vcpu_load,
4173 .vcpu_put = svm_vcpu_put,
4174
4175 .set_guest_debug = svm_guest_debug,
4176 .get_msr = svm_get_msr,
4177 .set_msr = svm_set_msr,
4178 .get_segment_base = svm_get_segment_base,
4179 .get_segment = svm_get_segment,
4180 .set_segment = svm_set_segment,
4181 .get_cpl = svm_get_cpl,
4182 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4183 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4184 .decache_cr3 = svm_decache_cr3,
4185 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4186 .set_cr0 = svm_set_cr0,
4187 .set_cr3 = svm_set_cr3,
4188 .set_cr4 = svm_set_cr4,
4189 .set_efer = svm_set_efer,
4190 .get_idt = svm_get_idt,
4191 .set_idt = svm_set_idt,
4192 .get_gdt = svm_get_gdt,
4193 .set_gdt = svm_set_gdt,
4194 .set_dr7 = svm_set_dr7,
4195 .cache_reg = svm_cache_reg,
4196 .get_rflags = svm_get_rflags,
4197 .set_rflags = svm_set_rflags,
4198 .fpu_activate = svm_fpu_activate,
4199 .fpu_deactivate = svm_fpu_deactivate,
4200
4201 .tlb_flush = svm_flush_tlb,
4202
4203 .run = svm_vcpu_run,
4204 .handle_exit = handle_exit,
4205 .skip_emulated_instruction = skip_emulated_instruction,
4206 .set_interrupt_shadow = svm_set_interrupt_shadow,
4207 .get_interrupt_shadow = svm_get_interrupt_shadow,
4208 .patch_hypercall = svm_patch_hypercall,
4209 .set_irq = svm_set_irq,
4210 .set_nmi = svm_inject_nmi,
4211 .queue_exception = svm_queue_exception,
4212 .cancel_injection = svm_cancel_injection,
4213 .interrupt_allowed = svm_interrupt_allowed,
4214 .nmi_allowed = svm_nmi_allowed,
4215 .get_nmi_mask = svm_get_nmi_mask,
4216 .set_nmi_mask = svm_set_nmi_mask,
4217 .enable_nmi_window = enable_nmi_window,
4218 .enable_irq_window = enable_irq_window,
4219 .update_cr8_intercept = update_cr8_intercept,
4220
4221 .set_tss_addr = svm_set_tss_addr,
4222 .get_tdp_level = get_npt_level,
4223 .get_mt_mask = svm_get_mt_mask,
4224
4225 .get_exit_info = svm_get_exit_info,
4226 .exit_reasons_str = svm_exit_reasons_str,
4227
4228 .get_lpage_level = svm_get_lpage_level,
4229
4230 .cpuid_update = svm_cpuid_update,
4231
4232 .rdtscp_supported = svm_rdtscp_supported,
4233
4234 .set_supported_cpuid = svm_set_supported_cpuid,
4235
4236 .has_wbinvd_exit = svm_has_wbinvd_exit,
4237
4238 .set_tsc_khz = svm_set_tsc_khz,
4239 .write_tsc_offset = svm_write_tsc_offset,
4240 .adjust_tsc_offset = svm_adjust_tsc_offset,
4241 .compute_tsc_offset = svm_compute_tsc_offset,
4242
4243 .set_tdp_cr3 = set_tdp_cr3,
4244
4245 .check_intercept = svm_check_intercept,
4246};
4247
4248static int __init svm_init(void)
4249{
4250 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4251 __alignof__(struct vcpu_svm), THIS_MODULE);
4252}
4253
4254static void __exit svm_exit(void)
4255{
4256 kvm_exit();
4257}
4258
4259module_init(svm_init)
4260module_exit(svm_exit)