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1config ARM64
2 def_bool y
3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_HAS_SG_CHAIN
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_SUPPORTS_ATOMIC_RMW
14 select ARCH_WANT_OPTIONAL_GPIOLIB
15 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
16 select ARCH_WANT_FRAME_POINTERS
17 select ARCH_HAS_UBSAN_SANITIZE_ALL
18 select ARM_AMBA
19 select ARM_ARCH_TIMER
20 select ARM_GIC
21 select AUDIT_ARCH_COMPAT_GENERIC
22 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3
24 select ARM_GIC_V3_ITS if PCI_MSI
25 select ARM_PSCI_FW
26 select BUILDTIME_EXTABLE_SORT
27 select CLONE_BACKWARDS
28 select COMMON_CLK
29 select CPU_PM if (SUSPEND || CPU_IDLE)
30 select DCACHE_WORD_ACCESS
31 select EDAC_SUPPORT
32 select FRAME_POINTER
33 select GENERIC_ALLOCATOR
34 select GENERIC_CLOCKEVENTS
35 select GENERIC_CLOCKEVENTS_BROADCAST
36 select GENERIC_CPU_AUTOPROBE
37 select GENERIC_EARLY_IOREMAP
38 select GENERIC_IDLE_POLL_SETUP
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_SHOW_LEVEL
42 select GENERIC_PCI_IOMAP
43 select GENERIC_SCHED_CLOCK
44 select GENERIC_SMP_IDLE_THREAD
45 select GENERIC_STRNCPY_FROM_USER
46 select GENERIC_STRNLEN_USER
47 select GENERIC_TIME_VSYSCALL
48 select HANDLE_DOMAIN_IRQ
49 select HARDIRQS_SW_RESEND
50 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
51 select HAVE_ARCH_AUDITSYSCALL
52 select HAVE_ARCH_BITREVERSE
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
56 select HAVE_ARCH_KGDB
57 select HAVE_ARCH_MMAP_RND_BITS
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
59 select HAVE_ARCH_SECCOMP_FILTER
60 select HAVE_ARCH_TRACEHOOK
61 select HAVE_BPF_JIT
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_CC_STACKPROTECTOR
64 select HAVE_CMPXCHG_DOUBLE
65 select HAVE_CMPXCHG_LOCAL
66 select HAVE_DEBUG_BUGVERBOSE
67 select HAVE_DEBUG_KMEMLEAK
68 select HAVE_DMA_API_DEBUG
69 select HAVE_DMA_CONTIGUOUS
70 select HAVE_DYNAMIC_FTRACE
71 select HAVE_EFFICIENT_UNALIGNED_ACCESS
72 select HAVE_FTRACE_MCOUNT_RECORD
73 select HAVE_FUNCTION_TRACER
74 select HAVE_FUNCTION_GRAPH_TRACER
75 select HAVE_GENERIC_DMA_COHERENT
76 select HAVE_HW_BREAKPOINT if PERF_EVENTS
77 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_MEMBLOCK
79 select HAVE_PATA_PLATFORM
80 select HAVE_PERF_EVENTS
81 select HAVE_PERF_REGS
82 select HAVE_PERF_USER_STACK_DUMP
83 select HAVE_RCU_TABLE_FREE
84 select HAVE_SYSCALL_TRACEPOINTS
85 select IOMMU_DMA if IOMMU_SUPPORT
86 select IRQ_DOMAIN
87 select IRQ_FORCED_THREADING
88 select MODULES_USE_ELF_RELA
89 select NO_BOOTMEM
90 select OF
91 select OF_EARLY_FLATTREE
92 select OF_RESERVED_MEM
93 select PERF_USE_VMALLOC
94 select POWER_RESET
95 select POWER_SUPPLY
96 select RTC_LIB
97 select SPARSE_IRQ
98 select SYSCTL_EXCEPTION_TRACE
99 select HAVE_CONTEXT_TRACKING
100 select HAVE_ARM_SMCCC
101 help
102 ARM 64-bit (AArch64) Linux support.
103
104config 64BIT
105 def_bool y
106
107config ARCH_PHYS_ADDR_T_64BIT
108 def_bool y
109
110config MMU
111 def_bool y
112
113config ARCH_MMAP_RND_BITS_MIN
114 default 14 if ARM64_64K_PAGES
115 default 16 if ARM64_16K_PAGES
116 default 18
117
118# max bits determined by the following formula:
119# VA_BITS - PAGE_SHIFT - 3
120config ARCH_MMAP_RND_BITS_MAX
121 default 19 if ARM64_VA_BITS=36
122 default 24 if ARM64_VA_BITS=39
123 default 27 if ARM64_VA_BITS=42
124 default 30 if ARM64_VA_BITS=47
125 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
126 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
127 default 33 if ARM64_VA_BITS=48
128 default 14 if ARM64_64K_PAGES
129 default 16 if ARM64_16K_PAGES
130 default 18
131
132config ARCH_MMAP_RND_COMPAT_BITS_MIN
133 default 7 if ARM64_64K_PAGES
134 default 9 if ARM64_16K_PAGES
135 default 11
136
137config ARCH_MMAP_RND_COMPAT_BITS_MAX
138 default 16
139
140config NO_IOPORT_MAP
141 def_bool y if !PCI
142
143config STACKTRACE_SUPPORT
144 def_bool y
145
146config ILLEGAL_POINTER_VALUE
147 hex
148 default 0xdead000000000000
149
150config LOCKDEP_SUPPORT
151 def_bool y
152
153config TRACE_IRQFLAGS_SUPPORT
154 def_bool y
155
156config RWSEM_XCHGADD_ALGORITHM
157 def_bool y
158
159config GENERIC_BUG
160 def_bool y
161 depends on BUG
162
163config GENERIC_BUG_RELATIVE_POINTERS
164 def_bool y
165 depends on GENERIC_BUG
166
167config GENERIC_HWEIGHT
168 def_bool y
169
170config GENERIC_CSUM
171 def_bool y
172
173config GENERIC_CALIBRATE_DELAY
174 def_bool y
175
176config ZONE_DMA
177 def_bool y
178
179config HAVE_GENERIC_RCU_GUP
180 def_bool y
181
182config ARCH_DMA_ADDR_T_64BIT
183 def_bool y
184
185config NEED_DMA_MAP_STATE
186 def_bool y
187
188config NEED_SG_DMA_LENGTH
189 def_bool y
190
191config SMP
192 def_bool y
193
194config SWIOTLB
195 def_bool y
196
197config IOMMU_HELPER
198 def_bool SWIOTLB
199
200config KERNEL_MODE_NEON
201 def_bool y
202
203config FIX_EARLYCON_MEM
204 def_bool y
205
206config PGTABLE_LEVELS
207 int
208 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
209 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
210 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
211 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
212 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
213 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
214
215source "init/Kconfig"
216
217source "kernel/Kconfig.freezer"
218
219source "arch/arm64/Kconfig.platforms"
220
221menu "Bus support"
222
223config PCI
224 bool "PCI support"
225 help
226 This feature enables support for PCI bus system. If you say Y
227 here, the kernel will include drivers and infrastructure code
228 to support PCI bus devices.
229
230config PCI_DOMAINS
231 def_bool PCI
232
233config PCI_DOMAINS_GENERIC
234 def_bool PCI
235
236config PCI_SYSCALL
237 def_bool PCI
238
239source "drivers/pci/Kconfig"
240
241endmenu
242
243menu "Kernel Features"
244
245menu "ARM errata workarounds via the alternatives framework"
246
247config ARM64_ERRATUM_826319
248 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
249 default y
250 help
251 This option adds an alternative code sequence to work around ARM
252 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
253 AXI master interface and an L2 cache.
254
255 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
256 and is unable to accept a certain write via this interface, it will
257 not progress on read data presented on the read data channel and the
258 system can deadlock.
259
260 The workaround promotes data cache clean instructions to
261 data cache clean-and-invalidate.
262 Please note that this does not necessarily enable the workaround,
263 as it depends on the alternative framework, which will only patch
264 the kernel if an affected CPU is detected.
265
266 If unsure, say Y.
267
268config ARM64_ERRATUM_827319
269 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
270 default y
271 help
272 This option adds an alternative code sequence to work around ARM
273 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
274 master interface and an L2 cache.
275
276 Under certain conditions this erratum can cause a clean line eviction
277 to occur at the same time as another transaction to the same address
278 on the AMBA 5 CHI interface, which can cause data corruption if the
279 interconnect reorders the two transactions.
280
281 The workaround promotes data cache clean instructions to
282 data cache clean-and-invalidate.
283 Please note that this does not necessarily enable the workaround,
284 as it depends on the alternative framework, which will only patch
285 the kernel if an affected CPU is detected.
286
287 If unsure, say Y.
288
289config ARM64_ERRATUM_824069
290 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
291 default y
292 help
293 This option adds an alternative code sequence to work around ARM
294 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
295 to a coherent interconnect.
296
297 If a Cortex-A53 processor is executing a store or prefetch for
298 write instruction at the same time as a processor in another
299 cluster is executing a cache maintenance operation to the same
300 address, then this erratum might cause a clean cache line to be
301 incorrectly marked as dirty.
302
303 The workaround promotes data cache clean instructions to
304 data cache clean-and-invalidate.
305 Please note that this option does not necessarily enable the
306 workaround, as it depends on the alternative framework, which will
307 only patch the kernel if an affected CPU is detected.
308
309 If unsure, say Y.
310
311config ARM64_ERRATUM_819472
312 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
313 default y
314 help
315 This option adds an alternative code sequence to work around ARM
316 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
317 present when it is connected to a coherent interconnect.
318
319 If the processor is executing a load and store exclusive sequence at
320 the same time as a processor in another cluster is executing a cache
321 maintenance operation to the same address, then this erratum might
322 cause data corruption.
323
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this does not necessarily enable the workaround,
327 as it depends on the alternative framework, which will only patch
328 the kernel if an affected CPU is detected.
329
330 If unsure, say Y.
331
332config ARM64_ERRATUM_832075
333 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
334 default y
335 help
336 This option adds an alternative code sequence to work around ARM
337 erratum 832075 on Cortex-A57 parts up to r1p2.
338
339 Affected Cortex-A57 parts might deadlock when exclusive load/store
340 instructions to Write-Back memory are mixed with Device loads.
341
342 The workaround is to promote device loads to use Load-Acquire
343 semantics.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
347
348 If unsure, say Y.
349
350config ARM64_ERRATUM_834220
351 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
352 depends on KVM
353 default y
354 help
355 This option adds an alternative code sequence to work around ARM
356 erratum 834220 on Cortex-A57 parts up to r1p2.
357
358 Affected Cortex-A57 parts might report a Stage 2 translation
359 fault as the result of a Stage 1 fault for load crossing a
360 page boundary when there is a permission or device memory
361 alignment fault at Stage 1 and a translation fault at Stage 2.
362
363 The workaround is to verify that the Stage 1 translation
364 doesn't generate a fault before handling the Stage 2 fault.
365 Please note that this does not necessarily enable the workaround,
366 as it depends on the alternative framework, which will only patch
367 the kernel if an affected CPU is detected.
368
369 If unsure, say Y.
370
371config ARM64_ERRATUM_845719
372 bool "Cortex-A53: 845719: a load might read incorrect data"
373 depends on COMPAT
374 default y
375 help
376 This option adds an alternative code sequence to work around ARM
377 erratum 845719 on Cortex-A53 parts up to r0p4.
378
379 When running a compat (AArch32) userspace on an affected Cortex-A53
380 part, a load at EL0 from a virtual address that matches the bottom 32
381 bits of the virtual address used by a recent load at (AArch64) EL1
382 might return incorrect data.
383
384 The workaround is to write the contextidr_el1 register on exception
385 return to a 32-bit task.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
389
390 If unsure, say Y.
391
392config ARM64_ERRATUM_843419
393 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
394 depends on MODULES
395 default y
396 select ARM64_MODULE_CMODEL_LARGE
397 help
398 This option builds kernel modules using the large memory model in
399 order to avoid the use of the ADRP instruction, which can cause
400 a subsequent memory access to use an incorrect address on Cortex-A53
401 parts up to r0p4.
402
403 Note that the kernel itself must be linked with a version of ld
404 which fixes potentially affected ADRP instructions through the
405 use of veneers.
406
407 If unsure, say Y.
408
409config CAVIUM_ERRATUM_22375
410 bool "Cavium erratum 22375, 24313"
411 default y
412 help
413 Enable workaround for erratum 22375, 24313.
414
415 This implements two gicv3-its errata workarounds for ThunderX. Both
416 with small impact affecting only ITS table allocation.
417
418 erratum 22375: only alloc 8MB table size
419 erratum 24313: ignore memory access type
420
421 The fixes are in ITS initialization and basically ignore memory access
422 type and table size provided by the TYPER and BASER registers.
423
424 If unsure, say Y.
425
426config CAVIUM_ERRATUM_23154
427 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
428 default y
429 help
430 The gicv3 of ThunderX requires a modified version for
431 reading the IAR status to ensure data synchronization
432 (access to icc_iar1_el1 is not sync'ed before and after).
433
434 If unsure, say Y.
435
436config CAVIUM_ERRATUM_27456
437 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
438 default y
439 help
440 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
441 instructions may cause the icache to become corrupted if it
442 contains data for a non-current ASID. The fix is to
443 invalidate the icache when changing the mm context.
444
445 If unsure, say Y.
446
447endmenu
448
449
450choice
451 prompt "Page size"
452 default ARM64_4K_PAGES
453 help
454 Page size (translation granule) configuration.
455
456config ARM64_4K_PAGES
457 bool "4KB"
458 help
459 This feature enables 4KB pages support.
460
461config ARM64_16K_PAGES
462 bool "16KB"
463 help
464 The system will use 16KB pages support. AArch32 emulation
465 requires applications compiled with 16K (or a multiple of 16K)
466 aligned segments.
467
468config ARM64_64K_PAGES
469 bool "64KB"
470 help
471 This feature enables 64KB pages support (4KB by default)
472 allowing only two levels of page tables and faster TLB
473 look-up. AArch32 emulation requires applications compiled
474 with 64K aligned segments.
475
476endchoice
477
478choice
479 prompt "Virtual address space size"
480 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
481 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
482 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
483 help
484 Allows choosing one of multiple possible virtual address
485 space sizes. The level of translation table is determined by
486 a combination of page size and virtual address space size.
487
488config ARM64_VA_BITS_36
489 bool "36-bit" if EXPERT
490 depends on ARM64_16K_PAGES
491
492config ARM64_VA_BITS_39
493 bool "39-bit"
494 depends on ARM64_4K_PAGES
495
496config ARM64_VA_BITS_42
497 bool "42-bit"
498 depends on ARM64_64K_PAGES
499
500config ARM64_VA_BITS_47
501 bool "47-bit"
502 depends on ARM64_16K_PAGES
503
504config ARM64_VA_BITS_48
505 bool "48-bit"
506
507endchoice
508
509config ARM64_VA_BITS
510 int
511 default 36 if ARM64_VA_BITS_36
512 default 39 if ARM64_VA_BITS_39
513 default 42 if ARM64_VA_BITS_42
514 default 47 if ARM64_VA_BITS_47
515 default 48 if ARM64_VA_BITS_48
516
517config CPU_BIG_ENDIAN
518 bool "Build big-endian kernel"
519 help
520 Say Y if you plan on running a kernel in big-endian mode.
521
522config SCHED_MC
523 bool "Multi-core scheduler support"
524 help
525 Multi-core scheduler support improves the CPU scheduler's decision
526 making when dealing with multi-core CPU chips at a cost of slightly
527 increased overhead in some places. If unsure say N here.
528
529config SCHED_SMT
530 bool "SMT scheduler support"
531 help
532 Improves the CPU scheduler's decision making when dealing with
533 MultiThreading at a cost of slightly increased overhead in some
534 places. If unsure say N here.
535
536config NR_CPUS
537 int "Maximum number of CPUs (2-4096)"
538 range 2 4096
539 # These have to remain sorted largest to smallest
540 default "64"
541
542config HOTPLUG_CPU
543 bool "Support for hot-pluggable CPUs"
544 select GENERIC_IRQ_MIGRATION
545 help
546 Say Y here to experiment with turning CPUs off and on. CPUs
547 can be controlled through /sys/devices/system/cpu.
548
549source kernel/Kconfig.preempt
550source kernel/Kconfig.hz
551
552config ARCH_SUPPORTS_DEBUG_PAGEALLOC
553 def_bool y
554
555config ARCH_HAS_HOLES_MEMORYMODEL
556 def_bool y if SPARSEMEM
557
558config ARCH_SPARSEMEM_ENABLE
559 def_bool y
560 select SPARSEMEM_VMEMMAP_ENABLE
561
562config ARCH_SPARSEMEM_DEFAULT
563 def_bool ARCH_SPARSEMEM_ENABLE
564
565config ARCH_SELECT_MEMORY_MODEL
566 def_bool ARCH_SPARSEMEM_ENABLE
567
568config HAVE_ARCH_PFN_VALID
569 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
570
571config HW_PERF_EVENTS
572 def_bool y
573 depends on ARM_PMU
574
575config SYS_SUPPORTS_HUGETLBFS
576 def_bool y
577
578config ARCH_WANT_HUGE_PMD_SHARE
579 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
580
581config HAVE_ARCH_TRANSPARENT_HUGEPAGE
582 def_bool y
583
584config ARCH_HAS_CACHE_LINE_SIZE
585 def_bool y
586
587source "mm/Kconfig"
588
589config SECCOMP
590 bool "Enable seccomp to safely compute untrusted bytecode"
591 ---help---
592 This kernel feature is useful for number crunching applications
593 that may need to compute untrusted bytecode during their
594 execution. By using pipes or other transports made available to
595 the process as file descriptors supporting the read/write
596 syscalls, it's possible to isolate those applications in
597 their own address space using seccomp. Once seccomp is
598 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
599 and the task is only allowed to execute a few safe syscalls
600 defined by each seccomp mode.
601
602config PARAVIRT
603 bool "Enable paravirtualization code"
604 help
605 This changes the kernel so it can modify itself when it is run
606 under a hypervisor, potentially improving performance significantly
607 over full virtualization.
608
609config PARAVIRT_TIME_ACCOUNTING
610 bool "Paravirtual steal time accounting"
611 select PARAVIRT
612 default n
613 help
614 Select this option to enable fine granularity task steal time
615 accounting. Time spent executing other tasks in parallel with
616 the current vCPU is discounted from the vCPU power. To account for
617 that, there can be a small performance impact.
618
619 If in doubt, say N here.
620
621config XEN_DOM0
622 def_bool y
623 depends on XEN
624
625config XEN
626 bool "Xen guest support on ARM64"
627 depends on ARM64 && OF
628 select SWIOTLB_XEN
629 select PARAVIRT
630 help
631 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
632
633config FORCE_MAX_ZONEORDER
634 int
635 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
636 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
637 default "11"
638 help
639 The kernel memory allocator divides physically contiguous memory
640 blocks into "zones", where each zone is a power of two number of
641 pages. This option selects the largest power of two that the kernel
642 keeps in the memory allocator. If you need to allocate very large
643 blocks of physically contiguous memory, then you may need to
644 increase this value.
645
646 This config option is actually maximum order plus one. For example,
647 a value of 11 means that the largest free memory block is 2^10 pages.
648
649 We make sure that we can allocate upto a HugePage size for each configuration.
650 Hence we have :
651 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
652
653 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
654 4M allocations matching the default size used by generic code.
655
656menuconfig ARMV8_DEPRECATED
657 bool "Emulate deprecated/obsolete ARMv8 instructions"
658 depends on COMPAT
659 help
660 Legacy software support may require certain instructions
661 that have been deprecated or obsoleted in the architecture.
662
663 Enable this config to enable selective emulation of these
664 features.
665
666 If unsure, say Y
667
668if ARMV8_DEPRECATED
669
670config SWP_EMULATION
671 bool "Emulate SWP/SWPB instructions"
672 help
673 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
674 they are always undefined. Say Y here to enable software
675 emulation of these instructions for userspace using LDXR/STXR.
676
677 In some older versions of glibc [<=2.8] SWP is used during futex
678 trylock() operations with the assumption that the code will not
679 be preempted. This invalid assumption may be more likely to fail
680 with SWP emulation enabled, leading to deadlock of the user
681 application.
682
683 NOTE: when accessing uncached shared regions, LDXR/STXR rely
684 on an external transaction monitoring block called a global
685 monitor to maintain update atomicity. If your system does not
686 implement a global monitor, this option can cause programs that
687 perform SWP operations to uncached memory to deadlock.
688
689 If unsure, say Y
690
691config CP15_BARRIER_EMULATION
692 bool "Emulate CP15 Barrier instructions"
693 help
694 The CP15 barrier instructions - CP15ISB, CP15DSB, and
695 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
696 strongly recommended to use the ISB, DSB, and DMB
697 instructions instead.
698
699 Say Y here to enable software emulation of these
700 instructions for AArch32 userspace code. When this option is
701 enabled, CP15 barrier usage is traced which can help
702 identify software that needs updating.
703
704 If unsure, say Y
705
706config SETEND_EMULATION
707 bool "Emulate SETEND instruction"
708 help
709 The SETEND instruction alters the data-endianness of the
710 AArch32 EL0, and is deprecated in ARMv8.
711
712 Say Y here to enable software emulation of the instruction
713 for AArch32 userspace code.
714
715 Note: All the cpus on the system must have mixed endian support at EL0
716 for this feature to be enabled. If a new CPU - which doesn't support mixed
717 endian - is hotplugged in after this feature has been enabled, there could
718 be unexpected results in the applications.
719
720 If unsure, say Y
721endif
722
723menu "ARMv8.1 architectural features"
724
725config ARM64_HW_AFDBM
726 bool "Support for hardware updates of the Access and Dirty page flags"
727 default y
728 help
729 The ARMv8.1 architecture extensions introduce support for
730 hardware updates of the access and dirty information in page
731 table entries. When enabled in TCR_EL1 (HA and HD bits) on
732 capable processors, accesses to pages with PTE_AF cleared will
733 set this bit instead of raising an access flag fault.
734 Similarly, writes to read-only pages with the DBM bit set will
735 clear the read-only bit (AP[2]) instead of raising a
736 permission fault.
737
738 Kernels built with this configuration option enabled continue
739 to work on pre-ARMv8.1 hardware and the performance impact is
740 minimal. If unsure, say Y.
741
742config ARM64_PAN
743 bool "Enable support for Privileged Access Never (PAN)"
744 default y
745 help
746 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
747 prevents the kernel or hypervisor from accessing user-space (EL0)
748 memory directly.
749
750 Choosing this option will cause any unprotected (not using
751 copy_to_user et al) memory access to fail with a permission fault.
752
753 The feature is detected at runtime, and will remain as a 'nop'
754 instruction if the cpu does not implement the feature.
755
756config ARM64_LSE_ATOMICS
757 bool "Atomic instructions"
758 help
759 As part of the Large System Extensions, ARMv8.1 introduces new
760 atomic instructions that are designed specifically to scale in
761 very large systems.
762
763 Say Y here to make use of these instructions for the in-kernel
764 atomic routines. This incurs a small overhead on CPUs that do
765 not support these instructions and requires the kernel to be
766 built with binutils >= 2.25.
767
768config ARM64_VHE
769 bool "Enable support for Virtualization Host Extensions (VHE)"
770 default y
771 help
772 Virtualization Host Extensions (VHE) allow the kernel to run
773 directly at EL2 (instead of EL1) on processors that support
774 it. This leads to better performance for KVM, as they reduce
775 the cost of the world switch.
776
777 Selecting this option allows the VHE feature to be detected
778 at runtime, and does not affect processors that do not
779 implement this feature.
780
781endmenu
782
783menu "ARMv8.2 architectural features"
784
785config ARM64_UAO
786 bool "Enable support for User Access Override (UAO)"
787 default y
788 help
789 User Access Override (UAO; part of the ARMv8.2 Extensions)
790 causes the 'unprivileged' variant of the load/store instructions to
791 be overriden to be privileged.
792
793 This option changes get_user() and friends to use the 'unprivileged'
794 variant of the load/store instructions. This ensures that user-space
795 really did have access to the supplied memory. When addr_limit is
796 set to kernel memory the UAO bit will be set, allowing privileged
797 access to kernel memory.
798
799 Choosing this option will cause copy_to_user() et al to use user-space
800 memory permissions.
801
802 The feature is detected at runtime, the kernel will use the
803 regular load/store instructions if the cpu does not implement the
804 feature.
805
806endmenu
807
808config ARM64_MODULE_CMODEL_LARGE
809 bool
810
811config ARM64_MODULE_PLTS
812 bool
813 select ARM64_MODULE_CMODEL_LARGE
814 select HAVE_MOD_ARCH_SPECIFIC
815
816config RELOCATABLE
817 bool
818 help
819 This builds the kernel as a Position Independent Executable (PIE),
820 which retains all relocation metadata required to relocate the
821 kernel binary at runtime to a different virtual address than the
822 address it was linked at.
823 Since AArch64 uses the RELA relocation format, this requires a
824 relocation pass at runtime even if the kernel is loaded at the
825 same address it was linked at.
826
827config RANDOMIZE_BASE
828 bool "Randomize the address of the kernel image"
829 select ARM64_MODULE_PLTS
830 select RELOCATABLE
831 help
832 Randomizes the virtual address at which the kernel image is
833 loaded, as a security feature that deters exploit attempts
834 relying on knowledge of the location of kernel internals.
835
836 It is the bootloader's job to provide entropy, by passing a
837 random u64 value in /chosen/kaslr-seed at kernel entry.
838
839 When booting via the UEFI stub, it will invoke the firmware's
840 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
841 to the kernel proper. In addition, it will randomise the physical
842 location of the kernel Image as well.
843
844 If unsure, say N.
845
846config RANDOMIZE_MODULE_REGION_FULL
847 bool "Randomize the module region independently from the core kernel"
848 depends on RANDOMIZE_BASE
849 default y
850 help
851 Randomizes the location of the module region without considering the
852 location of the core kernel. This way, it is impossible for modules
853 to leak information about the location of core kernel data structures
854 but it does imply that function calls between modules and the core
855 kernel will need to be resolved via veneers in the module PLT.
856
857 When this option is not set, the module region will be randomized over
858 a limited range that contains the [_stext, _etext] interval of the
859 core kernel, so branch relocations are always in range.
860
861endmenu
862
863menu "Boot options"
864
865config ARM64_ACPI_PARKING_PROTOCOL
866 bool "Enable support for the ARM64 ACPI parking protocol"
867 depends on ACPI
868 help
869 Enable support for the ARM64 ACPI parking protocol. If disabled
870 the kernel will not allow booting through the ARM64 ACPI parking
871 protocol even if the corresponding data is present in the ACPI
872 MADT table.
873
874config CMDLINE
875 string "Default kernel command string"
876 default ""
877 help
878 Provide a set of default command-line options at build time by
879 entering them here. As a minimum, you should specify the the
880 root device (e.g. root=/dev/nfs).
881
882config CMDLINE_FORCE
883 bool "Always use the default kernel command string"
884 help
885 Always use the default kernel command string, even if the boot
886 loader passes other arguments to the kernel.
887 This is useful if you cannot or don't want to change the
888 command-line options your boot loader passes to the kernel.
889
890config EFI_STUB
891 bool
892
893config EFI
894 bool "UEFI runtime support"
895 depends on OF && !CPU_BIG_ENDIAN
896 select LIBFDT
897 select UCS2_STRING
898 select EFI_PARAMS_FROM_FDT
899 select EFI_RUNTIME_WRAPPERS
900 select EFI_STUB
901 select EFI_ARMSTUB
902 default y
903 help
904 This option provides support for runtime services provided
905 by UEFI firmware (such as non-volatile variables, realtime
906 clock, and platform reset). A UEFI stub is also provided to
907 allow the kernel to be booted as an EFI application. This
908 is only useful on systems that have UEFI firmware.
909
910config DMI
911 bool "Enable support for SMBIOS (DMI) tables"
912 depends on EFI
913 default y
914 help
915 This enables SMBIOS/DMI feature for systems.
916
917 This option is only useful on systems that have UEFI firmware.
918 However, even with this option, the resultant kernel should
919 continue to boot on existing non-UEFI platforms.
920
921endmenu
922
923menu "Userspace binary formats"
924
925source "fs/Kconfig.binfmt"
926
927config COMPAT
928 bool "Kernel support for 32-bit EL0"
929 depends on ARM64_4K_PAGES || EXPERT
930 select COMPAT_BINFMT_ELF
931 select HAVE_UID16
932 select OLD_SIGSUSPEND3
933 select COMPAT_OLD_SIGACTION
934 help
935 This option enables support for a 32-bit EL0 running under a 64-bit
936 kernel at EL1. AArch32-specific components such as system calls,
937 the user helper functions, VFP support and the ptrace interface are
938 handled appropriately by the kernel.
939
940 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
941 that you will only be able to execute AArch32 binaries that were compiled
942 with page size aligned segments.
943
944 If you want to execute 32-bit userspace applications, say Y.
945
946config SYSVIPC_COMPAT
947 def_bool y
948 depends on COMPAT && SYSVIPC
949
950endmenu
951
952menu "Power management options"
953
954source "kernel/power/Kconfig"
955
956config ARCH_SUSPEND_POSSIBLE
957 def_bool y
958
959endmenu
960
961menu "CPU Power Management"
962
963source "drivers/cpuidle/Kconfig"
964
965source "drivers/cpufreq/Kconfig"
966
967endmenu
968
969source "net/Kconfig"
970
971source "drivers/Kconfig"
972
973source "drivers/firmware/Kconfig"
974
975source "drivers/acpi/Kconfig"
976
977source "fs/Kconfig"
978
979source "arch/arm64/kvm/Kconfig"
980
981source "arch/arm64/Kconfig.debug"
982
983source "security/Kconfig"
984
985source "crypto/Kconfig"
986if CRYPTO
987source "arch/arm64/crypto/Kconfig"
988endif
989
990source "lib/Kconfig"
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3 def_bool y
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU
9 select ACPI_IORT if ACPI
10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
11 select ACPI_MCFG if (ACPI && PCI)
12 select ACPI_SPCR_TABLE if ACPI
13 select ACPI_PPTT if ACPI
14 select ARCH_HAS_DEBUG_WX
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS
16 select ARCH_BINFMT_ELF_STATE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CC_PLATFORM
24 select ARCH_HAS_CURRENT_STACK_POINTER
25 select ARCH_HAS_DEBUG_VIRTUAL
26 select ARCH_HAS_DEBUG_VM_PGTABLE
27 select ARCH_HAS_DMA_OPS if XEN
28 select ARCH_HAS_DMA_PREP_COHERENT
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
30 select ARCH_HAS_FAST_MULTIPLIER
31 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL
33 select ARCH_HAS_GIGANTIC_PAGE
34 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON
36 select ARCH_HAS_KEEPINITRD
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE
38 select ARCH_HAS_MEM_ENCRYPT
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
41 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT
42 select ARCH_HAS_PTE_DEVMAP
43 select ARCH_HAS_PTE_SPECIAL
44 select ARCH_HAS_HW_PTE_YOUNG
45 select ARCH_HAS_SETUP_DMA_OPS
46 select ARCH_HAS_SET_DIRECT_MAP
47 select ARCH_HAS_SET_MEMORY
48 select ARCH_HAS_MEM_ENCRYPT
49 select ARCH_HAS_FORCE_DMA_UNENCRYPTED
50 select ARCH_STACKWALK
51 select ARCH_HAS_STRICT_KERNEL_RWX
52 select ARCH_HAS_STRICT_MODULE_RWX
53 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
54 select ARCH_HAS_SYNC_DMA_FOR_CPU
55 select ARCH_HAS_SYSCALL_WRAPPER
56 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
57 select ARCH_HAS_ZONE_DMA_SET if EXPERT
58 select ARCH_HAVE_ELF_PROT
59 select ARCH_HAVE_NMI_SAFE_CMPXCHG
60 select ARCH_HAVE_TRACE_MMIO_ACCESS
61 select ARCH_INLINE_READ_LOCK if !PREEMPTION
62 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
63 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
64 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
65 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
66 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
67 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
68 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
69 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
70 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
71 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
72 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
73 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
74 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
75 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
76 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
77 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
78 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
79 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
80 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
81 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
82 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
83 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
84 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
85 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
86 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
87 select ARCH_KEEP_MEMBLOCK
88 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
89 select ARCH_USE_CMPXCHG_LOCKREF
90 select ARCH_USE_GNU_PROPERTY
91 select ARCH_USE_MEMTEST
92 select ARCH_USE_QUEUED_RWLOCKS
93 select ARCH_USE_QUEUED_SPINLOCKS
94 select ARCH_USE_SYM_ANNOTATIONS
95 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
96 select ARCH_SUPPORTS_HUGETLBFS
97 select ARCH_SUPPORTS_MEMORY_FAILURE
98 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
99 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
100 select ARCH_SUPPORTS_LTO_CLANG_THIN
101 select ARCH_SUPPORTS_CFI_CLANG
102 select ARCH_SUPPORTS_ATOMIC_RMW
103 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
104 select ARCH_SUPPORTS_NUMA_BALANCING
105 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
106 select ARCH_SUPPORTS_PER_VMA_LOCK
107 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE
108 select ARCH_SUPPORTS_RT
109 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
110 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
111 select ARCH_WANT_DEFAULT_BPF_JIT
112 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
113 select ARCH_WANT_FRAME_POINTERS
114 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
115 select ARCH_WANT_LD_ORPHAN_WARN
116 select ARCH_WANTS_EXECMEM_LATE if EXECMEM
117 select ARCH_WANTS_NO_INSTR
118 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
119 select ARCH_HAS_UBSAN
120 select ARM_AMBA
121 select ARM_ARCH_TIMER
122 select ARM_GIC
123 select AUDIT_ARCH_COMPAT_GENERIC
124 select ARM_GIC_V2M if PCI
125 select ARM_GIC_V3
126 select ARM_GIC_V3_ITS if PCI
127 select ARM_PSCI_FW
128 select BUILDTIME_TABLE_SORT
129 select CLONE_BACKWARDS
130 select COMMON_CLK
131 select CPU_PM if (SUSPEND || CPU_IDLE)
132 select CPUMASK_OFFSTACK if NR_CPUS > 256
133 select CRC32
134 select DCACHE_WORD_ACCESS
135 select DYNAMIC_FTRACE if FUNCTION_TRACER
136 select DMA_BOUNCE_UNALIGNED_KMALLOC
137 select DMA_DIRECT_REMAP
138 select EDAC_SUPPORT
139 select FRAME_POINTER
140 select FUNCTION_ALIGNMENT_4B
141 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
142 select GENERIC_ALLOCATOR
143 select GENERIC_ARCH_TOPOLOGY
144 select GENERIC_CLOCKEVENTS_BROADCAST
145 select GENERIC_CPU_AUTOPROBE
146 select GENERIC_CPU_DEVICES
147 select GENERIC_CPU_VULNERABILITIES
148 select GENERIC_EARLY_IOREMAP
149 select GENERIC_IDLE_POLL_SETUP
150 select GENERIC_IOREMAP
151 select GENERIC_IRQ_IPI
152 select GENERIC_IRQ_PROBE
153 select GENERIC_IRQ_SHOW
154 select GENERIC_IRQ_SHOW_LEVEL
155 select GENERIC_LIB_DEVMEM_IS_ALLOWED
156 select GENERIC_PCI_IOMAP
157 select GENERIC_PTDUMP
158 select GENERIC_SCHED_CLOCK
159 select GENERIC_SMP_IDLE_THREAD
160 select GENERIC_TIME_VSYSCALL
161 select GENERIC_GETTIMEOFDAY
162 select GENERIC_VDSO_TIME_NS
163 select HARDIRQS_SW_RESEND
164 select HAS_IOPORT
165 select HAVE_MOVE_PMD
166 select HAVE_MOVE_PUD
167 select HAVE_PCI
168 select HAVE_ACPI_APEI if (ACPI && EFI)
169 select HAVE_ALIGNED_STRUCT_PAGE
170 select HAVE_ARCH_AUDITSYSCALL
171 select HAVE_ARCH_BITREVERSE
172 select HAVE_ARCH_COMPILER_H
173 select HAVE_ARCH_HUGE_VMALLOC
174 select HAVE_ARCH_HUGE_VMAP
175 select HAVE_ARCH_JUMP_LABEL
176 select HAVE_ARCH_JUMP_LABEL_RELATIVE
177 select HAVE_ARCH_KASAN
178 select HAVE_ARCH_KASAN_VMALLOC
179 select HAVE_ARCH_KASAN_SW_TAGS
180 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE
181 # Some instrumentation may be unsound, hence EXPERT
182 select HAVE_ARCH_KCSAN if EXPERT
183 select HAVE_ARCH_KFENCE
184 select HAVE_ARCH_KGDB
185 select HAVE_ARCH_MMAP_RND_BITS
186 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
187 select HAVE_ARCH_PREL32_RELOCATIONS
188 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
189 select HAVE_ARCH_SECCOMP_FILTER
190 select HAVE_ARCH_STACKLEAK
191 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
192 select HAVE_ARCH_TRACEHOOK
193 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
194 select HAVE_ARCH_VMAP_STACK
195 select HAVE_ARM_SMCCC
196 select HAVE_ASM_MODVERSIONS
197 select HAVE_EBPF_JIT
198 select HAVE_C_RECORDMCOUNT
199 select HAVE_CMPXCHG_DOUBLE
200 select HAVE_CMPXCHG_LOCAL
201 select HAVE_CONTEXT_TRACKING_USER
202 select HAVE_DEBUG_KMEMLEAK
203 select HAVE_DMA_CONTIGUOUS
204 select HAVE_DYNAMIC_FTRACE
205 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
206 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \
207 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS)
208 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
209 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
210 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
211 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
212 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE))
213 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
214 if DYNAMIC_FTRACE_WITH_ARGS
215 select HAVE_SAMPLE_FTRACE_DIRECT
216 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
217 select HAVE_EFFICIENT_UNALIGNED_ACCESS
218 select HAVE_GUP_FAST
219 select HAVE_FTRACE_MCOUNT_RECORD
220 select HAVE_FUNCTION_TRACER
221 select HAVE_FUNCTION_ERROR_INJECTION
222 select HAVE_FUNCTION_GRAPH_TRACER
223 select HAVE_FUNCTION_GRAPH_RETVAL
224 select HAVE_GCC_PLUGINS
225 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
226 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
227 select HAVE_HW_BREAKPOINT if PERF_EVENTS
228 select HAVE_IOREMAP_PROT
229 select HAVE_IRQ_TIME_ACCOUNTING
230 select HAVE_MOD_ARCH_SPECIFIC
231 select HAVE_NMI
232 select HAVE_PERF_EVENTS
233 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
234 select HAVE_PERF_REGS
235 select HAVE_PERF_USER_STACK_DUMP
236 select HAVE_PREEMPT_DYNAMIC_KEY
237 select HAVE_REGS_AND_STACK_ACCESS_API
238 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
239 select HAVE_FUNCTION_ARG_ACCESS_API
240 select MMU_GATHER_RCU_TABLE_FREE
241 select HAVE_RSEQ
242 select HAVE_RUST if RUSTC_SUPPORTS_ARM64
243 select HAVE_STACKPROTECTOR
244 select HAVE_SYSCALL_TRACEPOINTS
245 select HAVE_KPROBES
246 select HAVE_KRETPROBES
247 select HAVE_GENERIC_VDSO
248 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
249 select IRQ_DOMAIN
250 select IRQ_FORCED_THREADING
251 select KASAN_VMALLOC if KASAN
252 select LOCK_MM_AND_FIND_VMA
253 select MODULES_USE_ELF_RELA
254 select NEED_DMA_MAP_STATE
255 select NEED_SG_DMA_LENGTH
256 select OF
257 select OF_EARLY_FLATTREE
258 select PCI_DOMAINS_GENERIC if PCI
259 select PCI_ECAM if (ACPI && PCI)
260 select PCI_SYSCALL if PCI
261 select POWER_RESET
262 select POWER_SUPPLY
263 select SPARSE_IRQ
264 select SWIOTLB
265 select SYSCTL_EXCEPTION_TRACE
266 select THREAD_INFO_IN_TASK
267 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
268 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD
269 select TRACE_IRQFLAGS_SUPPORT
270 select TRACE_IRQFLAGS_NMI_SUPPORT
271 select HAVE_SOFTIRQ_ON_OWN_STACK
272 select USER_STACKTRACE_SUPPORT
273 select VDSO_GETRANDOM
274 help
275 ARM 64-bit (AArch64) Linux support.
276
277config RUSTC_SUPPORTS_ARM64
278 def_bool y
279 depends on CPU_LITTLE_ENDIAN
280 # Shadow call stack is only supported on certain rustc versions.
281 #
282 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is
283 # required due to use of the -Zfixed-x18 flag.
284 #
285 # Otherwise, rustc version 1.82+ is required due to use of the
286 # -Zsanitizer=shadow-call-stack flag.
287 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS
288
289config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
290 def_bool CC_IS_CLANG
291 # https://github.com/ClangBuiltLinux/linux/issues/1507
292 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
293
294config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
295 def_bool CC_IS_GCC
296 depends on $(cc-option,-fpatchable-function-entry=2)
297
298config 64BIT
299 def_bool y
300
301config MMU
302 def_bool y
303
304config ARM64_CONT_PTE_SHIFT
305 int
306 default 5 if PAGE_SIZE_64KB
307 default 7 if PAGE_SIZE_16KB
308 default 4
309
310config ARM64_CONT_PMD_SHIFT
311 int
312 default 5 if PAGE_SIZE_64KB
313 default 5 if PAGE_SIZE_16KB
314 default 4
315
316config ARCH_MMAP_RND_BITS_MIN
317 default 14 if PAGE_SIZE_64KB
318 default 16 if PAGE_SIZE_16KB
319 default 18
320
321# max bits determined by the following formula:
322# VA_BITS - PAGE_SHIFT - 3
323config ARCH_MMAP_RND_BITS_MAX
324 default 19 if ARM64_VA_BITS=36
325 default 24 if ARM64_VA_BITS=39
326 default 27 if ARM64_VA_BITS=42
327 default 30 if ARM64_VA_BITS=47
328 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
329 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
330 default 33 if ARM64_VA_BITS=48
331 default 14 if ARM64_64K_PAGES
332 default 16 if ARM64_16K_PAGES
333 default 18
334
335config ARCH_MMAP_RND_COMPAT_BITS_MIN
336 default 7 if ARM64_64K_PAGES
337 default 9 if ARM64_16K_PAGES
338 default 11
339
340config ARCH_MMAP_RND_COMPAT_BITS_MAX
341 default 16
342
343config NO_IOPORT_MAP
344 def_bool y if !PCI
345
346config STACKTRACE_SUPPORT
347 def_bool y
348
349config ILLEGAL_POINTER_VALUE
350 hex
351 default 0xdead000000000000
352
353config LOCKDEP_SUPPORT
354 def_bool y
355
356config GENERIC_BUG
357 def_bool y
358 depends on BUG
359
360config GENERIC_BUG_RELATIVE_POINTERS
361 def_bool y
362 depends on GENERIC_BUG
363
364config GENERIC_HWEIGHT
365 def_bool y
366
367config GENERIC_CSUM
368 def_bool y
369
370config GENERIC_CALIBRATE_DELAY
371 def_bool y
372
373config SMP
374 def_bool y
375
376config KERNEL_MODE_NEON
377 def_bool y
378
379config FIX_EARLYCON_MEM
380 def_bool y
381
382config PGTABLE_LEVELS
383 int
384 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
385 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
386 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
387 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
388 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
389 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
390 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
391 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52
392
393config ARCH_SUPPORTS_UPROBES
394 def_bool y
395
396config ARCH_PROC_KCORE_TEXT
397 def_bool y
398
399config BROKEN_GAS_INST
400 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
401
402config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
403 bool
404 # Clang's __builtin_return_address() strips the PAC since 12.0.0
405 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
406 default y if CC_IS_CLANG
407 # GCC's __builtin_return_address() strips the PAC since 11.1.0,
408 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
409 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
410 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
411 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
412 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
413 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
414 default n
415
416config KASAN_SHADOW_OFFSET
417 hex
418 depends on KASAN_GENERIC || KASAN_SW_TAGS
419 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS
420 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS
421 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
422 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
423 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
424 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS
425 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS
426 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
427 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
428 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
429 default 0xffffffffffffffff
430
431config UNWIND_TABLES
432 bool
433
434source "arch/arm64/Kconfig.platforms"
435
436menu "Kernel Features"
437
438menu "ARM errata workarounds via the alternatives framework"
439
440config AMPERE_ERRATUM_AC03_CPU_38
441 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
442 default y
443 help
444 This option adds an alternative code sequence to work around Ampere
445 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.
446
447 The affected design reports FEAT_HAFDBS as not implemented in
448 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
449 as required by the architecture. The unadvertised HAFDBS
450 implementation suffers from an additional erratum where hardware
451 A/D updates can occur after a PTE has been marked invalid.
452
453 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
454 which avoids enabling unadvertised hardware Access Flag management
455 at stage-2.
456
457 If unsure, say Y.
458
459config ARM64_WORKAROUND_CLEAN_CACHE
460 bool
461
462config ARM64_ERRATUM_826319
463 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
464 default y
465 select ARM64_WORKAROUND_CLEAN_CACHE
466 help
467 This option adds an alternative code sequence to work around ARM
468 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
469 AXI master interface and an L2 cache.
470
471 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
472 and is unable to accept a certain write via this interface, it will
473 not progress on read data presented on the read data channel and the
474 system can deadlock.
475
476 The workaround promotes data cache clean instructions to
477 data cache clean-and-invalidate.
478 Please note that this does not necessarily enable the workaround,
479 as it depends on the alternative framework, which will only patch
480 the kernel if an affected CPU is detected.
481
482 If unsure, say Y.
483
484config ARM64_ERRATUM_827319
485 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
486 default y
487 select ARM64_WORKAROUND_CLEAN_CACHE
488 help
489 This option adds an alternative code sequence to work around ARM
490 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
491 master interface and an L2 cache.
492
493 Under certain conditions this erratum can cause a clean line eviction
494 to occur at the same time as another transaction to the same address
495 on the AMBA 5 CHI interface, which can cause data corruption if the
496 interconnect reorders the two transactions.
497
498 The workaround promotes data cache clean instructions to
499 data cache clean-and-invalidate.
500 Please note that this does not necessarily enable the workaround,
501 as it depends on the alternative framework, which will only patch
502 the kernel if an affected CPU is detected.
503
504 If unsure, say Y.
505
506config ARM64_ERRATUM_824069
507 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
508 default y
509 select ARM64_WORKAROUND_CLEAN_CACHE
510 help
511 This option adds an alternative code sequence to work around ARM
512 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
513 to a coherent interconnect.
514
515 If a Cortex-A53 processor is executing a store or prefetch for
516 write instruction at the same time as a processor in another
517 cluster is executing a cache maintenance operation to the same
518 address, then this erratum might cause a clean cache line to be
519 incorrectly marked as dirty.
520
521 The workaround promotes data cache clean instructions to
522 data cache clean-and-invalidate.
523 Please note that this option does not necessarily enable the
524 workaround, as it depends on the alternative framework, which will
525 only patch the kernel if an affected CPU is detected.
526
527 If unsure, say Y.
528
529config ARM64_ERRATUM_819472
530 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
531 default y
532 select ARM64_WORKAROUND_CLEAN_CACHE
533 help
534 This option adds an alternative code sequence to work around ARM
535 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
536 present when it is connected to a coherent interconnect.
537
538 If the processor is executing a load and store exclusive sequence at
539 the same time as a processor in another cluster is executing a cache
540 maintenance operation to the same address, then this erratum might
541 cause data corruption.
542
543 The workaround promotes data cache clean instructions to
544 data cache clean-and-invalidate.
545 Please note that this does not necessarily enable the workaround,
546 as it depends on the alternative framework, which will only patch
547 the kernel if an affected CPU is detected.
548
549 If unsure, say Y.
550
551config ARM64_ERRATUM_832075
552 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
553 default y
554 help
555 This option adds an alternative code sequence to work around ARM
556 erratum 832075 on Cortex-A57 parts up to r1p2.
557
558 Affected Cortex-A57 parts might deadlock when exclusive load/store
559 instructions to Write-Back memory are mixed with Device loads.
560
561 The workaround is to promote device loads to use Load-Acquire
562 semantics.
563 Please note that this does not necessarily enable the workaround,
564 as it depends on the alternative framework, which will only patch
565 the kernel if an affected CPU is detected.
566
567 If unsure, say Y.
568
569config ARM64_ERRATUM_834220
570 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"
571 depends on KVM
572 help
573 This option adds an alternative code sequence to work around ARM
574 erratum 834220 on Cortex-A57 parts up to r1p2.
575
576 Affected Cortex-A57 parts might report a Stage 2 translation
577 fault as the result of a Stage 1 fault for load crossing a
578 page boundary when there is a permission or device memory
579 alignment fault at Stage 1 and a translation fault at Stage 2.
580
581 The workaround is to verify that the Stage 1 translation
582 doesn't generate a fault before handling the Stage 2 fault.
583 Please note that this does not necessarily enable the workaround,
584 as it depends on the alternative framework, which will only patch
585 the kernel if an affected CPU is detected.
586
587 If unsure, say N.
588
589config ARM64_ERRATUM_1742098
590 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
591 depends on COMPAT
592 default y
593 help
594 This option removes the AES hwcap for aarch32 user-space to
595 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
596
597 Affected parts may corrupt the AES state if an interrupt is
598 taken between a pair of AES instructions. These instructions
599 are only present if the cryptography extensions are present.
600 All software should have a fallback implementation for CPUs
601 that don't implement the cryptography extensions.
602
603 If unsure, say Y.
604
605config ARM64_ERRATUM_845719
606 bool "Cortex-A53: 845719: a load might read incorrect data"
607 depends on COMPAT
608 default y
609 help
610 This option adds an alternative code sequence to work around ARM
611 erratum 845719 on Cortex-A53 parts up to r0p4.
612
613 When running a compat (AArch32) userspace on an affected Cortex-A53
614 part, a load at EL0 from a virtual address that matches the bottom 32
615 bits of the virtual address used by a recent load at (AArch64) EL1
616 might return incorrect data.
617
618 The workaround is to write the contextidr_el1 register on exception
619 return to a 32-bit task.
620 Please note that this does not necessarily enable the workaround,
621 as it depends on the alternative framework, which will only patch
622 the kernel if an affected CPU is detected.
623
624 If unsure, say Y.
625
626config ARM64_ERRATUM_843419
627 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
628 default y
629 help
630 This option links the kernel with '--fix-cortex-a53-843419' and
631 enables PLT support to replace certain ADRP instructions, which can
632 cause subsequent memory accesses to use an incorrect address on
633 Cortex-A53 parts up to r0p4.
634
635 If unsure, say Y.
636
637config ARM64_LD_HAS_FIX_ERRATUM_843419
638 def_bool $(ld-option,--fix-cortex-a53-843419)
639
640config ARM64_ERRATUM_1024718
641 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
642 default y
643 help
644 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
645
646 Affected Cortex-A55 cores (all revisions) could cause incorrect
647 update of the hardware dirty bit when the DBM/AP bits are updated
648 without a break-before-make. The workaround is to disable the usage
649 of hardware DBM locally on the affected cores. CPUs not affected by
650 this erratum will continue to use the feature.
651
652 If unsure, say Y.
653
654config ARM64_ERRATUM_1418040
655 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
656 default y
657 depends on COMPAT
658 help
659 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
660 errata 1188873 and 1418040.
661
662 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
663 cause register corruption when accessing the timer registers
664 from AArch32 userspace.
665
666 If unsure, say Y.
667
668config ARM64_WORKAROUND_SPECULATIVE_AT
669 bool
670
671config ARM64_ERRATUM_1165522
672 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
673 default y
674 select ARM64_WORKAROUND_SPECULATIVE_AT
675 help
676 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
677
678 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
679 corrupted TLBs by speculating an AT instruction during a guest
680 context switch.
681
682 If unsure, say Y.
683
684config ARM64_ERRATUM_1319367
685 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
686 default y
687 select ARM64_WORKAROUND_SPECULATIVE_AT
688 help
689 This option adds work arounds for ARM Cortex-A57 erratum 1319537
690 and A72 erratum 1319367
691
692 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
693 speculating an AT instruction during a guest context switch.
694
695 If unsure, say Y.
696
697config ARM64_ERRATUM_1530923
698 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
699 default y
700 select ARM64_WORKAROUND_SPECULATIVE_AT
701 help
702 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
703
704 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
705 corrupted TLBs by speculating an AT instruction during a guest
706 context switch.
707
708 If unsure, say Y.
709
710config ARM64_WORKAROUND_REPEAT_TLBI
711 bool
712
713config ARM64_ERRATUM_2441007
714 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
715 select ARM64_WORKAROUND_REPEAT_TLBI
716 help
717 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
718
719 Under very rare circumstances, affected Cortex-A55 CPUs
720 may not handle a race between a break-before-make sequence on one
721 CPU, and another CPU accessing the same page. This could allow a
722 store to a page that has been unmapped.
723
724 Work around this by adding the affected CPUs to the list that needs
725 TLB sequences to be done twice.
726
727 If unsure, say N.
728
729config ARM64_ERRATUM_1286807
730 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)"
731 select ARM64_WORKAROUND_REPEAT_TLBI
732 help
733 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
734
735 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
736 address for a cacheable mapping of a location is being
737 accessed by a core while another core is remapping the virtual
738 address to a new physical page using the recommended
739 break-before-make sequence, then under very rare circumstances
740 TLBI+DSB completes before a read using the translation being
741 invalidated has been observed by other observers. The
742 workaround repeats the TLBI+DSB operation.
743
744 If unsure, say N.
745
746config ARM64_ERRATUM_1463225
747 bool "Cortex-A76: Software Step might prevent interrupt recognition"
748 default y
749 help
750 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
751
752 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
753 of a system call instruction (SVC) can prevent recognition of
754 subsequent interrupts when software stepping is disabled in the
755 exception handler of the system call and either kernel debugging
756 is enabled or VHE is in use.
757
758 Work around the erratum by triggering a dummy step exception
759 when handling a system call from a task that is being stepped
760 in a VHE configuration of the kernel.
761
762 If unsure, say Y.
763
764config ARM64_ERRATUM_1542419
765 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
766 help
767 This option adds a workaround for ARM Neoverse-N1 erratum
768 1542419.
769
770 Affected Neoverse-N1 cores could execute a stale instruction when
771 modified by another CPU. The workaround depends on a firmware
772 counterpart.
773
774 Workaround the issue by hiding the DIC feature from EL0. This
775 forces user-space to perform cache maintenance.
776
777 If unsure, say N.
778
779config ARM64_ERRATUM_1508412
780 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
781 default y
782 help
783 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
784
785 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
786 of a store-exclusive or read of PAR_EL1 and a load with device or
787 non-cacheable memory attributes. The workaround depends on a firmware
788 counterpart.
789
790 KVM guests must also have the workaround implemented or they can
791 deadlock the system.
792
793 Work around the issue by inserting DMB SY barriers around PAR_EL1
794 register reads and warning KVM users. The DMB barrier is sufficient
795 to prevent a speculative PAR_EL1 read.
796
797 If unsure, say Y.
798
799config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
800 bool
801
802config ARM64_ERRATUM_2051678
803 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
804 default y
805 help
806 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
807 Affected Cortex-A510 might not respect the ordering rules for
808 hardware update of the page table's dirty bit. The workaround
809 is to not enable the feature on affected CPUs.
810
811 If unsure, say Y.
812
813config ARM64_ERRATUM_2077057
814 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
815 default y
816 help
817 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
818 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
819 expected, but a Pointer Authentication trap is taken instead. The
820 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
821 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
822
823 This can only happen when EL2 is stepping EL1.
824
825 When these conditions occur, the SPSR_EL2 value is unchanged from the
826 previous guest entry, and can be restored from the in-memory copy.
827
828 If unsure, say Y.
829
830config ARM64_ERRATUM_2658417
831 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
832 default y
833 help
834 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
835 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
836 BFMMLA or VMMLA instructions in rare circumstances when a pair of
837 A510 CPUs are using shared neon hardware. As the sharing is not
838 discoverable by the kernel, hide the BF16 HWCAP to indicate that
839 user-space should not be using these instructions.
840
841 If unsure, say Y.
842
843config ARM64_ERRATUM_2119858
844 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
845 default y
846 depends on CORESIGHT_TRBE
847 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
848 help
849 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
850
851 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
852 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
853 the event of a WRAP event.
854
855 Work around the issue by always making sure we move the TRBPTR_EL1 by
856 256 bytes before enabling the buffer and filling the first 256 bytes of
857 the buffer with ETM ignore packets upon disabling.
858
859 If unsure, say Y.
860
861config ARM64_ERRATUM_2139208
862 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
863 default y
864 depends on CORESIGHT_TRBE
865 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
866 help
867 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
868
869 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
870 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
871 the event of a WRAP event.
872
873 Work around the issue by always making sure we move the TRBPTR_EL1 by
874 256 bytes before enabling the buffer and filling the first 256 bytes of
875 the buffer with ETM ignore packets upon disabling.
876
877 If unsure, say Y.
878
879config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
880 bool
881
882config ARM64_ERRATUM_2054223
883 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
884 default y
885 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
886 help
887 Enable workaround for ARM Cortex-A710 erratum 2054223
888
889 Affected cores may fail to flush the trace data on a TSB instruction, when
890 the PE is in trace prohibited state. This will cause losing a few bytes
891 of the trace cached.
892
893 Workaround is to issue two TSB consecutively on affected cores.
894
895 If unsure, say Y.
896
897config ARM64_ERRATUM_2067961
898 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
899 default y
900 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
901 help
902 Enable workaround for ARM Neoverse-N2 erratum 2067961
903
904 Affected cores may fail to flush the trace data on a TSB instruction, when
905 the PE is in trace prohibited state. This will cause losing a few bytes
906 of the trace cached.
907
908 Workaround is to issue two TSB consecutively on affected cores.
909
910 If unsure, say Y.
911
912config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
913 bool
914
915config ARM64_ERRATUM_2253138
916 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
917 depends on CORESIGHT_TRBE
918 default y
919 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
920 help
921 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
922
923 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
924 for TRBE. Under some conditions, the TRBE might generate a write to the next
925 virtually addressed page following the last page of the TRBE address space
926 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
927
928 Work around this in the driver by always making sure that there is a
929 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
930
931 If unsure, say Y.
932
933config ARM64_ERRATUM_2224489
934 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
935 depends on CORESIGHT_TRBE
936 default y
937 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
938 help
939 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
940
941 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
942 for TRBE. Under some conditions, the TRBE might generate a write to the next
943 virtually addressed page following the last page of the TRBE address space
944 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
945
946 Work around this in the driver by always making sure that there is a
947 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
948
949 If unsure, say Y.
950
951config ARM64_ERRATUM_2441009
952 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
953 select ARM64_WORKAROUND_REPEAT_TLBI
954 help
955 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
956
957 Under very rare circumstances, affected Cortex-A510 CPUs
958 may not handle a race between a break-before-make sequence on one
959 CPU, and another CPU accessing the same page. This could allow a
960 store to a page that has been unmapped.
961
962 Work around this by adding the affected CPUs to the list that needs
963 TLB sequences to be done twice.
964
965 If unsure, say N.
966
967config ARM64_ERRATUM_2064142
968 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
969 depends on CORESIGHT_TRBE
970 default y
971 help
972 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
973
974 Affected Cortex-A510 core might fail to write into system registers after the
975 TRBE has been disabled. Under some conditions after the TRBE has been disabled
976 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
977 and TRBTRG_EL1 will be ignored and will not be effected.
978
979 Work around this in the driver by executing TSB CSYNC and DSB after collection
980 is stopped and before performing a system register write to one of the affected
981 registers.
982
983 If unsure, say Y.
984
985config ARM64_ERRATUM_2038923
986 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
987 depends on CORESIGHT_TRBE
988 default y
989 help
990 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
991
992 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
993 prohibited within the CPU. As a result, the trace buffer or trace buffer state
994 might be corrupted. This happens after TRBE buffer has been enabled by setting
995 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
996 execution changes from a context, in which trace is prohibited to one where it
997 isn't, or vice versa. In these mentioned conditions, the view of whether trace
998 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
999 the trace buffer state might be corrupted.
1000
1001 Work around this in the driver by preventing an inconsistent view of whether the
1002 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
1003 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
1004 two ISB instructions if no ERET is to take place.
1005
1006 If unsure, say Y.
1007
1008config ARM64_ERRATUM_1902691
1009 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1010 depends on CORESIGHT_TRBE
1011 default y
1012 help
1013 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1014
1015 Affected Cortex-A510 core might cause trace data corruption, when being written
1016 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1017 trace data.
1018
1019 Work around this problem in the driver by just preventing TRBE initialization on
1020 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1021 on such implementations. This will cover the kernel for any firmware that doesn't
1022 do this already.
1023
1024 If unsure, say Y.
1025
1026config ARM64_ERRATUM_2457168
1027 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1028 depends on ARM64_AMU_EXTN
1029 default y
1030 help
1031 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1032
1033 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1034 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1035 incorrectly giving a significantly higher output value.
1036
1037 Work around this problem by returning 0 when reading the affected counter in
1038 key locations that results in disabling all users of this counter. This effect
1039 is the same to firmware disabling affected counters.
1040
1041 If unsure, say Y.
1042
1043config ARM64_ERRATUM_2645198
1044 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1045 default y
1046 help
1047 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1048
1049 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1050 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1051 next instruction abort caused by permission fault.
1052
1053 Only user-space does executable to non-executable permission transition via
1054 mprotect() system call. Workaround the problem by doing a break-before-make
1055 TLB invalidation, for all changes to executable user space mappings.
1056
1057 If unsure, say Y.
1058
1059config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1060 bool
1061
1062config ARM64_ERRATUM_2966298
1063 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1064 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1065 default y
1066 help
1067 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1068
1069 On an affected Cortex-A520 core, a speculatively executed unprivileged
1070 load might leak data from a privileged level via a cache side channel.
1071
1072 Work around this problem by executing a TLBI before returning to EL0.
1073
1074 If unsure, say Y.
1075
1076config ARM64_ERRATUM_3117295
1077 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1078 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1079 default y
1080 help
1081 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1082
1083 On an affected Cortex-A510 core, a speculatively executed unprivileged
1084 load might leak data from a privileged level via a cache side channel.
1085
1086 Work around this problem by executing a TLBI before returning to EL0.
1087
1088 If unsure, say Y.
1089
1090config ARM64_ERRATUM_3194386
1091 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1092 default y
1093 help
1094 This option adds the workaround for the following errata:
1095
1096 * ARM Cortex-A76 erratum 3324349
1097 * ARM Cortex-A77 erratum 3324348
1098 * ARM Cortex-A78 erratum 3324344
1099 * ARM Cortex-A78C erratum 3324346
1100 * ARM Cortex-A78C erratum 3324347
1101 * ARM Cortex-A710 erratam 3324338
1102 * ARM Cortex-A715 errartum 3456084
1103 * ARM Cortex-A720 erratum 3456091
1104 * ARM Cortex-A725 erratum 3456106
1105 * ARM Cortex-X1 erratum 3324344
1106 * ARM Cortex-X1C erratum 3324346
1107 * ARM Cortex-X2 erratum 3324338
1108 * ARM Cortex-X3 erratum 3324335
1109 * ARM Cortex-X4 erratum 3194386
1110 * ARM Cortex-X925 erratum 3324334
1111 * ARM Neoverse-N1 erratum 3324349
1112 * ARM Neoverse N2 erratum 3324339
1113 * ARM Neoverse-N3 erratum 3456111
1114 * ARM Neoverse-V1 erratum 3324341
1115 * ARM Neoverse V2 erratum 3324336
1116 * ARM Neoverse-V3 erratum 3312417
1117
1118 On affected cores "MSR SSBS, #0" instructions may not affect
1119 subsequent speculative instructions, which may permit unexepected
1120 speculative store bypassing.
1121
1122 Work around this problem by placing a Speculation Barrier (SB) or
1123 Instruction Synchronization Barrier (ISB) after kernel changes to
1124 SSBS. The presence of the SSBS special-purpose register is hidden
1125 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1126 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
1127
1128 If unsure, say Y.
1129
1130config CAVIUM_ERRATUM_22375
1131 bool "Cavium erratum 22375, 24313"
1132 default y
1133 help
1134 Enable workaround for errata 22375 and 24313.
1135
1136 This implements two gicv3-its errata workarounds for ThunderX. Both
1137 with a small impact affecting only ITS table allocation.
1138
1139 erratum 22375: only alloc 8MB table size
1140 erratum 24313: ignore memory access type
1141
1142 The fixes are in ITS initialization and basically ignore memory access
1143 type and table size provided by the TYPER and BASER registers.
1144
1145 If unsure, say Y.
1146
1147config CAVIUM_ERRATUM_23144
1148 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1149 depends on NUMA
1150 default y
1151 help
1152 ITS SYNC command hang for cross node io and collections/cpu mapping.
1153
1154 If unsure, say Y.
1155
1156config CAVIUM_ERRATUM_23154
1157 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1158 default y
1159 help
1160 The ThunderX GICv3 implementation requires a modified version for
1161 reading the IAR status to ensure data synchronization
1162 (access to icc_iar1_el1 is not sync'ed before and after).
1163
1164 It also suffers from erratum 38545 (also present on Marvell's
1165 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1166 spuriously presented to the CPU interface.
1167
1168 If unsure, say Y.
1169
1170config CAVIUM_ERRATUM_27456
1171 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1172 default y
1173 help
1174 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1175 instructions may cause the icache to become corrupted if it
1176 contains data for a non-current ASID. The fix is to
1177 invalidate the icache when changing the mm context.
1178
1179 If unsure, say Y.
1180
1181config CAVIUM_ERRATUM_30115
1182 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1183 default y
1184 help
1185 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1186 1.2, and T83 Pass 1.0, KVM guest execution may disable
1187 interrupts in host. Trapping both GICv3 group-0 and group-1
1188 accesses sidesteps the issue.
1189
1190 If unsure, say Y.
1191
1192config CAVIUM_TX2_ERRATUM_219
1193 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1194 default y
1195 help
1196 On Cavium ThunderX2, a load, store or prefetch instruction between a
1197 TTBR update and the corresponding context synchronizing operation can
1198 cause a spurious Data Abort to be delivered to any hardware thread in
1199 the CPU core.
1200
1201 Work around the issue by avoiding the problematic code sequence and
1202 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1203 trap handler performs the corresponding register access, skips the
1204 instruction and ensures context synchronization by virtue of the
1205 exception return.
1206
1207 If unsure, say Y.
1208
1209config FUJITSU_ERRATUM_010001
1210 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1211 default y
1212 help
1213 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1214 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1215 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1216 This fault occurs under a specific hardware condition when a
1217 load/store instruction performs an address translation using:
1218 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1219 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1220 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1221 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1222
1223 The workaround is to ensure these bits are clear in TCR_ELx.
1224 The workaround only affects the Fujitsu-A64FX.
1225
1226 If unsure, say Y.
1227
1228config HISILICON_ERRATUM_161600802
1229 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1230 default y
1231 help
1232 The HiSilicon Hip07 SoC uses the wrong redistributor base
1233 when issued ITS commands such as VMOVP and VMAPP, and requires
1234 a 128kB offset to be applied to the target address in this commands.
1235
1236 If unsure, say Y.
1237
1238config HISILICON_ERRATUM_162100801
1239 bool "Hip09 162100801 erratum support"
1240 default y
1241 help
1242 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches
1243 during unmapping operation, which will cause some vSGIs lost.
1244 To fix the issue, invalidate related vPE cache through GICR_INVALLR
1245 after VMOVP.
1246
1247 If unsure, say Y.
1248
1249config QCOM_FALKOR_ERRATUM_1003
1250 bool "Falkor E1003: Incorrect translation due to ASID change"
1251 default y
1252 help
1253 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1254 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1255 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1256 then only for entries in the walk cache, since the leaf translation
1257 is unchanged. Work around the erratum by invalidating the walk cache
1258 entries for the trampoline before entering the kernel proper.
1259
1260config QCOM_FALKOR_ERRATUM_1009
1261 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1262 default y
1263 select ARM64_WORKAROUND_REPEAT_TLBI
1264 help
1265 On Falkor v1, the CPU may prematurely complete a DSB following a
1266 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1267 one more time to fix the issue.
1268
1269 If unsure, say Y.
1270
1271config QCOM_QDF2400_ERRATUM_0065
1272 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1273 default y
1274 help
1275 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1276 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1277 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1278
1279 If unsure, say Y.
1280
1281config QCOM_FALKOR_ERRATUM_E1041
1282 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1283 default y
1284 help
1285 Falkor CPU may speculatively fetch instructions from an improper
1286 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1287 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1288
1289 If unsure, say Y.
1290
1291config NVIDIA_CARMEL_CNP_ERRATUM
1292 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1293 default y
1294 help
1295 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1296 invalidate shared TLB entries installed by a different core, as it would
1297 on standard ARM cores.
1298
1299 If unsure, say Y.
1300
1301config ROCKCHIP_ERRATUM_3588001
1302 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1303 default y
1304 help
1305 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1306 This means, that its sharability feature may not be used, even though it
1307 is supported by the IP itself.
1308
1309 If unsure, say Y.
1310
1311config SOCIONEXT_SYNQUACER_PREITS
1312 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1313 default y
1314 help
1315 Socionext Synquacer SoCs implement a separate h/w block to generate
1316 MSI doorbell writes with non-zero values for the device ID.
1317
1318 If unsure, say Y.
1319
1320endmenu # "ARM errata workarounds via the alternatives framework"
1321
1322choice
1323 prompt "Page size"
1324 default ARM64_4K_PAGES
1325 help
1326 Page size (translation granule) configuration.
1327
1328config ARM64_4K_PAGES
1329 bool "4KB"
1330 select HAVE_PAGE_SIZE_4KB
1331 help
1332 This feature enables 4KB pages support.
1333
1334config ARM64_16K_PAGES
1335 bool "16KB"
1336 select HAVE_PAGE_SIZE_16KB
1337 help
1338 The system will use 16KB pages support. AArch32 emulation
1339 requires applications compiled with 16K (or a multiple of 16K)
1340 aligned segments.
1341
1342config ARM64_64K_PAGES
1343 bool "64KB"
1344 select HAVE_PAGE_SIZE_64KB
1345 help
1346 This feature enables 64KB pages support (4KB by default)
1347 allowing only two levels of page tables and faster TLB
1348 look-up. AArch32 emulation requires applications compiled
1349 with 64K aligned segments.
1350
1351endchoice
1352
1353choice
1354 prompt "Virtual address space size"
1355 default ARM64_VA_BITS_52
1356 help
1357 Allows choosing one of multiple possible virtual address
1358 space sizes. The level of translation table is determined by
1359 a combination of page size and virtual address space size.
1360
1361config ARM64_VA_BITS_36
1362 bool "36-bit" if EXPERT
1363 depends on PAGE_SIZE_16KB
1364
1365config ARM64_VA_BITS_39
1366 bool "39-bit"
1367 depends on PAGE_SIZE_4KB
1368
1369config ARM64_VA_BITS_42
1370 bool "42-bit"
1371 depends on PAGE_SIZE_64KB
1372
1373config ARM64_VA_BITS_47
1374 bool "47-bit"
1375 depends on PAGE_SIZE_16KB
1376
1377config ARM64_VA_BITS_48
1378 bool "48-bit"
1379
1380config ARM64_VA_BITS_52
1381 bool "52-bit"
1382 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1383 help
1384 Enable 52-bit virtual addressing for userspace when explicitly
1385 requested via a hint to mmap(). The kernel will also use 52-bit
1386 virtual addresses for its own mappings (provided HW support for
1387 this feature is available, otherwise it reverts to 48-bit).
1388
1389 NOTE: Enabling 52-bit virtual addressing in conjunction with
1390 ARMv8.3 Pointer Authentication will result in the PAC being
1391 reduced from 7 bits to 3 bits, which may have a significant
1392 impact on its susceptibility to brute-force attacks.
1393
1394 If unsure, select 48-bit virtual addressing instead.
1395
1396endchoice
1397
1398config ARM64_FORCE_52BIT
1399 bool "Force 52-bit virtual addresses for userspace"
1400 depends on ARM64_VA_BITS_52 && EXPERT
1401 help
1402 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1403 to maintain compatibility with older software by providing 48-bit VAs
1404 unless a hint is supplied to mmap.
1405
1406 This configuration option disables the 48-bit compatibility logic, and
1407 forces all userspace addresses to be 52-bit on HW that supports it. One
1408 should only enable this configuration option for stress testing userspace
1409 memory management code. If unsure say N here.
1410
1411config ARM64_VA_BITS
1412 int
1413 default 36 if ARM64_VA_BITS_36
1414 default 39 if ARM64_VA_BITS_39
1415 default 42 if ARM64_VA_BITS_42
1416 default 47 if ARM64_VA_BITS_47
1417 default 48 if ARM64_VA_BITS_48
1418 default 52 if ARM64_VA_BITS_52
1419
1420choice
1421 prompt "Physical address space size"
1422 default ARM64_PA_BITS_48
1423 help
1424 Choose the maximum physical address range that the kernel will
1425 support.
1426
1427config ARM64_PA_BITS_48
1428 bool "48-bit"
1429 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52
1430
1431config ARM64_PA_BITS_52
1432 bool "52-bit"
1433 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52
1434 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1435 help
1436 Enable support for a 52-bit physical address space, introduced as
1437 part of the ARMv8.2-LPA extension.
1438
1439 With this enabled, the kernel will also continue to work on CPUs that
1440 do not support ARMv8.2-LPA, but with some added memory overhead (and
1441 minor performance overhead).
1442
1443endchoice
1444
1445config ARM64_PA_BITS
1446 int
1447 default 48 if ARM64_PA_BITS_48
1448 default 52 if ARM64_PA_BITS_52
1449
1450config ARM64_LPA2
1451 def_bool y
1452 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES
1453
1454choice
1455 prompt "Endianness"
1456 default CPU_LITTLE_ENDIAN
1457 help
1458 Select the endianness of data accesses performed by the CPU. Userspace
1459 applications will need to be compiled and linked for the endianness
1460 that is selected here.
1461
1462config CPU_BIG_ENDIAN
1463 bool "Build big-endian kernel"
1464 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1465 depends on AS_IS_GNU || AS_VERSION >= 150000
1466 help
1467 Say Y if you plan on running a kernel with a big-endian userspace.
1468
1469config CPU_LITTLE_ENDIAN
1470 bool "Build little-endian kernel"
1471 help
1472 Say Y if you plan on running a kernel with a little-endian userspace.
1473 This is usually the case for distributions targeting arm64.
1474
1475endchoice
1476
1477config SCHED_MC
1478 bool "Multi-core scheduler support"
1479 help
1480 Multi-core scheduler support improves the CPU scheduler's decision
1481 making when dealing with multi-core CPU chips at a cost of slightly
1482 increased overhead in some places. If unsure say N here.
1483
1484config SCHED_CLUSTER
1485 bool "Cluster scheduler support"
1486 help
1487 Cluster scheduler support improves the CPU scheduler's decision
1488 making when dealing with machines that have clusters of CPUs.
1489 Cluster usually means a couple of CPUs which are placed closely
1490 by sharing mid-level caches, last-level cache tags or internal
1491 busses.
1492
1493config SCHED_SMT
1494 bool "SMT scheduler support"
1495 help
1496 Improves the CPU scheduler's decision making when dealing with
1497 MultiThreading at a cost of slightly increased overhead in some
1498 places. If unsure say N here.
1499
1500config NR_CPUS
1501 int "Maximum number of CPUs (2-4096)"
1502 range 2 4096
1503 default "512"
1504
1505config HOTPLUG_CPU
1506 bool "Support for hot-pluggable CPUs"
1507 select GENERIC_IRQ_MIGRATION
1508 help
1509 Say Y here to experiment with turning CPUs off and on. CPUs
1510 can be controlled through /sys/devices/system/cpu.
1511
1512# Common NUMA Features
1513config NUMA
1514 bool "NUMA Memory Allocation and Scheduler Support"
1515 select GENERIC_ARCH_NUMA
1516 select OF_NUMA
1517 select HAVE_SETUP_PER_CPU_AREA
1518 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1519 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1520 select USE_PERCPU_NUMA_NODE_ID
1521 help
1522 Enable NUMA (Non-Uniform Memory Access) support.
1523
1524 The kernel will try to allocate memory used by a CPU on the
1525 local memory of the CPU and add some more
1526 NUMA awareness to the kernel.
1527
1528config NODES_SHIFT
1529 int "Maximum NUMA Nodes (as a power of 2)"
1530 range 1 10
1531 default "4"
1532 depends on NUMA
1533 help
1534 Specify the maximum number of NUMA Nodes available on the target
1535 system. Increases memory reserved to accommodate various tables.
1536
1537source "kernel/Kconfig.hz"
1538
1539config ARCH_SPARSEMEM_ENABLE
1540 def_bool y
1541 select SPARSEMEM_VMEMMAP_ENABLE
1542 select SPARSEMEM_VMEMMAP
1543
1544config HW_PERF_EVENTS
1545 def_bool y
1546 depends on ARM_PMU
1547
1548# Supported by clang >= 7.0 or GCC >= 12.0.0
1549config CC_HAVE_SHADOW_CALL_STACK
1550 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1551
1552config PARAVIRT
1553 bool "Enable paravirtualization code"
1554 help
1555 This changes the kernel so it can modify itself when it is run
1556 under a hypervisor, potentially improving performance significantly
1557 over full virtualization.
1558
1559config PARAVIRT_TIME_ACCOUNTING
1560 bool "Paravirtual steal time accounting"
1561 select PARAVIRT
1562 help
1563 Select this option to enable fine granularity task steal time
1564 accounting. Time spent executing other tasks in parallel with
1565 the current vCPU is discounted from the vCPU power. To account for
1566 that, there can be a small performance impact.
1567
1568 If in doubt, say N here.
1569
1570config ARCH_SUPPORTS_KEXEC
1571 def_bool PM_SLEEP_SMP
1572
1573config ARCH_SUPPORTS_KEXEC_FILE
1574 def_bool y
1575
1576config ARCH_SELECTS_KEXEC_FILE
1577 def_bool y
1578 depends on KEXEC_FILE
1579 select HAVE_IMA_KEXEC if IMA
1580
1581config ARCH_SUPPORTS_KEXEC_SIG
1582 def_bool y
1583
1584config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1585 def_bool y
1586
1587config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1588 def_bool y
1589
1590config ARCH_SUPPORTS_CRASH_DUMP
1591 def_bool y
1592
1593config ARCH_DEFAULT_CRASH_DUMP
1594 def_bool y
1595
1596config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
1597 def_bool CRASH_RESERVE
1598
1599config TRANS_TABLE
1600 def_bool y
1601 depends on HIBERNATION || KEXEC_CORE
1602
1603config XEN_DOM0
1604 def_bool y
1605 depends on XEN
1606
1607config XEN
1608 bool "Xen guest support on ARM64"
1609 depends on ARM64 && OF
1610 select SWIOTLB_XEN
1611 select PARAVIRT
1612 help
1613 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1614
1615# include/linux/mmzone.h requires the following to be true:
1616#
1617# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1618#
1619# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1620#
1621# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER |
1622# ----+-------------------+--------------+----------------------+-------------------------+
1623# 4K | 27 | 12 | 15 | 10 |
1624# 16K | 27 | 14 | 13 | 11 |
1625# 64K | 29 | 16 | 13 | 13 |
1626config ARCH_FORCE_MAX_ORDER
1627 int
1628 default "13" if ARM64_64K_PAGES
1629 default "11" if ARM64_16K_PAGES
1630 default "10"
1631 help
1632 The kernel page allocator limits the size of maximal physically
1633 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1634 defines the maximal power of two of number of pages that can be
1635 allocated as a single contiguous block. This option allows
1636 overriding the default setting when ability to allocate very
1637 large blocks of physically contiguous memory is required.
1638
1639 The maximal size of allocation cannot exceed the size of the
1640 section, so the value of MAX_PAGE_ORDER should satisfy
1641
1642 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1643
1644 Don't change if unsure.
1645
1646config UNMAP_KERNEL_AT_EL0
1647 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1648 default y
1649 help
1650 Speculation attacks against some high-performance processors can
1651 be used to bypass MMU permission checks and leak kernel data to
1652 userspace. This can be defended against by unmapping the kernel
1653 when running in userspace, mapping it back in on exception entry
1654 via a trampoline page in the vector table.
1655
1656 If unsure, say Y.
1657
1658config MITIGATE_SPECTRE_BRANCH_HISTORY
1659 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1660 default y
1661 help
1662 Speculation attacks against some high-performance processors can
1663 make use of branch history to influence future speculation.
1664 When taking an exception from user-space, a sequence of branches
1665 or a firmware call overwrites the branch history.
1666
1667config RODATA_FULL_DEFAULT_ENABLED
1668 bool "Apply r/o permissions of VM areas also to their linear aliases"
1669 default y
1670 help
1671 Apply read-only attributes of VM areas to the linear alias of
1672 the backing pages as well. This prevents code or read-only data
1673 from being modified (inadvertently or intentionally) via another
1674 mapping of the same memory page. This additional enhancement can
1675 be turned off at runtime by passing rodata=[off|on] (and turned on
1676 with rodata=full if this option is set to 'n')
1677
1678 This requires the linear region to be mapped down to pages,
1679 which may adversely affect performance in some cases.
1680
1681config ARM64_SW_TTBR0_PAN
1682 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1683 depends on !KCSAN
1684 help
1685 Enabling this option prevents the kernel from accessing
1686 user-space memory directly by pointing TTBR0_EL1 to a reserved
1687 zeroed area and reserved ASID. The user access routines
1688 restore the valid TTBR0_EL1 temporarily.
1689
1690config ARM64_TAGGED_ADDR_ABI
1691 bool "Enable the tagged user addresses syscall ABI"
1692 default y
1693 help
1694 When this option is enabled, user applications can opt in to a
1695 relaxed ABI via prctl() allowing tagged addresses to be passed
1696 to system calls as pointer arguments. For details, see
1697 Documentation/arch/arm64/tagged-address-abi.rst.
1698
1699menuconfig COMPAT
1700 bool "Kernel support for 32-bit EL0"
1701 depends on ARM64_4K_PAGES || EXPERT
1702 select HAVE_UID16
1703 select OLD_SIGSUSPEND3
1704 select COMPAT_OLD_SIGACTION
1705 help
1706 This option enables support for a 32-bit EL0 running under a 64-bit
1707 kernel at EL1. AArch32-specific components such as system calls,
1708 the user helper functions, VFP support and the ptrace interface are
1709 handled appropriately by the kernel.
1710
1711 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1712 that you will only be able to execute AArch32 binaries that were compiled
1713 with page size aligned segments.
1714
1715 If you want to execute 32-bit userspace applications, say Y.
1716
1717if COMPAT
1718
1719config KUSER_HELPERS
1720 bool "Enable kuser helpers page for 32-bit applications"
1721 default y
1722 help
1723 Warning: disabling this option may break 32-bit user programs.
1724
1725 Provide kuser helpers to compat tasks. The kernel provides
1726 helper code to userspace in read only form at a fixed location
1727 to allow userspace to be independent of the CPU type fitted to
1728 the system. This permits binaries to be run on ARMv4 through
1729 to ARMv8 without modification.
1730
1731 See Documentation/arch/arm/kernel_user_helpers.rst for details.
1732
1733 However, the fixed address nature of these helpers can be used
1734 by ROP (return orientated programming) authors when creating
1735 exploits.
1736
1737 If all of the binaries and libraries which run on your platform
1738 are built specifically for your platform, and make no use of
1739 these helpers, then you can turn this option off to hinder
1740 such exploits. However, in that case, if a binary or library
1741 relying on those helpers is run, it will not function correctly.
1742
1743 Say N here only if you are absolutely certain that you do not
1744 need these helpers; otherwise, the safe option is to say Y.
1745
1746config COMPAT_VDSO
1747 bool "Enable vDSO for 32-bit applications"
1748 depends on !CPU_BIG_ENDIAN
1749 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1750 select GENERIC_COMPAT_VDSO
1751 default y
1752 help
1753 Place in the process address space of 32-bit applications an
1754 ELF shared object providing fast implementations of gettimeofday
1755 and clock_gettime.
1756
1757 You must have a 32-bit build of glibc 2.22 or later for programs
1758 to seamlessly take advantage of this.
1759
1760config THUMB2_COMPAT_VDSO
1761 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1762 depends on COMPAT_VDSO
1763 default y
1764 help
1765 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1766 otherwise with '-marm'.
1767
1768config COMPAT_ALIGNMENT_FIXUPS
1769 bool "Fix up misaligned multi-word loads and stores in user space"
1770
1771menuconfig ARMV8_DEPRECATED
1772 bool "Emulate deprecated/obsolete ARMv8 instructions"
1773 depends on SYSCTL
1774 help
1775 Legacy software support may require certain instructions
1776 that have been deprecated or obsoleted in the architecture.
1777
1778 Enable this config to enable selective emulation of these
1779 features.
1780
1781 If unsure, say Y
1782
1783if ARMV8_DEPRECATED
1784
1785config SWP_EMULATION
1786 bool "Emulate SWP/SWPB instructions"
1787 help
1788 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1789 they are always undefined. Say Y here to enable software
1790 emulation of these instructions for userspace using LDXR/STXR.
1791 This feature can be controlled at runtime with the abi.swp
1792 sysctl which is disabled by default.
1793
1794 In some older versions of glibc [<=2.8] SWP is used during futex
1795 trylock() operations with the assumption that the code will not
1796 be preempted. This invalid assumption may be more likely to fail
1797 with SWP emulation enabled, leading to deadlock of the user
1798 application.
1799
1800 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1801 on an external transaction monitoring block called a global
1802 monitor to maintain update atomicity. If your system does not
1803 implement a global monitor, this option can cause programs that
1804 perform SWP operations to uncached memory to deadlock.
1805
1806 If unsure, say Y
1807
1808config CP15_BARRIER_EMULATION
1809 bool "Emulate CP15 Barrier instructions"
1810 help
1811 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1812 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1813 strongly recommended to use the ISB, DSB, and DMB
1814 instructions instead.
1815
1816 Say Y here to enable software emulation of these
1817 instructions for AArch32 userspace code. When this option is
1818 enabled, CP15 barrier usage is traced which can help
1819 identify software that needs updating. This feature can be
1820 controlled at runtime with the abi.cp15_barrier sysctl.
1821
1822 If unsure, say Y
1823
1824config SETEND_EMULATION
1825 bool "Emulate SETEND instruction"
1826 help
1827 The SETEND instruction alters the data-endianness of the
1828 AArch32 EL0, and is deprecated in ARMv8.
1829
1830 Say Y here to enable software emulation of the instruction
1831 for AArch32 userspace code. This feature can be controlled
1832 at runtime with the abi.setend sysctl.
1833
1834 Note: All the cpus on the system must have mixed endian support at EL0
1835 for this feature to be enabled. If a new CPU - which doesn't support mixed
1836 endian - is hotplugged in after this feature has been enabled, there could
1837 be unexpected results in the applications.
1838
1839 If unsure, say Y
1840endif # ARMV8_DEPRECATED
1841
1842endif # COMPAT
1843
1844menu "ARMv8.1 architectural features"
1845
1846config ARM64_HW_AFDBM
1847 bool "Support for hardware updates of the Access and Dirty page flags"
1848 default y
1849 help
1850 The ARMv8.1 architecture extensions introduce support for
1851 hardware updates of the access and dirty information in page
1852 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1853 capable processors, accesses to pages with PTE_AF cleared will
1854 set this bit instead of raising an access flag fault.
1855 Similarly, writes to read-only pages with the DBM bit set will
1856 clear the read-only bit (AP[2]) instead of raising a
1857 permission fault.
1858
1859 Kernels built with this configuration option enabled continue
1860 to work on pre-ARMv8.1 hardware and the performance impact is
1861 minimal. If unsure, say Y.
1862
1863config ARM64_PAN
1864 bool "Enable support for Privileged Access Never (PAN)"
1865 default y
1866 help
1867 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1868 prevents the kernel or hypervisor from accessing user-space (EL0)
1869 memory directly.
1870
1871 Choosing this option will cause any unprotected (not using
1872 copy_to_user et al) memory access to fail with a permission fault.
1873
1874 The feature is detected at runtime, and will remain as a 'nop'
1875 instruction if the cpu does not implement the feature.
1876
1877config AS_HAS_LSE_ATOMICS
1878 def_bool $(as-instr,.arch_extension lse)
1879
1880config ARM64_LSE_ATOMICS
1881 bool
1882 default ARM64_USE_LSE_ATOMICS
1883 depends on AS_HAS_LSE_ATOMICS
1884
1885config ARM64_USE_LSE_ATOMICS
1886 bool "Atomic instructions"
1887 default y
1888 help
1889 As part of the Large System Extensions, ARMv8.1 introduces new
1890 atomic instructions that are designed specifically to scale in
1891 very large systems.
1892
1893 Say Y here to make use of these instructions for the in-kernel
1894 atomic routines. This incurs a small overhead on CPUs that do
1895 not support these instructions and requires the kernel to be
1896 built with binutils >= 2.25 in order for the new instructions
1897 to be used.
1898
1899endmenu # "ARMv8.1 architectural features"
1900
1901menu "ARMv8.2 architectural features"
1902
1903config AS_HAS_ARMV8_2
1904 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1905
1906config AS_HAS_SHA3
1907 def_bool $(as-instr,.arch armv8.2-a+sha3)
1908
1909config ARM64_PMEM
1910 bool "Enable support for persistent memory"
1911 select ARCH_HAS_PMEM_API
1912 select ARCH_HAS_UACCESS_FLUSHCACHE
1913 help
1914 Say Y to enable support for the persistent memory API based on the
1915 ARMv8.2 DCPoP feature.
1916
1917 The feature is detected at runtime, and the kernel will use DC CVAC
1918 operations if DC CVAP is not supported (following the behaviour of
1919 DC CVAP itself if the system does not define a point of persistence).
1920
1921config ARM64_RAS_EXTN
1922 bool "Enable support for RAS CPU Extensions"
1923 default y
1924 help
1925 CPUs that support the Reliability, Availability and Serviceability
1926 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1927 errors, classify them and report them to software.
1928
1929 On CPUs with these extensions system software can use additional
1930 barriers to determine if faults are pending and read the
1931 classification from a new set of registers.
1932
1933 Selecting this feature will allow the kernel to use these barriers
1934 and access the new registers if the system supports the extension.
1935 Platform RAS features may additionally depend on firmware support.
1936
1937config ARM64_CNP
1938 bool "Enable support for Common Not Private (CNP) translations"
1939 default y
1940 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1941 help
1942 Common Not Private (CNP) allows translation table entries to
1943 be shared between different PEs in the same inner shareable
1944 domain, so the hardware can use this fact to optimise the
1945 caching of such entries in the TLB.
1946
1947 Selecting this option allows the CNP feature to be detected
1948 at runtime, and does not affect PEs that do not implement
1949 this feature.
1950
1951endmenu # "ARMv8.2 architectural features"
1952
1953menu "ARMv8.3 architectural features"
1954
1955config ARM64_PTR_AUTH
1956 bool "Enable support for pointer authentication"
1957 default y
1958 help
1959 Pointer authentication (part of the ARMv8.3 Extensions) provides
1960 instructions for signing and authenticating pointers against secret
1961 keys, which can be used to mitigate Return Oriented Programming (ROP)
1962 and other attacks.
1963
1964 This option enables these instructions at EL0 (i.e. for userspace).
1965 Choosing this option will cause the kernel to initialise secret keys
1966 for each process at exec() time, with these keys being
1967 context-switched along with the process.
1968
1969 The feature is detected at runtime. If the feature is not present in
1970 hardware it will not be advertised to userspace/KVM guest nor will it
1971 be enabled.
1972
1973 If the feature is present on the boot CPU but not on a late CPU, then
1974 the late CPU will be parked. Also, if the boot CPU does not have
1975 address auth and the late CPU has then the late CPU will still boot
1976 but with the feature disabled. On such a system, this option should
1977 not be selected.
1978
1979config ARM64_PTR_AUTH_KERNEL
1980 bool "Use pointer authentication for kernel"
1981 default y
1982 depends on ARM64_PTR_AUTH
1983 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1984 # Modern compilers insert a .note.gnu.property section note for PAC
1985 # which is only understood by binutils starting with version 2.33.1.
1986 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1987 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1988 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1989 help
1990 If the compiler supports the -mbranch-protection or
1991 -msign-return-address flag (e.g. GCC 7 or later), then this option
1992 will cause the kernel itself to be compiled with return address
1993 protection. In this case, and if the target hardware is known to
1994 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1995 disabled with minimal loss of protection.
1996
1997 This feature works with FUNCTION_GRAPH_TRACER option only if
1998 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1999
2000config CC_HAS_BRANCH_PROT_PAC_RET
2001 # GCC 9 or later, clang 8 or later
2002 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2003
2004config CC_HAS_SIGN_RETURN_ADDRESS
2005 # GCC 7, 8
2006 def_bool $(cc-option,-msign-return-address=all)
2007
2008config AS_HAS_ARMV8_3
2009 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2010
2011config AS_HAS_CFI_NEGATE_RA_STATE
2012 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2013
2014config AS_HAS_LDAPR
2015 def_bool $(as-instr,.arch_extension rcpc)
2016
2017endmenu # "ARMv8.3 architectural features"
2018
2019menu "ARMv8.4 architectural features"
2020
2021config ARM64_AMU_EXTN
2022 bool "Enable support for the Activity Monitors Unit CPU extension"
2023 default y
2024 help
2025 The activity monitors extension is an optional extension introduced
2026 by the ARMv8.4 CPU architecture. This enables support for version 1
2027 of the activity monitors architecture, AMUv1.
2028
2029 To enable the use of this extension on CPUs that implement it, say Y.
2030
2031 Note that for architectural reasons, firmware _must_ implement AMU
2032 support when running on CPUs that present the activity monitors
2033 extension. The required support is present in:
2034 * Version 1.5 and later of the ARM Trusted Firmware
2035
2036 For kernels that have this configuration enabled but boot with broken
2037 firmware, you may need to say N here until the firmware is fixed.
2038 Otherwise you may experience firmware panics or lockups when
2039 accessing the counter registers. Even if you are not observing these
2040 symptoms, the values returned by the register reads might not
2041 correctly reflect reality. Most commonly, the value read will be 0,
2042 indicating that the counter is not enabled.
2043
2044config AS_HAS_ARMV8_4
2045 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2046
2047config ARM64_TLB_RANGE
2048 bool "Enable support for tlbi range feature"
2049 default y
2050 depends on AS_HAS_ARMV8_4
2051 help
2052 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2053 range of input addresses.
2054
2055 The feature introduces new assembly instructions, and they were
2056 support when binutils >= 2.30.
2057
2058endmenu # "ARMv8.4 architectural features"
2059
2060menu "ARMv8.5 architectural features"
2061
2062config AS_HAS_ARMV8_5
2063 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2064
2065config ARM64_BTI
2066 bool "Branch Target Identification support"
2067 default y
2068 help
2069 Branch Target Identification (part of the ARMv8.5 Extensions)
2070 provides a mechanism to limit the set of locations to which computed
2071 branch instructions such as BR or BLR can jump.
2072
2073 To make use of BTI on CPUs that support it, say Y.
2074
2075 BTI is intended to provide complementary protection to other control
2076 flow integrity protection mechanisms, such as the Pointer
2077 authentication mechanism provided as part of the ARMv8.3 Extensions.
2078 For this reason, it does not make sense to enable this option without
2079 also enabling support for pointer authentication. Thus, when
2080 enabling this option you should also select ARM64_PTR_AUTH=y.
2081
2082 Userspace binaries must also be specifically compiled to make use of
2083 this mechanism. If you say N here or the hardware does not support
2084 BTI, such binaries can still run, but you get no additional
2085 enforcement of branch destinations.
2086
2087config ARM64_BTI_KERNEL
2088 bool "Use Branch Target Identification for kernel"
2089 default y
2090 depends on ARM64_BTI
2091 depends on ARM64_PTR_AUTH_KERNEL
2092 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2093 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2094 depends on !CC_IS_GCC || GCC_VERSION >= 100100
2095 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2096 depends on !CC_IS_GCC
2097 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2098 help
2099 Build the kernel with Branch Target Identification annotations
2100 and enable enforcement of this for kernel code. When this option
2101 is enabled and the system supports BTI all kernel code including
2102 modular code must have BTI enabled.
2103
2104config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2105 # GCC 9 or later, clang 8 or later
2106 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2107
2108config ARM64_E0PD
2109 bool "Enable support for E0PD"
2110 default y
2111 help
2112 E0PD (part of the ARMv8.5 extensions) allows us to ensure
2113 that EL0 accesses made via TTBR1 always fault in constant time,
2114 providing similar benefits to KASLR as those provided by KPTI, but
2115 with lower overhead and without disrupting legitimate access to
2116 kernel memory such as SPE.
2117
2118 This option enables E0PD for TTBR1 where available.
2119
2120config ARM64_AS_HAS_MTE
2121 # Initial support for MTE went in binutils 2.32.0, checked with
2122 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2123 # as a late addition to the final architecture spec (LDGM/STGM)
2124 # is only supported in the newer 2.32.x and 2.33 binutils
2125 # versions, hence the extra "stgm" instruction check below.
2126 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2127
2128config ARM64_MTE
2129 bool "Memory Tagging Extension support"
2130 default y
2131 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2132 depends on AS_HAS_ARMV8_5
2133 depends on AS_HAS_LSE_ATOMICS
2134 # Required for tag checking in the uaccess routines
2135 depends on ARM64_PAN
2136 select ARCH_HAS_SUBPAGE_FAULTS
2137 select ARCH_USES_HIGH_VMA_FLAGS
2138 select ARCH_USES_PG_ARCH_2
2139 select ARCH_USES_PG_ARCH_3
2140 help
2141 Memory Tagging (part of the ARMv8.5 Extensions) provides
2142 architectural support for run-time, always-on detection of
2143 various classes of memory error to aid with software debugging
2144 to eliminate vulnerabilities arising from memory-unsafe
2145 languages.
2146
2147 This option enables the support for the Memory Tagging
2148 Extension at EL0 (i.e. for userspace).
2149
2150 Selecting this option allows the feature to be detected at
2151 runtime. Any secondary CPU not implementing this feature will
2152 not be allowed a late bring-up.
2153
2154 Userspace binaries that want to use this feature must
2155 explicitly opt in. The mechanism for the userspace is
2156 described in:
2157
2158 Documentation/arch/arm64/memory-tagging-extension.rst.
2159
2160endmenu # "ARMv8.5 architectural features"
2161
2162menu "ARMv8.7 architectural features"
2163
2164config ARM64_EPAN
2165 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2166 default y
2167 depends on ARM64_PAN
2168 help
2169 Enhanced Privileged Access Never (EPAN) allows Privileged
2170 Access Never to be used with Execute-only mappings.
2171
2172 The feature is detected at runtime, and will remain disabled
2173 if the cpu does not implement the feature.
2174endmenu # "ARMv8.7 architectural features"
2175
2176config AS_HAS_MOPS
2177 def_bool $(as-instr,.arch_extension mops)
2178
2179menu "ARMv8.9 architectural features"
2180
2181config ARM64_POE
2182 prompt "Permission Overlay Extension"
2183 def_bool y
2184 select ARCH_USES_HIGH_VMA_FLAGS
2185 select ARCH_HAS_PKEYS
2186 help
2187 The Permission Overlay Extension is used to implement Memory
2188 Protection Keys. Memory Protection Keys provides a mechanism for
2189 enforcing page-based protections, but without requiring modification
2190 of the page tables when an application changes protection domains.
2191
2192 For details, see Documentation/core-api/protection-keys.rst
2193
2194 If unsure, say y.
2195
2196config ARCH_PKEY_BITS
2197 int
2198 default 3
2199
2200config ARM64_HAFT
2201 bool "Support for Hardware managed Access Flag for Table Descriptors"
2202 depends on ARM64_HW_AFDBM
2203 default y
2204 help
2205 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access
2206 Flag for Table descriptors. When enabled an architectural executed
2207 memory access will update the Access Flag in each Table descriptor
2208 which is accessed during the translation table walk and for which
2209 the Access Flag is 0. The Access Flag of the Table descriptor use
2210 the same bit of PTE_AF.
2211
2212 The feature will only be enabled if all the CPUs in the system
2213 support this feature. If unsure, say Y.
2214
2215endmenu # "ARMv8.9 architectural features"
2216
2217menu "v9.4 architectural features"
2218
2219config ARM64_GCS
2220 bool "Enable support for Guarded Control Stack (GCS)"
2221 default y
2222 select ARCH_HAS_USER_SHADOW_STACK
2223 select ARCH_USES_HIGH_VMA_FLAGS
2224 depends on !UPROBES
2225 help
2226 Guarded Control Stack (GCS) provides support for a separate
2227 stack with restricted access which contains only return
2228 addresses. This can be used to harden against some attacks
2229 by comparing return address used by the program with what is
2230 stored in the GCS, and may also be used to efficiently obtain
2231 the call stack for applications such as profiling.
2232
2233 The feature is detected at runtime, and will remain disabled
2234 if the system does not implement the feature.
2235
2236endmenu # "v9.4 architectural features"
2237
2238config ARM64_SVE
2239 bool "ARM Scalable Vector Extension support"
2240 default y
2241 help
2242 The Scalable Vector Extension (SVE) is an extension to the AArch64
2243 execution state which complements and extends the SIMD functionality
2244 of the base architecture to support much larger vectors and to enable
2245 additional vectorisation opportunities.
2246
2247 To enable use of this extension on CPUs that implement it, say Y.
2248
2249 On CPUs that support the SVE2 extensions, this option will enable
2250 those too.
2251
2252 Note that for architectural reasons, firmware _must_ implement SVE
2253 support when running on SVE capable hardware. The required support
2254 is present in:
2255
2256 * version 1.5 and later of the ARM Trusted Firmware
2257 * the AArch64 boot wrapper since commit 5e1261e08abf
2258 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2259
2260 For other firmware implementations, consult the firmware documentation
2261 or vendor.
2262
2263 If you need the kernel to boot on SVE-capable hardware with broken
2264 firmware, you may need to say N here until you get your firmware
2265 fixed. Otherwise, you may experience firmware panics or lockups when
2266 booting the kernel. If unsure and you are not observing these
2267 symptoms, you should assume that it is safe to say Y.
2268
2269config ARM64_SME
2270 bool "ARM Scalable Matrix Extension support"
2271 default y
2272 depends on ARM64_SVE
2273 depends on BROKEN
2274 help
2275 The Scalable Matrix Extension (SME) is an extension to the AArch64
2276 execution state which utilises a substantial subset of the SVE
2277 instruction set, together with the addition of new architectural
2278 register state capable of holding two dimensional matrix tiles to
2279 enable various matrix operations.
2280
2281config ARM64_PSEUDO_NMI
2282 bool "Support for NMI-like interrupts"
2283 select ARM_GIC_V3
2284 help
2285 Adds support for mimicking Non-Maskable Interrupts through the use of
2286 GIC interrupt priority. This support requires version 3 or later of
2287 ARM GIC.
2288
2289 This high priority configuration for interrupts needs to be
2290 explicitly enabled by setting the kernel parameter
2291 "irqchip.gicv3_pseudo_nmi" to 1.
2292
2293 If unsure, say N
2294
2295if ARM64_PSEUDO_NMI
2296config ARM64_DEBUG_PRIORITY_MASKING
2297 bool "Debug interrupt priority masking"
2298 help
2299 This adds runtime checks to functions enabling/disabling
2300 interrupts when using priority masking. The additional checks verify
2301 the validity of ICC_PMR_EL1 when calling concerned functions.
2302
2303 If unsure, say N
2304endif # ARM64_PSEUDO_NMI
2305
2306config RELOCATABLE
2307 bool "Build a relocatable kernel image" if EXPERT
2308 select ARCH_HAS_RELR
2309 default y
2310 help
2311 This builds the kernel as a Position Independent Executable (PIE),
2312 which retains all relocation metadata required to relocate the
2313 kernel binary at runtime to a different virtual address than the
2314 address it was linked at.
2315 Since AArch64 uses the RELA relocation format, this requires a
2316 relocation pass at runtime even if the kernel is loaded at the
2317 same address it was linked at.
2318
2319config RANDOMIZE_BASE
2320 bool "Randomize the address of the kernel image"
2321 select RELOCATABLE
2322 help
2323 Randomizes the virtual address at which the kernel image is
2324 loaded, as a security feature that deters exploit attempts
2325 relying on knowledge of the location of kernel internals.
2326
2327 It is the bootloader's job to provide entropy, by passing a
2328 random u64 value in /chosen/kaslr-seed at kernel entry.
2329
2330 When booting via the UEFI stub, it will invoke the firmware's
2331 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2332 to the kernel proper. In addition, it will randomise the physical
2333 location of the kernel Image as well.
2334
2335 If unsure, say N.
2336
2337config RANDOMIZE_MODULE_REGION_FULL
2338 bool "Randomize the module region over a 2 GB range"
2339 depends on RANDOMIZE_BASE
2340 default y
2341 help
2342 Randomizes the location of the module region inside a 2 GB window
2343 covering the core kernel. This way, it is less likely for modules
2344 to leak information about the location of core kernel data structures
2345 but it does imply that function calls between modules and the core
2346 kernel will need to be resolved via veneers in the module PLT.
2347
2348 When this option is not set, the module region will be randomized over
2349 a limited range that contains the [_stext, _etext] interval of the
2350 core kernel, so branch relocations are almost always in range unless
2351 the region is exhausted. In this particular case of region
2352 exhaustion, modules might be able to fall back to a larger 2GB area.
2353
2354config CC_HAVE_STACKPROTECTOR_SYSREG
2355 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2356
2357config STACKPROTECTOR_PER_TASK
2358 def_bool y
2359 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2360
2361config UNWIND_PATCH_PAC_INTO_SCS
2362 bool "Enable shadow call stack dynamically using code patching"
2363 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated
2364 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2365 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2366 depends on SHADOW_CALL_STACK
2367 select UNWIND_TABLES
2368 select DYNAMIC_SCS
2369
2370config ARM64_CONTPTE
2371 bool "Contiguous PTE mappings for user memory" if EXPERT
2372 depends on TRANSPARENT_HUGEPAGE
2373 default y
2374 help
2375 When enabled, user mappings are configured using the PTE contiguous
2376 bit, for any mappings that meet the size and alignment requirements.
2377 This reduces TLB pressure and improves performance.
2378
2379endmenu # "Kernel Features"
2380
2381menu "Boot options"
2382
2383config ARM64_ACPI_PARKING_PROTOCOL
2384 bool "Enable support for the ARM64 ACPI parking protocol"
2385 depends on ACPI
2386 help
2387 Enable support for the ARM64 ACPI parking protocol. If disabled
2388 the kernel will not allow booting through the ARM64 ACPI parking
2389 protocol even if the corresponding data is present in the ACPI
2390 MADT table.
2391
2392config CMDLINE
2393 string "Default kernel command string"
2394 default ""
2395 help
2396 Provide a set of default command-line options at build time by
2397 entering them here. As a minimum, you should specify the the
2398 root device (e.g. root=/dev/nfs).
2399
2400choice
2401 prompt "Kernel command line type"
2402 depends on CMDLINE != ""
2403 default CMDLINE_FROM_BOOTLOADER
2404 help
2405 Choose how the kernel will handle the provided default kernel
2406 command line string.
2407
2408config CMDLINE_FROM_BOOTLOADER
2409 bool "Use bootloader kernel arguments if available"
2410 help
2411 Uses the command-line options passed by the boot loader. If
2412 the boot loader doesn't provide any, the default kernel command
2413 string provided in CMDLINE will be used.
2414
2415config CMDLINE_FORCE
2416 bool "Always use the default kernel command string"
2417 help
2418 Always use the default kernel command string, even if the boot
2419 loader passes other arguments to the kernel.
2420 This is useful if you cannot or don't want to change the
2421 command-line options your boot loader passes to the kernel.
2422
2423endchoice
2424
2425config EFI_STUB
2426 bool
2427
2428config EFI
2429 bool "UEFI runtime support"
2430 depends on OF && !CPU_BIG_ENDIAN
2431 depends on KERNEL_MODE_NEON
2432 select ARCH_SUPPORTS_ACPI
2433 select LIBFDT
2434 select UCS2_STRING
2435 select EFI_PARAMS_FROM_FDT
2436 select EFI_RUNTIME_WRAPPERS
2437 select EFI_STUB
2438 select EFI_GENERIC_STUB
2439 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2440 default y
2441 help
2442 This option provides support for runtime services provided
2443 by UEFI firmware (such as non-volatile variables, realtime
2444 clock, and platform reset). A UEFI stub is also provided to
2445 allow the kernel to be booted as an EFI application. This
2446 is only useful on systems that have UEFI firmware.
2447
2448config COMPRESSED_INSTALL
2449 bool "Install compressed image by default"
2450 help
2451 This makes the regular "make install" install the compressed
2452 image we built, not the legacy uncompressed one.
2453
2454 You can check that a compressed image works for you by doing
2455 "make zinstall" first, and verifying that everything is fine
2456 in your environment before making "make install" do this for
2457 you.
2458
2459config DMI
2460 bool "Enable support for SMBIOS (DMI) tables"
2461 depends on EFI
2462 default y
2463 help
2464 This enables SMBIOS/DMI feature for systems.
2465
2466 This option is only useful on systems that have UEFI firmware.
2467 However, even with this option, the resultant kernel should
2468 continue to boot on existing non-UEFI platforms.
2469
2470endmenu # "Boot options"
2471
2472menu "Power management options"
2473
2474source "kernel/power/Kconfig"
2475
2476config ARCH_HIBERNATION_POSSIBLE
2477 def_bool y
2478 depends on CPU_PM
2479
2480config ARCH_HIBERNATION_HEADER
2481 def_bool y
2482 depends on HIBERNATION
2483
2484config ARCH_SUSPEND_POSSIBLE
2485 def_bool y
2486
2487endmenu # "Power management options"
2488
2489menu "CPU Power Management"
2490
2491source "drivers/cpuidle/Kconfig"
2492
2493source "drivers/cpufreq/Kconfig"
2494
2495endmenu # "CPU Power Management"
2496
2497source "drivers/acpi/Kconfig"
2498
2499source "arch/arm64/kvm/Kconfig"
2500