1config ARM64
  2	def_bool y
  3	select ACPI_CCA_REQUIRED if ACPI
  4	select ACPI_GENERIC_GSI if ACPI
 
 
  5	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 
 
 
 
 
 
 
  6	select ARCH_HAS_DEVMEM_IS_ALLOWED
  7	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  8	select ARCH_HAS_ELF_RANDOMIZE
 
 
  9	select ARCH_HAS_GCOV_PROFILE_ALL
 10	select ARCH_HAS_SG_CHAIN
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 11	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 12	select ARCH_USE_CMPXCHG_LOCKREF
 
 
 
 
 
 
 13	select ARCH_SUPPORTS_ATOMIC_RMW
 14	select ARCH_WANT_OPTIONAL_GPIOLIB
 15	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 
 
 
 16	select ARCH_WANT_FRAME_POINTERS
 
 17	select ARCH_HAS_UBSAN_SANITIZE_ALL
 18	select ARM_AMBA
 19	select ARM_ARCH_TIMER
 20	select ARM_GIC
 21	select AUDIT_ARCH_COMPAT_GENERIC
 22	select ARM_GIC_V2M if PCI_MSI
 23	select ARM_GIC_V3
 24	select ARM_GIC_V3_ITS if PCI_MSI
 25	select ARM_PSCI_FW
 26	select BUILDTIME_EXTABLE_SORT
 27	select CLONE_BACKWARDS
 28	select COMMON_CLK
 29	select CPU_PM if (SUSPEND || CPU_IDLE)
 
 30	select DCACHE_WORD_ACCESS
 
 31	select EDAC_SUPPORT
 32	select FRAME_POINTER
 33	select GENERIC_ALLOCATOR
 
 34	select GENERIC_CLOCKEVENTS
 35	select GENERIC_CLOCKEVENTS_BROADCAST
 36	select GENERIC_CPU_AUTOPROBE
 
 37	select GENERIC_EARLY_IOREMAP
 38	select GENERIC_IDLE_POLL_SETUP
 
 39	select GENERIC_IRQ_PROBE
 40	select GENERIC_IRQ_SHOW
 41	select GENERIC_IRQ_SHOW_LEVEL
 42	select GENERIC_PCI_IOMAP
 
 43	select GENERIC_SCHED_CLOCK
 44	select GENERIC_SMP_IDLE_THREAD
 45	select GENERIC_STRNCPY_FROM_USER
 46	select GENERIC_STRNLEN_USER
 47	select GENERIC_TIME_VSYSCALL
 
 
 48	select HANDLE_DOMAIN_IRQ
 49	select HARDIRQS_SW_RESEND
 
 
 50	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 51	select HAVE_ARCH_AUDITSYSCALL
 52	select HAVE_ARCH_BITREVERSE
 
 53	select HAVE_ARCH_HUGE_VMAP
 54	select HAVE_ARCH_JUMP_LABEL
 55	select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 
 
 56	select HAVE_ARCH_KGDB
 57	select HAVE_ARCH_MMAP_RND_BITS
 58	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 
 59	select HAVE_ARCH_SECCOMP_FILTER
 
 
 60	select HAVE_ARCH_TRACEHOOK
 61	select HAVE_BPF_JIT
 
 
 
 
 62	select HAVE_C_RECORDMCOUNT
 63	select HAVE_CC_STACKPROTECTOR
 64	select HAVE_CMPXCHG_DOUBLE
 65	select HAVE_CMPXCHG_LOCAL
 
 66	select HAVE_DEBUG_BUGVERBOSE
 67	select HAVE_DEBUG_KMEMLEAK
 68	select HAVE_DMA_API_DEBUG
 69	select HAVE_DMA_CONTIGUOUS
 70	select HAVE_DYNAMIC_FTRACE
 
 
 71	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 
 72	select HAVE_FTRACE_MCOUNT_RECORD
 73	select HAVE_FUNCTION_TRACER
 
 74	select HAVE_FUNCTION_GRAPH_TRACER
 75	select HAVE_GENERIC_DMA_COHERENT
 76	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 77	select HAVE_IRQ_TIME_ACCOUNTING
 78	select HAVE_MEMBLOCK
 79	select HAVE_PATA_PLATFORM
 80	select HAVE_PERF_EVENTS
 81	select HAVE_PERF_REGS
 82	select HAVE_PERF_USER_STACK_DUMP
 83	select HAVE_RCU_TABLE_FREE
 
 
 
 
 
 84	select HAVE_SYSCALL_TRACEPOINTS
 
 
 
 85	select IOMMU_DMA if IOMMU_SUPPORT
 86	select IRQ_DOMAIN
 87	select IRQ_FORCED_THREADING
 88	select MODULES_USE_ELF_RELA
 89	select NO_BOOTMEM
 
 90	select OF
 91	select OF_EARLY_FLATTREE
 92	select OF_RESERVED_MEM
 93	select PERF_USE_VMALLOC
 
 94	select POWER_RESET
 95	select POWER_SUPPLY
 96	select RTC_LIB
 97	select SPARSE_IRQ
 
 98	select SYSCTL_EXCEPTION_TRACE
 99	select HAVE_CONTEXT_TRACKING
100	select HAVE_ARM_SMCCC
101	help
102	  ARM 64-bit (AArch64) Linux support.
103
104config 64BIT
105	def_bool y
106
107config ARCH_PHYS_ADDR_T_64BIT
108	def_bool y
109
110config MMU
111	def_bool y
112
 
 
 
 
 
 
 
 
 
 
 
 
113config ARCH_MMAP_RND_BITS_MIN
114       default 14 if ARM64_64K_PAGES
115       default 16 if ARM64_16K_PAGES
116       default 18
117
118# max bits determined by the following formula:
119#  VA_BITS - PAGE_SHIFT - 3
120config ARCH_MMAP_RND_BITS_MAX
121       default 19 if ARM64_VA_BITS=36
122       default 24 if ARM64_VA_BITS=39
123       default 27 if ARM64_VA_BITS=42
124       default 30 if ARM64_VA_BITS=47
125       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
126       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
127       default 33 if ARM64_VA_BITS=48
128       default 14 if ARM64_64K_PAGES
129       default 16 if ARM64_16K_PAGES
130       default 18
131
132config ARCH_MMAP_RND_COMPAT_BITS_MIN
133       default 7 if ARM64_64K_PAGES
134       default 9 if ARM64_16K_PAGES
135       default 11
136
137config ARCH_MMAP_RND_COMPAT_BITS_MAX
138       default 16
139
140config NO_IOPORT_MAP
141	def_bool y if !PCI
142
143config STACKTRACE_SUPPORT
144	def_bool y
145
146config ILLEGAL_POINTER_VALUE
147	hex
148	default 0xdead000000000000
149
150config LOCKDEP_SUPPORT
151	def_bool y
152
153config TRACE_IRQFLAGS_SUPPORT
154	def_bool y
155
156config RWSEM_XCHGADD_ALGORITHM
157	def_bool y
158
159config GENERIC_BUG
160	def_bool y
161	depends on BUG
162
163config GENERIC_BUG_RELATIVE_POINTERS
164	def_bool y
165	depends on GENERIC_BUG
166
167config GENERIC_HWEIGHT
168	def_bool y
169
170config GENERIC_CSUM
171        def_bool y
172
173config GENERIC_CALIBRATE_DELAY
174	def_bool y
175
176config ZONE_DMA
177	def_bool y
178
179config HAVE_GENERIC_RCU_GUP
180	def_bool y
181
182config ARCH_DMA_ADDR_T_64BIT
183	def_bool y
 
184
185config NEED_DMA_MAP_STATE
186	def_bool y
187
188config NEED_SG_DMA_LENGTH
189	def_bool y
190
191config SMP
192	def_bool y
193
194config SWIOTLB
195	def_bool y
196
197config IOMMU_HELPER
198	def_bool SWIOTLB
199
200config KERNEL_MODE_NEON
201	def_bool y
202
203config FIX_EARLYCON_MEM
204	def_bool y
205
206config PGTABLE_LEVELS
207	int
208	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
209	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
210	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
211	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
212	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
213	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
214
215source "init/Kconfig"
216
217source "kernel/Kconfig.freezer"
218
219source "arch/arm64/Kconfig.platforms"
220
221menu "Bus support"
222
223config PCI
224	bool "PCI support"
225	help
226	  This feature enables support for PCI bus system. If you say Y
227	  here, the kernel will include drivers and infrastructure code
228	  to support PCI bus devices.
229
230config PCI_DOMAINS
231	def_bool PCI
232
233config PCI_DOMAINS_GENERIC
234	def_bool PCI
235
236config PCI_SYSCALL
237	def_bool PCI
238
239source "drivers/pci/Kconfig"
 
 
 
 
 
 
 
 
 
 
 
 
 
240
241endmenu
242
243menu "Kernel Features"
244
245menu "ARM errata workarounds via the alternatives framework"
246
 
 
 
247config ARM64_ERRATUM_826319
248	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
249	default y
 
250	help
251	  This option adds an alternative code sequence to work around ARM
252	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
253	  AXI master interface and an L2 cache.
254
255	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
256	  and is unable to accept a certain write via this interface, it will
257	  not progress on read data presented on the read data channel and the
258	  system can deadlock.
259
260	  The workaround promotes data cache clean instructions to
261	  data cache clean-and-invalidate.
262	  Please note that this does not necessarily enable the workaround,
263	  as it depends on the alternative framework, which will only patch
264	  the kernel if an affected CPU is detected.
265
266	  If unsure, say Y.
267
268config ARM64_ERRATUM_827319
269	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
270	default y
 
271	help
272	  This option adds an alternative code sequence to work around ARM
273	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
274	  master interface and an L2 cache.
275
276	  Under certain conditions this erratum can cause a clean line eviction
277	  to occur at the same time as another transaction to the same address
278	  on the AMBA 5 CHI interface, which can cause data corruption if the
279	  interconnect reorders the two transactions.
280
281	  The workaround promotes data cache clean instructions to
282	  data cache clean-and-invalidate.
283	  Please note that this does not necessarily enable the workaround,
284	  as it depends on the alternative framework, which will only patch
285	  the kernel if an affected CPU is detected.
286
287	  If unsure, say Y.
288
289config ARM64_ERRATUM_824069
290	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
291	default y
 
292	help
293	  This option adds an alternative code sequence to work around ARM
294	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
295	  to a coherent interconnect.
296
297	  If a Cortex-A53 processor is executing a store or prefetch for
298	  write instruction at the same time as a processor in another
299	  cluster is executing a cache maintenance operation to the same
300	  address, then this erratum might cause a clean cache line to be
301	  incorrectly marked as dirty.
302
303	  The workaround promotes data cache clean instructions to
304	  data cache clean-and-invalidate.
305	  Please note that this option does not necessarily enable the
306	  workaround, as it depends on the alternative framework, which will
307	  only patch the kernel if an affected CPU is detected.
308
309	  If unsure, say Y.
310
311config ARM64_ERRATUM_819472
312	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
313	default y
 
314	help
315	  This option adds an alternative code sequence to work around ARM
316	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
317	  present when it is connected to a coherent interconnect.
318
319	  If the processor is executing a load and store exclusive sequence at
320	  the same time as a processor in another cluster is executing a cache
321	  maintenance operation to the same address, then this erratum might
322	  cause data corruption.
323
324	  The workaround promotes data cache clean instructions to
325	  data cache clean-and-invalidate.
326	  Please note that this does not necessarily enable the workaround,
327	  as it depends on the alternative framework, which will only patch
328	  the kernel if an affected CPU is detected.
329
330	  If unsure, say Y.
331
332config ARM64_ERRATUM_832075
333	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
334	default y
335	help
336	  This option adds an alternative code sequence to work around ARM
337	  erratum 832075 on Cortex-A57 parts up to r1p2.
338
339	  Affected Cortex-A57 parts might deadlock when exclusive load/store
340	  instructions to Write-Back memory are mixed with Device loads.
341
342	  The workaround is to promote device loads to use Load-Acquire
343	  semantics.
344	  Please note that this does not necessarily enable the workaround,
345	  as it depends on the alternative framework, which will only patch
346	  the kernel if an affected CPU is detected.
347
348	  If unsure, say Y.
349
350config ARM64_ERRATUM_834220
351	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
352	depends on KVM
353	default y
354	help
355	  This option adds an alternative code sequence to work around ARM
356	  erratum 834220 on Cortex-A57 parts up to r1p2.
357
358	  Affected Cortex-A57 parts might report a Stage 2 translation
359	  fault as the result of a Stage 1 fault for load crossing a
360	  page boundary when there is a permission or device memory
361	  alignment fault at Stage 1 and a translation fault at Stage 2.
362
363	  The workaround is to verify that the Stage 1 translation
364	  doesn't generate a fault before handling the Stage 2 fault.
365	  Please note that this does not necessarily enable the workaround,
366	  as it depends on the alternative framework, which will only patch
367	  the kernel if an affected CPU is detected.
368
369	  If unsure, say Y.
370
371config ARM64_ERRATUM_845719
372	bool "Cortex-A53: 845719: a load might read incorrect data"
373	depends on COMPAT
374	default y
375	help
376	  This option adds an alternative code sequence to work around ARM
377	  erratum 845719 on Cortex-A53 parts up to r0p4.
378
379	  When running a compat (AArch32) userspace on an affected Cortex-A53
380	  part, a load at EL0 from a virtual address that matches the bottom 32
381	  bits of the virtual address used by a recent load at (AArch64) EL1
382	  might return incorrect data.
383
384	  The workaround is to write the contextidr_el1 register on exception
385	  return to a 32-bit task.
386	  Please note that this does not necessarily enable the workaround,
387	  as it depends on the alternative framework, which will only patch
388	  the kernel if an affected CPU is detected.
389
390	  If unsure, say Y.
391
392config ARM64_ERRATUM_843419
393	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
394	depends on MODULES
395	default y
396	select ARM64_MODULE_CMODEL_LARGE
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
397	help
398	  This option builds kernel modules using the large memory model in
399	  order to avoid the use of the ADRP instruction, which can cause
400	  a subsequent memory access to use an incorrect address on Cortex-A53
401	  parts up to r0p4.
402
403	  Note that the kernel itself must be linked with a version of ld
404	  which fixes potentially affected ADRP instructions through the
405	  use of veneers.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
406
407	  If unsure, say Y.
408
409config CAVIUM_ERRATUM_22375
410	bool "Cavium erratum 22375, 24313"
411	default y
412	help
413	  Enable workaround for erratum 22375, 24313.
414
415	  This implements two gicv3-its errata workarounds for ThunderX. Both
416	  with small impact affecting only ITS table allocation.
417
418	    erratum 22375: only alloc 8MB table size
419	    erratum 24313: ignore memory access type
420
421	  The fixes are in ITS initialization and basically ignore memory access
422	  type and table size provided by the TYPER and BASER registers.
423
424	  If unsure, say Y.
425
 
 
 
 
 
 
 
 
 
426config CAVIUM_ERRATUM_23154
427	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
428	default y
429	help
430	  The gicv3 of ThunderX requires a modified version for
431	  reading the IAR status to ensure data synchronization
432	  (access to icc_iar1_el1 is not sync'ed before and after).
433
434	  If unsure, say Y.
435
436config CAVIUM_ERRATUM_27456
437	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
438	default y
439	help
440	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
441	  instructions may cause the icache to become corrupted if it
442	  contains data for a non-current ASID.  The fix is to
443	  invalidate the icache when changing the mm context.
444
445	  If unsure, say Y.
446
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
447endmenu
448
449
450choice
451	prompt "Page size"
452	default ARM64_4K_PAGES
453	help
454	  Page size (translation granule) configuration.
455
456config ARM64_4K_PAGES
457	bool "4KB"
458	help
459	  This feature enables 4KB pages support.
460
461config ARM64_16K_PAGES
462	bool "16KB"
463	help
464	  The system will use 16KB pages support. AArch32 emulation
465	  requires applications compiled with 16K (or a multiple of 16K)
466	  aligned segments.
467
468config ARM64_64K_PAGES
469	bool "64KB"
470	help
471	  This feature enables 64KB pages support (4KB by default)
472	  allowing only two levels of page tables and faster TLB
473	  look-up. AArch32 emulation requires applications compiled
474	  with 64K aligned segments.
475
476endchoice
477
478choice
479	prompt "Virtual address space size"
480	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
481	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
482	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
483	help
484	  Allows choosing one of multiple possible virtual address
485	  space sizes. The level of translation table is determined by
486	  a combination of page size and virtual address space size.
487
488config ARM64_VA_BITS_36
489	bool "36-bit" if EXPERT
490	depends on ARM64_16K_PAGES
491
492config ARM64_VA_BITS_39
493	bool "39-bit"
494	depends on ARM64_4K_PAGES
495
496config ARM64_VA_BITS_42
497	bool "42-bit"
498	depends on ARM64_64K_PAGES
499
500config ARM64_VA_BITS_47
501	bool "47-bit"
502	depends on ARM64_16K_PAGES
503
504config ARM64_VA_BITS_48
505	bool "48-bit"
506
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
507endchoice
508
 
 
 
 
 
 
 
 
 
 
 
 
 
509config ARM64_VA_BITS
510	int
511	default 36 if ARM64_VA_BITS_36
512	default 39 if ARM64_VA_BITS_39
513	default 42 if ARM64_VA_BITS_42
514	default 47 if ARM64_VA_BITS_47
515	default 48 if ARM64_VA_BITS_48
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
516
517config CPU_BIG_ENDIAN
518       bool "Build big-endian kernel"
519       help
520         Say Y if you plan on running a kernel in big-endian mode.
 
 
 
 
 
 
 
 
521
522config SCHED_MC
523	bool "Multi-core scheduler support"
524	help
525	  Multi-core scheduler support improves the CPU scheduler's decision
526	  making when dealing with multi-core CPU chips at a cost of slightly
527	  increased overhead in some places. If unsure say N here.
528
529config SCHED_SMT
530	bool "SMT scheduler support"
531	help
532	  Improves the CPU scheduler's decision making when dealing with
533	  MultiThreading at a cost of slightly increased overhead in some
534	  places. If unsure say N here.
535
536config NR_CPUS
537	int "Maximum number of CPUs (2-4096)"
538	range 2 4096
539	# These have to remain sorted largest to smallest
540	default "64"
541
542config HOTPLUG_CPU
543	bool "Support for hot-pluggable CPUs"
544	select GENERIC_IRQ_MIGRATION
545	help
546	  Say Y here to experiment with turning CPUs off and on.  CPUs
547	  can be controlled through /sys/devices/system/cpu.
548
549source kernel/Kconfig.preempt
550source kernel/Kconfig.hz
 
 
 
 
 
551
552config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 
 
 
 
 
 
 
 
 
 
 
 
 
553	def_bool y
 
554
555config ARCH_HAS_HOLES_MEMORYMODEL
556	def_bool y if SPARSEMEM
 
 
 
 
 
 
 
 
 
 
 
 
 
557
558config ARCH_SPARSEMEM_ENABLE
559	def_bool y
560	select SPARSEMEM_VMEMMAP_ENABLE
561
562config ARCH_SPARSEMEM_DEFAULT
563	def_bool ARCH_SPARSEMEM_ENABLE
564
565config ARCH_SELECT_MEMORY_MODEL
566	def_bool ARCH_SPARSEMEM_ENABLE
567
 
 
 
568config HAVE_ARCH_PFN_VALID
569	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
570
571config HW_PERF_EVENTS
572	def_bool y
573	depends on ARM_PMU
574
575config SYS_SUPPORTS_HUGETLBFS
576	def_bool y
577
578config ARCH_WANT_HUGE_PMD_SHARE
579	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
580
581config HAVE_ARCH_TRANSPARENT_HUGEPAGE
582	def_bool y
583
584config ARCH_HAS_CACHE_LINE_SIZE
585	def_bool y
586
587source "mm/Kconfig"
 
 
 
 
 
588
589config SECCOMP
590	bool "Enable seccomp to safely compute untrusted bytecode"
591	---help---
592	  This kernel feature is useful for number crunching applications
593	  that may need to compute untrusted bytecode during their
594	  execution. By using pipes or other transports made available to
595	  the process as file descriptors supporting the read/write
596	  syscalls, it's possible to isolate those applications in
597	  their own address space using seccomp. Once seccomp is
598	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
599	  and the task is only allowed to execute a few safe syscalls
600	  defined by each seccomp mode.
601
602config PARAVIRT
603	bool "Enable paravirtualization code"
604	help
605	  This changes the kernel so it can modify itself when it is run
606	  under a hypervisor, potentially improving performance significantly
607	  over full virtualization.
608
609config PARAVIRT_TIME_ACCOUNTING
610	bool "Paravirtual steal time accounting"
611	select PARAVIRT
612	default n
613	help
614	  Select this option to enable fine granularity task steal time
615	  accounting. Time spent executing other tasks in parallel with
616	  the current vCPU is discounted from the vCPU power. To account for
617	  that, there can be a small performance impact.
618
619	  If in doubt, say N here.
620
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
621config XEN_DOM0
622	def_bool y
623	depends on XEN
624
625config XEN
626	bool "Xen guest support on ARM64"
627	depends on ARM64 && OF
628	select SWIOTLB_XEN
629	select PARAVIRT
630	help
631	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
632
633config FORCE_MAX_ZONEORDER
634	int
635	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
636	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
637	default "11"
638	help
639	  The kernel memory allocator divides physically contiguous memory
640	  blocks into "zones", where each zone is a power of two number of
641	  pages.  This option selects the largest power of two that the kernel
642	  keeps in the memory allocator.  If you need to allocate very large
643	  blocks of physically contiguous memory, then you may need to
644	  increase this value.
645
646	  This config option is actually maximum order plus one. For example,
647	  a value of 11 means that the largest free memory block is 2^10 pages.
648
649	  We make sure that we can allocate upto a HugePage size for each configuration.
650	  Hence we have :
651		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
652
653	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
654	  4M allocations matching the default size used by generic code.
655
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
656menuconfig ARMV8_DEPRECATED
657	bool "Emulate deprecated/obsolete ARMv8 instructions"
658	depends on COMPAT
659	help
660	  Legacy software support may require certain instructions
661	  that have been deprecated or obsoleted in the architecture.
662
663	  Enable this config to enable selective emulation of these
664	  features.
665
666	  If unsure, say Y
667
668if ARMV8_DEPRECATED
669
670config SWP_EMULATION
671	bool "Emulate SWP/SWPB instructions"
672	help
673	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
674	  they are always undefined. Say Y here to enable software
675	  emulation of these instructions for userspace using LDXR/STXR.
 
 
676
677	  In some older versions of glibc [<=2.8] SWP is used during futex
678	  trylock() operations with the assumption that the code will not
679	  be preempted. This invalid assumption may be more likely to fail
680	  with SWP emulation enabled, leading to deadlock of the user
681	  application.
682
683	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
684	  on an external transaction monitoring block called a global
685	  monitor to maintain update atomicity. If your system does not
686	  implement a global monitor, this option can cause programs that
687	  perform SWP operations to uncached memory to deadlock.
688
689	  If unsure, say Y
690
691config CP15_BARRIER_EMULATION
692	bool "Emulate CP15 Barrier instructions"
693	help
694	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
695	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
696	  strongly recommended to use the ISB, DSB, and DMB
697	  instructions instead.
698
699	  Say Y here to enable software emulation of these
700	  instructions for AArch32 userspace code. When this option is
701	  enabled, CP15 barrier usage is traced which can help
702	  identify software that needs updating.
 
703
704	  If unsure, say Y
705
706config SETEND_EMULATION
707	bool "Emulate SETEND instruction"
708	help
709	  The SETEND instruction alters the data-endianness of the
710	  AArch32 EL0, and is deprecated in ARMv8.
711
712	  Say Y here to enable software emulation of the instruction
713	  for AArch32 userspace code.
 
714
715	  Note: All the cpus on the system must have mixed endian support at EL0
716	  for this feature to be enabled. If a new CPU - which doesn't support mixed
717	  endian - is hotplugged in after this feature has been enabled, there could
718	  be unexpected results in the applications.
719
720	  If unsure, say Y
721endif
722
 
 
723menu "ARMv8.1 architectural features"
724
725config ARM64_HW_AFDBM
726	bool "Support for hardware updates of the Access and Dirty page flags"
727	default y
728	help
729	  The ARMv8.1 architecture extensions introduce support for
730	  hardware updates of the access and dirty information in page
731	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
732	  capable processors, accesses to pages with PTE_AF cleared will
733	  set this bit instead of raising an access flag fault.
734	  Similarly, writes to read-only pages with the DBM bit set will
735	  clear the read-only bit (AP[2]) instead of raising a
736	  permission fault.
737
738	  Kernels built with this configuration option enabled continue
739	  to work on pre-ARMv8.1 hardware and the performance impact is
740	  minimal. If unsure, say Y.
741
742config ARM64_PAN
743	bool "Enable support for Privileged Access Never (PAN)"
744	default y
745	help
746	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
747	 prevents the kernel or hypervisor from accessing user-space (EL0)
748	 memory directly.
749
750	 Choosing this option will cause any unprotected (not using
751	 copy_to_user et al) memory access to fail with a permission fault.
752
753	 The feature is detected at runtime, and will remain as a 'nop'
754	 instruction if the cpu does not implement the feature.
755
756config ARM64_LSE_ATOMICS
 
 
 
 
 
757	bool "Atomic instructions"
 
 
758	help
759	  As part of the Large System Extensions, ARMv8.1 introduces new
760	  atomic instructions that are designed specifically to scale in
761	  very large systems.
762
763	  Say Y here to make use of these instructions for the in-kernel
764	  atomic routines. This incurs a small overhead on CPUs that do
765	  not support these instructions and requires the kernel to be
766	  built with binutils >= 2.25.
 
767
768config ARM64_VHE
769	bool "Enable support for Virtualization Host Extensions (VHE)"
770	default y
771	help
772	  Virtualization Host Extensions (VHE) allow the kernel to run
773	  directly at EL2 (instead of EL1) on processors that support
774	  it. This leads to better performance for KVM, as they reduce
775	  the cost of the world switch.
776
777	  Selecting this option allows the VHE feature to be detected
778	  at runtime, and does not affect processors that do not
779	  implement this feature.
780
781endmenu
782
783menu "ARMv8.2 architectural features"
784
785config ARM64_UAO
786	bool "Enable support for User Access Override (UAO)"
787	default y
788	help
789	  User Access Override (UAO; part of the ARMv8.2 Extensions)
790	  causes the 'unprivileged' variant of the load/store instructions to
791	  be overriden to be privileged.
792
793	  This option changes get_user() and friends to use the 'unprivileged'
794	  variant of the load/store instructions. This ensures that user-space
795	  really did have access to the supplied memory. When addr_limit is
796	  set to kernel memory the UAO bit will be set, allowing privileged
797	  access to kernel memory.
798
799	  Choosing this option will cause copy_to_user() et al to use user-space
800	  memory permissions.
801
802	  The feature is detected at runtime, the kernel will use the
803	  regular load/store instructions if the cpu does not implement the
804	  feature.
805
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
806endmenu
807
808config ARM64_MODULE_CMODEL_LARGE
809	bool
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
810
811config ARM64_MODULE_PLTS
812	bool
813	select ARM64_MODULE_CMODEL_LARGE
814	select HAVE_MOD_ARCH_SPECIFIC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
815
816config RELOCATABLE
817	bool
 
 
818	help
819	  This builds the kernel as a Position Independent Executable (PIE),
820	  which retains all relocation metadata required to relocate the
821	  kernel binary at runtime to a different virtual address than the
822	  address it was linked at.
823	  Since AArch64 uses the RELA relocation format, this requires a
824	  relocation pass at runtime even if the kernel is loaded at the
825	  same address it was linked at.
826
827config RANDOMIZE_BASE
828	bool "Randomize the address of the kernel image"
829	select ARM64_MODULE_PLTS
830	select RELOCATABLE
831	help
832	  Randomizes the virtual address at which the kernel image is
833	  loaded, as a security feature that deters exploit attempts
834	  relying on knowledge of the location of kernel internals.
835
836	  It is the bootloader's job to provide entropy, by passing a
837	  random u64 value in /chosen/kaslr-seed at kernel entry.
838
839	  When booting via the UEFI stub, it will invoke the firmware's
840	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
841	  to the kernel proper. In addition, it will randomise the physical
842	  location of the kernel Image as well.
843
844	  If unsure, say N.
845
846config RANDOMIZE_MODULE_REGION_FULL
847	bool "Randomize the module region independently from the core kernel"
848	depends on RANDOMIZE_BASE
849	default y
850	help
851	  Randomizes the location of the module region without considering the
852	  location of the core kernel. This way, it is impossible for modules
853	  to leak information about the location of core kernel data structures
854	  but it does imply that function calls between modules and the core
855	  kernel will need to be resolved via veneers in the module PLT.
856
857	  When this option is not set, the module region will be randomized over
858	  a limited range that contains the [_stext, _etext] interval of the
859	  core kernel, so branch relocations are always in range.
860
 
 
 
 
 
 
 
861endmenu
862
863menu "Boot options"
864
865config ARM64_ACPI_PARKING_PROTOCOL
866	bool "Enable support for the ARM64 ACPI parking protocol"
867	depends on ACPI
868	help
869	  Enable support for the ARM64 ACPI parking protocol. If disabled
870	  the kernel will not allow booting through the ARM64 ACPI parking
871	  protocol even if the corresponding data is present in the ACPI
872	  MADT table.
873
874config CMDLINE
875	string "Default kernel command string"
876	default ""
877	help
878	  Provide a set of default command-line options at build time by
879	  entering them here. As a minimum, you should specify the the
880	  root device (e.g. root=/dev/nfs).
881
882config CMDLINE_FORCE
883	bool "Always use the default kernel command string"
 
884	help
885	  Always use the default kernel command string, even if the boot
886	  loader passes other arguments to the kernel.
887	  This is useful if you cannot or don't want to change the
888	  command-line options your boot loader passes to the kernel.
889
890config EFI_STUB
891	bool
892
893config EFI
894	bool "UEFI runtime support"
895	depends on OF && !CPU_BIG_ENDIAN
 
 
896	select LIBFDT
897	select UCS2_STRING
898	select EFI_PARAMS_FROM_FDT
899	select EFI_RUNTIME_WRAPPERS
900	select EFI_STUB
901	select EFI_ARMSTUB
902	default y
903	help
904	  This option provides support for runtime services provided
905	  by UEFI firmware (such as non-volatile variables, realtime
906          clock, and platform reset). A UEFI stub is also provided to
907	  allow the kernel to be booted as an EFI application. This
908	  is only useful on systems that have UEFI firmware.
909
910config DMI
911	bool "Enable support for SMBIOS (DMI) tables"
912	depends on EFI
913	default y
914	help
915	  This enables SMBIOS/DMI feature for systems.
916
917	  This option is only useful on systems that have UEFI firmware.
918	  However, even with this option, the resultant kernel should
919	  continue to boot on existing non-UEFI platforms.
920
921endmenu
922
923menu "Userspace binary formats"
924
925source "fs/Kconfig.binfmt"
926
927config COMPAT
928	bool "Kernel support for 32-bit EL0"
929	depends on ARM64_4K_PAGES || EXPERT
930	select COMPAT_BINFMT_ELF
931	select HAVE_UID16
932	select OLD_SIGSUSPEND3
933	select COMPAT_OLD_SIGACTION
934	help
935	  This option enables support for a 32-bit EL0 running under a 64-bit
936	  kernel at EL1. AArch32-specific components such as system calls,
937	  the user helper functions, VFP support and the ptrace interface are
938	  handled appropriately by the kernel.
939
940	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
941	  that you will only be able to execute AArch32 binaries that were compiled
942	  with page size aligned segments.
943
944	  If you want to execute 32-bit userspace applications, say Y.
945
946config SYSVIPC_COMPAT
947	def_bool y
948	depends on COMPAT && SYSVIPC
949
950endmenu
 
 
951
952menu "Power management options"
953
954source "kernel/power/Kconfig"
955
 
 
 
 
 
 
 
 
956config ARCH_SUSPEND_POSSIBLE
957	def_bool y
958
959endmenu
960
961menu "CPU Power Management"
962
963source "drivers/cpuidle/Kconfig"
964
965source "drivers/cpufreq/Kconfig"
966
967endmenu
968
969source "net/Kconfig"
970
971source "drivers/Kconfig"
972
973source "drivers/firmware/Kconfig"
974
975source "drivers/acpi/Kconfig"
976
977source "fs/Kconfig"
978
979source "arch/arm64/kvm/Kconfig"
980
981source "arch/arm64/Kconfig.debug"
982
983source "security/Kconfig"
984
985source "crypto/Kconfig"
986if CRYPTO
987source "arch/arm64/crypto/Kconfig"
988endif
989
990source "lib/Kconfig"

   1# SPDX-License-Identifier: GPL-2.0-only
   2config ARM64
   3	def_bool y
   4	select ACPI_CCA_REQUIRED if ACPI
   5	select ACPI_GENERIC_GSI if ACPI
   6	select ACPI_GTDT if ACPI
   7	select ACPI_IORT if ACPI
   8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   9	select ACPI_MCFG if (ACPI && PCI)
  10	select ACPI_SPCR_TABLE if ACPI
  11	select ACPI_PPTT if ACPI
  12	select ARCH_HAS_DEBUG_WX
  13	select ARCH_BINFMT_ELF_STATE
  14	select ARCH_HAS_DEBUG_VIRTUAL
  15	select ARCH_HAS_DEBUG_VM_PGTABLE
  16	select ARCH_HAS_DEVMEM_IS_ALLOWED
  17	select ARCH_HAS_DMA_PREP_COHERENT
  18	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
  19	select ARCH_HAS_FAST_MULTIPLIER
  20	select ARCH_HAS_FORTIFY_SOURCE
  21	select ARCH_HAS_GCOV_PROFILE_ALL
  22	select ARCH_HAS_GIGANTIC_PAGE
  23	select ARCH_HAS_KCOV
  24	select ARCH_HAS_KEEPINITRD
  25	select ARCH_HAS_MEMBARRIER_SYNC_CORE
  26	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
  27	select ARCH_HAS_PTE_DEVMAP
  28	select ARCH_HAS_PTE_SPECIAL
  29	select ARCH_HAS_SETUP_DMA_OPS
  30	select ARCH_HAS_SET_DIRECT_MAP
  31	select ARCH_HAS_SET_MEMORY
  32	select ARCH_HAS_STRICT_KERNEL_RWX
  33	select ARCH_HAS_STRICT_MODULE_RWX
  34	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  35	select ARCH_HAS_SYNC_DMA_FOR_CPU
  36	select ARCH_HAS_SYSCALL_WRAPPER
  37	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
  38	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  39	select ARCH_HAVE_ELF_PROT
  40	select ARCH_HAVE_NMI_SAFE_CMPXCHG
  41	select ARCH_INLINE_READ_LOCK if !PREEMPTION
  42	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
  43	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
  44	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
  45	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
  46	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
  47	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
  48	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
  49	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
  50	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
  51	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
  52	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
  53	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
  54	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
  55	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
  56	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
  57	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
  58	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
  59	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
  60	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
  61	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
  62	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
  63	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
  64	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
  65	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
  66	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
  67	select ARCH_KEEP_MEMBLOCK
  68	select ARCH_USE_CMPXCHG_LOCKREF
  69	select ARCH_USE_GNU_PROPERTY
  70	select ARCH_USE_QUEUED_RWLOCKS
  71	select ARCH_USE_QUEUED_SPINLOCKS
  72	select ARCH_USE_SYM_ANNOTATIONS
  73	select ARCH_SUPPORTS_MEMORY_FAILURE
  74	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
  75	select ARCH_SUPPORTS_ATOMIC_RMW
  76	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
  77	select ARCH_SUPPORTS_NUMA_BALANCING
  78	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
  79	select ARCH_WANT_DEFAULT_BPF_JIT
  80	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
  81	select ARCH_WANT_FRAME_POINTERS
  82	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
  83	select ARCH_HAS_UBSAN_SANITIZE_ALL
  84	select ARM_AMBA
  85	select ARM_ARCH_TIMER
  86	select ARM_GIC
  87	select AUDIT_ARCH_COMPAT_GENERIC
  88	select ARM_GIC_V2M if PCI
  89	select ARM_GIC_V3
  90	select ARM_GIC_V3_ITS if PCI
  91	select ARM_PSCI_FW
  92	select BUILDTIME_TABLE_SORT
  93	select CLONE_BACKWARDS
  94	select COMMON_CLK
  95	select CPU_PM if (SUSPEND || CPU_IDLE)
  96	select CRC32
  97	select DCACHE_WORD_ACCESS
  98	select DMA_DIRECT_REMAP
  99	select EDAC_SUPPORT
 100	select FRAME_POINTER
 101	select GENERIC_ALLOCATOR
 102	select GENERIC_ARCH_TOPOLOGY
 103	select GENERIC_CLOCKEVENTS
 104	select GENERIC_CLOCKEVENTS_BROADCAST
 105	select GENERIC_CPU_AUTOPROBE
 106	select GENERIC_CPU_VULNERABILITIES
 107	select GENERIC_EARLY_IOREMAP
 108	select GENERIC_IDLE_POLL_SETUP
 109	select GENERIC_IRQ_MULTI_HANDLER
 110	select GENERIC_IRQ_PROBE
 111	select GENERIC_IRQ_SHOW
 112	select GENERIC_IRQ_SHOW_LEVEL
 113	select GENERIC_PCI_IOMAP
 114	select GENERIC_PTDUMP
 115	select GENERIC_SCHED_CLOCK
 116	select GENERIC_SMP_IDLE_THREAD
 117	select GENERIC_STRNCPY_FROM_USER
 118	select GENERIC_STRNLEN_USER
 119	select GENERIC_TIME_VSYSCALL
 120	select GENERIC_GETTIMEOFDAY
 121	select GENERIC_VDSO_TIME_NS
 122	select HANDLE_DOMAIN_IRQ
 123	select HARDIRQS_SW_RESEND
 124	select HAVE_PCI
 125	select HAVE_ACPI_APEI if (ACPI && EFI)
 126	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 127	select HAVE_ARCH_AUDITSYSCALL
 128	select HAVE_ARCH_BITREVERSE
 129	select HAVE_ARCH_COMPILER_H
 130	select HAVE_ARCH_HUGE_VMAP
 131	select HAVE_ARCH_JUMP_LABEL
 132	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 133	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 134	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
 135	select HAVE_ARCH_KGDB
 136	select HAVE_ARCH_MMAP_RND_BITS
 137	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 138	select HAVE_ARCH_PREL32_RELOCATIONS
 139	select HAVE_ARCH_SECCOMP_FILTER
 140	select HAVE_ARCH_STACKLEAK
 141	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 142	select HAVE_ARCH_TRACEHOOK
 143	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 144	select HAVE_ARCH_VMAP_STACK
 145	select HAVE_ARM_SMCCC
 146	select HAVE_ASM_MODVERSIONS
 147	select HAVE_EBPF_JIT
 148	select HAVE_C_RECORDMCOUNT
 
 149	select HAVE_CMPXCHG_DOUBLE
 150	select HAVE_CMPXCHG_LOCAL
 151	select HAVE_CONTEXT_TRACKING
 152	select HAVE_DEBUG_BUGVERBOSE
 153	select HAVE_DEBUG_KMEMLEAK
 
 154	select HAVE_DMA_CONTIGUOUS
 155	select HAVE_DYNAMIC_FTRACE
 156	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
 157		if $(cc-option,-fpatchable-function-entry=2)
 158	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 159	select HAVE_FAST_GUP
 160	select HAVE_FTRACE_MCOUNT_RECORD
 161	select HAVE_FUNCTION_TRACER
 162	select HAVE_FUNCTION_ERROR_INJECTION
 163	select HAVE_FUNCTION_GRAPH_TRACER
 164	select HAVE_GCC_PLUGINS
 165	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 166	select HAVE_IRQ_TIME_ACCOUNTING
 167	select HAVE_NMI
 168	select HAVE_PATA_PLATFORM
 169	select HAVE_PERF_EVENTS
 170	select HAVE_PERF_REGS
 171	select HAVE_PERF_USER_STACK_DUMP
 172	select HAVE_REGS_AND_STACK_ACCESS_API
 173	select HAVE_FUNCTION_ARG_ACCESS_API
 174	select HAVE_FUTEX_CMPXCHG if FUTEX
 175	select MMU_GATHER_RCU_TABLE_FREE
 176	select HAVE_RSEQ
 177	select HAVE_STACKPROTECTOR
 178	select HAVE_SYSCALL_TRACEPOINTS
 179	select HAVE_KPROBES
 180	select HAVE_KRETPROBES
 181	select HAVE_GENERIC_VDSO
 182	select IOMMU_DMA if IOMMU_SUPPORT
 183	select IRQ_DOMAIN
 184	select IRQ_FORCED_THREADING
 185	select MODULES_USE_ELF_RELA
 186	select NEED_DMA_MAP_STATE
 187	select NEED_SG_DMA_LENGTH
 188	select OF
 189	select OF_EARLY_FLATTREE
 190	select PCI_DOMAINS_GENERIC if PCI
 191	select PCI_ECAM if (ACPI && PCI)
 192	select PCI_SYSCALL if PCI
 193	select POWER_RESET
 194	select POWER_SUPPLY
 
 195	select SPARSE_IRQ
 196	select SWIOTLB
 197	select SYSCTL_EXCEPTION_TRACE
 198	select THREAD_INFO_IN_TASK
 
 199	help
 200	  ARM 64-bit (AArch64) Linux support.
 201
 202config 64BIT
 203	def_bool y
 204
 
 
 
 205config MMU
 206	def_bool y
 207
 208config ARM64_PAGE_SHIFT
 209	int
 210	default 16 if ARM64_64K_PAGES
 211	default 14 if ARM64_16K_PAGES
 212	default 12
 213
 214config ARM64_CONT_SHIFT
 215	int
 216	default 5 if ARM64_64K_PAGES
 217	default 7 if ARM64_16K_PAGES
 218	default 4
 219
 220config ARCH_MMAP_RND_BITS_MIN
 221       default 14 if ARM64_64K_PAGES
 222       default 16 if ARM64_16K_PAGES
 223       default 18
 224
 225# max bits determined by the following formula:
 226#  VA_BITS - PAGE_SHIFT - 3
 227config ARCH_MMAP_RND_BITS_MAX
 228       default 19 if ARM64_VA_BITS=36
 229       default 24 if ARM64_VA_BITS=39
 230       default 27 if ARM64_VA_BITS=42
 231       default 30 if ARM64_VA_BITS=47
 232       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 233       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 234       default 33 if ARM64_VA_BITS=48
 235       default 14 if ARM64_64K_PAGES
 236       default 16 if ARM64_16K_PAGES
 237       default 18
 238
 239config ARCH_MMAP_RND_COMPAT_BITS_MIN
 240       default 7 if ARM64_64K_PAGES
 241       default 9 if ARM64_16K_PAGES
 242       default 11
 243
 244config ARCH_MMAP_RND_COMPAT_BITS_MAX
 245       default 16
 246
 247config NO_IOPORT_MAP
 248	def_bool y if !PCI
 249
 250config STACKTRACE_SUPPORT
 251	def_bool y
 252
 253config ILLEGAL_POINTER_VALUE
 254	hex
 255	default 0xdead000000000000
 256
 257config LOCKDEP_SUPPORT
 258	def_bool y
 259
 260config TRACE_IRQFLAGS_SUPPORT
 261	def_bool y
 262
 
 
 
 263config GENERIC_BUG
 264	def_bool y
 265	depends on BUG
 266
 267config GENERIC_BUG_RELATIVE_POINTERS
 268	def_bool y
 269	depends on GENERIC_BUG
 270
 271config GENERIC_HWEIGHT
 272	def_bool y
 273
 274config GENERIC_CSUM
 275        def_bool y
 276
 277config GENERIC_CALIBRATE_DELAY
 278	def_bool y
 279
 280config ZONE_DMA
 281	bool "Support DMA zone" if EXPERT
 282	default y
 
 
 283
 284config ZONE_DMA32
 285	bool "Support DMA32 zone" if EXPERT
 286	default y
 287
 288config ARCH_ENABLE_MEMORY_HOTPLUG
 289	def_bool y
 290
 291config ARCH_ENABLE_MEMORY_HOTREMOVE
 292	def_bool y
 293
 294config SMP
 295	def_bool y
 296
 
 
 
 
 
 
 297config KERNEL_MODE_NEON
 298	def_bool y
 299
 300config FIX_EARLYCON_MEM
 301	def_bool y
 302
 303config PGTABLE_LEVELS
 304	int
 305	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 306	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 307	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
 308	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 309	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 310	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 311
 312config ARCH_SUPPORTS_UPROBES
 313	def_bool y
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 314
 315config ARCH_PROC_KCORE_TEXT
 316	def_bool y
 317
 318config BROKEN_GAS_INST
 319	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
 320
 321config KASAN_SHADOW_OFFSET
 322	hex
 323	depends on KASAN
 324	default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
 325	default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
 326	default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
 327	default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
 328	default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
 329	default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
 330	default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
 331	default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
 332	default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
 333	default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
 334	default 0xffffffffffffffff
 335
 336source "arch/arm64/Kconfig.platforms"
 337
 338menu "Kernel Features"
 339
 340menu "ARM errata workarounds via the alternatives framework"
 341
 342config ARM64_WORKAROUND_CLEAN_CACHE
 343	bool
 344
 345config ARM64_ERRATUM_826319
 346	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 347	default y
 348	select ARM64_WORKAROUND_CLEAN_CACHE
 349	help
 350	  This option adds an alternative code sequence to work around ARM
 351	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 352	  AXI master interface and an L2 cache.
 353
 354	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 355	  and is unable to accept a certain write via this interface, it will
 356	  not progress on read data presented on the read data channel and the
 357	  system can deadlock.
 358
 359	  The workaround promotes data cache clean instructions to
 360	  data cache clean-and-invalidate.
 361	  Please note that this does not necessarily enable the workaround,
 362	  as it depends on the alternative framework, which will only patch
 363	  the kernel if an affected CPU is detected.
 364
 365	  If unsure, say Y.
 366
 367config ARM64_ERRATUM_827319
 368	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 369	default y
 370	select ARM64_WORKAROUND_CLEAN_CACHE
 371	help
 372	  This option adds an alternative code sequence to work around ARM
 373	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 374	  master interface and an L2 cache.
 375
 376	  Under certain conditions this erratum can cause a clean line eviction
 377	  to occur at the same time as another transaction to the same address
 378	  on the AMBA 5 CHI interface, which can cause data corruption if the
 379	  interconnect reorders the two transactions.
 380
 381	  The workaround promotes data cache clean instructions to
 382	  data cache clean-and-invalidate.
 383	  Please note that this does not necessarily enable the workaround,
 384	  as it depends on the alternative framework, which will only patch
 385	  the kernel if an affected CPU is detected.
 386
 387	  If unsure, say Y.
 388
 389config ARM64_ERRATUM_824069
 390	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 391	default y
 392	select ARM64_WORKAROUND_CLEAN_CACHE
 393	help
 394	  This option adds an alternative code sequence to work around ARM
 395	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 396	  to a coherent interconnect.
 397
 398	  If a Cortex-A53 processor is executing a store or prefetch for
 399	  write instruction at the same time as a processor in another
 400	  cluster is executing a cache maintenance operation to the same
 401	  address, then this erratum might cause a clean cache line to be
 402	  incorrectly marked as dirty.
 403
 404	  The workaround promotes data cache clean instructions to
 405	  data cache clean-and-invalidate.
 406	  Please note that this option does not necessarily enable the
 407	  workaround, as it depends on the alternative framework, which will
 408	  only patch the kernel if an affected CPU is detected.
 409
 410	  If unsure, say Y.
 411
 412config ARM64_ERRATUM_819472
 413	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 414	default y
 415	select ARM64_WORKAROUND_CLEAN_CACHE
 416	help
 417	  This option adds an alternative code sequence to work around ARM
 418	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 419	  present when it is connected to a coherent interconnect.
 420
 421	  If the processor is executing a load and store exclusive sequence at
 422	  the same time as a processor in another cluster is executing a cache
 423	  maintenance operation to the same address, then this erratum might
 424	  cause data corruption.
 425
 426	  The workaround promotes data cache clean instructions to
 427	  data cache clean-and-invalidate.
 428	  Please note that this does not necessarily enable the workaround,
 429	  as it depends on the alternative framework, which will only patch
 430	  the kernel if an affected CPU is detected.
 431
 432	  If unsure, say Y.
 433
 434config ARM64_ERRATUM_832075
 435	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 436	default y
 437	help
 438	  This option adds an alternative code sequence to work around ARM
 439	  erratum 832075 on Cortex-A57 parts up to r1p2.
 440
 441	  Affected Cortex-A57 parts might deadlock when exclusive load/store
 442	  instructions to Write-Back memory are mixed with Device loads.
 443
 444	  The workaround is to promote device loads to use Load-Acquire
 445	  semantics.
 446	  Please note that this does not necessarily enable the workaround,
 447	  as it depends on the alternative framework, which will only patch
 448	  the kernel if an affected CPU is detected.
 449
 450	  If unsure, say Y.
 451
 452config ARM64_ERRATUM_834220
 453	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 454	depends on KVM
 455	default y
 456	help
 457	  This option adds an alternative code sequence to work around ARM
 458	  erratum 834220 on Cortex-A57 parts up to r1p2.
 459
 460	  Affected Cortex-A57 parts might report a Stage 2 translation
 461	  fault as the result of a Stage 1 fault for load crossing a
 462	  page boundary when there is a permission or device memory
 463	  alignment fault at Stage 1 and a translation fault at Stage 2.
 464
 465	  The workaround is to verify that the Stage 1 translation
 466	  doesn't generate a fault before handling the Stage 2 fault.
 467	  Please note that this does not necessarily enable the workaround,
 468	  as it depends on the alternative framework, which will only patch
 469	  the kernel if an affected CPU is detected.
 470
 471	  If unsure, say Y.
 472
 473config ARM64_ERRATUM_845719
 474	bool "Cortex-A53: 845719: a load might read incorrect data"
 475	depends on COMPAT
 476	default y
 477	help
 478	  This option adds an alternative code sequence to work around ARM
 479	  erratum 845719 on Cortex-A53 parts up to r0p4.
 480
 481	  When running a compat (AArch32) userspace on an affected Cortex-A53
 482	  part, a load at EL0 from a virtual address that matches the bottom 32
 483	  bits of the virtual address used by a recent load at (AArch64) EL1
 484	  might return incorrect data.
 485
 486	  The workaround is to write the contextidr_el1 register on exception
 487	  return to a 32-bit task.
 488	  Please note that this does not necessarily enable the workaround,
 489	  as it depends on the alternative framework, which will only patch
 490	  the kernel if an affected CPU is detected.
 491
 492	  If unsure, say Y.
 493
 494config ARM64_ERRATUM_843419
 495	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 
 496	default y
 497	select ARM64_MODULE_PLTS if MODULES
 498	help
 499	  This option links the kernel with '--fix-cortex-a53-843419' and
 500	  enables PLT support to replace certain ADRP instructions, which can
 501	  cause subsequent memory accesses to use an incorrect address on
 502	  Cortex-A53 parts up to r0p4.
 503
 504	  If unsure, say Y.
 505
 506config ARM64_ERRATUM_1024718
 507	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
 508	default y
 509	help
 510	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 511
 512	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
 513	  update of the hardware dirty bit when the DBM/AP bits are updated
 514	  without a break-before-make. The workaround is to disable the usage
 515	  of hardware DBM locally on the affected cores. CPUs not affected by
 516	  this erratum will continue to use the feature.
 517
 518	  If unsure, say Y.
 519
 520config ARM64_ERRATUM_1418040
 521	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
 522	default y
 523	depends on COMPAT
 524	help
 525	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
 526	  errata 1188873 and 1418040.
 527
 528	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
 529	  cause register corruption when accessing the timer registers
 530	  from AArch32 userspace.
 531
 532	  If unsure, say Y.
 533
 534config ARM64_WORKAROUND_SPECULATIVE_AT
 535	bool
 536
 537config ARM64_ERRATUM_1165522
 538	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 539	default y
 540	select ARM64_WORKAROUND_SPECULATIVE_AT
 541	help
 542	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
 543
 544	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
 545	  corrupted TLBs by speculating an AT instruction during a guest
 546	  context switch.
 547
 548	  If unsure, say Y.
 549
 550config ARM64_ERRATUM_1319367
 551	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 552	default y
 553	select ARM64_WORKAROUND_SPECULATIVE_AT
 554	help
 555	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
 556	  and A72 erratum 1319367
 557
 558	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
 559	  speculating an AT instruction during a guest context switch.
 560
 561	  If unsure, say Y.
 562
 563config ARM64_ERRATUM_1530923
 564	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 565	default y
 566	select ARM64_WORKAROUND_SPECULATIVE_AT
 567	help
 568	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
 569
 570	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
 571	  corrupted TLBs by speculating an AT instruction during a guest
 572	  context switch.
 573
 574	  If unsure, say Y.
 575
 576config ARM64_WORKAROUND_REPEAT_TLBI
 577	bool
 578
 579config ARM64_ERRATUM_1286807
 580	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
 581	default y
 582	select ARM64_WORKAROUND_REPEAT_TLBI
 583	help
 584	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
 585
 586	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
 587	  address for a cacheable mapping of a location is being
 588	  accessed by a core while another core is remapping the virtual
 589	  address to a new physical page using the recommended
 590	  break-before-make sequence, then under very rare circumstances
 591	  TLBI+DSB completes before a read using the translation being
 592	  invalidated has been observed by other observers. The
 593	  workaround repeats the TLBI+DSB operation.
 594
 595config ARM64_ERRATUM_1463225
 596	bool "Cortex-A76: Software Step might prevent interrupt recognition"
 597	default y
 598	help
 599	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
 600
 601	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
 602	  of a system call instruction (SVC) can prevent recognition of
 603	  subsequent interrupts when software stepping is disabled in the
 604	  exception handler of the system call and either kernel debugging
 605	  is enabled or VHE is in use.
 606
 607	  Work around the erratum by triggering a dummy step exception
 608	  when handling a system call from a task that is being stepped
 609	  in a VHE configuration of the kernel.
 610
 611	  If unsure, say Y.
 612
 613config ARM64_ERRATUM_1542419
 614	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
 615	default y
 616	help
 617	  This option adds a workaround for ARM Neoverse-N1 erratum
 618	  1542419.
 619
 620	  Affected Neoverse-N1 cores could execute a stale instruction when
 621	  modified by another CPU. The workaround depends on a firmware
 622	  counterpart.
 623
 624	  Workaround the issue by hiding the DIC feature from EL0. This
 625	  forces user-space to perform cache maintenance.
 626
 627	  If unsure, say Y.
 628
 629config CAVIUM_ERRATUM_22375
 630	bool "Cavium erratum 22375, 24313"
 631	default y
 632	help
 633	  Enable workaround for errata 22375 and 24313.
 634
 635	  This implements two gicv3-its errata workarounds for ThunderX. Both
 636	  with a small impact affecting only ITS table allocation.
 637
 638	    erratum 22375: only alloc 8MB table size
 639	    erratum 24313: ignore memory access type
 640
 641	  The fixes are in ITS initialization and basically ignore memory access
 642	  type and table size provided by the TYPER and BASER registers.
 643
 644	  If unsure, say Y.
 645
 646config CAVIUM_ERRATUM_23144
 647	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
 648	depends on NUMA
 649	default y
 650	help
 651	  ITS SYNC command hang for cross node io and collections/cpu mapping.
 652
 653	  If unsure, say Y.
 654
 655config CAVIUM_ERRATUM_23154
 656	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 657	default y
 658	help
 659	  The gicv3 of ThunderX requires a modified version for
 660	  reading the IAR status to ensure data synchronization
 661	  (access to icc_iar1_el1 is not sync'ed before and after).
 662
 663	  If unsure, say Y.
 664
 665config CAVIUM_ERRATUM_27456
 666	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 667	default y
 668	help
 669	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 670	  instructions may cause the icache to become corrupted if it
 671	  contains data for a non-current ASID.  The fix is to
 672	  invalidate the icache when changing the mm context.
 673
 674	  If unsure, say Y.
 675
 676config CAVIUM_ERRATUM_30115
 677	bool "Cavium erratum 30115: Guest may disable interrupts in host"
 678	default y
 679	help
 680	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
 681	  1.2, and T83 Pass 1.0, KVM guest execution may disable
 682	  interrupts in host. Trapping both GICv3 group-0 and group-1
 683	  accesses sidesteps the issue.
 684
 685	  If unsure, say Y.
 686
 687config CAVIUM_TX2_ERRATUM_219
 688	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
 689	default y
 690	help
 691	  On Cavium ThunderX2, a load, store or prefetch instruction between a
 692	  TTBR update and the corresponding context synchronizing operation can
 693	  cause a spurious Data Abort to be delivered to any hardware thread in
 694	  the CPU core.
 695
 696	  Work around the issue by avoiding the problematic code sequence and
 697	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
 698	  trap handler performs the corresponding register access, skips the
 699	  instruction and ensures context synchronization by virtue of the
 700	  exception return.
 701
 702	  If unsure, say Y.
 703
 704config FUJITSU_ERRATUM_010001
 705	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
 706	default y
 707	help
 708	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
 709	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
 710	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
 711	  This fault occurs under a specific hardware condition when a
 712	  load/store instruction performs an address translation using:
 713	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
 714	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
 715	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
 716	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
 717
 718	  The workaround is to ensure these bits are clear in TCR_ELx.
 719	  The workaround only affects the Fujitsu-A64FX.
 720
 721	  If unsure, say Y.
 722
 723config HISILICON_ERRATUM_161600802
 724	bool "Hip07 161600802: Erroneous redistributor VLPI base"
 725	default y
 726	help
 727	  The HiSilicon Hip07 SoC uses the wrong redistributor base
 728	  when issued ITS commands such as VMOVP and VMAPP, and requires
 729	  a 128kB offset to be applied to the target address in this commands.
 730
 731	  If unsure, say Y.
 732
 733config QCOM_FALKOR_ERRATUM_1003
 734	bool "Falkor E1003: Incorrect translation due to ASID change"
 735	default y
 736	help
 737	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
 738	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
 739	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
 740	  then only for entries in the walk cache, since the leaf translation
 741	  is unchanged. Work around the erratum by invalidating the walk cache
 742	  entries for the trampoline before entering the kernel proper.
 743
 744config QCOM_FALKOR_ERRATUM_1009
 745	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
 746	default y
 747	select ARM64_WORKAROUND_REPEAT_TLBI
 748	help
 749	  On Falkor v1, the CPU may prematurely complete a DSB following a
 750	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
 751	  one more time to fix the issue.
 752
 753	  If unsure, say Y.
 754
 755config QCOM_QDF2400_ERRATUM_0065
 756	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
 757	default y
 758	help
 759	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
 760	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
 761	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
 762
 763	  If unsure, say Y.
 764
 765config QCOM_FALKOR_ERRATUM_E1041
 766	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
 767	default y
 768	help
 769	  Falkor CPU may speculatively fetch instructions from an improper
 770	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
 771	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
 772
 773	  If unsure, say Y.
 774
 775config SOCIONEXT_SYNQUACER_PREITS
 776	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
 777	default y
 778	help
 779	  Socionext Synquacer SoCs implement a separate h/w block to generate
 780	  MSI doorbell writes with non-zero values for the device ID.
 781
 782	  If unsure, say Y.
 783
 784endmenu
 785
 786
 787choice
 788	prompt "Page size"
 789	default ARM64_4K_PAGES
 790	help
 791	  Page size (translation granule) configuration.
 792
 793config ARM64_4K_PAGES
 794	bool "4KB"
 795	help
 796	  This feature enables 4KB pages support.
 797
 798config ARM64_16K_PAGES
 799	bool "16KB"
 800	help
 801	  The system will use 16KB pages support. AArch32 emulation
 802	  requires applications compiled with 16K (or a multiple of 16K)
 803	  aligned segments.
 804
 805config ARM64_64K_PAGES
 806	bool "64KB"
 807	help
 808	  This feature enables 64KB pages support (4KB by default)
 809	  allowing only two levels of page tables and faster TLB
 810	  look-up. AArch32 emulation requires applications compiled
 811	  with 64K aligned segments.
 812
 813endchoice
 814
 815choice
 816	prompt "Virtual address space size"
 817	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 818	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 819	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 820	help
 821	  Allows choosing one of multiple possible virtual address
 822	  space sizes. The level of translation table is determined by
 823	  a combination of page size and virtual address space size.
 824
 825config ARM64_VA_BITS_36
 826	bool "36-bit" if EXPERT
 827	depends on ARM64_16K_PAGES
 828
 829config ARM64_VA_BITS_39
 830	bool "39-bit"
 831	depends on ARM64_4K_PAGES
 832
 833config ARM64_VA_BITS_42
 834	bool "42-bit"
 835	depends on ARM64_64K_PAGES
 836
 837config ARM64_VA_BITS_47
 838	bool "47-bit"
 839	depends on ARM64_16K_PAGES
 840
 841config ARM64_VA_BITS_48
 842	bool "48-bit"
 843
 844config ARM64_VA_BITS_52
 845	bool "52-bit"
 846	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
 847	help
 848	  Enable 52-bit virtual addressing for userspace when explicitly
 849	  requested via a hint to mmap(). The kernel will also use 52-bit
 850	  virtual addresses for its own mappings (provided HW support for
 851	  this feature is available, otherwise it reverts to 48-bit).
 852
 853	  NOTE: Enabling 52-bit virtual addressing in conjunction with
 854	  ARMv8.3 Pointer Authentication will result in the PAC being
 855	  reduced from 7 bits to 3 bits, which may have a significant
 856	  impact on its susceptibility to brute-force attacks.
 857
 858	  If unsure, select 48-bit virtual addressing instead.
 859
 860endchoice
 861
 862config ARM64_FORCE_52BIT
 863	bool "Force 52-bit virtual addresses for userspace"
 864	depends on ARM64_VA_BITS_52 && EXPERT
 865	help
 866	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
 867	  to maintain compatibility with older software by providing 48-bit VAs
 868	  unless a hint is supplied to mmap.
 869
 870	  This configuration option disables the 48-bit compatibility logic, and
 871	  forces all userspace addresses to be 52-bit on HW that supports it. One
 872	  should only enable this configuration option for stress testing userspace
 873	  memory management code. If unsure say N here.
 874
 875config ARM64_VA_BITS
 876	int
 877	default 36 if ARM64_VA_BITS_36
 878	default 39 if ARM64_VA_BITS_39
 879	default 42 if ARM64_VA_BITS_42
 880	default 47 if ARM64_VA_BITS_47
 881	default 48 if ARM64_VA_BITS_48
 882	default 52 if ARM64_VA_BITS_52
 883
 884choice
 885	prompt "Physical address space size"
 886	default ARM64_PA_BITS_48
 887	help
 888	  Choose the maximum physical address range that the kernel will
 889	  support.
 890
 891config ARM64_PA_BITS_48
 892	bool "48-bit"
 893
 894config ARM64_PA_BITS_52
 895	bool "52-bit (ARMv8.2)"
 896	depends on ARM64_64K_PAGES
 897	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
 898	help
 899	  Enable support for a 52-bit physical address space, introduced as
 900	  part of the ARMv8.2-LPA extension.
 901
 902	  With this enabled, the kernel will also continue to work on CPUs that
 903	  do not support ARMv8.2-LPA, but with some added memory overhead (and
 904	  minor performance overhead).
 905
 906endchoice
 907
 908config ARM64_PA_BITS
 909	int
 910	default 48 if ARM64_PA_BITS_48
 911	default 52 if ARM64_PA_BITS_52
 912
 913choice
 914	prompt "Endianness"
 915	default CPU_LITTLE_ENDIAN
 916	help
 917	  Select the endianness of data accesses performed by the CPU. Userspace
 918	  applications will need to be compiled and linked for the endianness
 919	  that is selected here.
 920
 921config CPU_BIG_ENDIAN
 922       bool "Build big-endian kernel"
 923       help
 924	  Say Y if you plan on running a kernel with a big-endian userspace.
 925
 926config CPU_LITTLE_ENDIAN
 927	bool "Build little-endian kernel"
 928	help
 929	  Say Y if you plan on running a kernel with a little-endian userspace.
 930	  This is usually the case for distributions targeting arm64.
 931
 932endchoice
 933
 934config SCHED_MC
 935	bool "Multi-core scheduler support"
 936	help
 937	  Multi-core scheduler support improves the CPU scheduler's decision
 938	  making when dealing with multi-core CPU chips at a cost of slightly
 939	  increased overhead in some places. If unsure say N here.
 940
 941config SCHED_SMT
 942	bool "SMT scheduler support"
 943	help
 944	  Improves the CPU scheduler's decision making when dealing with
 945	  MultiThreading at a cost of slightly increased overhead in some
 946	  places. If unsure say N here.
 947
 948config NR_CPUS
 949	int "Maximum number of CPUs (2-4096)"
 950	range 2 4096
 951	default "256"
 
 952
 953config HOTPLUG_CPU
 954	bool "Support for hot-pluggable CPUs"
 955	select GENERIC_IRQ_MIGRATION
 956	help
 957	  Say Y here to experiment with turning CPUs off and on.  CPUs
 958	  can be controlled through /sys/devices/system/cpu.
 959
 960# Common NUMA Features
 961config NUMA
 962	bool "NUMA Memory Allocation and Scheduler Support"
 963	select ACPI_NUMA if ACPI
 964	select OF_NUMA
 965	help
 966	  Enable NUMA (Non-Uniform Memory Access) support.
 967
 968	  The kernel will try to allocate memory used by a CPU on the
 969	  local memory of the CPU and add some more
 970	  NUMA awareness to the kernel.
 971
 972config NODES_SHIFT
 973	int "Maximum NUMA Nodes (as a power of 2)"
 974	range 1 10
 975	default "2"
 976	depends on NEED_MULTIPLE_NODES
 977	help
 978	  Specify the maximum number of NUMA Nodes available on the target
 979	  system.  Increases memory reserved to accommodate various tables.
 980
 981config USE_PERCPU_NUMA_NODE_ID
 982	def_bool y
 983	depends on NUMA
 984
 985config HAVE_SETUP_PER_CPU_AREA
 986	def_bool y
 987	depends on NUMA
 988
 989config NEED_PER_CPU_EMBED_FIRST_CHUNK
 990	def_bool y
 991	depends on NUMA
 992
 993config HOLES_IN_ZONE
 994	def_bool y
 995
 996source "kernel/Kconfig.hz"
 997
 998config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 999	def_bool y
1000
1001config ARCH_SPARSEMEM_ENABLE
1002	def_bool y
1003	select SPARSEMEM_VMEMMAP_ENABLE
1004
1005config ARCH_SPARSEMEM_DEFAULT
1006	def_bool ARCH_SPARSEMEM_ENABLE
1007
1008config ARCH_SELECT_MEMORY_MODEL
1009	def_bool ARCH_SPARSEMEM_ENABLE
1010
1011config ARCH_FLATMEM_ENABLE
1012	def_bool !NUMA
1013
1014config HAVE_ARCH_PFN_VALID
1015	def_bool y
1016
1017config HW_PERF_EVENTS
1018	def_bool y
1019	depends on ARM_PMU
1020
1021config SYS_SUPPORTS_HUGETLBFS
1022	def_bool y
1023
1024config ARCH_WANT_HUGE_PMD_SHARE
 
 
 
 
1025
1026config ARCH_HAS_CACHE_LINE_SIZE
1027	def_bool y
1028
1029config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1030	def_bool y if PGTABLE_LEVELS > 2
1031
1032# Supported by clang >= 7.0
1033config CC_HAVE_SHADOW_CALL_STACK
1034	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1035
1036config SECCOMP
1037	bool "Enable seccomp to safely compute untrusted bytecode"
1038	help
1039	  This kernel feature is useful for number crunching applications
1040	  that may need to compute untrusted bytecode during their
1041	  execution. By using pipes or other transports made available to
1042	  the process as file descriptors supporting the read/write
1043	  syscalls, it's possible to isolate those applications in
1044	  their own address space using seccomp. Once seccomp is
1045	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1046	  and the task is only allowed to execute a few safe syscalls
1047	  defined by each seccomp mode.
1048
1049config PARAVIRT
1050	bool "Enable paravirtualization code"
1051	help
1052	  This changes the kernel so it can modify itself when it is run
1053	  under a hypervisor, potentially improving performance significantly
1054	  over full virtualization.
1055
1056config PARAVIRT_TIME_ACCOUNTING
1057	bool "Paravirtual steal time accounting"
1058	select PARAVIRT
 
1059	help
1060	  Select this option to enable fine granularity task steal time
1061	  accounting. Time spent executing other tasks in parallel with
1062	  the current vCPU is discounted from the vCPU power. To account for
1063	  that, there can be a small performance impact.
1064
1065	  If in doubt, say N here.
1066
1067config KEXEC
1068	depends on PM_SLEEP_SMP
1069	select KEXEC_CORE
1070	bool "kexec system call"
1071	help
1072	  kexec is a system call that implements the ability to shutdown your
1073	  current kernel, and to start another kernel.  It is like a reboot
1074	  but it is independent of the system firmware.   And like a reboot
1075	  you can start any kernel with it, not just Linux.
1076
1077config KEXEC_FILE
1078	bool "kexec file based system call"
1079	select KEXEC_CORE
1080	help
1081	  This is new version of kexec system call. This system call is
1082	  file based and takes file descriptors as system call argument
1083	  for kernel and initramfs as opposed to list of segments as
1084	  accepted by previous system call.
1085
1086config KEXEC_SIG
1087	bool "Verify kernel signature during kexec_file_load() syscall"
1088	depends on KEXEC_FILE
1089	help
1090	  Select this option to verify a signature with loaded kernel
1091	  image. If configured, any attempt of loading a image without
1092	  valid signature will fail.
1093
1094	  In addition to that option, you need to enable signature
1095	  verification for the corresponding kernel image type being
1096	  loaded in order for this to work.
1097
1098config KEXEC_IMAGE_VERIFY_SIG
1099	bool "Enable Image signature verification support"
1100	default y
1101	depends on KEXEC_SIG
1102	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1103	help
1104	  Enable Image signature verification support.
1105
1106comment "Support for PE file signature verification disabled"
1107	depends on KEXEC_SIG
1108	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1109
1110config CRASH_DUMP
1111	bool "Build kdump crash kernel"
1112	help
1113	  Generate crash dump after being started by kexec. This should
1114	  be normally only set in special crash dump kernels which are
1115	  loaded in the main kernel with kexec-tools into a specially
1116	  reserved region and then later executed after a crash by
1117	  kdump/kexec.
1118
1119	  For more details see Documentation/admin-guide/kdump/kdump.rst
1120
1121config XEN_DOM0
1122	def_bool y
1123	depends on XEN
1124
1125config XEN
1126	bool "Xen guest support on ARM64"
1127	depends on ARM64 && OF
1128	select SWIOTLB_XEN
1129	select PARAVIRT
1130	help
1131	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1132
1133config FORCE_MAX_ZONEORDER
1134	int
1135	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1136	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1137	default "11"
1138	help
1139	  The kernel memory allocator divides physically contiguous memory
1140	  blocks into "zones", where each zone is a power of two number of
1141	  pages.  This option selects the largest power of two that the kernel
1142	  keeps in the memory allocator.  If you need to allocate very large
1143	  blocks of physically contiguous memory, then you may need to
1144	  increase this value.
1145
1146	  This config option is actually maximum order plus one. For example,
1147	  a value of 11 means that the largest free memory block is 2^10 pages.
1148
1149	  We make sure that we can allocate upto a HugePage size for each configuration.
1150	  Hence we have :
1151		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1152
1153	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1154	  4M allocations matching the default size used by generic code.
1155
1156config UNMAP_KERNEL_AT_EL0
1157	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1158	default y
1159	help
1160	  Speculation attacks against some high-performance processors can
1161	  be used to bypass MMU permission checks and leak kernel data to
1162	  userspace. This can be defended against by unmapping the kernel
1163	  when running in userspace, mapping it back in on exception entry
1164	  via a trampoline page in the vector table.
1165
1166	  If unsure, say Y.
1167
1168config HARDEN_BRANCH_PREDICTOR
1169	bool "Harden the branch predictor against aliasing attacks" if EXPERT
1170	default y
1171	help
1172	  Speculation attacks against some high-performance processors rely on
1173	  being able to manipulate the branch predictor for a victim context by
1174	  executing aliasing branches in the attacker context.  Such attacks
1175	  can be partially mitigated against by clearing internal branch
1176	  predictor state and limiting the prediction logic in some situations.
1177
1178	  This config option will take CPU-specific actions to harden the
1179	  branch predictor against aliasing attacks and may rely on specific
1180	  instruction sequences or control bits being set by the system
1181	  firmware.
1182
1183	  If unsure, say Y.
1184
1185config ARM64_SSBD
1186	bool "Speculative Store Bypass Disable" if EXPERT
1187	default y
1188	help
1189	  This enables mitigation of the bypassing of previous stores
1190	  by speculative loads.
1191
1192	  If unsure, say Y.
1193
1194config RODATA_FULL_DEFAULT_ENABLED
1195	bool "Apply r/o permissions of VM areas also to their linear aliases"
1196	default y
1197	help
1198	  Apply read-only attributes of VM areas to the linear alias of
1199	  the backing pages as well. This prevents code or read-only data
1200	  from being modified (inadvertently or intentionally) via another
1201	  mapping of the same memory page. This additional enhancement can
1202	  be turned off at runtime by passing rodata=[off|on] (and turned on
1203	  with rodata=full if this option is set to 'n')
1204
1205	  This requires the linear region to be mapped down to pages,
1206	  which may adversely affect performance in some cases.
1207
1208config ARM64_SW_TTBR0_PAN
1209	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1210	help
1211	  Enabling this option prevents the kernel from accessing
1212	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1213	  zeroed area and reserved ASID. The user access routines
1214	  restore the valid TTBR0_EL1 temporarily.
1215
1216config ARM64_TAGGED_ADDR_ABI
1217	bool "Enable the tagged user addresses syscall ABI"
1218	default y
1219	help
1220	  When this option is enabled, user applications can opt in to a
1221	  relaxed ABI via prctl() allowing tagged addresses to be passed
1222	  to system calls as pointer arguments. For details, see
1223	  Documentation/arm64/tagged-address-abi.rst.
1224
1225menuconfig COMPAT
1226	bool "Kernel support for 32-bit EL0"
1227	depends on ARM64_4K_PAGES || EXPERT
1228	select COMPAT_BINFMT_ELF if BINFMT_ELF
1229	select HAVE_UID16
1230	select OLD_SIGSUSPEND3
1231	select COMPAT_OLD_SIGACTION
1232	help
1233	  This option enables support for a 32-bit EL0 running under a 64-bit
1234	  kernel at EL1. AArch32-specific components such as system calls,
1235	  the user helper functions, VFP support and the ptrace interface are
1236	  handled appropriately by the kernel.
1237
1238	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1239	  that you will only be able to execute AArch32 binaries that were compiled
1240	  with page size aligned segments.
1241
1242	  If you want to execute 32-bit userspace applications, say Y.
1243
1244if COMPAT
1245
1246config KUSER_HELPERS
1247	bool "Enable kuser helpers page for 32-bit applications"
1248	default y
1249	help
1250	  Warning: disabling this option may break 32-bit user programs.
1251
1252	  Provide kuser helpers to compat tasks. The kernel provides
1253	  helper code to userspace in read only form at a fixed location
1254	  to allow userspace to be independent of the CPU type fitted to
1255	  the system. This permits binaries to be run on ARMv4 through
1256	  to ARMv8 without modification.
1257
1258	  See Documentation/arm/kernel_user_helpers.rst for details.
1259
1260	  However, the fixed address nature of these helpers can be used
1261	  by ROP (return orientated programming) authors when creating
1262	  exploits.
1263
1264	  If all of the binaries and libraries which run on your platform
1265	  are built specifically for your platform, and make no use of
1266	  these helpers, then you can turn this option off to hinder
1267	  such exploits. However, in that case, if a binary or library
1268	  relying on those helpers is run, it will not function correctly.
1269
1270	  Say N here only if you are absolutely certain that you do not
1271	  need these helpers; otherwise, the safe option is to say Y.
1272
1273config COMPAT_VDSO
1274	bool "Enable vDSO for 32-bit applications"
1275	depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1276	select GENERIC_COMPAT_VDSO
1277	default y
1278	help
1279	  Place in the process address space of 32-bit applications an
1280	  ELF shared object providing fast implementations of gettimeofday
1281	  and clock_gettime.
1282
1283	  You must have a 32-bit build of glibc 2.22 or later for programs
1284	  to seamlessly take advantage of this.
1285
1286config THUMB2_COMPAT_VDSO
1287	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1288	depends on COMPAT_VDSO
1289	default y
1290	help
1291	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1292	  otherwise with '-marm'.
1293
1294menuconfig ARMV8_DEPRECATED
1295	bool "Emulate deprecated/obsolete ARMv8 instructions"
1296	depends on SYSCTL
1297	help
1298	  Legacy software support may require certain instructions
1299	  that have been deprecated or obsoleted in the architecture.
1300
1301	  Enable this config to enable selective emulation of these
1302	  features.
1303
1304	  If unsure, say Y
1305
1306if ARMV8_DEPRECATED
1307
1308config SWP_EMULATION
1309	bool "Emulate SWP/SWPB instructions"
1310	help
1311	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1312	  they are always undefined. Say Y here to enable software
1313	  emulation of these instructions for userspace using LDXR/STXR.
1314	  This feature can be controlled at runtime with the abi.swp
1315	  sysctl which is disabled by default.
1316
1317	  In some older versions of glibc [<=2.8] SWP is used during futex
1318	  trylock() operations with the assumption that the code will not
1319	  be preempted. This invalid assumption may be more likely to fail
1320	  with SWP emulation enabled, leading to deadlock of the user
1321	  application.
1322
1323	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1324	  on an external transaction monitoring block called a global
1325	  monitor to maintain update atomicity. If your system does not
1326	  implement a global monitor, this option can cause programs that
1327	  perform SWP operations to uncached memory to deadlock.
1328
1329	  If unsure, say Y
1330
1331config CP15_BARRIER_EMULATION
1332	bool "Emulate CP15 Barrier instructions"
1333	help
1334	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1335	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1336	  strongly recommended to use the ISB, DSB, and DMB
1337	  instructions instead.
1338
1339	  Say Y here to enable software emulation of these
1340	  instructions for AArch32 userspace code. When this option is
1341	  enabled, CP15 barrier usage is traced which can help
1342	  identify software that needs updating. This feature can be
1343	  controlled at runtime with the abi.cp15_barrier sysctl.
1344
1345	  If unsure, say Y
1346
1347config SETEND_EMULATION
1348	bool "Emulate SETEND instruction"
1349	help
1350	  The SETEND instruction alters the data-endianness of the
1351	  AArch32 EL0, and is deprecated in ARMv8.
1352
1353	  Say Y here to enable software emulation of the instruction
1354	  for AArch32 userspace code. This feature can be controlled
1355	  at runtime with the abi.setend sysctl.
1356
1357	  Note: All the cpus on the system must have mixed endian support at EL0
1358	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1359	  endian - is hotplugged in after this feature has been enabled, there could
1360	  be unexpected results in the applications.
1361
1362	  If unsure, say Y
1363endif
1364
1365endif
1366
1367menu "ARMv8.1 architectural features"
1368
1369config ARM64_HW_AFDBM
1370	bool "Support for hardware updates of the Access and Dirty page flags"
1371	default y
1372	help
1373	  The ARMv8.1 architecture extensions introduce support for
1374	  hardware updates of the access and dirty information in page
1375	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1376	  capable processors, accesses to pages with PTE_AF cleared will
1377	  set this bit instead of raising an access flag fault.
1378	  Similarly, writes to read-only pages with the DBM bit set will
1379	  clear the read-only bit (AP[2]) instead of raising a
1380	  permission fault.
1381
1382	  Kernels built with this configuration option enabled continue
1383	  to work on pre-ARMv8.1 hardware and the performance impact is
1384	  minimal. If unsure, say Y.
1385
1386config ARM64_PAN
1387	bool "Enable support for Privileged Access Never (PAN)"
1388	default y
1389	help
1390	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1391	 prevents the kernel or hypervisor from accessing user-space (EL0)
1392	 memory directly.
1393
1394	 Choosing this option will cause any unprotected (not using
1395	 copy_to_user et al) memory access to fail with a permission fault.
1396
1397	 The feature is detected at runtime, and will remain as a 'nop'
1398	 instruction if the cpu does not implement the feature.
1399
1400config ARM64_LSE_ATOMICS
1401	bool
1402	default ARM64_USE_LSE_ATOMICS
1403	depends on $(as-instr,.arch_extension lse)
1404
1405config ARM64_USE_LSE_ATOMICS
1406	bool "Atomic instructions"
1407	depends on JUMP_LABEL
1408	default y
1409	help
1410	  As part of the Large System Extensions, ARMv8.1 introduces new
1411	  atomic instructions that are designed specifically to scale in
1412	  very large systems.
1413
1414	  Say Y here to make use of these instructions for the in-kernel
1415	  atomic routines. This incurs a small overhead on CPUs that do
1416	  not support these instructions and requires the kernel to be
1417	  built with binutils >= 2.25 in order for the new instructions
1418	  to be used.
1419
1420config ARM64_VHE
1421	bool "Enable support for Virtualization Host Extensions (VHE)"
1422	default y
1423	help
1424	  Virtualization Host Extensions (VHE) allow the kernel to run
1425	  directly at EL2 (instead of EL1) on processors that support
1426	  it. This leads to better performance for KVM, as they reduce
1427	  the cost of the world switch.
1428
1429	  Selecting this option allows the VHE feature to be detected
1430	  at runtime, and does not affect processors that do not
1431	  implement this feature.
1432
1433endmenu
1434
1435menu "ARMv8.2 architectural features"
1436
1437config ARM64_UAO
1438	bool "Enable support for User Access Override (UAO)"
1439	default y
1440	help
1441	  User Access Override (UAO; part of the ARMv8.2 Extensions)
1442	  causes the 'unprivileged' variant of the load/store instructions to
1443	  be overridden to be privileged.
1444
1445	  This option changes get_user() and friends to use the 'unprivileged'
1446	  variant of the load/store instructions. This ensures that user-space
1447	  really did have access to the supplied memory. When addr_limit is
1448	  set to kernel memory the UAO bit will be set, allowing privileged
1449	  access to kernel memory.
1450
1451	  Choosing this option will cause copy_to_user() et al to use user-space
1452	  memory permissions.
1453
1454	  The feature is detected at runtime, the kernel will use the
1455	  regular load/store instructions if the cpu does not implement the
1456	  feature.
1457
1458config ARM64_PMEM
1459	bool "Enable support for persistent memory"
1460	select ARCH_HAS_PMEM_API
1461	select ARCH_HAS_UACCESS_FLUSHCACHE
1462	help
1463	  Say Y to enable support for the persistent memory API based on the
1464	  ARMv8.2 DCPoP feature.
1465
1466	  The feature is detected at runtime, and the kernel will use DC CVAC
1467	  operations if DC CVAP is not supported (following the behaviour of
1468	  DC CVAP itself if the system does not define a point of persistence).
1469
1470config ARM64_RAS_EXTN
1471	bool "Enable support for RAS CPU Extensions"
1472	default y
1473	help
1474	  CPUs that support the Reliability, Availability and Serviceability
1475	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1476	  errors, classify them and report them to software.
1477
1478	  On CPUs with these extensions system software can use additional
1479	  barriers to determine if faults are pending and read the
1480	  classification from a new set of registers.
1481
1482	  Selecting this feature will allow the kernel to use these barriers
1483	  and access the new registers if the system supports the extension.
1484	  Platform RAS features may additionally depend on firmware support.
1485
1486config ARM64_CNP
1487	bool "Enable support for Common Not Private (CNP) translations"
1488	default y
1489	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1490	help
1491	  Common Not Private (CNP) allows translation table entries to
1492	  be shared between different PEs in the same inner shareable
1493	  domain, so the hardware can use this fact to optimise the
1494	  caching of such entries in the TLB.
1495
1496	  Selecting this option allows the CNP feature to be detected
1497	  at runtime, and does not affect PEs that do not implement
1498	  this feature.
1499
1500endmenu
1501
1502menu "ARMv8.3 architectural features"
1503
1504config ARM64_PTR_AUTH
1505	bool "Enable support for pointer authentication"
1506	default y
1507	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1508	# Modern compilers insert a .note.gnu.property section note for PAC
1509	# which is only understood by binutils starting with version 2.33.1.
1510	depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1511	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1512	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1513	help
1514	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1515	  instructions for signing and authenticating pointers against secret
1516	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1517	  and other attacks.
1518
1519	  This option enables these instructions at EL0 (i.e. for userspace).
1520	  Choosing this option will cause the kernel to initialise secret keys
1521	  for each process at exec() time, with these keys being
1522	  context-switched along with the process.
1523
1524	  If the compiler supports the -mbranch-protection or
1525	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1526	  will also cause the kernel itself to be compiled with return address
1527	  protection. In this case, and if the target hardware is known to
1528	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1529	  disabled with minimal loss of protection.
1530
1531	  The feature is detected at runtime. If the feature is not present in
1532	  hardware it will not be advertised to userspace/KVM guest nor will it
1533	  be enabled.
1534
1535	  If the feature is present on the boot CPU but not on a late CPU, then
1536	  the late CPU will be parked. Also, if the boot CPU does not have
1537	  address auth and the late CPU has then the late CPU will still boot
1538	  but with the feature disabled. On such a system, this option should
1539	  not be selected.
1540
1541	  This feature works with FUNCTION_GRAPH_TRACER option only if
1542	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1543
1544config CC_HAS_BRANCH_PROT_PAC_RET
1545	# GCC 9 or later, clang 8 or later
1546	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1547
1548config CC_HAS_SIGN_RETURN_ADDRESS
1549	# GCC 7, 8
1550	def_bool $(cc-option,-msign-return-address=all)
1551
1552config AS_HAS_PAC
1553	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1554
1555config AS_HAS_CFI_NEGATE_RA_STATE
1556	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1557
1558endmenu
1559
1560menu "ARMv8.4 architectural features"
1561
1562config ARM64_AMU_EXTN
1563	bool "Enable support for the Activity Monitors Unit CPU extension"
1564	default y
1565	help
1566	  The activity monitors extension is an optional extension introduced
1567	  by the ARMv8.4 CPU architecture. This enables support for version 1
1568	  of the activity monitors architecture, AMUv1.
1569
1570	  To enable the use of this extension on CPUs that implement it, say Y.
1571
1572	  Note that for architectural reasons, firmware _must_ implement AMU
1573	  support when running on CPUs that present the activity monitors
1574	  extension. The required support is present in:
1575	    * Version 1.5 and later of the ARM Trusted Firmware
1576
1577	  For kernels that have this configuration enabled but boot with broken
1578	  firmware, you may need to say N here until the firmware is fixed.
1579	  Otherwise you may experience firmware panics or lockups when
1580	  accessing the counter registers. Even if you are not observing these
1581	  symptoms, the values returned by the register reads might not
1582	  correctly reflect reality. Most commonly, the value read will be 0,
1583	  indicating that the counter is not enabled.
1584
1585config AS_HAS_ARMV8_4
1586	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1587
1588config ARM64_TLB_RANGE
1589	bool "Enable support for tlbi range feature"
1590	default y
1591	depends on AS_HAS_ARMV8_4
1592	help
1593	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1594	  range of input addresses.
1595
1596	  The feature introduces new assembly instructions, and they were
1597	  support when binutils >= 2.30.
1598
1599endmenu
1600
1601menu "ARMv8.5 architectural features"
1602
1603config ARM64_BTI
1604	bool "Branch Target Identification support"
1605	default y
1606	help
1607	  Branch Target Identification (part of the ARMv8.5 Extensions)
1608	  provides a mechanism to limit the set of locations to which computed
1609	  branch instructions such as BR or BLR can jump.
1610
1611	  To make use of BTI on CPUs that support it, say Y.
1612
1613	  BTI is intended to provide complementary protection to other control
1614	  flow integrity protection mechanisms, such as the Pointer
1615	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1616	  For this reason, it does not make sense to enable this option without
1617	  also enabling support for pointer authentication.  Thus, when
1618	  enabling this option you should also select ARM64_PTR_AUTH=y.
1619
1620	  Userspace binaries must also be specifically compiled to make use of
1621	  this mechanism.  If you say N here or the hardware does not support
1622	  BTI, such binaries can still run, but you get no additional
1623	  enforcement of branch destinations.
1624
1625config ARM64_BTI_KERNEL
1626	bool "Use Branch Target Identification for kernel"
1627	default y
1628	depends on ARM64_BTI
1629	depends on ARM64_PTR_AUTH
1630	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1631	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1632	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1633	# https://reviews.llvm.org/rGb8ae3fdfa579dbf366b1bb1cbfdbf8c51db7fa55
1634	depends on !CC_IS_CLANG || CLANG_VERSION >= 100001
1635	depends on !(CC_IS_CLANG && GCOV_KERNEL)
1636	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1637	help
1638	  Build the kernel with Branch Target Identification annotations
1639	  and enable enforcement of this for kernel code. When this option
1640	  is enabled and the system supports BTI all kernel code including
1641	  modular code must have BTI enabled.
1642
1643config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1644	# GCC 9 or later, clang 8 or later
1645	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1646
1647config ARM64_E0PD
1648	bool "Enable support for E0PD"
1649	default y
1650	help
1651	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1652	  that EL0 accesses made via TTBR1 always fault in constant time,
1653	  providing similar benefits to KASLR as those provided by KPTI, but
1654	  with lower overhead and without disrupting legitimate access to
1655	  kernel memory such as SPE.
1656
1657	  This option enables E0PD for TTBR1 where available.
1658
1659config ARCH_RANDOM
1660	bool "Enable support for random number generation"
1661	default y
1662	help
1663	  Random number generation (part of the ARMv8.5 Extensions)
1664	  provides a high bandwidth, cryptographically secure
1665	  hardware random number generator.
1666
1667endmenu
1668
1669config ARM64_SVE
1670	bool "ARM Scalable Vector Extension support"
1671	default y
1672	depends on !KVM || ARM64_VHE
1673	help
1674	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1675	  execution state which complements and extends the SIMD functionality
1676	  of the base architecture to support much larger vectors and to enable
1677	  additional vectorisation opportunities.
1678
1679	  To enable use of this extension on CPUs that implement it, say Y.
1680
1681	  On CPUs that support the SVE2 extensions, this option will enable
1682	  those too.
1683
1684	  Note that for architectural reasons, firmware _must_ implement SVE
1685	  support when running on SVE capable hardware.  The required support
1686	  is present in:
1687
1688	    * version 1.5 and later of the ARM Trusted Firmware
1689	    * the AArch64 boot wrapper since commit 5e1261e08abf
1690	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1691
1692	  For other firmware implementations, consult the firmware documentation
1693	  or vendor.
1694
1695	  If you need the kernel to boot on SVE-capable hardware with broken
1696	  firmware, you may need to say N here until you get your firmware
1697	  fixed.  Otherwise, you may experience firmware panics or lockups when
1698	  booting the kernel.  If unsure and you are not observing these
1699	  symptoms, you should assume that it is safe to say Y.
1700
1701	  CPUs that support SVE are architecturally required to support the
1702	  Virtualization Host Extensions (VHE), so the kernel makes no
1703	  provision for supporting SVE alongside KVM without VHE enabled.
1704	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1705	  KVM in the same kernel image.
1706
1707config ARM64_MODULE_PLTS
1708	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1709	depends on MODULES
1710	select HAVE_MOD_ARCH_SPECIFIC
1711	help
1712	  Allocate PLTs when loading modules so that jumps and calls whose
1713	  targets are too far away for their relative offsets to be encoded
1714	  in the instructions themselves can be bounced via veneers in the
1715	  module's PLT. This allows modules to be allocated in the generic
1716	  vmalloc area after the dedicated module memory area has been
1717	  exhausted.
1718
1719	  When running with address space randomization (KASLR), the module
1720	  region itself may be too far away for ordinary relative jumps and
1721	  calls, and so in that case, module PLTs are required and cannot be
1722	  disabled.
1723
1724	  Specific errata workaround(s) might also force module PLTs to be
1725	  enabled (ARM64_ERRATUM_843419).
1726
1727config ARM64_PSEUDO_NMI
1728	bool "Support for NMI-like interrupts"
1729	select ARM_GIC_V3
1730	help
1731	  Adds support for mimicking Non-Maskable Interrupts through the use of
1732	  GIC interrupt priority. This support requires version 3 or later of
1733	  ARM GIC.
1734
1735	  This high priority configuration for interrupts needs to be
1736	  explicitly enabled by setting the kernel parameter
1737	  "irqchip.gicv3_pseudo_nmi" to 1.
1738
1739	  If unsure, say N
1740
1741if ARM64_PSEUDO_NMI
1742config ARM64_DEBUG_PRIORITY_MASKING
1743	bool "Debug interrupt priority masking"
1744	help
1745	  This adds runtime checks to functions enabling/disabling
1746	  interrupts when using priority masking. The additional checks verify
1747	  the validity of ICC_PMR_EL1 when calling concerned functions.
1748
1749	  If unsure, say N
1750endif
1751
1752config RELOCATABLE
1753	bool "Build a relocatable kernel image" if EXPERT
1754	select ARCH_HAS_RELR
1755	default y
1756	help
1757	  This builds the kernel as a Position Independent Executable (PIE),
1758	  which retains all relocation metadata required to relocate the
1759	  kernel binary at runtime to a different virtual address than the
1760	  address it was linked at.
1761	  Since AArch64 uses the RELA relocation format, this requires a
1762	  relocation pass at runtime even if the kernel is loaded at the
1763	  same address it was linked at.
1764
1765config RANDOMIZE_BASE
1766	bool "Randomize the address of the kernel image"
1767	select ARM64_MODULE_PLTS if MODULES
1768	select RELOCATABLE
1769	help
1770	  Randomizes the virtual address at which the kernel image is
1771	  loaded, as a security feature that deters exploit attempts
1772	  relying on knowledge of the location of kernel internals.
1773
1774	  It is the bootloader's job to provide entropy, by passing a
1775	  random u64 value in /chosen/kaslr-seed at kernel entry.
1776
1777	  When booting via the UEFI stub, it will invoke the firmware's
1778	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1779	  to the kernel proper. In addition, it will randomise the physical
1780	  location of the kernel Image as well.
1781
1782	  If unsure, say N.
1783
1784config RANDOMIZE_MODULE_REGION_FULL
1785	bool "Randomize the module region over a 4 GB range"
1786	depends on RANDOMIZE_BASE
1787	default y
1788	help
1789	  Randomizes the location of the module region inside a 4 GB window
1790	  covering the core kernel. This way, it is less likely for modules
1791	  to leak information about the location of core kernel data structures
1792	  but it does imply that function calls between modules and the core
1793	  kernel will need to be resolved via veneers in the module PLT.
1794
1795	  When this option is not set, the module region will be randomized over
1796	  a limited range that contains the [_stext, _etext] interval of the
1797	  core kernel, so branch relocations are always in range.
1798
1799config CC_HAVE_STACKPROTECTOR_SYSREG
1800	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1801
1802config STACKPROTECTOR_PER_TASK
1803	def_bool y
1804	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1805
1806endmenu
1807
1808menu "Boot options"
1809
1810config ARM64_ACPI_PARKING_PROTOCOL
1811	bool "Enable support for the ARM64 ACPI parking protocol"
1812	depends on ACPI
1813	help
1814	  Enable support for the ARM64 ACPI parking protocol. If disabled
1815	  the kernel will not allow booting through the ARM64 ACPI parking
1816	  protocol even if the corresponding data is present in the ACPI
1817	  MADT table.
1818
1819config CMDLINE
1820	string "Default kernel command string"
1821	default ""
1822	help
1823	  Provide a set of default command-line options at build time by
1824	  entering them here. As a minimum, you should specify the the
1825	  root device (e.g. root=/dev/nfs).
1826
1827config CMDLINE_FORCE
1828	bool "Always use the default kernel command string"
1829	depends on CMDLINE != ""
1830	help
1831	  Always use the default kernel command string, even if the boot
1832	  loader passes other arguments to the kernel.
1833	  This is useful if you cannot or don't want to change the
1834	  command-line options your boot loader passes to the kernel.
1835
1836config EFI_STUB
1837	bool
1838
1839config EFI
1840	bool "UEFI runtime support"
1841	depends on OF && !CPU_BIG_ENDIAN
1842	depends on KERNEL_MODE_NEON
1843	select ARCH_SUPPORTS_ACPI
1844	select LIBFDT
1845	select UCS2_STRING
1846	select EFI_PARAMS_FROM_FDT
1847	select EFI_RUNTIME_WRAPPERS
1848	select EFI_STUB
1849	select EFI_GENERIC_STUB
1850	default y
1851	help
1852	  This option provides support for runtime services provided
1853	  by UEFI firmware (such as non-volatile variables, realtime
1854          clock, and platform reset). A UEFI stub is also provided to
1855	  allow the kernel to be booted as an EFI application. This
1856	  is only useful on systems that have UEFI firmware.
1857
1858config DMI
1859	bool "Enable support for SMBIOS (DMI) tables"
1860	depends on EFI
1861	default y
1862	help
1863	  This enables SMBIOS/DMI feature for systems.
1864
1865	  This option is only useful on systems that have UEFI firmware.
1866	  However, even with this option, the resultant kernel should
1867	  continue to boot on existing non-UEFI platforms.
1868
1869endmenu
1870
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1871config SYSVIPC_COMPAT
1872	def_bool y
1873	depends on COMPAT && SYSVIPC
1874
1875config ARCH_ENABLE_HUGEPAGE_MIGRATION
1876	def_bool y
1877	depends on HUGETLB_PAGE && MIGRATION
1878
1879menu "Power management options"
1880
1881source "kernel/power/Kconfig"
1882
1883config ARCH_HIBERNATION_POSSIBLE
1884	def_bool y
1885	depends on CPU_PM
1886
1887config ARCH_HIBERNATION_HEADER
1888	def_bool y
1889	depends on HIBERNATION
1890
1891config ARCH_SUSPEND_POSSIBLE
1892	def_bool y
1893
1894endmenu
1895
1896menu "CPU Power Management"
1897
1898source "drivers/cpuidle/Kconfig"
1899
1900source "drivers/cpufreq/Kconfig"
1901
1902endmenu
1903
 
 
 
 
1904source "drivers/firmware/Kconfig"
1905
1906source "drivers/acpi/Kconfig"
1907
 
 
1908source "arch/arm64/kvm/Kconfig"
1909
 
 
 
 
 
1910if CRYPTO
1911source "arch/arm64/crypto/Kconfig"
1912endif