1config ARM64
  2	def_bool y
  3	select ACPI_CCA_REQUIRED if ACPI
  4	select ACPI_GENERIC_GSI if ACPI
 
 
  5	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
 
 
 
 
 
  6	select ARCH_HAS_DEVMEM_IS_ALLOWED
  7	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  8	select ARCH_HAS_ELF_RANDOMIZE
 
 
 
  9	select ARCH_HAS_GCOV_PROFILE_ALL
 10	select ARCH_HAS_SG_CHAIN
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 11	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 12	select ARCH_USE_CMPXCHG_LOCKREF
 
 
 
 13	select ARCH_SUPPORTS_ATOMIC_RMW
 14	select ARCH_WANT_OPTIONAL_GPIOLIB
 15	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 
 
 16	select ARCH_WANT_FRAME_POINTERS
 
 17	select ARCH_HAS_UBSAN_SANITIZE_ALL
 18	select ARM_AMBA
 19	select ARM_ARCH_TIMER
 20	select ARM_GIC
 21	select AUDIT_ARCH_COMPAT_GENERIC
 22	select ARM_GIC_V2M if PCI_MSI
 23	select ARM_GIC_V3
 24	select ARM_GIC_V3_ITS if PCI_MSI
 25	select ARM_PSCI_FW
 26	select BUILDTIME_EXTABLE_SORT
 27	select CLONE_BACKWARDS
 28	select COMMON_CLK
 29	select CPU_PM if (SUSPEND || CPU_IDLE)
 
 30	select DCACHE_WORD_ACCESS
 
 31	select EDAC_SUPPORT
 32	select FRAME_POINTER
 33	select GENERIC_ALLOCATOR
 
 34	select GENERIC_CLOCKEVENTS
 35	select GENERIC_CLOCKEVENTS_BROADCAST
 36	select GENERIC_CPU_AUTOPROBE
 
 37	select GENERIC_EARLY_IOREMAP
 38	select GENERIC_IDLE_POLL_SETUP
 
 39	select GENERIC_IRQ_PROBE
 40	select GENERIC_IRQ_SHOW
 41	select GENERIC_IRQ_SHOW_LEVEL
 42	select GENERIC_PCI_IOMAP
 43	select GENERIC_SCHED_CLOCK
 44	select GENERIC_SMP_IDLE_THREAD
 45	select GENERIC_STRNCPY_FROM_USER
 46	select GENERIC_STRNLEN_USER
 47	select GENERIC_TIME_VSYSCALL
 
 48	select HANDLE_DOMAIN_IRQ
 49	select HARDIRQS_SW_RESEND
 
 
 50	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 51	select HAVE_ARCH_AUDITSYSCALL
 52	select HAVE_ARCH_BITREVERSE
 53	select HAVE_ARCH_HUGE_VMAP
 54	select HAVE_ARCH_JUMP_LABEL
 55	select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 
 
 56	select HAVE_ARCH_KGDB
 57	select HAVE_ARCH_MMAP_RND_BITS
 58	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 
 59	select HAVE_ARCH_SECCOMP_FILTER
 
 
 60	select HAVE_ARCH_TRACEHOOK
 61	select HAVE_BPF_JIT
 
 
 
 
 62	select HAVE_C_RECORDMCOUNT
 63	select HAVE_CC_STACKPROTECTOR
 64	select HAVE_CMPXCHG_DOUBLE
 65	select HAVE_CMPXCHG_LOCAL
 
 66	select HAVE_DEBUG_BUGVERBOSE
 67	select HAVE_DEBUG_KMEMLEAK
 68	select HAVE_DMA_API_DEBUG
 69	select HAVE_DMA_CONTIGUOUS
 70	select HAVE_DYNAMIC_FTRACE
 71	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 
 72	select HAVE_FTRACE_MCOUNT_RECORD
 73	select HAVE_FUNCTION_TRACER
 
 74	select HAVE_FUNCTION_GRAPH_TRACER
 75	select HAVE_GENERIC_DMA_COHERENT
 76	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 77	select HAVE_IRQ_TIME_ACCOUNTING
 78	select HAVE_MEMBLOCK
 
 79	select HAVE_PATA_PLATFORM
 80	select HAVE_PERF_EVENTS
 81	select HAVE_PERF_REGS
 82	select HAVE_PERF_USER_STACK_DUMP
 
 
 83	select HAVE_RCU_TABLE_FREE
 
 
 84	select HAVE_SYSCALL_TRACEPOINTS
 
 
 
 85	select IOMMU_DMA if IOMMU_SUPPORT
 86	select IRQ_DOMAIN
 87	select IRQ_FORCED_THREADING
 88	select MODULES_USE_ELF_RELA
 89	select NO_BOOTMEM
 
 90	select OF
 91	select OF_EARLY_FLATTREE
 92	select OF_RESERVED_MEM
 93	select PERF_USE_VMALLOC
 
 94	select POWER_RESET
 95	select POWER_SUPPLY
 96	select RTC_LIB
 97	select SPARSE_IRQ
 
 98	select SYSCTL_EXCEPTION_TRACE
 99	select HAVE_CONTEXT_TRACKING
100	select HAVE_ARM_SMCCC
101	help
102	  ARM 64-bit (AArch64) Linux support.
103
104config 64BIT
105	def_bool y
106
107config ARCH_PHYS_ADDR_T_64BIT
108	def_bool y
109
110config MMU
111	def_bool y
112
 
 
 
 
 
 
 
 
 
 
 
 
113config ARCH_MMAP_RND_BITS_MIN
114       default 14 if ARM64_64K_PAGES
115       default 16 if ARM64_16K_PAGES
116       default 18
117
118# max bits determined by the following formula:
119#  VA_BITS - PAGE_SHIFT - 3
120config ARCH_MMAP_RND_BITS_MAX
121       default 19 if ARM64_VA_BITS=36
122       default 24 if ARM64_VA_BITS=39
123       default 27 if ARM64_VA_BITS=42
124       default 30 if ARM64_VA_BITS=47
125       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
126       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
127       default 33 if ARM64_VA_BITS=48
128       default 14 if ARM64_64K_PAGES
129       default 16 if ARM64_16K_PAGES
130       default 18
131
132config ARCH_MMAP_RND_COMPAT_BITS_MIN
133       default 7 if ARM64_64K_PAGES
134       default 9 if ARM64_16K_PAGES
135       default 11
136
137config ARCH_MMAP_RND_COMPAT_BITS_MAX
138       default 16
139
140config NO_IOPORT_MAP
141	def_bool y if !PCI
142
143config STACKTRACE_SUPPORT
144	def_bool y
145
146config ILLEGAL_POINTER_VALUE
147	hex
148	default 0xdead000000000000
149
150config LOCKDEP_SUPPORT
151	def_bool y
152
153config TRACE_IRQFLAGS_SUPPORT
154	def_bool y
155
156config RWSEM_XCHGADD_ALGORITHM
157	def_bool y
158
159config GENERIC_BUG
160	def_bool y
161	depends on BUG
162
163config GENERIC_BUG_RELATIVE_POINTERS
164	def_bool y
165	depends on GENERIC_BUG
166
167config GENERIC_HWEIGHT
168	def_bool y
169
170config GENERIC_CSUM
171        def_bool y
172
173config GENERIC_CALIBRATE_DELAY
174	def_bool y
175
176config ZONE_DMA
177	def_bool y
178
179config HAVE_GENERIC_RCU_GUP
180	def_bool y
181
182config ARCH_DMA_ADDR_T_64BIT
183	def_bool y
184
185config NEED_DMA_MAP_STATE
186	def_bool y
187
188config NEED_SG_DMA_LENGTH
189	def_bool y
190
191config SMP
192	def_bool y
193
194config SWIOTLB
195	def_bool y
196
197config IOMMU_HELPER
198	def_bool SWIOTLB
199
200config KERNEL_MODE_NEON
201	def_bool y
202
203config FIX_EARLYCON_MEM
204	def_bool y
205
206config PGTABLE_LEVELS
207	int
208	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
209	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
210	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
211	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
212	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
213	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
214
215source "init/Kconfig"
216
217source "kernel/Kconfig.freezer"
218
219source "arch/arm64/Kconfig.platforms"
220
221menu "Bus support"
222
223config PCI
224	bool "PCI support"
225	help
226	  This feature enables support for PCI bus system. If you say Y
227	  here, the kernel will include drivers and infrastructure code
228	  to support PCI bus devices.
229
230config PCI_DOMAINS
231	def_bool PCI
232
233config PCI_DOMAINS_GENERIC
234	def_bool PCI
235
236config PCI_SYSCALL
237	def_bool PCI
238
239source "drivers/pci/Kconfig"
 
 
 
 
 
 
 
 
 
 
 
 
 
240
241endmenu
242
243menu "Kernel Features"
244
245menu "ARM errata workarounds via the alternatives framework"
246
 
 
 
247config ARM64_ERRATUM_826319
248	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
249	default y
 
250	help
251	  This option adds an alternative code sequence to work around ARM
252	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
253	  AXI master interface and an L2 cache.
254
255	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
256	  and is unable to accept a certain write via this interface, it will
257	  not progress on read data presented on the read data channel and the
258	  system can deadlock.
259
260	  The workaround promotes data cache clean instructions to
261	  data cache clean-and-invalidate.
262	  Please note that this does not necessarily enable the workaround,
263	  as it depends on the alternative framework, which will only patch
264	  the kernel if an affected CPU is detected.
265
266	  If unsure, say Y.
267
268config ARM64_ERRATUM_827319
269	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
270	default y
 
271	help
272	  This option adds an alternative code sequence to work around ARM
273	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
274	  master interface and an L2 cache.
275
276	  Under certain conditions this erratum can cause a clean line eviction
277	  to occur at the same time as another transaction to the same address
278	  on the AMBA 5 CHI interface, which can cause data corruption if the
279	  interconnect reorders the two transactions.
280
281	  The workaround promotes data cache clean instructions to
282	  data cache clean-and-invalidate.
283	  Please note that this does not necessarily enable the workaround,
284	  as it depends on the alternative framework, which will only patch
285	  the kernel if an affected CPU is detected.
286
287	  If unsure, say Y.
288
289config ARM64_ERRATUM_824069
290	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
291	default y
 
292	help
293	  This option adds an alternative code sequence to work around ARM
294	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
295	  to a coherent interconnect.
296
297	  If a Cortex-A53 processor is executing a store or prefetch for
298	  write instruction at the same time as a processor in another
299	  cluster is executing a cache maintenance operation to the same
300	  address, then this erratum might cause a clean cache line to be
301	  incorrectly marked as dirty.
302
303	  The workaround promotes data cache clean instructions to
304	  data cache clean-and-invalidate.
305	  Please note that this option does not necessarily enable the
306	  workaround, as it depends on the alternative framework, which will
307	  only patch the kernel if an affected CPU is detected.
308
309	  If unsure, say Y.
310
311config ARM64_ERRATUM_819472
312	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
313	default y
 
314	help
315	  This option adds an alternative code sequence to work around ARM
316	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
317	  present when it is connected to a coherent interconnect.
318
319	  If the processor is executing a load and store exclusive sequence at
320	  the same time as a processor in another cluster is executing a cache
321	  maintenance operation to the same address, then this erratum might
322	  cause data corruption.
323
324	  The workaround promotes data cache clean instructions to
325	  data cache clean-and-invalidate.
326	  Please note that this does not necessarily enable the workaround,
327	  as it depends on the alternative framework, which will only patch
328	  the kernel if an affected CPU is detected.
329
330	  If unsure, say Y.
331
332config ARM64_ERRATUM_832075
333	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
334	default y
335	help
336	  This option adds an alternative code sequence to work around ARM
337	  erratum 832075 on Cortex-A57 parts up to r1p2.
338
339	  Affected Cortex-A57 parts might deadlock when exclusive load/store
340	  instructions to Write-Back memory are mixed with Device loads.
341
342	  The workaround is to promote device loads to use Load-Acquire
343	  semantics.
344	  Please note that this does not necessarily enable the workaround,
345	  as it depends on the alternative framework, which will only patch
346	  the kernel if an affected CPU is detected.
347
348	  If unsure, say Y.
349
350config ARM64_ERRATUM_834220
351	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
352	depends on KVM
353	default y
354	help
355	  This option adds an alternative code sequence to work around ARM
356	  erratum 834220 on Cortex-A57 parts up to r1p2.
357
358	  Affected Cortex-A57 parts might report a Stage 2 translation
359	  fault as the result of a Stage 1 fault for load crossing a
360	  page boundary when there is a permission or device memory
361	  alignment fault at Stage 1 and a translation fault at Stage 2.
362
363	  The workaround is to verify that the Stage 1 translation
364	  doesn't generate a fault before handling the Stage 2 fault.
365	  Please note that this does not necessarily enable the workaround,
366	  as it depends on the alternative framework, which will only patch
367	  the kernel if an affected CPU is detected.
368
369	  If unsure, say Y.
370
371config ARM64_ERRATUM_845719
372	bool "Cortex-A53: 845719: a load might read incorrect data"
373	depends on COMPAT
374	default y
375	help
376	  This option adds an alternative code sequence to work around ARM
377	  erratum 845719 on Cortex-A53 parts up to r0p4.
378
379	  When running a compat (AArch32) userspace on an affected Cortex-A53
380	  part, a load at EL0 from a virtual address that matches the bottom 32
381	  bits of the virtual address used by a recent load at (AArch64) EL1
382	  might return incorrect data.
383
384	  The workaround is to write the contextidr_el1 register on exception
385	  return to a 32-bit task.
386	  Please note that this does not necessarily enable the workaround,
387	  as it depends on the alternative framework, which will only patch
388	  the kernel if an affected CPU is detected.
389
390	  If unsure, say Y.
391
392config ARM64_ERRATUM_843419
393	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
394	depends on MODULES
395	default y
396	select ARM64_MODULE_CMODEL_LARGE
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
397	help
398	  This option builds kernel modules using the large memory model in
399	  order to avoid the use of the ADRP instruction, which can cause
400	  a subsequent memory access to use an incorrect address on Cortex-A53
401	  parts up to r0p4.
402
403	  Note that the kernel itself must be linked with a version of ld
404	  which fixes potentially affected ADRP instructions through the
405	  use of veneers.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
406
407	  If unsure, say Y.
408
409config CAVIUM_ERRATUM_22375
410	bool "Cavium erratum 22375, 24313"
411	default y
412	help
413	  Enable workaround for erratum 22375, 24313.
414
415	  This implements two gicv3-its errata workarounds for ThunderX. Both
416	  with small impact affecting only ITS table allocation.
417
418	    erratum 22375: only alloc 8MB table size
419	    erratum 24313: ignore memory access type
420
421	  The fixes are in ITS initialization and basically ignore memory access
422	  type and table size provided by the TYPER and BASER registers.
423
424	  If unsure, say Y.
425
 
 
 
 
 
 
 
 
 
426config CAVIUM_ERRATUM_23154
427	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
428	default y
429	help
430	  The gicv3 of ThunderX requires a modified version for
431	  reading the IAR status to ensure data synchronization
432	  (access to icc_iar1_el1 is not sync'ed before and after).
433
434	  If unsure, say Y.
435
436config CAVIUM_ERRATUM_27456
437	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
438	default y
439	help
440	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
441	  instructions may cause the icache to become corrupted if it
442	  contains data for a non-current ASID.  The fix is to
443	  invalidate the icache when changing the mm context.
444
445	  If unsure, say Y.
446
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
447endmenu
448
449
450choice
451	prompt "Page size"
452	default ARM64_4K_PAGES
453	help
454	  Page size (translation granule) configuration.
455
456config ARM64_4K_PAGES
457	bool "4KB"
458	help
459	  This feature enables 4KB pages support.
460
461config ARM64_16K_PAGES
462	bool "16KB"
463	help
464	  The system will use 16KB pages support. AArch32 emulation
465	  requires applications compiled with 16K (or a multiple of 16K)
466	  aligned segments.
467
468config ARM64_64K_PAGES
469	bool "64KB"
470	help
471	  This feature enables 64KB pages support (4KB by default)
472	  allowing only two levels of page tables and faster TLB
473	  look-up. AArch32 emulation requires applications compiled
474	  with 64K aligned segments.
475
476endchoice
477
478choice
479	prompt "Virtual address space size"
480	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
481	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
482	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
483	help
484	  Allows choosing one of multiple possible virtual address
485	  space sizes. The level of translation table is determined by
486	  a combination of page size and virtual address space size.
487
488config ARM64_VA_BITS_36
489	bool "36-bit" if EXPERT
490	depends on ARM64_16K_PAGES
491
492config ARM64_VA_BITS_39
493	bool "39-bit"
494	depends on ARM64_4K_PAGES
495
496config ARM64_VA_BITS_42
497	bool "42-bit"
498	depends on ARM64_64K_PAGES
499
500config ARM64_VA_BITS_47
501	bool "47-bit"
502	depends on ARM64_16K_PAGES
503
504config ARM64_VA_BITS_48
505	bool "48-bit"
506
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
507endchoice
508
 
 
 
 
 
 
 
 
 
 
 
 
 
509config ARM64_VA_BITS
510	int
511	default 36 if ARM64_VA_BITS_36
512	default 39 if ARM64_VA_BITS_39
513	default 42 if ARM64_VA_BITS_42
514	default 47 if ARM64_VA_BITS_47
515	default 48 if ARM64_VA_BITS_48
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
516
517config CPU_BIG_ENDIAN
518       bool "Build big-endian kernel"
519       help
520         Say Y if you plan on running a kernel in big-endian mode.
521
522config SCHED_MC
523	bool "Multi-core scheduler support"
524	help
525	  Multi-core scheduler support improves the CPU scheduler's decision
526	  making when dealing with multi-core CPU chips at a cost of slightly
527	  increased overhead in some places. If unsure say N here.
528
529config SCHED_SMT
530	bool "SMT scheduler support"
531	help
532	  Improves the CPU scheduler's decision making when dealing with
533	  MultiThreading at a cost of slightly increased overhead in some
534	  places. If unsure say N here.
535
536config NR_CPUS
537	int "Maximum number of CPUs (2-4096)"
538	range 2 4096
539	# These have to remain sorted largest to smallest
540	default "64"
541
542config HOTPLUG_CPU
543	bool "Support for hot-pluggable CPUs"
544	select GENERIC_IRQ_MIGRATION
545	help
546	  Say Y here to experiment with turning CPUs off and on.  CPUs
547	  can be controlled through /sys/devices/system/cpu.
548
549source kernel/Kconfig.preempt
550source kernel/Kconfig.hz
 
 
 
 
 
551
552config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
553	def_bool y
 
554
555config ARCH_HAS_HOLES_MEMORYMODEL
556	def_bool y if SPARSEMEM
 
 
 
 
 
557
558config ARCH_SPARSEMEM_ENABLE
559	def_bool y
560	select SPARSEMEM_VMEMMAP_ENABLE
561
562config ARCH_SPARSEMEM_DEFAULT
563	def_bool ARCH_SPARSEMEM_ENABLE
564
565config ARCH_SELECT_MEMORY_MODEL
566	def_bool ARCH_SPARSEMEM_ENABLE
567
 
 
 
568config HAVE_ARCH_PFN_VALID
569	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
570
571config HW_PERF_EVENTS
572	def_bool y
573	depends on ARM_PMU
574
575config SYS_SUPPORTS_HUGETLBFS
576	def_bool y
577
578config ARCH_WANT_HUGE_PMD_SHARE
579	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
580
581config HAVE_ARCH_TRANSPARENT_HUGEPAGE
582	def_bool y
583
584config ARCH_HAS_CACHE_LINE_SIZE
585	def_bool y
586
587source "mm/Kconfig"
 
588
589config SECCOMP
590	bool "Enable seccomp to safely compute untrusted bytecode"
591	---help---
592	  This kernel feature is useful for number crunching applications
593	  that may need to compute untrusted bytecode during their
594	  execution. By using pipes or other transports made available to
595	  the process as file descriptors supporting the read/write
596	  syscalls, it's possible to isolate those applications in
597	  their own address space using seccomp. Once seccomp is
598	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
599	  and the task is only allowed to execute a few safe syscalls
600	  defined by each seccomp mode.
601
602config PARAVIRT
603	bool "Enable paravirtualization code"
604	help
605	  This changes the kernel so it can modify itself when it is run
606	  under a hypervisor, potentially improving performance significantly
607	  over full virtualization.
608
609config PARAVIRT_TIME_ACCOUNTING
610	bool "Paravirtual steal time accounting"
611	select PARAVIRT
612	default n
613	help
614	  Select this option to enable fine granularity task steal time
615	  accounting. Time spent executing other tasks in parallel with
616	  the current vCPU is discounted from the vCPU power. To account for
617	  that, there can be a small performance impact.
618
619	  If in doubt, say N here.
620
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
621config XEN_DOM0
622	def_bool y
623	depends on XEN
624
625config XEN
626	bool "Xen guest support on ARM64"
627	depends on ARM64 && OF
628	select SWIOTLB_XEN
629	select PARAVIRT
630	help
631	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
632
633config FORCE_MAX_ZONEORDER
634	int
635	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
636	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
637	default "11"
638	help
639	  The kernel memory allocator divides physically contiguous memory
640	  blocks into "zones", where each zone is a power of two number of
641	  pages.  This option selects the largest power of two that the kernel
642	  keeps in the memory allocator.  If you need to allocate very large
643	  blocks of physically contiguous memory, then you may need to
644	  increase this value.
645
646	  This config option is actually maximum order plus one. For example,
647	  a value of 11 means that the largest free memory block is 2^10 pages.
648
649	  We make sure that we can allocate upto a HugePage size for each configuration.
650	  Hence we have :
651		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
652
653	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
654	  4M allocations matching the default size used by generic code.
655
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
656menuconfig ARMV8_DEPRECATED
657	bool "Emulate deprecated/obsolete ARMv8 instructions"
658	depends on COMPAT
659	help
660	  Legacy software support may require certain instructions
661	  that have been deprecated or obsoleted in the architecture.
662
663	  Enable this config to enable selective emulation of these
664	  features.
665
666	  If unsure, say Y
667
668if ARMV8_DEPRECATED
669
670config SWP_EMULATION
671	bool "Emulate SWP/SWPB instructions"
672	help
673	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
674	  they are always undefined. Say Y here to enable software
675	  emulation of these instructions for userspace using LDXR/STXR.
676
677	  In some older versions of glibc [<=2.8] SWP is used during futex
678	  trylock() operations with the assumption that the code will not
679	  be preempted. This invalid assumption may be more likely to fail
680	  with SWP emulation enabled, leading to deadlock of the user
681	  application.
682
683	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
684	  on an external transaction monitoring block called a global
685	  monitor to maintain update atomicity. If your system does not
686	  implement a global monitor, this option can cause programs that
687	  perform SWP operations to uncached memory to deadlock.
688
689	  If unsure, say Y
690
691config CP15_BARRIER_EMULATION
692	bool "Emulate CP15 Barrier instructions"
693	help
694	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
695	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
696	  strongly recommended to use the ISB, DSB, and DMB
697	  instructions instead.
698
699	  Say Y here to enable software emulation of these
700	  instructions for AArch32 userspace code. When this option is
701	  enabled, CP15 barrier usage is traced which can help
702	  identify software that needs updating.
703
704	  If unsure, say Y
705
706config SETEND_EMULATION
707	bool "Emulate SETEND instruction"
708	help
709	  The SETEND instruction alters the data-endianness of the
710	  AArch32 EL0, and is deprecated in ARMv8.
711
712	  Say Y here to enable software emulation of the instruction
713	  for AArch32 userspace code.
714
715	  Note: All the cpus on the system must have mixed endian support at EL0
716	  for this feature to be enabled. If a new CPU - which doesn't support mixed
717	  endian - is hotplugged in after this feature has been enabled, there could
718	  be unexpected results in the applications.
719
720	  If unsure, say Y
721endif
722
 
 
723menu "ARMv8.1 architectural features"
724
725config ARM64_HW_AFDBM
726	bool "Support for hardware updates of the Access and Dirty page flags"
727	default y
728	help
729	  The ARMv8.1 architecture extensions introduce support for
730	  hardware updates of the access and dirty information in page
731	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
732	  capable processors, accesses to pages with PTE_AF cleared will
733	  set this bit instead of raising an access flag fault.
734	  Similarly, writes to read-only pages with the DBM bit set will
735	  clear the read-only bit (AP[2]) instead of raising a
736	  permission fault.
737
738	  Kernels built with this configuration option enabled continue
739	  to work on pre-ARMv8.1 hardware and the performance impact is
740	  minimal. If unsure, say Y.
741
742config ARM64_PAN
743	bool "Enable support for Privileged Access Never (PAN)"
744	default y
745	help
746	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
747	 prevents the kernel or hypervisor from accessing user-space (EL0)
748	 memory directly.
749
750	 Choosing this option will cause any unprotected (not using
751	 copy_to_user et al) memory access to fail with a permission fault.
752
753	 The feature is detected at runtime, and will remain as a 'nop'
754	 instruction if the cpu does not implement the feature.
755
756config ARM64_LSE_ATOMICS
757	bool "Atomic instructions"
 
 
758	help
759	  As part of the Large System Extensions, ARMv8.1 introduces new
760	  atomic instructions that are designed specifically to scale in
761	  very large systems.
762
763	  Say Y here to make use of these instructions for the in-kernel
764	  atomic routines. This incurs a small overhead on CPUs that do
765	  not support these instructions and requires the kernel to be
766	  built with binutils >= 2.25.
 
767
768config ARM64_VHE
769	bool "Enable support for Virtualization Host Extensions (VHE)"
770	default y
771	help
772	  Virtualization Host Extensions (VHE) allow the kernel to run
773	  directly at EL2 (instead of EL1) on processors that support
774	  it. This leads to better performance for KVM, as they reduce
775	  the cost of the world switch.
776
777	  Selecting this option allows the VHE feature to be detected
778	  at runtime, and does not affect processors that do not
779	  implement this feature.
780
781endmenu
782
783menu "ARMv8.2 architectural features"
784
785config ARM64_UAO
786	bool "Enable support for User Access Override (UAO)"
787	default y
788	help
789	  User Access Override (UAO; part of the ARMv8.2 Extensions)
790	  causes the 'unprivileged' variant of the load/store instructions to
791	  be overriden to be privileged.
792
793	  This option changes get_user() and friends to use the 'unprivileged'
794	  variant of the load/store instructions. This ensures that user-space
795	  really did have access to the supplied memory. When addr_limit is
796	  set to kernel memory the UAO bit will be set, allowing privileged
797	  access to kernel memory.
798
799	  Choosing this option will cause copy_to_user() et al to use user-space
800	  memory permissions.
801
802	  The feature is detected at runtime, the kernel will use the
803	  regular load/store instructions if the cpu does not implement the
804	  feature.
805
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
806endmenu
807
808config ARM64_MODULE_CMODEL_LARGE
809	bool
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
810
811config ARM64_MODULE_PLTS
812	bool
813	select ARM64_MODULE_CMODEL_LARGE
814	select HAVE_MOD_ARCH_SPECIFIC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
815
816config RELOCATABLE
817	bool
 
818	help
819	  This builds the kernel as a Position Independent Executable (PIE),
820	  which retains all relocation metadata required to relocate the
821	  kernel binary at runtime to a different virtual address than the
822	  address it was linked at.
823	  Since AArch64 uses the RELA relocation format, this requires a
824	  relocation pass at runtime even if the kernel is loaded at the
825	  same address it was linked at.
826
827config RANDOMIZE_BASE
828	bool "Randomize the address of the kernel image"
829	select ARM64_MODULE_PLTS
830	select RELOCATABLE
831	help
832	  Randomizes the virtual address at which the kernel image is
833	  loaded, as a security feature that deters exploit attempts
834	  relying on knowledge of the location of kernel internals.
835
836	  It is the bootloader's job to provide entropy, by passing a
837	  random u64 value in /chosen/kaslr-seed at kernel entry.
838
839	  When booting via the UEFI stub, it will invoke the firmware's
840	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
841	  to the kernel proper. In addition, it will randomise the physical
842	  location of the kernel Image as well.
843
844	  If unsure, say N.
845
846config RANDOMIZE_MODULE_REGION_FULL
847	bool "Randomize the module region independently from the core kernel"
848	depends on RANDOMIZE_BASE
849	default y
850	help
851	  Randomizes the location of the module region without considering the
852	  location of the core kernel. This way, it is impossible for modules
853	  to leak information about the location of core kernel data structures
854	  but it does imply that function calls between modules and the core
855	  kernel will need to be resolved via veneers in the module PLT.
856
857	  When this option is not set, the module region will be randomized over
858	  a limited range that contains the [_stext, _etext] interval of the
859	  core kernel, so branch relocations are always in range.
860
 
 
 
 
 
 
 
861endmenu
862
863menu "Boot options"
864
865config ARM64_ACPI_PARKING_PROTOCOL
866	bool "Enable support for the ARM64 ACPI parking protocol"
867	depends on ACPI
868	help
869	  Enable support for the ARM64 ACPI parking protocol. If disabled
870	  the kernel will not allow booting through the ARM64 ACPI parking
871	  protocol even if the corresponding data is present in the ACPI
872	  MADT table.
873
874config CMDLINE
875	string "Default kernel command string"
876	default ""
877	help
878	  Provide a set of default command-line options at build time by
879	  entering them here. As a minimum, you should specify the the
880	  root device (e.g. root=/dev/nfs).
881
882config CMDLINE_FORCE
883	bool "Always use the default kernel command string"
884	help
885	  Always use the default kernel command string, even if the boot
886	  loader passes other arguments to the kernel.
887	  This is useful if you cannot or don't want to change the
888	  command-line options your boot loader passes to the kernel.
889
890config EFI_STUB
891	bool
892
893config EFI
894	bool "UEFI runtime support"
895	depends on OF && !CPU_BIG_ENDIAN
 
 
896	select LIBFDT
897	select UCS2_STRING
898	select EFI_PARAMS_FROM_FDT
899	select EFI_RUNTIME_WRAPPERS
900	select EFI_STUB
901	select EFI_ARMSTUB
902	default y
903	help
904	  This option provides support for runtime services provided
905	  by UEFI firmware (such as non-volatile variables, realtime
906          clock, and platform reset). A UEFI stub is also provided to
907	  allow the kernel to be booted as an EFI application. This
908	  is only useful on systems that have UEFI firmware.
909
910config DMI
911	bool "Enable support for SMBIOS (DMI) tables"
912	depends on EFI
913	default y
914	help
915	  This enables SMBIOS/DMI feature for systems.
916
917	  This option is only useful on systems that have UEFI firmware.
918	  However, even with this option, the resultant kernel should
919	  continue to boot on existing non-UEFI platforms.
920
921endmenu
922
923menu "Userspace binary formats"
924
925source "fs/Kconfig.binfmt"
926
927config COMPAT
928	bool "Kernel support for 32-bit EL0"
929	depends on ARM64_4K_PAGES || EXPERT
930	select COMPAT_BINFMT_ELF
931	select HAVE_UID16
932	select OLD_SIGSUSPEND3
933	select COMPAT_OLD_SIGACTION
934	help
935	  This option enables support for a 32-bit EL0 running under a 64-bit
936	  kernel at EL1. AArch32-specific components such as system calls,
937	  the user helper functions, VFP support and the ptrace interface are
938	  handled appropriately by the kernel.
939
940	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
941	  that you will only be able to execute AArch32 binaries that were compiled
942	  with page size aligned segments.
943
944	  If you want to execute 32-bit userspace applications, say Y.
945
946config SYSVIPC_COMPAT
947	def_bool y
948	depends on COMPAT && SYSVIPC
949
950endmenu
 
 
951
952menu "Power management options"
953
954source "kernel/power/Kconfig"
955
 
 
 
 
 
 
 
 
956config ARCH_SUSPEND_POSSIBLE
957	def_bool y
958
959endmenu
960
961menu "CPU Power Management"
962
963source "drivers/cpuidle/Kconfig"
964
965source "drivers/cpufreq/Kconfig"
966
967endmenu
968
969source "net/Kconfig"
970
971source "drivers/Kconfig"
972
973source "drivers/firmware/Kconfig"
974
975source "drivers/acpi/Kconfig"
976
977source "fs/Kconfig"
978
979source "arch/arm64/kvm/Kconfig"
980
981source "arch/arm64/Kconfig.debug"
982
983source "security/Kconfig"
984
985source "crypto/Kconfig"
986if CRYPTO
987source "arch/arm64/crypto/Kconfig"
988endif
989
990source "lib/Kconfig"

   1# SPDX-License-Identifier: GPL-2.0-only
   2config ARM64
   3	def_bool y
   4	select ACPI_CCA_REQUIRED if ACPI
   5	select ACPI_GENERIC_GSI if ACPI
   6	select ACPI_GTDT if ACPI
   7	select ACPI_IORT if ACPI
   8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   9	select ACPI_MCFG if (ACPI && PCI)
  10	select ACPI_SPCR_TABLE if ACPI
  11	select ACPI_PPTT if ACPI
  12	select ARCH_CLOCKSOURCE_DATA
  13	select ARCH_HAS_DEBUG_VIRTUAL
  14	select ARCH_HAS_DEVMEM_IS_ALLOWED
  15	select ARCH_HAS_DMA_COHERENT_TO_PFN
  16	select ARCH_HAS_DMA_PREP_COHERENT
  17	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
  18	select ARCH_HAS_FAST_MULTIPLIER
  19	select ARCH_HAS_FORTIFY_SOURCE
  20	select ARCH_HAS_GCOV_PROFILE_ALL
  21	select ARCH_HAS_GIGANTIC_PAGE
  22	select ARCH_HAS_KCOV
  23	select ARCH_HAS_KEEPINITRD
  24	select ARCH_HAS_MEMBARRIER_SYNC_CORE
  25	select ARCH_HAS_PTE_DEVMAP
  26	select ARCH_HAS_PTE_SPECIAL
  27	select ARCH_HAS_SETUP_DMA_OPS
  28	select ARCH_HAS_SET_DIRECT_MAP
  29	select ARCH_HAS_SET_MEMORY
  30	select ARCH_HAS_STRICT_KERNEL_RWX
  31	select ARCH_HAS_STRICT_MODULE_RWX
  32	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  33	select ARCH_HAS_SYNC_DMA_FOR_CPU
  34	select ARCH_HAS_SYSCALL_WRAPPER
  35	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
  36	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  37	select ARCH_HAVE_NMI_SAFE_CMPXCHG
  38	select ARCH_INLINE_READ_LOCK if !PREEMPT
  39	select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
  40	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
  41	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
  42	select ARCH_INLINE_READ_UNLOCK if !PREEMPT
  43	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
  44	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
  45	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
  46	select ARCH_INLINE_WRITE_LOCK if !PREEMPT
  47	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
  48	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
  49	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
  50	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
  51	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
  52	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
  53	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
  54	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
  55	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
  56	select ARCH_INLINE_SPIN_LOCK if !PREEMPT
  57	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
  58	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
  59	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
  60	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
  61	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
  62	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
  63	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
  64	select ARCH_KEEP_MEMBLOCK
  65	select ARCH_USE_CMPXCHG_LOCKREF
  66	select ARCH_USE_QUEUED_RWLOCKS
  67	select ARCH_USE_QUEUED_SPINLOCKS
  68	select ARCH_SUPPORTS_MEMORY_FAILURE
  69	select ARCH_SUPPORTS_ATOMIC_RMW
  70	select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
  71	select ARCH_SUPPORTS_NUMA_BALANCING
  72	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
  73	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
  74	select ARCH_WANT_FRAME_POINTERS
  75	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
  76	select ARCH_HAS_UBSAN_SANITIZE_ALL
  77	select ARM_AMBA
  78	select ARM_ARCH_TIMER
  79	select ARM_GIC
  80	select AUDIT_ARCH_COMPAT_GENERIC
  81	select ARM_GIC_V2M if PCI
  82	select ARM_GIC_V3
  83	select ARM_GIC_V3_ITS if PCI
  84	select ARM_PSCI_FW
  85	select BUILDTIME_EXTABLE_SORT
  86	select CLONE_BACKWARDS
  87	select COMMON_CLK
  88	select CPU_PM if (SUSPEND || CPU_IDLE)
  89	select CRC32
  90	select DCACHE_WORD_ACCESS
  91	select DMA_DIRECT_REMAP
  92	select EDAC_SUPPORT
  93	select FRAME_POINTER
  94	select GENERIC_ALLOCATOR
  95	select GENERIC_ARCH_TOPOLOGY
  96	select GENERIC_CLOCKEVENTS
  97	select GENERIC_CLOCKEVENTS_BROADCAST
  98	select GENERIC_CPU_AUTOPROBE
  99	select GENERIC_CPU_VULNERABILITIES
 100	select GENERIC_EARLY_IOREMAP
 101	select GENERIC_IDLE_POLL_SETUP
 102	select GENERIC_IRQ_MULTI_HANDLER
 103	select GENERIC_IRQ_PROBE
 104	select GENERIC_IRQ_SHOW
 105	select GENERIC_IRQ_SHOW_LEVEL
 106	select GENERIC_PCI_IOMAP
 107	select GENERIC_SCHED_CLOCK
 108	select GENERIC_SMP_IDLE_THREAD
 109	select GENERIC_STRNCPY_FROM_USER
 110	select GENERIC_STRNLEN_USER
 111	select GENERIC_TIME_VSYSCALL
 112	select GENERIC_GETTIMEOFDAY
 113	select HANDLE_DOMAIN_IRQ
 114	select HARDIRQS_SW_RESEND
 115	select HAVE_PCI
 116	select HAVE_ACPI_APEI if (ACPI && EFI)
 117	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 118	select HAVE_ARCH_AUDITSYSCALL
 119	select HAVE_ARCH_BITREVERSE
 120	select HAVE_ARCH_HUGE_VMAP
 121	select HAVE_ARCH_JUMP_LABEL
 122	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 123	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 124	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
 125	select HAVE_ARCH_KGDB
 126	select HAVE_ARCH_MMAP_RND_BITS
 127	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 128	select HAVE_ARCH_PREL32_RELOCATIONS
 129	select HAVE_ARCH_SECCOMP_FILTER
 130	select HAVE_ARCH_STACKLEAK
 131	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 132	select HAVE_ARCH_TRACEHOOK
 133	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 134	select HAVE_ARCH_VMAP_STACK
 135	select HAVE_ARM_SMCCC
 136	select HAVE_ASM_MODVERSIONS
 137	select HAVE_EBPF_JIT
 138	select HAVE_C_RECORDMCOUNT
 
 139	select HAVE_CMPXCHG_DOUBLE
 140	select HAVE_CMPXCHG_LOCAL
 141	select HAVE_CONTEXT_TRACKING
 142	select HAVE_DEBUG_BUGVERBOSE
 143	select HAVE_DEBUG_KMEMLEAK
 
 144	select HAVE_DMA_CONTIGUOUS
 145	select HAVE_DYNAMIC_FTRACE
 146	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 147	select HAVE_FAST_GUP
 148	select HAVE_FTRACE_MCOUNT_RECORD
 149	select HAVE_FUNCTION_TRACER
 150	select HAVE_FUNCTION_ERROR_INJECTION
 151	select HAVE_FUNCTION_GRAPH_TRACER
 152	select HAVE_GCC_PLUGINS
 153	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 154	select HAVE_IRQ_TIME_ACCOUNTING
 155	select HAVE_MEMBLOCK_NODE_MAP if NUMA
 156	select HAVE_NMI
 157	select HAVE_PATA_PLATFORM
 158	select HAVE_PERF_EVENTS
 159	select HAVE_PERF_REGS
 160	select HAVE_PERF_USER_STACK_DUMP
 161	select HAVE_REGS_AND_STACK_ACCESS_API
 162	select HAVE_FUNCTION_ARG_ACCESS_API
 163	select HAVE_RCU_TABLE_FREE
 164	select HAVE_RSEQ
 165	select HAVE_STACKPROTECTOR
 166	select HAVE_SYSCALL_TRACEPOINTS
 167	select HAVE_KPROBES
 168	select HAVE_KRETPROBES
 169	select HAVE_GENERIC_VDSO
 170	select IOMMU_DMA if IOMMU_SUPPORT
 171	select IRQ_DOMAIN
 172	select IRQ_FORCED_THREADING
 173	select MODULES_USE_ELF_RELA
 174	select NEED_DMA_MAP_STATE
 175	select NEED_SG_DMA_LENGTH
 176	select OF
 177	select OF_EARLY_FLATTREE
 178	select PCI_DOMAINS_GENERIC if PCI
 179	select PCI_ECAM if (ACPI && PCI)
 180	select PCI_SYSCALL if PCI
 181	select POWER_RESET
 182	select POWER_SUPPLY
 183	select REFCOUNT_FULL
 184	select SPARSE_IRQ
 185	select SWIOTLB
 186	select SYSCTL_EXCEPTION_TRACE
 187	select THREAD_INFO_IN_TASK
 
 188	help
 189	  ARM 64-bit (AArch64) Linux support.
 190
 191config 64BIT
 192	def_bool y
 193
 
 
 
 194config MMU
 195	def_bool y
 196
 197config ARM64_PAGE_SHIFT
 198	int
 199	default 16 if ARM64_64K_PAGES
 200	default 14 if ARM64_16K_PAGES
 201	default 12
 202
 203config ARM64_CONT_SHIFT
 204	int
 205	default 5 if ARM64_64K_PAGES
 206	default 7 if ARM64_16K_PAGES
 207	default 4
 208
 209config ARCH_MMAP_RND_BITS_MIN
 210       default 14 if ARM64_64K_PAGES
 211       default 16 if ARM64_16K_PAGES
 212       default 18
 213
 214# max bits determined by the following formula:
 215#  VA_BITS - PAGE_SHIFT - 3
 216config ARCH_MMAP_RND_BITS_MAX
 217       default 19 if ARM64_VA_BITS=36
 218       default 24 if ARM64_VA_BITS=39
 219       default 27 if ARM64_VA_BITS=42
 220       default 30 if ARM64_VA_BITS=47
 221       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 222       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 223       default 33 if ARM64_VA_BITS=48
 224       default 14 if ARM64_64K_PAGES
 225       default 16 if ARM64_16K_PAGES
 226       default 18
 227
 228config ARCH_MMAP_RND_COMPAT_BITS_MIN
 229       default 7 if ARM64_64K_PAGES
 230       default 9 if ARM64_16K_PAGES
 231       default 11
 232
 233config ARCH_MMAP_RND_COMPAT_BITS_MAX
 234       default 16
 235
 236config NO_IOPORT_MAP
 237	def_bool y if !PCI
 238
 239config STACKTRACE_SUPPORT
 240	def_bool y
 241
 242config ILLEGAL_POINTER_VALUE
 243	hex
 244	default 0xdead000000000000
 245
 246config LOCKDEP_SUPPORT
 247	def_bool y
 248
 249config TRACE_IRQFLAGS_SUPPORT
 250	def_bool y
 251
 
 
 
 252config GENERIC_BUG
 253	def_bool y
 254	depends on BUG
 255
 256config GENERIC_BUG_RELATIVE_POINTERS
 257	def_bool y
 258	depends on GENERIC_BUG
 259
 260config GENERIC_HWEIGHT
 261	def_bool y
 262
 263config GENERIC_CSUM
 264        def_bool y
 265
 266config GENERIC_CALIBRATE_DELAY
 267	def_bool y
 268
 269config ZONE_DMA32
 270	bool "Support DMA32 zone" if EXPERT
 271	default y
 
 
 
 
 
 
 
 
 272
 273config ARCH_ENABLE_MEMORY_HOTPLUG
 274	def_bool y
 275
 276config SMP
 277	def_bool y
 278
 
 
 
 
 
 
 279config KERNEL_MODE_NEON
 280	def_bool y
 281
 282config FIX_EARLYCON_MEM
 283	def_bool y
 284
 285config PGTABLE_LEVELS
 286	int
 287	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 288	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 289	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
 290	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 291	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 292	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 293
 294config ARCH_SUPPORTS_UPROBES
 295	def_bool y
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 296
 297config ARCH_PROC_KCORE_TEXT
 298	def_bool y
 299
 300config KASAN_SHADOW_OFFSET
 301	hex
 302	depends on KASAN
 303	default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
 304	default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
 305	default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
 306	default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
 307	default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
 308	default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
 309	default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
 310	default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
 311	default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
 312	default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
 313	default 0xffffffffffffffff
 314
 315source "arch/arm64/Kconfig.platforms"
 316
 317menu "Kernel Features"
 318
 319menu "ARM errata workarounds via the alternatives framework"
 320
 321config ARM64_WORKAROUND_CLEAN_CACHE
 322	bool
 323
 324config ARM64_ERRATUM_826319
 325	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 326	default y
 327	select ARM64_WORKAROUND_CLEAN_CACHE
 328	help
 329	  This option adds an alternative code sequence to work around ARM
 330	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 331	  AXI master interface and an L2 cache.
 332
 333	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 334	  and is unable to accept a certain write via this interface, it will
 335	  not progress on read data presented on the read data channel and the
 336	  system can deadlock.
 337
 338	  The workaround promotes data cache clean instructions to
 339	  data cache clean-and-invalidate.
 340	  Please note that this does not necessarily enable the workaround,
 341	  as it depends on the alternative framework, which will only patch
 342	  the kernel if an affected CPU is detected.
 343
 344	  If unsure, say Y.
 345
 346config ARM64_ERRATUM_827319
 347	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 348	default y
 349	select ARM64_WORKAROUND_CLEAN_CACHE
 350	help
 351	  This option adds an alternative code sequence to work around ARM
 352	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 353	  master interface and an L2 cache.
 354
 355	  Under certain conditions this erratum can cause a clean line eviction
 356	  to occur at the same time as another transaction to the same address
 357	  on the AMBA 5 CHI interface, which can cause data corruption if the
 358	  interconnect reorders the two transactions.
 359
 360	  The workaround promotes data cache clean instructions to
 361	  data cache clean-and-invalidate.
 362	  Please note that this does not necessarily enable the workaround,
 363	  as it depends on the alternative framework, which will only patch
 364	  the kernel if an affected CPU is detected.
 365
 366	  If unsure, say Y.
 367
 368config ARM64_ERRATUM_824069
 369	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 370	default y
 371	select ARM64_WORKAROUND_CLEAN_CACHE
 372	help
 373	  This option adds an alternative code sequence to work around ARM
 374	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 375	  to a coherent interconnect.
 376
 377	  If a Cortex-A53 processor is executing a store or prefetch for
 378	  write instruction at the same time as a processor in another
 379	  cluster is executing a cache maintenance operation to the same
 380	  address, then this erratum might cause a clean cache line to be
 381	  incorrectly marked as dirty.
 382
 383	  The workaround promotes data cache clean instructions to
 384	  data cache clean-and-invalidate.
 385	  Please note that this option does not necessarily enable the
 386	  workaround, as it depends on the alternative framework, which will
 387	  only patch the kernel if an affected CPU is detected.
 388
 389	  If unsure, say Y.
 390
 391config ARM64_ERRATUM_819472
 392	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 393	default y
 394	select ARM64_WORKAROUND_CLEAN_CACHE
 395	help
 396	  This option adds an alternative code sequence to work around ARM
 397	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 398	  present when it is connected to a coherent interconnect.
 399
 400	  If the processor is executing a load and store exclusive sequence at
 401	  the same time as a processor in another cluster is executing a cache
 402	  maintenance operation to the same address, then this erratum might
 403	  cause data corruption.
 404
 405	  The workaround promotes data cache clean instructions to
 406	  data cache clean-and-invalidate.
 407	  Please note that this does not necessarily enable the workaround,
 408	  as it depends on the alternative framework, which will only patch
 409	  the kernel if an affected CPU is detected.
 410
 411	  If unsure, say Y.
 412
 413config ARM64_ERRATUM_832075
 414	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 415	default y
 416	help
 417	  This option adds an alternative code sequence to work around ARM
 418	  erratum 832075 on Cortex-A57 parts up to r1p2.
 419
 420	  Affected Cortex-A57 parts might deadlock when exclusive load/store
 421	  instructions to Write-Back memory are mixed with Device loads.
 422
 423	  The workaround is to promote device loads to use Load-Acquire
 424	  semantics.
 425	  Please note that this does not necessarily enable the workaround,
 426	  as it depends on the alternative framework, which will only patch
 427	  the kernel if an affected CPU is detected.
 428
 429	  If unsure, say Y.
 430
 431config ARM64_ERRATUM_834220
 432	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 433	depends on KVM
 434	default y
 435	help
 436	  This option adds an alternative code sequence to work around ARM
 437	  erratum 834220 on Cortex-A57 parts up to r1p2.
 438
 439	  Affected Cortex-A57 parts might report a Stage 2 translation
 440	  fault as the result of a Stage 1 fault for load crossing a
 441	  page boundary when there is a permission or device memory
 442	  alignment fault at Stage 1 and a translation fault at Stage 2.
 443
 444	  The workaround is to verify that the Stage 1 translation
 445	  doesn't generate a fault before handling the Stage 2 fault.
 446	  Please note that this does not necessarily enable the workaround,
 447	  as it depends on the alternative framework, which will only patch
 448	  the kernel if an affected CPU is detected.
 449
 450	  If unsure, say Y.
 451
 452config ARM64_ERRATUM_845719
 453	bool "Cortex-A53: 845719: a load might read incorrect data"
 454	depends on COMPAT
 455	default y
 456	help
 457	  This option adds an alternative code sequence to work around ARM
 458	  erratum 845719 on Cortex-A53 parts up to r0p4.
 459
 460	  When running a compat (AArch32) userspace on an affected Cortex-A53
 461	  part, a load at EL0 from a virtual address that matches the bottom 32
 462	  bits of the virtual address used by a recent load at (AArch64) EL1
 463	  might return incorrect data.
 464
 465	  The workaround is to write the contextidr_el1 register on exception
 466	  return to a 32-bit task.
 467	  Please note that this does not necessarily enable the workaround,
 468	  as it depends on the alternative framework, which will only patch
 469	  the kernel if an affected CPU is detected.
 470
 471	  If unsure, say Y.
 472
 473config ARM64_ERRATUM_843419
 474	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 
 475	default y
 476	select ARM64_MODULE_PLTS if MODULES
 477	help
 478	  This option links the kernel with '--fix-cortex-a53-843419' and
 479	  enables PLT support to replace certain ADRP instructions, which can
 480	  cause subsequent memory accesses to use an incorrect address on
 481	  Cortex-A53 parts up to r0p4.
 482
 483	  If unsure, say Y.
 484
 485config ARM64_ERRATUM_1024718
 486	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
 487	default y
 488	help
 489	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 490
 491	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
 492	  update of the hardware dirty bit when the DBM/AP bits are updated
 493	  without a break-before-make. The workaround is to disable the usage
 494	  of hardware DBM locally on the affected cores. CPUs not affected by
 495	  this erratum will continue to use the feature.
 496
 497	  If unsure, say Y.
 498
 499config ARM64_ERRATUM_1418040
 500	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
 501	default y
 502	depends on COMPAT
 503	help
 504	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
 505	  errata 1188873 and 1418040.
 506
 507	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
 508	  cause register corruption when accessing the timer registers
 509	  from AArch32 userspace.
 510
 511	  If unsure, say Y.
 512
 513config ARM64_ERRATUM_1165522
 514	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 515	default y
 516	help
 517	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
 518
 519	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
 520	  corrupted TLBs by speculating an AT instruction during a guest
 521	  context switch.
 522
 523	  If unsure, say Y.
 524
 525config ARM64_ERRATUM_1286807
 526	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
 527	default y
 528	select ARM64_WORKAROUND_REPEAT_TLBI
 529	help
 530	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
 531
 532	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
 533	  address for a cacheable mapping of a location is being
 534	  accessed by a core while another core is remapping the virtual
 535	  address to a new physical page using the recommended
 536	  break-before-make sequence, then under very rare circumstances
 537	  TLBI+DSB completes before a read using the translation being
 538	  invalidated has been observed by other observers. The
 539	  workaround repeats the TLBI+DSB operation.
 540
 541	  If unsure, say Y.
 542
 543config ARM64_ERRATUM_1463225
 544	bool "Cortex-A76: Software Step might prevent interrupt recognition"
 545	default y
 546	help
 547	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
 548
 549	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
 550	  of a system call instruction (SVC) can prevent recognition of
 551	  subsequent interrupts when software stepping is disabled in the
 552	  exception handler of the system call and either kernel debugging
 553	  is enabled or VHE is in use.
 554
 555	  Work around the erratum by triggering a dummy step exception
 556	  when handling a system call from a task that is being stepped
 557	  in a VHE configuration of the kernel.
 558
 559	  If unsure, say Y.
 560
 561config CAVIUM_ERRATUM_22375
 562	bool "Cavium erratum 22375, 24313"
 563	default y
 564	help
 565	  Enable workaround for errata 22375 and 24313.
 566
 567	  This implements two gicv3-its errata workarounds for ThunderX. Both
 568	  with a small impact affecting only ITS table allocation.
 569
 570	    erratum 22375: only alloc 8MB table size
 571	    erratum 24313: ignore memory access type
 572
 573	  The fixes are in ITS initialization and basically ignore memory access
 574	  type and table size provided by the TYPER and BASER registers.
 575
 576	  If unsure, say Y.
 577
 578config CAVIUM_ERRATUM_23144
 579	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
 580	depends on NUMA
 581	default y
 582	help
 583	  ITS SYNC command hang for cross node io and collections/cpu mapping.
 584
 585	  If unsure, say Y.
 586
 587config CAVIUM_ERRATUM_23154
 588	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 589	default y
 590	help
 591	  The gicv3 of ThunderX requires a modified version for
 592	  reading the IAR status to ensure data synchronization
 593	  (access to icc_iar1_el1 is not sync'ed before and after).
 594
 595	  If unsure, say Y.
 596
 597config CAVIUM_ERRATUM_27456
 598	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 599	default y
 600	help
 601	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 602	  instructions may cause the icache to become corrupted if it
 603	  contains data for a non-current ASID.  The fix is to
 604	  invalidate the icache when changing the mm context.
 605
 606	  If unsure, say Y.
 607
 608config CAVIUM_ERRATUM_30115
 609	bool "Cavium erratum 30115: Guest may disable interrupts in host"
 610	default y
 611	help
 612	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
 613	  1.2, and T83 Pass 1.0, KVM guest execution may disable
 614	  interrupts in host. Trapping both GICv3 group-0 and group-1
 615	  accesses sidesteps the issue.
 616
 617	  If unsure, say Y.
 618
 619config CAVIUM_TX2_ERRATUM_219
 620	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
 621	default y
 622	help
 623	  On Cavium ThunderX2, a load, store or prefetch instruction between a
 624	  TTBR update and the corresponding context synchronizing operation can
 625	  cause a spurious Data Abort to be delivered to any hardware thread in
 626	  the CPU core.
 627
 628	  Work around the issue by avoiding the problematic code sequence and
 629	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
 630	  trap handler performs the corresponding register access, skips the
 631	  instruction and ensures context synchronization by virtue of the
 632	  exception return.
 633
 634	  If unsure, say Y.
 635
 636config QCOM_FALKOR_ERRATUM_1003
 637	bool "Falkor E1003: Incorrect translation due to ASID change"
 638	default y
 639	help
 640	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
 641	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
 642	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
 643	  then only for entries in the walk cache, since the leaf translation
 644	  is unchanged. Work around the erratum by invalidating the walk cache
 645	  entries for the trampoline before entering the kernel proper.
 646
 647config ARM64_WORKAROUND_REPEAT_TLBI
 648	bool
 649
 650config QCOM_FALKOR_ERRATUM_1009
 651	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
 652	default y
 653	select ARM64_WORKAROUND_REPEAT_TLBI
 654	help
 655	  On Falkor v1, the CPU may prematurely complete a DSB following a
 656	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
 657	  one more time to fix the issue.
 658
 659	  If unsure, say Y.
 660
 661config QCOM_QDF2400_ERRATUM_0065
 662	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
 663	default y
 664	help
 665	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
 666	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
 667	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
 668
 669	  If unsure, say Y.
 670
 671config SOCIONEXT_SYNQUACER_PREITS
 672	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
 673	default y
 674	help
 675	  Socionext Synquacer SoCs implement a separate h/w block to generate
 676	  MSI doorbell writes with non-zero values for the device ID.
 677
 678	  If unsure, say Y.
 679
 680config HISILICON_ERRATUM_161600802
 681	bool "Hip07 161600802: Erroneous redistributor VLPI base"
 682	default y
 683	help
 684	  The HiSilicon Hip07 SoC uses the wrong redistributor base
 685	  when issued ITS commands such as VMOVP and VMAPP, and requires
 686	  a 128kB offset to be applied to the target address in this commands.
 687
 688	  If unsure, say Y.
 689
 690config QCOM_FALKOR_ERRATUM_E1041
 691	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
 692	default y
 693	help
 694	  Falkor CPU may speculatively fetch instructions from an improper
 695	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
 696	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
 697
 698	  If unsure, say Y.
 699
 700config FUJITSU_ERRATUM_010001
 701	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
 702	default y
 703	help
 704	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
 705	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
 706	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
 707	  This fault occurs under a specific hardware condition when a
 708	  load/store instruction performs an address translation using:
 709	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
 710	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
 711	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
 712	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
 713
 714	  The workaround is to ensure these bits are clear in TCR_ELx.
 715	  The workaround only affects the Fujitsu-A64FX.
 716
 717	  If unsure, say Y.
 718
 719endmenu
 720
 721
 722choice
 723	prompt "Page size"
 724	default ARM64_4K_PAGES
 725	help
 726	  Page size (translation granule) configuration.
 727
 728config ARM64_4K_PAGES
 729	bool "4KB"
 730	help
 731	  This feature enables 4KB pages support.
 732
 733config ARM64_16K_PAGES
 734	bool "16KB"
 735	help
 736	  The system will use 16KB pages support. AArch32 emulation
 737	  requires applications compiled with 16K (or a multiple of 16K)
 738	  aligned segments.
 739
 740config ARM64_64K_PAGES
 741	bool "64KB"
 742	help
 743	  This feature enables 64KB pages support (4KB by default)
 744	  allowing only two levels of page tables and faster TLB
 745	  look-up. AArch32 emulation requires applications compiled
 746	  with 64K aligned segments.
 747
 748endchoice
 749
 750choice
 751	prompt "Virtual address space size"
 752	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 753	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 754	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 755	help
 756	  Allows choosing one of multiple possible virtual address
 757	  space sizes. The level of translation table is determined by
 758	  a combination of page size and virtual address space size.
 759
 760config ARM64_VA_BITS_36
 761	bool "36-bit" if EXPERT
 762	depends on ARM64_16K_PAGES
 763
 764config ARM64_VA_BITS_39
 765	bool "39-bit"
 766	depends on ARM64_4K_PAGES
 767
 768config ARM64_VA_BITS_42
 769	bool "42-bit"
 770	depends on ARM64_64K_PAGES
 771
 772config ARM64_VA_BITS_47
 773	bool "47-bit"
 774	depends on ARM64_16K_PAGES
 775
 776config ARM64_VA_BITS_48
 777	bool "48-bit"
 778
 779config ARM64_VA_BITS_52
 780	bool "52-bit"
 781	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
 782	help
 783	  Enable 52-bit virtual addressing for userspace when explicitly
 784	  requested via a hint to mmap(). The kernel will also use 52-bit
 785	  virtual addresses for its own mappings (provided HW support for
 786	  this feature is available, otherwise it reverts to 48-bit).
 787
 788	  NOTE: Enabling 52-bit virtual addressing in conjunction with
 789	  ARMv8.3 Pointer Authentication will result in the PAC being
 790	  reduced from 7 bits to 3 bits, which may have a significant
 791	  impact on its susceptibility to brute-force attacks.
 792
 793	  If unsure, select 48-bit virtual addressing instead.
 794
 795endchoice
 796
 797config ARM64_FORCE_52BIT
 798	bool "Force 52-bit virtual addresses for userspace"
 799	depends on ARM64_VA_BITS_52 && EXPERT
 800	help
 801	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
 802	  to maintain compatibility with older software by providing 48-bit VAs
 803	  unless a hint is supplied to mmap.
 804
 805	  This configuration option disables the 48-bit compatibility logic, and
 806	  forces all userspace addresses to be 52-bit on HW that supports it. One
 807	  should only enable this configuration option for stress testing userspace
 808	  memory management code. If unsure say N here.
 809
 810config ARM64_VA_BITS
 811	int
 812	default 36 if ARM64_VA_BITS_36
 813	default 39 if ARM64_VA_BITS_39
 814	default 42 if ARM64_VA_BITS_42
 815	default 47 if ARM64_VA_BITS_47
 816	default 48 if ARM64_VA_BITS_48
 817	default 52 if ARM64_VA_BITS_52
 818
 819choice
 820	prompt "Physical address space size"
 821	default ARM64_PA_BITS_48
 822	help
 823	  Choose the maximum physical address range that the kernel will
 824	  support.
 825
 826config ARM64_PA_BITS_48
 827	bool "48-bit"
 828
 829config ARM64_PA_BITS_52
 830	bool "52-bit (ARMv8.2)"
 831	depends on ARM64_64K_PAGES
 832	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
 833	help
 834	  Enable support for a 52-bit physical address space, introduced as
 835	  part of the ARMv8.2-LPA extension.
 836
 837	  With this enabled, the kernel will also continue to work on CPUs that
 838	  do not support ARMv8.2-LPA, but with some added memory overhead (and
 839	  minor performance overhead).
 840
 841endchoice
 842
 843config ARM64_PA_BITS
 844	int
 845	default 48 if ARM64_PA_BITS_48
 846	default 52 if ARM64_PA_BITS_52
 847
 848config CPU_BIG_ENDIAN
 849       bool "Build big-endian kernel"
 850       help
 851         Say Y if you plan on running a kernel in big-endian mode.
 852
 853config SCHED_MC
 854	bool "Multi-core scheduler support"
 855	help
 856	  Multi-core scheduler support improves the CPU scheduler's decision
 857	  making when dealing with multi-core CPU chips at a cost of slightly
 858	  increased overhead in some places. If unsure say N here.
 859
 860config SCHED_SMT
 861	bool "SMT scheduler support"
 862	help
 863	  Improves the CPU scheduler's decision making when dealing with
 864	  MultiThreading at a cost of slightly increased overhead in some
 865	  places. If unsure say N here.
 866
 867config NR_CPUS
 868	int "Maximum number of CPUs (2-4096)"
 869	range 2 4096
 870	default "256"
 
 871
 872config HOTPLUG_CPU
 873	bool "Support for hot-pluggable CPUs"
 874	select GENERIC_IRQ_MIGRATION
 875	help
 876	  Say Y here to experiment with turning CPUs off and on.  CPUs
 877	  can be controlled through /sys/devices/system/cpu.
 878
 879# Common NUMA Features
 880config NUMA
 881	bool "Numa Memory Allocation and Scheduler Support"
 882	select ACPI_NUMA if ACPI
 883	select OF_NUMA
 884	help
 885	  Enable NUMA (Non Uniform Memory Access) support.
 886
 887	  The kernel will try to allocate memory used by a CPU on the
 888	  local memory of the CPU and add some more
 889	  NUMA awareness to the kernel.
 890
 891config NODES_SHIFT
 892	int "Maximum NUMA Nodes (as a power of 2)"
 893	range 1 10
 894	default "2"
 895	depends on NEED_MULTIPLE_NODES
 896	help
 897	  Specify the maximum number of NUMA Nodes available on the target
 898	  system.  Increases memory reserved to accommodate various tables.
 899
 900config USE_PERCPU_NUMA_NODE_ID
 901	def_bool y
 902	depends on NUMA
 903
 904config HAVE_SETUP_PER_CPU_AREA
 905	def_bool y
 906	depends on NUMA
 907
 908config NEED_PER_CPU_EMBED_FIRST_CHUNK
 909	def_bool y
 910	depends on NUMA
 911
 912config HOLES_IN_ZONE
 913	def_bool y
 914
 915source "kernel/Kconfig.hz"
 916
 917config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 918	def_bool y
 919
 920config ARCH_SPARSEMEM_ENABLE
 921	def_bool y
 922	select SPARSEMEM_VMEMMAP_ENABLE
 923
 924config ARCH_SPARSEMEM_DEFAULT
 925	def_bool ARCH_SPARSEMEM_ENABLE
 926
 927config ARCH_SELECT_MEMORY_MODEL
 928	def_bool ARCH_SPARSEMEM_ENABLE
 929
 930config ARCH_FLATMEM_ENABLE
 931	def_bool !NUMA
 932
 933config HAVE_ARCH_PFN_VALID
 934	def_bool y
 935
 936config HW_PERF_EVENTS
 937	def_bool y
 938	depends on ARM_PMU
 939
 940config SYS_SUPPORTS_HUGETLBFS
 941	def_bool y
 942
 943config ARCH_WANT_HUGE_PMD_SHARE
 
 
 
 
 944
 945config ARCH_HAS_CACHE_LINE_SIZE
 946	def_bool y
 947
 948config ARCH_ENABLE_SPLIT_PMD_PTLOCK
 949	def_bool y if PGTABLE_LEVELS > 2
 950
 951config SECCOMP
 952	bool "Enable seccomp to safely compute untrusted bytecode"
 953	---help---
 954	  This kernel feature is useful for number crunching applications
 955	  that may need to compute untrusted bytecode during their
 956	  execution. By using pipes or other transports made available to
 957	  the process as file descriptors supporting the read/write
 958	  syscalls, it's possible to isolate those applications in
 959	  their own address space using seccomp. Once seccomp is
 960	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 961	  and the task is only allowed to execute a few safe syscalls
 962	  defined by each seccomp mode.
 963
 964config PARAVIRT
 965	bool "Enable paravirtualization code"
 966	help
 967	  This changes the kernel so it can modify itself when it is run
 968	  under a hypervisor, potentially improving performance significantly
 969	  over full virtualization.
 970
 971config PARAVIRT_TIME_ACCOUNTING
 972	bool "Paravirtual steal time accounting"
 973	select PARAVIRT
 
 974	help
 975	  Select this option to enable fine granularity task steal time
 976	  accounting. Time spent executing other tasks in parallel with
 977	  the current vCPU is discounted from the vCPU power. To account for
 978	  that, there can be a small performance impact.
 979
 980	  If in doubt, say N here.
 981
 982config KEXEC
 983	depends on PM_SLEEP_SMP
 984	select KEXEC_CORE
 985	bool "kexec system call"
 986	---help---
 987	  kexec is a system call that implements the ability to shutdown your
 988	  current kernel, and to start another kernel.  It is like a reboot
 989	  but it is independent of the system firmware.   And like a reboot
 990	  you can start any kernel with it, not just Linux.
 991
 992config KEXEC_FILE
 993	bool "kexec file based system call"
 994	select KEXEC_CORE
 995	help
 996	  This is new version of kexec system call. This system call is
 997	  file based and takes file descriptors as system call argument
 998	  for kernel and initramfs as opposed to list of segments as
 999	  accepted by previous system call.
1000
1001config KEXEC_SIG
1002	bool "Verify kernel signature during kexec_file_load() syscall"
1003	depends on KEXEC_FILE
1004	help
1005	  Select this option to verify a signature with loaded kernel
1006	  image. If configured, any attempt of loading a image without
1007	  valid signature will fail.
1008
1009	  In addition to that option, you need to enable signature
1010	  verification for the corresponding kernel image type being
1011	  loaded in order for this to work.
1012
1013config KEXEC_IMAGE_VERIFY_SIG
1014	bool "Enable Image signature verification support"
1015	default y
1016	depends on KEXEC_SIG
1017	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1018	help
1019	  Enable Image signature verification support.
1020
1021comment "Support for PE file signature verification disabled"
1022	depends on KEXEC_SIG
1023	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1024
1025config CRASH_DUMP
1026	bool "Build kdump crash kernel"
1027	help
1028	  Generate crash dump after being started by kexec. This should
1029	  be normally only set in special crash dump kernels which are
1030	  loaded in the main kernel with kexec-tools into a specially
1031	  reserved region and then later executed after a crash by
1032	  kdump/kexec.
1033
1034	  For more details see Documentation/admin-guide/kdump/kdump.rst
1035
1036config XEN_DOM0
1037	def_bool y
1038	depends on XEN
1039
1040config XEN
1041	bool "Xen guest support on ARM64"
1042	depends on ARM64 && OF
1043	select SWIOTLB_XEN
1044	select PARAVIRT
1045	help
1046	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1047
1048config FORCE_MAX_ZONEORDER
1049	int
1050	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1051	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1052	default "11"
1053	help
1054	  The kernel memory allocator divides physically contiguous memory
1055	  blocks into "zones", where each zone is a power of two number of
1056	  pages.  This option selects the largest power of two that the kernel
1057	  keeps in the memory allocator.  If you need to allocate very large
1058	  blocks of physically contiguous memory, then you may need to
1059	  increase this value.
1060
1061	  This config option is actually maximum order plus one. For example,
1062	  a value of 11 means that the largest free memory block is 2^10 pages.
1063
1064	  We make sure that we can allocate upto a HugePage size for each configuration.
1065	  Hence we have :
1066		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1067
1068	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1069	  4M allocations matching the default size used by generic code.
1070
1071config UNMAP_KERNEL_AT_EL0
1072	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1073	default y
1074	help
1075	  Speculation attacks against some high-performance processors can
1076	  be used to bypass MMU permission checks and leak kernel data to
1077	  userspace. This can be defended against by unmapping the kernel
1078	  when running in userspace, mapping it back in on exception entry
1079	  via a trampoline page in the vector table.
1080
1081	  If unsure, say Y.
1082
1083config HARDEN_BRANCH_PREDICTOR
1084	bool "Harden the branch predictor against aliasing attacks" if EXPERT
1085	default y
1086	help
1087	  Speculation attacks against some high-performance processors rely on
1088	  being able to manipulate the branch predictor for a victim context by
1089	  executing aliasing branches in the attacker context.  Such attacks
1090	  can be partially mitigated against by clearing internal branch
1091	  predictor state and limiting the prediction logic in some situations.
1092
1093	  This config option will take CPU-specific actions to harden the
1094	  branch predictor against aliasing attacks and may rely on specific
1095	  instruction sequences or control bits being set by the system
1096	  firmware.
1097
1098	  If unsure, say Y.
1099
1100config HARDEN_EL2_VECTORS
1101	bool "Harden EL2 vector mapping against system register leak" if EXPERT
1102	default y
1103	help
1104	  Speculation attacks against some high-performance processors can
1105	  be used to leak privileged information such as the vector base
1106	  register, resulting in a potential defeat of the EL2 layout
1107	  randomization.
1108
1109	  This config option will map the vectors to a fixed location,
1110	  independent of the EL2 code mapping, so that revealing VBAR_EL2
1111	  to an attacker does not give away any extra information. This
1112	  only gets enabled on affected CPUs.
1113
1114	  If unsure, say Y.
1115
1116config ARM64_SSBD
1117	bool "Speculative Store Bypass Disable" if EXPERT
1118	default y
1119	help
1120	  This enables mitigation of the bypassing of previous stores
1121	  by speculative loads.
1122
1123	  If unsure, say Y.
1124
1125config RODATA_FULL_DEFAULT_ENABLED
1126	bool "Apply r/o permissions of VM areas also to their linear aliases"
1127	default y
1128	help
1129	  Apply read-only attributes of VM areas to the linear alias of
1130	  the backing pages as well. This prevents code or read-only data
1131	  from being modified (inadvertently or intentionally) via another
1132	  mapping of the same memory page. This additional enhancement can
1133	  be turned off at runtime by passing rodata=[off|on] (and turned on
1134	  with rodata=full if this option is set to 'n')
1135
1136	  This requires the linear region to be mapped down to pages,
1137	  which may adversely affect performance in some cases.
1138
1139config ARM64_SW_TTBR0_PAN
1140	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1141	help
1142	  Enabling this option prevents the kernel from accessing
1143	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1144	  zeroed area and reserved ASID. The user access routines
1145	  restore the valid TTBR0_EL1 temporarily.
1146
1147config ARM64_TAGGED_ADDR_ABI
1148	bool "Enable the tagged user addresses syscall ABI"
1149	default y
1150	help
1151	  When this option is enabled, user applications can opt in to a
1152	  relaxed ABI via prctl() allowing tagged addresses to be passed
1153	  to system calls as pointer arguments. For details, see
1154	  Documentation/arm64/tagged-address-abi.rst.
1155
1156menuconfig COMPAT
1157	bool "Kernel support for 32-bit EL0"
1158	depends on ARM64_4K_PAGES || EXPERT
1159	select COMPAT_BINFMT_ELF if BINFMT_ELF
1160	select HAVE_UID16
1161	select OLD_SIGSUSPEND3
1162	select COMPAT_OLD_SIGACTION
1163	help
1164	  This option enables support for a 32-bit EL0 running under a 64-bit
1165	  kernel at EL1. AArch32-specific components such as system calls,
1166	  the user helper functions, VFP support and the ptrace interface are
1167	  handled appropriately by the kernel.
1168
1169	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1170	  that you will only be able to execute AArch32 binaries that were compiled
1171	  with page size aligned segments.
1172
1173	  If you want to execute 32-bit userspace applications, say Y.
1174
1175if COMPAT
1176
1177config KUSER_HELPERS
1178	bool "Enable kuser helpers page for 32-bit applications"
1179	default y
1180	help
1181	  Warning: disabling this option may break 32-bit user programs.
1182
1183	  Provide kuser helpers to compat tasks. The kernel provides
1184	  helper code to userspace in read only form at a fixed location
1185	  to allow userspace to be independent of the CPU type fitted to
1186	  the system. This permits binaries to be run on ARMv4 through
1187	  to ARMv8 without modification.
1188
1189	  See Documentation/arm/kernel_user_helpers.rst for details.
1190
1191	  However, the fixed address nature of these helpers can be used
1192	  by ROP (return orientated programming) authors when creating
1193	  exploits.
1194
1195	  If all of the binaries and libraries which run on your platform
1196	  are built specifically for your platform, and make no use of
1197	  these helpers, then you can turn this option off to hinder
1198	  such exploits. However, in that case, if a binary or library
1199	  relying on those helpers is run, it will not function correctly.
1200
1201	  Say N here only if you are absolutely certain that you do not
1202	  need these helpers; otherwise, the safe option is to say Y.
1203
1204config COMPAT_VDSO
1205	bool "Enable vDSO for 32-bit applications"
1206	depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1207	select GENERIC_COMPAT_VDSO
1208	default y
1209	help
1210	  Place in the process address space of 32-bit applications an
1211	  ELF shared object providing fast implementations of gettimeofday
1212	  and clock_gettime.
1213
1214	  You must have a 32-bit build of glibc 2.22 or later for programs
1215	  to seamlessly take advantage of this.
1216
1217menuconfig ARMV8_DEPRECATED
1218	bool "Emulate deprecated/obsolete ARMv8 instructions"
1219	depends on SYSCTL
1220	help
1221	  Legacy software support may require certain instructions
1222	  that have been deprecated or obsoleted in the architecture.
1223
1224	  Enable this config to enable selective emulation of these
1225	  features.
1226
1227	  If unsure, say Y
1228
1229if ARMV8_DEPRECATED
1230
1231config SWP_EMULATION
1232	bool "Emulate SWP/SWPB instructions"
1233	help
1234	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1235	  they are always undefined. Say Y here to enable software
1236	  emulation of these instructions for userspace using LDXR/STXR.
1237
1238	  In some older versions of glibc [<=2.8] SWP is used during futex
1239	  trylock() operations with the assumption that the code will not
1240	  be preempted. This invalid assumption may be more likely to fail
1241	  with SWP emulation enabled, leading to deadlock of the user
1242	  application.
1243
1244	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1245	  on an external transaction monitoring block called a global
1246	  monitor to maintain update atomicity. If your system does not
1247	  implement a global monitor, this option can cause programs that
1248	  perform SWP operations to uncached memory to deadlock.
1249
1250	  If unsure, say Y
1251
1252config CP15_BARRIER_EMULATION
1253	bool "Emulate CP15 Barrier instructions"
1254	help
1255	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1256	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1257	  strongly recommended to use the ISB, DSB, and DMB
1258	  instructions instead.
1259
1260	  Say Y here to enable software emulation of these
1261	  instructions for AArch32 userspace code. When this option is
1262	  enabled, CP15 barrier usage is traced which can help
1263	  identify software that needs updating.
1264
1265	  If unsure, say Y
1266
1267config SETEND_EMULATION
1268	bool "Emulate SETEND instruction"
1269	help
1270	  The SETEND instruction alters the data-endianness of the
1271	  AArch32 EL0, and is deprecated in ARMv8.
1272
1273	  Say Y here to enable software emulation of the instruction
1274	  for AArch32 userspace code.
1275
1276	  Note: All the cpus on the system must have mixed endian support at EL0
1277	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1278	  endian - is hotplugged in after this feature has been enabled, there could
1279	  be unexpected results in the applications.
1280
1281	  If unsure, say Y
1282endif
1283
1284endif
1285
1286menu "ARMv8.1 architectural features"
1287
1288config ARM64_HW_AFDBM
1289	bool "Support for hardware updates of the Access and Dirty page flags"
1290	default y
1291	help
1292	  The ARMv8.1 architecture extensions introduce support for
1293	  hardware updates of the access and dirty information in page
1294	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1295	  capable processors, accesses to pages with PTE_AF cleared will
1296	  set this bit instead of raising an access flag fault.
1297	  Similarly, writes to read-only pages with the DBM bit set will
1298	  clear the read-only bit (AP[2]) instead of raising a
1299	  permission fault.
1300
1301	  Kernels built with this configuration option enabled continue
1302	  to work on pre-ARMv8.1 hardware and the performance impact is
1303	  minimal. If unsure, say Y.
1304
1305config ARM64_PAN
1306	bool "Enable support for Privileged Access Never (PAN)"
1307	default y
1308	help
1309	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1310	 prevents the kernel or hypervisor from accessing user-space (EL0)
1311	 memory directly.
1312
1313	 Choosing this option will cause any unprotected (not using
1314	 copy_to_user et al) memory access to fail with a permission fault.
1315
1316	 The feature is detected at runtime, and will remain as a 'nop'
1317	 instruction if the cpu does not implement the feature.
1318
1319config ARM64_LSE_ATOMICS
1320	bool "Atomic instructions"
1321	depends on JUMP_LABEL
1322	default y
1323	help
1324	  As part of the Large System Extensions, ARMv8.1 introduces new
1325	  atomic instructions that are designed specifically to scale in
1326	  very large systems.
1327
1328	  Say Y here to make use of these instructions for the in-kernel
1329	  atomic routines. This incurs a small overhead on CPUs that do
1330	  not support these instructions and requires the kernel to be
1331	  built with binutils >= 2.25 in order for the new instructions
1332	  to be used.
1333
1334config ARM64_VHE
1335	bool "Enable support for Virtualization Host Extensions (VHE)"
1336	default y
1337	help
1338	  Virtualization Host Extensions (VHE) allow the kernel to run
1339	  directly at EL2 (instead of EL1) on processors that support
1340	  it. This leads to better performance for KVM, as they reduce
1341	  the cost of the world switch.
1342
1343	  Selecting this option allows the VHE feature to be detected
1344	  at runtime, and does not affect processors that do not
1345	  implement this feature.
1346
1347endmenu
1348
1349menu "ARMv8.2 architectural features"
1350
1351config ARM64_UAO
1352	bool "Enable support for User Access Override (UAO)"
1353	default y
1354	help
1355	  User Access Override (UAO; part of the ARMv8.2 Extensions)
1356	  causes the 'unprivileged' variant of the load/store instructions to
1357	  be overridden to be privileged.
1358
1359	  This option changes get_user() and friends to use the 'unprivileged'
1360	  variant of the load/store instructions. This ensures that user-space
1361	  really did have access to the supplied memory. When addr_limit is
1362	  set to kernel memory the UAO bit will be set, allowing privileged
1363	  access to kernel memory.
1364
1365	  Choosing this option will cause copy_to_user() et al to use user-space
1366	  memory permissions.
1367
1368	  The feature is detected at runtime, the kernel will use the
1369	  regular load/store instructions if the cpu does not implement the
1370	  feature.
1371
1372config ARM64_PMEM
1373	bool "Enable support for persistent memory"
1374	select ARCH_HAS_PMEM_API
1375	select ARCH_HAS_UACCESS_FLUSHCACHE
1376	help
1377	  Say Y to enable support for the persistent memory API based on the
1378	  ARMv8.2 DCPoP feature.
1379
1380	  The feature is detected at runtime, and the kernel will use DC CVAC
1381	  operations if DC CVAP is not supported (following the behaviour of
1382	  DC CVAP itself if the system does not define a point of persistence).
1383
1384config ARM64_RAS_EXTN
1385	bool "Enable support for RAS CPU Extensions"
1386	default y
1387	help
1388	  CPUs that support the Reliability, Availability and Serviceability
1389	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1390	  errors, classify them and report them to software.
1391
1392	  On CPUs with these extensions system software can use additional
1393	  barriers to determine if faults are pending and read the
1394	  classification from a new set of registers.
1395
1396	  Selecting this feature will allow the kernel to use these barriers
1397	  and access the new registers if the system supports the extension.
1398	  Platform RAS features may additionally depend on firmware support.
1399
1400config ARM64_CNP
1401	bool "Enable support for Common Not Private (CNP) translations"
1402	default y
1403	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1404	help
1405	  Common Not Private (CNP) allows translation table entries to
1406	  be shared between different PEs in the same inner shareable
1407	  domain, so the hardware can use this fact to optimise the
1408	  caching of such entries in the TLB.
1409
1410	  Selecting this option allows the CNP feature to be detected
1411	  at runtime, and does not affect PEs that do not implement
1412	  this feature.
1413
1414endmenu
1415
1416menu "ARMv8.3 architectural features"
1417
1418config ARM64_PTR_AUTH
1419	bool "Enable support for pointer authentication"
1420	default y
1421	depends on !KVM || ARM64_VHE
1422	help
1423	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1424	  instructions for signing and authenticating pointers against secret
1425	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1426	  and other attacks.
1427
1428	  This option enables these instructions at EL0 (i.e. for userspace).
1429
1430	  Choosing this option will cause the kernel to initialise secret keys
1431	  for each process at exec() time, with these keys being
1432	  context-switched along with the process.
1433
1434	  The feature is detected at runtime. If the feature is not present in
1435	  hardware it will not be advertised to userspace/KVM guest nor will it
1436	  be enabled. However, KVM guest also require VHE mode and hence
1437	  CONFIG_ARM64_VHE=y option to use this feature.
1438
1439endmenu
1440
1441config ARM64_SVE
1442	bool "ARM Scalable Vector Extension support"
1443	default y
1444	depends on !KVM || ARM64_VHE
1445	help
1446	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1447	  execution state which complements and extends the SIMD functionality
1448	  of the base architecture to support much larger vectors and to enable
1449	  additional vectorisation opportunities.
1450
1451	  To enable use of this extension on CPUs that implement it, say Y.
1452
1453	  On CPUs that support the SVE2 extensions, this option will enable
1454	  those too.
1455
1456	  Note that for architectural reasons, firmware _must_ implement SVE
1457	  support when running on SVE capable hardware.  The required support
1458	  is present in:
1459
1460	    * version 1.5 and later of the ARM Trusted Firmware
1461	    * the AArch64 boot wrapper since commit 5e1261e08abf
1462	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1463
1464	  For other firmware implementations, consult the firmware documentation
1465	  or vendor.
1466
1467	  If you need the kernel to boot on SVE-capable hardware with broken
1468	  firmware, you may need to say N here until you get your firmware
1469	  fixed.  Otherwise, you may experience firmware panics or lockups when
1470	  booting the kernel.  If unsure and you are not observing these
1471	  symptoms, you should assume that it is safe to say Y.
1472
1473	  CPUs that support SVE are architecturally required to support the
1474	  Virtualization Host Extensions (VHE), so the kernel makes no
1475	  provision for supporting SVE alongside KVM without VHE enabled.
1476	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1477	  KVM in the same kernel image.
1478
1479config ARM64_MODULE_PLTS
1480	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1481	depends on MODULES
1482	select HAVE_MOD_ARCH_SPECIFIC
1483	help
1484	  Allocate PLTs when loading modules so that jumps and calls whose
1485	  targets are too far away for their relative offsets to be encoded
1486	  in the instructions themselves can be bounced via veneers in the
1487	  module's PLT. This allows modules to be allocated in the generic
1488	  vmalloc area after the dedicated module memory area has been
1489	  exhausted.
1490
1491	  When running with address space randomization (KASLR), the module
1492	  region itself may be too far away for ordinary relative jumps and
1493	  calls, and so in that case, module PLTs are required and cannot be
1494	  disabled.
1495
1496	  Specific errata workaround(s) might also force module PLTs to be
1497	  enabled (ARM64_ERRATUM_843419).
1498
1499config ARM64_PSEUDO_NMI
1500	bool "Support for NMI-like interrupts"
1501	select CONFIG_ARM_GIC_V3
1502	help
1503	  Adds support for mimicking Non-Maskable Interrupts through the use of
1504	  GIC interrupt priority. This support requires version 3 or later of
1505	  ARM GIC.
1506
1507	  This high priority configuration for interrupts needs to be
1508	  explicitly enabled by setting the kernel parameter
1509	  "irqchip.gicv3_pseudo_nmi" to 1.
1510
1511	  If unsure, say N
1512
1513if ARM64_PSEUDO_NMI
1514config ARM64_DEBUG_PRIORITY_MASKING
1515	bool "Debug interrupt priority masking"
1516	help
1517	  This adds runtime checks to functions enabling/disabling
1518	  interrupts when using priority masking. The additional checks verify
1519	  the validity of ICC_PMR_EL1 when calling concerned functions.
1520
1521	  If unsure, say N
1522endif
1523
1524config RELOCATABLE
1525	bool
1526	select ARCH_HAS_RELR
1527	help
1528	  This builds the kernel as a Position Independent Executable (PIE),
1529	  which retains all relocation metadata required to relocate the
1530	  kernel binary at runtime to a different virtual address than the
1531	  address it was linked at.
1532	  Since AArch64 uses the RELA relocation format, this requires a
1533	  relocation pass at runtime even if the kernel is loaded at the
1534	  same address it was linked at.
1535
1536config RANDOMIZE_BASE
1537	bool "Randomize the address of the kernel image"
1538	select ARM64_MODULE_PLTS if MODULES
1539	select RELOCATABLE
1540	help
1541	  Randomizes the virtual address at which the kernel image is
1542	  loaded, as a security feature that deters exploit attempts
1543	  relying on knowledge of the location of kernel internals.
1544
1545	  It is the bootloader's job to provide entropy, by passing a
1546	  random u64 value in /chosen/kaslr-seed at kernel entry.
1547
1548	  When booting via the UEFI stub, it will invoke the firmware's
1549	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1550	  to the kernel proper. In addition, it will randomise the physical
1551	  location of the kernel Image as well.
1552
1553	  If unsure, say N.
1554
1555config RANDOMIZE_MODULE_REGION_FULL
1556	bool "Randomize the module region over a 4 GB range"
1557	depends on RANDOMIZE_BASE
1558	default y
1559	help
1560	  Randomizes the location of the module region inside a 4 GB window
1561	  covering the core kernel. This way, it is less likely for modules
1562	  to leak information about the location of core kernel data structures
1563	  but it does imply that function calls between modules and the core
1564	  kernel will need to be resolved via veneers in the module PLT.
1565
1566	  When this option is not set, the module region will be randomized over
1567	  a limited range that contains the [_stext, _etext] interval of the
1568	  core kernel, so branch relocations are always in range.
1569
1570config CC_HAVE_STACKPROTECTOR_SYSREG
1571	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1572
1573config STACKPROTECTOR_PER_TASK
1574	def_bool y
1575	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1576
1577endmenu
1578
1579menu "Boot options"
1580
1581config ARM64_ACPI_PARKING_PROTOCOL
1582	bool "Enable support for the ARM64 ACPI parking protocol"
1583	depends on ACPI
1584	help
1585	  Enable support for the ARM64 ACPI parking protocol. If disabled
1586	  the kernel will not allow booting through the ARM64 ACPI parking
1587	  protocol even if the corresponding data is present in the ACPI
1588	  MADT table.
1589
1590config CMDLINE
1591	string "Default kernel command string"
1592	default ""
1593	help
1594	  Provide a set of default command-line options at build time by
1595	  entering them here. As a minimum, you should specify the the
1596	  root device (e.g. root=/dev/nfs).
1597
1598config CMDLINE_FORCE
1599	bool "Always use the default kernel command string"
1600	help
1601	  Always use the default kernel command string, even if the boot
1602	  loader passes other arguments to the kernel.
1603	  This is useful if you cannot or don't want to change the
1604	  command-line options your boot loader passes to the kernel.
1605
1606config EFI_STUB
1607	bool
1608
1609config EFI
1610	bool "UEFI runtime support"
1611	depends on OF && !CPU_BIG_ENDIAN
1612	depends on KERNEL_MODE_NEON
1613	select ARCH_SUPPORTS_ACPI
1614	select LIBFDT
1615	select UCS2_STRING
1616	select EFI_PARAMS_FROM_FDT
1617	select EFI_RUNTIME_WRAPPERS
1618	select EFI_STUB
1619	select EFI_ARMSTUB
1620	default y
1621	help
1622	  This option provides support for runtime services provided
1623	  by UEFI firmware (such as non-volatile variables, realtime
1624          clock, and platform reset). A UEFI stub is also provided to
1625	  allow the kernel to be booted as an EFI application. This
1626	  is only useful on systems that have UEFI firmware.
1627
1628config DMI
1629	bool "Enable support for SMBIOS (DMI) tables"
1630	depends on EFI
1631	default y
1632	help
1633	  This enables SMBIOS/DMI feature for systems.
1634
1635	  This option is only useful on systems that have UEFI firmware.
1636	  However, even with this option, the resultant kernel should
1637	  continue to boot on existing non-UEFI platforms.
1638
1639endmenu
1640
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1641config SYSVIPC_COMPAT
1642	def_bool y
1643	depends on COMPAT && SYSVIPC
1644
1645config ARCH_ENABLE_HUGEPAGE_MIGRATION
1646	def_bool y
1647	depends on HUGETLB_PAGE && MIGRATION
1648
1649menu "Power management options"
1650
1651source "kernel/power/Kconfig"
1652
1653config ARCH_HIBERNATION_POSSIBLE
1654	def_bool y
1655	depends on CPU_PM
1656
1657config ARCH_HIBERNATION_HEADER
1658	def_bool y
1659	depends on HIBERNATION
1660
1661config ARCH_SUSPEND_POSSIBLE
1662	def_bool y
1663
1664endmenu
1665
1666menu "CPU Power Management"
1667
1668source "drivers/cpuidle/Kconfig"
1669
1670source "drivers/cpufreq/Kconfig"
1671
1672endmenu
1673
 
 
 
 
1674source "drivers/firmware/Kconfig"
1675
1676source "drivers/acpi/Kconfig"
1677
 
 
1678source "arch/arm64/kvm/Kconfig"
1679
 
 
 
 
 
1680if CRYPTO
1681source "arch/arm64/crypto/Kconfig"
1682endif