1config ARM64
  2	def_bool y
  3	select ACPI_CCA_REQUIRED if ACPI
  4	select ACPI_GENERIC_GSI if ACPI
 
 
  5	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
  6	select ARCH_HAS_DEVMEM_IS_ALLOWED
  7	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  8	select ARCH_HAS_ELF_RANDOMIZE
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  9	select ARCH_HAS_GCOV_PROFILE_ALL
 10	select ARCH_HAS_SG_CHAIN
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 11	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 12	select ARCH_USE_CMPXCHG_LOCKREF
 
 
 
 
 
 
 
 
 
 
 
 
 13	select ARCH_SUPPORTS_ATOMIC_RMW
 14	select ARCH_WANT_OPTIONAL_GPIOLIB
 15	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 
 
 
 16	select ARCH_WANT_FRAME_POINTERS
 
 
 
 17	select ARCH_HAS_UBSAN_SANITIZE_ALL
 18	select ARM_AMBA
 19	select ARM_ARCH_TIMER
 20	select ARM_GIC
 21	select AUDIT_ARCH_COMPAT_GENERIC
 22	select ARM_GIC_V2M if PCI_MSI
 23	select ARM_GIC_V3
 24	select ARM_GIC_V3_ITS if PCI_MSI
 25	select ARM_PSCI_FW
 26	select BUILDTIME_EXTABLE_SORT
 27	select CLONE_BACKWARDS
 28	select COMMON_CLK
 29	select CPU_PM if (SUSPEND || CPU_IDLE)
 
 30	select DCACHE_WORD_ACCESS
 
 31	select EDAC_SUPPORT
 32	select FRAME_POINTER
 33	select GENERIC_ALLOCATOR
 34	select GENERIC_CLOCKEVENTS
 35	select GENERIC_CLOCKEVENTS_BROADCAST
 36	select GENERIC_CPU_AUTOPROBE
 
 37	select GENERIC_EARLY_IOREMAP
 
 38	select GENERIC_IDLE_POLL_SETUP
 
 39	select GENERIC_IRQ_PROBE
 40	select GENERIC_IRQ_SHOW
 41	select GENERIC_IRQ_SHOW_LEVEL
 
 42	select GENERIC_PCI_IOMAP
 
 43	select GENERIC_SCHED_CLOCK
 44	select GENERIC_SMP_IDLE_THREAD
 45	select GENERIC_STRNCPY_FROM_USER
 46	select GENERIC_STRNLEN_USER
 47	select GENERIC_TIME_VSYSCALL
 
 
 48	select HANDLE_DOMAIN_IRQ
 49	select HARDIRQS_SW_RESEND
 
 
 
 
 50	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 51	select HAVE_ARCH_AUDITSYSCALL
 52	select HAVE_ARCH_BITREVERSE
 
 53	select HAVE_ARCH_HUGE_VMAP
 54	select HAVE_ARCH_JUMP_LABEL
 55	select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 
 
 
 
 
 56	select HAVE_ARCH_KGDB
 57	select HAVE_ARCH_MMAP_RND_BITS
 58	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 
 
 
 59	select HAVE_ARCH_SECCOMP_FILTER
 
 
 60	select HAVE_ARCH_TRACEHOOK
 61	select HAVE_BPF_JIT
 
 
 
 
 62	select HAVE_C_RECORDMCOUNT
 63	select HAVE_CC_STACKPROTECTOR
 64	select HAVE_CMPXCHG_DOUBLE
 65	select HAVE_CMPXCHG_LOCAL
 66	select HAVE_DEBUG_BUGVERBOSE
 67	select HAVE_DEBUG_KMEMLEAK
 68	select HAVE_DMA_API_DEBUG
 69	select HAVE_DMA_CONTIGUOUS
 70	select HAVE_DYNAMIC_FTRACE
 
 
 
 
 71	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 
 72	select HAVE_FTRACE_MCOUNT_RECORD
 73	select HAVE_FUNCTION_TRACER
 
 74	select HAVE_FUNCTION_GRAPH_TRACER
 75	select HAVE_GENERIC_DMA_COHERENT
 76	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 77	select HAVE_IRQ_TIME_ACCOUNTING
 78	select HAVE_MEMBLOCK
 79	select HAVE_PATA_PLATFORM
 80	select HAVE_PERF_EVENTS
 81	select HAVE_PERF_REGS
 82	select HAVE_PERF_USER_STACK_DUMP
 83	select HAVE_RCU_TABLE_FREE
 
 
 
 
 
 84	select HAVE_SYSCALL_TRACEPOINTS
 
 
 
 85	select IOMMU_DMA if IOMMU_SUPPORT
 86	select IRQ_DOMAIN
 87	select IRQ_FORCED_THREADING
 
 88	select MODULES_USE_ELF_RELA
 89	select NO_BOOTMEM
 
 90	select OF
 91	select OF_EARLY_FLATTREE
 92	select OF_RESERVED_MEM
 93	select PERF_USE_VMALLOC
 
 94	select POWER_RESET
 95	select POWER_SUPPLY
 96	select RTC_LIB
 97	select SPARSE_IRQ
 
 98	select SYSCTL_EXCEPTION_TRACE
 99	select HAVE_CONTEXT_TRACKING
100	select HAVE_ARM_SMCCC
101	help
102	  ARM 64-bit (AArch64) Linux support.
103
104config 64BIT
105	def_bool y
106
107config ARCH_PHYS_ADDR_T_64BIT
108	def_bool y
109
110config MMU
111	def_bool y
112
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
113config ARCH_MMAP_RND_BITS_MIN
114       default 14 if ARM64_64K_PAGES
115       default 16 if ARM64_16K_PAGES
116       default 18
117
118# max bits determined by the following formula:
119#  VA_BITS - PAGE_SHIFT - 3
120config ARCH_MMAP_RND_BITS_MAX
121       default 19 if ARM64_VA_BITS=36
122       default 24 if ARM64_VA_BITS=39
123       default 27 if ARM64_VA_BITS=42
124       default 30 if ARM64_VA_BITS=47
125       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
126       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
127       default 33 if ARM64_VA_BITS=48
128       default 14 if ARM64_64K_PAGES
129       default 16 if ARM64_16K_PAGES
130       default 18
131
132config ARCH_MMAP_RND_COMPAT_BITS_MIN
133       default 7 if ARM64_64K_PAGES
134       default 9 if ARM64_16K_PAGES
135       default 11
136
137config ARCH_MMAP_RND_COMPAT_BITS_MAX
138       default 16
139
140config NO_IOPORT_MAP
141	def_bool y if !PCI
142
143config STACKTRACE_SUPPORT
144	def_bool y
145
146config ILLEGAL_POINTER_VALUE
147	hex
148	default 0xdead000000000000
149
150config LOCKDEP_SUPPORT
151	def_bool y
152
153config TRACE_IRQFLAGS_SUPPORT
154	def_bool y
155
156config RWSEM_XCHGADD_ALGORITHM
157	def_bool y
158
159config GENERIC_BUG
160	def_bool y
161	depends on BUG
162
163config GENERIC_BUG_RELATIVE_POINTERS
164	def_bool y
165	depends on GENERIC_BUG
166
167config GENERIC_HWEIGHT
168	def_bool y
169
170config GENERIC_CSUM
171        def_bool y
172
173config GENERIC_CALIBRATE_DELAY
174	def_bool y
175
176config ZONE_DMA
177	def_bool y
178
179config HAVE_GENERIC_RCU_GUP
180	def_bool y
181
182config ARCH_DMA_ADDR_T_64BIT
183	def_bool y
184
185config NEED_DMA_MAP_STATE
186	def_bool y
187
188config NEED_SG_DMA_LENGTH
189	def_bool y
190
191config SMP
192	def_bool y
193
194config SWIOTLB
195	def_bool y
196
197config IOMMU_HELPER
198	def_bool SWIOTLB
199
200config KERNEL_MODE_NEON
201	def_bool y
202
203config FIX_EARLYCON_MEM
204	def_bool y
205
206config PGTABLE_LEVELS
207	int
208	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
209	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
210	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
211	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
212	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
213	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
214
215source "init/Kconfig"
216
217source "kernel/Kconfig.freezer"
218
219source "arch/arm64/Kconfig.platforms"
220
221menu "Bus support"
222
223config PCI
224	bool "PCI support"
225	help
226	  This feature enables support for PCI bus system. If you say Y
227	  here, the kernel will include drivers and infrastructure code
228	  to support PCI bus devices.
229
230config PCI_DOMAINS
231	def_bool PCI
232
233config PCI_DOMAINS_GENERIC
234	def_bool PCI
235
236config PCI_SYSCALL
237	def_bool PCI
238
239source "drivers/pci/Kconfig"
 
 
 
 
 
 
 
 
 
 
 
 
 
240
241endmenu
242
243menu "Kernel Features"
244
245menu "ARM errata workarounds via the alternatives framework"
246
 
 
 
247config ARM64_ERRATUM_826319
248	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
249	default y
 
250	help
251	  This option adds an alternative code sequence to work around ARM
252	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
253	  AXI master interface and an L2 cache.
254
255	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
256	  and is unable to accept a certain write via this interface, it will
257	  not progress on read data presented on the read data channel and the
258	  system can deadlock.
259
260	  The workaround promotes data cache clean instructions to
261	  data cache clean-and-invalidate.
262	  Please note that this does not necessarily enable the workaround,
263	  as it depends on the alternative framework, which will only patch
264	  the kernel if an affected CPU is detected.
265
266	  If unsure, say Y.
267
268config ARM64_ERRATUM_827319
269	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
270	default y
 
271	help
272	  This option adds an alternative code sequence to work around ARM
273	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
274	  master interface and an L2 cache.
275
276	  Under certain conditions this erratum can cause a clean line eviction
277	  to occur at the same time as another transaction to the same address
278	  on the AMBA 5 CHI interface, which can cause data corruption if the
279	  interconnect reorders the two transactions.
280
281	  The workaround promotes data cache clean instructions to
282	  data cache clean-and-invalidate.
283	  Please note that this does not necessarily enable the workaround,
284	  as it depends on the alternative framework, which will only patch
285	  the kernel if an affected CPU is detected.
286
287	  If unsure, say Y.
288
289config ARM64_ERRATUM_824069
290	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
291	default y
 
292	help
293	  This option adds an alternative code sequence to work around ARM
294	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
295	  to a coherent interconnect.
296
297	  If a Cortex-A53 processor is executing a store or prefetch for
298	  write instruction at the same time as a processor in another
299	  cluster is executing a cache maintenance operation to the same
300	  address, then this erratum might cause a clean cache line to be
301	  incorrectly marked as dirty.
302
303	  The workaround promotes data cache clean instructions to
304	  data cache clean-and-invalidate.
305	  Please note that this option does not necessarily enable the
306	  workaround, as it depends on the alternative framework, which will
307	  only patch the kernel if an affected CPU is detected.
308
309	  If unsure, say Y.
310
311config ARM64_ERRATUM_819472
312	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
313	default y
 
314	help
315	  This option adds an alternative code sequence to work around ARM
316	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
317	  present when it is connected to a coherent interconnect.
318
319	  If the processor is executing a load and store exclusive sequence at
320	  the same time as a processor in another cluster is executing a cache
321	  maintenance operation to the same address, then this erratum might
322	  cause data corruption.
323
324	  The workaround promotes data cache clean instructions to
325	  data cache clean-and-invalidate.
326	  Please note that this does not necessarily enable the workaround,
327	  as it depends on the alternative framework, which will only patch
328	  the kernel if an affected CPU is detected.
329
330	  If unsure, say Y.
331
332config ARM64_ERRATUM_832075
333	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
334	default y
335	help
336	  This option adds an alternative code sequence to work around ARM
337	  erratum 832075 on Cortex-A57 parts up to r1p2.
338
339	  Affected Cortex-A57 parts might deadlock when exclusive load/store
340	  instructions to Write-Back memory are mixed with Device loads.
341
342	  The workaround is to promote device loads to use Load-Acquire
343	  semantics.
344	  Please note that this does not necessarily enable the workaround,
345	  as it depends on the alternative framework, which will only patch
346	  the kernel if an affected CPU is detected.
347
348	  If unsure, say Y.
349
350config ARM64_ERRATUM_834220
351	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
352	depends on KVM
353	default y
354	help
355	  This option adds an alternative code sequence to work around ARM
356	  erratum 834220 on Cortex-A57 parts up to r1p2.
357
358	  Affected Cortex-A57 parts might report a Stage 2 translation
359	  fault as the result of a Stage 1 fault for load crossing a
360	  page boundary when there is a permission or device memory
361	  alignment fault at Stage 1 and a translation fault at Stage 2.
362
363	  The workaround is to verify that the Stage 1 translation
364	  doesn't generate a fault before handling the Stage 2 fault.
365	  Please note that this does not necessarily enable the workaround,
366	  as it depends on the alternative framework, which will only patch
367	  the kernel if an affected CPU is detected.
368
369	  If unsure, say Y.
370
371config ARM64_ERRATUM_845719
372	bool "Cortex-A53: 845719: a load might read incorrect data"
373	depends on COMPAT
374	default y
375	help
376	  This option adds an alternative code sequence to work around ARM
377	  erratum 845719 on Cortex-A53 parts up to r0p4.
378
379	  When running a compat (AArch32) userspace on an affected Cortex-A53
380	  part, a load at EL0 from a virtual address that matches the bottom 32
381	  bits of the virtual address used by a recent load at (AArch64) EL1
382	  might return incorrect data.
383
384	  The workaround is to write the contextidr_el1 register on exception
385	  return to a 32-bit task.
386	  Please note that this does not necessarily enable the workaround,
387	  as it depends on the alternative framework, which will only patch
388	  the kernel if an affected CPU is detected.
389
390	  If unsure, say Y.
391
392config ARM64_ERRATUM_843419
393	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
394	depends on MODULES
395	default y
396	select ARM64_MODULE_CMODEL_LARGE
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
397	help
398	  This option builds kernel modules using the large memory model in
399	  order to avoid the use of the ADRP instruction, which can cause
400	  a subsequent memory access to use an incorrect address on Cortex-A53
401	  parts up to r0p4.
402
403	  Note that the kernel itself must be linked with a version of ld
404	  which fixes potentially affected ADRP instructions through the
405	  use of veneers.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
406
407	  If unsure, say Y.
408
409config CAVIUM_ERRATUM_22375
410	bool "Cavium erratum 22375, 24313"
411	default y
412	help
413	  Enable workaround for erratum 22375, 24313.
414
415	  This implements two gicv3-its errata workarounds for ThunderX. Both
416	  with small impact affecting only ITS table allocation.
417
418	    erratum 22375: only alloc 8MB table size
419	    erratum 24313: ignore memory access type
420
421	  The fixes are in ITS initialization and basically ignore memory access
422	  type and table size provided by the TYPER and BASER registers.
423
424	  If unsure, say Y.
425
 
 
 
 
 
 
 
 
 
426config CAVIUM_ERRATUM_23154
427	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
428	default y
429	help
430	  The gicv3 of ThunderX requires a modified version for
431	  reading the IAR status to ensure data synchronization
432	  (access to icc_iar1_el1 is not sync'ed before and after).
433
434	  If unsure, say Y.
435
436config CAVIUM_ERRATUM_27456
437	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
438	default y
439	help
440	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
441	  instructions may cause the icache to become corrupted if it
442	  contains data for a non-current ASID.  The fix is to
443	  invalidate the icache when changing the mm context.
444
445	  If unsure, say Y.
446
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
447endmenu
448
449
450choice
451	prompt "Page size"
452	default ARM64_4K_PAGES
453	help
454	  Page size (translation granule) configuration.
455
456config ARM64_4K_PAGES
457	bool "4KB"
458	help
459	  This feature enables 4KB pages support.
460
461config ARM64_16K_PAGES
462	bool "16KB"
463	help
464	  The system will use 16KB pages support. AArch32 emulation
465	  requires applications compiled with 16K (or a multiple of 16K)
466	  aligned segments.
467
468config ARM64_64K_PAGES
469	bool "64KB"
470	help
471	  This feature enables 64KB pages support (4KB by default)
472	  allowing only two levels of page tables and faster TLB
473	  look-up. AArch32 emulation requires applications compiled
474	  with 64K aligned segments.
475
476endchoice
477
478choice
479	prompt "Virtual address space size"
480	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
481	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
482	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
483	help
484	  Allows choosing one of multiple possible virtual address
485	  space sizes. The level of translation table is determined by
486	  a combination of page size and virtual address space size.
487
488config ARM64_VA_BITS_36
489	bool "36-bit" if EXPERT
490	depends on ARM64_16K_PAGES
491
492config ARM64_VA_BITS_39
493	bool "39-bit"
494	depends on ARM64_4K_PAGES
495
496config ARM64_VA_BITS_42
497	bool "42-bit"
498	depends on ARM64_64K_PAGES
499
500config ARM64_VA_BITS_47
501	bool "47-bit"
502	depends on ARM64_16K_PAGES
503
504config ARM64_VA_BITS_48
505	bool "48-bit"
506
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
507endchoice
508
 
 
 
 
 
 
 
 
 
 
 
 
 
509config ARM64_VA_BITS
510	int
511	default 36 if ARM64_VA_BITS_36
512	default 39 if ARM64_VA_BITS_39
513	default 42 if ARM64_VA_BITS_42
514	default 47 if ARM64_VA_BITS_47
515	default 48 if ARM64_VA_BITS_48
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
516
517config CPU_BIG_ENDIAN
518       bool "Build big-endian kernel"
519       help
520         Say Y if you plan on running a kernel in big-endian mode.
 
 
 
 
 
 
 
 
 
521
522config SCHED_MC
523	bool "Multi-core scheduler support"
524	help
525	  Multi-core scheduler support improves the CPU scheduler's decision
526	  making when dealing with multi-core CPU chips at a cost of slightly
527	  increased overhead in some places. If unsure say N here.
528
529config SCHED_SMT
530	bool "SMT scheduler support"
531	help
532	  Improves the CPU scheduler's decision making when dealing with
533	  MultiThreading at a cost of slightly increased overhead in some
534	  places. If unsure say N here.
535
536config NR_CPUS
537	int "Maximum number of CPUs (2-4096)"
538	range 2 4096
539	# These have to remain sorted largest to smallest
540	default "64"
541
542config HOTPLUG_CPU
543	bool "Support for hot-pluggable CPUs"
544	select GENERIC_IRQ_MIGRATION
545	help
546	  Say Y here to experiment with turning CPUs off and on.  CPUs
547	  can be controlled through /sys/devices/system/cpu.
548
549source kernel/Kconfig.preempt
550source kernel/Kconfig.hz
 
 
 
 
 
 
551
552config ARCH_SUPPORTS_DEBUG_PAGEALLOC
553	def_bool y
 
554
555config ARCH_HAS_HOLES_MEMORYMODEL
556	def_bool y if SPARSEMEM
 
 
 
 
 
 
557
558config ARCH_SPARSEMEM_ENABLE
559	def_bool y
560	select SPARSEMEM_VMEMMAP_ENABLE
561
562config ARCH_SPARSEMEM_DEFAULT
563	def_bool ARCH_SPARSEMEM_ENABLE
564
565config ARCH_SELECT_MEMORY_MODEL
566	def_bool ARCH_SPARSEMEM_ENABLE
567
568config HAVE_ARCH_PFN_VALID
569	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
570
571config HW_PERF_EVENTS
572	def_bool y
573	depends on ARM_PMU
574
575config SYS_SUPPORTS_HUGETLBFS
576	def_bool y
 
577
578config ARCH_WANT_HUGE_PMD_SHARE
579	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
580
581config HAVE_ARCH_TRANSPARENT_HUGEPAGE
582	def_bool y
 
 
583
584config ARCH_HAS_CACHE_LINE_SIZE
585	def_bool y
 
586
587source "mm/Kconfig"
 
588
589config SECCOMP
590	bool "Enable seccomp to safely compute untrusted bytecode"
591	---help---
592	  This kernel feature is useful for number crunching applications
593	  that may need to compute untrusted bytecode during their
594	  execution. By using pipes or other transports made available to
595	  the process as file descriptors supporting the read/write
596	  syscalls, it's possible to isolate those applications in
597	  their own address space using seccomp. Once seccomp is
598	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
599	  and the task is only allowed to execute a few safe syscalls
600	  defined by each seccomp mode.
601
602config PARAVIRT
603	bool "Enable paravirtualization code"
604	help
605	  This changes the kernel so it can modify itself when it is run
606	  under a hypervisor, potentially improving performance significantly
607	  over full virtualization.
608
609config PARAVIRT_TIME_ACCOUNTING
610	bool "Paravirtual steal time accounting"
611	select PARAVIRT
612	default n
613	help
614	  Select this option to enable fine granularity task steal time
615	  accounting. Time spent executing other tasks in parallel with
616	  the current vCPU is discounted from the vCPU power. To account for
617	  that, there can be a small performance impact.
618
619	  If in doubt, say N here.
620
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
621config XEN_DOM0
622	def_bool y
623	depends on XEN
624
625config XEN
626	bool "Xen guest support on ARM64"
627	depends on ARM64 && OF
628	select SWIOTLB_XEN
629	select PARAVIRT
630	help
631	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
632
633config FORCE_MAX_ZONEORDER
634	int
635	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
636	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
637	default "11"
638	help
639	  The kernel memory allocator divides physically contiguous memory
640	  blocks into "zones", where each zone is a power of two number of
641	  pages.  This option selects the largest power of two that the kernel
642	  keeps in the memory allocator.  If you need to allocate very large
643	  blocks of physically contiguous memory, then you may need to
644	  increase this value.
645
646	  This config option is actually maximum order plus one. For example,
647	  a value of 11 means that the largest free memory block is 2^10 pages.
648
649	  We make sure that we can allocate upto a HugePage size for each configuration.
650	  Hence we have :
651		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
652
653	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
654	  4M allocations matching the default size used by generic code.
655
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
656menuconfig ARMV8_DEPRECATED
657	bool "Emulate deprecated/obsolete ARMv8 instructions"
658	depends on COMPAT
659	help
660	  Legacy software support may require certain instructions
661	  that have been deprecated or obsoleted in the architecture.
662
663	  Enable this config to enable selective emulation of these
664	  features.
665
666	  If unsure, say Y
667
668if ARMV8_DEPRECATED
669
670config SWP_EMULATION
671	bool "Emulate SWP/SWPB instructions"
672	help
673	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
674	  they are always undefined. Say Y here to enable software
675	  emulation of these instructions for userspace using LDXR/STXR.
 
 
676
677	  In some older versions of glibc [<=2.8] SWP is used during futex
678	  trylock() operations with the assumption that the code will not
679	  be preempted. This invalid assumption may be more likely to fail
680	  with SWP emulation enabled, leading to deadlock of the user
681	  application.
682
683	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
684	  on an external transaction monitoring block called a global
685	  monitor to maintain update atomicity. If your system does not
686	  implement a global monitor, this option can cause programs that
687	  perform SWP operations to uncached memory to deadlock.
688
689	  If unsure, say Y
690
691config CP15_BARRIER_EMULATION
692	bool "Emulate CP15 Barrier instructions"
693	help
694	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
695	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
696	  strongly recommended to use the ISB, DSB, and DMB
697	  instructions instead.
698
699	  Say Y here to enable software emulation of these
700	  instructions for AArch32 userspace code. When this option is
701	  enabled, CP15 barrier usage is traced which can help
702	  identify software that needs updating.
 
703
704	  If unsure, say Y
705
706config SETEND_EMULATION
707	bool "Emulate SETEND instruction"
708	help
709	  The SETEND instruction alters the data-endianness of the
710	  AArch32 EL0, and is deprecated in ARMv8.
711
712	  Say Y here to enable software emulation of the instruction
713	  for AArch32 userspace code.
 
714
715	  Note: All the cpus on the system must have mixed endian support at EL0
716	  for this feature to be enabled. If a new CPU - which doesn't support mixed
717	  endian - is hotplugged in after this feature has been enabled, there could
718	  be unexpected results in the applications.
719
720	  If unsure, say Y
721endif
722
 
 
723menu "ARMv8.1 architectural features"
724
725config ARM64_HW_AFDBM
726	bool "Support for hardware updates of the Access and Dirty page flags"
727	default y
728	help
729	  The ARMv8.1 architecture extensions introduce support for
730	  hardware updates of the access and dirty information in page
731	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
732	  capable processors, accesses to pages with PTE_AF cleared will
733	  set this bit instead of raising an access flag fault.
734	  Similarly, writes to read-only pages with the DBM bit set will
735	  clear the read-only bit (AP[2]) instead of raising a
736	  permission fault.
737
738	  Kernels built with this configuration option enabled continue
739	  to work on pre-ARMv8.1 hardware and the performance impact is
740	  minimal. If unsure, say Y.
741
742config ARM64_PAN
743	bool "Enable support for Privileged Access Never (PAN)"
744	default y
745	help
746	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
747	 prevents the kernel or hypervisor from accessing user-space (EL0)
748	 memory directly.
749
750	 Choosing this option will cause any unprotected (not using
751	 copy_to_user et al) memory access to fail with a permission fault.
752
753	 The feature is detected at runtime, and will remain as a 'nop'
754	 instruction if the cpu does not implement the feature.
755
 
 
 
 
 
 
756config ARM64_LSE_ATOMICS
 
 
 
 
 
757	bool "Atomic instructions"
 
 
758	help
759	  As part of the Large System Extensions, ARMv8.1 introduces new
760	  atomic instructions that are designed specifically to scale in
761	  very large systems.
762
763	  Say Y here to make use of these instructions for the in-kernel
764	  atomic routines. This incurs a small overhead on CPUs that do
765	  not support these instructions and requires the kernel to be
766	  built with binutils >= 2.25.
 
767
768config ARM64_VHE
769	bool "Enable support for Virtualization Host Extensions (VHE)"
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
770	default y
771	help
772	  Virtualization Host Extensions (VHE) allow the kernel to run
773	  directly at EL2 (instead of EL1) on processors that support
774	  it. This leads to better performance for KVM, as they reduce
775	  the cost of the world switch.
 
 
 
 
 
 
 
776
777	  Selecting this option allows the VHE feature to be detected
778	  at runtime, and does not affect processors that do not
779	  implement this feature.
 
 
 
 
 
 
 
 
 
 
780
781endmenu
782
783menu "ARMv8.2 architectural features"
784
785config ARM64_UAO
786	bool "Enable support for User Access Override (UAO)"
787	default y
788	help
789	  User Access Override (UAO; part of the ARMv8.2 Extensions)
790	  causes the 'unprivileged' variant of the load/store instructions to
791	  be overriden to be privileged.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
792
793	  This option changes get_user() and friends to use the 'unprivileged'
794	  variant of the load/store instructions. This ensures that user-space
795	  really did have access to the supplied memory. When addr_limit is
796	  set to kernel memory the UAO bit will be set, allowing privileged
797	  access to kernel memory.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
798
799	  Choosing this option will cause copy_to_user() et al to use user-space
800	  memory permissions.
801
802	  The feature is detected at runtime, the kernel will use the
803	  regular load/store instructions if the cpu does not implement the
804	  feature.
805
806endmenu
807
808config ARM64_MODULE_CMODEL_LARGE
809	bool
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
810
811config ARM64_MODULE_PLTS
812	bool
813	select ARM64_MODULE_CMODEL_LARGE
814	select HAVE_MOD_ARCH_SPECIFIC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
815
816config RELOCATABLE
817	bool
 
 
818	help
819	  This builds the kernel as a Position Independent Executable (PIE),
820	  which retains all relocation metadata required to relocate the
821	  kernel binary at runtime to a different virtual address than the
822	  address it was linked at.
823	  Since AArch64 uses the RELA relocation format, this requires a
824	  relocation pass at runtime even if the kernel is loaded at the
825	  same address it was linked at.
826
827config RANDOMIZE_BASE
828	bool "Randomize the address of the kernel image"
829	select ARM64_MODULE_PLTS
830	select RELOCATABLE
831	help
832	  Randomizes the virtual address at which the kernel image is
833	  loaded, as a security feature that deters exploit attempts
834	  relying on knowledge of the location of kernel internals.
835
836	  It is the bootloader's job to provide entropy, by passing a
837	  random u64 value in /chosen/kaslr-seed at kernel entry.
838
839	  When booting via the UEFI stub, it will invoke the firmware's
840	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
841	  to the kernel proper. In addition, it will randomise the physical
842	  location of the kernel Image as well.
843
844	  If unsure, say N.
845
846config RANDOMIZE_MODULE_REGION_FULL
847	bool "Randomize the module region independently from the core kernel"
848	depends on RANDOMIZE_BASE
849	default y
850	help
851	  Randomizes the location of the module region without considering the
852	  location of the core kernel. This way, it is impossible for modules
853	  to leak information about the location of core kernel data structures
854	  but it does imply that function calls between modules and the core
855	  kernel will need to be resolved via veneers in the module PLT.
856
857	  When this option is not set, the module region will be randomized over
858	  a limited range that contains the [_stext, _etext] interval of the
859	  core kernel, so branch relocations are always in range.
 
 
 
 
 
 
 
 
 
 
860
861endmenu
862
863menu "Boot options"
864
865config ARM64_ACPI_PARKING_PROTOCOL
866	bool "Enable support for the ARM64 ACPI parking protocol"
867	depends on ACPI
868	help
869	  Enable support for the ARM64 ACPI parking protocol. If disabled
870	  the kernel will not allow booting through the ARM64 ACPI parking
871	  protocol even if the corresponding data is present in the ACPI
872	  MADT table.
873
874config CMDLINE
875	string "Default kernel command string"
876	default ""
877	help
878	  Provide a set of default command-line options at build time by
879	  entering them here. As a minimum, you should specify the the
880	  root device (e.g. root=/dev/nfs).
881
 
 
 
 
 
 
 
 
 
 
 
 
 
 
882config CMDLINE_FORCE
883	bool "Always use the default kernel command string"
884	help
885	  Always use the default kernel command string, even if the boot
886	  loader passes other arguments to the kernel.
887	  This is useful if you cannot or don't want to change the
888	  command-line options your boot loader passes to the kernel.
889
 
 
890config EFI_STUB
891	bool
892
893config EFI
894	bool "UEFI runtime support"
895	depends on OF && !CPU_BIG_ENDIAN
 
 
896	select LIBFDT
897	select UCS2_STRING
898	select EFI_PARAMS_FROM_FDT
899	select EFI_RUNTIME_WRAPPERS
900	select EFI_STUB
901	select EFI_ARMSTUB
 
902	default y
903	help
904	  This option provides support for runtime services provided
905	  by UEFI firmware (such as non-volatile variables, realtime
906          clock, and platform reset). A UEFI stub is also provided to
907	  allow the kernel to be booted as an EFI application. This
908	  is only useful on systems that have UEFI firmware.
909
910config DMI
911	bool "Enable support for SMBIOS (DMI) tables"
912	depends on EFI
913	default y
914	help
915	  This enables SMBIOS/DMI feature for systems.
916
917	  This option is only useful on systems that have UEFI firmware.
918	  However, even with this option, the resultant kernel should
919	  continue to boot on existing non-UEFI platforms.
920
921endmenu
922
923menu "Userspace binary formats"
924
925source "fs/Kconfig.binfmt"
926
927config COMPAT
928	bool "Kernel support for 32-bit EL0"
929	depends on ARM64_4K_PAGES || EXPERT
930	select COMPAT_BINFMT_ELF
931	select HAVE_UID16
932	select OLD_SIGSUSPEND3
933	select COMPAT_OLD_SIGACTION
934	help
935	  This option enables support for a 32-bit EL0 running under a 64-bit
936	  kernel at EL1. AArch32-specific components such as system calls,
937	  the user helper functions, VFP support and the ptrace interface are
938	  handled appropriately by the kernel.
939
940	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
941	  that you will only be able to execute AArch32 binaries that were compiled
942	  with page size aligned segments.
943
944	  If you want to execute 32-bit userspace applications, say Y.
945
946config SYSVIPC_COMPAT
947	def_bool y
948	depends on COMPAT && SYSVIPC
949
950endmenu
951
952menu "Power management options"
953
954source "kernel/power/Kconfig"
955
 
 
 
 
 
 
 
 
956config ARCH_SUSPEND_POSSIBLE
957	def_bool y
958
959endmenu
960
961menu "CPU Power Management"
962
963source "drivers/cpuidle/Kconfig"
964
965source "drivers/cpufreq/Kconfig"
966
967endmenu
968
969source "net/Kconfig"
970
971source "drivers/Kconfig"
972
973source "drivers/firmware/Kconfig"
974
975source "drivers/acpi/Kconfig"
976
977source "fs/Kconfig"
978
979source "arch/arm64/kvm/Kconfig"
980
981source "arch/arm64/Kconfig.debug"
982
983source "security/Kconfig"
984
985source "crypto/Kconfig"
986if CRYPTO
987source "arch/arm64/crypto/Kconfig"
988endif
989
990source "lib/Kconfig"

   1# SPDX-License-Identifier: GPL-2.0-only
   2config ARM64
   3	def_bool y
   4	select ACPI_CCA_REQUIRED if ACPI
   5	select ACPI_GENERIC_GSI if ACPI
   6	select ACPI_GTDT if ACPI
   7	select ACPI_IORT if ACPI
   8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   9	select ACPI_MCFG if (ACPI && PCI)
  10	select ACPI_SPCR_TABLE if ACPI
  11	select ACPI_PPTT if ACPI
  12	select ARCH_HAS_DEBUG_WX
  13	select ARCH_BINFMT_ELF_STATE
  14	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
  15	select ARCH_ENABLE_MEMORY_HOTPLUG
  16	select ARCH_ENABLE_MEMORY_HOTREMOVE
  17	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
  18	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
  19	select ARCH_HAS_CACHE_LINE_SIZE
  20	select ARCH_HAS_DEBUG_VIRTUAL
  21	select ARCH_HAS_DEBUG_VM_PGTABLE
  22	select ARCH_HAS_DMA_PREP_COHERENT
  23	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
  24	select ARCH_HAS_FAST_MULTIPLIER
  25	select ARCH_HAS_FORTIFY_SOURCE
  26	select ARCH_HAS_GCOV_PROFILE_ALL
  27	select ARCH_HAS_GIGANTIC_PAGE
  28	select ARCH_HAS_KCOV
  29	select ARCH_HAS_KEEPINITRD
  30	select ARCH_HAS_MEMBARRIER_SYNC_CORE
  31	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
  32	select ARCH_HAS_PTE_DEVMAP
  33	select ARCH_HAS_PTE_SPECIAL
  34	select ARCH_HAS_SETUP_DMA_OPS
  35	select ARCH_HAS_SET_DIRECT_MAP
  36	select ARCH_HAS_SET_MEMORY
  37	select ARCH_STACKWALK
  38	select ARCH_HAS_STRICT_KERNEL_RWX
  39	select ARCH_HAS_STRICT_MODULE_RWX
  40	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  41	select ARCH_HAS_SYNC_DMA_FOR_CPU
  42	select ARCH_HAS_SYSCALL_WRAPPER
  43	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
  44	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  45	select ARCH_HAS_ZONE_DMA_SET if EXPERT
  46	select ARCH_HAVE_ELF_PROT
  47	select ARCH_HAVE_NMI_SAFE_CMPXCHG
  48	select ARCH_INLINE_READ_LOCK if !PREEMPTION
  49	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
  50	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
  51	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
  52	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
  53	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
  54	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
  55	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
  56	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
  57	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
  58	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
  59	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
  60	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
  61	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
  62	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
  63	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
  64	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
  65	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
  66	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
  67	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
  68	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
  69	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
  70	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
  71	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
  72	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
  73	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
  74	select ARCH_KEEP_MEMBLOCK
  75	select ARCH_USE_CMPXCHG_LOCKREF
  76	select ARCH_USE_GNU_PROPERTY
  77	select ARCH_USE_MEMTEST
  78	select ARCH_USE_QUEUED_RWLOCKS
  79	select ARCH_USE_QUEUED_SPINLOCKS
  80	select ARCH_USE_SYM_ANNOTATIONS
  81	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
  82	select ARCH_SUPPORTS_HUGETLBFS
  83	select ARCH_SUPPORTS_MEMORY_FAILURE
  84	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
  85	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
  86	select ARCH_SUPPORTS_LTO_CLANG_THIN
  87	select ARCH_SUPPORTS_CFI_CLANG
  88	select ARCH_SUPPORTS_ATOMIC_RMW
  89	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
  90	select ARCH_SUPPORTS_NUMA_BALANCING
  91	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
  92	select ARCH_WANT_DEFAULT_BPF_JIT
  93	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
  94	select ARCH_WANT_FRAME_POINTERS
  95	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
  96	select ARCH_WANT_LD_ORPHAN_WARN
  97	select ARCH_WANTS_NO_INSTR
  98	select ARCH_HAS_UBSAN_SANITIZE_ALL
  99	select ARM_AMBA
 100	select ARM_ARCH_TIMER
 101	select ARM_GIC
 102	select AUDIT_ARCH_COMPAT_GENERIC
 103	select ARM_GIC_V2M if PCI
 104	select ARM_GIC_V3
 105	select ARM_GIC_V3_ITS if PCI
 106	select ARM_PSCI_FW
 107	select BUILDTIME_TABLE_SORT
 108	select CLONE_BACKWARDS
 109	select COMMON_CLK
 110	select CPU_PM if (SUSPEND || CPU_IDLE)
 111	select CRC32
 112	select DCACHE_WORD_ACCESS
 113	select DMA_DIRECT_REMAP
 114	select EDAC_SUPPORT
 115	select FRAME_POINTER
 116	select GENERIC_ALLOCATOR
 117	select GENERIC_ARCH_TOPOLOGY
 118	select GENERIC_CLOCKEVENTS_BROADCAST
 119	select GENERIC_CPU_AUTOPROBE
 120	select GENERIC_CPU_VULNERABILITIES
 121	select GENERIC_EARLY_IOREMAP
 122	select GENERIC_FIND_FIRST_BIT
 123	select GENERIC_IDLE_POLL_SETUP
 124	select GENERIC_IRQ_IPI
 125	select GENERIC_IRQ_PROBE
 126	select GENERIC_IRQ_SHOW
 127	select GENERIC_IRQ_SHOW_LEVEL
 128	select GENERIC_LIB_DEVMEM_IS_ALLOWED
 129	select GENERIC_PCI_IOMAP
 130	select GENERIC_PTDUMP
 131	select GENERIC_SCHED_CLOCK
 132	select GENERIC_SMP_IDLE_THREAD
 133	select GENERIC_STRNCPY_FROM_USER
 134	select GENERIC_STRNLEN_USER
 135	select GENERIC_TIME_VSYSCALL
 136	select GENERIC_GETTIMEOFDAY
 137	select GENERIC_VDSO_TIME_NS
 138	select HANDLE_DOMAIN_IRQ
 139	select HARDIRQS_SW_RESEND
 140	select HAVE_MOVE_PMD
 141	select HAVE_MOVE_PUD
 142	select HAVE_PCI
 143	select HAVE_ACPI_APEI if (ACPI && EFI)
 144	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 145	select HAVE_ARCH_AUDITSYSCALL
 146	select HAVE_ARCH_BITREVERSE
 147	select HAVE_ARCH_COMPILER_H
 148	select HAVE_ARCH_HUGE_VMAP
 149	select HAVE_ARCH_JUMP_LABEL
 150	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 151	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 152	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
 153	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
 154	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
 155	select HAVE_ARCH_KFENCE
 156	select HAVE_ARCH_KGDB
 157	select HAVE_ARCH_MMAP_RND_BITS
 158	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 159	select HAVE_ARCH_PFN_VALID
 160	select HAVE_ARCH_PREL32_RELOCATIONS
 161	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
 162	select HAVE_ARCH_SECCOMP_FILTER
 163	select HAVE_ARCH_STACKLEAK
 164	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 165	select HAVE_ARCH_TRACEHOOK
 166	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 167	select HAVE_ARCH_VMAP_STACK
 168	select HAVE_ARM_SMCCC
 169	select HAVE_ASM_MODVERSIONS
 170	select HAVE_EBPF_JIT
 171	select HAVE_C_RECORDMCOUNT
 
 172	select HAVE_CMPXCHG_DOUBLE
 173	select HAVE_CMPXCHG_LOCAL
 174	select HAVE_CONTEXT_TRACKING
 175	select HAVE_DEBUG_KMEMLEAK
 
 176	select HAVE_DMA_CONTIGUOUS
 177	select HAVE_DYNAMIC_FTRACE
 178	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
 179		if $(cc-option,-fpatchable-function-entry=2)
 180	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
 181		if DYNAMIC_FTRACE_WITH_REGS
 182	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 183	select HAVE_FAST_GUP
 184	select HAVE_FTRACE_MCOUNT_RECORD
 185	select HAVE_FUNCTION_TRACER
 186	select HAVE_FUNCTION_ERROR_INJECTION
 187	select HAVE_FUNCTION_GRAPH_TRACER
 188	select HAVE_GCC_PLUGINS
 189	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 190	select HAVE_IRQ_TIME_ACCOUNTING
 191	select HAVE_NMI
 192	select HAVE_PATA_PLATFORM
 193	select HAVE_PERF_EVENTS
 194	select HAVE_PERF_REGS
 195	select HAVE_PERF_USER_STACK_DUMP
 196	select HAVE_REGS_AND_STACK_ACCESS_API
 197	select HAVE_FUNCTION_ARG_ACCESS_API
 198	select HAVE_FUTEX_CMPXCHG if FUTEX
 199	select MMU_GATHER_RCU_TABLE_FREE
 200	select HAVE_RSEQ
 201	select HAVE_STACKPROTECTOR
 202	select HAVE_SYSCALL_TRACEPOINTS
 203	select HAVE_KPROBES
 204	select HAVE_KRETPROBES
 205	select HAVE_GENERIC_VDSO
 206	select IOMMU_DMA if IOMMU_SUPPORT
 207	select IRQ_DOMAIN
 208	select IRQ_FORCED_THREADING
 209	select KASAN_VMALLOC if KASAN_GENERIC
 210	select MODULES_USE_ELF_RELA
 211	select NEED_DMA_MAP_STATE
 212	select NEED_SG_DMA_LENGTH
 213	select OF
 214	select OF_EARLY_FLATTREE
 215	select PCI_DOMAINS_GENERIC if PCI
 216	select PCI_ECAM if (ACPI && PCI)
 217	select PCI_SYSCALL if PCI
 218	select POWER_RESET
 219	select POWER_SUPPLY
 
 220	select SPARSE_IRQ
 221	select SWIOTLB
 222	select SYSCTL_EXCEPTION_TRACE
 223	select THREAD_INFO_IN_TASK
 224	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
 225	help
 226	  ARM 64-bit (AArch64) Linux support.
 227
 228config 64BIT
 229	def_bool y
 230
 
 
 
 231config MMU
 232	def_bool y
 233
 234config ARM64_PAGE_SHIFT
 235	int
 236	default 16 if ARM64_64K_PAGES
 237	default 14 if ARM64_16K_PAGES
 238	default 12
 239
 240config ARM64_CONT_PTE_SHIFT
 241	int
 242	default 5 if ARM64_64K_PAGES
 243	default 7 if ARM64_16K_PAGES
 244	default 4
 245
 246config ARM64_CONT_PMD_SHIFT
 247	int
 248	default 5 if ARM64_64K_PAGES
 249	default 5 if ARM64_16K_PAGES
 250	default 4
 251
 252config ARCH_MMAP_RND_BITS_MIN
 253       default 14 if ARM64_64K_PAGES
 254       default 16 if ARM64_16K_PAGES
 255       default 18
 256
 257# max bits determined by the following formula:
 258#  VA_BITS - PAGE_SHIFT - 3
 259config ARCH_MMAP_RND_BITS_MAX
 260       default 19 if ARM64_VA_BITS=36
 261       default 24 if ARM64_VA_BITS=39
 262       default 27 if ARM64_VA_BITS=42
 263       default 30 if ARM64_VA_BITS=47
 264       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 265       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 266       default 33 if ARM64_VA_BITS=48
 267       default 14 if ARM64_64K_PAGES
 268       default 16 if ARM64_16K_PAGES
 269       default 18
 270
 271config ARCH_MMAP_RND_COMPAT_BITS_MIN
 272       default 7 if ARM64_64K_PAGES
 273       default 9 if ARM64_16K_PAGES
 274       default 11
 275
 276config ARCH_MMAP_RND_COMPAT_BITS_MAX
 277       default 16
 278
 279config NO_IOPORT_MAP
 280	def_bool y if !PCI
 281
 282config STACKTRACE_SUPPORT
 283	def_bool y
 284
 285config ILLEGAL_POINTER_VALUE
 286	hex
 287	default 0xdead000000000000
 288
 289config LOCKDEP_SUPPORT
 290	def_bool y
 291
 292config TRACE_IRQFLAGS_SUPPORT
 293	def_bool y
 294
 
 
 
 295config GENERIC_BUG
 296	def_bool y
 297	depends on BUG
 298
 299config GENERIC_BUG_RELATIVE_POINTERS
 300	def_bool y
 301	depends on GENERIC_BUG
 302
 303config GENERIC_HWEIGHT
 304	def_bool y
 305
 306config GENERIC_CSUM
 307        def_bool y
 308
 309config GENERIC_CALIBRATE_DELAY
 310	def_bool y
 311
 312config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
 
 
 
 
 
 
 
 
 
 
 
 
 313	def_bool y
 314
 315config SMP
 316	def_bool y
 317
 
 
 
 
 
 
 318config KERNEL_MODE_NEON
 319	def_bool y
 320
 321config FIX_EARLYCON_MEM
 322	def_bool y
 323
 324config PGTABLE_LEVELS
 325	int
 326	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 327	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 328	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
 329	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 330	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 331	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 332
 333config ARCH_SUPPORTS_UPROBES
 334	def_bool y
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 335
 336config ARCH_PROC_KCORE_TEXT
 337	def_bool y
 338
 339config BROKEN_GAS_INST
 340	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
 341
 342config KASAN_SHADOW_OFFSET
 343	hex
 344	depends on KASAN_GENERIC || KASAN_SW_TAGS
 345	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
 346	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
 347	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
 348	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
 349	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
 350	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
 351	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
 352	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
 353	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
 354	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
 355	default 0xffffffffffffffff
 356
 357source "arch/arm64/Kconfig.platforms"
 358
 359menu "Kernel Features"
 360
 361menu "ARM errata workarounds via the alternatives framework"
 362
 363config ARM64_WORKAROUND_CLEAN_CACHE
 364	bool
 365
 366config ARM64_ERRATUM_826319
 367	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 368	default y
 369	select ARM64_WORKAROUND_CLEAN_CACHE
 370	help
 371	  This option adds an alternative code sequence to work around ARM
 372	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 373	  AXI master interface and an L2 cache.
 374
 375	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 376	  and is unable to accept a certain write via this interface, it will
 377	  not progress on read data presented on the read data channel and the
 378	  system can deadlock.
 379
 380	  The workaround promotes data cache clean instructions to
 381	  data cache clean-and-invalidate.
 382	  Please note that this does not necessarily enable the workaround,
 383	  as it depends on the alternative framework, which will only patch
 384	  the kernel if an affected CPU is detected.
 385
 386	  If unsure, say Y.
 387
 388config ARM64_ERRATUM_827319
 389	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 390	default y
 391	select ARM64_WORKAROUND_CLEAN_CACHE
 392	help
 393	  This option adds an alternative code sequence to work around ARM
 394	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 395	  master interface and an L2 cache.
 396
 397	  Under certain conditions this erratum can cause a clean line eviction
 398	  to occur at the same time as another transaction to the same address
 399	  on the AMBA 5 CHI interface, which can cause data corruption if the
 400	  interconnect reorders the two transactions.
 401
 402	  The workaround promotes data cache clean instructions to
 403	  data cache clean-and-invalidate.
 404	  Please note that this does not necessarily enable the workaround,
 405	  as it depends on the alternative framework, which will only patch
 406	  the kernel if an affected CPU is detected.
 407
 408	  If unsure, say Y.
 409
 410config ARM64_ERRATUM_824069
 411	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 412	default y
 413	select ARM64_WORKAROUND_CLEAN_CACHE
 414	help
 415	  This option adds an alternative code sequence to work around ARM
 416	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 417	  to a coherent interconnect.
 418
 419	  If a Cortex-A53 processor is executing a store or prefetch for
 420	  write instruction at the same time as a processor in another
 421	  cluster is executing a cache maintenance operation to the same
 422	  address, then this erratum might cause a clean cache line to be
 423	  incorrectly marked as dirty.
 424
 425	  The workaround promotes data cache clean instructions to
 426	  data cache clean-and-invalidate.
 427	  Please note that this option does not necessarily enable the
 428	  workaround, as it depends on the alternative framework, which will
 429	  only patch the kernel if an affected CPU is detected.
 430
 431	  If unsure, say Y.
 432
 433config ARM64_ERRATUM_819472
 434	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 435	default y
 436	select ARM64_WORKAROUND_CLEAN_CACHE
 437	help
 438	  This option adds an alternative code sequence to work around ARM
 439	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 440	  present when it is connected to a coherent interconnect.
 441
 442	  If the processor is executing a load and store exclusive sequence at
 443	  the same time as a processor in another cluster is executing a cache
 444	  maintenance operation to the same address, then this erratum might
 445	  cause data corruption.
 446
 447	  The workaround promotes data cache clean instructions to
 448	  data cache clean-and-invalidate.
 449	  Please note that this does not necessarily enable the workaround,
 450	  as it depends on the alternative framework, which will only patch
 451	  the kernel if an affected CPU is detected.
 452
 453	  If unsure, say Y.
 454
 455config ARM64_ERRATUM_832075
 456	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 457	default y
 458	help
 459	  This option adds an alternative code sequence to work around ARM
 460	  erratum 832075 on Cortex-A57 parts up to r1p2.
 461
 462	  Affected Cortex-A57 parts might deadlock when exclusive load/store
 463	  instructions to Write-Back memory are mixed with Device loads.
 464
 465	  The workaround is to promote device loads to use Load-Acquire
 466	  semantics.
 467	  Please note that this does not necessarily enable the workaround,
 468	  as it depends on the alternative framework, which will only patch
 469	  the kernel if an affected CPU is detected.
 470
 471	  If unsure, say Y.
 472
 473config ARM64_ERRATUM_834220
 474	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 475	depends on KVM
 476	default y
 477	help
 478	  This option adds an alternative code sequence to work around ARM
 479	  erratum 834220 on Cortex-A57 parts up to r1p2.
 480
 481	  Affected Cortex-A57 parts might report a Stage 2 translation
 482	  fault as the result of a Stage 1 fault for load crossing a
 483	  page boundary when there is a permission or device memory
 484	  alignment fault at Stage 1 and a translation fault at Stage 2.
 485
 486	  The workaround is to verify that the Stage 1 translation
 487	  doesn't generate a fault before handling the Stage 2 fault.
 488	  Please note that this does not necessarily enable the workaround,
 489	  as it depends on the alternative framework, which will only patch
 490	  the kernel if an affected CPU is detected.
 491
 492	  If unsure, say Y.
 493
 494config ARM64_ERRATUM_845719
 495	bool "Cortex-A53: 845719: a load might read incorrect data"
 496	depends on COMPAT
 497	default y
 498	help
 499	  This option adds an alternative code sequence to work around ARM
 500	  erratum 845719 on Cortex-A53 parts up to r0p4.
 501
 502	  When running a compat (AArch32) userspace on an affected Cortex-A53
 503	  part, a load at EL0 from a virtual address that matches the bottom 32
 504	  bits of the virtual address used by a recent load at (AArch64) EL1
 505	  might return incorrect data.
 506
 507	  The workaround is to write the contextidr_el1 register on exception
 508	  return to a 32-bit task.
 509	  Please note that this does not necessarily enable the workaround,
 510	  as it depends on the alternative framework, which will only patch
 511	  the kernel if an affected CPU is detected.
 512
 513	  If unsure, say Y.
 514
 515config ARM64_ERRATUM_843419
 516	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 
 517	default y
 518	select ARM64_MODULE_PLTS if MODULES
 519	help
 520	  This option links the kernel with '--fix-cortex-a53-843419' and
 521	  enables PLT support to replace certain ADRP instructions, which can
 522	  cause subsequent memory accesses to use an incorrect address on
 523	  Cortex-A53 parts up to r0p4.
 524
 525	  If unsure, say Y.
 526
 527config ARM64_LD_HAS_FIX_ERRATUM_843419
 528	def_bool $(ld-option,--fix-cortex-a53-843419)
 529
 530config ARM64_ERRATUM_1024718
 531	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
 532	default y
 533	help
 534	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 535
 536	  Affected Cortex-A55 cores (all revisions) could cause incorrect
 537	  update of the hardware dirty bit when the DBM/AP bits are updated
 538	  without a break-before-make. The workaround is to disable the usage
 539	  of hardware DBM locally on the affected cores. CPUs not affected by
 540	  this erratum will continue to use the feature.
 541
 542	  If unsure, say Y.
 543
 544config ARM64_ERRATUM_1418040
 545	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
 546	default y
 547	depends on COMPAT
 548	help
 549	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
 550	  errata 1188873 and 1418040.
 551
 552	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
 553	  cause register corruption when accessing the timer registers
 554	  from AArch32 userspace.
 555
 556	  If unsure, say Y.
 557
 558config ARM64_WORKAROUND_SPECULATIVE_AT
 559	bool
 560
 561config ARM64_ERRATUM_1165522
 562	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 563	default y
 564	select ARM64_WORKAROUND_SPECULATIVE_AT
 565	help
 566	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
 567
 568	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
 569	  corrupted TLBs by speculating an AT instruction during a guest
 570	  context switch.
 571
 572	  If unsure, say Y.
 573
 574config ARM64_ERRATUM_1319367
 575	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 576	default y
 577	select ARM64_WORKAROUND_SPECULATIVE_AT
 578	help
 579	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
 580	  and A72 erratum 1319367
 581
 582	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
 583	  speculating an AT instruction during a guest context switch.
 584
 585	  If unsure, say Y.
 586
 587config ARM64_ERRATUM_1530923
 588	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 589	default y
 590	select ARM64_WORKAROUND_SPECULATIVE_AT
 591	help
 592	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
 593
 594	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
 595	  corrupted TLBs by speculating an AT instruction during a guest
 596	  context switch.
 597
 598	  If unsure, say Y.
 599
 600config ARM64_WORKAROUND_REPEAT_TLBI
 601	bool
 602
 603config ARM64_ERRATUM_1286807
 604	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
 605	default y
 606	select ARM64_WORKAROUND_REPEAT_TLBI
 607	help
 608	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
 609
 610	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
 611	  address for a cacheable mapping of a location is being
 612	  accessed by a core while another core is remapping the virtual
 613	  address to a new physical page using the recommended
 614	  break-before-make sequence, then under very rare circumstances
 615	  TLBI+DSB completes before a read using the translation being
 616	  invalidated has been observed by other observers. The
 617	  workaround repeats the TLBI+DSB operation.
 618
 619config ARM64_ERRATUM_1463225
 620	bool "Cortex-A76: Software Step might prevent interrupt recognition"
 621	default y
 622	help
 623	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
 624
 625	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
 626	  of a system call instruction (SVC) can prevent recognition of
 627	  subsequent interrupts when software stepping is disabled in the
 628	  exception handler of the system call and either kernel debugging
 629	  is enabled or VHE is in use.
 630
 631	  Work around the erratum by triggering a dummy step exception
 632	  when handling a system call from a task that is being stepped
 633	  in a VHE configuration of the kernel.
 634
 635	  If unsure, say Y.
 636
 637config ARM64_ERRATUM_1542419
 638	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
 639	default y
 640	help
 641	  This option adds a workaround for ARM Neoverse-N1 erratum
 642	  1542419.
 643
 644	  Affected Neoverse-N1 cores could execute a stale instruction when
 645	  modified by another CPU. The workaround depends on a firmware
 646	  counterpart.
 647
 648	  Workaround the issue by hiding the DIC feature from EL0. This
 649	  forces user-space to perform cache maintenance.
 650
 651	  If unsure, say Y.
 652
 653config ARM64_ERRATUM_1508412
 654	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
 655	default y
 656	help
 657	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
 658
 659	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
 660	  of a store-exclusive or read of PAR_EL1 and a load with device or
 661	  non-cacheable memory attributes. The workaround depends on a firmware
 662	  counterpart.
 663
 664	  KVM guests must also have the workaround implemented or they can
 665	  deadlock the system.
 666
 667	  Work around the issue by inserting DMB SY barriers around PAR_EL1
 668	  register reads and warning KVM users. The DMB barrier is sufficient
 669	  to prevent a speculative PAR_EL1 read.
 670
 671	  If unsure, say Y.
 672
 673config CAVIUM_ERRATUM_22375
 674	bool "Cavium erratum 22375, 24313"
 675	default y
 676	help
 677	  Enable workaround for errata 22375 and 24313.
 678
 679	  This implements two gicv3-its errata workarounds for ThunderX. Both
 680	  with a small impact affecting only ITS table allocation.
 681
 682	    erratum 22375: only alloc 8MB table size
 683	    erratum 24313: ignore memory access type
 684
 685	  The fixes are in ITS initialization and basically ignore memory access
 686	  type and table size provided by the TYPER and BASER registers.
 687
 688	  If unsure, say Y.
 689
 690config CAVIUM_ERRATUM_23144
 691	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
 692	depends on NUMA
 693	default y
 694	help
 695	  ITS SYNC command hang for cross node io and collections/cpu mapping.
 696
 697	  If unsure, say Y.
 698
 699config CAVIUM_ERRATUM_23154
 700	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 701	default y
 702	help
 703	  The gicv3 of ThunderX requires a modified version for
 704	  reading the IAR status to ensure data synchronization
 705	  (access to icc_iar1_el1 is not sync'ed before and after).
 706
 707	  If unsure, say Y.
 708
 709config CAVIUM_ERRATUM_27456
 710	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 711	default y
 712	help
 713	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 714	  instructions may cause the icache to become corrupted if it
 715	  contains data for a non-current ASID.  The fix is to
 716	  invalidate the icache when changing the mm context.
 717
 718	  If unsure, say Y.
 719
 720config CAVIUM_ERRATUM_30115
 721	bool "Cavium erratum 30115: Guest may disable interrupts in host"
 722	default y
 723	help
 724	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
 725	  1.2, and T83 Pass 1.0, KVM guest execution may disable
 726	  interrupts in host. Trapping both GICv3 group-0 and group-1
 727	  accesses sidesteps the issue.
 728
 729	  If unsure, say Y.
 730
 731config CAVIUM_TX2_ERRATUM_219
 732	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
 733	default y
 734	help
 735	  On Cavium ThunderX2, a load, store or prefetch instruction between a
 736	  TTBR update and the corresponding context synchronizing operation can
 737	  cause a spurious Data Abort to be delivered to any hardware thread in
 738	  the CPU core.
 739
 740	  Work around the issue by avoiding the problematic code sequence and
 741	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
 742	  trap handler performs the corresponding register access, skips the
 743	  instruction and ensures context synchronization by virtue of the
 744	  exception return.
 745
 746	  If unsure, say Y.
 747
 748config FUJITSU_ERRATUM_010001
 749	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
 750	default y
 751	help
 752	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
 753	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
 754	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
 755	  This fault occurs under a specific hardware condition when a
 756	  load/store instruction performs an address translation using:
 757	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
 758	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
 759	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
 760	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
 761
 762	  The workaround is to ensure these bits are clear in TCR_ELx.
 763	  The workaround only affects the Fujitsu-A64FX.
 764
 765	  If unsure, say Y.
 766
 767config HISILICON_ERRATUM_161600802
 768	bool "Hip07 161600802: Erroneous redistributor VLPI base"
 769	default y
 770	help
 771	  The HiSilicon Hip07 SoC uses the wrong redistributor base
 772	  when issued ITS commands such as VMOVP and VMAPP, and requires
 773	  a 128kB offset to be applied to the target address in this commands.
 774
 775	  If unsure, say Y.
 776
 777config QCOM_FALKOR_ERRATUM_1003
 778	bool "Falkor E1003: Incorrect translation due to ASID change"
 779	default y
 780	help
 781	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
 782	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
 783	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
 784	  then only for entries in the walk cache, since the leaf translation
 785	  is unchanged. Work around the erratum by invalidating the walk cache
 786	  entries for the trampoline before entering the kernel proper.
 787
 788config QCOM_FALKOR_ERRATUM_1009
 789	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
 790	default y
 791	select ARM64_WORKAROUND_REPEAT_TLBI
 792	help
 793	  On Falkor v1, the CPU may prematurely complete a DSB following a
 794	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
 795	  one more time to fix the issue.
 796
 797	  If unsure, say Y.
 798
 799config QCOM_QDF2400_ERRATUM_0065
 800	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
 801	default y
 802	help
 803	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
 804	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
 805	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
 806
 807	  If unsure, say Y.
 808
 809config QCOM_FALKOR_ERRATUM_E1041
 810	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
 811	default y
 812	help
 813	  Falkor CPU may speculatively fetch instructions from an improper
 814	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
 815	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
 816
 817	  If unsure, say Y.
 818
 819config NVIDIA_CARMEL_CNP_ERRATUM
 820	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
 821	default y
 822	help
 823	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
 824	  invalidate shared TLB entries installed by a different core, as it would
 825	  on standard ARM cores.
 826
 827	  If unsure, say Y.
 828
 829config SOCIONEXT_SYNQUACER_PREITS
 830	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
 831	default y
 832	help
 833	  Socionext Synquacer SoCs implement a separate h/w block to generate
 834	  MSI doorbell writes with non-zero values for the device ID.
 835
 836	  If unsure, say Y.
 837
 838endmenu
 839
 840
 841choice
 842	prompt "Page size"
 843	default ARM64_4K_PAGES
 844	help
 845	  Page size (translation granule) configuration.
 846
 847config ARM64_4K_PAGES
 848	bool "4KB"
 849	help
 850	  This feature enables 4KB pages support.
 851
 852config ARM64_16K_PAGES
 853	bool "16KB"
 854	help
 855	  The system will use 16KB pages support. AArch32 emulation
 856	  requires applications compiled with 16K (or a multiple of 16K)
 857	  aligned segments.
 858
 859config ARM64_64K_PAGES
 860	bool "64KB"
 861	help
 862	  This feature enables 64KB pages support (4KB by default)
 863	  allowing only two levels of page tables and faster TLB
 864	  look-up. AArch32 emulation requires applications compiled
 865	  with 64K aligned segments.
 866
 867endchoice
 868
 869choice
 870	prompt "Virtual address space size"
 871	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 872	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 873	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 874	help
 875	  Allows choosing one of multiple possible virtual address
 876	  space sizes. The level of translation table is determined by
 877	  a combination of page size and virtual address space size.
 878
 879config ARM64_VA_BITS_36
 880	bool "36-bit" if EXPERT
 881	depends on ARM64_16K_PAGES
 882
 883config ARM64_VA_BITS_39
 884	bool "39-bit"
 885	depends on ARM64_4K_PAGES
 886
 887config ARM64_VA_BITS_42
 888	bool "42-bit"
 889	depends on ARM64_64K_PAGES
 890
 891config ARM64_VA_BITS_47
 892	bool "47-bit"
 893	depends on ARM64_16K_PAGES
 894
 895config ARM64_VA_BITS_48
 896	bool "48-bit"
 897
 898config ARM64_VA_BITS_52
 899	bool "52-bit"
 900	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
 901	help
 902	  Enable 52-bit virtual addressing for userspace when explicitly
 903	  requested via a hint to mmap(). The kernel will also use 52-bit
 904	  virtual addresses for its own mappings (provided HW support for
 905	  this feature is available, otherwise it reverts to 48-bit).
 906
 907	  NOTE: Enabling 52-bit virtual addressing in conjunction with
 908	  ARMv8.3 Pointer Authentication will result in the PAC being
 909	  reduced from 7 bits to 3 bits, which may have a significant
 910	  impact on its susceptibility to brute-force attacks.
 911
 912	  If unsure, select 48-bit virtual addressing instead.
 913
 914endchoice
 915
 916config ARM64_FORCE_52BIT
 917	bool "Force 52-bit virtual addresses for userspace"
 918	depends on ARM64_VA_BITS_52 && EXPERT
 919	help
 920	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
 921	  to maintain compatibility with older software by providing 48-bit VAs
 922	  unless a hint is supplied to mmap.
 923
 924	  This configuration option disables the 48-bit compatibility logic, and
 925	  forces all userspace addresses to be 52-bit on HW that supports it. One
 926	  should only enable this configuration option for stress testing userspace
 927	  memory management code. If unsure say N here.
 928
 929config ARM64_VA_BITS
 930	int
 931	default 36 if ARM64_VA_BITS_36
 932	default 39 if ARM64_VA_BITS_39
 933	default 42 if ARM64_VA_BITS_42
 934	default 47 if ARM64_VA_BITS_47
 935	default 48 if ARM64_VA_BITS_48
 936	default 52 if ARM64_VA_BITS_52
 937
 938choice
 939	prompt "Physical address space size"
 940	default ARM64_PA_BITS_48
 941	help
 942	  Choose the maximum physical address range that the kernel will
 943	  support.
 944
 945config ARM64_PA_BITS_48
 946	bool "48-bit"
 947
 948config ARM64_PA_BITS_52
 949	bool "52-bit (ARMv8.2)"
 950	depends on ARM64_64K_PAGES
 951	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
 952	help
 953	  Enable support for a 52-bit physical address space, introduced as
 954	  part of the ARMv8.2-LPA extension.
 955
 956	  With this enabled, the kernel will also continue to work on CPUs that
 957	  do not support ARMv8.2-LPA, but with some added memory overhead (and
 958	  minor performance overhead).
 959
 960endchoice
 961
 962config ARM64_PA_BITS
 963	int
 964	default 48 if ARM64_PA_BITS_48
 965	default 52 if ARM64_PA_BITS_52
 966
 967choice
 968	prompt "Endianness"
 969	default CPU_LITTLE_ENDIAN
 970	help
 971	  Select the endianness of data accesses performed by the CPU. Userspace
 972	  applications will need to be compiled and linked for the endianness
 973	  that is selected here.
 974
 975config CPU_BIG_ENDIAN
 976	bool "Build big-endian kernel"
 977	depends on !LD_IS_LLD || LLD_VERSION >= 130000
 978	help
 979	  Say Y if you plan on running a kernel with a big-endian userspace.
 980
 981config CPU_LITTLE_ENDIAN
 982	bool "Build little-endian kernel"
 983	help
 984	  Say Y if you plan on running a kernel with a little-endian userspace.
 985	  This is usually the case for distributions targeting arm64.
 986
 987endchoice
 988
 989config SCHED_MC
 990	bool "Multi-core scheduler support"
 991	help
 992	  Multi-core scheduler support improves the CPU scheduler's decision
 993	  making when dealing with multi-core CPU chips at a cost of slightly
 994	  increased overhead in some places. If unsure say N here.
 995
 996config SCHED_SMT
 997	bool "SMT scheduler support"
 998	help
 999	  Improves the CPU scheduler's decision making when dealing with
1000	  MultiThreading at a cost of slightly increased overhead in some
1001	  places. If unsure say N here.
1002
1003config NR_CPUS
1004	int "Maximum number of CPUs (2-4096)"
1005	range 2 4096
1006	default "256"
 
1007
1008config HOTPLUG_CPU
1009	bool "Support for hot-pluggable CPUs"
1010	select GENERIC_IRQ_MIGRATION
1011	help
1012	  Say Y here to experiment with turning CPUs off and on.  CPUs
1013	  can be controlled through /sys/devices/system/cpu.
1014
1015# Common NUMA Features
1016config NUMA
1017	bool "NUMA Memory Allocation and Scheduler Support"
1018	select GENERIC_ARCH_NUMA
1019	select ACPI_NUMA if ACPI
1020	select OF_NUMA
1021	help
1022	  Enable NUMA (Non-Uniform Memory Access) support.
1023
1024	  The kernel will try to allocate memory used by a CPU on the
1025	  local memory of the CPU and add some more
1026	  NUMA awareness to the kernel.
1027
1028config NODES_SHIFT
1029	int "Maximum NUMA Nodes (as a power of 2)"
1030	range 1 10
1031	default "4"
1032	depends on NUMA
1033	help
1034	  Specify the maximum number of NUMA Nodes available on the target
1035	  system.  Increases memory reserved to accommodate various tables.
1036
1037config USE_PERCPU_NUMA_NODE_ID
1038	def_bool y
1039	depends on NUMA
1040
1041config HAVE_SETUP_PER_CPU_AREA
 
 
 
 
 
 
 
 
 
1042	def_bool y
1043	depends on NUMA
1044
1045config NEED_PER_CPU_EMBED_FIRST_CHUNK
1046	def_bool y
1047	depends on NUMA
1048
1049source "kernel/Kconfig.hz"
 
1050
1051config ARCH_SPARSEMEM_ENABLE
1052	def_bool y
1053	select SPARSEMEM_VMEMMAP_ENABLE
1054	select SPARSEMEM_VMEMMAP
1055
1056config HW_PERF_EVENTS
1057	def_bool y
1058	depends on ARM_PMU
1059
1060config ARCH_HAS_FILTER_PGPROT
1061	def_bool y
1062
1063# Supported by clang >= 7.0
1064config CC_HAVE_SHADOW_CALL_STACK
1065	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
 
 
 
 
 
 
 
 
 
1066
1067config PARAVIRT
1068	bool "Enable paravirtualization code"
1069	help
1070	  This changes the kernel so it can modify itself when it is run
1071	  under a hypervisor, potentially improving performance significantly
1072	  over full virtualization.
1073
1074config PARAVIRT_TIME_ACCOUNTING
1075	bool "Paravirtual steal time accounting"
1076	select PARAVIRT
 
1077	help
1078	  Select this option to enable fine granularity task steal time
1079	  accounting. Time spent executing other tasks in parallel with
1080	  the current vCPU is discounted from the vCPU power. To account for
1081	  that, there can be a small performance impact.
1082
1083	  If in doubt, say N here.
1084
1085config KEXEC
1086	depends on PM_SLEEP_SMP
1087	select KEXEC_CORE
1088	bool "kexec system call"
1089	help
1090	  kexec is a system call that implements the ability to shutdown your
1091	  current kernel, and to start another kernel.  It is like a reboot
1092	  but it is independent of the system firmware.   And like a reboot
1093	  you can start any kernel with it, not just Linux.
1094
1095config KEXEC_FILE
1096	bool "kexec file based system call"
1097	select KEXEC_CORE
1098	select HAVE_IMA_KEXEC if IMA
1099	help
1100	  This is new version of kexec system call. This system call is
1101	  file based and takes file descriptors as system call argument
1102	  for kernel and initramfs as opposed to list of segments as
1103	  accepted by previous system call.
1104
1105config KEXEC_SIG
1106	bool "Verify kernel signature during kexec_file_load() syscall"
1107	depends on KEXEC_FILE
1108	help
1109	  Select this option to verify a signature with loaded kernel
1110	  image. If configured, any attempt of loading a image without
1111	  valid signature will fail.
1112
1113	  In addition to that option, you need to enable signature
1114	  verification for the corresponding kernel image type being
1115	  loaded in order for this to work.
1116
1117config KEXEC_IMAGE_VERIFY_SIG
1118	bool "Enable Image signature verification support"
1119	default y
1120	depends on KEXEC_SIG
1121	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1122	help
1123	  Enable Image signature verification support.
1124
1125comment "Support for PE file signature verification disabled"
1126	depends on KEXEC_SIG
1127	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1128
1129config CRASH_DUMP
1130	bool "Build kdump crash kernel"
1131	help
1132	  Generate crash dump after being started by kexec. This should
1133	  be normally only set in special crash dump kernels which are
1134	  loaded in the main kernel with kexec-tools into a specially
1135	  reserved region and then later executed after a crash by
1136	  kdump/kexec.
1137
1138	  For more details see Documentation/admin-guide/kdump/kdump.rst
1139
1140config TRANS_TABLE
1141	def_bool y
1142	depends on HIBERNATION
1143
1144config XEN_DOM0
1145	def_bool y
1146	depends on XEN
1147
1148config XEN
1149	bool "Xen guest support on ARM64"
1150	depends on ARM64 && OF
1151	select SWIOTLB_XEN
1152	select PARAVIRT
1153	help
1154	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1155
1156config FORCE_MAX_ZONEORDER
1157	int
1158	default "14" if ARM64_64K_PAGES
1159	default "12" if ARM64_16K_PAGES
1160	default "11"
1161	help
1162	  The kernel memory allocator divides physically contiguous memory
1163	  blocks into "zones", where each zone is a power of two number of
1164	  pages.  This option selects the largest power of two that the kernel
1165	  keeps in the memory allocator.  If you need to allocate very large
1166	  blocks of physically contiguous memory, then you may need to
1167	  increase this value.
1168
1169	  This config option is actually maximum order plus one. For example,
1170	  a value of 11 means that the largest free memory block is 2^10 pages.
1171
1172	  We make sure that we can allocate upto a HugePage size for each configuration.
1173	  Hence we have :
1174		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1175
1176	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1177	  4M allocations matching the default size used by generic code.
1178
1179config UNMAP_KERNEL_AT_EL0
1180	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1181	default y
1182	help
1183	  Speculation attacks against some high-performance processors can
1184	  be used to bypass MMU permission checks and leak kernel data to
1185	  userspace. This can be defended against by unmapping the kernel
1186	  when running in userspace, mapping it back in on exception entry
1187	  via a trampoline page in the vector table.
1188
1189	  If unsure, say Y.
1190
1191config RODATA_FULL_DEFAULT_ENABLED
1192	bool "Apply r/o permissions of VM areas also to their linear aliases"
1193	default y
1194	help
1195	  Apply read-only attributes of VM areas to the linear alias of
1196	  the backing pages as well. This prevents code or read-only data
1197	  from being modified (inadvertently or intentionally) via another
1198	  mapping of the same memory page. This additional enhancement can
1199	  be turned off at runtime by passing rodata=[off|on] (and turned on
1200	  with rodata=full if this option is set to 'n')
1201
1202	  This requires the linear region to be mapped down to pages,
1203	  which may adversely affect performance in some cases.
1204
1205config ARM64_SW_TTBR0_PAN
1206	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1207	help
1208	  Enabling this option prevents the kernel from accessing
1209	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1210	  zeroed area and reserved ASID. The user access routines
1211	  restore the valid TTBR0_EL1 temporarily.
1212
1213config ARM64_TAGGED_ADDR_ABI
1214	bool "Enable the tagged user addresses syscall ABI"
1215	default y
1216	help
1217	  When this option is enabled, user applications can opt in to a
1218	  relaxed ABI via prctl() allowing tagged addresses to be passed
1219	  to system calls as pointer arguments. For details, see
1220	  Documentation/arm64/tagged-address-abi.rst.
1221
1222menuconfig COMPAT
1223	bool "Kernel support for 32-bit EL0"
1224	depends on ARM64_4K_PAGES || EXPERT
1225	select HAVE_UID16
1226	select OLD_SIGSUSPEND3
1227	select COMPAT_OLD_SIGACTION
1228	help
1229	  This option enables support for a 32-bit EL0 running under a 64-bit
1230	  kernel at EL1. AArch32-specific components such as system calls,
1231	  the user helper functions, VFP support and the ptrace interface are
1232	  handled appropriately by the kernel.
1233
1234	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1235	  that you will only be able to execute AArch32 binaries that were compiled
1236	  with page size aligned segments.
1237
1238	  If you want to execute 32-bit userspace applications, say Y.
1239
1240if COMPAT
1241
1242config KUSER_HELPERS
1243	bool "Enable kuser helpers page for 32-bit applications"
1244	default y
1245	help
1246	  Warning: disabling this option may break 32-bit user programs.
1247
1248	  Provide kuser helpers to compat tasks. The kernel provides
1249	  helper code to userspace in read only form at a fixed location
1250	  to allow userspace to be independent of the CPU type fitted to
1251	  the system. This permits binaries to be run on ARMv4 through
1252	  to ARMv8 without modification.
1253
1254	  See Documentation/arm/kernel_user_helpers.rst for details.
1255
1256	  However, the fixed address nature of these helpers can be used
1257	  by ROP (return orientated programming) authors when creating
1258	  exploits.
1259
1260	  If all of the binaries and libraries which run on your platform
1261	  are built specifically for your platform, and make no use of
1262	  these helpers, then you can turn this option off to hinder
1263	  such exploits. However, in that case, if a binary or library
1264	  relying on those helpers is run, it will not function correctly.
1265
1266	  Say N here only if you are absolutely certain that you do not
1267	  need these helpers; otherwise, the safe option is to say Y.
1268
1269config COMPAT_VDSO
1270	bool "Enable vDSO for 32-bit applications"
1271	depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1272	select GENERIC_COMPAT_VDSO
1273	default y
1274	help
1275	  Place in the process address space of 32-bit applications an
1276	  ELF shared object providing fast implementations of gettimeofday
1277	  and clock_gettime.
1278
1279	  You must have a 32-bit build of glibc 2.22 or later for programs
1280	  to seamlessly take advantage of this.
1281
1282config THUMB2_COMPAT_VDSO
1283	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1284	depends on COMPAT_VDSO
1285	default y
1286	help
1287	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1288	  otherwise with '-marm'.
1289
1290menuconfig ARMV8_DEPRECATED
1291	bool "Emulate deprecated/obsolete ARMv8 instructions"
1292	depends on SYSCTL
1293	help
1294	  Legacy software support may require certain instructions
1295	  that have been deprecated or obsoleted in the architecture.
1296
1297	  Enable this config to enable selective emulation of these
1298	  features.
1299
1300	  If unsure, say Y
1301
1302if ARMV8_DEPRECATED
1303
1304config SWP_EMULATION
1305	bool "Emulate SWP/SWPB instructions"
1306	help
1307	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1308	  they are always undefined. Say Y here to enable software
1309	  emulation of these instructions for userspace using LDXR/STXR.
1310	  This feature can be controlled at runtime with the abi.swp
1311	  sysctl which is disabled by default.
1312
1313	  In some older versions of glibc [<=2.8] SWP is used during futex
1314	  trylock() operations with the assumption that the code will not
1315	  be preempted. This invalid assumption may be more likely to fail
1316	  with SWP emulation enabled, leading to deadlock of the user
1317	  application.
1318
1319	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1320	  on an external transaction monitoring block called a global
1321	  monitor to maintain update atomicity. If your system does not
1322	  implement a global monitor, this option can cause programs that
1323	  perform SWP operations to uncached memory to deadlock.
1324
1325	  If unsure, say Y
1326
1327config CP15_BARRIER_EMULATION
1328	bool "Emulate CP15 Barrier instructions"
1329	help
1330	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1331	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1332	  strongly recommended to use the ISB, DSB, and DMB
1333	  instructions instead.
1334
1335	  Say Y here to enable software emulation of these
1336	  instructions for AArch32 userspace code. When this option is
1337	  enabled, CP15 barrier usage is traced which can help
1338	  identify software that needs updating. This feature can be
1339	  controlled at runtime with the abi.cp15_barrier sysctl.
1340
1341	  If unsure, say Y
1342
1343config SETEND_EMULATION
1344	bool "Emulate SETEND instruction"
1345	help
1346	  The SETEND instruction alters the data-endianness of the
1347	  AArch32 EL0, and is deprecated in ARMv8.
1348
1349	  Say Y here to enable software emulation of the instruction
1350	  for AArch32 userspace code. This feature can be controlled
1351	  at runtime with the abi.setend sysctl.
1352
1353	  Note: All the cpus on the system must have mixed endian support at EL0
1354	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1355	  endian - is hotplugged in after this feature has been enabled, there could
1356	  be unexpected results in the applications.
1357
1358	  If unsure, say Y
1359endif
1360
1361endif
1362
1363menu "ARMv8.1 architectural features"
1364
1365config ARM64_HW_AFDBM
1366	bool "Support for hardware updates of the Access and Dirty page flags"
1367	default y
1368	help
1369	  The ARMv8.1 architecture extensions introduce support for
1370	  hardware updates of the access and dirty information in page
1371	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1372	  capable processors, accesses to pages with PTE_AF cleared will
1373	  set this bit instead of raising an access flag fault.
1374	  Similarly, writes to read-only pages with the DBM bit set will
1375	  clear the read-only bit (AP[2]) instead of raising a
1376	  permission fault.
1377
1378	  Kernels built with this configuration option enabled continue
1379	  to work on pre-ARMv8.1 hardware and the performance impact is
1380	  minimal. If unsure, say Y.
1381
1382config ARM64_PAN
1383	bool "Enable support for Privileged Access Never (PAN)"
1384	default y
1385	help
1386	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1387	 prevents the kernel or hypervisor from accessing user-space (EL0)
1388	 memory directly.
1389
1390	 Choosing this option will cause any unprotected (not using
1391	 copy_to_user et al) memory access to fail with a permission fault.
1392
1393	 The feature is detected at runtime, and will remain as a 'nop'
1394	 instruction if the cpu does not implement the feature.
1395
1396config AS_HAS_LDAPR
1397	def_bool $(as-instr,.arch_extension rcpc)
1398
1399config AS_HAS_LSE_ATOMICS
1400	def_bool $(as-instr,.arch_extension lse)
1401
1402config ARM64_LSE_ATOMICS
1403	bool
1404	default ARM64_USE_LSE_ATOMICS
1405	depends on AS_HAS_LSE_ATOMICS
1406
1407config ARM64_USE_LSE_ATOMICS
1408	bool "Atomic instructions"
1409	depends on JUMP_LABEL
1410	default y
1411	help
1412	  As part of the Large System Extensions, ARMv8.1 introduces new
1413	  atomic instructions that are designed specifically to scale in
1414	  very large systems.
1415
1416	  Say Y here to make use of these instructions for the in-kernel
1417	  atomic routines. This incurs a small overhead on CPUs that do
1418	  not support these instructions and requires the kernel to be
1419	  built with binutils >= 2.25 in order for the new instructions
1420	  to be used.
1421
1422endmenu
1423
1424menu "ARMv8.2 architectural features"
1425
1426config ARM64_PMEM
1427	bool "Enable support for persistent memory"
1428	select ARCH_HAS_PMEM_API
1429	select ARCH_HAS_UACCESS_FLUSHCACHE
1430	help
1431	  Say Y to enable support for the persistent memory API based on the
1432	  ARMv8.2 DCPoP feature.
1433
1434	  The feature is detected at runtime, and the kernel will use DC CVAC
1435	  operations if DC CVAP is not supported (following the behaviour of
1436	  DC CVAP itself if the system does not define a point of persistence).
1437
1438config ARM64_RAS_EXTN
1439	bool "Enable support for RAS CPU Extensions"
1440	default y
1441	help
1442	  CPUs that support the Reliability, Availability and Serviceability
1443	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1444	  errors, classify them and report them to software.
1445
1446	  On CPUs with these extensions system software can use additional
1447	  barriers to determine if faults are pending and read the
1448	  classification from a new set of registers.
1449
1450	  Selecting this feature will allow the kernel to use these barriers
1451	  and access the new registers if the system supports the extension.
1452	  Platform RAS features may additionally depend on firmware support.
1453
1454config ARM64_CNP
1455	bool "Enable support for Common Not Private (CNP) translations"
1456	default y
1457	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1458	help
1459	  Common Not Private (CNP) allows translation table entries to
1460	  be shared between different PEs in the same inner shareable
1461	  domain, so the hardware can use this fact to optimise the
1462	  caching of such entries in the TLB.
1463
1464	  Selecting this option allows the CNP feature to be detected
1465	  at runtime, and does not affect PEs that do not implement
1466	  this feature.
1467
1468endmenu
1469
1470menu "ARMv8.3 architectural features"
1471
1472config ARM64_PTR_AUTH
1473	bool "Enable support for pointer authentication"
1474	default y
1475	help
1476	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1477	  instructions for signing and authenticating pointers against secret
1478	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1479	  and other attacks.
1480
1481	  This option enables these instructions at EL0 (i.e. for userspace).
1482	  Choosing this option will cause the kernel to initialise secret keys
1483	  for each process at exec() time, with these keys being
1484	  context-switched along with the process.
1485
1486	  The feature is detected at runtime. If the feature is not present in
1487	  hardware it will not be advertised to userspace/KVM guest nor will it
1488	  be enabled.
1489
1490	  If the feature is present on the boot CPU but not on a late CPU, then
1491	  the late CPU will be parked. Also, if the boot CPU does not have
1492	  address auth and the late CPU has then the late CPU will still boot
1493	  but with the feature disabled. On such a system, this option should
1494	  not be selected.
1495
1496config ARM64_PTR_AUTH_KERNEL
1497	bool "Use pointer authentication for kernel"
1498	default y
1499	depends on ARM64_PTR_AUTH
1500	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1501	# Modern compilers insert a .note.gnu.property section note for PAC
1502	# which is only understood by binutils starting with version 2.33.1.
1503	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1504	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1505	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1506	help
1507	  If the compiler supports the -mbranch-protection or
1508	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1509	  will cause the kernel itself to be compiled with return address
1510	  protection. In this case, and if the target hardware is known to
1511	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1512	  disabled with minimal loss of protection.
1513
1514	  This feature works with FUNCTION_GRAPH_TRACER option only if
1515	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1516
1517config CC_HAS_BRANCH_PROT_PAC_RET
1518	# GCC 9 or later, clang 8 or later
1519	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1520
1521config CC_HAS_SIGN_RETURN_ADDRESS
1522	# GCC 7, 8
1523	def_bool $(cc-option,-msign-return-address=all)
1524
1525config AS_HAS_PAC
1526	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1527
1528config AS_HAS_CFI_NEGATE_RA_STATE
1529	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
 
1530
1531endmenu
1532
1533menu "ARMv8.4 architectural features"
1534
1535config ARM64_AMU_EXTN
1536	bool "Enable support for the Activity Monitors Unit CPU extension"
1537	default y
1538	help
1539	  The activity monitors extension is an optional extension introduced
1540	  by the ARMv8.4 CPU architecture. This enables support for version 1
1541	  of the activity monitors architecture, AMUv1.
1542
1543	  To enable the use of this extension on CPUs that implement it, say Y.
1544
1545	  Note that for architectural reasons, firmware _must_ implement AMU
1546	  support when running on CPUs that present the activity monitors
1547	  extension. The required support is present in:
1548	    * Version 1.5 and later of the ARM Trusted Firmware
1549
1550	  For kernels that have this configuration enabled but boot with broken
1551	  firmware, you may need to say N here until the firmware is fixed.
1552	  Otherwise you may experience firmware panics or lockups when
1553	  accessing the counter registers. Even if you are not observing these
1554	  symptoms, the values returned by the register reads might not
1555	  correctly reflect reality. Most commonly, the value read will be 0,
1556	  indicating that the counter is not enabled.
1557
1558config AS_HAS_ARMV8_4
1559	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1560
1561config ARM64_TLB_RANGE
1562	bool "Enable support for tlbi range feature"
1563	default y
1564	depends on AS_HAS_ARMV8_4
1565	help
1566	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1567	  range of input addresses.
1568
1569	  The feature introduces new assembly instructions, and they were
1570	  support when binutils >= 2.30.
1571
1572endmenu
1573
1574menu "ARMv8.5 architectural features"
1575
1576config AS_HAS_ARMV8_5
1577	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1578
1579config ARM64_BTI
1580	bool "Branch Target Identification support"
1581	default y
1582	help
1583	  Branch Target Identification (part of the ARMv8.5 Extensions)
1584	  provides a mechanism to limit the set of locations to which computed
1585	  branch instructions such as BR or BLR can jump.
1586
1587	  To make use of BTI on CPUs that support it, say Y.
1588
1589	  BTI is intended to provide complementary protection to other control
1590	  flow integrity protection mechanisms, such as the Pointer
1591	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1592	  For this reason, it does not make sense to enable this option without
1593	  also enabling support for pointer authentication.  Thus, when
1594	  enabling this option you should also select ARM64_PTR_AUTH=y.
1595
1596	  Userspace binaries must also be specifically compiled to make use of
1597	  this mechanism.  If you say N here or the hardware does not support
1598	  BTI, such binaries can still run, but you get no additional
1599	  enforcement of branch destinations.
1600
1601config ARM64_BTI_KERNEL
1602	bool "Use Branch Target Identification for kernel"
1603	default y
1604	depends on ARM64_BTI
1605	depends on ARM64_PTR_AUTH_KERNEL
1606	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1607	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1608	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1609	# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1610	depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1611	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1612	help
1613	  Build the kernel with Branch Target Identification annotations
1614	  and enable enforcement of this for kernel code. When this option
1615	  is enabled and the system supports BTI all kernel code including
1616	  modular code must have BTI enabled.
1617
1618config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1619	# GCC 9 or later, clang 8 or later
1620	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1621
1622config ARM64_E0PD
1623	bool "Enable support for E0PD"
1624	default y
1625	help
1626	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1627	  that EL0 accesses made via TTBR1 always fault in constant time,
1628	  providing similar benefits to KASLR as those provided by KPTI, but
1629	  with lower overhead and without disrupting legitimate access to
1630	  kernel memory such as SPE.
1631
1632	  This option enables E0PD for TTBR1 where available.
1633
1634config ARCH_RANDOM
1635	bool "Enable support for random number generation"
1636	default y
1637	help
1638	  Random number generation (part of the ARMv8.5 Extensions)
1639	  provides a high bandwidth, cryptographically secure
1640	  hardware random number generator.
1641
1642config ARM64_AS_HAS_MTE
1643	# Initial support for MTE went in binutils 2.32.0, checked with
1644	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1645	# as a late addition to the final architecture spec (LDGM/STGM)
1646	# is only supported in the newer 2.32.x and 2.33 binutils
1647	# versions, hence the extra "stgm" instruction check below.
1648	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1649
1650config ARM64_MTE
1651	bool "Memory Tagging Extension support"
1652	default y
1653	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1654	depends on AS_HAS_ARMV8_5
1655	depends on AS_HAS_LSE_ATOMICS
1656	# Required for tag checking in the uaccess routines
1657	depends on ARM64_PAN
1658	select ARCH_USES_HIGH_VMA_FLAGS
1659	help
1660	  Memory Tagging (part of the ARMv8.5 Extensions) provides
1661	  architectural support for run-time, always-on detection of
1662	  various classes of memory error to aid with software debugging
1663	  to eliminate vulnerabilities arising from memory-unsafe
1664	  languages.
1665
1666	  This option enables the support for the Memory Tagging
1667	  Extension at EL0 (i.e. for userspace).
1668
1669	  Selecting this option allows the feature to be detected at
1670	  runtime. Any secondary CPU not implementing this feature will
1671	  not be allowed a late bring-up.
1672
1673	  Userspace binaries that want to use this feature must
1674	  explicitly opt in. The mechanism for the userspace is
1675	  described in:
1676
1677	  Documentation/arm64/memory-tagging-extension.rst.
1678
1679endmenu
1680
1681menu "ARMv8.7 architectural features"
1682
1683config ARM64_EPAN
1684	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1685	default y
1686	depends on ARM64_PAN
1687	help
1688	 Enhanced Privileged Access Never (EPAN) allows Privileged
1689	 Access Never to be used with Execute-only mappings.
1690
1691	 The feature is detected at runtime, and will remain disabled
1692	 if the cpu does not implement the feature.
1693endmenu
1694
1695config ARM64_SVE
1696	bool "ARM Scalable Vector Extension support"
1697	default y
1698	help
1699	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1700	  execution state which complements and extends the SIMD functionality
1701	  of the base architecture to support much larger vectors and to enable
1702	  additional vectorisation opportunities.
1703
1704	  To enable use of this extension on CPUs that implement it, say Y.
1705
1706	  On CPUs that support the SVE2 extensions, this option will enable
1707	  those too.
1708
1709	  Note that for architectural reasons, firmware _must_ implement SVE
1710	  support when running on SVE capable hardware.  The required support
1711	  is present in:
1712
1713	    * version 1.5 and later of the ARM Trusted Firmware
1714	    * the AArch64 boot wrapper since commit 5e1261e08abf
1715	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1716
1717	  For other firmware implementations, consult the firmware documentation
1718	  or vendor.
1719
1720	  If you need the kernel to boot on SVE-capable hardware with broken
1721	  firmware, you may need to say N here until you get your firmware
1722	  fixed.  Otherwise, you may experience firmware panics or lockups when
1723	  booting the kernel.  If unsure and you are not observing these
1724	  symptoms, you should assume that it is safe to say Y.
1725
1726config ARM64_MODULE_PLTS
1727	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1728	depends on MODULES
1729	select HAVE_MOD_ARCH_SPECIFIC
1730	help
1731	  Allocate PLTs when loading modules so that jumps and calls whose
1732	  targets are too far away for their relative offsets to be encoded
1733	  in the instructions themselves can be bounced via veneers in the
1734	  module's PLT. This allows modules to be allocated in the generic
1735	  vmalloc area after the dedicated module memory area has been
1736	  exhausted.
1737
1738	  When running with address space randomization (KASLR), the module
1739	  region itself may be too far away for ordinary relative jumps and
1740	  calls, and so in that case, module PLTs are required and cannot be
1741	  disabled.
1742
1743	  Specific errata workaround(s) might also force module PLTs to be
1744	  enabled (ARM64_ERRATUM_843419).
1745
1746config ARM64_PSEUDO_NMI
1747	bool "Support for NMI-like interrupts"
1748	select ARM_GIC_V3
1749	help
1750	  Adds support for mimicking Non-Maskable Interrupts through the use of
1751	  GIC interrupt priority. This support requires version 3 or later of
1752	  ARM GIC.
1753
1754	  This high priority configuration for interrupts needs to be
1755	  explicitly enabled by setting the kernel parameter
1756	  "irqchip.gicv3_pseudo_nmi" to 1.
1757
1758	  If unsure, say N
1759
1760if ARM64_PSEUDO_NMI
1761config ARM64_DEBUG_PRIORITY_MASKING
1762	bool "Debug interrupt priority masking"
1763	help
1764	  This adds runtime checks to functions enabling/disabling
1765	  interrupts when using priority masking. The additional checks verify
1766	  the validity of ICC_PMR_EL1 when calling concerned functions.
1767
1768	  If unsure, say N
1769endif
1770
1771config RELOCATABLE
1772	bool "Build a relocatable kernel image" if EXPERT
1773	select ARCH_HAS_RELR
1774	default y
1775	help
1776	  This builds the kernel as a Position Independent Executable (PIE),
1777	  which retains all relocation metadata required to relocate the
1778	  kernel binary at runtime to a different virtual address than the
1779	  address it was linked at.
1780	  Since AArch64 uses the RELA relocation format, this requires a
1781	  relocation pass at runtime even if the kernel is loaded at the
1782	  same address it was linked at.
1783
1784config RANDOMIZE_BASE
1785	bool "Randomize the address of the kernel image"
1786	select ARM64_MODULE_PLTS if MODULES
1787	select RELOCATABLE
1788	help
1789	  Randomizes the virtual address at which the kernel image is
1790	  loaded, as a security feature that deters exploit attempts
1791	  relying on knowledge of the location of kernel internals.
1792
1793	  It is the bootloader's job to provide entropy, by passing a
1794	  random u64 value in /chosen/kaslr-seed at kernel entry.
1795
1796	  When booting via the UEFI stub, it will invoke the firmware's
1797	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1798	  to the kernel proper. In addition, it will randomise the physical
1799	  location of the kernel Image as well.
1800
1801	  If unsure, say N.
1802
1803config RANDOMIZE_MODULE_REGION_FULL
1804	bool "Randomize the module region over a 2 GB range"
1805	depends on RANDOMIZE_BASE
1806	default y
1807	help
1808	  Randomizes the location of the module region inside a 2 GB window
1809	  covering the core kernel. This way, it is less likely for modules
1810	  to leak information about the location of core kernel data structures
1811	  but it does imply that function calls between modules and the core
1812	  kernel will need to be resolved via veneers in the module PLT.
1813
1814	  When this option is not set, the module region will be randomized over
1815	  a limited range that contains the [_stext, _etext] interval of the
1816	  core kernel, so branch relocations are almost always in range unless
1817	  ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1818	  particular case of region exhaustion, modules might be able to fall
1819	  back to a larger 2GB area.
1820
1821config CC_HAVE_STACKPROTECTOR_SYSREG
1822	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1823
1824config STACKPROTECTOR_PER_TASK
1825	def_bool y
1826	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1827
1828endmenu
1829
1830menu "Boot options"
1831
1832config ARM64_ACPI_PARKING_PROTOCOL
1833	bool "Enable support for the ARM64 ACPI parking protocol"
1834	depends on ACPI
1835	help
1836	  Enable support for the ARM64 ACPI parking protocol. If disabled
1837	  the kernel will not allow booting through the ARM64 ACPI parking
1838	  protocol even if the corresponding data is present in the ACPI
1839	  MADT table.
1840
1841config CMDLINE
1842	string "Default kernel command string"
1843	default ""
1844	help
1845	  Provide a set of default command-line options at build time by
1846	  entering them here. As a minimum, you should specify the the
1847	  root device (e.g. root=/dev/nfs).
1848
1849choice
1850	prompt "Kernel command line type" if CMDLINE != ""
1851	default CMDLINE_FROM_BOOTLOADER
1852	help
1853	  Choose how the kernel will handle the provided default kernel
1854	  command line string.
1855
1856config CMDLINE_FROM_BOOTLOADER
1857	bool "Use bootloader kernel arguments if available"
1858	help
1859	  Uses the command-line options passed by the boot loader. If
1860	  the boot loader doesn't provide any, the default kernel command
1861	  string provided in CMDLINE will be used.
1862
1863config CMDLINE_FORCE
1864	bool "Always use the default kernel command string"
1865	help
1866	  Always use the default kernel command string, even if the boot
1867	  loader passes other arguments to the kernel.
1868	  This is useful if you cannot or don't want to change the
1869	  command-line options your boot loader passes to the kernel.
1870
1871endchoice
1872
1873config EFI_STUB
1874	bool
1875
1876config EFI
1877	bool "UEFI runtime support"
1878	depends on OF && !CPU_BIG_ENDIAN
1879	depends on KERNEL_MODE_NEON
1880	select ARCH_SUPPORTS_ACPI
1881	select LIBFDT
1882	select UCS2_STRING
1883	select EFI_PARAMS_FROM_FDT
1884	select EFI_RUNTIME_WRAPPERS
1885	select EFI_STUB
1886	select EFI_GENERIC_STUB
1887	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1888	default y
1889	help
1890	  This option provides support for runtime services provided
1891	  by UEFI firmware (such as non-volatile variables, realtime
1892          clock, and platform reset). A UEFI stub is also provided to
1893	  allow the kernel to be booted as an EFI application. This
1894	  is only useful on systems that have UEFI firmware.
1895
1896config DMI
1897	bool "Enable support for SMBIOS (DMI) tables"
1898	depends on EFI
1899	default y
1900	help
1901	  This enables SMBIOS/DMI feature for systems.
1902
1903	  This option is only useful on systems that have UEFI firmware.
1904	  However, even with this option, the resultant kernel should
1905	  continue to boot on existing non-UEFI platforms.
1906
1907endmenu
1908
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1909config SYSVIPC_COMPAT
1910	def_bool y
1911	depends on COMPAT && SYSVIPC
1912
 
 
1913menu "Power management options"
1914
1915source "kernel/power/Kconfig"
1916
1917config ARCH_HIBERNATION_POSSIBLE
1918	def_bool y
1919	depends on CPU_PM
1920
1921config ARCH_HIBERNATION_HEADER
1922	def_bool y
1923	depends on HIBERNATION
1924
1925config ARCH_SUSPEND_POSSIBLE
1926	def_bool y
1927
1928endmenu
1929
1930menu "CPU Power Management"
1931
1932source "drivers/cpuidle/Kconfig"
1933
1934source "drivers/cpufreq/Kconfig"
1935
1936endmenu
1937
 
 
 
 
1938source "drivers/firmware/Kconfig"
1939
1940source "drivers/acpi/Kconfig"
1941
 
 
1942source "arch/arm64/kvm/Kconfig"
1943
 
 
 
 
 
1944if CRYPTO
1945source "arch/arm64/crypto/Kconfig"
1946endif