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1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/ktime.h>
18#include <linux/highmem.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/dma-mapping.h>
22#include <linux/slab.h>
23#include <linux/scatterlist.h>
24#include <linux/sizes.h>
25#include <linux/swiotlb.h>
26#include <linux/regulator/consumer.h>
27#include <linux/pm_runtime.h>
28#include <linux/of.h>
29
30#include <linux/leds.h>
31
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/card.h>
35#include <linux/mmc/sdio.h>
36#include <linux/mmc/slot-gpio.h>
37
38#include "sdhci.h"
39
40#define DRIVER_NAME "sdhci"
41
42#define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48#define MAX_TUNING_LOOP 40
49
50static unsigned int debug_quirks = 0;
51static unsigned int debug_quirks2;
52
53static void sdhci_finish_data(struct sdhci_host *);
54
55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57void sdhci_dumpregs(struct sdhci_host *host)
58{
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_ACMD12_ERR),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127{
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
129}
130
131static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
132{
133 u32 present;
134
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
137 return;
138
139 if (enable) {
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT;
142
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
145 } else {
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
147 }
148
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
151}
152
153static void sdhci_enable_card_detection(struct sdhci_host *host)
154{
155 sdhci_set_card_detection(host, true);
156}
157
158static void sdhci_disable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, false);
161}
162
163static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
164{
165 if (host->bus_on)
166 return;
167 host->bus_on = true;
168 pm_runtime_get_noresume(host->mmc->parent);
169}
170
171static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
172{
173 if (!host->bus_on)
174 return;
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
177}
178
179void sdhci_reset(struct sdhci_host *host, u8 mask)
180{
181 ktime_t timeout;
182
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184
185 if (mask & SDHCI_RESET_ALL) {
186 host->clock = 0;
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
190 }
191
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
194
195 /* hw clears the bit when it's done */
196 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 if (ktime_after(ktime_get(), timeout)) {
198 pr_err("%s: Reset 0x%x never completed.\n",
199 mmc_hostname(host->mmc), (int)mask);
200 sdhci_dumpregs(host);
201 return;
202 }
203 udelay(10);
204 }
205}
206EXPORT_SYMBOL_GPL(sdhci_reset);
207
208static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
209{
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 struct mmc_host *mmc = host->mmc;
212
213 if (!mmc->ops->get_cd(mmc))
214 return;
215 }
216
217 host->ops->reset(host, mask);
218
219 if (mask & SDHCI_RESET_ALL) {
220 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
221 if (host->ops->enable_dma)
222 host->ops->enable_dma(host);
223 }
224
225 /* Resetting the controller clears many */
226 host->preset_enabled = false;
227 }
228}
229
230static void sdhci_set_default_irqs(struct sdhci_host *host)
231{
232 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
233 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
234 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
235 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
236 SDHCI_INT_RESPONSE;
237
238 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
239 host->tuning_mode == SDHCI_TUNING_MODE_3)
240 host->ier |= SDHCI_INT_RETUNE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
244}
245
246static void sdhci_init(struct sdhci_host *host, int soft)
247{
248 struct mmc_host *mmc = host->mmc;
249
250 if (soft)
251 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
252 else
253 sdhci_do_reset(host, SDHCI_RESET_ALL);
254
255 sdhci_set_default_irqs(host);
256
257 host->cqe_on = false;
258
259 if (soft) {
260 /* force clock reconfiguration */
261 host->clock = 0;
262 mmc->ops->set_ios(mmc, &mmc->ios);
263 }
264}
265
266static void sdhci_reinit(struct sdhci_host *host)
267{
268 sdhci_init(host, 0);
269 sdhci_enable_card_detection(host);
270}
271
272static void __sdhci_led_activate(struct sdhci_host *host)
273{
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl |= SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279}
280
281static void __sdhci_led_deactivate(struct sdhci_host *host)
282{
283 u8 ctrl;
284
285 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
286 ctrl &= ~SDHCI_CTRL_LED;
287 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
288}
289
290#if IS_REACHABLE(CONFIG_LEDS_CLASS)
291static void sdhci_led_control(struct led_classdev *led,
292 enum led_brightness brightness)
293{
294 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
295 unsigned long flags;
296
297 spin_lock_irqsave(&host->lock, flags);
298
299 if (host->runtime_suspended)
300 goto out;
301
302 if (brightness == LED_OFF)
303 __sdhci_led_deactivate(host);
304 else
305 __sdhci_led_activate(host);
306out:
307 spin_unlock_irqrestore(&host->lock, flags);
308}
309
310static int sdhci_led_register(struct sdhci_host *host)
311{
312 struct mmc_host *mmc = host->mmc;
313
314 snprintf(host->led_name, sizeof(host->led_name),
315 "%s::", mmc_hostname(mmc));
316
317 host->led.name = host->led_name;
318 host->led.brightness = LED_OFF;
319 host->led.default_trigger = mmc_hostname(mmc);
320 host->led.brightness_set = sdhci_led_control;
321
322 return led_classdev_register(mmc_dev(mmc), &host->led);
323}
324
325static void sdhci_led_unregister(struct sdhci_host *host)
326{
327 led_classdev_unregister(&host->led);
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332}
333
334static inline void sdhci_led_deactivate(struct sdhci_host *host)
335{
336}
337
338#else
339
340static inline int sdhci_led_register(struct sdhci_host *host)
341{
342 return 0;
343}
344
345static inline void sdhci_led_unregister(struct sdhci_host *host)
346{
347}
348
349static inline void sdhci_led_activate(struct sdhci_host *host)
350{
351 __sdhci_led_activate(host);
352}
353
354static inline void sdhci_led_deactivate(struct sdhci_host *host)
355{
356 __sdhci_led_deactivate(host);
357}
358
359#endif
360
361/*****************************************************************************\
362 * *
363 * Core functions *
364 * *
365\*****************************************************************************/
366
367static void sdhci_read_block_pio(struct sdhci_host *host)
368{
369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 uninitialized_var(scratch);
372 u8 *buf;
373
374 DBG("PIO reading\n");
375
376 blksize = host->data->blksz;
377 chunk = 0;
378
379 local_irq_save(flags);
380
381 while (blksize) {
382 BUG_ON(!sg_miter_next(&host->sg_miter));
383
384 len = min(host->sg_miter.length, blksize);
385
386 blksize -= len;
387 host->sg_miter.consumed = len;
388
389 buf = host->sg_miter.addr;
390
391 while (len) {
392 if (chunk == 0) {
393 scratch = sdhci_readl(host, SDHCI_BUFFER);
394 chunk = 4;
395 }
396
397 *buf = scratch & 0xFF;
398
399 buf++;
400 scratch >>= 8;
401 chunk--;
402 len--;
403 }
404 }
405
406 sg_miter_stop(&host->sg_miter);
407
408 local_irq_restore(flags);
409}
410
411static void sdhci_write_block_pio(struct sdhci_host *host)
412{
413 unsigned long flags;
414 size_t blksize, len, chunk;
415 u32 scratch;
416 u8 *buf;
417
418 DBG("PIO writing\n");
419
420 blksize = host->data->blksz;
421 chunk = 0;
422 scratch = 0;
423
424 local_irq_save(flags);
425
426 while (blksize) {
427 BUG_ON(!sg_miter_next(&host->sg_miter));
428
429 len = min(host->sg_miter.length, blksize);
430
431 blksize -= len;
432 host->sg_miter.consumed = len;
433
434 buf = host->sg_miter.addr;
435
436 while (len) {
437 scratch |= (u32)*buf << (chunk * 8);
438
439 buf++;
440 chunk++;
441 len--;
442
443 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
444 sdhci_writel(host, scratch, SDHCI_BUFFER);
445 chunk = 0;
446 scratch = 0;
447 }
448 }
449 }
450
451 sg_miter_stop(&host->sg_miter);
452
453 local_irq_restore(flags);
454}
455
456static void sdhci_transfer_pio(struct sdhci_host *host)
457{
458 u32 mask;
459
460 if (host->blocks == 0)
461 return;
462
463 if (host->data->flags & MMC_DATA_READ)
464 mask = SDHCI_DATA_AVAILABLE;
465 else
466 mask = SDHCI_SPACE_AVAILABLE;
467
468 /*
469 * Some controllers (JMicron JMB38x) mess up the buffer bits
470 * for transfers < 4 bytes. As long as it is just one block,
471 * we can ignore the bits.
472 */
473 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
474 (host->data->blocks == 1))
475 mask = ~0;
476
477 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
478 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
479 udelay(100);
480
481 if (host->data->flags & MMC_DATA_READ)
482 sdhci_read_block_pio(host);
483 else
484 sdhci_write_block_pio(host);
485
486 host->blocks--;
487 if (host->blocks == 0)
488 break;
489 }
490
491 DBG("PIO transfer complete.\n");
492}
493
494static int sdhci_pre_dma_transfer(struct sdhci_host *host,
495 struct mmc_data *data, int cookie)
496{
497 int sg_count;
498
499 /*
500 * If the data buffers are already mapped, return the previous
501 * dma_map_sg() result.
502 */
503 if (data->host_cookie == COOKIE_PRE_MAPPED)
504 return data->sg_count;
505
506 /* Bounce write requests to the bounce buffer */
507 if (host->bounce_buffer) {
508 unsigned int length = data->blksz * data->blocks;
509
510 if (length > host->bounce_buffer_size) {
511 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
512 mmc_hostname(host->mmc), length,
513 host->bounce_buffer_size);
514 return -EIO;
515 }
516 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
517 /* Copy the data to the bounce buffer */
518 sg_copy_to_buffer(data->sg, data->sg_len,
519 host->bounce_buffer,
520 length);
521 }
522 /* Switch ownership to the DMA */
523 dma_sync_single_for_device(host->mmc->parent,
524 host->bounce_addr,
525 host->bounce_buffer_size,
526 mmc_get_dma_dir(data));
527 /* Just a dummy value */
528 sg_count = 1;
529 } else {
530 /* Just access the data directly from memory */
531 sg_count = dma_map_sg(mmc_dev(host->mmc),
532 data->sg, data->sg_len,
533 mmc_get_dma_dir(data));
534 }
535
536 if (sg_count == 0)
537 return -ENOSPC;
538
539 data->sg_count = sg_count;
540 data->host_cookie = cookie;
541
542 return sg_count;
543}
544
545static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
546{
547 local_irq_save(*flags);
548 return kmap_atomic(sg_page(sg)) + sg->offset;
549}
550
551static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
552{
553 kunmap_atomic(buffer);
554 local_irq_restore(*flags);
555}
556
557static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
558 dma_addr_t addr, int len, unsigned cmd)
559{
560 struct sdhci_adma2_64_desc *dma_desc = desc;
561
562 /* 32-bit and 64-bit descriptors have these members in same position */
563 dma_desc->cmd = cpu_to_le16(cmd);
564 dma_desc->len = cpu_to_le16(len);
565 dma_desc->addr_lo = cpu_to_le32((u32)addr);
566
567 if (host->flags & SDHCI_USE_64_BIT_DMA)
568 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
569}
570
571static void sdhci_adma_mark_end(void *desc)
572{
573 struct sdhci_adma2_64_desc *dma_desc = desc;
574
575 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
576 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
577}
578
579static void sdhci_adma_table_pre(struct sdhci_host *host,
580 struct mmc_data *data, int sg_count)
581{
582 struct scatterlist *sg;
583 unsigned long flags;
584 dma_addr_t addr, align_addr;
585 void *desc, *align;
586 char *buffer;
587 int len, offset, i;
588
589 /*
590 * The spec does not specify endianness of descriptor table.
591 * We currently guess that it is LE.
592 */
593
594 host->sg_count = sg_count;
595
596 desc = host->adma_table;
597 align = host->align_buffer;
598
599 align_addr = host->align_addr;
600
601 for_each_sg(data->sg, sg, host->sg_count, i) {
602 addr = sg_dma_address(sg);
603 len = sg_dma_len(sg);
604
605 /*
606 * The SDHCI specification states that ADMA addresses must
607 * be 32-bit aligned. If they aren't, then we use a bounce
608 * buffer for the (up to three) bytes that screw up the
609 * alignment.
610 */
611 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
612 SDHCI_ADMA2_MASK;
613 if (offset) {
614 if (data->flags & MMC_DATA_WRITE) {
615 buffer = sdhci_kmap_atomic(sg, &flags);
616 memcpy(align, buffer, offset);
617 sdhci_kunmap_atomic(buffer, &flags);
618 }
619
620 /* tran, valid */
621 sdhci_adma_write_desc(host, desc, align_addr, offset,
622 ADMA2_TRAN_VALID);
623
624 BUG_ON(offset > 65536);
625
626 align += SDHCI_ADMA2_ALIGN;
627 align_addr += SDHCI_ADMA2_ALIGN;
628
629 desc += host->desc_sz;
630
631 addr += offset;
632 len -= offset;
633 }
634
635 BUG_ON(len > 65536);
636
637 if (len) {
638 /* tran, valid */
639 sdhci_adma_write_desc(host, desc, addr, len,
640 ADMA2_TRAN_VALID);
641 desc += host->desc_sz;
642 }
643
644 /*
645 * If this triggers then we have a calculation bug
646 * somewhere. :/
647 */
648 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
649 }
650
651 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
652 /* Mark the last descriptor as the terminating descriptor */
653 if (desc != host->adma_table) {
654 desc -= host->desc_sz;
655 sdhci_adma_mark_end(desc);
656 }
657 } else {
658 /* Add a terminating entry - nop, end, valid */
659 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
660 }
661}
662
663static void sdhci_adma_table_post(struct sdhci_host *host,
664 struct mmc_data *data)
665{
666 struct scatterlist *sg;
667 int i, size;
668 void *align;
669 char *buffer;
670 unsigned long flags;
671
672 if (data->flags & MMC_DATA_READ) {
673 bool has_unaligned = false;
674
675 /* Do a quick scan of the SG list for any unaligned mappings */
676 for_each_sg(data->sg, sg, host->sg_count, i)
677 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
678 has_unaligned = true;
679 break;
680 }
681
682 if (has_unaligned) {
683 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
684 data->sg_len, DMA_FROM_DEVICE);
685
686 align = host->align_buffer;
687
688 for_each_sg(data->sg, sg, host->sg_count, i) {
689 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
690 size = SDHCI_ADMA2_ALIGN -
691 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
692
693 buffer = sdhci_kmap_atomic(sg, &flags);
694 memcpy(buffer, align, size);
695 sdhci_kunmap_atomic(buffer, &flags);
696
697 align += SDHCI_ADMA2_ALIGN;
698 }
699 }
700 }
701 }
702}
703
704static u32 sdhci_sdma_address(struct sdhci_host *host)
705{
706 if (host->bounce_buffer)
707 return host->bounce_addr;
708 else
709 return sg_dma_address(host->data->sg);
710}
711
712static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
713{
714 u8 count;
715 struct mmc_data *data = cmd->data;
716 unsigned target_timeout, current_timeout;
717
718 /*
719 * If the host controller provides us with an incorrect timeout
720 * value, just skip the check and use 0xE. The hardware may take
721 * longer to time out, but that's much better than having a too-short
722 * timeout value.
723 */
724 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
725 return 0xE;
726
727 /* Unspecified timeout, assume max */
728 if (!data && !cmd->busy_timeout)
729 return 0xE;
730
731 /* timeout in us */
732 if (!data)
733 target_timeout = cmd->busy_timeout * 1000;
734 else {
735 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
736 if (host->clock && data->timeout_clks) {
737 unsigned long long val;
738
739 /*
740 * data->timeout_clks is in units of clock cycles.
741 * host->clock is in Hz. target_timeout is in us.
742 * Hence, us = 1000000 * cycles / Hz. Round up.
743 */
744 val = 1000000ULL * data->timeout_clks;
745 if (do_div(val, host->clock))
746 target_timeout++;
747 target_timeout += val;
748 }
749 }
750
751 /*
752 * Figure out needed cycles.
753 * We do this in steps in order to fit inside a 32 bit int.
754 * The first step is the minimum timeout, which will have a
755 * minimum resolution of 6 bits:
756 * (1) 2^13*1000 > 2^22,
757 * (2) host->timeout_clk < 2^16
758 * =>
759 * (1) / (2) > 2^6
760 */
761 count = 0;
762 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
763 while (current_timeout < target_timeout) {
764 count++;
765 current_timeout <<= 1;
766 if (count >= 0xF)
767 break;
768 }
769
770 if (count >= 0xF) {
771 DBG("Too large timeout 0x%x requested for CMD%d!\n",
772 count, cmd->opcode);
773 count = 0xE;
774 }
775
776 return count;
777}
778
779static void sdhci_set_transfer_irqs(struct sdhci_host *host)
780{
781 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
782 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
783
784 if (host->flags & SDHCI_REQ_USE_DMA)
785 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
786 else
787 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
788
789 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
790 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
791}
792
793static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
794{
795 u8 count;
796
797 if (host->ops->set_timeout) {
798 host->ops->set_timeout(host, cmd);
799 } else {
800 count = sdhci_calc_timeout(host, cmd);
801 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
802 }
803}
804
805static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
806{
807 u8 ctrl;
808 struct mmc_data *data = cmd->data;
809
810 if (sdhci_data_line_cmd(cmd))
811 sdhci_set_timeout(host, cmd);
812
813 if (!data)
814 return;
815
816 WARN_ON(host->data);
817
818 /* Sanity checks */
819 BUG_ON(data->blksz * data->blocks > 524288);
820 BUG_ON(data->blksz > host->mmc->max_blk_size);
821 BUG_ON(data->blocks > 65535);
822
823 host->data = data;
824 host->data_early = 0;
825 host->data->bytes_xfered = 0;
826
827 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
828 struct scatterlist *sg;
829 unsigned int length_mask, offset_mask;
830 int i;
831
832 host->flags |= SDHCI_REQ_USE_DMA;
833
834 /*
835 * FIXME: This doesn't account for merging when mapping the
836 * scatterlist.
837 *
838 * The assumption here being that alignment and lengths are
839 * the same after DMA mapping to device address space.
840 */
841 length_mask = 0;
842 offset_mask = 0;
843 if (host->flags & SDHCI_USE_ADMA) {
844 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
845 length_mask = 3;
846 /*
847 * As we use up to 3 byte chunks to work
848 * around alignment problems, we need to
849 * check the offset as well.
850 */
851 offset_mask = 3;
852 }
853 } else {
854 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
855 length_mask = 3;
856 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
857 offset_mask = 3;
858 }
859
860 if (unlikely(length_mask | offset_mask)) {
861 for_each_sg(data->sg, sg, data->sg_len, i) {
862 if (sg->length & length_mask) {
863 DBG("Reverting to PIO because of transfer size (%d)\n",
864 sg->length);
865 host->flags &= ~SDHCI_REQ_USE_DMA;
866 break;
867 }
868 if (sg->offset & offset_mask) {
869 DBG("Reverting to PIO because of bad alignment\n");
870 host->flags &= ~SDHCI_REQ_USE_DMA;
871 break;
872 }
873 }
874 }
875 }
876
877 if (host->flags & SDHCI_REQ_USE_DMA) {
878 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
879
880 if (sg_cnt <= 0) {
881 /*
882 * This only happens when someone fed
883 * us an invalid request.
884 */
885 WARN_ON(1);
886 host->flags &= ~SDHCI_REQ_USE_DMA;
887 } else if (host->flags & SDHCI_USE_ADMA) {
888 sdhci_adma_table_pre(host, data, sg_cnt);
889
890 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
891 if (host->flags & SDHCI_USE_64_BIT_DMA)
892 sdhci_writel(host,
893 (u64)host->adma_addr >> 32,
894 SDHCI_ADMA_ADDRESS_HI);
895 } else {
896 WARN_ON(sg_cnt != 1);
897 sdhci_writel(host, sdhci_sdma_address(host),
898 SDHCI_DMA_ADDRESS);
899 }
900 }
901
902 /*
903 * Always adjust the DMA selection as some controllers
904 * (e.g. JMicron) can't do PIO properly when the selection
905 * is ADMA.
906 */
907 if (host->version >= SDHCI_SPEC_200) {
908 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
909 ctrl &= ~SDHCI_CTRL_DMA_MASK;
910 if ((host->flags & SDHCI_REQ_USE_DMA) &&
911 (host->flags & SDHCI_USE_ADMA)) {
912 if (host->flags & SDHCI_USE_64_BIT_DMA)
913 ctrl |= SDHCI_CTRL_ADMA64;
914 else
915 ctrl |= SDHCI_CTRL_ADMA32;
916 } else {
917 ctrl |= SDHCI_CTRL_SDMA;
918 }
919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
920 }
921
922 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
923 int flags;
924
925 flags = SG_MITER_ATOMIC;
926 if (host->data->flags & MMC_DATA_READ)
927 flags |= SG_MITER_TO_SG;
928 else
929 flags |= SG_MITER_FROM_SG;
930 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
931 host->blocks = data->blocks;
932 }
933
934 sdhci_set_transfer_irqs(host);
935
936 /* Set the DMA boundary value and block size */
937 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
938 SDHCI_BLOCK_SIZE);
939 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
940}
941
942static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
943 struct mmc_request *mrq)
944{
945 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
946 !mrq->cap_cmd_during_tfr;
947}
948
949static void sdhci_set_transfer_mode(struct sdhci_host *host,
950 struct mmc_command *cmd)
951{
952 u16 mode = 0;
953 struct mmc_data *data = cmd->data;
954
955 if (data == NULL) {
956 if (host->quirks2 &
957 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
958 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
959 } else {
960 /* clear Auto CMD settings for no data CMDs */
961 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
962 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
963 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
964 }
965 return;
966 }
967
968 WARN_ON(!host->data);
969
970 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
971 mode = SDHCI_TRNS_BLK_CNT_EN;
972
973 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
974 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
975 /*
976 * If we are sending CMD23, CMD12 never gets sent
977 * on successful completion (so no Auto-CMD12).
978 */
979 if (sdhci_auto_cmd12(host, cmd->mrq) &&
980 (cmd->opcode != SD_IO_RW_EXTENDED))
981 mode |= SDHCI_TRNS_AUTO_CMD12;
982 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
983 mode |= SDHCI_TRNS_AUTO_CMD23;
984 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
985 }
986 }
987
988 if (data->flags & MMC_DATA_READ)
989 mode |= SDHCI_TRNS_READ;
990 if (host->flags & SDHCI_REQ_USE_DMA)
991 mode |= SDHCI_TRNS_DMA;
992
993 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
994}
995
996static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
997{
998 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
999 ((mrq->cmd && mrq->cmd->error) ||
1000 (mrq->sbc && mrq->sbc->error) ||
1001 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
1002 (mrq->data->stop && mrq->data->stop->error))) ||
1003 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1004}
1005
1006static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1007{
1008 int i;
1009
1010 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1011 if (host->mrqs_done[i] == mrq) {
1012 WARN_ON(1);
1013 return;
1014 }
1015 }
1016
1017 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1018 if (!host->mrqs_done[i]) {
1019 host->mrqs_done[i] = mrq;
1020 break;
1021 }
1022 }
1023
1024 WARN_ON(i >= SDHCI_MAX_MRQS);
1025
1026 tasklet_schedule(&host->finish_tasklet);
1027}
1028
1029static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1030{
1031 if (host->cmd && host->cmd->mrq == mrq)
1032 host->cmd = NULL;
1033
1034 if (host->data_cmd && host->data_cmd->mrq == mrq)
1035 host->data_cmd = NULL;
1036
1037 if (host->data && host->data->mrq == mrq)
1038 host->data = NULL;
1039
1040 if (sdhci_needs_reset(host, mrq))
1041 host->pending_reset = true;
1042
1043 __sdhci_finish_mrq(host, mrq);
1044}
1045
1046static void sdhci_finish_data(struct sdhci_host *host)
1047{
1048 struct mmc_command *data_cmd = host->data_cmd;
1049 struct mmc_data *data = host->data;
1050
1051 host->data = NULL;
1052 host->data_cmd = NULL;
1053
1054 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1055 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1056 sdhci_adma_table_post(host, data);
1057
1058 /*
1059 * The specification states that the block count register must
1060 * be updated, but it does not specify at what point in the
1061 * data flow. That makes the register entirely useless to read
1062 * back so we have to assume that nothing made it to the card
1063 * in the event of an error.
1064 */
1065 if (data->error)
1066 data->bytes_xfered = 0;
1067 else
1068 data->bytes_xfered = data->blksz * data->blocks;
1069
1070 /*
1071 * Need to send CMD12 if -
1072 * a) open-ended multiblock transfer (no CMD23)
1073 * b) error in multiblock transfer
1074 */
1075 if (data->stop &&
1076 (data->error ||
1077 !data->mrq->sbc)) {
1078
1079 /*
1080 * The controller needs a reset of internal state machines
1081 * upon error conditions.
1082 */
1083 if (data->error) {
1084 if (!host->cmd || host->cmd == data_cmd)
1085 sdhci_do_reset(host, SDHCI_RESET_CMD);
1086 sdhci_do_reset(host, SDHCI_RESET_DATA);
1087 }
1088
1089 /*
1090 * 'cap_cmd_during_tfr' request must not use the command line
1091 * after mmc_command_done() has been called. It is upper layer's
1092 * responsibility to send the stop command if required.
1093 */
1094 if (data->mrq->cap_cmd_during_tfr) {
1095 sdhci_finish_mrq(host, data->mrq);
1096 } else {
1097 /* Avoid triggering warning in sdhci_send_command() */
1098 host->cmd = NULL;
1099 sdhci_send_command(host, data->stop);
1100 }
1101 } else {
1102 sdhci_finish_mrq(host, data->mrq);
1103 }
1104}
1105
1106static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1107 unsigned long timeout)
1108{
1109 if (sdhci_data_line_cmd(mrq->cmd))
1110 mod_timer(&host->data_timer, timeout);
1111 else
1112 mod_timer(&host->timer, timeout);
1113}
1114
1115static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1116{
1117 if (sdhci_data_line_cmd(mrq->cmd))
1118 del_timer(&host->data_timer);
1119 else
1120 del_timer(&host->timer);
1121}
1122
1123void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1124{
1125 int flags;
1126 u32 mask;
1127 unsigned long timeout;
1128
1129 WARN_ON(host->cmd);
1130
1131 /* Initially, a command has no error */
1132 cmd->error = 0;
1133
1134 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1135 cmd->opcode == MMC_STOP_TRANSMISSION)
1136 cmd->flags |= MMC_RSP_BUSY;
1137
1138 /* Wait max 10 ms */
1139 timeout = 10;
1140
1141 mask = SDHCI_CMD_INHIBIT;
1142 if (sdhci_data_line_cmd(cmd))
1143 mask |= SDHCI_DATA_INHIBIT;
1144
1145 /* We shouldn't wait for data inihibit for stop commands, even
1146 though they might use busy signaling */
1147 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1148 mask &= ~SDHCI_DATA_INHIBIT;
1149
1150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1151 if (timeout == 0) {
1152 pr_err("%s: Controller never released inhibit bit(s).\n",
1153 mmc_hostname(host->mmc));
1154 sdhci_dumpregs(host);
1155 cmd->error = -EIO;
1156 sdhci_finish_mrq(host, cmd->mrq);
1157 return;
1158 }
1159 timeout--;
1160 mdelay(1);
1161 }
1162
1163 timeout = jiffies;
1164 if (!cmd->data && cmd->busy_timeout > 9000)
1165 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1166 else
1167 timeout += 10 * HZ;
1168 sdhci_mod_timer(host, cmd->mrq, timeout);
1169
1170 host->cmd = cmd;
1171 if (sdhci_data_line_cmd(cmd)) {
1172 WARN_ON(host->data_cmd);
1173 host->data_cmd = cmd;
1174 }
1175
1176 sdhci_prepare_data(host, cmd);
1177
1178 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1179
1180 sdhci_set_transfer_mode(host, cmd);
1181
1182 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1183 pr_err("%s: Unsupported response type!\n",
1184 mmc_hostname(host->mmc));
1185 cmd->error = -EINVAL;
1186 sdhci_finish_mrq(host, cmd->mrq);
1187 return;
1188 }
1189
1190 if (!(cmd->flags & MMC_RSP_PRESENT))
1191 flags = SDHCI_CMD_RESP_NONE;
1192 else if (cmd->flags & MMC_RSP_136)
1193 flags = SDHCI_CMD_RESP_LONG;
1194 else if (cmd->flags & MMC_RSP_BUSY)
1195 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1196 else
1197 flags = SDHCI_CMD_RESP_SHORT;
1198
1199 if (cmd->flags & MMC_RSP_CRC)
1200 flags |= SDHCI_CMD_CRC;
1201 if (cmd->flags & MMC_RSP_OPCODE)
1202 flags |= SDHCI_CMD_INDEX;
1203
1204 /* CMD19 is special in that the Data Present Select should be set */
1205 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1206 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1207 flags |= SDHCI_CMD_DATA;
1208
1209 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1210}
1211EXPORT_SYMBOL_GPL(sdhci_send_command);
1212
1213static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1214{
1215 int i, reg;
1216
1217 for (i = 0; i < 4; i++) {
1218 reg = SDHCI_RESPONSE + (3 - i) * 4;
1219 cmd->resp[i] = sdhci_readl(host, reg);
1220 }
1221
1222 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1223 return;
1224
1225 /* CRC is stripped so we need to do some shifting */
1226 for (i = 0; i < 4; i++) {
1227 cmd->resp[i] <<= 8;
1228 if (i != 3)
1229 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1230 }
1231}
1232
1233static void sdhci_finish_command(struct sdhci_host *host)
1234{
1235 struct mmc_command *cmd = host->cmd;
1236
1237 host->cmd = NULL;
1238
1239 if (cmd->flags & MMC_RSP_PRESENT) {
1240 if (cmd->flags & MMC_RSP_136) {
1241 sdhci_read_rsp_136(host, cmd);
1242 } else {
1243 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1244 }
1245 }
1246
1247 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1248 mmc_command_done(host->mmc, cmd->mrq);
1249
1250 /*
1251 * The host can send and interrupt when the busy state has
1252 * ended, allowing us to wait without wasting CPU cycles.
1253 * The busy signal uses DAT0 so this is similar to waiting
1254 * for data to complete.
1255 *
1256 * Note: The 1.0 specification is a bit ambiguous about this
1257 * feature so there might be some problems with older
1258 * controllers.
1259 */
1260 if (cmd->flags & MMC_RSP_BUSY) {
1261 if (cmd->data) {
1262 DBG("Cannot wait for busy signal when also doing a data transfer");
1263 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1264 cmd == host->data_cmd) {
1265 /* Command complete before busy is ended */
1266 return;
1267 }
1268 }
1269
1270 /* Finished CMD23, now send actual command. */
1271 if (cmd == cmd->mrq->sbc) {
1272 sdhci_send_command(host, cmd->mrq->cmd);
1273 } else {
1274
1275 /* Processed actual command. */
1276 if (host->data && host->data_early)
1277 sdhci_finish_data(host);
1278
1279 if (!cmd->data)
1280 sdhci_finish_mrq(host, cmd->mrq);
1281 }
1282}
1283
1284static u16 sdhci_get_preset_value(struct sdhci_host *host)
1285{
1286 u16 preset = 0;
1287
1288 switch (host->timing) {
1289 case MMC_TIMING_UHS_SDR12:
1290 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1291 break;
1292 case MMC_TIMING_UHS_SDR25:
1293 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1294 break;
1295 case MMC_TIMING_UHS_SDR50:
1296 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1297 break;
1298 case MMC_TIMING_UHS_SDR104:
1299 case MMC_TIMING_MMC_HS200:
1300 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1301 break;
1302 case MMC_TIMING_UHS_DDR50:
1303 case MMC_TIMING_MMC_DDR52:
1304 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1305 break;
1306 case MMC_TIMING_MMC_HS400:
1307 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1308 break;
1309 default:
1310 pr_warn("%s: Invalid UHS-I mode selected\n",
1311 mmc_hostname(host->mmc));
1312 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1313 break;
1314 }
1315 return preset;
1316}
1317
1318u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1319 unsigned int *actual_clock)
1320{
1321 int div = 0; /* Initialized for compiler warning */
1322 int real_div = div, clk_mul = 1;
1323 u16 clk = 0;
1324 bool switch_base_clk = false;
1325
1326 if (host->version >= SDHCI_SPEC_300) {
1327 if (host->preset_enabled) {
1328 u16 pre_val;
1329
1330 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1331 pre_val = sdhci_get_preset_value(host);
1332 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1333 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1334 if (host->clk_mul &&
1335 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1336 clk = SDHCI_PROG_CLOCK_MODE;
1337 real_div = div + 1;
1338 clk_mul = host->clk_mul;
1339 } else {
1340 real_div = max_t(int, 1, div << 1);
1341 }
1342 goto clock_set;
1343 }
1344
1345 /*
1346 * Check if the Host Controller supports Programmable Clock
1347 * Mode.
1348 */
1349 if (host->clk_mul) {
1350 for (div = 1; div <= 1024; div++) {
1351 if ((host->max_clk * host->clk_mul / div)
1352 <= clock)
1353 break;
1354 }
1355 if ((host->max_clk * host->clk_mul / div) <= clock) {
1356 /*
1357 * Set Programmable Clock Mode in the Clock
1358 * Control register.
1359 */
1360 clk = SDHCI_PROG_CLOCK_MODE;
1361 real_div = div;
1362 clk_mul = host->clk_mul;
1363 div--;
1364 } else {
1365 /*
1366 * Divisor can be too small to reach clock
1367 * speed requirement. Then use the base clock.
1368 */
1369 switch_base_clk = true;
1370 }
1371 }
1372
1373 if (!host->clk_mul || switch_base_clk) {
1374 /* Version 3.00 divisors must be a multiple of 2. */
1375 if (host->max_clk <= clock)
1376 div = 1;
1377 else {
1378 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1379 div += 2) {
1380 if ((host->max_clk / div) <= clock)
1381 break;
1382 }
1383 }
1384 real_div = div;
1385 div >>= 1;
1386 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1387 && !div && host->max_clk <= 25000000)
1388 div = 1;
1389 }
1390 } else {
1391 /* Version 2.00 divisors must be a power of 2. */
1392 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1393 if ((host->max_clk / div) <= clock)
1394 break;
1395 }
1396 real_div = div;
1397 div >>= 1;
1398 }
1399
1400clock_set:
1401 if (real_div)
1402 *actual_clock = (host->max_clk * clk_mul) / real_div;
1403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1405 << SDHCI_DIVIDER_HI_SHIFT;
1406
1407 return clk;
1408}
1409EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1410
1411void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1412{
1413 ktime_t timeout;
1414
1415 clk |= SDHCI_CLOCK_INT_EN;
1416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1417
1418 /* Wait max 20 ms */
1419 timeout = ktime_add_ms(ktime_get(), 20);
1420 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1421 & SDHCI_CLOCK_INT_STABLE)) {
1422 if (ktime_after(ktime_get(), timeout)) {
1423 pr_err("%s: Internal clock never stabilised.\n",
1424 mmc_hostname(host->mmc));
1425 sdhci_dumpregs(host);
1426 return;
1427 }
1428 udelay(10);
1429 }
1430
1431 clk |= SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433}
1434EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1435
1436void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1437{
1438 u16 clk;
1439
1440 host->mmc->actual_clock = 0;
1441
1442 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1443
1444 if (clock == 0)
1445 return;
1446
1447 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1448 sdhci_enable_clk(host, clk);
1449}
1450EXPORT_SYMBOL_GPL(sdhci_set_clock);
1451
1452static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1453 unsigned short vdd)
1454{
1455 struct mmc_host *mmc = host->mmc;
1456
1457 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1458
1459 if (mode != MMC_POWER_OFF)
1460 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1461 else
1462 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1463}
1464
1465void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1466 unsigned short vdd)
1467{
1468 u8 pwr = 0;
1469
1470 if (mode != MMC_POWER_OFF) {
1471 switch (1 << vdd) {
1472 case MMC_VDD_165_195:
1473 /*
1474 * Without a regulator, SDHCI does not support 2.0v
1475 * so we only get here if the driver deliberately
1476 * added the 2.0v range to ocr_avail. Map it to 1.8v
1477 * for the purpose of turning on the power.
1478 */
1479 case MMC_VDD_20_21:
1480 pwr = SDHCI_POWER_180;
1481 break;
1482 case MMC_VDD_29_30:
1483 case MMC_VDD_30_31:
1484 pwr = SDHCI_POWER_300;
1485 break;
1486 case MMC_VDD_32_33:
1487 case MMC_VDD_33_34:
1488 pwr = SDHCI_POWER_330;
1489 break;
1490 default:
1491 WARN(1, "%s: Invalid vdd %#x\n",
1492 mmc_hostname(host->mmc), vdd);
1493 break;
1494 }
1495 }
1496
1497 if (host->pwr == pwr)
1498 return;
1499
1500 host->pwr = pwr;
1501
1502 if (pwr == 0) {
1503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1504 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1505 sdhci_runtime_pm_bus_off(host);
1506 } else {
1507 /*
1508 * Spec says that we should clear the power reg before setting
1509 * a new value. Some controllers don't seem to like this though.
1510 */
1511 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1512 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1513
1514 /*
1515 * At least the Marvell CaFe chip gets confused if we set the
1516 * voltage and set turn on power at the same time, so set the
1517 * voltage first.
1518 */
1519 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1520 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1521
1522 pwr |= SDHCI_POWER_ON;
1523
1524 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1525
1526 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1527 sdhci_runtime_pm_bus_on(host);
1528
1529 /*
1530 * Some controllers need an extra 10ms delay of 10ms before
1531 * they can apply clock after applying power
1532 */
1533 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1534 mdelay(10);
1535 }
1536}
1537EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1538
1539void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1540 unsigned short vdd)
1541{
1542 if (IS_ERR(host->mmc->supply.vmmc))
1543 sdhci_set_power_noreg(host, mode, vdd);
1544 else
1545 sdhci_set_power_reg(host, mode, vdd);
1546}
1547EXPORT_SYMBOL_GPL(sdhci_set_power);
1548
1549/*****************************************************************************\
1550 * *
1551 * MMC callbacks *
1552 * *
1553\*****************************************************************************/
1554
1555static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1556{
1557 struct sdhci_host *host;
1558 int present;
1559 unsigned long flags;
1560
1561 host = mmc_priv(mmc);
1562
1563 /* Firstly check card presence */
1564 present = mmc->ops->get_cd(mmc);
1565
1566 spin_lock_irqsave(&host->lock, flags);
1567
1568 sdhci_led_activate(host);
1569
1570 /*
1571 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1572 * requests if Auto-CMD12 is enabled.
1573 */
1574 if (sdhci_auto_cmd12(host, mrq)) {
1575 if (mrq->stop) {
1576 mrq->data->stop = NULL;
1577 mrq->stop = NULL;
1578 }
1579 }
1580
1581 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1582 mrq->cmd->error = -ENOMEDIUM;
1583 sdhci_finish_mrq(host, mrq);
1584 } else {
1585 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1586 sdhci_send_command(host, mrq->sbc);
1587 else
1588 sdhci_send_command(host, mrq->cmd);
1589 }
1590
1591 mmiowb();
1592 spin_unlock_irqrestore(&host->lock, flags);
1593}
1594
1595void sdhci_set_bus_width(struct sdhci_host *host, int width)
1596{
1597 u8 ctrl;
1598
1599 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1600 if (width == MMC_BUS_WIDTH_8) {
1601 ctrl &= ~SDHCI_CTRL_4BITBUS;
1602 ctrl |= SDHCI_CTRL_8BITBUS;
1603 } else {
1604 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1605 ctrl &= ~SDHCI_CTRL_8BITBUS;
1606 if (width == MMC_BUS_WIDTH_4)
1607 ctrl |= SDHCI_CTRL_4BITBUS;
1608 else
1609 ctrl &= ~SDHCI_CTRL_4BITBUS;
1610 }
1611 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1612}
1613EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1614
1615void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1616{
1617 u16 ctrl_2;
1618
1619 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1620 /* Select Bus Speed Mode for host */
1621 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1622 if ((timing == MMC_TIMING_MMC_HS200) ||
1623 (timing == MMC_TIMING_UHS_SDR104))
1624 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1625 else if (timing == MMC_TIMING_UHS_SDR12)
1626 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1627 else if (timing == MMC_TIMING_UHS_SDR25)
1628 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1629 else if (timing == MMC_TIMING_UHS_SDR50)
1630 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1631 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1632 (timing == MMC_TIMING_MMC_DDR52))
1633 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1634 else if (timing == MMC_TIMING_MMC_HS400)
1635 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1636 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1637}
1638EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1639
1640void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 u8 ctrl;
1644
1645 if (ios->power_mode == MMC_POWER_UNDEFINED)
1646 return;
1647
1648 if (host->flags & SDHCI_DEVICE_DEAD) {
1649 if (!IS_ERR(mmc->supply.vmmc) &&
1650 ios->power_mode == MMC_POWER_OFF)
1651 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1652 return;
1653 }
1654
1655 /*
1656 * Reset the chip on each power off.
1657 * Should clear out any weird states.
1658 */
1659 if (ios->power_mode == MMC_POWER_OFF) {
1660 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1661 sdhci_reinit(host);
1662 }
1663
1664 if (host->version >= SDHCI_SPEC_300 &&
1665 (ios->power_mode == MMC_POWER_UP) &&
1666 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1667 sdhci_enable_preset_value(host, false);
1668
1669 if (!ios->clock || ios->clock != host->clock) {
1670 host->ops->set_clock(host, ios->clock);
1671 host->clock = ios->clock;
1672
1673 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1674 host->clock) {
1675 host->timeout_clk = host->mmc->actual_clock ?
1676 host->mmc->actual_clock / 1000 :
1677 host->clock / 1000;
1678 host->mmc->max_busy_timeout =
1679 host->ops->get_max_timeout_count ?
1680 host->ops->get_max_timeout_count(host) :
1681 1 << 27;
1682 host->mmc->max_busy_timeout /= host->timeout_clk;
1683 }
1684 }
1685
1686 if (host->ops->set_power)
1687 host->ops->set_power(host, ios->power_mode, ios->vdd);
1688 else
1689 sdhci_set_power(host, ios->power_mode, ios->vdd);
1690
1691 if (host->ops->platform_send_init_74_clocks)
1692 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1693
1694 host->ops->set_bus_width(host, ios->bus_width);
1695
1696 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1697
1698 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1699 if (ios->timing == MMC_TIMING_SD_HS ||
1700 ios->timing == MMC_TIMING_MMC_HS ||
1701 ios->timing == MMC_TIMING_MMC_HS400 ||
1702 ios->timing == MMC_TIMING_MMC_HS200 ||
1703 ios->timing == MMC_TIMING_MMC_DDR52 ||
1704 ios->timing == MMC_TIMING_UHS_SDR50 ||
1705 ios->timing == MMC_TIMING_UHS_SDR104 ||
1706 ios->timing == MMC_TIMING_UHS_DDR50 ||
1707 ios->timing == MMC_TIMING_UHS_SDR25)
1708 ctrl |= SDHCI_CTRL_HISPD;
1709 else
1710 ctrl &= ~SDHCI_CTRL_HISPD;
1711 }
1712
1713 if (host->version >= SDHCI_SPEC_300) {
1714 u16 clk, ctrl_2;
1715
1716 if (!host->preset_enabled) {
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1718 /*
1719 * We only need to set Driver Strength if the
1720 * preset value enable is not set.
1721 */
1722 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1723 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1724 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1725 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1726 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1727 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1728 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1729 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1730 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1731 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1732 else {
1733 pr_warn("%s: invalid driver type, default to driver type B\n",
1734 mmc_hostname(mmc));
1735 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1736 }
1737
1738 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1739 } else {
1740 /*
1741 * According to SDHC Spec v3.00, if the Preset Value
1742 * Enable in the Host Control 2 register is set, we
1743 * need to reset SD Clock Enable before changing High
1744 * Speed Enable to avoid generating clock gliches.
1745 */
1746
1747 /* Reset SD Clock Enable */
1748 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1749 clk &= ~SDHCI_CLOCK_CARD_EN;
1750 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1751
1752 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1753
1754 /* Re-enable SD Clock */
1755 host->ops->set_clock(host, host->clock);
1756 }
1757
1758 /* Reset SD Clock Enable */
1759 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1760 clk &= ~SDHCI_CLOCK_CARD_EN;
1761 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1762
1763 host->ops->set_uhs_signaling(host, ios->timing);
1764 host->timing = ios->timing;
1765
1766 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1767 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1768 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1769 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1770 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1771 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1772 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1773 u16 preset;
1774
1775 sdhci_enable_preset_value(host, true);
1776 preset = sdhci_get_preset_value(host);
1777 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1778 >> SDHCI_PRESET_DRV_SHIFT;
1779 }
1780
1781 /* Re-enable SD Clock */
1782 host->ops->set_clock(host, host->clock);
1783 } else
1784 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1785
1786 /*
1787 * Some (ENE) controllers go apeshit on some ios operation,
1788 * signalling timeout and CRC errors even on CMD0. Resetting
1789 * it on each ios seems to solve the problem.
1790 */
1791 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1792 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1793
1794 mmiowb();
1795}
1796EXPORT_SYMBOL_GPL(sdhci_set_ios);
1797
1798static int sdhci_get_cd(struct mmc_host *mmc)
1799{
1800 struct sdhci_host *host = mmc_priv(mmc);
1801 int gpio_cd = mmc_gpio_get_cd(mmc);
1802
1803 if (host->flags & SDHCI_DEVICE_DEAD)
1804 return 0;
1805
1806 /* If nonremovable, assume that the card is always present. */
1807 if (!mmc_card_is_removable(host->mmc))
1808 return 1;
1809
1810 /*
1811 * Try slot gpio detect, if defined it take precedence
1812 * over build in controller functionality
1813 */
1814 if (gpio_cd >= 0)
1815 return !!gpio_cd;
1816
1817 /* If polling, assume that the card is always present. */
1818 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1819 return 1;
1820
1821 /* Host native card detect */
1822 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1823}
1824
1825static int sdhci_check_ro(struct sdhci_host *host)
1826{
1827 unsigned long flags;
1828 int is_readonly;
1829
1830 spin_lock_irqsave(&host->lock, flags);
1831
1832 if (host->flags & SDHCI_DEVICE_DEAD)
1833 is_readonly = 0;
1834 else if (host->ops->get_ro)
1835 is_readonly = host->ops->get_ro(host);
1836 else
1837 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1838 & SDHCI_WRITE_PROTECT);
1839
1840 spin_unlock_irqrestore(&host->lock, flags);
1841
1842 /* This quirk needs to be replaced by a callback-function later */
1843 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1844 !is_readonly : is_readonly;
1845}
1846
1847#define SAMPLE_COUNT 5
1848
1849static int sdhci_get_ro(struct mmc_host *mmc)
1850{
1851 struct sdhci_host *host = mmc_priv(mmc);
1852 int i, ro_count;
1853
1854 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1855 return sdhci_check_ro(host);
1856
1857 ro_count = 0;
1858 for (i = 0; i < SAMPLE_COUNT; i++) {
1859 if (sdhci_check_ro(host)) {
1860 if (++ro_count > SAMPLE_COUNT / 2)
1861 return 1;
1862 }
1863 msleep(30);
1864 }
1865 return 0;
1866}
1867
1868static void sdhci_hw_reset(struct mmc_host *mmc)
1869{
1870 struct sdhci_host *host = mmc_priv(mmc);
1871
1872 if (host->ops && host->ops->hw_reset)
1873 host->ops->hw_reset(host);
1874}
1875
1876static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1877{
1878 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1879 if (enable)
1880 host->ier |= SDHCI_INT_CARD_INT;
1881 else
1882 host->ier &= ~SDHCI_INT_CARD_INT;
1883
1884 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1885 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1886 mmiowb();
1887 }
1888}
1889
1890void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1891{
1892 struct sdhci_host *host = mmc_priv(mmc);
1893 unsigned long flags;
1894
1895 if (enable)
1896 pm_runtime_get_noresume(host->mmc->parent);
1897
1898 spin_lock_irqsave(&host->lock, flags);
1899 if (enable)
1900 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1901 else
1902 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1903
1904 sdhci_enable_sdio_irq_nolock(host, enable);
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 if (!enable)
1908 pm_runtime_put_noidle(host->mmc->parent);
1909}
1910EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1911
1912int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1913 struct mmc_ios *ios)
1914{
1915 struct sdhci_host *host = mmc_priv(mmc);
1916 u16 ctrl;
1917 int ret;
1918
1919 /*
1920 * Signal Voltage Switching is only applicable for Host Controllers
1921 * v3.00 and above.
1922 */
1923 if (host->version < SDHCI_SPEC_300)
1924 return 0;
1925
1926 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927
1928 switch (ios->signal_voltage) {
1929 case MMC_SIGNAL_VOLTAGE_330:
1930 if (!(host->flags & SDHCI_SIGNALING_330))
1931 return -EINVAL;
1932 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1933 ctrl &= ~SDHCI_CTRL_VDD_180;
1934 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1935
1936 if (!IS_ERR(mmc->supply.vqmmc)) {
1937 ret = mmc_regulator_set_vqmmc(mmc, ios);
1938 if (ret) {
1939 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1940 mmc_hostname(mmc));
1941 return -EIO;
1942 }
1943 }
1944 /* Wait for 5ms */
1945 usleep_range(5000, 5500);
1946
1947 /* 3.3V regulator output should be stable within 5 ms */
1948 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1949 if (!(ctrl & SDHCI_CTRL_VDD_180))
1950 return 0;
1951
1952 pr_warn("%s: 3.3V regulator output did not became stable\n",
1953 mmc_hostname(mmc));
1954
1955 return -EAGAIN;
1956 case MMC_SIGNAL_VOLTAGE_180:
1957 if (!(host->flags & SDHCI_SIGNALING_180))
1958 return -EINVAL;
1959 if (!IS_ERR(mmc->supply.vqmmc)) {
1960 ret = mmc_regulator_set_vqmmc(mmc, ios);
1961 if (ret) {
1962 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1963 mmc_hostname(mmc));
1964 return -EIO;
1965 }
1966 }
1967
1968 /*
1969 * Enable 1.8V Signal Enable in the Host Control2
1970 * register
1971 */
1972 ctrl |= SDHCI_CTRL_VDD_180;
1973 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1974
1975 /* Some controller need to do more when switching */
1976 if (host->ops->voltage_switch)
1977 host->ops->voltage_switch(host);
1978
1979 /* 1.8V regulator output should be stable within 5 ms */
1980 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1981 if (ctrl & SDHCI_CTRL_VDD_180)
1982 return 0;
1983
1984 pr_warn("%s: 1.8V regulator output did not became stable\n",
1985 mmc_hostname(mmc));
1986
1987 return -EAGAIN;
1988 case MMC_SIGNAL_VOLTAGE_120:
1989 if (!(host->flags & SDHCI_SIGNALING_120))
1990 return -EINVAL;
1991 if (!IS_ERR(mmc->supply.vqmmc)) {
1992 ret = mmc_regulator_set_vqmmc(mmc, ios);
1993 if (ret) {
1994 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1995 mmc_hostname(mmc));
1996 return -EIO;
1997 }
1998 }
1999 return 0;
2000 default:
2001 /* No signal voltage switch required */
2002 return 0;
2003 }
2004}
2005EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2006
2007static int sdhci_card_busy(struct mmc_host *mmc)
2008{
2009 struct sdhci_host *host = mmc_priv(mmc);
2010 u32 present_state;
2011
2012 /* Check whether DAT[0] is 0 */
2013 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2014
2015 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2016}
2017
2018static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2019{
2020 struct sdhci_host *host = mmc_priv(mmc);
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&host->lock, flags);
2024 host->flags |= SDHCI_HS400_TUNING;
2025 spin_unlock_irqrestore(&host->lock, flags);
2026
2027 return 0;
2028}
2029
2030static void sdhci_start_tuning(struct sdhci_host *host)
2031{
2032 u16 ctrl;
2033
2034 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2036 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2037 ctrl |= SDHCI_CTRL_TUNED_CLK;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039
2040 /*
2041 * As per the Host Controller spec v3.00, tuning command
2042 * generates Buffer Read Ready interrupt, so enable that.
2043 *
2044 * Note: The spec clearly says that when tuning sequence
2045 * is being performed, the controller does not generate
2046 * interrupts other than Buffer Read Ready interrupt. But
2047 * to make sure we don't hit a controller bug, we _only_
2048 * enable Buffer Read Ready interrupt here.
2049 */
2050 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2051 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2052}
2053
2054static void sdhci_end_tuning(struct sdhci_host *host)
2055{
2056 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2057 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2058}
2059
2060static void sdhci_reset_tuning(struct sdhci_host *host)
2061{
2062 u16 ctrl;
2063
2064 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068}
2069
2070static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2071{
2072 sdhci_reset_tuning(host);
2073
2074 sdhci_do_reset(host, SDHCI_RESET_CMD);
2075 sdhci_do_reset(host, SDHCI_RESET_DATA);
2076
2077 sdhci_end_tuning(host);
2078
2079 mmc_abort_tuning(host->mmc, opcode);
2080}
2081
2082/*
2083 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2084 * tuning command does not have a data payload (or rather the hardware does it
2085 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2086 * interrupt setup is different to other commands and there is no timeout
2087 * interrupt so special handling is needed.
2088 */
2089static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2090{
2091 struct mmc_host *mmc = host->mmc;
2092 struct mmc_command cmd = {};
2093 struct mmc_request mrq = {};
2094 unsigned long flags;
2095 u32 b = host->sdma_boundary;
2096
2097 spin_lock_irqsave(&host->lock, flags);
2098
2099 cmd.opcode = opcode;
2100 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2101 cmd.mrq = &mrq;
2102
2103 mrq.cmd = &cmd;
2104 /*
2105 * In response to CMD19, the card sends 64 bytes of tuning
2106 * block to the Host Controller. So we set the block size
2107 * to 64 here.
2108 */
2109 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2110 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2111 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2112 else
2113 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2114
2115 /*
2116 * The tuning block is sent by the card to the host controller.
2117 * So we set the TRNS_READ bit in the Transfer Mode register.
2118 * This also takes care of setting DMA Enable and Multi Block
2119 * Select in the same register to 0.
2120 */
2121 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2122
2123 sdhci_send_command(host, &cmd);
2124
2125 host->cmd = NULL;
2126
2127 sdhci_del_timer(host, &mrq);
2128
2129 host->tuning_done = 0;
2130
2131 mmiowb();
2132 spin_unlock_irqrestore(&host->lock, flags);
2133
2134 /* Wait for Buffer Read Ready interrupt */
2135 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2136 msecs_to_jiffies(50));
2137
2138}
2139
2140static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2141{
2142 int i;
2143
2144 /*
2145 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2146 * of loops reaches 40 times.
2147 */
2148 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2149 u16 ctrl;
2150
2151 sdhci_send_tuning(host, opcode);
2152
2153 if (!host->tuning_done) {
2154 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2155 mmc_hostname(host->mmc));
2156 sdhci_abort_tuning(host, opcode);
2157 return;
2158 }
2159
2160 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2161 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2162 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2163 return; /* Success! */
2164 break;
2165 }
2166
2167 /* Spec does not require a delay between tuning cycles */
2168 if (host->tuning_delay > 0)
2169 mdelay(host->tuning_delay);
2170 }
2171
2172 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2173 mmc_hostname(host->mmc));
2174 sdhci_reset_tuning(host);
2175}
2176
2177int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2178{
2179 struct sdhci_host *host = mmc_priv(mmc);
2180 int err = 0;
2181 unsigned int tuning_count = 0;
2182 bool hs400_tuning;
2183
2184 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2185
2186 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2187 tuning_count = host->tuning_count;
2188
2189 /*
2190 * The Host Controller needs tuning in case of SDR104 and DDR50
2191 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2192 * the Capabilities register.
2193 * If the Host Controller supports the HS200 mode then the
2194 * tuning function has to be executed.
2195 */
2196 switch (host->timing) {
2197 /* HS400 tuning is done in HS200 mode */
2198 case MMC_TIMING_MMC_HS400:
2199 err = -EINVAL;
2200 goto out;
2201
2202 case MMC_TIMING_MMC_HS200:
2203 /*
2204 * Periodic re-tuning for HS400 is not expected to be needed, so
2205 * disable it here.
2206 */
2207 if (hs400_tuning)
2208 tuning_count = 0;
2209 break;
2210
2211 case MMC_TIMING_UHS_SDR104:
2212 case MMC_TIMING_UHS_DDR50:
2213 break;
2214
2215 case MMC_TIMING_UHS_SDR50:
2216 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2217 break;
2218 /* FALLTHROUGH */
2219
2220 default:
2221 goto out;
2222 }
2223
2224 if (host->ops->platform_execute_tuning) {
2225 err = host->ops->platform_execute_tuning(host, opcode);
2226 goto out;
2227 }
2228
2229 host->mmc->retune_period = tuning_count;
2230
2231 if (host->tuning_delay < 0)
2232 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2233
2234 sdhci_start_tuning(host);
2235
2236 __sdhci_execute_tuning(host, opcode);
2237
2238 sdhci_end_tuning(host);
2239out:
2240 host->flags &= ~SDHCI_HS400_TUNING;
2241
2242 return err;
2243}
2244EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2245
2246static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2247{
2248 /* Host Controller v3.00 defines preset value registers */
2249 if (host->version < SDHCI_SPEC_300)
2250 return;
2251
2252 /*
2253 * We only enable or disable Preset Value if they are not already
2254 * enabled or disabled respectively. Otherwise, we bail out.
2255 */
2256 if (host->preset_enabled != enable) {
2257 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2258
2259 if (enable)
2260 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2261 else
2262 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2263
2264 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2265
2266 if (enable)
2267 host->flags |= SDHCI_PV_ENABLED;
2268 else
2269 host->flags &= ~SDHCI_PV_ENABLED;
2270
2271 host->preset_enabled = enable;
2272 }
2273}
2274
2275static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2276 int err)
2277{
2278 struct sdhci_host *host = mmc_priv(mmc);
2279 struct mmc_data *data = mrq->data;
2280
2281 if (data->host_cookie != COOKIE_UNMAPPED)
2282 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2283 mmc_get_dma_dir(data));
2284
2285 data->host_cookie = COOKIE_UNMAPPED;
2286}
2287
2288static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2289{
2290 struct sdhci_host *host = mmc_priv(mmc);
2291
2292 mrq->data->host_cookie = COOKIE_UNMAPPED;
2293
2294 /*
2295 * No pre-mapping in the pre hook if we're using the bounce buffer,
2296 * for that we would need two bounce buffers since one buffer is
2297 * in flight when this is getting called.
2298 */
2299 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2300 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2301}
2302
2303static inline bool sdhci_has_requests(struct sdhci_host *host)
2304{
2305 return host->cmd || host->data_cmd;
2306}
2307
2308static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2309{
2310 if (host->data_cmd) {
2311 host->data_cmd->error = err;
2312 sdhci_finish_mrq(host, host->data_cmd->mrq);
2313 }
2314
2315 if (host->cmd) {
2316 host->cmd->error = err;
2317 sdhci_finish_mrq(host, host->cmd->mrq);
2318 }
2319}
2320
2321static void sdhci_card_event(struct mmc_host *mmc)
2322{
2323 struct sdhci_host *host = mmc_priv(mmc);
2324 unsigned long flags;
2325 int present;
2326
2327 /* First check if client has provided their own card event */
2328 if (host->ops->card_event)
2329 host->ops->card_event(host);
2330
2331 present = mmc->ops->get_cd(mmc);
2332
2333 spin_lock_irqsave(&host->lock, flags);
2334
2335 /* Check sdhci_has_requests() first in case we are runtime suspended */
2336 if (sdhci_has_requests(host) && !present) {
2337 pr_err("%s: Card removed during transfer!\n",
2338 mmc_hostname(host->mmc));
2339 pr_err("%s: Resetting controller.\n",
2340 mmc_hostname(host->mmc));
2341
2342 sdhci_do_reset(host, SDHCI_RESET_CMD);
2343 sdhci_do_reset(host, SDHCI_RESET_DATA);
2344
2345 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2346 }
2347
2348 spin_unlock_irqrestore(&host->lock, flags);
2349}
2350
2351static const struct mmc_host_ops sdhci_ops = {
2352 .request = sdhci_request,
2353 .post_req = sdhci_post_req,
2354 .pre_req = sdhci_pre_req,
2355 .set_ios = sdhci_set_ios,
2356 .get_cd = sdhci_get_cd,
2357 .get_ro = sdhci_get_ro,
2358 .hw_reset = sdhci_hw_reset,
2359 .enable_sdio_irq = sdhci_enable_sdio_irq,
2360 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2361 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2362 .execute_tuning = sdhci_execute_tuning,
2363 .card_event = sdhci_card_event,
2364 .card_busy = sdhci_card_busy,
2365};
2366
2367/*****************************************************************************\
2368 * *
2369 * Tasklets *
2370 * *
2371\*****************************************************************************/
2372
2373static bool sdhci_request_done(struct sdhci_host *host)
2374{
2375 unsigned long flags;
2376 struct mmc_request *mrq;
2377 int i;
2378
2379 spin_lock_irqsave(&host->lock, flags);
2380
2381 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2382 mrq = host->mrqs_done[i];
2383 if (mrq)
2384 break;
2385 }
2386
2387 if (!mrq) {
2388 spin_unlock_irqrestore(&host->lock, flags);
2389 return true;
2390 }
2391
2392 sdhci_del_timer(host, mrq);
2393
2394 /*
2395 * Always unmap the data buffers if they were mapped by
2396 * sdhci_prepare_data() whenever we finish with a request.
2397 * This avoids leaking DMA mappings on error.
2398 */
2399 if (host->flags & SDHCI_REQ_USE_DMA) {
2400 struct mmc_data *data = mrq->data;
2401
2402 if (data && data->host_cookie == COOKIE_MAPPED) {
2403 if (host->bounce_buffer) {
2404 /*
2405 * On reads, copy the bounced data into the
2406 * sglist
2407 */
2408 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2409 unsigned int length = data->bytes_xfered;
2410
2411 if (length > host->bounce_buffer_size) {
2412 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2413 mmc_hostname(host->mmc),
2414 host->bounce_buffer_size,
2415 data->bytes_xfered);
2416 /* Cap it down and continue */
2417 length = host->bounce_buffer_size;
2418 }
2419 dma_sync_single_for_cpu(
2420 host->mmc->parent,
2421 host->bounce_addr,
2422 host->bounce_buffer_size,
2423 DMA_FROM_DEVICE);
2424 sg_copy_from_buffer(data->sg,
2425 data->sg_len,
2426 host->bounce_buffer,
2427 length);
2428 } else {
2429 /* No copying, just switch ownership */
2430 dma_sync_single_for_cpu(
2431 host->mmc->parent,
2432 host->bounce_addr,
2433 host->bounce_buffer_size,
2434 mmc_get_dma_dir(data));
2435 }
2436 } else {
2437 /* Unmap the raw data */
2438 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2439 data->sg_len,
2440 mmc_get_dma_dir(data));
2441 }
2442 data->host_cookie = COOKIE_UNMAPPED;
2443 }
2444 }
2445
2446 /*
2447 * The controller needs a reset of internal state machines
2448 * upon error conditions.
2449 */
2450 if (sdhci_needs_reset(host, mrq)) {
2451 /*
2452 * Do not finish until command and data lines are available for
2453 * reset. Note there can only be one other mrq, so it cannot
2454 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2455 * would both be null.
2456 */
2457 if (host->cmd || host->data_cmd) {
2458 spin_unlock_irqrestore(&host->lock, flags);
2459 return true;
2460 }
2461
2462 /* Some controllers need this kick or reset won't work here */
2463 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2464 /* This is to force an update */
2465 host->ops->set_clock(host, host->clock);
2466
2467 /* Spec says we should do both at the same time, but Ricoh
2468 controllers do not like that. */
2469 sdhci_do_reset(host, SDHCI_RESET_CMD);
2470 sdhci_do_reset(host, SDHCI_RESET_DATA);
2471
2472 host->pending_reset = false;
2473 }
2474
2475 if (!sdhci_has_requests(host))
2476 sdhci_led_deactivate(host);
2477
2478 host->mrqs_done[i] = NULL;
2479
2480 mmiowb();
2481 spin_unlock_irqrestore(&host->lock, flags);
2482
2483 mmc_request_done(host->mmc, mrq);
2484
2485 return false;
2486}
2487
2488static void sdhci_tasklet_finish(unsigned long param)
2489{
2490 struct sdhci_host *host = (struct sdhci_host *)param;
2491
2492 while (!sdhci_request_done(host))
2493 ;
2494}
2495
2496static void sdhci_timeout_timer(struct timer_list *t)
2497{
2498 struct sdhci_host *host;
2499 unsigned long flags;
2500
2501 host = from_timer(host, t, timer);
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2506 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2507 mmc_hostname(host->mmc));
2508 sdhci_dumpregs(host);
2509
2510 host->cmd->error = -ETIMEDOUT;
2511 sdhci_finish_mrq(host, host->cmd->mrq);
2512 }
2513
2514 mmiowb();
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518static void sdhci_timeout_data_timer(struct timer_list *t)
2519{
2520 struct sdhci_host *host;
2521 unsigned long flags;
2522
2523 host = from_timer(host, t, data_timer);
2524
2525 spin_lock_irqsave(&host->lock, flags);
2526
2527 if (host->data || host->data_cmd ||
2528 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2529 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2530 mmc_hostname(host->mmc));
2531 sdhci_dumpregs(host);
2532
2533 if (host->data) {
2534 host->data->error = -ETIMEDOUT;
2535 sdhci_finish_data(host);
2536 } else if (host->data_cmd) {
2537 host->data_cmd->error = -ETIMEDOUT;
2538 sdhci_finish_mrq(host, host->data_cmd->mrq);
2539 } else {
2540 host->cmd->error = -ETIMEDOUT;
2541 sdhci_finish_mrq(host, host->cmd->mrq);
2542 }
2543 }
2544
2545 mmiowb();
2546 spin_unlock_irqrestore(&host->lock, flags);
2547}
2548
2549/*****************************************************************************\
2550 * *
2551 * Interrupt handling *
2552 * *
2553\*****************************************************************************/
2554
2555static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2556{
2557 if (!host->cmd) {
2558 /*
2559 * SDHCI recovers from errors by resetting the cmd and data
2560 * circuits. Until that is done, there very well might be more
2561 * interrupts, so ignore them in that case.
2562 */
2563 if (host->pending_reset)
2564 return;
2565 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2566 mmc_hostname(host->mmc), (unsigned)intmask);
2567 sdhci_dumpregs(host);
2568 return;
2569 }
2570
2571 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2572 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2573 if (intmask & SDHCI_INT_TIMEOUT)
2574 host->cmd->error = -ETIMEDOUT;
2575 else
2576 host->cmd->error = -EILSEQ;
2577
2578 /*
2579 * If this command initiates a data phase and a response
2580 * CRC error is signalled, the card can start transferring
2581 * data - the card may have received the command without
2582 * error. We must not terminate the mmc_request early.
2583 *
2584 * If the card did not receive the command or returned an
2585 * error which prevented it sending data, the data phase
2586 * will time out.
2587 */
2588 if (host->cmd->data &&
2589 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2590 SDHCI_INT_CRC) {
2591 host->cmd = NULL;
2592 return;
2593 }
2594
2595 sdhci_finish_mrq(host, host->cmd->mrq);
2596 return;
2597 }
2598
2599 if (intmask & SDHCI_INT_RESPONSE)
2600 sdhci_finish_command(host);
2601}
2602
2603static void sdhci_adma_show_error(struct sdhci_host *host)
2604{
2605 void *desc = host->adma_table;
2606
2607 sdhci_dumpregs(host);
2608
2609 while (true) {
2610 struct sdhci_adma2_64_desc *dma_desc = desc;
2611
2612 if (host->flags & SDHCI_USE_64_BIT_DMA)
2613 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2614 desc, le32_to_cpu(dma_desc->addr_hi),
2615 le32_to_cpu(dma_desc->addr_lo),
2616 le16_to_cpu(dma_desc->len),
2617 le16_to_cpu(dma_desc->cmd));
2618 else
2619 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2620 desc, le32_to_cpu(dma_desc->addr_lo),
2621 le16_to_cpu(dma_desc->len),
2622 le16_to_cpu(dma_desc->cmd));
2623
2624 desc += host->desc_sz;
2625
2626 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2627 break;
2628 }
2629}
2630
2631static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2632{
2633 u32 command;
2634
2635 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2636 if (intmask & SDHCI_INT_DATA_AVAIL) {
2637 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2638 if (command == MMC_SEND_TUNING_BLOCK ||
2639 command == MMC_SEND_TUNING_BLOCK_HS200) {
2640 host->tuning_done = 1;
2641 wake_up(&host->buf_ready_int);
2642 return;
2643 }
2644 }
2645
2646 if (!host->data) {
2647 struct mmc_command *data_cmd = host->data_cmd;
2648
2649 /*
2650 * The "data complete" interrupt is also used to
2651 * indicate that a busy state has ended. See comment
2652 * above in sdhci_cmd_irq().
2653 */
2654 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2655 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2656 host->data_cmd = NULL;
2657 data_cmd->error = -ETIMEDOUT;
2658 sdhci_finish_mrq(host, data_cmd->mrq);
2659 return;
2660 }
2661 if (intmask & SDHCI_INT_DATA_END) {
2662 host->data_cmd = NULL;
2663 /*
2664 * Some cards handle busy-end interrupt
2665 * before the command completed, so make
2666 * sure we do things in the proper order.
2667 */
2668 if (host->cmd == data_cmd)
2669 return;
2670
2671 sdhci_finish_mrq(host, data_cmd->mrq);
2672 return;
2673 }
2674 }
2675
2676 /*
2677 * SDHCI recovers from errors by resetting the cmd and data
2678 * circuits. Until that is done, there very well might be more
2679 * interrupts, so ignore them in that case.
2680 */
2681 if (host->pending_reset)
2682 return;
2683
2684 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2685 mmc_hostname(host->mmc), (unsigned)intmask);
2686 sdhci_dumpregs(host);
2687
2688 return;
2689 }
2690
2691 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2692 host->data->error = -ETIMEDOUT;
2693 else if (intmask & SDHCI_INT_DATA_END_BIT)
2694 host->data->error = -EILSEQ;
2695 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2696 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2697 != MMC_BUS_TEST_R)
2698 host->data->error = -EILSEQ;
2699 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2700 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2701 sdhci_adma_show_error(host);
2702 host->data->error = -EIO;
2703 if (host->ops->adma_workaround)
2704 host->ops->adma_workaround(host, intmask);
2705 }
2706
2707 if (host->data->error)
2708 sdhci_finish_data(host);
2709 else {
2710 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2711 sdhci_transfer_pio(host);
2712
2713 /*
2714 * We currently don't do anything fancy with DMA
2715 * boundaries, but as we can't disable the feature
2716 * we need to at least restart the transfer.
2717 *
2718 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2719 * should return a valid address to continue from, but as
2720 * some controllers are faulty, don't trust them.
2721 */
2722 if (intmask & SDHCI_INT_DMA_END) {
2723 u32 dmastart, dmanow;
2724
2725 dmastart = sdhci_sdma_address(host);
2726 dmanow = dmastart + host->data->bytes_xfered;
2727 /*
2728 * Force update to the next DMA block boundary.
2729 */
2730 dmanow = (dmanow &
2731 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2732 SDHCI_DEFAULT_BOUNDARY_SIZE;
2733 host->data->bytes_xfered = dmanow - dmastart;
2734 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2735 dmastart, host->data->bytes_xfered, dmanow);
2736 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2737 }
2738
2739 if (intmask & SDHCI_INT_DATA_END) {
2740 if (host->cmd == host->data_cmd) {
2741 /*
2742 * Data managed to finish before the
2743 * command completed. Make sure we do
2744 * things in the proper order.
2745 */
2746 host->data_early = 1;
2747 } else {
2748 sdhci_finish_data(host);
2749 }
2750 }
2751 }
2752}
2753
2754static irqreturn_t sdhci_irq(int irq, void *dev_id)
2755{
2756 irqreturn_t result = IRQ_NONE;
2757 struct sdhci_host *host = dev_id;
2758 u32 intmask, mask, unexpected = 0;
2759 int max_loops = 16;
2760
2761 spin_lock(&host->lock);
2762
2763 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2764 spin_unlock(&host->lock);
2765 return IRQ_NONE;
2766 }
2767
2768 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2769 if (!intmask || intmask == 0xffffffff) {
2770 result = IRQ_NONE;
2771 goto out;
2772 }
2773
2774 do {
2775 DBG("IRQ status 0x%08x\n", intmask);
2776
2777 if (host->ops->irq) {
2778 intmask = host->ops->irq(host, intmask);
2779 if (!intmask)
2780 goto cont;
2781 }
2782
2783 /* Clear selected interrupts. */
2784 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2785 SDHCI_INT_BUS_POWER);
2786 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2787
2788 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2789 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2790 SDHCI_CARD_PRESENT;
2791
2792 /*
2793 * There is a observation on i.mx esdhc. INSERT
2794 * bit will be immediately set again when it gets
2795 * cleared, if a card is inserted. We have to mask
2796 * the irq to prevent interrupt storm which will
2797 * freeze the system. And the REMOVE gets the
2798 * same situation.
2799 *
2800 * More testing are needed here to ensure it works
2801 * for other platforms though.
2802 */
2803 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2804 SDHCI_INT_CARD_REMOVE);
2805 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2806 SDHCI_INT_CARD_INSERT;
2807 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2808 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2809
2810 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2811 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2812
2813 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2814 SDHCI_INT_CARD_REMOVE);
2815 result = IRQ_WAKE_THREAD;
2816 }
2817
2818 if (intmask & SDHCI_INT_CMD_MASK)
2819 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2820
2821 if (intmask & SDHCI_INT_DATA_MASK)
2822 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2823
2824 if (intmask & SDHCI_INT_BUS_POWER)
2825 pr_err("%s: Card is consuming too much power!\n",
2826 mmc_hostname(host->mmc));
2827
2828 if (intmask & SDHCI_INT_RETUNE)
2829 mmc_retune_needed(host->mmc);
2830
2831 if ((intmask & SDHCI_INT_CARD_INT) &&
2832 (host->ier & SDHCI_INT_CARD_INT)) {
2833 sdhci_enable_sdio_irq_nolock(host, false);
2834 host->thread_isr |= SDHCI_INT_CARD_INT;
2835 result = IRQ_WAKE_THREAD;
2836 }
2837
2838 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2839 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2840 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2841 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2842
2843 if (intmask) {
2844 unexpected |= intmask;
2845 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2846 }
2847cont:
2848 if (result == IRQ_NONE)
2849 result = IRQ_HANDLED;
2850
2851 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2852 } while (intmask && --max_loops);
2853out:
2854 spin_unlock(&host->lock);
2855
2856 if (unexpected) {
2857 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2858 mmc_hostname(host->mmc), unexpected);
2859 sdhci_dumpregs(host);
2860 }
2861
2862 return result;
2863}
2864
2865static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2866{
2867 struct sdhci_host *host = dev_id;
2868 unsigned long flags;
2869 u32 isr;
2870
2871 spin_lock_irqsave(&host->lock, flags);
2872 isr = host->thread_isr;
2873 host->thread_isr = 0;
2874 spin_unlock_irqrestore(&host->lock, flags);
2875
2876 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2877 struct mmc_host *mmc = host->mmc;
2878
2879 mmc->ops->card_event(mmc);
2880 mmc_detect_change(mmc, msecs_to_jiffies(200));
2881 }
2882
2883 if (isr & SDHCI_INT_CARD_INT) {
2884 sdio_run_irqs(host->mmc);
2885
2886 spin_lock_irqsave(&host->lock, flags);
2887 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2888 sdhci_enable_sdio_irq_nolock(host, true);
2889 spin_unlock_irqrestore(&host->lock, flags);
2890 }
2891
2892 return isr ? IRQ_HANDLED : IRQ_NONE;
2893}
2894
2895/*****************************************************************************\
2896 * *
2897 * Suspend/resume *
2898 * *
2899\*****************************************************************************/
2900
2901#ifdef CONFIG_PM
2902
2903static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
2904{
2905 return mmc_card_is_removable(host->mmc) &&
2906 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2907 !mmc_can_gpio_cd(host->mmc);
2908}
2909
2910/*
2911 * To enable wakeup events, the corresponding events have to be enabled in
2912 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2913 * Table' in the SD Host Controller Standard Specification.
2914 * It is useless to restore SDHCI_INT_ENABLE state in
2915 * sdhci_disable_irq_wakeups() since it will be set by
2916 * sdhci_enable_card_detection() or sdhci_init().
2917 */
2918static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
2919{
2920 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
2921 SDHCI_WAKE_ON_INT;
2922 u32 irq_val = 0;
2923 u8 wake_val = 0;
2924 u8 val;
2925
2926 if (sdhci_cd_irq_can_wakeup(host)) {
2927 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
2928 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
2929 }
2930
2931 if (mmc_card_wake_sdio_irq(host->mmc)) {
2932 wake_val |= SDHCI_WAKE_ON_INT;
2933 irq_val |= SDHCI_INT_CARD_INT;
2934 }
2935
2936 if (!irq_val)
2937 return false;
2938
2939 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2940 val &= ~mask;
2941 val |= wake_val;
2942 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2943
2944 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2945
2946 host->irq_wake_enabled = !enable_irq_wake(host->irq);
2947
2948 return host->irq_wake_enabled;
2949}
2950
2951static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2952{
2953 u8 val;
2954 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2955 | SDHCI_WAKE_ON_INT;
2956
2957 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2958 val &= ~mask;
2959 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2960
2961 disable_irq_wake(host->irq);
2962
2963 host->irq_wake_enabled = false;
2964}
2965
2966int sdhci_suspend_host(struct sdhci_host *host)
2967{
2968 sdhci_disable_card_detection(host);
2969
2970 mmc_retune_timer_stop(host->mmc);
2971
2972 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
2973 !sdhci_enable_irq_wakeups(host)) {
2974 host->ier = 0;
2975 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2976 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2977 free_irq(host->irq, host);
2978 }
2979
2980 return 0;
2981}
2982
2983EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2984
2985int sdhci_resume_host(struct sdhci_host *host)
2986{
2987 struct mmc_host *mmc = host->mmc;
2988 int ret = 0;
2989
2990 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2991 if (host->ops->enable_dma)
2992 host->ops->enable_dma(host);
2993 }
2994
2995 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2996 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2997 /* Card keeps power but host controller does not */
2998 sdhci_init(host, 0);
2999 host->pwr = 0;
3000 host->clock = 0;
3001 mmc->ops->set_ios(mmc, &mmc->ios);
3002 } else {
3003 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3004 mmiowb();
3005 }
3006
3007 if (host->irq_wake_enabled) {
3008 sdhci_disable_irq_wakeups(host);
3009 } else {
3010 ret = request_threaded_irq(host->irq, sdhci_irq,
3011 sdhci_thread_irq, IRQF_SHARED,
3012 mmc_hostname(host->mmc), host);
3013 if (ret)
3014 return ret;
3015 }
3016
3017 sdhci_enable_card_detection(host);
3018
3019 return ret;
3020}
3021
3022EXPORT_SYMBOL_GPL(sdhci_resume_host);
3023
3024int sdhci_runtime_suspend_host(struct sdhci_host *host)
3025{
3026 unsigned long flags;
3027
3028 mmc_retune_timer_stop(host->mmc);
3029
3030 spin_lock_irqsave(&host->lock, flags);
3031 host->ier &= SDHCI_INT_CARD_INT;
3032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3034 spin_unlock_irqrestore(&host->lock, flags);
3035
3036 synchronize_hardirq(host->irq);
3037
3038 spin_lock_irqsave(&host->lock, flags);
3039 host->runtime_suspended = true;
3040 spin_unlock_irqrestore(&host->lock, flags);
3041
3042 return 0;
3043}
3044EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3045
3046int sdhci_runtime_resume_host(struct sdhci_host *host)
3047{
3048 struct mmc_host *mmc = host->mmc;
3049 unsigned long flags;
3050 int host_flags = host->flags;
3051
3052 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3053 if (host->ops->enable_dma)
3054 host->ops->enable_dma(host);
3055 }
3056
3057 sdhci_init(host, 0);
3058
3059 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3060 mmc->ios.power_mode != MMC_POWER_OFF) {
3061 /* Force clock and power re-program */
3062 host->pwr = 0;
3063 host->clock = 0;
3064 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3065 mmc->ops->set_ios(mmc, &mmc->ios);
3066
3067 if ((host_flags & SDHCI_PV_ENABLED) &&
3068 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3069 spin_lock_irqsave(&host->lock, flags);
3070 sdhci_enable_preset_value(host, true);
3071 spin_unlock_irqrestore(&host->lock, flags);
3072 }
3073
3074 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3075 mmc->ops->hs400_enhanced_strobe)
3076 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3077 }
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 host->runtime_suspended = false;
3082
3083 /* Enable SDIO IRQ */
3084 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3085 sdhci_enable_sdio_irq_nolock(host, true);
3086
3087 /* Enable Card Detection */
3088 sdhci_enable_card_detection(host);
3089
3090 spin_unlock_irqrestore(&host->lock, flags);
3091
3092 return 0;
3093}
3094EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3095
3096#endif /* CONFIG_PM */
3097
3098/*****************************************************************************\
3099 * *
3100 * Command Queue Engine (CQE) helpers *
3101 * *
3102\*****************************************************************************/
3103
3104void sdhci_cqe_enable(struct mmc_host *mmc)
3105{
3106 struct sdhci_host *host = mmc_priv(mmc);
3107 unsigned long flags;
3108 u8 ctrl;
3109
3110 spin_lock_irqsave(&host->lock, flags);
3111
3112 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3113 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3114 if (host->flags & SDHCI_USE_64_BIT_DMA)
3115 ctrl |= SDHCI_CTRL_ADMA64;
3116 else
3117 ctrl |= SDHCI_CTRL_ADMA32;
3118 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3119
3120 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3121 SDHCI_BLOCK_SIZE);
3122
3123 /* Set maximum timeout */
3124 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3125
3126 host->ier = host->cqe_ier;
3127
3128 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3129 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3130
3131 host->cqe_on = true;
3132
3133 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3134 mmc_hostname(mmc), host->ier,
3135 sdhci_readl(host, SDHCI_INT_STATUS));
3136
3137 mmiowb();
3138 spin_unlock_irqrestore(&host->lock, flags);
3139}
3140EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3141
3142void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3143{
3144 struct sdhci_host *host = mmc_priv(mmc);
3145 unsigned long flags;
3146
3147 spin_lock_irqsave(&host->lock, flags);
3148
3149 sdhci_set_default_irqs(host);
3150
3151 host->cqe_on = false;
3152
3153 if (recovery) {
3154 sdhci_do_reset(host, SDHCI_RESET_CMD);
3155 sdhci_do_reset(host, SDHCI_RESET_DATA);
3156 }
3157
3158 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3159 mmc_hostname(mmc), host->ier,
3160 sdhci_readl(host, SDHCI_INT_STATUS));
3161
3162 mmiowb();
3163 spin_unlock_irqrestore(&host->lock, flags);
3164}
3165EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3166
3167bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3168 int *data_error)
3169{
3170 u32 mask;
3171
3172 if (!host->cqe_on)
3173 return false;
3174
3175 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3176 *cmd_error = -EILSEQ;
3177 else if (intmask & SDHCI_INT_TIMEOUT)
3178 *cmd_error = -ETIMEDOUT;
3179 else
3180 *cmd_error = 0;
3181
3182 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3183 *data_error = -EILSEQ;
3184 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3185 *data_error = -ETIMEDOUT;
3186 else if (intmask & SDHCI_INT_ADMA_ERROR)
3187 *data_error = -EIO;
3188 else
3189 *data_error = 0;
3190
3191 /* Clear selected interrupts. */
3192 mask = intmask & host->cqe_ier;
3193 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3194
3195 if (intmask & SDHCI_INT_BUS_POWER)
3196 pr_err("%s: Card is consuming too much power!\n",
3197 mmc_hostname(host->mmc));
3198
3199 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3200 if (intmask) {
3201 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3202 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3203 mmc_hostname(host->mmc), intmask);
3204 sdhci_dumpregs(host);
3205 }
3206
3207 return true;
3208}
3209EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3210
3211/*****************************************************************************\
3212 * *
3213 * Device allocation/registration *
3214 * *
3215\*****************************************************************************/
3216
3217struct sdhci_host *sdhci_alloc_host(struct device *dev,
3218 size_t priv_size)
3219{
3220 struct mmc_host *mmc;
3221 struct sdhci_host *host;
3222
3223 WARN_ON(dev == NULL);
3224
3225 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3226 if (!mmc)
3227 return ERR_PTR(-ENOMEM);
3228
3229 host = mmc_priv(mmc);
3230 host->mmc = mmc;
3231 host->mmc_host_ops = sdhci_ops;
3232 mmc->ops = &host->mmc_host_ops;
3233
3234 host->flags = SDHCI_SIGNALING_330;
3235
3236 host->cqe_ier = SDHCI_CQE_INT_MASK;
3237 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3238
3239 host->tuning_delay = -1;
3240
3241 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3242
3243 return host;
3244}
3245
3246EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3247
3248static int sdhci_set_dma_mask(struct sdhci_host *host)
3249{
3250 struct mmc_host *mmc = host->mmc;
3251 struct device *dev = mmc_dev(mmc);
3252 int ret = -EINVAL;
3253
3254 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3255 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3256
3257 /* Try 64-bit mask if hardware is capable of it */
3258 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3259 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3260 if (ret) {
3261 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3262 mmc_hostname(mmc));
3263 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3264 }
3265 }
3266
3267 /* 32-bit mask as default & fallback */
3268 if (ret) {
3269 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3270 if (ret)
3271 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3272 mmc_hostname(mmc));
3273 }
3274
3275 return ret;
3276}
3277
3278void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3279{
3280 u16 v;
3281 u64 dt_caps_mask = 0;
3282 u64 dt_caps = 0;
3283
3284 if (host->read_caps)
3285 return;
3286
3287 host->read_caps = true;
3288
3289 if (debug_quirks)
3290 host->quirks = debug_quirks;
3291
3292 if (debug_quirks2)
3293 host->quirks2 = debug_quirks2;
3294
3295 sdhci_do_reset(host, SDHCI_RESET_ALL);
3296
3297 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3298 "sdhci-caps-mask", &dt_caps_mask);
3299 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3300 "sdhci-caps", &dt_caps);
3301
3302 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3303 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3304
3305 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3306 return;
3307
3308 if (caps) {
3309 host->caps = *caps;
3310 } else {
3311 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3312 host->caps &= ~lower_32_bits(dt_caps_mask);
3313 host->caps |= lower_32_bits(dt_caps);
3314 }
3315
3316 if (host->version < SDHCI_SPEC_300)
3317 return;
3318
3319 if (caps1) {
3320 host->caps1 = *caps1;
3321 } else {
3322 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3323 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3324 host->caps1 |= upper_32_bits(dt_caps);
3325 }
3326}
3327EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3328
3329static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3330{
3331 struct mmc_host *mmc = host->mmc;
3332 unsigned int max_blocks;
3333 unsigned int bounce_size;
3334 int ret;
3335
3336 /*
3337 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3338 * has diminishing returns, this is probably because SD/MMC
3339 * cards are usually optimized to handle this size of requests.
3340 */
3341 bounce_size = SZ_64K;
3342 /*
3343 * Adjust downwards to maximum request size if this is less
3344 * than our segment size, else hammer down the maximum
3345 * request size to the maximum buffer size.
3346 */
3347 if (mmc->max_req_size < bounce_size)
3348 bounce_size = mmc->max_req_size;
3349 max_blocks = bounce_size / 512;
3350
3351 /*
3352 * When we just support one segment, we can get significant
3353 * speedups by the help of a bounce buffer to group scattered
3354 * reads/writes together.
3355 */
3356 host->bounce_buffer = devm_kmalloc(mmc->parent,
3357 bounce_size,
3358 GFP_KERNEL);
3359 if (!host->bounce_buffer) {
3360 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3361 mmc_hostname(mmc),
3362 bounce_size);
3363 /*
3364 * Exiting with zero here makes sure we proceed with
3365 * mmc->max_segs == 1.
3366 */
3367 return 0;
3368 }
3369
3370 host->bounce_addr = dma_map_single(mmc->parent,
3371 host->bounce_buffer,
3372 bounce_size,
3373 DMA_BIDIRECTIONAL);
3374 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3375 if (ret)
3376 /* Again fall back to max_segs == 1 */
3377 return 0;
3378 host->bounce_buffer_size = bounce_size;
3379
3380 /* Lie about this since we're bouncing */
3381 mmc->max_segs = max_blocks;
3382 mmc->max_seg_size = bounce_size;
3383 mmc->max_req_size = bounce_size;
3384
3385 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3386 mmc_hostname(mmc), max_blocks, bounce_size);
3387
3388 return 0;
3389}
3390
3391int sdhci_setup_host(struct sdhci_host *host)
3392{
3393 struct mmc_host *mmc;
3394 u32 max_current_caps;
3395 unsigned int ocr_avail;
3396 unsigned int override_timeout_clk;
3397 u32 max_clk;
3398 int ret;
3399
3400 WARN_ON(host == NULL);
3401 if (host == NULL)
3402 return -EINVAL;
3403
3404 mmc = host->mmc;
3405
3406 /*
3407 * If there are external regulators, get them. Note this must be done
3408 * early before resetting the host and reading the capabilities so that
3409 * the host can take the appropriate action if regulators are not
3410 * available.
3411 */
3412 ret = mmc_regulator_get_supply(mmc);
3413 if (ret)
3414 return ret;
3415
3416 DBG("Version: 0x%08x | Present: 0x%08x\n",
3417 sdhci_readw(host, SDHCI_HOST_VERSION),
3418 sdhci_readl(host, SDHCI_PRESENT_STATE));
3419 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3420 sdhci_readl(host, SDHCI_CAPABILITIES),
3421 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3422
3423 sdhci_read_caps(host);
3424
3425 override_timeout_clk = host->timeout_clk;
3426
3427 if (host->version > SDHCI_SPEC_300) {
3428 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3429 mmc_hostname(mmc), host->version);
3430 }
3431
3432 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3433 host->flags |= SDHCI_USE_SDMA;
3434 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3435 DBG("Controller doesn't have SDMA capability\n");
3436 else
3437 host->flags |= SDHCI_USE_SDMA;
3438
3439 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3440 (host->flags & SDHCI_USE_SDMA)) {
3441 DBG("Disabling DMA as it is marked broken\n");
3442 host->flags &= ~SDHCI_USE_SDMA;
3443 }
3444
3445 if ((host->version >= SDHCI_SPEC_200) &&
3446 (host->caps & SDHCI_CAN_DO_ADMA2))
3447 host->flags |= SDHCI_USE_ADMA;
3448
3449 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3450 (host->flags & SDHCI_USE_ADMA)) {
3451 DBG("Disabling ADMA as it is marked broken\n");
3452 host->flags &= ~SDHCI_USE_ADMA;
3453 }
3454
3455 /*
3456 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3457 * and *must* do 64-bit DMA. A driver has the opportunity to change
3458 * that during the first call to ->enable_dma(). Similarly
3459 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3460 * implement.
3461 */
3462 if (host->caps & SDHCI_CAN_64BIT)
3463 host->flags |= SDHCI_USE_64_BIT_DMA;
3464
3465 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3466 ret = sdhci_set_dma_mask(host);
3467
3468 if (!ret && host->ops->enable_dma)
3469 ret = host->ops->enable_dma(host);
3470
3471 if (ret) {
3472 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3473 mmc_hostname(mmc));
3474 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3475
3476 ret = 0;
3477 }
3478 }
3479
3480 /* SDMA does not support 64-bit DMA */
3481 if (host->flags & SDHCI_USE_64_BIT_DMA)
3482 host->flags &= ~SDHCI_USE_SDMA;
3483
3484 if (host->flags & SDHCI_USE_ADMA) {
3485 dma_addr_t dma;
3486 void *buf;
3487
3488 /*
3489 * The DMA descriptor table size is calculated as the maximum
3490 * number of segments times 2, to allow for an alignment
3491 * descriptor for each segment, plus 1 for a nop end descriptor,
3492 * all multipled by the descriptor size.
3493 */
3494 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3495 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3496 SDHCI_ADMA2_64_DESC_SZ;
3497 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3498 } else {
3499 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3500 SDHCI_ADMA2_32_DESC_SZ;
3501 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3502 }
3503
3504 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3505 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3506 host->adma_table_sz, &dma, GFP_KERNEL);
3507 if (!buf) {
3508 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3509 mmc_hostname(mmc));
3510 host->flags &= ~SDHCI_USE_ADMA;
3511 } else if ((dma + host->align_buffer_sz) &
3512 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3513 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3514 mmc_hostname(mmc));
3515 host->flags &= ~SDHCI_USE_ADMA;
3516 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3517 host->adma_table_sz, buf, dma);
3518 } else {
3519 host->align_buffer = buf;
3520 host->align_addr = dma;
3521
3522 host->adma_table = buf + host->align_buffer_sz;
3523 host->adma_addr = dma + host->align_buffer_sz;
3524 }
3525 }
3526
3527 /*
3528 * If we use DMA, then it's up to the caller to set the DMA
3529 * mask, but PIO does not need the hw shim so we set a new
3530 * mask here in that case.
3531 */
3532 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3533 host->dma_mask = DMA_BIT_MASK(64);
3534 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3535 }
3536
3537 if (host->version >= SDHCI_SPEC_300)
3538 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3539 >> SDHCI_CLOCK_BASE_SHIFT;
3540 else
3541 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3542 >> SDHCI_CLOCK_BASE_SHIFT;
3543
3544 host->max_clk *= 1000000;
3545 if (host->max_clk == 0 || host->quirks &
3546 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3547 if (!host->ops->get_max_clock) {
3548 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3549 mmc_hostname(mmc));
3550 ret = -ENODEV;
3551 goto undma;
3552 }
3553 host->max_clk = host->ops->get_max_clock(host);
3554 }
3555
3556 /*
3557 * In case of Host Controller v3.00, find out whether clock
3558 * multiplier is supported.
3559 */
3560 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3561 SDHCI_CLOCK_MUL_SHIFT;
3562
3563 /*
3564 * In case the value in Clock Multiplier is 0, then programmable
3565 * clock mode is not supported, otherwise the actual clock
3566 * multiplier is one more than the value of Clock Multiplier
3567 * in the Capabilities Register.
3568 */
3569 if (host->clk_mul)
3570 host->clk_mul += 1;
3571
3572 /*
3573 * Set host parameters.
3574 */
3575 max_clk = host->max_clk;
3576
3577 if (host->ops->get_min_clock)
3578 mmc->f_min = host->ops->get_min_clock(host);
3579 else if (host->version >= SDHCI_SPEC_300) {
3580 if (host->clk_mul) {
3581 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3582 max_clk = host->max_clk * host->clk_mul;
3583 } else
3584 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3585 } else
3586 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3587
3588 if (!mmc->f_max || mmc->f_max > max_clk)
3589 mmc->f_max = max_clk;
3590
3591 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3592 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3593 SDHCI_TIMEOUT_CLK_SHIFT;
3594
3595 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3596 host->timeout_clk *= 1000;
3597
3598 if (host->timeout_clk == 0) {
3599 if (!host->ops->get_timeout_clock) {
3600 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3601 mmc_hostname(mmc));
3602 ret = -ENODEV;
3603 goto undma;
3604 }
3605
3606 host->timeout_clk =
3607 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3608 1000);
3609 }
3610
3611 if (override_timeout_clk)
3612 host->timeout_clk = override_timeout_clk;
3613
3614 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3615 host->ops->get_max_timeout_count(host) : 1 << 27;
3616 mmc->max_busy_timeout /= host->timeout_clk;
3617 }
3618
3619 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3620 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3621
3622 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3623 host->flags |= SDHCI_AUTO_CMD12;
3624
3625 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3626 if ((host->version >= SDHCI_SPEC_300) &&
3627 ((host->flags & SDHCI_USE_ADMA) ||
3628 !(host->flags & SDHCI_USE_SDMA)) &&
3629 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3630 host->flags |= SDHCI_AUTO_CMD23;
3631 DBG("Auto-CMD23 available\n");
3632 } else {
3633 DBG("Auto-CMD23 unavailable\n");
3634 }
3635
3636 /*
3637 * A controller may support 8-bit width, but the board itself
3638 * might not have the pins brought out. Boards that support
3639 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3640 * their platform code before calling sdhci_add_host(), and we
3641 * won't assume 8-bit width for hosts without that CAP.
3642 */
3643 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3644 mmc->caps |= MMC_CAP_4_BIT_DATA;
3645
3646 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3647 mmc->caps &= ~MMC_CAP_CMD23;
3648
3649 if (host->caps & SDHCI_CAN_DO_HISPD)
3650 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3651
3652 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3653 mmc_card_is_removable(mmc) &&
3654 mmc_gpio_get_cd(host->mmc) < 0)
3655 mmc->caps |= MMC_CAP_NEEDS_POLL;
3656
3657 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3658 if (!IS_ERR(mmc->supply.vqmmc)) {
3659 ret = regulator_enable(mmc->supply.vqmmc);
3660 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3661 1950000))
3662 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3663 SDHCI_SUPPORT_SDR50 |
3664 SDHCI_SUPPORT_DDR50);
3665 if (ret) {
3666 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3667 mmc_hostname(mmc), ret);
3668 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3669 }
3670 }
3671
3672 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3673 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3674 SDHCI_SUPPORT_DDR50);
3675 }
3676
3677 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3678 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3679 SDHCI_SUPPORT_DDR50))
3680 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3681
3682 /* SDR104 supports also implies SDR50 support */
3683 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3684 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3685 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3686 * field can be promoted to support HS200.
3687 */
3688 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3689 mmc->caps2 |= MMC_CAP2_HS200;
3690 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3691 mmc->caps |= MMC_CAP_UHS_SDR50;
3692 }
3693
3694 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3695 (host->caps1 & SDHCI_SUPPORT_HS400))
3696 mmc->caps2 |= MMC_CAP2_HS400;
3697
3698 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3699 (IS_ERR(mmc->supply.vqmmc) ||
3700 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3701 1300000)))
3702 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3703
3704 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3705 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3706 mmc->caps |= MMC_CAP_UHS_DDR50;
3707
3708 /* Does the host need tuning for SDR50? */
3709 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3710 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3711
3712 /* Driver Type(s) (A, C, D) supported by the host */
3713 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3714 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3715 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3716 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3717 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3718 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3719
3720 /* Initial value for re-tuning timer count */
3721 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3722 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3723
3724 /*
3725 * In case Re-tuning Timer is not disabled, the actual value of
3726 * re-tuning timer will be 2 ^ (n - 1).
3727 */
3728 if (host->tuning_count)
3729 host->tuning_count = 1 << (host->tuning_count - 1);
3730
3731 /* Re-tuning mode supported by the Host Controller */
3732 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3733 SDHCI_RETUNING_MODE_SHIFT;
3734
3735 ocr_avail = 0;
3736
3737 /*
3738 * According to SD Host Controller spec v3.00, if the Host System
3739 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3740 * the value is meaningful only if Voltage Support in the Capabilities
3741 * register is set. The actual current value is 4 times the register
3742 * value.
3743 */
3744 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3745 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3746 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3747 if (curr > 0) {
3748
3749 /* convert to SDHCI_MAX_CURRENT format */
3750 curr = curr/1000; /* convert to mA */
3751 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3752
3753 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3754 max_current_caps =
3755 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3756 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3757 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3758 }
3759 }
3760
3761 if (host->caps & SDHCI_CAN_VDD_330) {
3762 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3763
3764 mmc->max_current_330 = ((max_current_caps &
3765 SDHCI_MAX_CURRENT_330_MASK) >>
3766 SDHCI_MAX_CURRENT_330_SHIFT) *
3767 SDHCI_MAX_CURRENT_MULTIPLIER;
3768 }
3769 if (host->caps & SDHCI_CAN_VDD_300) {
3770 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3771
3772 mmc->max_current_300 = ((max_current_caps &
3773 SDHCI_MAX_CURRENT_300_MASK) >>
3774 SDHCI_MAX_CURRENT_300_SHIFT) *
3775 SDHCI_MAX_CURRENT_MULTIPLIER;
3776 }
3777 if (host->caps & SDHCI_CAN_VDD_180) {
3778 ocr_avail |= MMC_VDD_165_195;
3779
3780 mmc->max_current_180 = ((max_current_caps &
3781 SDHCI_MAX_CURRENT_180_MASK) >>
3782 SDHCI_MAX_CURRENT_180_SHIFT) *
3783 SDHCI_MAX_CURRENT_MULTIPLIER;
3784 }
3785
3786 /* If OCR set by host, use it instead. */
3787 if (host->ocr_mask)
3788 ocr_avail = host->ocr_mask;
3789
3790 /* If OCR set by external regulators, give it highest prio. */
3791 if (mmc->ocr_avail)
3792 ocr_avail = mmc->ocr_avail;
3793
3794 mmc->ocr_avail = ocr_avail;
3795 mmc->ocr_avail_sdio = ocr_avail;
3796 if (host->ocr_avail_sdio)
3797 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3798 mmc->ocr_avail_sd = ocr_avail;
3799 if (host->ocr_avail_sd)
3800 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3801 else /* normal SD controllers don't support 1.8V */
3802 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3803 mmc->ocr_avail_mmc = ocr_avail;
3804 if (host->ocr_avail_mmc)
3805 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3806
3807 if (mmc->ocr_avail == 0) {
3808 pr_err("%s: Hardware doesn't report any support voltages.\n",
3809 mmc_hostname(mmc));
3810 ret = -ENODEV;
3811 goto unreg;
3812 }
3813
3814 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3815 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3816 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3817 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3818 host->flags |= SDHCI_SIGNALING_180;
3819
3820 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3821 host->flags |= SDHCI_SIGNALING_120;
3822
3823 spin_lock_init(&host->lock);
3824
3825 /*
3826 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3827 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3828 * is less anyway.
3829 */
3830 mmc->max_req_size = 524288;
3831
3832 /*
3833 * Maximum number of segments. Depends on if the hardware
3834 * can do scatter/gather or not.
3835 */
3836 if (host->flags & SDHCI_USE_ADMA) {
3837 mmc->max_segs = SDHCI_MAX_SEGS;
3838 } else if (host->flags & SDHCI_USE_SDMA) {
3839 mmc->max_segs = 1;
3840 if (swiotlb_max_segment()) {
3841 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3842 IO_TLB_SEGSIZE;
3843 mmc->max_req_size = min(mmc->max_req_size,
3844 max_req_size);
3845 }
3846 } else { /* PIO */
3847 mmc->max_segs = SDHCI_MAX_SEGS;
3848 }
3849
3850 /*
3851 * Maximum segment size. Could be one segment with the maximum number
3852 * of bytes. When doing hardware scatter/gather, each entry cannot
3853 * be larger than 64 KiB though.
3854 */
3855 if (host->flags & SDHCI_USE_ADMA) {
3856 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3857 mmc->max_seg_size = 65535;
3858 else
3859 mmc->max_seg_size = 65536;
3860 } else {
3861 mmc->max_seg_size = mmc->max_req_size;
3862 }
3863
3864 /*
3865 * Maximum block size. This varies from controller to controller and
3866 * is specified in the capabilities register.
3867 */
3868 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3869 mmc->max_blk_size = 2;
3870 } else {
3871 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3872 SDHCI_MAX_BLOCK_SHIFT;
3873 if (mmc->max_blk_size >= 3) {
3874 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3875 mmc_hostname(mmc));
3876 mmc->max_blk_size = 0;
3877 }
3878 }
3879
3880 mmc->max_blk_size = 512 << mmc->max_blk_size;
3881
3882 /*
3883 * Maximum block count.
3884 */
3885 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3886
3887 if (mmc->max_segs == 1) {
3888 /* This may alter mmc->*_blk_* parameters */
3889 ret = sdhci_allocate_bounce_buffer(host);
3890 if (ret)
3891 return ret;
3892 }
3893
3894 return 0;
3895
3896unreg:
3897 if (!IS_ERR(mmc->supply.vqmmc))
3898 regulator_disable(mmc->supply.vqmmc);
3899undma:
3900 if (host->align_buffer)
3901 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3902 host->adma_table_sz, host->align_buffer,
3903 host->align_addr);
3904 host->adma_table = NULL;
3905 host->align_buffer = NULL;
3906
3907 return ret;
3908}
3909EXPORT_SYMBOL_GPL(sdhci_setup_host);
3910
3911void sdhci_cleanup_host(struct sdhci_host *host)
3912{
3913 struct mmc_host *mmc = host->mmc;
3914
3915 if (!IS_ERR(mmc->supply.vqmmc))
3916 regulator_disable(mmc->supply.vqmmc);
3917
3918 if (host->align_buffer)
3919 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3920 host->adma_table_sz, host->align_buffer,
3921 host->align_addr);
3922 host->adma_table = NULL;
3923 host->align_buffer = NULL;
3924}
3925EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3926
3927int __sdhci_add_host(struct sdhci_host *host)
3928{
3929 struct mmc_host *mmc = host->mmc;
3930 int ret;
3931
3932 /*
3933 * Init tasklets.
3934 */
3935 tasklet_init(&host->finish_tasklet,
3936 sdhci_tasklet_finish, (unsigned long)host);
3937
3938 timer_setup(&host->timer, sdhci_timeout_timer, 0);
3939 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
3940
3941 init_waitqueue_head(&host->buf_ready_int);
3942
3943 sdhci_init(host, 0);
3944
3945 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3946 IRQF_SHARED, mmc_hostname(mmc), host);
3947 if (ret) {
3948 pr_err("%s: Failed to request IRQ %d: %d\n",
3949 mmc_hostname(mmc), host->irq, ret);
3950 goto untasklet;
3951 }
3952
3953 ret = sdhci_led_register(host);
3954 if (ret) {
3955 pr_err("%s: Failed to register LED device: %d\n",
3956 mmc_hostname(mmc), ret);
3957 goto unirq;
3958 }
3959
3960 mmiowb();
3961
3962 ret = mmc_add_host(mmc);
3963 if (ret)
3964 goto unled;
3965
3966 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3967 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3968 (host->flags & SDHCI_USE_ADMA) ?
3969 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3970 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3971
3972 sdhci_enable_card_detection(host);
3973
3974 return 0;
3975
3976unled:
3977 sdhci_led_unregister(host);
3978unirq:
3979 sdhci_do_reset(host, SDHCI_RESET_ALL);
3980 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3981 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3982 free_irq(host->irq, host);
3983untasklet:
3984 tasklet_kill(&host->finish_tasklet);
3985
3986 return ret;
3987}
3988EXPORT_SYMBOL_GPL(__sdhci_add_host);
3989
3990int sdhci_add_host(struct sdhci_host *host)
3991{
3992 int ret;
3993
3994 ret = sdhci_setup_host(host);
3995 if (ret)
3996 return ret;
3997
3998 ret = __sdhci_add_host(host);
3999 if (ret)
4000 goto cleanup;
4001
4002 return 0;
4003
4004cleanup:
4005 sdhci_cleanup_host(host);
4006
4007 return ret;
4008}
4009EXPORT_SYMBOL_GPL(sdhci_add_host);
4010
4011void sdhci_remove_host(struct sdhci_host *host, int dead)
4012{
4013 struct mmc_host *mmc = host->mmc;
4014 unsigned long flags;
4015
4016 if (dead) {
4017 spin_lock_irqsave(&host->lock, flags);
4018
4019 host->flags |= SDHCI_DEVICE_DEAD;
4020
4021 if (sdhci_has_requests(host)) {
4022 pr_err("%s: Controller removed during "
4023 " transfer!\n", mmc_hostname(mmc));
4024 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4025 }
4026
4027 spin_unlock_irqrestore(&host->lock, flags);
4028 }
4029
4030 sdhci_disable_card_detection(host);
4031
4032 mmc_remove_host(mmc);
4033
4034 sdhci_led_unregister(host);
4035
4036 if (!dead)
4037 sdhci_do_reset(host, SDHCI_RESET_ALL);
4038
4039 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4040 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4041 free_irq(host->irq, host);
4042
4043 del_timer_sync(&host->timer);
4044 del_timer_sync(&host->data_timer);
4045
4046 tasklet_kill(&host->finish_tasklet);
4047
4048 if (!IS_ERR(mmc->supply.vqmmc))
4049 regulator_disable(mmc->supply.vqmmc);
4050
4051 if (host->align_buffer)
4052 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4053 host->adma_table_sz, host->align_buffer,
4054 host->align_addr);
4055
4056 host->adma_table = NULL;
4057 host->align_buffer = NULL;
4058}
4059
4060EXPORT_SYMBOL_GPL(sdhci_remove_host);
4061
4062void sdhci_free_host(struct sdhci_host *host)
4063{
4064 mmc_free_host(host->mmc);
4065}
4066
4067EXPORT_SYMBOL_GPL(sdhci_free_host);
4068
4069/*****************************************************************************\
4070 * *
4071 * Driver init/exit *
4072 * *
4073\*****************************************************************************/
4074
4075static int __init sdhci_drv_init(void)
4076{
4077 pr_info(DRIVER_NAME
4078 ": Secure Digital Host Controller Interface driver\n");
4079 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4080
4081 return 0;
4082}
4083
4084static void __exit sdhci_drv_exit(void)
4085{
4086}
4087
4088module_init(sdhci_drv_init);
4089module_exit(sdhci_drv_exit);
4090
4091module_param(debug_quirks, uint, 0444);
4092module_param(debug_quirks2, uint, 0444);
4093
4094MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4095MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4096MODULE_LICENSE("GPL");
4097
4098MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4099MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/delay.h>
13#include <linux/ktime.h>
14#include <linux/highmem.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/dma-mapping.h>
18#include <linux/slab.h>
19#include <linux/scatterlist.h>
20#include <linux/sizes.h>
21#include <linux/swiotlb.h>
22#include <linux/regulator/consumer.h>
23#include <linux/pm_runtime.h>
24#include <linux/of.h>
25
26#include <linux/leds.h>
27
28#include <linux/mmc/mmc.h>
29#include <linux/mmc/host.h>
30#include <linux/mmc/card.h>
31#include <linux/mmc/sdio.h>
32#include <linux/mmc/slot-gpio.h>
33
34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
37
38#define DBG(f, x...) \
39 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
40
41#define SDHCI_DUMP(f, x...) \
42 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
43
44#define MAX_TUNING_LOOP 40
45
46static unsigned int debug_quirks = 0;
47static unsigned int debug_quirks2;
48
49static void sdhci_finish_data(struct sdhci_host *);
50
51static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
52
53void sdhci_dumpregs(struct sdhci_host *host)
54{
55 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
56
57 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
60 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
63 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
66 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
69 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
72 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
75 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
78 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
81 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
82 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
84 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
85 sdhci_readl(host, SDHCI_CAPABILITIES),
86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
89 sdhci_readl(host, SDHCI_MAX_CURRENT));
90 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
91 sdhci_readl(host, SDHCI_RESPONSE),
92 sdhci_readl(host, SDHCI_RESPONSE + 4));
93 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
94 sdhci_readl(host, SDHCI_RESPONSE + 8),
95 sdhci_readl(host, SDHCI_RESPONSE + 12));
96 SDHCI_DUMP("Host ctl2: 0x%08x\n",
97 sdhci_readw(host, SDHCI_HOST_CONTROL2));
98
99 if (host->flags & SDHCI_USE_ADMA) {
100 if (host->flags & SDHCI_USE_64_BIT_DMA) {
101 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
102 sdhci_readl(host, SDHCI_ADMA_ERROR),
103 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
105 } else {
106 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
107 sdhci_readl(host, SDHCI_ADMA_ERROR),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 }
110 }
111
112 SDHCI_DUMP("============================================\n");
113}
114EXPORT_SYMBOL_GPL(sdhci_dumpregs);
115
116/*****************************************************************************\
117 * *
118 * Low level functions *
119 * *
120\*****************************************************************************/
121
122static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
123{
124 u16 ctrl2;
125
126 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
127 if (ctrl2 & SDHCI_CTRL_V4_MODE)
128 return;
129
130 ctrl2 |= SDHCI_CTRL_V4_MODE;
131 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
132}
133
134/*
135 * This can be called before sdhci_add_host() by Vendor's host controller
136 * driver to enable v4 mode if supported.
137 */
138void sdhci_enable_v4_mode(struct sdhci_host *host)
139{
140 host->v4_mode = true;
141 sdhci_do_enable_v4_mode(host);
142}
143EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
144
145static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
146{
147 return cmd->data || cmd->flags & MMC_RSP_BUSY;
148}
149
150static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
151{
152 u32 present;
153
154 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
155 !mmc_card_is_removable(host->mmc))
156 return;
157
158 if (enable) {
159 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
160 SDHCI_CARD_PRESENT;
161
162 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
163 SDHCI_INT_CARD_INSERT;
164 } else {
165 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
166 }
167
168 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
169 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
170}
171
172static void sdhci_enable_card_detection(struct sdhci_host *host)
173{
174 sdhci_set_card_detection(host, true);
175}
176
177static void sdhci_disable_card_detection(struct sdhci_host *host)
178{
179 sdhci_set_card_detection(host, false);
180}
181
182static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
183{
184 if (host->bus_on)
185 return;
186 host->bus_on = true;
187 pm_runtime_get_noresume(host->mmc->parent);
188}
189
190static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
191{
192 if (!host->bus_on)
193 return;
194 host->bus_on = false;
195 pm_runtime_put_noidle(host->mmc->parent);
196}
197
198void sdhci_reset(struct sdhci_host *host, u8 mask)
199{
200 ktime_t timeout;
201
202 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
203
204 if (mask & SDHCI_RESET_ALL) {
205 host->clock = 0;
206 /* Reset-all turns off SD Bus Power */
207 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
208 sdhci_runtime_pm_bus_off(host);
209 }
210
211 /* Wait max 100 ms */
212 timeout = ktime_add_ms(ktime_get(), 100);
213
214 /* hw clears the bit when it's done */
215 while (1) {
216 bool timedout = ktime_after(ktime_get(), timeout);
217
218 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
219 break;
220 if (timedout) {
221 pr_err("%s: Reset 0x%x never completed.\n",
222 mmc_hostname(host->mmc), (int)mask);
223 sdhci_dumpregs(host);
224 return;
225 }
226 udelay(10);
227 }
228}
229EXPORT_SYMBOL_GPL(sdhci_reset);
230
231static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
232{
233 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
234 struct mmc_host *mmc = host->mmc;
235
236 if (!mmc->ops->get_cd(mmc))
237 return;
238 }
239
240 host->ops->reset(host, mask);
241
242 if (mask & SDHCI_RESET_ALL) {
243 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
244 if (host->ops->enable_dma)
245 host->ops->enable_dma(host);
246 }
247
248 /* Resetting the controller clears many */
249 host->preset_enabled = false;
250 }
251}
252
253static void sdhci_set_default_irqs(struct sdhci_host *host)
254{
255 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
256 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
257 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
258 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
259 SDHCI_INT_RESPONSE;
260
261 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
262 host->tuning_mode == SDHCI_TUNING_MODE_3)
263 host->ier |= SDHCI_INT_RETUNE;
264
265 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
266 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
267}
268
269static void sdhci_config_dma(struct sdhci_host *host)
270{
271 u8 ctrl;
272 u16 ctrl2;
273
274 if (host->version < SDHCI_SPEC_200)
275 return;
276
277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
278
279 /*
280 * Always adjust the DMA selection as some controllers
281 * (e.g. JMicron) can't do PIO properly when the selection
282 * is ADMA.
283 */
284 ctrl &= ~SDHCI_CTRL_DMA_MASK;
285 if (!(host->flags & SDHCI_REQ_USE_DMA))
286 goto out;
287
288 /* Note if DMA Select is zero then SDMA is selected */
289 if (host->flags & SDHCI_USE_ADMA)
290 ctrl |= SDHCI_CTRL_ADMA32;
291
292 if (host->flags & SDHCI_USE_64_BIT_DMA) {
293 /*
294 * If v4 mode, all supported DMA can be 64-bit addressing if
295 * controller supports 64-bit system address, otherwise only
296 * ADMA can support 64-bit addressing.
297 */
298 if (host->v4_mode) {
299 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
300 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
301 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
302 } else if (host->flags & SDHCI_USE_ADMA) {
303 /*
304 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
305 * set SDHCI_CTRL_ADMA64.
306 */
307 ctrl |= SDHCI_CTRL_ADMA64;
308 }
309 }
310
311out:
312 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
313}
314
315static void sdhci_init(struct sdhci_host *host, int soft)
316{
317 struct mmc_host *mmc = host->mmc;
318
319 if (soft)
320 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
321 else
322 sdhci_do_reset(host, SDHCI_RESET_ALL);
323
324 if (host->v4_mode)
325 sdhci_do_enable_v4_mode(host);
326
327 sdhci_set_default_irqs(host);
328
329 host->cqe_on = false;
330
331 if (soft) {
332 /* force clock reconfiguration */
333 host->clock = 0;
334 mmc->ops->set_ios(mmc, &mmc->ios);
335 }
336}
337
338static void sdhci_reinit(struct sdhci_host *host)
339{
340 sdhci_init(host, 0);
341 sdhci_enable_card_detection(host);
342}
343
344static void __sdhci_led_activate(struct sdhci_host *host)
345{
346 u8 ctrl;
347
348 if (host->quirks & SDHCI_QUIRK_NO_LED)
349 return;
350
351 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
352 ctrl |= SDHCI_CTRL_LED;
353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
354}
355
356static void __sdhci_led_deactivate(struct sdhci_host *host)
357{
358 u8 ctrl;
359
360 if (host->quirks & SDHCI_QUIRK_NO_LED)
361 return;
362
363 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
364 ctrl &= ~SDHCI_CTRL_LED;
365 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
366}
367
368#if IS_REACHABLE(CONFIG_LEDS_CLASS)
369static void sdhci_led_control(struct led_classdev *led,
370 enum led_brightness brightness)
371{
372 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
373 unsigned long flags;
374
375 spin_lock_irqsave(&host->lock, flags);
376
377 if (host->runtime_suspended)
378 goto out;
379
380 if (brightness == LED_OFF)
381 __sdhci_led_deactivate(host);
382 else
383 __sdhci_led_activate(host);
384out:
385 spin_unlock_irqrestore(&host->lock, flags);
386}
387
388static int sdhci_led_register(struct sdhci_host *host)
389{
390 struct mmc_host *mmc = host->mmc;
391
392 if (host->quirks & SDHCI_QUIRK_NO_LED)
393 return 0;
394
395 snprintf(host->led_name, sizeof(host->led_name),
396 "%s::", mmc_hostname(mmc));
397
398 host->led.name = host->led_name;
399 host->led.brightness = LED_OFF;
400 host->led.default_trigger = mmc_hostname(mmc);
401 host->led.brightness_set = sdhci_led_control;
402
403 return led_classdev_register(mmc_dev(mmc), &host->led);
404}
405
406static void sdhci_led_unregister(struct sdhci_host *host)
407{
408 if (host->quirks & SDHCI_QUIRK_NO_LED)
409 return;
410
411 led_classdev_unregister(&host->led);
412}
413
414static inline void sdhci_led_activate(struct sdhci_host *host)
415{
416}
417
418static inline void sdhci_led_deactivate(struct sdhci_host *host)
419{
420}
421
422#else
423
424static inline int sdhci_led_register(struct sdhci_host *host)
425{
426 return 0;
427}
428
429static inline void sdhci_led_unregister(struct sdhci_host *host)
430{
431}
432
433static inline void sdhci_led_activate(struct sdhci_host *host)
434{
435 __sdhci_led_activate(host);
436}
437
438static inline void sdhci_led_deactivate(struct sdhci_host *host)
439{
440 __sdhci_led_deactivate(host);
441}
442
443#endif
444
445static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
446 unsigned long timeout)
447{
448 if (sdhci_data_line_cmd(mrq->cmd))
449 mod_timer(&host->data_timer, timeout);
450 else
451 mod_timer(&host->timer, timeout);
452}
453
454static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
455{
456 if (sdhci_data_line_cmd(mrq->cmd))
457 del_timer(&host->data_timer);
458 else
459 del_timer(&host->timer);
460}
461
462static inline bool sdhci_has_requests(struct sdhci_host *host)
463{
464 return host->cmd || host->data_cmd;
465}
466
467/*****************************************************************************\
468 * *
469 * Core functions *
470 * *
471\*****************************************************************************/
472
473static void sdhci_read_block_pio(struct sdhci_host *host)
474{
475 unsigned long flags;
476 size_t blksize, len, chunk;
477 u32 uninitialized_var(scratch);
478 u8 *buf;
479
480 DBG("PIO reading\n");
481
482 blksize = host->data->blksz;
483 chunk = 0;
484
485 local_irq_save(flags);
486
487 while (blksize) {
488 BUG_ON(!sg_miter_next(&host->sg_miter));
489
490 len = min(host->sg_miter.length, blksize);
491
492 blksize -= len;
493 host->sg_miter.consumed = len;
494
495 buf = host->sg_miter.addr;
496
497 while (len) {
498 if (chunk == 0) {
499 scratch = sdhci_readl(host, SDHCI_BUFFER);
500 chunk = 4;
501 }
502
503 *buf = scratch & 0xFF;
504
505 buf++;
506 scratch >>= 8;
507 chunk--;
508 len--;
509 }
510 }
511
512 sg_miter_stop(&host->sg_miter);
513
514 local_irq_restore(flags);
515}
516
517static void sdhci_write_block_pio(struct sdhci_host *host)
518{
519 unsigned long flags;
520 size_t blksize, len, chunk;
521 u32 scratch;
522 u8 *buf;
523
524 DBG("PIO writing\n");
525
526 blksize = host->data->blksz;
527 chunk = 0;
528 scratch = 0;
529
530 local_irq_save(flags);
531
532 while (blksize) {
533 BUG_ON(!sg_miter_next(&host->sg_miter));
534
535 len = min(host->sg_miter.length, blksize);
536
537 blksize -= len;
538 host->sg_miter.consumed = len;
539
540 buf = host->sg_miter.addr;
541
542 while (len) {
543 scratch |= (u32)*buf << (chunk * 8);
544
545 buf++;
546 chunk++;
547 len--;
548
549 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
550 sdhci_writel(host, scratch, SDHCI_BUFFER);
551 chunk = 0;
552 scratch = 0;
553 }
554 }
555 }
556
557 sg_miter_stop(&host->sg_miter);
558
559 local_irq_restore(flags);
560}
561
562static void sdhci_transfer_pio(struct sdhci_host *host)
563{
564 u32 mask;
565
566 if (host->blocks == 0)
567 return;
568
569 if (host->data->flags & MMC_DATA_READ)
570 mask = SDHCI_DATA_AVAILABLE;
571 else
572 mask = SDHCI_SPACE_AVAILABLE;
573
574 /*
575 * Some controllers (JMicron JMB38x) mess up the buffer bits
576 * for transfers < 4 bytes. As long as it is just one block,
577 * we can ignore the bits.
578 */
579 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
580 (host->data->blocks == 1))
581 mask = ~0;
582
583 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
584 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
585 udelay(100);
586
587 if (host->data->flags & MMC_DATA_READ)
588 sdhci_read_block_pio(host);
589 else
590 sdhci_write_block_pio(host);
591
592 host->blocks--;
593 if (host->blocks == 0)
594 break;
595 }
596
597 DBG("PIO transfer complete.\n");
598}
599
600static int sdhci_pre_dma_transfer(struct sdhci_host *host,
601 struct mmc_data *data, int cookie)
602{
603 int sg_count;
604
605 /*
606 * If the data buffers are already mapped, return the previous
607 * dma_map_sg() result.
608 */
609 if (data->host_cookie == COOKIE_PRE_MAPPED)
610 return data->sg_count;
611
612 /* Bounce write requests to the bounce buffer */
613 if (host->bounce_buffer) {
614 unsigned int length = data->blksz * data->blocks;
615
616 if (length > host->bounce_buffer_size) {
617 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
618 mmc_hostname(host->mmc), length,
619 host->bounce_buffer_size);
620 return -EIO;
621 }
622 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
623 /* Copy the data to the bounce buffer */
624 sg_copy_to_buffer(data->sg, data->sg_len,
625 host->bounce_buffer,
626 length);
627 }
628 /* Switch ownership to the DMA */
629 dma_sync_single_for_device(host->mmc->parent,
630 host->bounce_addr,
631 host->bounce_buffer_size,
632 mmc_get_dma_dir(data));
633 /* Just a dummy value */
634 sg_count = 1;
635 } else {
636 /* Just access the data directly from memory */
637 sg_count = dma_map_sg(mmc_dev(host->mmc),
638 data->sg, data->sg_len,
639 mmc_get_dma_dir(data));
640 }
641
642 if (sg_count == 0)
643 return -ENOSPC;
644
645 data->sg_count = sg_count;
646 data->host_cookie = cookie;
647
648 return sg_count;
649}
650
651static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
652{
653 local_irq_save(*flags);
654 return kmap_atomic(sg_page(sg)) + sg->offset;
655}
656
657static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
658{
659 kunmap_atomic(buffer);
660 local_irq_restore(*flags);
661}
662
663void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
664 dma_addr_t addr, int len, unsigned int cmd)
665{
666 struct sdhci_adma2_64_desc *dma_desc = *desc;
667
668 /* 32-bit and 64-bit descriptors have these members in same position */
669 dma_desc->cmd = cpu_to_le16(cmd);
670 dma_desc->len = cpu_to_le16(len);
671 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
672
673 if (host->flags & SDHCI_USE_64_BIT_DMA)
674 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
675
676 *desc += host->desc_sz;
677}
678EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
679
680static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
681 void **desc, dma_addr_t addr,
682 int len, unsigned int cmd)
683{
684 if (host->ops->adma_write_desc)
685 host->ops->adma_write_desc(host, desc, addr, len, cmd);
686 else
687 sdhci_adma_write_desc(host, desc, addr, len, cmd);
688}
689
690static void sdhci_adma_mark_end(void *desc)
691{
692 struct sdhci_adma2_64_desc *dma_desc = desc;
693
694 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
695 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
696}
697
698static void sdhci_adma_table_pre(struct sdhci_host *host,
699 struct mmc_data *data, int sg_count)
700{
701 struct scatterlist *sg;
702 unsigned long flags;
703 dma_addr_t addr, align_addr;
704 void *desc, *align;
705 char *buffer;
706 int len, offset, i;
707
708 /*
709 * The spec does not specify endianness of descriptor table.
710 * We currently guess that it is LE.
711 */
712
713 host->sg_count = sg_count;
714
715 desc = host->adma_table;
716 align = host->align_buffer;
717
718 align_addr = host->align_addr;
719
720 for_each_sg(data->sg, sg, host->sg_count, i) {
721 addr = sg_dma_address(sg);
722 len = sg_dma_len(sg);
723
724 /*
725 * The SDHCI specification states that ADMA addresses must
726 * be 32-bit aligned. If they aren't, then we use a bounce
727 * buffer for the (up to three) bytes that screw up the
728 * alignment.
729 */
730 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
731 SDHCI_ADMA2_MASK;
732 if (offset) {
733 if (data->flags & MMC_DATA_WRITE) {
734 buffer = sdhci_kmap_atomic(sg, &flags);
735 memcpy(align, buffer, offset);
736 sdhci_kunmap_atomic(buffer, &flags);
737 }
738
739 /* tran, valid */
740 __sdhci_adma_write_desc(host, &desc, align_addr,
741 offset, ADMA2_TRAN_VALID);
742
743 BUG_ON(offset > 65536);
744
745 align += SDHCI_ADMA2_ALIGN;
746 align_addr += SDHCI_ADMA2_ALIGN;
747
748 addr += offset;
749 len -= offset;
750 }
751
752 BUG_ON(len > 65536);
753
754 /* tran, valid */
755 if (len)
756 __sdhci_adma_write_desc(host, &desc, addr, len,
757 ADMA2_TRAN_VALID);
758
759 /*
760 * If this triggers then we have a calculation bug
761 * somewhere. :/
762 */
763 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
764 }
765
766 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
767 /* Mark the last descriptor as the terminating descriptor */
768 if (desc != host->adma_table) {
769 desc -= host->desc_sz;
770 sdhci_adma_mark_end(desc);
771 }
772 } else {
773 /* Add a terminating entry - nop, end, valid */
774 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
775 }
776}
777
778static void sdhci_adma_table_post(struct sdhci_host *host,
779 struct mmc_data *data)
780{
781 struct scatterlist *sg;
782 int i, size;
783 void *align;
784 char *buffer;
785 unsigned long flags;
786
787 if (data->flags & MMC_DATA_READ) {
788 bool has_unaligned = false;
789
790 /* Do a quick scan of the SG list for any unaligned mappings */
791 for_each_sg(data->sg, sg, host->sg_count, i)
792 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
793 has_unaligned = true;
794 break;
795 }
796
797 if (has_unaligned) {
798 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
799 data->sg_len, DMA_FROM_DEVICE);
800
801 align = host->align_buffer;
802
803 for_each_sg(data->sg, sg, host->sg_count, i) {
804 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
805 size = SDHCI_ADMA2_ALIGN -
806 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
807
808 buffer = sdhci_kmap_atomic(sg, &flags);
809 memcpy(buffer, align, size);
810 sdhci_kunmap_atomic(buffer, &flags);
811
812 align += SDHCI_ADMA2_ALIGN;
813 }
814 }
815 }
816 }
817}
818
819static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
820{
821 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
822 if (host->flags & SDHCI_USE_64_BIT_DMA)
823 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
824}
825
826static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
827{
828 if (host->bounce_buffer)
829 return host->bounce_addr;
830 else
831 return sg_dma_address(host->data->sg);
832}
833
834static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
835{
836 if (host->v4_mode)
837 sdhci_set_adma_addr(host, addr);
838 else
839 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
840}
841
842static unsigned int sdhci_target_timeout(struct sdhci_host *host,
843 struct mmc_command *cmd,
844 struct mmc_data *data)
845{
846 unsigned int target_timeout;
847
848 /* timeout in us */
849 if (!data) {
850 target_timeout = cmd->busy_timeout * 1000;
851 } else {
852 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
853 if (host->clock && data->timeout_clks) {
854 unsigned long long val;
855
856 /*
857 * data->timeout_clks is in units of clock cycles.
858 * host->clock is in Hz. target_timeout is in us.
859 * Hence, us = 1000000 * cycles / Hz. Round up.
860 */
861 val = 1000000ULL * data->timeout_clks;
862 if (do_div(val, host->clock))
863 target_timeout++;
864 target_timeout += val;
865 }
866 }
867
868 return target_timeout;
869}
870
871static void sdhci_calc_sw_timeout(struct sdhci_host *host,
872 struct mmc_command *cmd)
873{
874 struct mmc_data *data = cmd->data;
875 struct mmc_host *mmc = host->mmc;
876 struct mmc_ios *ios = &mmc->ios;
877 unsigned char bus_width = 1 << ios->bus_width;
878 unsigned int blksz;
879 unsigned int freq;
880 u64 target_timeout;
881 u64 transfer_time;
882
883 target_timeout = sdhci_target_timeout(host, cmd, data);
884 target_timeout *= NSEC_PER_USEC;
885
886 if (data) {
887 blksz = data->blksz;
888 freq = host->mmc->actual_clock ? : host->clock;
889 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
890 do_div(transfer_time, freq);
891 /* multiply by '2' to account for any unknowns */
892 transfer_time = transfer_time * 2;
893 /* calculate timeout for the entire data */
894 host->data_timeout = data->blocks * target_timeout +
895 transfer_time;
896 } else {
897 host->data_timeout = target_timeout;
898 }
899
900 if (host->data_timeout)
901 host->data_timeout += MMC_CMD_TRANSFER_TIME;
902}
903
904static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
905 bool *too_big)
906{
907 u8 count;
908 struct mmc_data *data;
909 unsigned target_timeout, current_timeout;
910
911 *too_big = true;
912
913 /*
914 * If the host controller provides us with an incorrect timeout
915 * value, just skip the check and use 0xE. The hardware may take
916 * longer to time out, but that's much better than having a too-short
917 * timeout value.
918 */
919 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
920 return 0xE;
921
922 /* Unspecified command, asume max */
923 if (cmd == NULL)
924 return 0xE;
925
926 data = cmd->data;
927 /* Unspecified timeout, assume max */
928 if (!data && !cmd->busy_timeout)
929 return 0xE;
930
931 /* timeout in us */
932 target_timeout = sdhci_target_timeout(host, cmd, data);
933
934 /*
935 * Figure out needed cycles.
936 * We do this in steps in order to fit inside a 32 bit int.
937 * The first step is the minimum timeout, which will have a
938 * minimum resolution of 6 bits:
939 * (1) 2^13*1000 > 2^22,
940 * (2) host->timeout_clk < 2^16
941 * =>
942 * (1) / (2) > 2^6
943 */
944 count = 0;
945 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
946 while (current_timeout < target_timeout) {
947 count++;
948 current_timeout <<= 1;
949 if (count >= 0xF)
950 break;
951 }
952
953 if (count >= 0xF) {
954 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
955 DBG("Too large timeout 0x%x requested for CMD%d!\n",
956 count, cmd->opcode);
957 count = 0xE;
958 } else {
959 *too_big = false;
960 }
961
962 return count;
963}
964
965static void sdhci_set_transfer_irqs(struct sdhci_host *host)
966{
967 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
968 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
969
970 if (host->flags & SDHCI_REQ_USE_DMA)
971 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
972 else
973 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
974
975 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
976 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
977 else
978 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
979
980 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
981 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
982}
983
984static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
985{
986 if (enable)
987 host->ier |= SDHCI_INT_DATA_TIMEOUT;
988 else
989 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
990 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
991 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
992}
993
994static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
995{
996 u8 count;
997
998 if (host->ops->set_timeout) {
999 host->ops->set_timeout(host, cmd);
1000 } else {
1001 bool too_big = false;
1002
1003 count = sdhci_calc_timeout(host, cmd, &too_big);
1004
1005 if (too_big &&
1006 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1007 sdhci_calc_sw_timeout(host, cmd);
1008 sdhci_set_data_timeout_irq(host, false);
1009 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1010 sdhci_set_data_timeout_irq(host, true);
1011 }
1012
1013 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1014 }
1015}
1016
1017static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1018{
1019 struct mmc_data *data = cmd->data;
1020
1021 host->data_timeout = 0;
1022
1023 if (sdhci_data_line_cmd(cmd))
1024 sdhci_set_timeout(host, cmd);
1025
1026 if (!data)
1027 return;
1028
1029 WARN_ON(host->data);
1030
1031 /* Sanity checks */
1032 BUG_ON(data->blksz * data->blocks > 524288);
1033 BUG_ON(data->blksz > host->mmc->max_blk_size);
1034 BUG_ON(data->blocks > 65535);
1035
1036 host->data = data;
1037 host->data_early = 0;
1038 host->data->bytes_xfered = 0;
1039
1040 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1041 struct scatterlist *sg;
1042 unsigned int length_mask, offset_mask;
1043 int i;
1044
1045 host->flags |= SDHCI_REQ_USE_DMA;
1046
1047 /*
1048 * FIXME: This doesn't account for merging when mapping the
1049 * scatterlist.
1050 *
1051 * The assumption here being that alignment and lengths are
1052 * the same after DMA mapping to device address space.
1053 */
1054 length_mask = 0;
1055 offset_mask = 0;
1056 if (host->flags & SDHCI_USE_ADMA) {
1057 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1058 length_mask = 3;
1059 /*
1060 * As we use up to 3 byte chunks to work
1061 * around alignment problems, we need to
1062 * check the offset as well.
1063 */
1064 offset_mask = 3;
1065 }
1066 } else {
1067 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1068 length_mask = 3;
1069 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1070 offset_mask = 3;
1071 }
1072
1073 if (unlikely(length_mask | offset_mask)) {
1074 for_each_sg(data->sg, sg, data->sg_len, i) {
1075 if (sg->length & length_mask) {
1076 DBG("Reverting to PIO because of transfer size (%d)\n",
1077 sg->length);
1078 host->flags &= ~SDHCI_REQ_USE_DMA;
1079 break;
1080 }
1081 if (sg->offset & offset_mask) {
1082 DBG("Reverting to PIO because of bad alignment\n");
1083 host->flags &= ~SDHCI_REQ_USE_DMA;
1084 break;
1085 }
1086 }
1087 }
1088 }
1089
1090 if (host->flags & SDHCI_REQ_USE_DMA) {
1091 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1092
1093 if (sg_cnt <= 0) {
1094 /*
1095 * This only happens when someone fed
1096 * us an invalid request.
1097 */
1098 WARN_ON(1);
1099 host->flags &= ~SDHCI_REQ_USE_DMA;
1100 } else if (host->flags & SDHCI_USE_ADMA) {
1101 sdhci_adma_table_pre(host, data, sg_cnt);
1102 sdhci_set_adma_addr(host, host->adma_addr);
1103 } else {
1104 WARN_ON(sg_cnt != 1);
1105 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1106 }
1107 }
1108
1109 sdhci_config_dma(host);
1110
1111 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1112 int flags;
1113
1114 flags = SG_MITER_ATOMIC;
1115 if (host->data->flags & MMC_DATA_READ)
1116 flags |= SG_MITER_TO_SG;
1117 else
1118 flags |= SG_MITER_FROM_SG;
1119 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1120 host->blocks = data->blocks;
1121 }
1122
1123 sdhci_set_transfer_irqs(host);
1124
1125 /* Set the DMA boundary value and block size */
1126 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1127 SDHCI_BLOCK_SIZE);
1128
1129 /*
1130 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1131 * can be supported, in that case 16-bit block count register must be 0.
1132 */
1133 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1134 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1135 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1136 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1137 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1138 } else {
1139 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1140 }
1141}
1142
1143static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1144 struct mmc_request *mrq)
1145{
1146 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1147 !mrq->cap_cmd_during_tfr;
1148}
1149
1150static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1151 struct mmc_command *cmd,
1152 u16 *mode)
1153{
1154 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1155 (cmd->opcode != SD_IO_RW_EXTENDED);
1156 bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1157 u16 ctrl2;
1158
1159 /*
1160 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1161 * Select' is recommended rather than use of 'Auto CMD12
1162 * Enable' or 'Auto CMD23 Enable'.
1163 */
1164 if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
1165 *mode |= SDHCI_TRNS_AUTO_SEL;
1166
1167 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1168 if (use_cmd23)
1169 ctrl2 |= SDHCI_CMD23_ENABLE;
1170 else
1171 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1172 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1173
1174 return;
1175 }
1176
1177 /*
1178 * If we are sending CMD23, CMD12 never gets sent
1179 * on successful completion (so no Auto-CMD12).
1180 */
1181 if (use_cmd12)
1182 *mode |= SDHCI_TRNS_AUTO_CMD12;
1183 else if (use_cmd23)
1184 *mode |= SDHCI_TRNS_AUTO_CMD23;
1185}
1186
1187static void sdhci_set_transfer_mode(struct sdhci_host *host,
1188 struct mmc_command *cmd)
1189{
1190 u16 mode = 0;
1191 struct mmc_data *data = cmd->data;
1192
1193 if (data == NULL) {
1194 if (host->quirks2 &
1195 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1196 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1197 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1198 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1199 } else {
1200 /* clear Auto CMD settings for no data CMDs */
1201 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1202 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1203 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1204 }
1205 return;
1206 }
1207
1208 WARN_ON(!host->data);
1209
1210 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1211 mode = SDHCI_TRNS_BLK_CNT_EN;
1212
1213 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1214 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1215 sdhci_auto_cmd_select(host, cmd, &mode);
1216 if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23))
1217 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1218 }
1219
1220 if (data->flags & MMC_DATA_READ)
1221 mode |= SDHCI_TRNS_READ;
1222 if (host->flags & SDHCI_REQ_USE_DMA)
1223 mode |= SDHCI_TRNS_DMA;
1224
1225 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1226}
1227
1228static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1229{
1230 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1231 ((mrq->cmd && mrq->cmd->error) ||
1232 (mrq->sbc && mrq->sbc->error) ||
1233 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1234 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1235}
1236
1237static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1238{
1239 int i;
1240
1241 if (host->cmd && host->cmd->mrq == mrq)
1242 host->cmd = NULL;
1243
1244 if (host->data_cmd && host->data_cmd->mrq == mrq)
1245 host->data_cmd = NULL;
1246
1247 if (host->data && host->data->mrq == mrq)
1248 host->data = NULL;
1249
1250 if (sdhci_needs_reset(host, mrq))
1251 host->pending_reset = true;
1252
1253 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1254 if (host->mrqs_done[i] == mrq) {
1255 WARN_ON(1);
1256 return;
1257 }
1258 }
1259
1260 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1261 if (!host->mrqs_done[i]) {
1262 host->mrqs_done[i] = mrq;
1263 break;
1264 }
1265 }
1266
1267 WARN_ON(i >= SDHCI_MAX_MRQS);
1268
1269 sdhci_del_timer(host, mrq);
1270
1271 if (!sdhci_has_requests(host))
1272 sdhci_led_deactivate(host);
1273}
1274
1275static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1276{
1277 __sdhci_finish_mrq(host, mrq);
1278
1279 queue_work(host->complete_wq, &host->complete_work);
1280}
1281
1282static void sdhci_finish_data(struct sdhci_host *host)
1283{
1284 struct mmc_command *data_cmd = host->data_cmd;
1285 struct mmc_data *data = host->data;
1286
1287 host->data = NULL;
1288 host->data_cmd = NULL;
1289
1290 /*
1291 * The controller needs a reset of internal state machines upon error
1292 * conditions.
1293 */
1294 if (data->error) {
1295 if (!host->cmd || host->cmd == data_cmd)
1296 sdhci_do_reset(host, SDHCI_RESET_CMD);
1297 sdhci_do_reset(host, SDHCI_RESET_DATA);
1298 }
1299
1300 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1301 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1302 sdhci_adma_table_post(host, data);
1303
1304 /*
1305 * The specification states that the block count register must
1306 * be updated, but it does not specify at what point in the
1307 * data flow. That makes the register entirely useless to read
1308 * back so we have to assume that nothing made it to the card
1309 * in the event of an error.
1310 */
1311 if (data->error)
1312 data->bytes_xfered = 0;
1313 else
1314 data->bytes_xfered = data->blksz * data->blocks;
1315
1316 /*
1317 * Need to send CMD12 if -
1318 * a) open-ended multiblock transfer (no CMD23)
1319 * b) error in multiblock transfer
1320 */
1321 if (data->stop &&
1322 (data->error ||
1323 !data->mrq->sbc)) {
1324 /*
1325 * 'cap_cmd_during_tfr' request must not use the command line
1326 * after mmc_command_done() has been called. It is upper layer's
1327 * responsibility to send the stop command if required.
1328 */
1329 if (data->mrq->cap_cmd_during_tfr) {
1330 __sdhci_finish_mrq(host, data->mrq);
1331 } else {
1332 /* Avoid triggering warning in sdhci_send_command() */
1333 host->cmd = NULL;
1334 sdhci_send_command(host, data->stop);
1335 }
1336 } else {
1337 __sdhci_finish_mrq(host, data->mrq);
1338 }
1339}
1340
1341void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1342{
1343 int flags;
1344 u32 mask;
1345 unsigned long timeout;
1346
1347 WARN_ON(host->cmd);
1348
1349 /* Initially, a command has no error */
1350 cmd->error = 0;
1351
1352 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1353 cmd->opcode == MMC_STOP_TRANSMISSION)
1354 cmd->flags |= MMC_RSP_BUSY;
1355
1356 /* Wait max 10 ms */
1357 timeout = 10;
1358
1359 mask = SDHCI_CMD_INHIBIT;
1360 if (sdhci_data_line_cmd(cmd))
1361 mask |= SDHCI_DATA_INHIBIT;
1362
1363 /* We shouldn't wait for data inihibit for stop commands, even
1364 though they might use busy signaling */
1365 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1366 mask &= ~SDHCI_DATA_INHIBIT;
1367
1368 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1369 if (timeout == 0) {
1370 pr_err("%s: Controller never released inhibit bit(s).\n",
1371 mmc_hostname(host->mmc));
1372 sdhci_dumpregs(host);
1373 cmd->error = -EIO;
1374 sdhci_finish_mrq(host, cmd->mrq);
1375 return;
1376 }
1377 timeout--;
1378 mdelay(1);
1379 }
1380
1381 host->cmd = cmd;
1382 if (sdhci_data_line_cmd(cmd)) {
1383 WARN_ON(host->data_cmd);
1384 host->data_cmd = cmd;
1385 }
1386
1387 sdhci_prepare_data(host, cmd);
1388
1389 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1390
1391 sdhci_set_transfer_mode(host, cmd);
1392
1393 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1394 pr_err("%s: Unsupported response type!\n",
1395 mmc_hostname(host->mmc));
1396 cmd->error = -EINVAL;
1397 sdhci_finish_mrq(host, cmd->mrq);
1398 return;
1399 }
1400
1401 if (!(cmd->flags & MMC_RSP_PRESENT))
1402 flags = SDHCI_CMD_RESP_NONE;
1403 else if (cmd->flags & MMC_RSP_136)
1404 flags = SDHCI_CMD_RESP_LONG;
1405 else if (cmd->flags & MMC_RSP_BUSY)
1406 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1407 else
1408 flags = SDHCI_CMD_RESP_SHORT;
1409
1410 if (cmd->flags & MMC_RSP_CRC)
1411 flags |= SDHCI_CMD_CRC;
1412 if (cmd->flags & MMC_RSP_OPCODE)
1413 flags |= SDHCI_CMD_INDEX;
1414
1415 /* CMD19 is special in that the Data Present Select should be set */
1416 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1417 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1418 flags |= SDHCI_CMD_DATA;
1419
1420 timeout = jiffies;
1421 if (host->data_timeout)
1422 timeout += nsecs_to_jiffies(host->data_timeout);
1423 else if (!cmd->data && cmd->busy_timeout > 9000)
1424 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1425 else
1426 timeout += 10 * HZ;
1427 sdhci_mod_timer(host, cmd->mrq, timeout);
1428
1429 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1430}
1431EXPORT_SYMBOL_GPL(sdhci_send_command);
1432
1433static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1434{
1435 int i, reg;
1436
1437 for (i = 0; i < 4; i++) {
1438 reg = SDHCI_RESPONSE + (3 - i) * 4;
1439 cmd->resp[i] = sdhci_readl(host, reg);
1440 }
1441
1442 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1443 return;
1444
1445 /* CRC is stripped so we need to do some shifting */
1446 for (i = 0; i < 4; i++) {
1447 cmd->resp[i] <<= 8;
1448 if (i != 3)
1449 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1450 }
1451}
1452
1453static void sdhci_finish_command(struct sdhci_host *host)
1454{
1455 struct mmc_command *cmd = host->cmd;
1456
1457 host->cmd = NULL;
1458
1459 if (cmd->flags & MMC_RSP_PRESENT) {
1460 if (cmd->flags & MMC_RSP_136) {
1461 sdhci_read_rsp_136(host, cmd);
1462 } else {
1463 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1464 }
1465 }
1466
1467 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1468 mmc_command_done(host->mmc, cmd->mrq);
1469
1470 /*
1471 * The host can send and interrupt when the busy state has
1472 * ended, allowing us to wait without wasting CPU cycles.
1473 * The busy signal uses DAT0 so this is similar to waiting
1474 * for data to complete.
1475 *
1476 * Note: The 1.0 specification is a bit ambiguous about this
1477 * feature so there might be some problems with older
1478 * controllers.
1479 */
1480 if (cmd->flags & MMC_RSP_BUSY) {
1481 if (cmd->data) {
1482 DBG("Cannot wait for busy signal when also doing a data transfer");
1483 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1484 cmd == host->data_cmd) {
1485 /* Command complete before busy is ended */
1486 return;
1487 }
1488 }
1489
1490 /* Finished CMD23, now send actual command. */
1491 if (cmd == cmd->mrq->sbc) {
1492 sdhci_send_command(host, cmd->mrq->cmd);
1493 } else {
1494
1495 /* Processed actual command. */
1496 if (host->data && host->data_early)
1497 sdhci_finish_data(host);
1498
1499 if (!cmd->data)
1500 __sdhci_finish_mrq(host, cmd->mrq);
1501 }
1502}
1503
1504static u16 sdhci_get_preset_value(struct sdhci_host *host)
1505{
1506 u16 preset = 0;
1507
1508 switch (host->timing) {
1509 case MMC_TIMING_UHS_SDR12:
1510 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1511 break;
1512 case MMC_TIMING_UHS_SDR25:
1513 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1514 break;
1515 case MMC_TIMING_UHS_SDR50:
1516 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1517 break;
1518 case MMC_TIMING_UHS_SDR104:
1519 case MMC_TIMING_MMC_HS200:
1520 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1521 break;
1522 case MMC_TIMING_UHS_DDR50:
1523 case MMC_TIMING_MMC_DDR52:
1524 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1525 break;
1526 case MMC_TIMING_MMC_HS400:
1527 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1528 break;
1529 default:
1530 pr_warn("%s: Invalid UHS-I mode selected\n",
1531 mmc_hostname(host->mmc));
1532 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1533 break;
1534 }
1535 return preset;
1536}
1537
1538u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1539 unsigned int *actual_clock)
1540{
1541 int div = 0; /* Initialized for compiler warning */
1542 int real_div = div, clk_mul = 1;
1543 u16 clk = 0;
1544 bool switch_base_clk = false;
1545
1546 if (host->version >= SDHCI_SPEC_300) {
1547 if (host->preset_enabled) {
1548 u16 pre_val;
1549
1550 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1551 pre_val = sdhci_get_preset_value(host);
1552 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1553 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1554 if (host->clk_mul &&
1555 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1556 clk = SDHCI_PROG_CLOCK_MODE;
1557 real_div = div + 1;
1558 clk_mul = host->clk_mul;
1559 } else {
1560 real_div = max_t(int, 1, div << 1);
1561 }
1562 goto clock_set;
1563 }
1564
1565 /*
1566 * Check if the Host Controller supports Programmable Clock
1567 * Mode.
1568 */
1569 if (host->clk_mul) {
1570 for (div = 1; div <= 1024; div++) {
1571 if ((host->max_clk * host->clk_mul / div)
1572 <= clock)
1573 break;
1574 }
1575 if ((host->max_clk * host->clk_mul / div) <= clock) {
1576 /*
1577 * Set Programmable Clock Mode in the Clock
1578 * Control register.
1579 */
1580 clk = SDHCI_PROG_CLOCK_MODE;
1581 real_div = div;
1582 clk_mul = host->clk_mul;
1583 div--;
1584 } else {
1585 /*
1586 * Divisor can be too small to reach clock
1587 * speed requirement. Then use the base clock.
1588 */
1589 switch_base_clk = true;
1590 }
1591 }
1592
1593 if (!host->clk_mul || switch_base_clk) {
1594 /* Version 3.00 divisors must be a multiple of 2. */
1595 if (host->max_clk <= clock)
1596 div = 1;
1597 else {
1598 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1599 div += 2) {
1600 if ((host->max_clk / div) <= clock)
1601 break;
1602 }
1603 }
1604 real_div = div;
1605 div >>= 1;
1606 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1607 && !div && host->max_clk <= 25000000)
1608 div = 1;
1609 }
1610 } else {
1611 /* Version 2.00 divisors must be a power of 2. */
1612 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1613 if ((host->max_clk / div) <= clock)
1614 break;
1615 }
1616 real_div = div;
1617 div >>= 1;
1618 }
1619
1620clock_set:
1621 if (real_div)
1622 *actual_clock = (host->max_clk * clk_mul) / real_div;
1623 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1624 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1625 << SDHCI_DIVIDER_HI_SHIFT;
1626
1627 return clk;
1628}
1629EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1630
1631void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1632{
1633 ktime_t timeout;
1634
1635 clk |= SDHCI_CLOCK_INT_EN;
1636 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1637
1638 /* Wait max 150 ms */
1639 timeout = ktime_add_ms(ktime_get(), 150);
1640 while (1) {
1641 bool timedout = ktime_after(ktime_get(), timeout);
1642
1643 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1644 if (clk & SDHCI_CLOCK_INT_STABLE)
1645 break;
1646 if (timedout) {
1647 pr_err("%s: Internal clock never stabilised.\n",
1648 mmc_hostname(host->mmc));
1649 sdhci_dumpregs(host);
1650 return;
1651 }
1652 udelay(10);
1653 }
1654
1655 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1656 clk |= SDHCI_CLOCK_PLL_EN;
1657 clk &= ~SDHCI_CLOCK_INT_STABLE;
1658 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1659
1660 /* Wait max 150 ms */
1661 timeout = ktime_add_ms(ktime_get(), 150);
1662 while (1) {
1663 bool timedout = ktime_after(ktime_get(), timeout);
1664
1665 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1666 if (clk & SDHCI_CLOCK_INT_STABLE)
1667 break;
1668 if (timedout) {
1669 pr_err("%s: PLL clock never stabilised.\n",
1670 mmc_hostname(host->mmc));
1671 sdhci_dumpregs(host);
1672 return;
1673 }
1674 udelay(10);
1675 }
1676 }
1677
1678 clk |= SDHCI_CLOCK_CARD_EN;
1679 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1680}
1681EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1682
1683void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1684{
1685 u16 clk;
1686
1687 host->mmc->actual_clock = 0;
1688
1689 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1690
1691 if (clock == 0)
1692 return;
1693
1694 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1695 sdhci_enable_clk(host, clk);
1696}
1697EXPORT_SYMBOL_GPL(sdhci_set_clock);
1698
1699static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1700 unsigned short vdd)
1701{
1702 struct mmc_host *mmc = host->mmc;
1703
1704 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1705
1706 if (mode != MMC_POWER_OFF)
1707 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1708 else
1709 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1710}
1711
1712void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1713 unsigned short vdd)
1714{
1715 u8 pwr = 0;
1716
1717 if (mode != MMC_POWER_OFF) {
1718 switch (1 << vdd) {
1719 case MMC_VDD_165_195:
1720 /*
1721 * Without a regulator, SDHCI does not support 2.0v
1722 * so we only get here if the driver deliberately
1723 * added the 2.0v range to ocr_avail. Map it to 1.8v
1724 * for the purpose of turning on the power.
1725 */
1726 case MMC_VDD_20_21:
1727 pwr = SDHCI_POWER_180;
1728 break;
1729 case MMC_VDD_29_30:
1730 case MMC_VDD_30_31:
1731 pwr = SDHCI_POWER_300;
1732 break;
1733 case MMC_VDD_32_33:
1734 case MMC_VDD_33_34:
1735 pwr = SDHCI_POWER_330;
1736 break;
1737 default:
1738 WARN(1, "%s: Invalid vdd %#x\n",
1739 mmc_hostname(host->mmc), vdd);
1740 break;
1741 }
1742 }
1743
1744 if (host->pwr == pwr)
1745 return;
1746
1747 host->pwr = pwr;
1748
1749 if (pwr == 0) {
1750 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1751 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1752 sdhci_runtime_pm_bus_off(host);
1753 } else {
1754 /*
1755 * Spec says that we should clear the power reg before setting
1756 * a new value. Some controllers don't seem to like this though.
1757 */
1758 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1759 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1760
1761 /*
1762 * At least the Marvell CaFe chip gets confused if we set the
1763 * voltage and set turn on power at the same time, so set the
1764 * voltage first.
1765 */
1766 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1767 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1768
1769 pwr |= SDHCI_POWER_ON;
1770
1771 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1772
1773 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1774 sdhci_runtime_pm_bus_on(host);
1775
1776 /*
1777 * Some controllers need an extra 10ms delay of 10ms before
1778 * they can apply clock after applying power
1779 */
1780 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1781 mdelay(10);
1782 }
1783}
1784EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1785
1786void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1787 unsigned short vdd)
1788{
1789 if (IS_ERR(host->mmc->supply.vmmc))
1790 sdhci_set_power_noreg(host, mode, vdd);
1791 else
1792 sdhci_set_power_reg(host, mode, vdd);
1793}
1794EXPORT_SYMBOL_GPL(sdhci_set_power);
1795
1796/*****************************************************************************\
1797 * *
1798 * MMC callbacks *
1799 * *
1800\*****************************************************************************/
1801
1802void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1803{
1804 struct sdhci_host *host;
1805 int present;
1806 unsigned long flags;
1807
1808 host = mmc_priv(mmc);
1809
1810 /* Firstly check card presence */
1811 present = mmc->ops->get_cd(mmc);
1812
1813 spin_lock_irqsave(&host->lock, flags);
1814
1815 sdhci_led_activate(host);
1816
1817 /*
1818 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1819 * requests if Auto-CMD12 is enabled.
1820 */
1821 if (sdhci_auto_cmd12(host, mrq)) {
1822 if (mrq->stop) {
1823 mrq->data->stop = NULL;
1824 mrq->stop = NULL;
1825 }
1826 }
1827
1828 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1829 mrq->cmd->error = -ENOMEDIUM;
1830 sdhci_finish_mrq(host, mrq);
1831 } else {
1832 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1833 sdhci_send_command(host, mrq->sbc);
1834 else
1835 sdhci_send_command(host, mrq->cmd);
1836 }
1837
1838 spin_unlock_irqrestore(&host->lock, flags);
1839}
1840EXPORT_SYMBOL_GPL(sdhci_request);
1841
1842void sdhci_set_bus_width(struct sdhci_host *host, int width)
1843{
1844 u8 ctrl;
1845
1846 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1847 if (width == MMC_BUS_WIDTH_8) {
1848 ctrl &= ~SDHCI_CTRL_4BITBUS;
1849 ctrl |= SDHCI_CTRL_8BITBUS;
1850 } else {
1851 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1852 ctrl &= ~SDHCI_CTRL_8BITBUS;
1853 if (width == MMC_BUS_WIDTH_4)
1854 ctrl |= SDHCI_CTRL_4BITBUS;
1855 else
1856 ctrl &= ~SDHCI_CTRL_4BITBUS;
1857 }
1858 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1859}
1860EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1861
1862void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1863{
1864 u16 ctrl_2;
1865
1866 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1867 /* Select Bus Speed Mode for host */
1868 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1869 if ((timing == MMC_TIMING_MMC_HS200) ||
1870 (timing == MMC_TIMING_UHS_SDR104))
1871 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1872 else if (timing == MMC_TIMING_UHS_SDR12)
1873 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1874 else if (timing == MMC_TIMING_SD_HS ||
1875 timing == MMC_TIMING_MMC_HS ||
1876 timing == MMC_TIMING_UHS_SDR25)
1877 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1878 else if (timing == MMC_TIMING_UHS_SDR50)
1879 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1880 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1881 (timing == MMC_TIMING_MMC_DDR52))
1882 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1883 else if (timing == MMC_TIMING_MMC_HS400)
1884 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1885 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1886}
1887EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1888
1889void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1890{
1891 struct sdhci_host *host = mmc_priv(mmc);
1892 u8 ctrl;
1893
1894 if (ios->power_mode == MMC_POWER_UNDEFINED)
1895 return;
1896
1897 if (host->flags & SDHCI_DEVICE_DEAD) {
1898 if (!IS_ERR(mmc->supply.vmmc) &&
1899 ios->power_mode == MMC_POWER_OFF)
1900 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1901 return;
1902 }
1903
1904 /*
1905 * Reset the chip on each power off.
1906 * Should clear out any weird states.
1907 */
1908 if (ios->power_mode == MMC_POWER_OFF) {
1909 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1910 sdhci_reinit(host);
1911 }
1912
1913 if (host->version >= SDHCI_SPEC_300 &&
1914 (ios->power_mode == MMC_POWER_UP) &&
1915 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1916 sdhci_enable_preset_value(host, false);
1917
1918 if (!ios->clock || ios->clock != host->clock) {
1919 host->ops->set_clock(host, ios->clock);
1920 host->clock = ios->clock;
1921
1922 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1923 host->clock) {
1924 host->timeout_clk = host->mmc->actual_clock ?
1925 host->mmc->actual_clock / 1000 :
1926 host->clock / 1000;
1927 host->mmc->max_busy_timeout =
1928 host->ops->get_max_timeout_count ?
1929 host->ops->get_max_timeout_count(host) :
1930 1 << 27;
1931 host->mmc->max_busy_timeout /= host->timeout_clk;
1932 }
1933 }
1934
1935 if (host->ops->set_power)
1936 host->ops->set_power(host, ios->power_mode, ios->vdd);
1937 else
1938 sdhci_set_power(host, ios->power_mode, ios->vdd);
1939
1940 if (host->ops->platform_send_init_74_clocks)
1941 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1942
1943 host->ops->set_bus_width(host, ios->bus_width);
1944
1945 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1946
1947 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1948 if (ios->timing == MMC_TIMING_SD_HS ||
1949 ios->timing == MMC_TIMING_MMC_HS ||
1950 ios->timing == MMC_TIMING_MMC_HS400 ||
1951 ios->timing == MMC_TIMING_MMC_HS200 ||
1952 ios->timing == MMC_TIMING_MMC_DDR52 ||
1953 ios->timing == MMC_TIMING_UHS_SDR50 ||
1954 ios->timing == MMC_TIMING_UHS_SDR104 ||
1955 ios->timing == MMC_TIMING_UHS_DDR50 ||
1956 ios->timing == MMC_TIMING_UHS_SDR25)
1957 ctrl |= SDHCI_CTRL_HISPD;
1958 else
1959 ctrl &= ~SDHCI_CTRL_HISPD;
1960 }
1961
1962 if (host->version >= SDHCI_SPEC_300) {
1963 u16 clk, ctrl_2;
1964
1965 if (!host->preset_enabled) {
1966 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1967 /*
1968 * We only need to set Driver Strength if the
1969 * preset value enable is not set.
1970 */
1971 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1972 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1973 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1974 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1975 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1976 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1977 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1978 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1979 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1980 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1981 else {
1982 pr_warn("%s: invalid driver type, default to driver type B\n",
1983 mmc_hostname(mmc));
1984 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1985 }
1986
1987 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1988 } else {
1989 /*
1990 * According to SDHC Spec v3.00, if the Preset Value
1991 * Enable in the Host Control 2 register is set, we
1992 * need to reset SD Clock Enable before changing High
1993 * Speed Enable to avoid generating clock gliches.
1994 */
1995
1996 /* Reset SD Clock Enable */
1997 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1998 clk &= ~SDHCI_CLOCK_CARD_EN;
1999 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2000
2001 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2002
2003 /* Re-enable SD Clock */
2004 host->ops->set_clock(host, host->clock);
2005 }
2006
2007 /* Reset SD Clock Enable */
2008 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2009 clk &= ~SDHCI_CLOCK_CARD_EN;
2010 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2011
2012 host->ops->set_uhs_signaling(host, ios->timing);
2013 host->timing = ios->timing;
2014
2015 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2016 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2017 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2018 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2019 (ios->timing == MMC_TIMING_UHS_SDR104) ||
2020 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2021 (ios->timing == MMC_TIMING_MMC_DDR52))) {
2022 u16 preset;
2023
2024 sdhci_enable_preset_value(host, true);
2025 preset = sdhci_get_preset_value(host);
2026 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
2027 >> SDHCI_PRESET_DRV_SHIFT;
2028 }
2029
2030 /* Re-enable SD Clock */
2031 host->ops->set_clock(host, host->clock);
2032 } else
2033 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2034
2035 /*
2036 * Some (ENE) controllers go apeshit on some ios operation,
2037 * signalling timeout and CRC errors even on CMD0. Resetting
2038 * it on each ios seems to solve the problem.
2039 */
2040 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2041 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2042}
2043EXPORT_SYMBOL_GPL(sdhci_set_ios);
2044
2045static int sdhci_get_cd(struct mmc_host *mmc)
2046{
2047 struct sdhci_host *host = mmc_priv(mmc);
2048 int gpio_cd = mmc_gpio_get_cd(mmc);
2049
2050 if (host->flags & SDHCI_DEVICE_DEAD)
2051 return 0;
2052
2053 /* If nonremovable, assume that the card is always present. */
2054 if (!mmc_card_is_removable(host->mmc))
2055 return 1;
2056
2057 /*
2058 * Try slot gpio detect, if defined it take precedence
2059 * over build in controller functionality
2060 */
2061 if (gpio_cd >= 0)
2062 return !!gpio_cd;
2063
2064 /* If polling, assume that the card is always present. */
2065 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2066 return 1;
2067
2068 /* Host native card detect */
2069 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2070}
2071
2072static int sdhci_check_ro(struct sdhci_host *host)
2073{
2074 unsigned long flags;
2075 int is_readonly;
2076
2077 spin_lock_irqsave(&host->lock, flags);
2078
2079 if (host->flags & SDHCI_DEVICE_DEAD)
2080 is_readonly = 0;
2081 else if (host->ops->get_ro)
2082 is_readonly = host->ops->get_ro(host);
2083 else if (mmc_can_gpio_ro(host->mmc))
2084 is_readonly = mmc_gpio_get_ro(host->mmc);
2085 else
2086 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2087 & SDHCI_WRITE_PROTECT);
2088
2089 spin_unlock_irqrestore(&host->lock, flags);
2090
2091 /* This quirk needs to be replaced by a callback-function later */
2092 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2093 !is_readonly : is_readonly;
2094}
2095
2096#define SAMPLE_COUNT 5
2097
2098static int sdhci_get_ro(struct mmc_host *mmc)
2099{
2100 struct sdhci_host *host = mmc_priv(mmc);
2101 int i, ro_count;
2102
2103 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2104 return sdhci_check_ro(host);
2105
2106 ro_count = 0;
2107 for (i = 0; i < SAMPLE_COUNT; i++) {
2108 if (sdhci_check_ro(host)) {
2109 if (++ro_count > SAMPLE_COUNT / 2)
2110 return 1;
2111 }
2112 msleep(30);
2113 }
2114 return 0;
2115}
2116
2117static void sdhci_hw_reset(struct mmc_host *mmc)
2118{
2119 struct sdhci_host *host = mmc_priv(mmc);
2120
2121 if (host->ops && host->ops->hw_reset)
2122 host->ops->hw_reset(host);
2123}
2124
2125static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2126{
2127 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2128 if (enable)
2129 host->ier |= SDHCI_INT_CARD_INT;
2130 else
2131 host->ier &= ~SDHCI_INT_CARD_INT;
2132
2133 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2134 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2135 }
2136}
2137
2138void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2139{
2140 struct sdhci_host *host = mmc_priv(mmc);
2141 unsigned long flags;
2142
2143 if (enable)
2144 pm_runtime_get_noresume(host->mmc->parent);
2145
2146 spin_lock_irqsave(&host->lock, flags);
2147 sdhci_enable_sdio_irq_nolock(host, enable);
2148 spin_unlock_irqrestore(&host->lock, flags);
2149
2150 if (!enable)
2151 pm_runtime_put_noidle(host->mmc->parent);
2152}
2153EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2154
2155static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2156{
2157 struct sdhci_host *host = mmc_priv(mmc);
2158 unsigned long flags;
2159
2160 spin_lock_irqsave(&host->lock, flags);
2161 sdhci_enable_sdio_irq_nolock(host, true);
2162 spin_unlock_irqrestore(&host->lock, flags);
2163}
2164
2165int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2166 struct mmc_ios *ios)
2167{
2168 struct sdhci_host *host = mmc_priv(mmc);
2169 u16 ctrl;
2170 int ret;
2171
2172 /*
2173 * Signal Voltage Switching is only applicable for Host Controllers
2174 * v3.00 and above.
2175 */
2176 if (host->version < SDHCI_SPEC_300)
2177 return 0;
2178
2179 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2180
2181 switch (ios->signal_voltage) {
2182 case MMC_SIGNAL_VOLTAGE_330:
2183 if (!(host->flags & SDHCI_SIGNALING_330))
2184 return -EINVAL;
2185 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2186 ctrl &= ~SDHCI_CTRL_VDD_180;
2187 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2188
2189 if (!IS_ERR(mmc->supply.vqmmc)) {
2190 ret = mmc_regulator_set_vqmmc(mmc, ios);
2191 if (ret) {
2192 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2193 mmc_hostname(mmc));
2194 return -EIO;
2195 }
2196 }
2197 /* Wait for 5ms */
2198 usleep_range(5000, 5500);
2199
2200 /* 3.3V regulator output should be stable within 5 ms */
2201 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2202 if (!(ctrl & SDHCI_CTRL_VDD_180))
2203 return 0;
2204
2205 pr_warn("%s: 3.3V regulator output did not became stable\n",
2206 mmc_hostname(mmc));
2207
2208 return -EAGAIN;
2209 case MMC_SIGNAL_VOLTAGE_180:
2210 if (!(host->flags & SDHCI_SIGNALING_180))
2211 return -EINVAL;
2212 if (!IS_ERR(mmc->supply.vqmmc)) {
2213 ret = mmc_regulator_set_vqmmc(mmc, ios);
2214 if (ret) {
2215 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2216 mmc_hostname(mmc));
2217 return -EIO;
2218 }
2219 }
2220
2221 /*
2222 * Enable 1.8V Signal Enable in the Host Control2
2223 * register
2224 */
2225 ctrl |= SDHCI_CTRL_VDD_180;
2226 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2227
2228 /* Some controller need to do more when switching */
2229 if (host->ops->voltage_switch)
2230 host->ops->voltage_switch(host);
2231
2232 /* 1.8V regulator output should be stable within 5 ms */
2233 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2234 if (ctrl & SDHCI_CTRL_VDD_180)
2235 return 0;
2236
2237 pr_warn("%s: 1.8V regulator output did not became stable\n",
2238 mmc_hostname(mmc));
2239
2240 return -EAGAIN;
2241 case MMC_SIGNAL_VOLTAGE_120:
2242 if (!(host->flags & SDHCI_SIGNALING_120))
2243 return -EINVAL;
2244 if (!IS_ERR(mmc->supply.vqmmc)) {
2245 ret = mmc_regulator_set_vqmmc(mmc, ios);
2246 if (ret) {
2247 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2248 mmc_hostname(mmc));
2249 return -EIO;
2250 }
2251 }
2252 return 0;
2253 default:
2254 /* No signal voltage switch required */
2255 return 0;
2256 }
2257}
2258EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2259
2260static int sdhci_card_busy(struct mmc_host *mmc)
2261{
2262 struct sdhci_host *host = mmc_priv(mmc);
2263 u32 present_state;
2264
2265 /* Check whether DAT[0] is 0 */
2266 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2267
2268 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2269}
2270
2271static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2272{
2273 struct sdhci_host *host = mmc_priv(mmc);
2274 unsigned long flags;
2275
2276 spin_lock_irqsave(&host->lock, flags);
2277 host->flags |= SDHCI_HS400_TUNING;
2278 spin_unlock_irqrestore(&host->lock, flags);
2279
2280 return 0;
2281}
2282
2283void sdhci_start_tuning(struct sdhci_host *host)
2284{
2285 u16 ctrl;
2286
2287 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2288 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2289 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2290 ctrl |= SDHCI_CTRL_TUNED_CLK;
2291 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2292
2293 /*
2294 * As per the Host Controller spec v3.00, tuning command
2295 * generates Buffer Read Ready interrupt, so enable that.
2296 *
2297 * Note: The spec clearly says that when tuning sequence
2298 * is being performed, the controller does not generate
2299 * interrupts other than Buffer Read Ready interrupt. But
2300 * to make sure we don't hit a controller bug, we _only_
2301 * enable Buffer Read Ready interrupt here.
2302 */
2303 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2304 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2305}
2306EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2307
2308void sdhci_end_tuning(struct sdhci_host *host)
2309{
2310 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2311 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2312}
2313EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2314
2315void sdhci_reset_tuning(struct sdhci_host *host)
2316{
2317 u16 ctrl;
2318
2319 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2320 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2321 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2322 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2323}
2324EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2325
2326void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2327{
2328 sdhci_reset_tuning(host);
2329
2330 sdhci_do_reset(host, SDHCI_RESET_CMD);
2331 sdhci_do_reset(host, SDHCI_RESET_DATA);
2332
2333 sdhci_end_tuning(host);
2334
2335 mmc_abort_tuning(host->mmc, opcode);
2336}
2337EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2338
2339/*
2340 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2341 * tuning command does not have a data payload (or rather the hardware does it
2342 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2343 * interrupt setup is different to other commands and there is no timeout
2344 * interrupt so special handling is needed.
2345 */
2346void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2347{
2348 struct mmc_host *mmc = host->mmc;
2349 struct mmc_command cmd = {};
2350 struct mmc_request mrq = {};
2351 unsigned long flags;
2352 u32 b = host->sdma_boundary;
2353
2354 spin_lock_irqsave(&host->lock, flags);
2355
2356 cmd.opcode = opcode;
2357 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2358 cmd.mrq = &mrq;
2359
2360 mrq.cmd = &cmd;
2361 /*
2362 * In response to CMD19, the card sends 64 bytes of tuning
2363 * block to the Host Controller. So we set the block size
2364 * to 64 here.
2365 */
2366 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2367 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2368 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2369 else
2370 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2371
2372 /*
2373 * The tuning block is sent by the card to the host controller.
2374 * So we set the TRNS_READ bit in the Transfer Mode register.
2375 * This also takes care of setting DMA Enable and Multi Block
2376 * Select in the same register to 0.
2377 */
2378 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2379
2380 sdhci_send_command(host, &cmd);
2381
2382 host->cmd = NULL;
2383
2384 sdhci_del_timer(host, &mrq);
2385
2386 host->tuning_done = 0;
2387
2388 spin_unlock_irqrestore(&host->lock, flags);
2389
2390 /* Wait for Buffer Read Ready interrupt */
2391 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2392 msecs_to_jiffies(50));
2393
2394}
2395EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2396
2397static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2398{
2399 int i;
2400
2401 /*
2402 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2403 * of loops reaches tuning loop count.
2404 */
2405 for (i = 0; i < host->tuning_loop_count; i++) {
2406 u16 ctrl;
2407
2408 sdhci_send_tuning(host, opcode);
2409
2410 if (!host->tuning_done) {
2411 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2412 mmc_hostname(host->mmc));
2413 sdhci_abort_tuning(host, opcode);
2414 return -ETIMEDOUT;
2415 }
2416
2417 /* Spec does not require a delay between tuning cycles */
2418 if (host->tuning_delay > 0)
2419 mdelay(host->tuning_delay);
2420
2421 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2422 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2423 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2424 return 0; /* Success! */
2425 break;
2426 }
2427
2428 }
2429
2430 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2431 mmc_hostname(host->mmc));
2432 sdhci_reset_tuning(host);
2433 return -EAGAIN;
2434}
2435
2436int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2437{
2438 struct sdhci_host *host = mmc_priv(mmc);
2439 int err = 0;
2440 unsigned int tuning_count = 0;
2441 bool hs400_tuning;
2442
2443 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2444
2445 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2446 tuning_count = host->tuning_count;
2447
2448 /*
2449 * The Host Controller needs tuning in case of SDR104 and DDR50
2450 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2451 * the Capabilities register.
2452 * If the Host Controller supports the HS200 mode then the
2453 * tuning function has to be executed.
2454 */
2455 switch (host->timing) {
2456 /* HS400 tuning is done in HS200 mode */
2457 case MMC_TIMING_MMC_HS400:
2458 err = -EINVAL;
2459 goto out;
2460
2461 case MMC_TIMING_MMC_HS200:
2462 /*
2463 * Periodic re-tuning for HS400 is not expected to be needed, so
2464 * disable it here.
2465 */
2466 if (hs400_tuning)
2467 tuning_count = 0;
2468 break;
2469
2470 case MMC_TIMING_UHS_SDR104:
2471 case MMC_TIMING_UHS_DDR50:
2472 break;
2473
2474 case MMC_TIMING_UHS_SDR50:
2475 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2476 break;
2477 /* FALLTHROUGH */
2478
2479 default:
2480 goto out;
2481 }
2482
2483 if (host->ops->platform_execute_tuning) {
2484 err = host->ops->platform_execute_tuning(host, opcode);
2485 goto out;
2486 }
2487
2488 host->mmc->retune_period = tuning_count;
2489
2490 if (host->tuning_delay < 0)
2491 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2492
2493 sdhci_start_tuning(host);
2494
2495 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2496
2497 sdhci_end_tuning(host);
2498out:
2499 host->flags &= ~SDHCI_HS400_TUNING;
2500
2501 return err;
2502}
2503EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2504
2505static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2506{
2507 /* Host Controller v3.00 defines preset value registers */
2508 if (host->version < SDHCI_SPEC_300)
2509 return;
2510
2511 /*
2512 * We only enable or disable Preset Value if they are not already
2513 * enabled or disabled respectively. Otherwise, we bail out.
2514 */
2515 if (host->preset_enabled != enable) {
2516 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2517
2518 if (enable)
2519 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2520 else
2521 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2522
2523 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2524
2525 if (enable)
2526 host->flags |= SDHCI_PV_ENABLED;
2527 else
2528 host->flags &= ~SDHCI_PV_ENABLED;
2529
2530 host->preset_enabled = enable;
2531 }
2532}
2533
2534static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2535 int err)
2536{
2537 struct sdhci_host *host = mmc_priv(mmc);
2538 struct mmc_data *data = mrq->data;
2539
2540 if (data->host_cookie != COOKIE_UNMAPPED)
2541 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2542 mmc_get_dma_dir(data));
2543
2544 data->host_cookie = COOKIE_UNMAPPED;
2545}
2546
2547static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2548{
2549 struct sdhci_host *host = mmc_priv(mmc);
2550
2551 mrq->data->host_cookie = COOKIE_UNMAPPED;
2552
2553 /*
2554 * No pre-mapping in the pre hook if we're using the bounce buffer,
2555 * for that we would need two bounce buffers since one buffer is
2556 * in flight when this is getting called.
2557 */
2558 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2559 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2560}
2561
2562static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2563{
2564 if (host->data_cmd) {
2565 host->data_cmd->error = err;
2566 sdhci_finish_mrq(host, host->data_cmd->mrq);
2567 }
2568
2569 if (host->cmd) {
2570 host->cmd->error = err;
2571 sdhci_finish_mrq(host, host->cmd->mrq);
2572 }
2573}
2574
2575static void sdhci_card_event(struct mmc_host *mmc)
2576{
2577 struct sdhci_host *host = mmc_priv(mmc);
2578 unsigned long flags;
2579 int present;
2580
2581 /* First check if client has provided their own card event */
2582 if (host->ops->card_event)
2583 host->ops->card_event(host);
2584
2585 present = mmc->ops->get_cd(mmc);
2586
2587 spin_lock_irqsave(&host->lock, flags);
2588
2589 /* Check sdhci_has_requests() first in case we are runtime suspended */
2590 if (sdhci_has_requests(host) && !present) {
2591 pr_err("%s: Card removed during transfer!\n",
2592 mmc_hostname(host->mmc));
2593 pr_err("%s: Resetting controller.\n",
2594 mmc_hostname(host->mmc));
2595
2596 sdhci_do_reset(host, SDHCI_RESET_CMD);
2597 sdhci_do_reset(host, SDHCI_RESET_DATA);
2598
2599 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2600 }
2601
2602 spin_unlock_irqrestore(&host->lock, flags);
2603}
2604
2605static const struct mmc_host_ops sdhci_ops = {
2606 .request = sdhci_request,
2607 .post_req = sdhci_post_req,
2608 .pre_req = sdhci_pre_req,
2609 .set_ios = sdhci_set_ios,
2610 .get_cd = sdhci_get_cd,
2611 .get_ro = sdhci_get_ro,
2612 .hw_reset = sdhci_hw_reset,
2613 .enable_sdio_irq = sdhci_enable_sdio_irq,
2614 .ack_sdio_irq = sdhci_ack_sdio_irq,
2615 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2616 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2617 .execute_tuning = sdhci_execute_tuning,
2618 .card_event = sdhci_card_event,
2619 .card_busy = sdhci_card_busy,
2620};
2621
2622/*****************************************************************************\
2623 * *
2624 * Request done *
2625 * *
2626\*****************************************************************************/
2627
2628static bool sdhci_request_done(struct sdhci_host *host)
2629{
2630 unsigned long flags;
2631 struct mmc_request *mrq;
2632 int i;
2633
2634 spin_lock_irqsave(&host->lock, flags);
2635
2636 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2637 mrq = host->mrqs_done[i];
2638 if (mrq)
2639 break;
2640 }
2641
2642 if (!mrq) {
2643 spin_unlock_irqrestore(&host->lock, flags);
2644 return true;
2645 }
2646
2647 /*
2648 * Always unmap the data buffers if they were mapped by
2649 * sdhci_prepare_data() whenever we finish with a request.
2650 * This avoids leaking DMA mappings on error.
2651 */
2652 if (host->flags & SDHCI_REQ_USE_DMA) {
2653 struct mmc_data *data = mrq->data;
2654
2655 if (data && data->host_cookie == COOKIE_MAPPED) {
2656 if (host->bounce_buffer) {
2657 /*
2658 * On reads, copy the bounced data into the
2659 * sglist
2660 */
2661 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2662 unsigned int length = data->bytes_xfered;
2663
2664 if (length > host->bounce_buffer_size) {
2665 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2666 mmc_hostname(host->mmc),
2667 host->bounce_buffer_size,
2668 data->bytes_xfered);
2669 /* Cap it down and continue */
2670 length = host->bounce_buffer_size;
2671 }
2672 dma_sync_single_for_cpu(
2673 host->mmc->parent,
2674 host->bounce_addr,
2675 host->bounce_buffer_size,
2676 DMA_FROM_DEVICE);
2677 sg_copy_from_buffer(data->sg,
2678 data->sg_len,
2679 host->bounce_buffer,
2680 length);
2681 } else {
2682 /* No copying, just switch ownership */
2683 dma_sync_single_for_cpu(
2684 host->mmc->parent,
2685 host->bounce_addr,
2686 host->bounce_buffer_size,
2687 mmc_get_dma_dir(data));
2688 }
2689 } else {
2690 /* Unmap the raw data */
2691 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2692 data->sg_len,
2693 mmc_get_dma_dir(data));
2694 }
2695 data->host_cookie = COOKIE_UNMAPPED;
2696 }
2697 }
2698
2699 /*
2700 * The controller needs a reset of internal state machines
2701 * upon error conditions.
2702 */
2703 if (sdhci_needs_reset(host, mrq)) {
2704 /*
2705 * Do not finish until command and data lines are available for
2706 * reset. Note there can only be one other mrq, so it cannot
2707 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2708 * would both be null.
2709 */
2710 if (host->cmd || host->data_cmd) {
2711 spin_unlock_irqrestore(&host->lock, flags);
2712 return true;
2713 }
2714
2715 /* Some controllers need this kick or reset won't work here */
2716 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2717 /* This is to force an update */
2718 host->ops->set_clock(host, host->clock);
2719
2720 /* Spec says we should do both at the same time, but Ricoh
2721 controllers do not like that. */
2722 sdhci_do_reset(host, SDHCI_RESET_CMD);
2723 sdhci_do_reset(host, SDHCI_RESET_DATA);
2724
2725 host->pending_reset = false;
2726 }
2727
2728 host->mrqs_done[i] = NULL;
2729
2730 spin_unlock_irqrestore(&host->lock, flags);
2731
2732 mmc_request_done(host->mmc, mrq);
2733
2734 return false;
2735}
2736
2737static void sdhci_complete_work(struct work_struct *work)
2738{
2739 struct sdhci_host *host = container_of(work, struct sdhci_host,
2740 complete_work);
2741
2742 while (!sdhci_request_done(host))
2743 ;
2744}
2745
2746static void sdhci_timeout_timer(struct timer_list *t)
2747{
2748 struct sdhci_host *host;
2749 unsigned long flags;
2750
2751 host = from_timer(host, t, timer);
2752
2753 spin_lock_irqsave(&host->lock, flags);
2754
2755 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2756 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2757 mmc_hostname(host->mmc));
2758 sdhci_dumpregs(host);
2759
2760 host->cmd->error = -ETIMEDOUT;
2761 sdhci_finish_mrq(host, host->cmd->mrq);
2762 }
2763
2764 spin_unlock_irqrestore(&host->lock, flags);
2765}
2766
2767static void sdhci_timeout_data_timer(struct timer_list *t)
2768{
2769 struct sdhci_host *host;
2770 unsigned long flags;
2771
2772 host = from_timer(host, t, data_timer);
2773
2774 spin_lock_irqsave(&host->lock, flags);
2775
2776 if (host->data || host->data_cmd ||
2777 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2778 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2779 mmc_hostname(host->mmc));
2780 sdhci_dumpregs(host);
2781
2782 if (host->data) {
2783 host->data->error = -ETIMEDOUT;
2784 sdhci_finish_data(host);
2785 queue_work(host->complete_wq, &host->complete_work);
2786 } else if (host->data_cmd) {
2787 host->data_cmd->error = -ETIMEDOUT;
2788 sdhci_finish_mrq(host, host->data_cmd->mrq);
2789 } else {
2790 host->cmd->error = -ETIMEDOUT;
2791 sdhci_finish_mrq(host, host->cmd->mrq);
2792 }
2793 }
2794
2795 spin_unlock_irqrestore(&host->lock, flags);
2796}
2797
2798/*****************************************************************************\
2799 * *
2800 * Interrupt handling *
2801 * *
2802\*****************************************************************************/
2803
2804static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2805{
2806 /* Handle auto-CMD12 error */
2807 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
2808 struct mmc_request *mrq = host->data_cmd->mrq;
2809 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2810 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2811 SDHCI_INT_DATA_TIMEOUT :
2812 SDHCI_INT_DATA_CRC;
2813
2814 /* Treat auto-CMD12 error the same as data error */
2815 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
2816 *intmask_p |= data_err_bit;
2817 return;
2818 }
2819 }
2820
2821 if (!host->cmd) {
2822 /*
2823 * SDHCI recovers from errors by resetting the cmd and data
2824 * circuits. Until that is done, there very well might be more
2825 * interrupts, so ignore them in that case.
2826 */
2827 if (host->pending_reset)
2828 return;
2829 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2830 mmc_hostname(host->mmc), (unsigned)intmask);
2831 sdhci_dumpregs(host);
2832 return;
2833 }
2834
2835 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2836 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2837 if (intmask & SDHCI_INT_TIMEOUT)
2838 host->cmd->error = -ETIMEDOUT;
2839 else
2840 host->cmd->error = -EILSEQ;
2841
2842 /* Treat data command CRC error the same as data CRC error */
2843 if (host->cmd->data &&
2844 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2845 SDHCI_INT_CRC) {
2846 host->cmd = NULL;
2847 *intmask_p |= SDHCI_INT_DATA_CRC;
2848 return;
2849 }
2850
2851 __sdhci_finish_mrq(host, host->cmd->mrq);
2852 return;
2853 }
2854
2855 /* Handle auto-CMD23 error */
2856 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
2857 struct mmc_request *mrq = host->cmd->mrq;
2858 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2859 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2860 -ETIMEDOUT :
2861 -EILSEQ;
2862
2863 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
2864 mrq->sbc->error = err;
2865 __sdhci_finish_mrq(host, mrq);
2866 return;
2867 }
2868 }
2869
2870 if (intmask & SDHCI_INT_RESPONSE)
2871 sdhci_finish_command(host);
2872}
2873
2874static void sdhci_adma_show_error(struct sdhci_host *host)
2875{
2876 void *desc = host->adma_table;
2877 dma_addr_t dma = host->adma_addr;
2878
2879 sdhci_dumpregs(host);
2880
2881 while (true) {
2882 struct sdhci_adma2_64_desc *dma_desc = desc;
2883
2884 if (host->flags & SDHCI_USE_64_BIT_DMA)
2885 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2886 (unsigned long long)dma,
2887 le32_to_cpu(dma_desc->addr_hi),
2888 le32_to_cpu(dma_desc->addr_lo),
2889 le16_to_cpu(dma_desc->len),
2890 le16_to_cpu(dma_desc->cmd));
2891 else
2892 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2893 (unsigned long long)dma,
2894 le32_to_cpu(dma_desc->addr_lo),
2895 le16_to_cpu(dma_desc->len),
2896 le16_to_cpu(dma_desc->cmd));
2897
2898 desc += host->desc_sz;
2899 dma += host->desc_sz;
2900
2901 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2902 break;
2903 }
2904}
2905
2906static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2907{
2908 u32 command;
2909
2910 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2911 if (intmask & SDHCI_INT_DATA_AVAIL) {
2912 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2913 if (command == MMC_SEND_TUNING_BLOCK ||
2914 command == MMC_SEND_TUNING_BLOCK_HS200) {
2915 host->tuning_done = 1;
2916 wake_up(&host->buf_ready_int);
2917 return;
2918 }
2919 }
2920
2921 if (!host->data) {
2922 struct mmc_command *data_cmd = host->data_cmd;
2923
2924 /*
2925 * The "data complete" interrupt is also used to
2926 * indicate that a busy state has ended. See comment
2927 * above in sdhci_cmd_irq().
2928 */
2929 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2930 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2931 host->data_cmd = NULL;
2932 data_cmd->error = -ETIMEDOUT;
2933 __sdhci_finish_mrq(host, data_cmd->mrq);
2934 return;
2935 }
2936 if (intmask & SDHCI_INT_DATA_END) {
2937 host->data_cmd = NULL;
2938 /*
2939 * Some cards handle busy-end interrupt
2940 * before the command completed, so make
2941 * sure we do things in the proper order.
2942 */
2943 if (host->cmd == data_cmd)
2944 return;
2945
2946 __sdhci_finish_mrq(host, data_cmd->mrq);
2947 return;
2948 }
2949 }
2950
2951 /*
2952 * SDHCI recovers from errors by resetting the cmd and data
2953 * circuits. Until that is done, there very well might be more
2954 * interrupts, so ignore them in that case.
2955 */
2956 if (host->pending_reset)
2957 return;
2958
2959 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2960 mmc_hostname(host->mmc), (unsigned)intmask);
2961 sdhci_dumpregs(host);
2962
2963 return;
2964 }
2965
2966 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2967 host->data->error = -ETIMEDOUT;
2968 else if (intmask & SDHCI_INT_DATA_END_BIT)
2969 host->data->error = -EILSEQ;
2970 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2971 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2972 != MMC_BUS_TEST_R)
2973 host->data->error = -EILSEQ;
2974 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2975 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
2976 intmask);
2977 sdhci_adma_show_error(host);
2978 host->data->error = -EIO;
2979 if (host->ops->adma_workaround)
2980 host->ops->adma_workaround(host, intmask);
2981 }
2982
2983 if (host->data->error)
2984 sdhci_finish_data(host);
2985 else {
2986 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2987 sdhci_transfer_pio(host);
2988
2989 /*
2990 * We currently don't do anything fancy with DMA
2991 * boundaries, but as we can't disable the feature
2992 * we need to at least restart the transfer.
2993 *
2994 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2995 * should return a valid address to continue from, but as
2996 * some controllers are faulty, don't trust them.
2997 */
2998 if (intmask & SDHCI_INT_DMA_END) {
2999 dma_addr_t dmastart, dmanow;
3000
3001 dmastart = sdhci_sdma_address(host);
3002 dmanow = dmastart + host->data->bytes_xfered;
3003 /*
3004 * Force update to the next DMA block boundary.
3005 */
3006 dmanow = (dmanow &
3007 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3008 SDHCI_DEFAULT_BOUNDARY_SIZE;
3009 host->data->bytes_xfered = dmanow - dmastart;
3010 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3011 &dmastart, host->data->bytes_xfered, &dmanow);
3012 sdhci_set_sdma_addr(host, dmanow);
3013 }
3014
3015 if (intmask & SDHCI_INT_DATA_END) {
3016 if (host->cmd == host->data_cmd) {
3017 /*
3018 * Data managed to finish before the
3019 * command completed. Make sure we do
3020 * things in the proper order.
3021 */
3022 host->data_early = 1;
3023 } else {
3024 sdhci_finish_data(host);
3025 }
3026 }
3027 }
3028}
3029
3030static inline bool sdhci_defer_done(struct sdhci_host *host,
3031 struct mmc_request *mrq)
3032{
3033 struct mmc_data *data = mrq->data;
3034
3035 return host->pending_reset ||
3036 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3037 data->host_cookie == COOKIE_MAPPED);
3038}
3039
3040static irqreturn_t sdhci_irq(int irq, void *dev_id)
3041{
3042 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3043 irqreturn_t result = IRQ_NONE;
3044 struct sdhci_host *host = dev_id;
3045 u32 intmask, mask, unexpected = 0;
3046 int max_loops = 16;
3047 int i;
3048
3049 spin_lock(&host->lock);
3050
3051 if (host->runtime_suspended) {
3052 spin_unlock(&host->lock);
3053 return IRQ_NONE;
3054 }
3055
3056 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3057 if (!intmask || intmask == 0xffffffff) {
3058 result = IRQ_NONE;
3059 goto out;
3060 }
3061
3062 do {
3063 DBG("IRQ status 0x%08x\n", intmask);
3064
3065 if (host->ops->irq) {
3066 intmask = host->ops->irq(host, intmask);
3067 if (!intmask)
3068 goto cont;
3069 }
3070
3071 /* Clear selected interrupts. */
3072 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3073 SDHCI_INT_BUS_POWER);
3074 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3075
3076 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3077 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3078 SDHCI_CARD_PRESENT;
3079
3080 /*
3081 * There is a observation on i.mx esdhc. INSERT
3082 * bit will be immediately set again when it gets
3083 * cleared, if a card is inserted. We have to mask
3084 * the irq to prevent interrupt storm which will
3085 * freeze the system. And the REMOVE gets the
3086 * same situation.
3087 *
3088 * More testing are needed here to ensure it works
3089 * for other platforms though.
3090 */
3091 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3092 SDHCI_INT_CARD_REMOVE);
3093 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3094 SDHCI_INT_CARD_INSERT;
3095 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3096 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3097
3098 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3099 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3100
3101 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3102 SDHCI_INT_CARD_REMOVE);
3103 result = IRQ_WAKE_THREAD;
3104 }
3105
3106 if (intmask & SDHCI_INT_CMD_MASK)
3107 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3108
3109 if (intmask & SDHCI_INT_DATA_MASK)
3110 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3111
3112 if (intmask & SDHCI_INT_BUS_POWER)
3113 pr_err("%s: Card is consuming too much power!\n",
3114 mmc_hostname(host->mmc));
3115
3116 if (intmask & SDHCI_INT_RETUNE)
3117 mmc_retune_needed(host->mmc);
3118
3119 if ((intmask & SDHCI_INT_CARD_INT) &&
3120 (host->ier & SDHCI_INT_CARD_INT)) {
3121 sdhci_enable_sdio_irq_nolock(host, false);
3122 sdio_signal_irq(host->mmc);
3123 }
3124
3125 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3126 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3127 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3128 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3129
3130 if (intmask) {
3131 unexpected |= intmask;
3132 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3133 }
3134cont:
3135 if (result == IRQ_NONE)
3136 result = IRQ_HANDLED;
3137
3138 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3139 } while (intmask && --max_loops);
3140
3141 /* Determine if mrqs can be completed immediately */
3142 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3143 struct mmc_request *mrq = host->mrqs_done[i];
3144
3145 if (!mrq)
3146 continue;
3147
3148 if (sdhci_defer_done(host, mrq)) {
3149 result = IRQ_WAKE_THREAD;
3150 } else {
3151 mrqs_done[i] = mrq;
3152 host->mrqs_done[i] = NULL;
3153 }
3154 }
3155out:
3156 spin_unlock(&host->lock);
3157
3158 /* Process mrqs ready for immediate completion */
3159 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3160 if (mrqs_done[i])
3161 mmc_request_done(host->mmc, mrqs_done[i]);
3162 }
3163
3164 if (unexpected) {
3165 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3166 mmc_hostname(host->mmc), unexpected);
3167 sdhci_dumpregs(host);
3168 }
3169
3170 return result;
3171}
3172
3173static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3174{
3175 struct sdhci_host *host = dev_id;
3176 unsigned long flags;
3177 u32 isr;
3178
3179 while (!sdhci_request_done(host))
3180 ;
3181
3182 spin_lock_irqsave(&host->lock, flags);
3183 isr = host->thread_isr;
3184 host->thread_isr = 0;
3185 spin_unlock_irqrestore(&host->lock, flags);
3186
3187 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3188 struct mmc_host *mmc = host->mmc;
3189
3190 mmc->ops->card_event(mmc);
3191 mmc_detect_change(mmc, msecs_to_jiffies(200));
3192 }
3193
3194 return IRQ_HANDLED;
3195}
3196
3197/*****************************************************************************\
3198 * *
3199 * Suspend/resume *
3200 * *
3201\*****************************************************************************/
3202
3203#ifdef CONFIG_PM
3204
3205static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3206{
3207 return mmc_card_is_removable(host->mmc) &&
3208 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3209 !mmc_can_gpio_cd(host->mmc);
3210}
3211
3212/*
3213 * To enable wakeup events, the corresponding events have to be enabled in
3214 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3215 * Table' in the SD Host Controller Standard Specification.
3216 * It is useless to restore SDHCI_INT_ENABLE state in
3217 * sdhci_disable_irq_wakeups() since it will be set by
3218 * sdhci_enable_card_detection() or sdhci_init().
3219 */
3220static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3221{
3222 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3223 SDHCI_WAKE_ON_INT;
3224 u32 irq_val = 0;
3225 u8 wake_val = 0;
3226 u8 val;
3227
3228 if (sdhci_cd_irq_can_wakeup(host)) {
3229 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3230 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3231 }
3232
3233 if (mmc_card_wake_sdio_irq(host->mmc)) {
3234 wake_val |= SDHCI_WAKE_ON_INT;
3235 irq_val |= SDHCI_INT_CARD_INT;
3236 }
3237
3238 if (!irq_val)
3239 return false;
3240
3241 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3242 val &= ~mask;
3243 val |= wake_val;
3244 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3245
3246 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3247
3248 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3249
3250 return host->irq_wake_enabled;
3251}
3252
3253static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3254{
3255 u8 val;
3256 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3257 | SDHCI_WAKE_ON_INT;
3258
3259 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3260 val &= ~mask;
3261 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3262
3263 disable_irq_wake(host->irq);
3264
3265 host->irq_wake_enabled = false;
3266}
3267
3268int sdhci_suspend_host(struct sdhci_host *host)
3269{
3270 sdhci_disable_card_detection(host);
3271
3272 mmc_retune_timer_stop(host->mmc);
3273
3274 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3275 !sdhci_enable_irq_wakeups(host)) {
3276 host->ier = 0;
3277 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3278 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3279 free_irq(host->irq, host);
3280 }
3281
3282 return 0;
3283}
3284
3285EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3286
3287int sdhci_resume_host(struct sdhci_host *host)
3288{
3289 struct mmc_host *mmc = host->mmc;
3290 int ret = 0;
3291
3292 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3293 if (host->ops->enable_dma)
3294 host->ops->enable_dma(host);
3295 }
3296
3297 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3298 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3299 /* Card keeps power but host controller does not */
3300 sdhci_init(host, 0);
3301 host->pwr = 0;
3302 host->clock = 0;
3303 mmc->ops->set_ios(mmc, &mmc->ios);
3304 } else {
3305 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3306 }
3307
3308 if (host->irq_wake_enabled) {
3309 sdhci_disable_irq_wakeups(host);
3310 } else {
3311 ret = request_threaded_irq(host->irq, sdhci_irq,
3312 sdhci_thread_irq, IRQF_SHARED,
3313 mmc_hostname(host->mmc), host);
3314 if (ret)
3315 return ret;
3316 }
3317
3318 sdhci_enable_card_detection(host);
3319
3320 return ret;
3321}
3322
3323EXPORT_SYMBOL_GPL(sdhci_resume_host);
3324
3325int sdhci_runtime_suspend_host(struct sdhci_host *host)
3326{
3327 unsigned long flags;
3328
3329 mmc_retune_timer_stop(host->mmc);
3330
3331 spin_lock_irqsave(&host->lock, flags);
3332 host->ier &= SDHCI_INT_CARD_INT;
3333 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3334 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3335 spin_unlock_irqrestore(&host->lock, flags);
3336
3337 synchronize_hardirq(host->irq);
3338
3339 spin_lock_irqsave(&host->lock, flags);
3340 host->runtime_suspended = true;
3341 spin_unlock_irqrestore(&host->lock, flags);
3342
3343 return 0;
3344}
3345EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3346
3347int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3348{
3349 struct mmc_host *mmc = host->mmc;
3350 unsigned long flags;
3351 int host_flags = host->flags;
3352
3353 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3354 if (host->ops->enable_dma)
3355 host->ops->enable_dma(host);
3356 }
3357
3358 sdhci_init(host, soft_reset);
3359
3360 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3361 mmc->ios.power_mode != MMC_POWER_OFF) {
3362 /* Force clock and power re-program */
3363 host->pwr = 0;
3364 host->clock = 0;
3365 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3366 mmc->ops->set_ios(mmc, &mmc->ios);
3367
3368 if ((host_flags & SDHCI_PV_ENABLED) &&
3369 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3370 spin_lock_irqsave(&host->lock, flags);
3371 sdhci_enable_preset_value(host, true);
3372 spin_unlock_irqrestore(&host->lock, flags);
3373 }
3374
3375 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3376 mmc->ops->hs400_enhanced_strobe)
3377 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3378 }
3379
3380 spin_lock_irqsave(&host->lock, flags);
3381
3382 host->runtime_suspended = false;
3383
3384 /* Enable SDIO IRQ */
3385 if (sdio_irq_claimed(mmc))
3386 sdhci_enable_sdio_irq_nolock(host, true);
3387
3388 /* Enable Card Detection */
3389 sdhci_enable_card_detection(host);
3390
3391 spin_unlock_irqrestore(&host->lock, flags);
3392
3393 return 0;
3394}
3395EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3396
3397#endif /* CONFIG_PM */
3398
3399/*****************************************************************************\
3400 * *
3401 * Command Queue Engine (CQE) helpers *
3402 * *
3403\*****************************************************************************/
3404
3405void sdhci_cqe_enable(struct mmc_host *mmc)
3406{
3407 struct sdhci_host *host = mmc_priv(mmc);
3408 unsigned long flags;
3409 u8 ctrl;
3410
3411 spin_lock_irqsave(&host->lock, flags);
3412
3413 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3414 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3415 /*
3416 * Host from V4.10 supports ADMA3 DMA type.
3417 * ADMA3 performs integrated descriptor which is more suitable
3418 * for cmd queuing to fetch both command and transfer descriptors.
3419 */
3420 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3421 ctrl |= SDHCI_CTRL_ADMA3;
3422 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3423 ctrl |= SDHCI_CTRL_ADMA64;
3424 else
3425 ctrl |= SDHCI_CTRL_ADMA32;
3426 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3427
3428 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3429 SDHCI_BLOCK_SIZE);
3430
3431 /* Set maximum timeout */
3432 sdhci_set_timeout(host, NULL);
3433
3434 host->ier = host->cqe_ier;
3435
3436 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3437 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3438
3439 host->cqe_on = true;
3440
3441 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3442 mmc_hostname(mmc), host->ier,
3443 sdhci_readl(host, SDHCI_INT_STATUS));
3444
3445 spin_unlock_irqrestore(&host->lock, flags);
3446}
3447EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3448
3449void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3450{
3451 struct sdhci_host *host = mmc_priv(mmc);
3452 unsigned long flags;
3453
3454 spin_lock_irqsave(&host->lock, flags);
3455
3456 sdhci_set_default_irqs(host);
3457
3458 host->cqe_on = false;
3459
3460 if (recovery) {
3461 sdhci_do_reset(host, SDHCI_RESET_CMD);
3462 sdhci_do_reset(host, SDHCI_RESET_DATA);
3463 }
3464
3465 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3466 mmc_hostname(mmc), host->ier,
3467 sdhci_readl(host, SDHCI_INT_STATUS));
3468
3469 spin_unlock_irqrestore(&host->lock, flags);
3470}
3471EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3472
3473bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3474 int *data_error)
3475{
3476 u32 mask;
3477
3478 if (!host->cqe_on)
3479 return false;
3480
3481 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3482 *cmd_error = -EILSEQ;
3483 else if (intmask & SDHCI_INT_TIMEOUT)
3484 *cmd_error = -ETIMEDOUT;
3485 else
3486 *cmd_error = 0;
3487
3488 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3489 *data_error = -EILSEQ;
3490 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3491 *data_error = -ETIMEDOUT;
3492 else if (intmask & SDHCI_INT_ADMA_ERROR)
3493 *data_error = -EIO;
3494 else
3495 *data_error = 0;
3496
3497 /* Clear selected interrupts. */
3498 mask = intmask & host->cqe_ier;
3499 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3500
3501 if (intmask & SDHCI_INT_BUS_POWER)
3502 pr_err("%s: Card is consuming too much power!\n",
3503 mmc_hostname(host->mmc));
3504
3505 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3506 if (intmask) {
3507 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3508 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3509 mmc_hostname(host->mmc), intmask);
3510 sdhci_dumpregs(host);
3511 }
3512
3513 return true;
3514}
3515EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3516
3517/*****************************************************************************\
3518 * *
3519 * Device allocation/registration *
3520 * *
3521\*****************************************************************************/
3522
3523struct sdhci_host *sdhci_alloc_host(struct device *dev,
3524 size_t priv_size)
3525{
3526 struct mmc_host *mmc;
3527 struct sdhci_host *host;
3528
3529 WARN_ON(dev == NULL);
3530
3531 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3532 if (!mmc)
3533 return ERR_PTR(-ENOMEM);
3534
3535 host = mmc_priv(mmc);
3536 host->mmc = mmc;
3537 host->mmc_host_ops = sdhci_ops;
3538 mmc->ops = &host->mmc_host_ops;
3539
3540 host->flags = SDHCI_SIGNALING_330;
3541
3542 host->cqe_ier = SDHCI_CQE_INT_MASK;
3543 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3544
3545 host->tuning_delay = -1;
3546 host->tuning_loop_count = MAX_TUNING_LOOP;
3547
3548 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3549
3550 /*
3551 * The DMA table descriptor count is calculated as the maximum
3552 * number of segments times 2, to allow for an alignment
3553 * descriptor for each segment, plus 1 for a nop end descriptor.
3554 */
3555 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3556
3557 return host;
3558}
3559
3560EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3561
3562static int sdhci_set_dma_mask(struct sdhci_host *host)
3563{
3564 struct mmc_host *mmc = host->mmc;
3565 struct device *dev = mmc_dev(mmc);
3566 int ret = -EINVAL;
3567
3568 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3569 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3570
3571 /* Try 64-bit mask if hardware is capable of it */
3572 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3573 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3574 if (ret) {
3575 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3576 mmc_hostname(mmc));
3577 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3578 }
3579 }
3580
3581 /* 32-bit mask as default & fallback */
3582 if (ret) {
3583 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3584 if (ret)
3585 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3586 mmc_hostname(mmc));
3587 }
3588
3589 return ret;
3590}
3591
3592void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3593 const u32 *caps, const u32 *caps1)
3594{
3595 u16 v;
3596 u64 dt_caps_mask = 0;
3597 u64 dt_caps = 0;
3598
3599 if (host->read_caps)
3600 return;
3601
3602 host->read_caps = true;
3603
3604 if (debug_quirks)
3605 host->quirks = debug_quirks;
3606
3607 if (debug_quirks2)
3608 host->quirks2 = debug_quirks2;
3609
3610 sdhci_do_reset(host, SDHCI_RESET_ALL);
3611
3612 if (host->v4_mode)
3613 sdhci_do_enable_v4_mode(host);
3614
3615 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3616 "sdhci-caps-mask", &dt_caps_mask);
3617 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3618 "sdhci-caps", &dt_caps);
3619
3620 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3621 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3622
3623 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3624 return;
3625
3626 if (caps) {
3627 host->caps = *caps;
3628 } else {
3629 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3630 host->caps &= ~lower_32_bits(dt_caps_mask);
3631 host->caps |= lower_32_bits(dt_caps);
3632 }
3633
3634 if (host->version < SDHCI_SPEC_300)
3635 return;
3636
3637 if (caps1) {
3638 host->caps1 = *caps1;
3639 } else {
3640 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3641 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3642 host->caps1 |= upper_32_bits(dt_caps);
3643 }
3644}
3645EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3646
3647static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3648{
3649 struct mmc_host *mmc = host->mmc;
3650 unsigned int max_blocks;
3651 unsigned int bounce_size;
3652 int ret;
3653
3654 /*
3655 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3656 * has diminishing returns, this is probably because SD/MMC
3657 * cards are usually optimized to handle this size of requests.
3658 */
3659 bounce_size = SZ_64K;
3660 /*
3661 * Adjust downwards to maximum request size if this is less
3662 * than our segment size, else hammer down the maximum
3663 * request size to the maximum buffer size.
3664 */
3665 if (mmc->max_req_size < bounce_size)
3666 bounce_size = mmc->max_req_size;
3667 max_blocks = bounce_size / 512;
3668
3669 /*
3670 * When we just support one segment, we can get significant
3671 * speedups by the help of a bounce buffer to group scattered
3672 * reads/writes together.
3673 */
3674 host->bounce_buffer = devm_kmalloc(mmc->parent,
3675 bounce_size,
3676 GFP_KERNEL);
3677 if (!host->bounce_buffer) {
3678 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3679 mmc_hostname(mmc),
3680 bounce_size);
3681 /*
3682 * Exiting with zero here makes sure we proceed with
3683 * mmc->max_segs == 1.
3684 */
3685 return;
3686 }
3687
3688 host->bounce_addr = dma_map_single(mmc->parent,
3689 host->bounce_buffer,
3690 bounce_size,
3691 DMA_BIDIRECTIONAL);
3692 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3693 if (ret)
3694 /* Again fall back to max_segs == 1 */
3695 return;
3696 host->bounce_buffer_size = bounce_size;
3697
3698 /* Lie about this since we're bouncing */
3699 mmc->max_segs = max_blocks;
3700 mmc->max_seg_size = bounce_size;
3701 mmc->max_req_size = bounce_size;
3702
3703 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3704 mmc_hostname(mmc), max_blocks, bounce_size);
3705}
3706
3707static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
3708{
3709 /*
3710 * According to SD Host Controller spec v4.10, bit[27] added from
3711 * version 4.10 in Capabilities Register is used as 64-bit System
3712 * Address support for V4 mode.
3713 */
3714 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
3715 return host->caps & SDHCI_CAN_64BIT_V4;
3716
3717 return host->caps & SDHCI_CAN_64BIT;
3718}
3719
3720int sdhci_setup_host(struct sdhci_host *host)
3721{
3722 struct mmc_host *mmc;
3723 u32 max_current_caps;
3724 unsigned int ocr_avail;
3725 unsigned int override_timeout_clk;
3726 u32 max_clk;
3727 int ret;
3728
3729 WARN_ON(host == NULL);
3730 if (host == NULL)
3731 return -EINVAL;
3732
3733 mmc = host->mmc;
3734
3735 /*
3736 * If there are external regulators, get them. Note this must be done
3737 * early before resetting the host and reading the capabilities so that
3738 * the host can take the appropriate action if regulators are not
3739 * available.
3740 */
3741 ret = mmc_regulator_get_supply(mmc);
3742 if (ret)
3743 return ret;
3744
3745 DBG("Version: 0x%08x | Present: 0x%08x\n",
3746 sdhci_readw(host, SDHCI_HOST_VERSION),
3747 sdhci_readl(host, SDHCI_PRESENT_STATE));
3748 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3749 sdhci_readl(host, SDHCI_CAPABILITIES),
3750 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3751
3752 sdhci_read_caps(host);
3753
3754 override_timeout_clk = host->timeout_clk;
3755
3756 if (host->version > SDHCI_SPEC_420) {
3757 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3758 mmc_hostname(mmc), host->version);
3759 }
3760
3761 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3762 host->flags |= SDHCI_USE_SDMA;
3763 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3764 DBG("Controller doesn't have SDMA capability\n");
3765 else
3766 host->flags |= SDHCI_USE_SDMA;
3767
3768 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3769 (host->flags & SDHCI_USE_SDMA)) {
3770 DBG("Disabling DMA as it is marked broken\n");
3771 host->flags &= ~SDHCI_USE_SDMA;
3772 }
3773
3774 if ((host->version >= SDHCI_SPEC_200) &&
3775 (host->caps & SDHCI_CAN_DO_ADMA2))
3776 host->flags |= SDHCI_USE_ADMA;
3777
3778 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3779 (host->flags & SDHCI_USE_ADMA)) {
3780 DBG("Disabling ADMA as it is marked broken\n");
3781 host->flags &= ~SDHCI_USE_ADMA;
3782 }
3783
3784 if (sdhci_can_64bit_dma(host))
3785 host->flags |= SDHCI_USE_64_BIT_DMA;
3786
3787 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3788 if (host->ops->set_dma_mask)
3789 ret = host->ops->set_dma_mask(host);
3790 else
3791 ret = sdhci_set_dma_mask(host);
3792
3793 if (!ret && host->ops->enable_dma)
3794 ret = host->ops->enable_dma(host);
3795
3796 if (ret) {
3797 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3798 mmc_hostname(mmc));
3799 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3800
3801 ret = 0;
3802 }
3803 }
3804
3805 /* SDMA does not support 64-bit DMA if v4 mode not set */
3806 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
3807 host->flags &= ~SDHCI_USE_SDMA;
3808
3809 if (host->flags & SDHCI_USE_ADMA) {
3810 dma_addr_t dma;
3811 void *buf;
3812
3813 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3814 host->adma_table_sz = host->adma_table_cnt *
3815 SDHCI_ADMA2_64_DESC_SZ(host);
3816 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
3817 } else {
3818 host->adma_table_sz = host->adma_table_cnt *
3819 SDHCI_ADMA2_32_DESC_SZ;
3820 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3821 }
3822
3823 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3824 /*
3825 * Use zalloc to zero the reserved high 32-bits of 128-bit
3826 * descriptors so that they never need to be written.
3827 */
3828 buf = dma_alloc_coherent(mmc_dev(mmc),
3829 host->align_buffer_sz + host->adma_table_sz,
3830 &dma, GFP_KERNEL);
3831 if (!buf) {
3832 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3833 mmc_hostname(mmc));
3834 host->flags &= ~SDHCI_USE_ADMA;
3835 } else if ((dma + host->align_buffer_sz) &
3836 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3837 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3838 mmc_hostname(mmc));
3839 host->flags &= ~SDHCI_USE_ADMA;
3840 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3841 host->adma_table_sz, buf, dma);
3842 } else {
3843 host->align_buffer = buf;
3844 host->align_addr = dma;
3845
3846 host->adma_table = buf + host->align_buffer_sz;
3847 host->adma_addr = dma + host->align_buffer_sz;
3848 }
3849 }
3850
3851 /*
3852 * If we use DMA, then it's up to the caller to set the DMA
3853 * mask, but PIO does not need the hw shim so we set a new
3854 * mask here in that case.
3855 */
3856 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3857 host->dma_mask = DMA_BIT_MASK(64);
3858 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3859 }
3860
3861 if (host->version >= SDHCI_SPEC_300)
3862 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3863 >> SDHCI_CLOCK_BASE_SHIFT;
3864 else
3865 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3866 >> SDHCI_CLOCK_BASE_SHIFT;
3867
3868 host->max_clk *= 1000000;
3869 if (host->max_clk == 0 || host->quirks &
3870 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3871 if (!host->ops->get_max_clock) {
3872 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3873 mmc_hostname(mmc));
3874 ret = -ENODEV;
3875 goto undma;
3876 }
3877 host->max_clk = host->ops->get_max_clock(host);
3878 }
3879
3880 /*
3881 * In case of Host Controller v3.00, find out whether clock
3882 * multiplier is supported.
3883 */
3884 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3885 SDHCI_CLOCK_MUL_SHIFT;
3886
3887 /*
3888 * In case the value in Clock Multiplier is 0, then programmable
3889 * clock mode is not supported, otherwise the actual clock
3890 * multiplier is one more than the value of Clock Multiplier
3891 * in the Capabilities Register.
3892 */
3893 if (host->clk_mul)
3894 host->clk_mul += 1;
3895
3896 /*
3897 * Set host parameters.
3898 */
3899 max_clk = host->max_clk;
3900
3901 if (host->ops->get_min_clock)
3902 mmc->f_min = host->ops->get_min_clock(host);
3903 else if (host->version >= SDHCI_SPEC_300) {
3904 if (host->clk_mul) {
3905 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3906 max_clk = host->max_clk * host->clk_mul;
3907 } else
3908 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3909 } else
3910 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3911
3912 if (!mmc->f_max || mmc->f_max > max_clk)
3913 mmc->f_max = max_clk;
3914
3915 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3916 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3917 SDHCI_TIMEOUT_CLK_SHIFT;
3918
3919 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3920 host->timeout_clk *= 1000;
3921
3922 if (host->timeout_clk == 0) {
3923 if (!host->ops->get_timeout_clock) {
3924 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3925 mmc_hostname(mmc));
3926 ret = -ENODEV;
3927 goto undma;
3928 }
3929
3930 host->timeout_clk =
3931 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3932 1000);
3933 }
3934
3935 if (override_timeout_clk)
3936 host->timeout_clk = override_timeout_clk;
3937
3938 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3939 host->ops->get_max_timeout_count(host) : 1 << 27;
3940 mmc->max_busy_timeout /= host->timeout_clk;
3941 }
3942
3943 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
3944 !host->ops->get_max_timeout_count)
3945 mmc->max_busy_timeout = 0;
3946
3947 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3948 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3949
3950 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3951 host->flags |= SDHCI_AUTO_CMD12;
3952
3953 /*
3954 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
3955 * For v4 mode, SDMA may use Auto-CMD23 as well.
3956 */
3957 if ((host->version >= SDHCI_SPEC_300) &&
3958 ((host->flags & SDHCI_USE_ADMA) ||
3959 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
3960 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3961 host->flags |= SDHCI_AUTO_CMD23;
3962 DBG("Auto-CMD23 available\n");
3963 } else {
3964 DBG("Auto-CMD23 unavailable\n");
3965 }
3966
3967 /*
3968 * A controller may support 8-bit width, but the board itself
3969 * might not have the pins brought out. Boards that support
3970 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3971 * their platform code before calling sdhci_add_host(), and we
3972 * won't assume 8-bit width for hosts without that CAP.
3973 */
3974 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3975 mmc->caps |= MMC_CAP_4_BIT_DATA;
3976
3977 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3978 mmc->caps &= ~MMC_CAP_CMD23;
3979
3980 if (host->caps & SDHCI_CAN_DO_HISPD)
3981 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3982
3983 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3984 mmc_card_is_removable(mmc) &&
3985 mmc_gpio_get_cd(host->mmc) < 0)
3986 mmc->caps |= MMC_CAP_NEEDS_POLL;
3987
3988 if (!IS_ERR(mmc->supply.vqmmc)) {
3989 ret = regulator_enable(mmc->supply.vqmmc);
3990
3991 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3992 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3993 1950000))
3994 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3995 SDHCI_SUPPORT_SDR50 |
3996 SDHCI_SUPPORT_DDR50);
3997
3998 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3999 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4000 3600000))
4001 host->flags &= ~SDHCI_SIGNALING_330;
4002
4003 if (ret) {
4004 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4005 mmc_hostname(mmc), ret);
4006 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4007 }
4008 }
4009
4010 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4011 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4012 SDHCI_SUPPORT_DDR50);
4013 /*
4014 * The SDHCI controller in a SoC might support HS200/HS400
4015 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4016 * but if the board is modeled such that the IO lines are not
4017 * connected to 1.8v then HS200/HS400 cannot be supported.
4018 * Disable HS200/HS400 if the board does not have 1.8v connected
4019 * to the IO lines. (Applicable for other modes in 1.8v)
4020 */
4021 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4022 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4023 }
4024
4025 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4026 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4027 SDHCI_SUPPORT_DDR50))
4028 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4029
4030 /* SDR104 supports also implies SDR50 support */
4031 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4032 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4033 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4034 * field can be promoted to support HS200.
4035 */
4036 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4037 mmc->caps2 |= MMC_CAP2_HS200;
4038 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4039 mmc->caps |= MMC_CAP_UHS_SDR50;
4040 }
4041
4042 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4043 (host->caps1 & SDHCI_SUPPORT_HS400))
4044 mmc->caps2 |= MMC_CAP2_HS400;
4045
4046 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4047 (IS_ERR(mmc->supply.vqmmc) ||
4048 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4049 1300000)))
4050 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4051
4052 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4053 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4054 mmc->caps |= MMC_CAP_UHS_DDR50;
4055
4056 /* Does the host need tuning for SDR50? */
4057 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4058 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4059
4060 /* Driver Type(s) (A, C, D) supported by the host */
4061 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4062 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4063 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4064 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4065 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4066 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4067
4068 /* Initial value for re-tuning timer count */
4069 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
4070 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
4071
4072 /*
4073 * In case Re-tuning Timer is not disabled, the actual value of
4074 * re-tuning timer will be 2 ^ (n - 1).
4075 */
4076 if (host->tuning_count)
4077 host->tuning_count = 1 << (host->tuning_count - 1);
4078
4079 /* Re-tuning mode supported by the Host Controller */
4080 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
4081 SDHCI_RETUNING_MODE_SHIFT;
4082
4083 ocr_avail = 0;
4084
4085 /*
4086 * According to SD Host Controller spec v3.00, if the Host System
4087 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4088 * the value is meaningful only if Voltage Support in the Capabilities
4089 * register is set. The actual current value is 4 times the register
4090 * value.
4091 */
4092 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4093 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4094 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4095 if (curr > 0) {
4096
4097 /* convert to SDHCI_MAX_CURRENT format */
4098 curr = curr/1000; /* convert to mA */
4099 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4100
4101 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4102 max_current_caps =
4103 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
4104 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
4105 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
4106 }
4107 }
4108
4109 if (host->caps & SDHCI_CAN_VDD_330) {
4110 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4111
4112 mmc->max_current_330 = ((max_current_caps &
4113 SDHCI_MAX_CURRENT_330_MASK) >>
4114 SDHCI_MAX_CURRENT_330_SHIFT) *
4115 SDHCI_MAX_CURRENT_MULTIPLIER;
4116 }
4117 if (host->caps & SDHCI_CAN_VDD_300) {
4118 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4119
4120 mmc->max_current_300 = ((max_current_caps &
4121 SDHCI_MAX_CURRENT_300_MASK) >>
4122 SDHCI_MAX_CURRENT_300_SHIFT) *
4123 SDHCI_MAX_CURRENT_MULTIPLIER;
4124 }
4125 if (host->caps & SDHCI_CAN_VDD_180) {
4126 ocr_avail |= MMC_VDD_165_195;
4127
4128 mmc->max_current_180 = ((max_current_caps &
4129 SDHCI_MAX_CURRENT_180_MASK) >>
4130 SDHCI_MAX_CURRENT_180_SHIFT) *
4131 SDHCI_MAX_CURRENT_MULTIPLIER;
4132 }
4133
4134 /* If OCR set by host, use it instead. */
4135 if (host->ocr_mask)
4136 ocr_avail = host->ocr_mask;
4137
4138 /* If OCR set by external regulators, give it highest prio. */
4139 if (mmc->ocr_avail)
4140 ocr_avail = mmc->ocr_avail;
4141
4142 mmc->ocr_avail = ocr_avail;
4143 mmc->ocr_avail_sdio = ocr_avail;
4144 if (host->ocr_avail_sdio)
4145 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4146 mmc->ocr_avail_sd = ocr_avail;
4147 if (host->ocr_avail_sd)
4148 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4149 else /* normal SD controllers don't support 1.8V */
4150 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4151 mmc->ocr_avail_mmc = ocr_avail;
4152 if (host->ocr_avail_mmc)
4153 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4154
4155 if (mmc->ocr_avail == 0) {
4156 pr_err("%s: Hardware doesn't report any support voltages.\n",
4157 mmc_hostname(mmc));
4158 ret = -ENODEV;
4159 goto unreg;
4160 }
4161
4162 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4163 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4164 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4165 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4166 host->flags |= SDHCI_SIGNALING_180;
4167
4168 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4169 host->flags |= SDHCI_SIGNALING_120;
4170
4171 spin_lock_init(&host->lock);
4172
4173 /*
4174 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4175 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4176 * is less anyway.
4177 */
4178 mmc->max_req_size = 524288;
4179
4180 /*
4181 * Maximum number of segments. Depends on if the hardware
4182 * can do scatter/gather or not.
4183 */
4184 if (host->flags & SDHCI_USE_ADMA) {
4185 mmc->max_segs = SDHCI_MAX_SEGS;
4186 } else if (host->flags & SDHCI_USE_SDMA) {
4187 mmc->max_segs = 1;
4188 if (swiotlb_max_segment()) {
4189 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4190 IO_TLB_SEGSIZE;
4191 mmc->max_req_size = min(mmc->max_req_size,
4192 max_req_size);
4193 }
4194 } else { /* PIO */
4195 mmc->max_segs = SDHCI_MAX_SEGS;
4196 }
4197
4198 /*
4199 * Maximum segment size. Could be one segment with the maximum number
4200 * of bytes. When doing hardware scatter/gather, each entry cannot
4201 * be larger than 64 KiB though.
4202 */
4203 if (host->flags & SDHCI_USE_ADMA) {
4204 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4205 mmc->max_seg_size = 65535;
4206 else
4207 mmc->max_seg_size = 65536;
4208 } else {
4209 mmc->max_seg_size = mmc->max_req_size;
4210 }
4211
4212 /*
4213 * Maximum block size. This varies from controller to controller and
4214 * is specified in the capabilities register.
4215 */
4216 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4217 mmc->max_blk_size = 2;
4218 } else {
4219 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4220 SDHCI_MAX_BLOCK_SHIFT;
4221 if (mmc->max_blk_size >= 3) {
4222 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4223 mmc_hostname(mmc));
4224 mmc->max_blk_size = 0;
4225 }
4226 }
4227
4228 mmc->max_blk_size = 512 << mmc->max_blk_size;
4229
4230 /*
4231 * Maximum block count.
4232 */
4233 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4234
4235 if (mmc->max_segs == 1)
4236 /* This may alter mmc->*_blk_* parameters */
4237 sdhci_allocate_bounce_buffer(host);
4238
4239 return 0;
4240
4241unreg:
4242 if (!IS_ERR(mmc->supply.vqmmc))
4243 regulator_disable(mmc->supply.vqmmc);
4244undma:
4245 if (host->align_buffer)
4246 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4247 host->adma_table_sz, host->align_buffer,
4248 host->align_addr);
4249 host->adma_table = NULL;
4250 host->align_buffer = NULL;
4251
4252 return ret;
4253}
4254EXPORT_SYMBOL_GPL(sdhci_setup_host);
4255
4256void sdhci_cleanup_host(struct sdhci_host *host)
4257{
4258 struct mmc_host *mmc = host->mmc;
4259
4260 if (!IS_ERR(mmc->supply.vqmmc))
4261 regulator_disable(mmc->supply.vqmmc);
4262
4263 if (host->align_buffer)
4264 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4265 host->adma_table_sz, host->align_buffer,
4266 host->align_addr);
4267 host->adma_table = NULL;
4268 host->align_buffer = NULL;
4269}
4270EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4271
4272int __sdhci_add_host(struct sdhci_host *host)
4273{
4274 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4275 struct mmc_host *mmc = host->mmc;
4276 int ret;
4277
4278 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4279 if (!host->complete_wq)
4280 return -ENOMEM;
4281
4282 INIT_WORK(&host->complete_work, sdhci_complete_work);
4283
4284 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4285 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4286
4287 init_waitqueue_head(&host->buf_ready_int);
4288
4289 sdhci_init(host, 0);
4290
4291 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4292 IRQF_SHARED, mmc_hostname(mmc), host);
4293 if (ret) {
4294 pr_err("%s: Failed to request IRQ %d: %d\n",
4295 mmc_hostname(mmc), host->irq, ret);
4296 goto unwq;
4297 }
4298
4299 ret = sdhci_led_register(host);
4300 if (ret) {
4301 pr_err("%s: Failed to register LED device: %d\n",
4302 mmc_hostname(mmc), ret);
4303 goto unirq;
4304 }
4305
4306 ret = mmc_add_host(mmc);
4307 if (ret)
4308 goto unled;
4309
4310 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4311 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4312 (host->flags & SDHCI_USE_ADMA) ?
4313 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4314 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4315
4316 sdhci_enable_card_detection(host);
4317
4318 return 0;
4319
4320unled:
4321 sdhci_led_unregister(host);
4322unirq:
4323 sdhci_do_reset(host, SDHCI_RESET_ALL);
4324 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4325 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4326 free_irq(host->irq, host);
4327unwq:
4328 destroy_workqueue(host->complete_wq);
4329
4330 return ret;
4331}
4332EXPORT_SYMBOL_GPL(__sdhci_add_host);
4333
4334int sdhci_add_host(struct sdhci_host *host)
4335{
4336 int ret;
4337
4338 ret = sdhci_setup_host(host);
4339 if (ret)
4340 return ret;
4341
4342 ret = __sdhci_add_host(host);
4343 if (ret)
4344 goto cleanup;
4345
4346 return 0;
4347
4348cleanup:
4349 sdhci_cleanup_host(host);
4350
4351 return ret;
4352}
4353EXPORT_SYMBOL_GPL(sdhci_add_host);
4354
4355void sdhci_remove_host(struct sdhci_host *host, int dead)
4356{
4357 struct mmc_host *mmc = host->mmc;
4358 unsigned long flags;
4359
4360 if (dead) {
4361 spin_lock_irqsave(&host->lock, flags);
4362
4363 host->flags |= SDHCI_DEVICE_DEAD;
4364
4365 if (sdhci_has_requests(host)) {
4366 pr_err("%s: Controller removed during "
4367 " transfer!\n", mmc_hostname(mmc));
4368 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4369 }
4370
4371 spin_unlock_irqrestore(&host->lock, flags);
4372 }
4373
4374 sdhci_disable_card_detection(host);
4375
4376 mmc_remove_host(mmc);
4377
4378 sdhci_led_unregister(host);
4379
4380 if (!dead)
4381 sdhci_do_reset(host, SDHCI_RESET_ALL);
4382
4383 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4384 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4385 free_irq(host->irq, host);
4386
4387 del_timer_sync(&host->timer);
4388 del_timer_sync(&host->data_timer);
4389
4390 destroy_workqueue(host->complete_wq);
4391
4392 if (!IS_ERR(mmc->supply.vqmmc))
4393 regulator_disable(mmc->supply.vqmmc);
4394
4395 if (host->align_buffer)
4396 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4397 host->adma_table_sz, host->align_buffer,
4398 host->align_addr);
4399
4400 host->adma_table = NULL;
4401 host->align_buffer = NULL;
4402}
4403
4404EXPORT_SYMBOL_GPL(sdhci_remove_host);
4405
4406void sdhci_free_host(struct sdhci_host *host)
4407{
4408 mmc_free_host(host->mmc);
4409}
4410
4411EXPORT_SYMBOL_GPL(sdhci_free_host);
4412
4413/*****************************************************************************\
4414 * *
4415 * Driver init/exit *
4416 * *
4417\*****************************************************************************/
4418
4419static int __init sdhci_drv_init(void)
4420{
4421 pr_info(DRIVER_NAME
4422 ": Secure Digital Host Controller Interface driver\n");
4423 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4424
4425 return 0;
4426}
4427
4428static void __exit sdhci_drv_exit(void)
4429{
4430}
4431
4432module_init(sdhci_drv_init);
4433module_exit(sdhci_drv_exit);
4434
4435module_param(debug_quirks, uint, 0444);
4436module_param(debug_quirks2, uint, 0444);
4437
4438MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4439MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4440MODULE_LICENSE("GPL");
4441
4442MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4443MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");