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1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/ktime.h>
18#include <linux/highmem.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/dma-mapping.h>
22#include <linux/slab.h>
23#include <linux/scatterlist.h>
24#include <linux/sizes.h>
25#include <linux/swiotlb.h>
26#include <linux/regulator/consumer.h>
27#include <linux/pm_runtime.h>
28#include <linux/of.h>
29
30#include <linux/leds.h>
31
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/card.h>
35#include <linux/mmc/sdio.h>
36#include <linux/mmc/slot-gpio.h>
37
38#include "sdhci.h"
39
40#define DRIVER_NAME "sdhci"
41
42#define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48#define MAX_TUNING_LOOP 40
49
50static unsigned int debug_quirks = 0;
51static unsigned int debug_quirks2;
52
53static void sdhci_finish_data(struct sdhci_host *);
54
55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57void sdhci_dumpregs(struct sdhci_host *host)
58{
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_ACMD12_ERR),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127{
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
129}
130
131static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
132{
133 u32 present;
134
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
137 return;
138
139 if (enable) {
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT;
142
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
145 } else {
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
147 }
148
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
151}
152
153static void sdhci_enable_card_detection(struct sdhci_host *host)
154{
155 sdhci_set_card_detection(host, true);
156}
157
158static void sdhci_disable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, false);
161}
162
163static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
164{
165 if (host->bus_on)
166 return;
167 host->bus_on = true;
168 pm_runtime_get_noresume(host->mmc->parent);
169}
170
171static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
172{
173 if (!host->bus_on)
174 return;
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
177}
178
179void sdhci_reset(struct sdhci_host *host, u8 mask)
180{
181 ktime_t timeout;
182
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184
185 if (mask & SDHCI_RESET_ALL) {
186 host->clock = 0;
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
190 }
191
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
194
195 /* hw clears the bit when it's done */
196 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 if (ktime_after(ktime_get(), timeout)) {
198 pr_err("%s: Reset 0x%x never completed.\n",
199 mmc_hostname(host->mmc), (int)mask);
200 sdhci_dumpregs(host);
201 return;
202 }
203 udelay(10);
204 }
205}
206EXPORT_SYMBOL_GPL(sdhci_reset);
207
208static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
209{
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 struct mmc_host *mmc = host->mmc;
212
213 if (!mmc->ops->get_cd(mmc))
214 return;
215 }
216
217 host->ops->reset(host, mask);
218
219 if (mask & SDHCI_RESET_ALL) {
220 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
221 if (host->ops->enable_dma)
222 host->ops->enable_dma(host);
223 }
224
225 /* Resetting the controller clears many */
226 host->preset_enabled = false;
227 }
228}
229
230static void sdhci_set_default_irqs(struct sdhci_host *host)
231{
232 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
233 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
234 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
235 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
236 SDHCI_INT_RESPONSE;
237
238 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
239 host->tuning_mode == SDHCI_TUNING_MODE_3)
240 host->ier |= SDHCI_INT_RETUNE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
244}
245
246static void sdhci_init(struct sdhci_host *host, int soft)
247{
248 struct mmc_host *mmc = host->mmc;
249
250 if (soft)
251 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
252 else
253 sdhci_do_reset(host, SDHCI_RESET_ALL);
254
255 sdhci_set_default_irqs(host);
256
257 host->cqe_on = false;
258
259 if (soft) {
260 /* force clock reconfiguration */
261 host->clock = 0;
262 mmc->ops->set_ios(mmc, &mmc->ios);
263 }
264}
265
266static void sdhci_reinit(struct sdhci_host *host)
267{
268 sdhci_init(host, 0);
269 sdhci_enable_card_detection(host);
270}
271
272static void __sdhci_led_activate(struct sdhci_host *host)
273{
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl |= SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279}
280
281static void __sdhci_led_deactivate(struct sdhci_host *host)
282{
283 u8 ctrl;
284
285 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
286 ctrl &= ~SDHCI_CTRL_LED;
287 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
288}
289
290#if IS_REACHABLE(CONFIG_LEDS_CLASS)
291static void sdhci_led_control(struct led_classdev *led,
292 enum led_brightness brightness)
293{
294 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
295 unsigned long flags;
296
297 spin_lock_irqsave(&host->lock, flags);
298
299 if (host->runtime_suspended)
300 goto out;
301
302 if (brightness == LED_OFF)
303 __sdhci_led_deactivate(host);
304 else
305 __sdhci_led_activate(host);
306out:
307 spin_unlock_irqrestore(&host->lock, flags);
308}
309
310static int sdhci_led_register(struct sdhci_host *host)
311{
312 struct mmc_host *mmc = host->mmc;
313
314 snprintf(host->led_name, sizeof(host->led_name),
315 "%s::", mmc_hostname(mmc));
316
317 host->led.name = host->led_name;
318 host->led.brightness = LED_OFF;
319 host->led.default_trigger = mmc_hostname(mmc);
320 host->led.brightness_set = sdhci_led_control;
321
322 return led_classdev_register(mmc_dev(mmc), &host->led);
323}
324
325static void sdhci_led_unregister(struct sdhci_host *host)
326{
327 led_classdev_unregister(&host->led);
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332}
333
334static inline void sdhci_led_deactivate(struct sdhci_host *host)
335{
336}
337
338#else
339
340static inline int sdhci_led_register(struct sdhci_host *host)
341{
342 return 0;
343}
344
345static inline void sdhci_led_unregister(struct sdhci_host *host)
346{
347}
348
349static inline void sdhci_led_activate(struct sdhci_host *host)
350{
351 __sdhci_led_activate(host);
352}
353
354static inline void sdhci_led_deactivate(struct sdhci_host *host)
355{
356 __sdhci_led_deactivate(host);
357}
358
359#endif
360
361/*****************************************************************************\
362 * *
363 * Core functions *
364 * *
365\*****************************************************************************/
366
367static void sdhci_read_block_pio(struct sdhci_host *host)
368{
369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 uninitialized_var(scratch);
372 u8 *buf;
373
374 DBG("PIO reading\n");
375
376 blksize = host->data->blksz;
377 chunk = 0;
378
379 local_irq_save(flags);
380
381 while (blksize) {
382 BUG_ON(!sg_miter_next(&host->sg_miter));
383
384 len = min(host->sg_miter.length, blksize);
385
386 blksize -= len;
387 host->sg_miter.consumed = len;
388
389 buf = host->sg_miter.addr;
390
391 while (len) {
392 if (chunk == 0) {
393 scratch = sdhci_readl(host, SDHCI_BUFFER);
394 chunk = 4;
395 }
396
397 *buf = scratch & 0xFF;
398
399 buf++;
400 scratch >>= 8;
401 chunk--;
402 len--;
403 }
404 }
405
406 sg_miter_stop(&host->sg_miter);
407
408 local_irq_restore(flags);
409}
410
411static void sdhci_write_block_pio(struct sdhci_host *host)
412{
413 unsigned long flags;
414 size_t blksize, len, chunk;
415 u32 scratch;
416 u8 *buf;
417
418 DBG("PIO writing\n");
419
420 blksize = host->data->blksz;
421 chunk = 0;
422 scratch = 0;
423
424 local_irq_save(flags);
425
426 while (blksize) {
427 BUG_ON(!sg_miter_next(&host->sg_miter));
428
429 len = min(host->sg_miter.length, blksize);
430
431 blksize -= len;
432 host->sg_miter.consumed = len;
433
434 buf = host->sg_miter.addr;
435
436 while (len) {
437 scratch |= (u32)*buf << (chunk * 8);
438
439 buf++;
440 chunk++;
441 len--;
442
443 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
444 sdhci_writel(host, scratch, SDHCI_BUFFER);
445 chunk = 0;
446 scratch = 0;
447 }
448 }
449 }
450
451 sg_miter_stop(&host->sg_miter);
452
453 local_irq_restore(flags);
454}
455
456static void sdhci_transfer_pio(struct sdhci_host *host)
457{
458 u32 mask;
459
460 if (host->blocks == 0)
461 return;
462
463 if (host->data->flags & MMC_DATA_READ)
464 mask = SDHCI_DATA_AVAILABLE;
465 else
466 mask = SDHCI_SPACE_AVAILABLE;
467
468 /*
469 * Some controllers (JMicron JMB38x) mess up the buffer bits
470 * for transfers < 4 bytes. As long as it is just one block,
471 * we can ignore the bits.
472 */
473 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
474 (host->data->blocks == 1))
475 mask = ~0;
476
477 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
478 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
479 udelay(100);
480
481 if (host->data->flags & MMC_DATA_READ)
482 sdhci_read_block_pio(host);
483 else
484 sdhci_write_block_pio(host);
485
486 host->blocks--;
487 if (host->blocks == 0)
488 break;
489 }
490
491 DBG("PIO transfer complete.\n");
492}
493
494static int sdhci_pre_dma_transfer(struct sdhci_host *host,
495 struct mmc_data *data, int cookie)
496{
497 int sg_count;
498
499 /*
500 * If the data buffers are already mapped, return the previous
501 * dma_map_sg() result.
502 */
503 if (data->host_cookie == COOKIE_PRE_MAPPED)
504 return data->sg_count;
505
506 /* Bounce write requests to the bounce buffer */
507 if (host->bounce_buffer) {
508 unsigned int length = data->blksz * data->blocks;
509
510 if (length > host->bounce_buffer_size) {
511 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
512 mmc_hostname(host->mmc), length,
513 host->bounce_buffer_size);
514 return -EIO;
515 }
516 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
517 /* Copy the data to the bounce buffer */
518 sg_copy_to_buffer(data->sg, data->sg_len,
519 host->bounce_buffer,
520 length);
521 }
522 /* Switch ownership to the DMA */
523 dma_sync_single_for_device(host->mmc->parent,
524 host->bounce_addr,
525 host->bounce_buffer_size,
526 mmc_get_dma_dir(data));
527 /* Just a dummy value */
528 sg_count = 1;
529 } else {
530 /* Just access the data directly from memory */
531 sg_count = dma_map_sg(mmc_dev(host->mmc),
532 data->sg, data->sg_len,
533 mmc_get_dma_dir(data));
534 }
535
536 if (sg_count == 0)
537 return -ENOSPC;
538
539 data->sg_count = sg_count;
540 data->host_cookie = cookie;
541
542 return sg_count;
543}
544
545static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
546{
547 local_irq_save(*flags);
548 return kmap_atomic(sg_page(sg)) + sg->offset;
549}
550
551static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
552{
553 kunmap_atomic(buffer);
554 local_irq_restore(*flags);
555}
556
557static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
558 dma_addr_t addr, int len, unsigned cmd)
559{
560 struct sdhci_adma2_64_desc *dma_desc = desc;
561
562 /* 32-bit and 64-bit descriptors have these members in same position */
563 dma_desc->cmd = cpu_to_le16(cmd);
564 dma_desc->len = cpu_to_le16(len);
565 dma_desc->addr_lo = cpu_to_le32((u32)addr);
566
567 if (host->flags & SDHCI_USE_64_BIT_DMA)
568 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
569}
570
571static void sdhci_adma_mark_end(void *desc)
572{
573 struct sdhci_adma2_64_desc *dma_desc = desc;
574
575 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
576 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
577}
578
579static void sdhci_adma_table_pre(struct sdhci_host *host,
580 struct mmc_data *data, int sg_count)
581{
582 struct scatterlist *sg;
583 unsigned long flags;
584 dma_addr_t addr, align_addr;
585 void *desc, *align;
586 char *buffer;
587 int len, offset, i;
588
589 /*
590 * The spec does not specify endianness of descriptor table.
591 * We currently guess that it is LE.
592 */
593
594 host->sg_count = sg_count;
595
596 desc = host->adma_table;
597 align = host->align_buffer;
598
599 align_addr = host->align_addr;
600
601 for_each_sg(data->sg, sg, host->sg_count, i) {
602 addr = sg_dma_address(sg);
603 len = sg_dma_len(sg);
604
605 /*
606 * The SDHCI specification states that ADMA addresses must
607 * be 32-bit aligned. If they aren't, then we use a bounce
608 * buffer for the (up to three) bytes that screw up the
609 * alignment.
610 */
611 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
612 SDHCI_ADMA2_MASK;
613 if (offset) {
614 if (data->flags & MMC_DATA_WRITE) {
615 buffer = sdhci_kmap_atomic(sg, &flags);
616 memcpy(align, buffer, offset);
617 sdhci_kunmap_atomic(buffer, &flags);
618 }
619
620 /* tran, valid */
621 sdhci_adma_write_desc(host, desc, align_addr, offset,
622 ADMA2_TRAN_VALID);
623
624 BUG_ON(offset > 65536);
625
626 align += SDHCI_ADMA2_ALIGN;
627 align_addr += SDHCI_ADMA2_ALIGN;
628
629 desc += host->desc_sz;
630
631 addr += offset;
632 len -= offset;
633 }
634
635 BUG_ON(len > 65536);
636
637 if (len) {
638 /* tran, valid */
639 sdhci_adma_write_desc(host, desc, addr, len,
640 ADMA2_TRAN_VALID);
641 desc += host->desc_sz;
642 }
643
644 /*
645 * If this triggers then we have a calculation bug
646 * somewhere. :/
647 */
648 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
649 }
650
651 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
652 /* Mark the last descriptor as the terminating descriptor */
653 if (desc != host->adma_table) {
654 desc -= host->desc_sz;
655 sdhci_adma_mark_end(desc);
656 }
657 } else {
658 /* Add a terminating entry - nop, end, valid */
659 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
660 }
661}
662
663static void sdhci_adma_table_post(struct sdhci_host *host,
664 struct mmc_data *data)
665{
666 struct scatterlist *sg;
667 int i, size;
668 void *align;
669 char *buffer;
670 unsigned long flags;
671
672 if (data->flags & MMC_DATA_READ) {
673 bool has_unaligned = false;
674
675 /* Do a quick scan of the SG list for any unaligned mappings */
676 for_each_sg(data->sg, sg, host->sg_count, i)
677 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
678 has_unaligned = true;
679 break;
680 }
681
682 if (has_unaligned) {
683 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
684 data->sg_len, DMA_FROM_DEVICE);
685
686 align = host->align_buffer;
687
688 for_each_sg(data->sg, sg, host->sg_count, i) {
689 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
690 size = SDHCI_ADMA2_ALIGN -
691 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
692
693 buffer = sdhci_kmap_atomic(sg, &flags);
694 memcpy(buffer, align, size);
695 sdhci_kunmap_atomic(buffer, &flags);
696
697 align += SDHCI_ADMA2_ALIGN;
698 }
699 }
700 }
701 }
702}
703
704static u32 sdhci_sdma_address(struct sdhci_host *host)
705{
706 if (host->bounce_buffer)
707 return host->bounce_addr;
708 else
709 return sg_dma_address(host->data->sg);
710}
711
712static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
713{
714 u8 count;
715 struct mmc_data *data = cmd->data;
716 unsigned target_timeout, current_timeout;
717
718 /*
719 * If the host controller provides us with an incorrect timeout
720 * value, just skip the check and use 0xE. The hardware may take
721 * longer to time out, but that's much better than having a too-short
722 * timeout value.
723 */
724 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
725 return 0xE;
726
727 /* Unspecified timeout, assume max */
728 if (!data && !cmd->busy_timeout)
729 return 0xE;
730
731 /* timeout in us */
732 if (!data)
733 target_timeout = cmd->busy_timeout * 1000;
734 else {
735 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
736 if (host->clock && data->timeout_clks) {
737 unsigned long long val;
738
739 /*
740 * data->timeout_clks is in units of clock cycles.
741 * host->clock is in Hz. target_timeout is in us.
742 * Hence, us = 1000000 * cycles / Hz. Round up.
743 */
744 val = 1000000ULL * data->timeout_clks;
745 if (do_div(val, host->clock))
746 target_timeout++;
747 target_timeout += val;
748 }
749 }
750
751 /*
752 * Figure out needed cycles.
753 * We do this in steps in order to fit inside a 32 bit int.
754 * The first step is the minimum timeout, which will have a
755 * minimum resolution of 6 bits:
756 * (1) 2^13*1000 > 2^22,
757 * (2) host->timeout_clk < 2^16
758 * =>
759 * (1) / (2) > 2^6
760 */
761 count = 0;
762 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
763 while (current_timeout < target_timeout) {
764 count++;
765 current_timeout <<= 1;
766 if (count >= 0xF)
767 break;
768 }
769
770 if (count >= 0xF) {
771 DBG("Too large timeout 0x%x requested for CMD%d!\n",
772 count, cmd->opcode);
773 count = 0xE;
774 }
775
776 return count;
777}
778
779static void sdhci_set_transfer_irqs(struct sdhci_host *host)
780{
781 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
782 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
783
784 if (host->flags & SDHCI_REQ_USE_DMA)
785 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
786 else
787 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
788
789 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
790 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
791}
792
793static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
794{
795 u8 count;
796
797 if (host->ops->set_timeout) {
798 host->ops->set_timeout(host, cmd);
799 } else {
800 count = sdhci_calc_timeout(host, cmd);
801 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
802 }
803}
804
805static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
806{
807 u8 ctrl;
808 struct mmc_data *data = cmd->data;
809
810 if (sdhci_data_line_cmd(cmd))
811 sdhci_set_timeout(host, cmd);
812
813 if (!data)
814 return;
815
816 WARN_ON(host->data);
817
818 /* Sanity checks */
819 BUG_ON(data->blksz * data->blocks > 524288);
820 BUG_ON(data->blksz > host->mmc->max_blk_size);
821 BUG_ON(data->blocks > 65535);
822
823 host->data = data;
824 host->data_early = 0;
825 host->data->bytes_xfered = 0;
826
827 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
828 struct scatterlist *sg;
829 unsigned int length_mask, offset_mask;
830 int i;
831
832 host->flags |= SDHCI_REQ_USE_DMA;
833
834 /*
835 * FIXME: This doesn't account for merging when mapping the
836 * scatterlist.
837 *
838 * The assumption here being that alignment and lengths are
839 * the same after DMA mapping to device address space.
840 */
841 length_mask = 0;
842 offset_mask = 0;
843 if (host->flags & SDHCI_USE_ADMA) {
844 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
845 length_mask = 3;
846 /*
847 * As we use up to 3 byte chunks to work
848 * around alignment problems, we need to
849 * check the offset as well.
850 */
851 offset_mask = 3;
852 }
853 } else {
854 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
855 length_mask = 3;
856 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
857 offset_mask = 3;
858 }
859
860 if (unlikely(length_mask | offset_mask)) {
861 for_each_sg(data->sg, sg, data->sg_len, i) {
862 if (sg->length & length_mask) {
863 DBG("Reverting to PIO because of transfer size (%d)\n",
864 sg->length);
865 host->flags &= ~SDHCI_REQ_USE_DMA;
866 break;
867 }
868 if (sg->offset & offset_mask) {
869 DBG("Reverting to PIO because of bad alignment\n");
870 host->flags &= ~SDHCI_REQ_USE_DMA;
871 break;
872 }
873 }
874 }
875 }
876
877 if (host->flags & SDHCI_REQ_USE_DMA) {
878 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
879
880 if (sg_cnt <= 0) {
881 /*
882 * This only happens when someone fed
883 * us an invalid request.
884 */
885 WARN_ON(1);
886 host->flags &= ~SDHCI_REQ_USE_DMA;
887 } else if (host->flags & SDHCI_USE_ADMA) {
888 sdhci_adma_table_pre(host, data, sg_cnt);
889
890 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
891 if (host->flags & SDHCI_USE_64_BIT_DMA)
892 sdhci_writel(host,
893 (u64)host->adma_addr >> 32,
894 SDHCI_ADMA_ADDRESS_HI);
895 } else {
896 WARN_ON(sg_cnt != 1);
897 sdhci_writel(host, sdhci_sdma_address(host),
898 SDHCI_DMA_ADDRESS);
899 }
900 }
901
902 /*
903 * Always adjust the DMA selection as some controllers
904 * (e.g. JMicron) can't do PIO properly when the selection
905 * is ADMA.
906 */
907 if (host->version >= SDHCI_SPEC_200) {
908 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
909 ctrl &= ~SDHCI_CTRL_DMA_MASK;
910 if ((host->flags & SDHCI_REQ_USE_DMA) &&
911 (host->flags & SDHCI_USE_ADMA)) {
912 if (host->flags & SDHCI_USE_64_BIT_DMA)
913 ctrl |= SDHCI_CTRL_ADMA64;
914 else
915 ctrl |= SDHCI_CTRL_ADMA32;
916 } else {
917 ctrl |= SDHCI_CTRL_SDMA;
918 }
919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
920 }
921
922 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
923 int flags;
924
925 flags = SG_MITER_ATOMIC;
926 if (host->data->flags & MMC_DATA_READ)
927 flags |= SG_MITER_TO_SG;
928 else
929 flags |= SG_MITER_FROM_SG;
930 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
931 host->blocks = data->blocks;
932 }
933
934 sdhci_set_transfer_irqs(host);
935
936 /* Set the DMA boundary value and block size */
937 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
938 SDHCI_BLOCK_SIZE);
939 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
940}
941
942static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
943 struct mmc_request *mrq)
944{
945 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
946 !mrq->cap_cmd_during_tfr;
947}
948
949static void sdhci_set_transfer_mode(struct sdhci_host *host,
950 struct mmc_command *cmd)
951{
952 u16 mode = 0;
953 struct mmc_data *data = cmd->data;
954
955 if (data == NULL) {
956 if (host->quirks2 &
957 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
958 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
959 } else {
960 /* clear Auto CMD settings for no data CMDs */
961 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
962 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
963 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
964 }
965 return;
966 }
967
968 WARN_ON(!host->data);
969
970 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
971 mode = SDHCI_TRNS_BLK_CNT_EN;
972
973 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
974 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
975 /*
976 * If we are sending CMD23, CMD12 never gets sent
977 * on successful completion (so no Auto-CMD12).
978 */
979 if (sdhci_auto_cmd12(host, cmd->mrq) &&
980 (cmd->opcode != SD_IO_RW_EXTENDED))
981 mode |= SDHCI_TRNS_AUTO_CMD12;
982 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
983 mode |= SDHCI_TRNS_AUTO_CMD23;
984 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
985 }
986 }
987
988 if (data->flags & MMC_DATA_READ)
989 mode |= SDHCI_TRNS_READ;
990 if (host->flags & SDHCI_REQ_USE_DMA)
991 mode |= SDHCI_TRNS_DMA;
992
993 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
994}
995
996static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
997{
998 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
999 ((mrq->cmd && mrq->cmd->error) ||
1000 (mrq->sbc && mrq->sbc->error) ||
1001 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
1002 (mrq->data->stop && mrq->data->stop->error))) ||
1003 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1004}
1005
1006static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1007{
1008 int i;
1009
1010 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1011 if (host->mrqs_done[i] == mrq) {
1012 WARN_ON(1);
1013 return;
1014 }
1015 }
1016
1017 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1018 if (!host->mrqs_done[i]) {
1019 host->mrqs_done[i] = mrq;
1020 break;
1021 }
1022 }
1023
1024 WARN_ON(i >= SDHCI_MAX_MRQS);
1025
1026 tasklet_schedule(&host->finish_tasklet);
1027}
1028
1029static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1030{
1031 if (host->cmd && host->cmd->mrq == mrq)
1032 host->cmd = NULL;
1033
1034 if (host->data_cmd && host->data_cmd->mrq == mrq)
1035 host->data_cmd = NULL;
1036
1037 if (host->data && host->data->mrq == mrq)
1038 host->data = NULL;
1039
1040 if (sdhci_needs_reset(host, mrq))
1041 host->pending_reset = true;
1042
1043 __sdhci_finish_mrq(host, mrq);
1044}
1045
1046static void sdhci_finish_data(struct sdhci_host *host)
1047{
1048 struct mmc_command *data_cmd = host->data_cmd;
1049 struct mmc_data *data = host->data;
1050
1051 host->data = NULL;
1052 host->data_cmd = NULL;
1053
1054 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1055 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1056 sdhci_adma_table_post(host, data);
1057
1058 /*
1059 * The specification states that the block count register must
1060 * be updated, but it does not specify at what point in the
1061 * data flow. That makes the register entirely useless to read
1062 * back so we have to assume that nothing made it to the card
1063 * in the event of an error.
1064 */
1065 if (data->error)
1066 data->bytes_xfered = 0;
1067 else
1068 data->bytes_xfered = data->blksz * data->blocks;
1069
1070 /*
1071 * Need to send CMD12 if -
1072 * a) open-ended multiblock transfer (no CMD23)
1073 * b) error in multiblock transfer
1074 */
1075 if (data->stop &&
1076 (data->error ||
1077 !data->mrq->sbc)) {
1078
1079 /*
1080 * The controller needs a reset of internal state machines
1081 * upon error conditions.
1082 */
1083 if (data->error) {
1084 if (!host->cmd || host->cmd == data_cmd)
1085 sdhci_do_reset(host, SDHCI_RESET_CMD);
1086 sdhci_do_reset(host, SDHCI_RESET_DATA);
1087 }
1088
1089 /*
1090 * 'cap_cmd_during_tfr' request must not use the command line
1091 * after mmc_command_done() has been called. It is upper layer's
1092 * responsibility to send the stop command if required.
1093 */
1094 if (data->mrq->cap_cmd_during_tfr) {
1095 sdhci_finish_mrq(host, data->mrq);
1096 } else {
1097 /* Avoid triggering warning in sdhci_send_command() */
1098 host->cmd = NULL;
1099 sdhci_send_command(host, data->stop);
1100 }
1101 } else {
1102 sdhci_finish_mrq(host, data->mrq);
1103 }
1104}
1105
1106static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1107 unsigned long timeout)
1108{
1109 if (sdhci_data_line_cmd(mrq->cmd))
1110 mod_timer(&host->data_timer, timeout);
1111 else
1112 mod_timer(&host->timer, timeout);
1113}
1114
1115static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1116{
1117 if (sdhci_data_line_cmd(mrq->cmd))
1118 del_timer(&host->data_timer);
1119 else
1120 del_timer(&host->timer);
1121}
1122
1123void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1124{
1125 int flags;
1126 u32 mask;
1127 unsigned long timeout;
1128
1129 WARN_ON(host->cmd);
1130
1131 /* Initially, a command has no error */
1132 cmd->error = 0;
1133
1134 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1135 cmd->opcode == MMC_STOP_TRANSMISSION)
1136 cmd->flags |= MMC_RSP_BUSY;
1137
1138 /* Wait max 10 ms */
1139 timeout = 10;
1140
1141 mask = SDHCI_CMD_INHIBIT;
1142 if (sdhci_data_line_cmd(cmd))
1143 mask |= SDHCI_DATA_INHIBIT;
1144
1145 /* We shouldn't wait for data inihibit for stop commands, even
1146 though they might use busy signaling */
1147 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1148 mask &= ~SDHCI_DATA_INHIBIT;
1149
1150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1151 if (timeout == 0) {
1152 pr_err("%s: Controller never released inhibit bit(s).\n",
1153 mmc_hostname(host->mmc));
1154 sdhci_dumpregs(host);
1155 cmd->error = -EIO;
1156 sdhci_finish_mrq(host, cmd->mrq);
1157 return;
1158 }
1159 timeout--;
1160 mdelay(1);
1161 }
1162
1163 timeout = jiffies;
1164 if (!cmd->data && cmd->busy_timeout > 9000)
1165 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1166 else
1167 timeout += 10 * HZ;
1168 sdhci_mod_timer(host, cmd->mrq, timeout);
1169
1170 host->cmd = cmd;
1171 if (sdhci_data_line_cmd(cmd)) {
1172 WARN_ON(host->data_cmd);
1173 host->data_cmd = cmd;
1174 }
1175
1176 sdhci_prepare_data(host, cmd);
1177
1178 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1179
1180 sdhci_set_transfer_mode(host, cmd);
1181
1182 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1183 pr_err("%s: Unsupported response type!\n",
1184 mmc_hostname(host->mmc));
1185 cmd->error = -EINVAL;
1186 sdhci_finish_mrq(host, cmd->mrq);
1187 return;
1188 }
1189
1190 if (!(cmd->flags & MMC_RSP_PRESENT))
1191 flags = SDHCI_CMD_RESP_NONE;
1192 else if (cmd->flags & MMC_RSP_136)
1193 flags = SDHCI_CMD_RESP_LONG;
1194 else if (cmd->flags & MMC_RSP_BUSY)
1195 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1196 else
1197 flags = SDHCI_CMD_RESP_SHORT;
1198
1199 if (cmd->flags & MMC_RSP_CRC)
1200 flags |= SDHCI_CMD_CRC;
1201 if (cmd->flags & MMC_RSP_OPCODE)
1202 flags |= SDHCI_CMD_INDEX;
1203
1204 /* CMD19 is special in that the Data Present Select should be set */
1205 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1206 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1207 flags |= SDHCI_CMD_DATA;
1208
1209 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1210}
1211EXPORT_SYMBOL_GPL(sdhci_send_command);
1212
1213static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1214{
1215 int i, reg;
1216
1217 for (i = 0; i < 4; i++) {
1218 reg = SDHCI_RESPONSE + (3 - i) * 4;
1219 cmd->resp[i] = sdhci_readl(host, reg);
1220 }
1221
1222 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1223 return;
1224
1225 /* CRC is stripped so we need to do some shifting */
1226 for (i = 0; i < 4; i++) {
1227 cmd->resp[i] <<= 8;
1228 if (i != 3)
1229 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1230 }
1231}
1232
1233static void sdhci_finish_command(struct sdhci_host *host)
1234{
1235 struct mmc_command *cmd = host->cmd;
1236
1237 host->cmd = NULL;
1238
1239 if (cmd->flags & MMC_RSP_PRESENT) {
1240 if (cmd->flags & MMC_RSP_136) {
1241 sdhci_read_rsp_136(host, cmd);
1242 } else {
1243 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1244 }
1245 }
1246
1247 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1248 mmc_command_done(host->mmc, cmd->mrq);
1249
1250 /*
1251 * The host can send and interrupt when the busy state has
1252 * ended, allowing us to wait without wasting CPU cycles.
1253 * The busy signal uses DAT0 so this is similar to waiting
1254 * for data to complete.
1255 *
1256 * Note: The 1.0 specification is a bit ambiguous about this
1257 * feature so there might be some problems with older
1258 * controllers.
1259 */
1260 if (cmd->flags & MMC_RSP_BUSY) {
1261 if (cmd->data) {
1262 DBG("Cannot wait for busy signal when also doing a data transfer");
1263 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1264 cmd == host->data_cmd) {
1265 /* Command complete before busy is ended */
1266 return;
1267 }
1268 }
1269
1270 /* Finished CMD23, now send actual command. */
1271 if (cmd == cmd->mrq->sbc) {
1272 sdhci_send_command(host, cmd->mrq->cmd);
1273 } else {
1274
1275 /* Processed actual command. */
1276 if (host->data && host->data_early)
1277 sdhci_finish_data(host);
1278
1279 if (!cmd->data)
1280 sdhci_finish_mrq(host, cmd->mrq);
1281 }
1282}
1283
1284static u16 sdhci_get_preset_value(struct sdhci_host *host)
1285{
1286 u16 preset = 0;
1287
1288 switch (host->timing) {
1289 case MMC_TIMING_UHS_SDR12:
1290 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1291 break;
1292 case MMC_TIMING_UHS_SDR25:
1293 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1294 break;
1295 case MMC_TIMING_UHS_SDR50:
1296 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1297 break;
1298 case MMC_TIMING_UHS_SDR104:
1299 case MMC_TIMING_MMC_HS200:
1300 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1301 break;
1302 case MMC_TIMING_UHS_DDR50:
1303 case MMC_TIMING_MMC_DDR52:
1304 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1305 break;
1306 case MMC_TIMING_MMC_HS400:
1307 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1308 break;
1309 default:
1310 pr_warn("%s: Invalid UHS-I mode selected\n",
1311 mmc_hostname(host->mmc));
1312 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1313 break;
1314 }
1315 return preset;
1316}
1317
1318u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1319 unsigned int *actual_clock)
1320{
1321 int div = 0; /* Initialized for compiler warning */
1322 int real_div = div, clk_mul = 1;
1323 u16 clk = 0;
1324 bool switch_base_clk = false;
1325
1326 if (host->version >= SDHCI_SPEC_300) {
1327 if (host->preset_enabled) {
1328 u16 pre_val;
1329
1330 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1331 pre_val = sdhci_get_preset_value(host);
1332 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1333 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1334 if (host->clk_mul &&
1335 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1336 clk = SDHCI_PROG_CLOCK_MODE;
1337 real_div = div + 1;
1338 clk_mul = host->clk_mul;
1339 } else {
1340 real_div = max_t(int, 1, div << 1);
1341 }
1342 goto clock_set;
1343 }
1344
1345 /*
1346 * Check if the Host Controller supports Programmable Clock
1347 * Mode.
1348 */
1349 if (host->clk_mul) {
1350 for (div = 1; div <= 1024; div++) {
1351 if ((host->max_clk * host->clk_mul / div)
1352 <= clock)
1353 break;
1354 }
1355 if ((host->max_clk * host->clk_mul / div) <= clock) {
1356 /*
1357 * Set Programmable Clock Mode in the Clock
1358 * Control register.
1359 */
1360 clk = SDHCI_PROG_CLOCK_MODE;
1361 real_div = div;
1362 clk_mul = host->clk_mul;
1363 div--;
1364 } else {
1365 /*
1366 * Divisor can be too small to reach clock
1367 * speed requirement. Then use the base clock.
1368 */
1369 switch_base_clk = true;
1370 }
1371 }
1372
1373 if (!host->clk_mul || switch_base_clk) {
1374 /* Version 3.00 divisors must be a multiple of 2. */
1375 if (host->max_clk <= clock)
1376 div = 1;
1377 else {
1378 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1379 div += 2) {
1380 if ((host->max_clk / div) <= clock)
1381 break;
1382 }
1383 }
1384 real_div = div;
1385 div >>= 1;
1386 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1387 && !div && host->max_clk <= 25000000)
1388 div = 1;
1389 }
1390 } else {
1391 /* Version 2.00 divisors must be a power of 2. */
1392 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1393 if ((host->max_clk / div) <= clock)
1394 break;
1395 }
1396 real_div = div;
1397 div >>= 1;
1398 }
1399
1400clock_set:
1401 if (real_div)
1402 *actual_clock = (host->max_clk * clk_mul) / real_div;
1403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1405 << SDHCI_DIVIDER_HI_SHIFT;
1406
1407 return clk;
1408}
1409EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1410
1411void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1412{
1413 ktime_t timeout;
1414
1415 clk |= SDHCI_CLOCK_INT_EN;
1416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1417
1418 /* Wait max 20 ms */
1419 timeout = ktime_add_ms(ktime_get(), 20);
1420 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1421 & SDHCI_CLOCK_INT_STABLE)) {
1422 if (ktime_after(ktime_get(), timeout)) {
1423 pr_err("%s: Internal clock never stabilised.\n",
1424 mmc_hostname(host->mmc));
1425 sdhci_dumpregs(host);
1426 return;
1427 }
1428 udelay(10);
1429 }
1430
1431 clk |= SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433}
1434EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1435
1436void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1437{
1438 u16 clk;
1439
1440 host->mmc->actual_clock = 0;
1441
1442 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1443
1444 if (clock == 0)
1445 return;
1446
1447 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1448 sdhci_enable_clk(host, clk);
1449}
1450EXPORT_SYMBOL_GPL(sdhci_set_clock);
1451
1452static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1453 unsigned short vdd)
1454{
1455 struct mmc_host *mmc = host->mmc;
1456
1457 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1458
1459 if (mode != MMC_POWER_OFF)
1460 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1461 else
1462 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1463}
1464
1465void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1466 unsigned short vdd)
1467{
1468 u8 pwr = 0;
1469
1470 if (mode != MMC_POWER_OFF) {
1471 switch (1 << vdd) {
1472 case MMC_VDD_165_195:
1473 /*
1474 * Without a regulator, SDHCI does not support 2.0v
1475 * so we only get here if the driver deliberately
1476 * added the 2.0v range to ocr_avail. Map it to 1.8v
1477 * for the purpose of turning on the power.
1478 */
1479 case MMC_VDD_20_21:
1480 pwr = SDHCI_POWER_180;
1481 break;
1482 case MMC_VDD_29_30:
1483 case MMC_VDD_30_31:
1484 pwr = SDHCI_POWER_300;
1485 break;
1486 case MMC_VDD_32_33:
1487 case MMC_VDD_33_34:
1488 pwr = SDHCI_POWER_330;
1489 break;
1490 default:
1491 WARN(1, "%s: Invalid vdd %#x\n",
1492 mmc_hostname(host->mmc), vdd);
1493 break;
1494 }
1495 }
1496
1497 if (host->pwr == pwr)
1498 return;
1499
1500 host->pwr = pwr;
1501
1502 if (pwr == 0) {
1503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1504 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1505 sdhci_runtime_pm_bus_off(host);
1506 } else {
1507 /*
1508 * Spec says that we should clear the power reg before setting
1509 * a new value. Some controllers don't seem to like this though.
1510 */
1511 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1512 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1513
1514 /*
1515 * At least the Marvell CaFe chip gets confused if we set the
1516 * voltage and set turn on power at the same time, so set the
1517 * voltage first.
1518 */
1519 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1520 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1521
1522 pwr |= SDHCI_POWER_ON;
1523
1524 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1525
1526 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1527 sdhci_runtime_pm_bus_on(host);
1528
1529 /*
1530 * Some controllers need an extra 10ms delay of 10ms before
1531 * they can apply clock after applying power
1532 */
1533 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1534 mdelay(10);
1535 }
1536}
1537EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1538
1539void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1540 unsigned short vdd)
1541{
1542 if (IS_ERR(host->mmc->supply.vmmc))
1543 sdhci_set_power_noreg(host, mode, vdd);
1544 else
1545 sdhci_set_power_reg(host, mode, vdd);
1546}
1547EXPORT_SYMBOL_GPL(sdhci_set_power);
1548
1549/*****************************************************************************\
1550 * *
1551 * MMC callbacks *
1552 * *
1553\*****************************************************************************/
1554
1555static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1556{
1557 struct sdhci_host *host;
1558 int present;
1559 unsigned long flags;
1560
1561 host = mmc_priv(mmc);
1562
1563 /* Firstly check card presence */
1564 present = mmc->ops->get_cd(mmc);
1565
1566 spin_lock_irqsave(&host->lock, flags);
1567
1568 sdhci_led_activate(host);
1569
1570 /*
1571 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1572 * requests if Auto-CMD12 is enabled.
1573 */
1574 if (sdhci_auto_cmd12(host, mrq)) {
1575 if (mrq->stop) {
1576 mrq->data->stop = NULL;
1577 mrq->stop = NULL;
1578 }
1579 }
1580
1581 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1582 mrq->cmd->error = -ENOMEDIUM;
1583 sdhci_finish_mrq(host, mrq);
1584 } else {
1585 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1586 sdhci_send_command(host, mrq->sbc);
1587 else
1588 sdhci_send_command(host, mrq->cmd);
1589 }
1590
1591 mmiowb();
1592 spin_unlock_irqrestore(&host->lock, flags);
1593}
1594
1595void sdhci_set_bus_width(struct sdhci_host *host, int width)
1596{
1597 u8 ctrl;
1598
1599 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1600 if (width == MMC_BUS_WIDTH_8) {
1601 ctrl &= ~SDHCI_CTRL_4BITBUS;
1602 ctrl |= SDHCI_CTRL_8BITBUS;
1603 } else {
1604 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1605 ctrl &= ~SDHCI_CTRL_8BITBUS;
1606 if (width == MMC_BUS_WIDTH_4)
1607 ctrl |= SDHCI_CTRL_4BITBUS;
1608 else
1609 ctrl &= ~SDHCI_CTRL_4BITBUS;
1610 }
1611 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1612}
1613EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1614
1615void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1616{
1617 u16 ctrl_2;
1618
1619 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1620 /* Select Bus Speed Mode for host */
1621 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1622 if ((timing == MMC_TIMING_MMC_HS200) ||
1623 (timing == MMC_TIMING_UHS_SDR104))
1624 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1625 else if (timing == MMC_TIMING_UHS_SDR12)
1626 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1627 else if (timing == MMC_TIMING_UHS_SDR25)
1628 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1629 else if (timing == MMC_TIMING_UHS_SDR50)
1630 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1631 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1632 (timing == MMC_TIMING_MMC_DDR52))
1633 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1634 else if (timing == MMC_TIMING_MMC_HS400)
1635 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1636 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1637}
1638EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1639
1640void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 u8 ctrl;
1644
1645 if (ios->power_mode == MMC_POWER_UNDEFINED)
1646 return;
1647
1648 if (host->flags & SDHCI_DEVICE_DEAD) {
1649 if (!IS_ERR(mmc->supply.vmmc) &&
1650 ios->power_mode == MMC_POWER_OFF)
1651 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1652 return;
1653 }
1654
1655 /*
1656 * Reset the chip on each power off.
1657 * Should clear out any weird states.
1658 */
1659 if (ios->power_mode == MMC_POWER_OFF) {
1660 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1661 sdhci_reinit(host);
1662 }
1663
1664 if (host->version >= SDHCI_SPEC_300 &&
1665 (ios->power_mode == MMC_POWER_UP) &&
1666 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1667 sdhci_enable_preset_value(host, false);
1668
1669 if (!ios->clock || ios->clock != host->clock) {
1670 host->ops->set_clock(host, ios->clock);
1671 host->clock = ios->clock;
1672
1673 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1674 host->clock) {
1675 host->timeout_clk = host->mmc->actual_clock ?
1676 host->mmc->actual_clock / 1000 :
1677 host->clock / 1000;
1678 host->mmc->max_busy_timeout =
1679 host->ops->get_max_timeout_count ?
1680 host->ops->get_max_timeout_count(host) :
1681 1 << 27;
1682 host->mmc->max_busy_timeout /= host->timeout_clk;
1683 }
1684 }
1685
1686 if (host->ops->set_power)
1687 host->ops->set_power(host, ios->power_mode, ios->vdd);
1688 else
1689 sdhci_set_power(host, ios->power_mode, ios->vdd);
1690
1691 if (host->ops->platform_send_init_74_clocks)
1692 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1693
1694 host->ops->set_bus_width(host, ios->bus_width);
1695
1696 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1697
1698 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1699 if (ios->timing == MMC_TIMING_SD_HS ||
1700 ios->timing == MMC_TIMING_MMC_HS ||
1701 ios->timing == MMC_TIMING_MMC_HS400 ||
1702 ios->timing == MMC_TIMING_MMC_HS200 ||
1703 ios->timing == MMC_TIMING_MMC_DDR52 ||
1704 ios->timing == MMC_TIMING_UHS_SDR50 ||
1705 ios->timing == MMC_TIMING_UHS_SDR104 ||
1706 ios->timing == MMC_TIMING_UHS_DDR50 ||
1707 ios->timing == MMC_TIMING_UHS_SDR25)
1708 ctrl |= SDHCI_CTRL_HISPD;
1709 else
1710 ctrl &= ~SDHCI_CTRL_HISPD;
1711 }
1712
1713 if (host->version >= SDHCI_SPEC_300) {
1714 u16 clk, ctrl_2;
1715
1716 if (!host->preset_enabled) {
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1718 /*
1719 * We only need to set Driver Strength if the
1720 * preset value enable is not set.
1721 */
1722 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1723 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1724 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1725 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1726 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1727 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1728 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1729 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1730 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1731 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1732 else {
1733 pr_warn("%s: invalid driver type, default to driver type B\n",
1734 mmc_hostname(mmc));
1735 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1736 }
1737
1738 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1739 } else {
1740 /*
1741 * According to SDHC Spec v3.00, if the Preset Value
1742 * Enable in the Host Control 2 register is set, we
1743 * need to reset SD Clock Enable before changing High
1744 * Speed Enable to avoid generating clock gliches.
1745 */
1746
1747 /* Reset SD Clock Enable */
1748 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1749 clk &= ~SDHCI_CLOCK_CARD_EN;
1750 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1751
1752 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1753
1754 /* Re-enable SD Clock */
1755 host->ops->set_clock(host, host->clock);
1756 }
1757
1758 /* Reset SD Clock Enable */
1759 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1760 clk &= ~SDHCI_CLOCK_CARD_EN;
1761 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1762
1763 host->ops->set_uhs_signaling(host, ios->timing);
1764 host->timing = ios->timing;
1765
1766 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1767 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1768 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1769 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1770 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1771 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1772 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1773 u16 preset;
1774
1775 sdhci_enable_preset_value(host, true);
1776 preset = sdhci_get_preset_value(host);
1777 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1778 >> SDHCI_PRESET_DRV_SHIFT;
1779 }
1780
1781 /* Re-enable SD Clock */
1782 host->ops->set_clock(host, host->clock);
1783 } else
1784 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1785
1786 /*
1787 * Some (ENE) controllers go apeshit on some ios operation,
1788 * signalling timeout and CRC errors even on CMD0. Resetting
1789 * it on each ios seems to solve the problem.
1790 */
1791 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1792 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1793
1794 mmiowb();
1795}
1796EXPORT_SYMBOL_GPL(sdhci_set_ios);
1797
1798static int sdhci_get_cd(struct mmc_host *mmc)
1799{
1800 struct sdhci_host *host = mmc_priv(mmc);
1801 int gpio_cd = mmc_gpio_get_cd(mmc);
1802
1803 if (host->flags & SDHCI_DEVICE_DEAD)
1804 return 0;
1805
1806 /* If nonremovable, assume that the card is always present. */
1807 if (!mmc_card_is_removable(host->mmc))
1808 return 1;
1809
1810 /*
1811 * Try slot gpio detect, if defined it take precedence
1812 * over build in controller functionality
1813 */
1814 if (gpio_cd >= 0)
1815 return !!gpio_cd;
1816
1817 /* If polling, assume that the card is always present. */
1818 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1819 return 1;
1820
1821 /* Host native card detect */
1822 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1823}
1824
1825static int sdhci_check_ro(struct sdhci_host *host)
1826{
1827 unsigned long flags;
1828 int is_readonly;
1829
1830 spin_lock_irqsave(&host->lock, flags);
1831
1832 if (host->flags & SDHCI_DEVICE_DEAD)
1833 is_readonly = 0;
1834 else if (host->ops->get_ro)
1835 is_readonly = host->ops->get_ro(host);
1836 else
1837 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1838 & SDHCI_WRITE_PROTECT);
1839
1840 spin_unlock_irqrestore(&host->lock, flags);
1841
1842 /* This quirk needs to be replaced by a callback-function later */
1843 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1844 !is_readonly : is_readonly;
1845}
1846
1847#define SAMPLE_COUNT 5
1848
1849static int sdhci_get_ro(struct mmc_host *mmc)
1850{
1851 struct sdhci_host *host = mmc_priv(mmc);
1852 int i, ro_count;
1853
1854 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1855 return sdhci_check_ro(host);
1856
1857 ro_count = 0;
1858 for (i = 0; i < SAMPLE_COUNT; i++) {
1859 if (sdhci_check_ro(host)) {
1860 if (++ro_count > SAMPLE_COUNT / 2)
1861 return 1;
1862 }
1863 msleep(30);
1864 }
1865 return 0;
1866}
1867
1868static void sdhci_hw_reset(struct mmc_host *mmc)
1869{
1870 struct sdhci_host *host = mmc_priv(mmc);
1871
1872 if (host->ops && host->ops->hw_reset)
1873 host->ops->hw_reset(host);
1874}
1875
1876static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1877{
1878 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1879 if (enable)
1880 host->ier |= SDHCI_INT_CARD_INT;
1881 else
1882 host->ier &= ~SDHCI_INT_CARD_INT;
1883
1884 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1885 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1886 mmiowb();
1887 }
1888}
1889
1890void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1891{
1892 struct sdhci_host *host = mmc_priv(mmc);
1893 unsigned long flags;
1894
1895 if (enable)
1896 pm_runtime_get_noresume(host->mmc->parent);
1897
1898 spin_lock_irqsave(&host->lock, flags);
1899 if (enable)
1900 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1901 else
1902 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1903
1904 sdhci_enable_sdio_irq_nolock(host, enable);
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 if (!enable)
1908 pm_runtime_put_noidle(host->mmc->parent);
1909}
1910EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1911
1912int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1913 struct mmc_ios *ios)
1914{
1915 struct sdhci_host *host = mmc_priv(mmc);
1916 u16 ctrl;
1917 int ret;
1918
1919 /*
1920 * Signal Voltage Switching is only applicable for Host Controllers
1921 * v3.00 and above.
1922 */
1923 if (host->version < SDHCI_SPEC_300)
1924 return 0;
1925
1926 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927
1928 switch (ios->signal_voltage) {
1929 case MMC_SIGNAL_VOLTAGE_330:
1930 if (!(host->flags & SDHCI_SIGNALING_330))
1931 return -EINVAL;
1932 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1933 ctrl &= ~SDHCI_CTRL_VDD_180;
1934 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1935
1936 if (!IS_ERR(mmc->supply.vqmmc)) {
1937 ret = mmc_regulator_set_vqmmc(mmc, ios);
1938 if (ret) {
1939 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1940 mmc_hostname(mmc));
1941 return -EIO;
1942 }
1943 }
1944 /* Wait for 5ms */
1945 usleep_range(5000, 5500);
1946
1947 /* 3.3V regulator output should be stable within 5 ms */
1948 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1949 if (!(ctrl & SDHCI_CTRL_VDD_180))
1950 return 0;
1951
1952 pr_warn("%s: 3.3V regulator output did not became stable\n",
1953 mmc_hostname(mmc));
1954
1955 return -EAGAIN;
1956 case MMC_SIGNAL_VOLTAGE_180:
1957 if (!(host->flags & SDHCI_SIGNALING_180))
1958 return -EINVAL;
1959 if (!IS_ERR(mmc->supply.vqmmc)) {
1960 ret = mmc_regulator_set_vqmmc(mmc, ios);
1961 if (ret) {
1962 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1963 mmc_hostname(mmc));
1964 return -EIO;
1965 }
1966 }
1967
1968 /*
1969 * Enable 1.8V Signal Enable in the Host Control2
1970 * register
1971 */
1972 ctrl |= SDHCI_CTRL_VDD_180;
1973 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1974
1975 /* Some controller need to do more when switching */
1976 if (host->ops->voltage_switch)
1977 host->ops->voltage_switch(host);
1978
1979 /* 1.8V regulator output should be stable within 5 ms */
1980 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1981 if (ctrl & SDHCI_CTRL_VDD_180)
1982 return 0;
1983
1984 pr_warn("%s: 1.8V regulator output did not became stable\n",
1985 mmc_hostname(mmc));
1986
1987 return -EAGAIN;
1988 case MMC_SIGNAL_VOLTAGE_120:
1989 if (!(host->flags & SDHCI_SIGNALING_120))
1990 return -EINVAL;
1991 if (!IS_ERR(mmc->supply.vqmmc)) {
1992 ret = mmc_regulator_set_vqmmc(mmc, ios);
1993 if (ret) {
1994 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1995 mmc_hostname(mmc));
1996 return -EIO;
1997 }
1998 }
1999 return 0;
2000 default:
2001 /* No signal voltage switch required */
2002 return 0;
2003 }
2004}
2005EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2006
2007static int sdhci_card_busy(struct mmc_host *mmc)
2008{
2009 struct sdhci_host *host = mmc_priv(mmc);
2010 u32 present_state;
2011
2012 /* Check whether DAT[0] is 0 */
2013 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2014
2015 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2016}
2017
2018static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2019{
2020 struct sdhci_host *host = mmc_priv(mmc);
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&host->lock, flags);
2024 host->flags |= SDHCI_HS400_TUNING;
2025 spin_unlock_irqrestore(&host->lock, flags);
2026
2027 return 0;
2028}
2029
2030static void sdhci_start_tuning(struct sdhci_host *host)
2031{
2032 u16 ctrl;
2033
2034 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2036 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2037 ctrl |= SDHCI_CTRL_TUNED_CLK;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039
2040 /*
2041 * As per the Host Controller spec v3.00, tuning command
2042 * generates Buffer Read Ready interrupt, so enable that.
2043 *
2044 * Note: The spec clearly says that when tuning sequence
2045 * is being performed, the controller does not generate
2046 * interrupts other than Buffer Read Ready interrupt. But
2047 * to make sure we don't hit a controller bug, we _only_
2048 * enable Buffer Read Ready interrupt here.
2049 */
2050 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2051 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2052}
2053
2054static void sdhci_end_tuning(struct sdhci_host *host)
2055{
2056 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2057 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2058}
2059
2060static void sdhci_reset_tuning(struct sdhci_host *host)
2061{
2062 u16 ctrl;
2063
2064 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068}
2069
2070static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2071{
2072 sdhci_reset_tuning(host);
2073
2074 sdhci_do_reset(host, SDHCI_RESET_CMD);
2075 sdhci_do_reset(host, SDHCI_RESET_DATA);
2076
2077 sdhci_end_tuning(host);
2078
2079 mmc_abort_tuning(host->mmc, opcode);
2080}
2081
2082/*
2083 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2084 * tuning command does not have a data payload (or rather the hardware does it
2085 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2086 * interrupt setup is different to other commands and there is no timeout
2087 * interrupt so special handling is needed.
2088 */
2089static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2090{
2091 struct mmc_host *mmc = host->mmc;
2092 struct mmc_command cmd = {};
2093 struct mmc_request mrq = {};
2094 unsigned long flags;
2095 u32 b = host->sdma_boundary;
2096
2097 spin_lock_irqsave(&host->lock, flags);
2098
2099 cmd.opcode = opcode;
2100 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2101 cmd.mrq = &mrq;
2102
2103 mrq.cmd = &cmd;
2104 /*
2105 * In response to CMD19, the card sends 64 bytes of tuning
2106 * block to the Host Controller. So we set the block size
2107 * to 64 here.
2108 */
2109 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2110 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2111 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2112 else
2113 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2114
2115 /*
2116 * The tuning block is sent by the card to the host controller.
2117 * So we set the TRNS_READ bit in the Transfer Mode register.
2118 * This also takes care of setting DMA Enable and Multi Block
2119 * Select in the same register to 0.
2120 */
2121 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2122
2123 sdhci_send_command(host, &cmd);
2124
2125 host->cmd = NULL;
2126
2127 sdhci_del_timer(host, &mrq);
2128
2129 host->tuning_done = 0;
2130
2131 mmiowb();
2132 spin_unlock_irqrestore(&host->lock, flags);
2133
2134 /* Wait for Buffer Read Ready interrupt */
2135 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2136 msecs_to_jiffies(50));
2137
2138}
2139
2140static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2141{
2142 int i;
2143
2144 /*
2145 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2146 * of loops reaches 40 times.
2147 */
2148 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2149 u16 ctrl;
2150
2151 sdhci_send_tuning(host, opcode);
2152
2153 if (!host->tuning_done) {
2154 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2155 mmc_hostname(host->mmc));
2156 sdhci_abort_tuning(host, opcode);
2157 return;
2158 }
2159
2160 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2161 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2162 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2163 return; /* Success! */
2164 break;
2165 }
2166
2167 /* Spec does not require a delay between tuning cycles */
2168 if (host->tuning_delay > 0)
2169 mdelay(host->tuning_delay);
2170 }
2171
2172 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2173 mmc_hostname(host->mmc));
2174 sdhci_reset_tuning(host);
2175}
2176
2177int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2178{
2179 struct sdhci_host *host = mmc_priv(mmc);
2180 int err = 0;
2181 unsigned int tuning_count = 0;
2182 bool hs400_tuning;
2183
2184 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2185
2186 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2187 tuning_count = host->tuning_count;
2188
2189 /*
2190 * The Host Controller needs tuning in case of SDR104 and DDR50
2191 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2192 * the Capabilities register.
2193 * If the Host Controller supports the HS200 mode then the
2194 * tuning function has to be executed.
2195 */
2196 switch (host->timing) {
2197 /* HS400 tuning is done in HS200 mode */
2198 case MMC_TIMING_MMC_HS400:
2199 err = -EINVAL;
2200 goto out;
2201
2202 case MMC_TIMING_MMC_HS200:
2203 /*
2204 * Periodic re-tuning for HS400 is not expected to be needed, so
2205 * disable it here.
2206 */
2207 if (hs400_tuning)
2208 tuning_count = 0;
2209 break;
2210
2211 case MMC_TIMING_UHS_SDR104:
2212 case MMC_TIMING_UHS_DDR50:
2213 break;
2214
2215 case MMC_TIMING_UHS_SDR50:
2216 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2217 break;
2218 /* FALLTHROUGH */
2219
2220 default:
2221 goto out;
2222 }
2223
2224 if (host->ops->platform_execute_tuning) {
2225 err = host->ops->platform_execute_tuning(host, opcode);
2226 goto out;
2227 }
2228
2229 host->mmc->retune_period = tuning_count;
2230
2231 if (host->tuning_delay < 0)
2232 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2233
2234 sdhci_start_tuning(host);
2235
2236 __sdhci_execute_tuning(host, opcode);
2237
2238 sdhci_end_tuning(host);
2239out:
2240 host->flags &= ~SDHCI_HS400_TUNING;
2241
2242 return err;
2243}
2244EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2245
2246static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2247{
2248 /* Host Controller v3.00 defines preset value registers */
2249 if (host->version < SDHCI_SPEC_300)
2250 return;
2251
2252 /*
2253 * We only enable or disable Preset Value if they are not already
2254 * enabled or disabled respectively. Otherwise, we bail out.
2255 */
2256 if (host->preset_enabled != enable) {
2257 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2258
2259 if (enable)
2260 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2261 else
2262 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2263
2264 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2265
2266 if (enable)
2267 host->flags |= SDHCI_PV_ENABLED;
2268 else
2269 host->flags &= ~SDHCI_PV_ENABLED;
2270
2271 host->preset_enabled = enable;
2272 }
2273}
2274
2275static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2276 int err)
2277{
2278 struct sdhci_host *host = mmc_priv(mmc);
2279 struct mmc_data *data = mrq->data;
2280
2281 if (data->host_cookie != COOKIE_UNMAPPED)
2282 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2283 mmc_get_dma_dir(data));
2284
2285 data->host_cookie = COOKIE_UNMAPPED;
2286}
2287
2288static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2289{
2290 struct sdhci_host *host = mmc_priv(mmc);
2291
2292 mrq->data->host_cookie = COOKIE_UNMAPPED;
2293
2294 /*
2295 * No pre-mapping in the pre hook if we're using the bounce buffer,
2296 * for that we would need two bounce buffers since one buffer is
2297 * in flight when this is getting called.
2298 */
2299 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2300 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2301}
2302
2303static inline bool sdhci_has_requests(struct sdhci_host *host)
2304{
2305 return host->cmd || host->data_cmd;
2306}
2307
2308static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2309{
2310 if (host->data_cmd) {
2311 host->data_cmd->error = err;
2312 sdhci_finish_mrq(host, host->data_cmd->mrq);
2313 }
2314
2315 if (host->cmd) {
2316 host->cmd->error = err;
2317 sdhci_finish_mrq(host, host->cmd->mrq);
2318 }
2319}
2320
2321static void sdhci_card_event(struct mmc_host *mmc)
2322{
2323 struct sdhci_host *host = mmc_priv(mmc);
2324 unsigned long flags;
2325 int present;
2326
2327 /* First check if client has provided their own card event */
2328 if (host->ops->card_event)
2329 host->ops->card_event(host);
2330
2331 present = mmc->ops->get_cd(mmc);
2332
2333 spin_lock_irqsave(&host->lock, flags);
2334
2335 /* Check sdhci_has_requests() first in case we are runtime suspended */
2336 if (sdhci_has_requests(host) && !present) {
2337 pr_err("%s: Card removed during transfer!\n",
2338 mmc_hostname(host->mmc));
2339 pr_err("%s: Resetting controller.\n",
2340 mmc_hostname(host->mmc));
2341
2342 sdhci_do_reset(host, SDHCI_RESET_CMD);
2343 sdhci_do_reset(host, SDHCI_RESET_DATA);
2344
2345 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2346 }
2347
2348 spin_unlock_irqrestore(&host->lock, flags);
2349}
2350
2351static const struct mmc_host_ops sdhci_ops = {
2352 .request = sdhci_request,
2353 .post_req = sdhci_post_req,
2354 .pre_req = sdhci_pre_req,
2355 .set_ios = sdhci_set_ios,
2356 .get_cd = sdhci_get_cd,
2357 .get_ro = sdhci_get_ro,
2358 .hw_reset = sdhci_hw_reset,
2359 .enable_sdio_irq = sdhci_enable_sdio_irq,
2360 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2361 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2362 .execute_tuning = sdhci_execute_tuning,
2363 .card_event = sdhci_card_event,
2364 .card_busy = sdhci_card_busy,
2365};
2366
2367/*****************************************************************************\
2368 * *
2369 * Tasklets *
2370 * *
2371\*****************************************************************************/
2372
2373static bool sdhci_request_done(struct sdhci_host *host)
2374{
2375 unsigned long flags;
2376 struct mmc_request *mrq;
2377 int i;
2378
2379 spin_lock_irqsave(&host->lock, flags);
2380
2381 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2382 mrq = host->mrqs_done[i];
2383 if (mrq)
2384 break;
2385 }
2386
2387 if (!mrq) {
2388 spin_unlock_irqrestore(&host->lock, flags);
2389 return true;
2390 }
2391
2392 sdhci_del_timer(host, mrq);
2393
2394 /*
2395 * Always unmap the data buffers if they were mapped by
2396 * sdhci_prepare_data() whenever we finish with a request.
2397 * This avoids leaking DMA mappings on error.
2398 */
2399 if (host->flags & SDHCI_REQ_USE_DMA) {
2400 struct mmc_data *data = mrq->data;
2401
2402 if (data && data->host_cookie == COOKIE_MAPPED) {
2403 if (host->bounce_buffer) {
2404 /*
2405 * On reads, copy the bounced data into the
2406 * sglist
2407 */
2408 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2409 unsigned int length = data->bytes_xfered;
2410
2411 if (length > host->bounce_buffer_size) {
2412 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2413 mmc_hostname(host->mmc),
2414 host->bounce_buffer_size,
2415 data->bytes_xfered);
2416 /* Cap it down and continue */
2417 length = host->bounce_buffer_size;
2418 }
2419 dma_sync_single_for_cpu(
2420 host->mmc->parent,
2421 host->bounce_addr,
2422 host->bounce_buffer_size,
2423 DMA_FROM_DEVICE);
2424 sg_copy_from_buffer(data->sg,
2425 data->sg_len,
2426 host->bounce_buffer,
2427 length);
2428 } else {
2429 /* No copying, just switch ownership */
2430 dma_sync_single_for_cpu(
2431 host->mmc->parent,
2432 host->bounce_addr,
2433 host->bounce_buffer_size,
2434 mmc_get_dma_dir(data));
2435 }
2436 } else {
2437 /* Unmap the raw data */
2438 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2439 data->sg_len,
2440 mmc_get_dma_dir(data));
2441 }
2442 data->host_cookie = COOKIE_UNMAPPED;
2443 }
2444 }
2445
2446 /*
2447 * The controller needs a reset of internal state machines
2448 * upon error conditions.
2449 */
2450 if (sdhci_needs_reset(host, mrq)) {
2451 /*
2452 * Do not finish until command and data lines are available for
2453 * reset. Note there can only be one other mrq, so it cannot
2454 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2455 * would both be null.
2456 */
2457 if (host->cmd || host->data_cmd) {
2458 spin_unlock_irqrestore(&host->lock, flags);
2459 return true;
2460 }
2461
2462 /* Some controllers need this kick or reset won't work here */
2463 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2464 /* This is to force an update */
2465 host->ops->set_clock(host, host->clock);
2466
2467 /* Spec says we should do both at the same time, but Ricoh
2468 controllers do not like that. */
2469 sdhci_do_reset(host, SDHCI_RESET_CMD);
2470 sdhci_do_reset(host, SDHCI_RESET_DATA);
2471
2472 host->pending_reset = false;
2473 }
2474
2475 if (!sdhci_has_requests(host))
2476 sdhci_led_deactivate(host);
2477
2478 host->mrqs_done[i] = NULL;
2479
2480 mmiowb();
2481 spin_unlock_irqrestore(&host->lock, flags);
2482
2483 mmc_request_done(host->mmc, mrq);
2484
2485 return false;
2486}
2487
2488static void sdhci_tasklet_finish(unsigned long param)
2489{
2490 struct sdhci_host *host = (struct sdhci_host *)param;
2491
2492 while (!sdhci_request_done(host))
2493 ;
2494}
2495
2496static void sdhci_timeout_timer(struct timer_list *t)
2497{
2498 struct sdhci_host *host;
2499 unsigned long flags;
2500
2501 host = from_timer(host, t, timer);
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2506 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2507 mmc_hostname(host->mmc));
2508 sdhci_dumpregs(host);
2509
2510 host->cmd->error = -ETIMEDOUT;
2511 sdhci_finish_mrq(host, host->cmd->mrq);
2512 }
2513
2514 mmiowb();
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518static void sdhci_timeout_data_timer(struct timer_list *t)
2519{
2520 struct sdhci_host *host;
2521 unsigned long flags;
2522
2523 host = from_timer(host, t, data_timer);
2524
2525 spin_lock_irqsave(&host->lock, flags);
2526
2527 if (host->data || host->data_cmd ||
2528 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2529 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2530 mmc_hostname(host->mmc));
2531 sdhci_dumpregs(host);
2532
2533 if (host->data) {
2534 host->data->error = -ETIMEDOUT;
2535 sdhci_finish_data(host);
2536 } else if (host->data_cmd) {
2537 host->data_cmd->error = -ETIMEDOUT;
2538 sdhci_finish_mrq(host, host->data_cmd->mrq);
2539 } else {
2540 host->cmd->error = -ETIMEDOUT;
2541 sdhci_finish_mrq(host, host->cmd->mrq);
2542 }
2543 }
2544
2545 mmiowb();
2546 spin_unlock_irqrestore(&host->lock, flags);
2547}
2548
2549/*****************************************************************************\
2550 * *
2551 * Interrupt handling *
2552 * *
2553\*****************************************************************************/
2554
2555static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2556{
2557 if (!host->cmd) {
2558 /*
2559 * SDHCI recovers from errors by resetting the cmd and data
2560 * circuits. Until that is done, there very well might be more
2561 * interrupts, so ignore them in that case.
2562 */
2563 if (host->pending_reset)
2564 return;
2565 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2566 mmc_hostname(host->mmc), (unsigned)intmask);
2567 sdhci_dumpregs(host);
2568 return;
2569 }
2570
2571 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2572 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2573 if (intmask & SDHCI_INT_TIMEOUT)
2574 host->cmd->error = -ETIMEDOUT;
2575 else
2576 host->cmd->error = -EILSEQ;
2577
2578 /*
2579 * If this command initiates a data phase and a response
2580 * CRC error is signalled, the card can start transferring
2581 * data - the card may have received the command without
2582 * error. We must not terminate the mmc_request early.
2583 *
2584 * If the card did not receive the command or returned an
2585 * error which prevented it sending data, the data phase
2586 * will time out.
2587 */
2588 if (host->cmd->data &&
2589 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2590 SDHCI_INT_CRC) {
2591 host->cmd = NULL;
2592 return;
2593 }
2594
2595 sdhci_finish_mrq(host, host->cmd->mrq);
2596 return;
2597 }
2598
2599 if (intmask & SDHCI_INT_RESPONSE)
2600 sdhci_finish_command(host);
2601}
2602
2603static void sdhci_adma_show_error(struct sdhci_host *host)
2604{
2605 void *desc = host->adma_table;
2606
2607 sdhci_dumpregs(host);
2608
2609 while (true) {
2610 struct sdhci_adma2_64_desc *dma_desc = desc;
2611
2612 if (host->flags & SDHCI_USE_64_BIT_DMA)
2613 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2614 desc, le32_to_cpu(dma_desc->addr_hi),
2615 le32_to_cpu(dma_desc->addr_lo),
2616 le16_to_cpu(dma_desc->len),
2617 le16_to_cpu(dma_desc->cmd));
2618 else
2619 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2620 desc, le32_to_cpu(dma_desc->addr_lo),
2621 le16_to_cpu(dma_desc->len),
2622 le16_to_cpu(dma_desc->cmd));
2623
2624 desc += host->desc_sz;
2625
2626 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2627 break;
2628 }
2629}
2630
2631static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2632{
2633 u32 command;
2634
2635 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2636 if (intmask & SDHCI_INT_DATA_AVAIL) {
2637 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2638 if (command == MMC_SEND_TUNING_BLOCK ||
2639 command == MMC_SEND_TUNING_BLOCK_HS200) {
2640 host->tuning_done = 1;
2641 wake_up(&host->buf_ready_int);
2642 return;
2643 }
2644 }
2645
2646 if (!host->data) {
2647 struct mmc_command *data_cmd = host->data_cmd;
2648
2649 /*
2650 * The "data complete" interrupt is also used to
2651 * indicate that a busy state has ended. See comment
2652 * above in sdhci_cmd_irq().
2653 */
2654 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2655 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2656 host->data_cmd = NULL;
2657 data_cmd->error = -ETIMEDOUT;
2658 sdhci_finish_mrq(host, data_cmd->mrq);
2659 return;
2660 }
2661 if (intmask & SDHCI_INT_DATA_END) {
2662 host->data_cmd = NULL;
2663 /*
2664 * Some cards handle busy-end interrupt
2665 * before the command completed, so make
2666 * sure we do things in the proper order.
2667 */
2668 if (host->cmd == data_cmd)
2669 return;
2670
2671 sdhci_finish_mrq(host, data_cmd->mrq);
2672 return;
2673 }
2674 }
2675
2676 /*
2677 * SDHCI recovers from errors by resetting the cmd and data
2678 * circuits. Until that is done, there very well might be more
2679 * interrupts, so ignore them in that case.
2680 */
2681 if (host->pending_reset)
2682 return;
2683
2684 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2685 mmc_hostname(host->mmc), (unsigned)intmask);
2686 sdhci_dumpregs(host);
2687
2688 return;
2689 }
2690
2691 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2692 host->data->error = -ETIMEDOUT;
2693 else if (intmask & SDHCI_INT_DATA_END_BIT)
2694 host->data->error = -EILSEQ;
2695 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2696 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2697 != MMC_BUS_TEST_R)
2698 host->data->error = -EILSEQ;
2699 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2700 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2701 sdhci_adma_show_error(host);
2702 host->data->error = -EIO;
2703 if (host->ops->adma_workaround)
2704 host->ops->adma_workaround(host, intmask);
2705 }
2706
2707 if (host->data->error)
2708 sdhci_finish_data(host);
2709 else {
2710 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2711 sdhci_transfer_pio(host);
2712
2713 /*
2714 * We currently don't do anything fancy with DMA
2715 * boundaries, but as we can't disable the feature
2716 * we need to at least restart the transfer.
2717 *
2718 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2719 * should return a valid address to continue from, but as
2720 * some controllers are faulty, don't trust them.
2721 */
2722 if (intmask & SDHCI_INT_DMA_END) {
2723 u32 dmastart, dmanow;
2724
2725 dmastart = sdhci_sdma_address(host);
2726 dmanow = dmastart + host->data->bytes_xfered;
2727 /*
2728 * Force update to the next DMA block boundary.
2729 */
2730 dmanow = (dmanow &
2731 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2732 SDHCI_DEFAULT_BOUNDARY_SIZE;
2733 host->data->bytes_xfered = dmanow - dmastart;
2734 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2735 dmastart, host->data->bytes_xfered, dmanow);
2736 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2737 }
2738
2739 if (intmask & SDHCI_INT_DATA_END) {
2740 if (host->cmd == host->data_cmd) {
2741 /*
2742 * Data managed to finish before the
2743 * command completed. Make sure we do
2744 * things in the proper order.
2745 */
2746 host->data_early = 1;
2747 } else {
2748 sdhci_finish_data(host);
2749 }
2750 }
2751 }
2752}
2753
2754static irqreturn_t sdhci_irq(int irq, void *dev_id)
2755{
2756 irqreturn_t result = IRQ_NONE;
2757 struct sdhci_host *host = dev_id;
2758 u32 intmask, mask, unexpected = 0;
2759 int max_loops = 16;
2760
2761 spin_lock(&host->lock);
2762
2763 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2764 spin_unlock(&host->lock);
2765 return IRQ_NONE;
2766 }
2767
2768 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2769 if (!intmask || intmask == 0xffffffff) {
2770 result = IRQ_NONE;
2771 goto out;
2772 }
2773
2774 do {
2775 DBG("IRQ status 0x%08x\n", intmask);
2776
2777 if (host->ops->irq) {
2778 intmask = host->ops->irq(host, intmask);
2779 if (!intmask)
2780 goto cont;
2781 }
2782
2783 /* Clear selected interrupts. */
2784 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2785 SDHCI_INT_BUS_POWER);
2786 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2787
2788 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2789 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2790 SDHCI_CARD_PRESENT;
2791
2792 /*
2793 * There is a observation on i.mx esdhc. INSERT
2794 * bit will be immediately set again when it gets
2795 * cleared, if a card is inserted. We have to mask
2796 * the irq to prevent interrupt storm which will
2797 * freeze the system. And the REMOVE gets the
2798 * same situation.
2799 *
2800 * More testing are needed here to ensure it works
2801 * for other platforms though.
2802 */
2803 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2804 SDHCI_INT_CARD_REMOVE);
2805 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2806 SDHCI_INT_CARD_INSERT;
2807 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2808 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2809
2810 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2811 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2812
2813 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2814 SDHCI_INT_CARD_REMOVE);
2815 result = IRQ_WAKE_THREAD;
2816 }
2817
2818 if (intmask & SDHCI_INT_CMD_MASK)
2819 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2820
2821 if (intmask & SDHCI_INT_DATA_MASK)
2822 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2823
2824 if (intmask & SDHCI_INT_BUS_POWER)
2825 pr_err("%s: Card is consuming too much power!\n",
2826 mmc_hostname(host->mmc));
2827
2828 if (intmask & SDHCI_INT_RETUNE)
2829 mmc_retune_needed(host->mmc);
2830
2831 if ((intmask & SDHCI_INT_CARD_INT) &&
2832 (host->ier & SDHCI_INT_CARD_INT)) {
2833 sdhci_enable_sdio_irq_nolock(host, false);
2834 host->thread_isr |= SDHCI_INT_CARD_INT;
2835 result = IRQ_WAKE_THREAD;
2836 }
2837
2838 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2839 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2840 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2841 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2842
2843 if (intmask) {
2844 unexpected |= intmask;
2845 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2846 }
2847cont:
2848 if (result == IRQ_NONE)
2849 result = IRQ_HANDLED;
2850
2851 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2852 } while (intmask && --max_loops);
2853out:
2854 spin_unlock(&host->lock);
2855
2856 if (unexpected) {
2857 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2858 mmc_hostname(host->mmc), unexpected);
2859 sdhci_dumpregs(host);
2860 }
2861
2862 return result;
2863}
2864
2865static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2866{
2867 struct sdhci_host *host = dev_id;
2868 unsigned long flags;
2869 u32 isr;
2870
2871 spin_lock_irqsave(&host->lock, flags);
2872 isr = host->thread_isr;
2873 host->thread_isr = 0;
2874 spin_unlock_irqrestore(&host->lock, flags);
2875
2876 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2877 struct mmc_host *mmc = host->mmc;
2878
2879 mmc->ops->card_event(mmc);
2880 mmc_detect_change(mmc, msecs_to_jiffies(200));
2881 }
2882
2883 if (isr & SDHCI_INT_CARD_INT) {
2884 sdio_run_irqs(host->mmc);
2885
2886 spin_lock_irqsave(&host->lock, flags);
2887 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2888 sdhci_enable_sdio_irq_nolock(host, true);
2889 spin_unlock_irqrestore(&host->lock, flags);
2890 }
2891
2892 return isr ? IRQ_HANDLED : IRQ_NONE;
2893}
2894
2895/*****************************************************************************\
2896 * *
2897 * Suspend/resume *
2898 * *
2899\*****************************************************************************/
2900
2901#ifdef CONFIG_PM
2902
2903static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
2904{
2905 return mmc_card_is_removable(host->mmc) &&
2906 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2907 !mmc_can_gpio_cd(host->mmc);
2908}
2909
2910/*
2911 * To enable wakeup events, the corresponding events have to be enabled in
2912 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2913 * Table' in the SD Host Controller Standard Specification.
2914 * It is useless to restore SDHCI_INT_ENABLE state in
2915 * sdhci_disable_irq_wakeups() since it will be set by
2916 * sdhci_enable_card_detection() or sdhci_init().
2917 */
2918static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
2919{
2920 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
2921 SDHCI_WAKE_ON_INT;
2922 u32 irq_val = 0;
2923 u8 wake_val = 0;
2924 u8 val;
2925
2926 if (sdhci_cd_irq_can_wakeup(host)) {
2927 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
2928 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
2929 }
2930
2931 if (mmc_card_wake_sdio_irq(host->mmc)) {
2932 wake_val |= SDHCI_WAKE_ON_INT;
2933 irq_val |= SDHCI_INT_CARD_INT;
2934 }
2935
2936 if (!irq_val)
2937 return false;
2938
2939 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2940 val &= ~mask;
2941 val |= wake_val;
2942 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2943
2944 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2945
2946 host->irq_wake_enabled = !enable_irq_wake(host->irq);
2947
2948 return host->irq_wake_enabled;
2949}
2950
2951static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2952{
2953 u8 val;
2954 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2955 | SDHCI_WAKE_ON_INT;
2956
2957 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2958 val &= ~mask;
2959 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2960
2961 disable_irq_wake(host->irq);
2962
2963 host->irq_wake_enabled = false;
2964}
2965
2966int sdhci_suspend_host(struct sdhci_host *host)
2967{
2968 sdhci_disable_card_detection(host);
2969
2970 mmc_retune_timer_stop(host->mmc);
2971
2972 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
2973 !sdhci_enable_irq_wakeups(host)) {
2974 host->ier = 0;
2975 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2976 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2977 free_irq(host->irq, host);
2978 }
2979
2980 return 0;
2981}
2982
2983EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2984
2985int sdhci_resume_host(struct sdhci_host *host)
2986{
2987 struct mmc_host *mmc = host->mmc;
2988 int ret = 0;
2989
2990 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2991 if (host->ops->enable_dma)
2992 host->ops->enable_dma(host);
2993 }
2994
2995 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2996 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2997 /* Card keeps power but host controller does not */
2998 sdhci_init(host, 0);
2999 host->pwr = 0;
3000 host->clock = 0;
3001 mmc->ops->set_ios(mmc, &mmc->ios);
3002 } else {
3003 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3004 mmiowb();
3005 }
3006
3007 if (host->irq_wake_enabled) {
3008 sdhci_disable_irq_wakeups(host);
3009 } else {
3010 ret = request_threaded_irq(host->irq, sdhci_irq,
3011 sdhci_thread_irq, IRQF_SHARED,
3012 mmc_hostname(host->mmc), host);
3013 if (ret)
3014 return ret;
3015 }
3016
3017 sdhci_enable_card_detection(host);
3018
3019 return ret;
3020}
3021
3022EXPORT_SYMBOL_GPL(sdhci_resume_host);
3023
3024int sdhci_runtime_suspend_host(struct sdhci_host *host)
3025{
3026 unsigned long flags;
3027
3028 mmc_retune_timer_stop(host->mmc);
3029
3030 spin_lock_irqsave(&host->lock, flags);
3031 host->ier &= SDHCI_INT_CARD_INT;
3032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3034 spin_unlock_irqrestore(&host->lock, flags);
3035
3036 synchronize_hardirq(host->irq);
3037
3038 spin_lock_irqsave(&host->lock, flags);
3039 host->runtime_suspended = true;
3040 spin_unlock_irqrestore(&host->lock, flags);
3041
3042 return 0;
3043}
3044EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3045
3046int sdhci_runtime_resume_host(struct sdhci_host *host)
3047{
3048 struct mmc_host *mmc = host->mmc;
3049 unsigned long flags;
3050 int host_flags = host->flags;
3051
3052 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3053 if (host->ops->enable_dma)
3054 host->ops->enable_dma(host);
3055 }
3056
3057 sdhci_init(host, 0);
3058
3059 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3060 mmc->ios.power_mode != MMC_POWER_OFF) {
3061 /* Force clock and power re-program */
3062 host->pwr = 0;
3063 host->clock = 0;
3064 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3065 mmc->ops->set_ios(mmc, &mmc->ios);
3066
3067 if ((host_flags & SDHCI_PV_ENABLED) &&
3068 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3069 spin_lock_irqsave(&host->lock, flags);
3070 sdhci_enable_preset_value(host, true);
3071 spin_unlock_irqrestore(&host->lock, flags);
3072 }
3073
3074 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3075 mmc->ops->hs400_enhanced_strobe)
3076 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3077 }
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 host->runtime_suspended = false;
3082
3083 /* Enable SDIO IRQ */
3084 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3085 sdhci_enable_sdio_irq_nolock(host, true);
3086
3087 /* Enable Card Detection */
3088 sdhci_enable_card_detection(host);
3089
3090 spin_unlock_irqrestore(&host->lock, flags);
3091
3092 return 0;
3093}
3094EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3095
3096#endif /* CONFIG_PM */
3097
3098/*****************************************************************************\
3099 * *
3100 * Command Queue Engine (CQE) helpers *
3101 * *
3102\*****************************************************************************/
3103
3104void sdhci_cqe_enable(struct mmc_host *mmc)
3105{
3106 struct sdhci_host *host = mmc_priv(mmc);
3107 unsigned long flags;
3108 u8 ctrl;
3109
3110 spin_lock_irqsave(&host->lock, flags);
3111
3112 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3113 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3114 if (host->flags & SDHCI_USE_64_BIT_DMA)
3115 ctrl |= SDHCI_CTRL_ADMA64;
3116 else
3117 ctrl |= SDHCI_CTRL_ADMA32;
3118 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3119
3120 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3121 SDHCI_BLOCK_SIZE);
3122
3123 /* Set maximum timeout */
3124 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3125
3126 host->ier = host->cqe_ier;
3127
3128 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3129 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3130
3131 host->cqe_on = true;
3132
3133 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3134 mmc_hostname(mmc), host->ier,
3135 sdhci_readl(host, SDHCI_INT_STATUS));
3136
3137 mmiowb();
3138 spin_unlock_irqrestore(&host->lock, flags);
3139}
3140EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3141
3142void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3143{
3144 struct sdhci_host *host = mmc_priv(mmc);
3145 unsigned long flags;
3146
3147 spin_lock_irqsave(&host->lock, flags);
3148
3149 sdhci_set_default_irqs(host);
3150
3151 host->cqe_on = false;
3152
3153 if (recovery) {
3154 sdhci_do_reset(host, SDHCI_RESET_CMD);
3155 sdhci_do_reset(host, SDHCI_RESET_DATA);
3156 }
3157
3158 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3159 mmc_hostname(mmc), host->ier,
3160 sdhci_readl(host, SDHCI_INT_STATUS));
3161
3162 mmiowb();
3163 spin_unlock_irqrestore(&host->lock, flags);
3164}
3165EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3166
3167bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3168 int *data_error)
3169{
3170 u32 mask;
3171
3172 if (!host->cqe_on)
3173 return false;
3174
3175 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3176 *cmd_error = -EILSEQ;
3177 else if (intmask & SDHCI_INT_TIMEOUT)
3178 *cmd_error = -ETIMEDOUT;
3179 else
3180 *cmd_error = 0;
3181
3182 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3183 *data_error = -EILSEQ;
3184 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3185 *data_error = -ETIMEDOUT;
3186 else if (intmask & SDHCI_INT_ADMA_ERROR)
3187 *data_error = -EIO;
3188 else
3189 *data_error = 0;
3190
3191 /* Clear selected interrupts. */
3192 mask = intmask & host->cqe_ier;
3193 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3194
3195 if (intmask & SDHCI_INT_BUS_POWER)
3196 pr_err("%s: Card is consuming too much power!\n",
3197 mmc_hostname(host->mmc));
3198
3199 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3200 if (intmask) {
3201 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3202 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3203 mmc_hostname(host->mmc), intmask);
3204 sdhci_dumpregs(host);
3205 }
3206
3207 return true;
3208}
3209EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3210
3211/*****************************************************************************\
3212 * *
3213 * Device allocation/registration *
3214 * *
3215\*****************************************************************************/
3216
3217struct sdhci_host *sdhci_alloc_host(struct device *dev,
3218 size_t priv_size)
3219{
3220 struct mmc_host *mmc;
3221 struct sdhci_host *host;
3222
3223 WARN_ON(dev == NULL);
3224
3225 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3226 if (!mmc)
3227 return ERR_PTR(-ENOMEM);
3228
3229 host = mmc_priv(mmc);
3230 host->mmc = mmc;
3231 host->mmc_host_ops = sdhci_ops;
3232 mmc->ops = &host->mmc_host_ops;
3233
3234 host->flags = SDHCI_SIGNALING_330;
3235
3236 host->cqe_ier = SDHCI_CQE_INT_MASK;
3237 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3238
3239 host->tuning_delay = -1;
3240
3241 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3242
3243 return host;
3244}
3245
3246EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3247
3248static int sdhci_set_dma_mask(struct sdhci_host *host)
3249{
3250 struct mmc_host *mmc = host->mmc;
3251 struct device *dev = mmc_dev(mmc);
3252 int ret = -EINVAL;
3253
3254 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3255 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3256
3257 /* Try 64-bit mask if hardware is capable of it */
3258 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3259 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3260 if (ret) {
3261 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3262 mmc_hostname(mmc));
3263 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3264 }
3265 }
3266
3267 /* 32-bit mask as default & fallback */
3268 if (ret) {
3269 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3270 if (ret)
3271 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3272 mmc_hostname(mmc));
3273 }
3274
3275 return ret;
3276}
3277
3278void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3279{
3280 u16 v;
3281 u64 dt_caps_mask = 0;
3282 u64 dt_caps = 0;
3283
3284 if (host->read_caps)
3285 return;
3286
3287 host->read_caps = true;
3288
3289 if (debug_quirks)
3290 host->quirks = debug_quirks;
3291
3292 if (debug_quirks2)
3293 host->quirks2 = debug_quirks2;
3294
3295 sdhci_do_reset(host, SDHCI_RESET_ALL);
3296
3297 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3298 "sdhci-caps-mask", &dt_caps_mask);
3299 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3300 "sdhci-caps", &dt_caps);
3301
3302 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3303 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3304
3305 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3306 return;
3307
3308 if (caps) {
3309 host->caps = *caps;
3310 } else {
3311 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3312 host->caps &= ~lower_32_bits(dt_caps_mask);
3313 host->caps |= lower_32_bits(dt_caps);
3314 }
3315
3316 if (host->version < SDHCI_SPEC_300)
3317 return;
3318
3319 if (caps1) {
3320 host->caps1 = *caps1;
3321 } else {
3322 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3323 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3324 host->caps1 |= upper_32_bits(dt_caps);
3325 }
3326}
3327EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3328
3329static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3330{
3331 struct mmc_host *mmc = host->mmc;
3332 unsigned int max_blocks;
3333 unsigned int bounce_size;
3334 int ret;
3335
3336 /*
3337 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3338 * has diminishing returns, this is probably because SD/MMC
3339 * cards are usually optimized to handle this size of requests.
3340 */
3341 bounce_size = SZ_64K;
3342 /*
3343 * Adjust downwards to maximum request size if this is less
3344 * than our segment size, else hammer down the maximum
3345 * request size to the maximum buffer size.
3346 */
3347 if (mmc->max_req_size < bounce_size)
3348 bounce_size = mmc->max_req_size;
3349 max_blocks = bounce_size / 512;
3350
3351 /*
3352 * When we just support one segment, we can get significant
3353 * speedups by the help of a bounce buffer to group scattered
3354 * reads/writes together.
3355 */
3356 host->bounce_buffer = devm_kmalloc(mmc->parent,
3357 bounce_size,
3358 GFP_KERNEL);
3359 if (!host->bounce_buffer) {
3360 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3361 mmc_hostname(mmc),
3362 bounce_size);
3363 /*
3364 * Exiting with zero here makes sure we proceed with
3365 * mmc->max_segs == 1.
3366 */
3367 return 0;
3368 }
3369
3370 host->bounce_addr = dma_map_single(mmc->parent,
3371 host->bounce_buffer,
3372 bounce_size,
3373 DMA_BIDIRECTIONAL);
3374 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3375 if (ret)
3376 /* Again fall back to max_segs == 1 */
3377 return 0;
3378 host->bounce_buffer_size = bounce_size;
3379
3380 /* Lie about this since we're bouncing */
3381 mmc->max_segs = max_blocks;
3382 mmc->max_seg_size = bounce_size;
3383 mmc->max_req_size = bounce_size;
3384
3385 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3386 mmc_hostname(mmc), max_blocks, bounce_size);
3387
3388 return 0;
3389}
3390
3391int sdhci_setup_host(struct sdhci_host *host)
3392{
3393 struct mmc_host *mmc;
3394 u32 max_current_caps;
3395 unsigned int ocr_avail;
3396 unsigned int override_timeout_clk;
3397 u32 max_clk;
3398 int ret;
3399
3400 WARN_ON(host == NULL);
3401 if (host == NULL)
3402 return -EINVAL;
3403
3404 mmc = host->mmc;
3405
3406 /*
3407 * If there are external regulators, get them. Note this must be done
3408 * early before resetting the host and reading the capabilities so that
3409 * the host can take the appropriate action if regulators are not
3410 * available.
3411 */
3412 ret = mmc_regulator_get_supply(mmc);
3413 if (ret)
3414 return ret;
3415
3416 DBG("Version: 0x%08x | Present: 0x%08x\n",
3417 sdhci_readw(host, SDHCI_HOST_VERSION),
3418 sdhci_readl(host, SDHCI_PRESENT_STATE));
3419 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3420 sdhci_readl(host, SDHCI_CAPABILITIES),
3421 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3422
3423 sdhci_read_caps(host);
3424
3425 override_timeout_clk = host->timeout_clk;
3426
3427 if (host->version > SDHCI_SPEC_300) {
3428 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3429 mmc_hostname(mmc), host->version);
3430 }
3431
3432 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3433 host->flags |= SDHCI_USE_SDMA;
3434 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3435 DBG("Controller doesn't have SDMA capability\n");
3436 else
3437 host->flags |= SDHCI_USE_SDMA;
3438
3439 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3440 (host->flags & SDHCI_USE_SDMA)) {
3441 DBG("Disabling DMA as it is marked broken\n");
3442 host->flags &= ~SDHCI_USE_SDMA;
3443 }
3444
3445 if ((host->version >= SDHCI_SPEC_200) &&
3446 (host->caps & SDHCI_CAN_DO_ADMA2))
3447 host->flags |= SDHCI_USE_ADMA;
3448
3449 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3450 (host->flags & SDHCI_USE_ADMA)) {
3451 DBG("Disabling ADMA as it is marked broken\n");
3452 host->flags &= ~SDHCI_USE_ADMA;
3453 }
3454
3455 /*
3456 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3457 * and *must* do 64-bit DMA. A driver has the opportunity to change
3458 * that during the first call to ->enable_dma(). Similarly
3459 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3460 * implement.
3461 */
3462 if (host->caps & SDHCI_CAN_64BIT)
3463 host->flags |= SDHCI_USE_64_BIT_DMA;
3464
3465 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3466 ret = sdhci_set_dma_mask(host);
3467
3468 if (!ret && host->ops->enable_dma)
3469 ret = host->ops->enable_dma(host);
3470
3471 if (ret) {
3472 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3473 mmc_hostname(mmc));
3474 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3475
3476 ret = 0;
3477 }
3478 }
3479
3480 /* SDMA does not support 64-bit DMA */
3481 if (host->flags & SDHCI_USE_64_BIT_DMA)
3482 host->flags &= ~SDHCI_USE_SDMA;
3483
3484 if (host->flags & SDHCI_USE_ADMA) {
3485 dma_addr_t dma;
3486 void *buf;
3487
3488 /*
3489 * The DMA descriptor table size is calculated as the maximum
3490 * number of segments times 2, to allow for an alignment
3491 * descriptor for each segment, plus 1 for a nop end descriptor,
3492 * all multipled by the descriptor size.
3493 */
3494 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3495 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3496 SDHCI_ADMA2_64_DESC_SZ;
3497 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3498 } else {
3499 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3500 SDHCI_ADMA2_32_DESC_SZ;
3501 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3502 }
3503
3504 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3505 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3506 host->adma_table_sz, &dma, GFP_KERNEL);
3507 if (!buf) {
3508 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3509 mmc_hostname(mmc));
3510 host->flags &= ~SDHCI_USE_ADMA;
3511 } else if ((dma + host->align_buffer_sz) &
3512 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3513 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3514 mmc_hostname(mmc));
3515 host->flags &= ~SDHCI_USE_ADMA;
3516 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3517 host->adma_table_sz, buf, dma);
3518 } else {
3519 host->align_buffer = buf;
3520 host->align_addr = dma;
3521
3522 host->adma_table = buf + host->align_buffer_sz;
3523 host->adma_addr = dma + host->align_buffer_sz;
3524 }
3525 }
3526
3527 /*
3528 * If we use DMA, then it's up to the caller to set the DMA
3529 * mask, but PIO does not need the hw shim so we set a new
3530 * mask here in that case.
3531 */
3532 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3533 host->dma_mask = DMA_BIT_MASK(64);
3534 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3535 }
3536
3537 if (host->version >= SDHCI_SPEC_300)
3538 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3539 >> SDHCI_CLOCK_BASE_SHIFT;
3540 else
3541 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3542 >> SDHCI_CLOCK_BASE_SHIFT;
3543
3544 host->max_clk *= 1000000;
3545 if (host->max_clk == 0 || host->quirks &
3546 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3547 if (!host->ops->get_max_clock) {
3548 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3549 mmc_hostname(mmc));
3550 ret = -ENODEV;
3551 goto undma;
3552 }
3553 host->max_clk = host->ops->get_max_clock(host);
3554 }
3555
3556 /*
3557 * In case of Host Controller v3.00, find out whether clock
3558 * multiplier is supported.
3559 */
3560 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3561 SDHCI_CLOCK_MUL_SHIFT;
3562
3563 /*
3564 * In case the value in Clock Multiplier is 0, then programmable
3565 * clock mode is not supported, otherwise the actual clock
3566 * multiplier is one more than the value of Clock Multiplier
3567 * in the Capabilities Register.
3568 */
3569 if (host->clk_mul)
3570 host->clk_mul += 1;
3571
3572 /*
3573 * Set host parameters.
3574 */
3575 max_clk = host->max_clk;
3576
3577 if (host->ops->get_min_clock)
3578 mmc->f_min = host->ops->get_min_clock(host);
3579 else if (host->version >= SDHCI_SPEC_300) {
3580 if (host->clk_mul) {
3581 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3582 max_clk = host->max_clk * host->clk_mul;
3583 } else
3584 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3585 } else
3586 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3587
3588 if (!mmc->f_max || mmc->f_max > max_clk)
3589 mmc->f_max = max_clk;
3590
3591 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3592 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3593 SDHCI_TIMEOUT_CLK_SHIFT;
3594
3595 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3596 host->timeout_clk *= 1000;
3597
3598 if (host->timeout_clk == 0) {
3599 if (!host->ops->get_timeout_clock) {
3600 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3601 mmc_hostname(mmc));
3602 ret = -ENODEV;
3603 goto undma;
3604 }
3605
3606 host->timeout_clk =
3607 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3608 1000);
3609 }
3610
3611 if (override_timeout_clk)
3612 host->timeout_clk = override_timeout_clk;
3613
3614 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3615 host->ops->get_max_timeout_count(host) : 1 << 27;
3616 mmc->max_busy_timeout /= host->timeout_clk;
3617 }
3618
3619 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3620 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3621
3622 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3623 host->flags |= SDHCI_AUTO_CMD12;
3624
3625 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3626 if ((host->version >= SDHCI_SPEC_300) &&
3627 ((host->flags & SDHCI_USE_ADMA) ||
3628 !(host->flags & SDHCI_USE_SDMA)) &&
3629 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3630 host->flags |= SDHCI_AUTO_CMD23;
3631 DBG("Auto-CMD23 available\n");
3632 } else {
3633 DBG("Auto-CMD23 unavailable\n");
3634 }
3635
3636 /*
3637 * A controller may support 8-bit width, but the board itself
3638 * might not have the pins brought out. Boards that support
3639 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3640 * their platform code before calling sdhci_add_host(), and we
3641 * won't assume 8-bit width for hosts without that CAP.
3642 */
3643 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3644 mmc->caps |= MMC_CAP_4_BIT_DATA;
3645
3646 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3647 mmc->caps &= ~MMC_CAP_CMD23;
3648
3649 if (host->caps & SDHCI_CAN_DO_HISPD)
3650 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3651
3652 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3653 mmc_card_is_removable(mmc) &&
3654 mmc_gpio_get_cd(host->mmc) < 0)
3655 mmc->caps |= MMC_CAP_NEEDS_POLL;
3656
3657 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3658 if (!IS_ERR(mmc->supply.vqmmc)) {
3659 ret = regulator_enable(mmc->supply.vqmmc);
3660 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3661 1950000))
3662 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3663 SDHCI_SUPPORT_SDR50 |
3664 SDHCI_SUPPORT_DDR50);
3665 if (ret) {
3666 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3667 mmc_hostname(mmc), ret);
3668 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3669 }
3670 }
3671
3672 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3673 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3674 SDHCI_SUPPORT_DDR50);
3675 }
3676
3677 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3678 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3679 SDHCI_SUPPORT_DDR50))
3680 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3681
3682 /* SDR104 supports also implies SDR50 support */
3683 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3684 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3685 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3686 * field can be promoted to support HS200.
3687 */
3688 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3689 mmc->caps2 |= MMC_CAP2_HS200;
3690 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3691 mmc->caps |= MMC_CAP_UHS_SDR50;
3692 }
3693
3694 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3695 (host->caps1 & SDHCI_SUPPORT_HS400))
3696 mmc->caps2 |= MMC_CAP2_HS400;
3697
3698 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3699 (IS_ERR(mmc->supply.vqmmc) ||
3700 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3701 1300000)))
3702 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3703
3704 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3705 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3706 mmc->caps |= MMC_CAP_UHS_DDR50;
3707
3708 /* Does the host need tuning for SDR50? */
3709 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3710 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3711
3712 /* Driver Type(s) (A, C, D) supported by the host */
3713 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3714 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3715 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3716 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3717 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3718 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3719
3720 /* Initial value for re-tuning timer count */
3721 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3722 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3723
3724 /*
3725 * In case Re-tuning Timer is not disabled, the actual value of
3726 * re-tuning timer will be 2 ^ (n - 1).
3727 */
3728 if (host->tuning_count)
3729 host->tuning_count = 1 << (host->tuning_count - 1);
3730
3731 /* Re-tuning mode supported by the Host Controller */
3732 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3733 SDHCI_RETUNING_MODE_SHIFT;
3734
3735 ocr_avail = 0;
3736
3737 /*
3738 * According to SD Host Controller spec v3.00, if the Host System
3739 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3740 * the value is meaningful only if Voltage Support in the Capabilities
3741 * register is set. The actual current value is 4 times the register
3742 * value.
3743 */
3744 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3745 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3746 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3747 if (curr > 0) {
3748
3749 /* convert to SDHCI_MAX_CURRENT format */
3750 curr = curr/1000; /* convert to mA */
3751 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3752
3753 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3754 max_current_caps =
3755 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3756 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3757 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3758 }
3759 }
3760
3761 if (host->caps & SDHCI_CAN_VDD_330) {
3762 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3763
3764 mmc->max_current_330 = ((max_current_caps &
3765 SDHCI_MAX_CURRENT_330_MASK) >>
3766 SDHCI_MAX_CURRENT_330_SHIFT) *
3767 SDHCI_MAX_CURRENT_MULTIPLIER;
3768 }
3769 if (host->caps & SDHCI_CAN_VDD_300) {
3770 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3771
3772 mmc->max_current_300 = ((max_current_caps &
3773 SDHCI_MAX_CURRENT_300_MASK) >>
3774 SDHCI_MAX_CURRENT_300_SHIFT) *
3775 SDHCI_MAX_CURRENT_MULTIPLIER;
3776 }
3777 if (host->caps & SDHCI_CAN_VDD_180) {
3778 ocr_avail |= MMC_VDD_165_195;
3779
3780 mmc->max_current_180 = ((max_current_caps &
3781 SDHCI_MAX_CURRENT_180_MASK) >>
3782 SDHCI_MAX_CURRENT_180_SHIFT) *
3783 SDHCI_MAX_CURRENT_MULTIPLIER;
3784 }
3785
3786 /* If OCR set by host, use it instead. */
3787 if (host->ocr_mask)
3788 ocr_avail = host->ocr_mask;
3789
3790 /* If OCR set by external regulators, give it highest prio. */
3791 if (mmc->ocr_avail)
3792 ocr_avail = mmc->ocr_avail;
3793
3794 mmc->ocr_avail = ocr_avail;
3795 mmc->ocr_avail_sdio = ocr_avail;
3796 if (host->ocr_avail_sdio)
3797 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3798 mmc->ocr_avail_sd = ocr_avail;
3799 if (host->ocr_avail_sd)
3800 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3801 else /* normal SD controllers don't support 1.8V */
3802 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3803 mmc->ocr_avail_mmc = ocr_avail;
3804 if (host->ocr_avail_mmc)
3805 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3806
3807 if (mmc->ocr_avail == 0) {
3808 pr_err("%s: Hardware doesn't report any support voltages.\n",
3809 mmc_hostname(mmc));
3810 ret = -ENODEV;
3811 goto unreg;
3812 }
3813
3814 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3815 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3816 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3817 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3818 host->flags |= SDHCI_SIGNALING_180;
3819
3820 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3821 host->flags |= SDHCI_SIGNALING_120;
3822
3823 spin_lock_init(&host->lock);
3824
3825 /*
3826 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3827 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3828 * is less anyway.
3829 */
3830 mmc->max_req_size = 524288;
3831
3832 /*
3833 * Maximum number of segments. Depends on if the hardware
3834 * can do scatter/gather or not.
3835 */
3836 if (host->flags & SDHCI_USE_ADMA) {
3837 mmc->max_segs = SDHCI_MAX_SEGS;
3838 } else if (host->flags & SDHCI_USE_SDMA) {
3839 mmc->max_segs = 1;
3840 if (swiotlb_max_segment()) {
3841 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3842 IO_TLB_SEGSIZE;
3843 mmc->max_req_size = min(mmc->max_req_size,
3844 max_req_size);
3845 }
3846 } else { /* PIO */
3847 mmc->max_segs = SDHCI_MAX_SEGS;
3848 }
3849
3850 /*
3851 * Maximum segment size. Could be one segment with the maximum number
3852 * of bytes. When doing hardware scatter/gather, each entry cannot
3853 * be larger than 64 KiB though.
3854 */
3855 if (host->flags & SDHCI_USE_ADMA) {
3856 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3857 mmc->max_seg_size = 65535;
3858 else
3859 mmc->max_seg_size = 65536;
3860 } else {
3861 mmc->max_seg_size = mmc->max_req_size;
3862 }
3863
3864 /*
3865 * Maximum block size. This varies from controller to controller and
3866 * is specified in the capabilities register.
3867 */
3868 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3869 mmc->max_blk_size = 2;
3870 } else {
3871 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3872 SDHCI_MAX_BLOCK_SHIFT;
3873 if (mmc->max_blk_size >= 3) {
3874 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3875 mmc_hostname(mmc));
3876 mmc->max_blk_size = 0;
3877 }
3878 }
3879
3880 mmc->max_blk_size = 512 << mmc->max_blk_size;
3881
3882 /*
3883 * Maximum block count.
3884 */
3885 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3886
3887 if (mmc->max_segs == 1) {
3888 /* This may alter mmc->*_blk_* parameters */
3889 ret = sdhci_allocate_bounce_buffer(host);
3890 if (ret)
3891 return ret;
3892 }
3893
3894 return 0;
3895
3896unreg:
3897 if (!IS_ERR(mmc->supply.vqmmc))
3898 regulator_disable(mmc->supply.vqmmc);
3899undma:
3900 if (host->align_buffer)
3901 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3902 host->adma_table_sz, host->align_buffer,
3903 host->align_addr);
3904 host->adma_table = NULL;
3905 host->align_buffer = NULL;
3906
3907 return ret;
3908}
3909EXPORT_SYMBOL_GPL(sdhci_setup_host);
3910
3911void sdhci_cleanup_host(struct sdhci_host *host)
3912{
3913 struct mmc_host *mmc = host->mmc;
3914
3915 if (!IS_ERR(mmc->supply.vqmmc))
3916 regulator_disable(mmc->supply.vqmmc);
3917
3918 if (host->align_buffer)
3919 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3920 host->adma_table_sz, host->align_buffer,
3921 host->align_addr);
3922 host->adma_table = NULL;
3923 host->align_buffer = NULL;
3924}
3925EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3926
3927int __sdhci_add_host(struct sdhci_host *host)
3928{
3929 struct mmc_host *mmc = host->mmc;
3930 int ret;
3931
3932 /*
3933 * Init tasklets.
3934 */
3935 tasklet_init(&host->finish_tasklet,
3936 sdhci_tasklet_finish, (unsigned long)host);
3937
3938 timer_setup(&host->timer, sdhci_timeout_timer, 0);
3939 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
3940
3941 init_waitqueue_head(&host->buf_ready_int);
3942
3943 sdhci_init(host, 0);
3944
3945 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3946 IRQF_SHARED, mmc_hostname(mmc), host);
3947 if (ret) {
3948 pr_err("%s: Failed to request IRQ %d: %d\n",
3949 mmc_hostname(mmc), host->irq, ret);
3950 goto untasklet;
3951 }
3952
3953 ret = sdhci_led_register(host);
3954 if (ret) {
3955 pr_err("%s: Failed to register LED device: %d\n",
3956 mmc_hostname(mmc), ret);
3957 goto unirq;
3958 }
3959
3960 mmiowb();
3961
3962 ret = mmc_add_host(mmc);
3963 if (ret)
3964 goto unled;
3965
3966 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3967 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3968 (host->flags & SDHCI_USE_ADMA) ?
3969 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3970 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3971
3972 sdhci_enable_card_detection(host);
3973
3974 return 0;
3975
3976unled:
3977 sdhci_led_unregister(host);
3978unirq:
3979 sdhci_do_reset(host, SDHCI_RESET_ALL);
3980 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3981 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3982 free_irq(host->irq, host);
3983untasklet:
3984 tasklet_kill(&host->finish_tasklet);
3985
3986 return ret;
3987}
3988EXPORT_SYMBOL_GPL(__sdhci_add_host);
3989
3990int sdhci_add_host(struct sdhci_host *host)
3991{
3992 int ret;
3993
3994 ret = sdhci_setup_host(host);
3995 if (ret)
3996 return ret;
3997
3998 ret = __sdhci_add_host(host);
3999 if (ret)
4000 goto cleanup;
4001
4002 return 0;
4003
4004cleanup:
4005 sdhci_cleanup_host(host);
4006
4007 return ret;
4008}
4009EXPORT_SYMBOL_GPL(sdhci_add_host);
4010
4011void sdhci_remove_host(struct sdhci_host *host, int dead)
4012{
4013 struct mmc_host *mmc = host->mmc;
4014 unsigned long flags;
4015
4016 if (dead) {
4017 spin_lock_irqsave(&host->lock, flags);
4018
4019 host->flags |= SDHCI_DEVICE_DEAD;
4020
4021 if (sdhci_has_requests(host)) {
4022 pr_err("%s: Controller removed during "
4023 " transfer!\n", mmc_hostname(mmc));
4024 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4025 }
4026
4027 spin_unlock_irqrestore(&host->lock, flags);
4028 }
4029
4030 sdhci_disable_card_detection(host);
4031
4032 mmc_remove_host(mmc);
4033
4034 sdhci_led_unregister(host);
4035
4036 if (!dead)
4037 sdhci_do_reset(host, SDHCI_RESET_ALL);
4038
4039 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4040 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4041 free_irq(host->irq, host);
4042
4043 del_timer_sync(&host->timer);
4044 del_timer_sync(&host->data_timer);
4045
4046 tasklet_kill(&host->finish_tasklet);
4047
4048 if (!IS_ERR(mmc->supply.vqmmc))
4049 regulator_disable(mmc->supply.vqmmc);
4050
4051 if (host->align_buffer)
4052 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4053 host->adma_table_sz, host->align_buffer,
4054 host->align_addr);
4055
4056 host->adma_table = NULL;
4057 host->align_buffer = NULL;
4058}
4059
4060EXPORT_SYMBOL_GPL(sdhci_remove_host);
4061
4062void sdhci_free_host(struct sdhci_host *host)
4063{
4064 mmc_free_host(host->mmc);
4065}
4066
4067EXPORT_SYMBOL_GPL(sdhci_free_host);
4068
4069/*****************************************************************************\
4070 * *
4071 * Driver init/exit *
4072 * *
4073\*****************************************************************************/
4074
4075static int __init sdhci_drv_init(void)
4076{
4077 pr_info(DRIVER_NAME
4078 ": Secure Digital Host Controller Interface driver\n");
4079 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4080
4081 return 0;
4082}
4083
4084static void __exit sdhci_drv_exit(void)
4085{
4086}
4087
4088module_init(sdhci_drv_init);
4089module_exit(sdhci_drv_exit);
4090
4091module_param(debug_quirks, uint, 0444);
4092module_param(debug_quirks2, uint, 0444);
4093
4094MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4095MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4096MODULE_LICENSE("GPL");
4097
4098MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4099MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/io.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/regulator/consumer.h>
23
24#include <linux/leds.h>
25
26#include <linux/mmc/mmc.h>
27#include <linux/mmc/host.h>
28
29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
32
33#define DBG(f, x...) \
34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
35
36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
41#define MAX_TUNING_LOOP 40
42
43static unsigned int debug_quirks = 0;
44
45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
49static int sdhci_execute_tuning(struct mmc_host *mmc);
50static void sdhci_tuning_timer(unsigned long data);
51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
56
57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
85 sdhci_readl(host, SDHCI_CAPABILITIES),
86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
89 sdhci_readl(host, SDHCI_MAX_CURRENT));
90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
92
93 if (host->flags & SDHCI_USE_ADMA)
94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97
98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
99}
100
101/*****************************************************************************\
102 * *
103 * Low level functions *
104 * *
105\*****************************************************************************/
106
107static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
108{
109 u32 ier;
110
111 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
112 ier &= ~clear;
113 ier |= set;
114 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
116}
117
118static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, 0, irqs);
121}
122
123static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
124{
125 sdhci_clear_set_irqs(host, irqs, 0);
126}
127
128static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
129{
130 u32 present, irqs;
131
132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
133 return;
134
135 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
136 SDHCI_CARD_PRESENT;
137 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
138
139 if (enable)
140 sdhci_unmask_irqs(host, irqs);
141 else
142 sdhci_mask_irqs(host, irqs);
143}
144
145static void sdhci_enable_card_detection(struct sdhci_host *host)
146{
147 sdhci_set_card_detection(host, true);
148}
149
150static void sdhci_disable_card_detection(struct sdhci_host *host)
151{
152 sdhci_set_card_detection(host, false);
153}
154
155static void sdhci_reset(struct sdhci_host *host, u8 mask)
156{
157 unsigned long timeout;
158 u32 uninitialized_var(ier);
159
160 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
161 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
162 SDHCI_CARD_PRESENT))
163 return;
164 }
165
166 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
167 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
168
169 if (host->ops->platform_reset_enter)
170 host->ops->platform_reset_enter(host, mask);
171
172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
173
174 if (mask & SDHCI_RESET_ALL)
175 host->clock = 0;
176
177 /* Wait max 100 ms */
178 timeout = 100;
179
180 /* hw clears the bit when it's done */
181 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
182 if (timeout == 0) {
183 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
186 return;
187 }
188 timeout--;
189 mdelay(1);
190 }
191
192 if (host->ops->platform_reset_exit)
193 host->ops->platform_reset_exit(host, mask);
194
195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
197}
198
199static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
200
201static void sdhci_init(struct sdhci_host *host, int soft)
202{
203 if (soft)
204 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
205 else
206 sdhci_reset(host, SDHCI_RESET_ALL);
207
208 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
209 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
210 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
211 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
212 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
213
214 if (soft) {
215 /* force clock reconfiguration */
216 host->clock = 0;
217 sdhci_set_ios(host->mmc, &host->mmc->ios);
218 }
219}
220
221static void sdhci_reinit(struct sdhci_host *host)
222{
223 sdhci_init(host, 0);
224 sdhci_enable_card_detection(host);
225}
226
227static void sdhci_activate_led(struct sdhci_host *host)
228{
229 u8 ctrl;
230
231 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
232 ctrl |= SDHCI_CTRL_LED;
233 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
234}
235
236static void sdhci_deactivate_led(struct sdhci_host *host)
237{
238 u8 ctrl;
239
240 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
241 ctrl &= ~SDHCI_CTRL_LED;
242 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
243}
244
245#ifdef SDHCI_USE_LEDS_CLASS
246static void sdhci_led_control(struct led_classdev *led,
247 enum led_brightness brightness)
248{
249 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
250 unsigned long flags;
251
252 spin_lock_irqsave(&host->lock, flags);
253
254 if (brightness == LED_OFF)
255 sdhci_deactivate_led(host);
256 else
257 sdhci_activate_led(host);
258
259 spin_unlock_irqrestore(&host->lock, flags);
260}
261#endif
262
263/*****************************************************************************\
264 * *
265 * Core functions *
266 * *
267\*****************************************************************************/
268
269static void sdhci_read_block_pio(struct sdhci_host *host)
270{
271 unsigned long flags;
272 size_t blksize, len, chunk;
273 u32 uninitialized_var(scratch);
274 u8 *buf;
275
276 DBG("PIO reading\n");
277
278 blksize = host->data->blksz;
279 chunk = 0;
280
281 local_irq_save(flags);
282
283 while (blksize) {
284 if (!sg_miter_next(&host->sg_miter))
285 BUG();
286
287 len = min(host->sg_miter.length, blksize);
288
289 blksize -= len;
290 host->sg_miter.consumed = len;
291
292 buf = host->sg_miter.addr;
293
294 while (len) {
295 if (chunk == 0) {
296 scratch = sdhci_readl(host, SDHCI_BUFFER);
297 chunk = 4;
298 }
299
300 *buf = scratch & 0xFF;
301
302 buf++;
303 scratch >>= 8;
304 chunk--;
305 len--;
306 }
307 }
308
309 sg_miter_stop(&host->sg_miter);
310
311 local_irq_restore(flags);
312}
313
314static void sdhci_write_block_pio(struct sdhci_host *host)
315{
316 unsigned long flags;
317 size_t blksize, len, chunk;
318 u32 scratch;
319 u8 *buf;
320
321 DBG("PIO writing\n");
322
323 blksize = host->data->blksz;
324 chunk = 0;
325 scratch = 0;
326
327 local_irq_save(flags);
328
329 while (blksize) {
330 if (!sg_miter_next(&host->sg_miter))
331 BUG();
332
333 len = min(host->sg_miter.length, blksize);
334
335 blksize -= len;
336 host->sg_miter.consumed = len;
337
338 buf = host->sg_miter.addr;
339
340 while (len) {
341 scratch |= (u32)*buf << (chunk * 8);
342
343 buf++;
344 chunk++;
345 len--;
346
347 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
348 sdhci_writel(host, scratch, SDHCI_BUFFER);
349 chunk = 0;
350 scratch = 0;
351 }
352 }
353 }
354
355 sg_miter_stop(&host->sg_miter);
356
357 local_irq_restore(flags);
358}
359
360static void sdhci_transfer_pio(struct sdhci_host *host)
361{
362 u32 mask;
363
364 BUG_ON(!host->data);
365
366 if (host->blocks == 0)
367 return;
368
369 if (host->data->flags & MMC_DATA_READ)
370 mask = SDHCI_DATA_AVAILABLE;
371 else
372 mask = SDHCI_SPACE_AVAILABLE;
373
374 /*
375 * Some controllers (JMicron JMB38x) mess up the buffer bits
376 * for transfers < 4 bytes. As long as it is just one block,
377 * we can ignore the bits.
378 */
379 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
380 (host->data->blocks == 1))
381 mask = ~0;
382
383 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
384 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
385 udelay(100);
386
387 if (host->data->flags & MMC_DATA_READ)
388 sdhci_read_block_pio(host);
389 else
390 sdhci_write_block_pio(host);
391
392 host->blocks--;
393 if (host->blocks == 0)
394 break;
395 }
396
397 DBG("PIO transfer complete.\n");
398}
399
400static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
401{
402 local_irq_save(*flags);
403 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
404}
405
406static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
407{
408 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
409 local_irq_restore(*flags);
410}
411
412static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
413{
414 __le32 *dataddr = (__le32 __force *)(desc + 4);
415 __le16 *cmdlen = (__le16 __force *)desc;
416
417 /* SDHCI specification says ADMA descriptors should be 4 byte
418 * aligned, so using 16 or 32bit operations should be safe. */
419
420 cmdlen[0] = cpu_to_le16(cmd);
421 cmdlen[1] = cpu_to_le16(len);
422
423 dataddr[0] = cpu_to_le32(addr);
424}
425
426static int sdhci_adma_table_pre(struct sdhci_host *host,
427 struct mmc_data *data)
428{
429 int direction;
430
431 u8 *desc;
432 u8 *align;
433 dma_addr_t addr;
434 dma_addr_t align_addr;
435 int len, offset;
436
437 struct scatterlist *sg;
438 int i;
439 char *buffer;
440 unsigned long flags;
441
442 /*
443 * The spec does not specify endianness of descriptor table.
444 * We currently guess that it is LE.
445 */
446
447 if (data->flags & MMC_DATA_READ)
448 direction = DMA_FROM_DEVICE;
449 else
450 direction = DMA_TO_DEVICE;
451
452 /*
453 * The ADMA descriptor table is mapped further down as we
454 * need to fill it with data first.
455 */
456
457 host->align_addr = dma_map_single(mmc_dev(host->mmc),
458 host->align_buffer, 128 * 4, direction);
459 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
460 goto fail;
461 BUG_ON(host->align_addr & 0x3);
462
463 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
464 data->sg, data->sg_len, direction);
465 if (host->sg_count == 0)
466 goto unmap_align;
467
468 desc = host->adma_desc;
469 align = host->align_buffer;
470
471 align_addr = host->align_addr;
472
473 for_each_sg(data->sg, sg, host->sg_count, i) {
474 addr = sg_dma_address(sg);
475 len = sg_dma_len(sg);
476
477 /*
478 * The SDHCI specification states that ADMA
479 * addresses must be 32-bit aligned. If they
480 * aren't, then we use a bounce buffer for
481 * the (up to three) bytes that screw up the
482 * alignment.
483 */
484 offset = (4 - (addr & 0x3)) & 0x3;
485 if (offset) {
486 if (data->flags & MMC_DATA_WRITE) {
487 buffer = sdhci_kmap_atomic(sg, &flags);
488 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
489 memcpy(align, buffer, offset);
490 sdhci_kunmap_atomic(buffer, &flags);
491 }
492
493 /* tran, valid */
494 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
495
496 BUG_ON(offset > 65536);
497
498 align += 4;
499 align_addr += 4;
500
501 desc += 8;
502
503 addr += offset;
504 len -= offset;
505 }
506
507 BUG_ON(len > 65536);
508
509 /* tran, valid */
510 sdhci_set_adma_desc(desc, addr, len, 0x21);
511 desc += 8;
512
513 /*
514 * If this triggers then we have a calculation bug
515 * somewhere. :/
516 */
517 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
518 }
519
520 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
521 /*
522 * Mark the last descriptor as the terminating descriptor
523 */
524 if (desc != host->adma_desc) {
525 desc -= 8;
526 desc[0] |= 0x2; /* end */
527 }
528 } else {
529 /*
530 * Add a terminating entry.
531 */
532
533 /* nop, end, valid */
534 sdhci_set_adma_desc(desc, 0, 0, 0x3);
535 }
536
537 /*
538 * Resync align buffer as we might have changed it.
539 */
540 if (data->flags & MMC_DATA_WRITE) {
541 dma_sync_single_for_device(mmc_dev(host->mmc),
542 host->align_addr, 128 * 4, direction);
543 }
544
545 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
546 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
547 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
548 goto unmap_entries;
549 BUG_ON(host->adma_addr & 0x3);
550
551 return 0;
552
553unmap_entries:
554 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
555 data->sg_len, direction);
556unmap_align:
557 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
558 128 * 4, direction);
559fail:
560 return -EINVAL;
561}
562
563static void sdhci_adma_table_post(struct sdhci_host *host,
564 struct mmc_data *data)
565{
566 int direction;
567
568 struct scatterlist *sg;
569 int i, size;
570 u8 *align;
571 char *buffer;
572 unsigned long flags;
573
574 if (data->flags & MMC_DATA_READ)
575 direction = DMA_FROM_DEVICE;
576 else
577 direction = DMA_TO_DEVICE;
578
579 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
580 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
581
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584
585 if (data->flags & MMC_DATA_READ) {
586 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588
589 align = host->align_buffer;
590
591 for_each_sg(data->sg, sg, host->sg_count, i) {
592 if (sg_dma_address(sg) & 0x3) {
593 size = 4 - (sg_dma_address(sg) & 0x3);
594
595 buffer = sdhci_kmap_atomic(sg, &flags);
596 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
597 memcpy(buffer, align, size);
598 sdhci_kunmap_atomic(buffer, &flags);
599
600 align += 4;
601 }
602 }
603 }
604
605 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
606 data->sg_len, direction);
607}
608
609static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
610{
611 u8 count;
612 struct mmc_data *data = cmd->data;
613 unsigned target_timeout, current_timeout;
614
615 /*
616 * If the host controller provides us with an incorrect timeout
617 * value, just skip the check and use 0xE. The hardware may take
618 * longer to time out, but that's much better than having a too-short
619 * timeout value.
620 */
621 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
622 return 0xE;
623
624 /* Unspecified timeout, assume max */
625 if (!data && !cmd->cmd_timeout_ms)
626 return 0xE;
627
628 /* timeout in us */
629 if (!data)
630 target_timeout = cmd->cmd_timeout_ms * 1000;
631 else {
632 target_timeout = data->timeout_ns / 1000;
633 if (host->clock)
634 target_timeout += data->timeout_clks / host->clock;
635 }
636
637 /*
638 * Figure out needed cycles.
639 * We do this in steps in order to fit inside a 32 bit int.
640 * The first step is the minimum timeout, which will have a
641 * minimum resolution of 6 bits:
642 * (1) 2^13*1000 > 2^22,
643 * (2) host->timeout_clk < 2^16
644 * =>
645 * (1) / (2) > 2^6
646 */
647 count = 0;
648 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
649 while (current_timeout < target_timeout) {
650 count++;
651 current_timeout <<= 1;
652 if (count >= 0xF)
653 break;
654 }
655
656 if (count >= 0xF) {
657 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
658 mmc_hostname(host->mmc), cmd->opcode);
659 count = 0xE;
660 }
661
662 return count;
663}
664
665static void sdhci_set_transfer_irqs(struct sdhci_host *host)
666{
667 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
668 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
669
670 if (host->flags & SDHCI_REQ_USE_DMA)
671 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
672 else
673 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
674}
675
676static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
677{
678 u8 count;
679 u8 ctrl;
680 struct mmc_data *data = cmd->data;
681 int ret;
682
683 WARN_ON(host->data);
684
685 if (data || (cmd->flags & MMC_RSP_BUSY)) {
686 count = sdhci_calc_timeout(host, cmd);
687 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
688 }
689
690 if (!data)
691 return;
692
693 /* Sanity checks */
694 BUG_ON(data->blksz * data->blocks > 524288);
695 BUG_ON(data->blksz > host->mmc->max_blk_size);
696 BUG_ON(data->blocks > 65535);
697
698 host->data = data;
699 host->data_early = 0;
700 host->data->bytes_xfered = 0;
701
702 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
703 host->flags |= SDHCI_REQ_USE_DMA;
704
705 /*
706 * FIXME: This doesn't account for merging when mapping the
707 * scatterlist.
708 */
709 if (host->flags & SDHCI_REQ_USE_DMA) {
710 int broken, i;
711 struct scatterlist *sg;
712
713 broken = 0;
714 if (host->flags & SDHCI_USE_ADMA) {
715 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
716 broken = 1;
717 } else {
718 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
719 broken = 1;
720 }
721
722 if (unlikely(broken)) {
723 for_each_sg(data->sg, sg, data->sg_len, i) {
724 if (sg->length & 0x3) {
725 DBG("Reverting to PIO because of "
726 "transfer size (%d)\n",
727 sg->length);
728 host->flags &= ~SDHCI_REQ_USE_DMA;
729 break;
730 }
731 }
732 }
733 }
734
735 /*
736 * The assumption here being that alignment is the same after
737 * translation to device address space.
738 */
739 if (host->flags & SDHCI_REQ_USE_DMA) {
740 int broken, i;
741 struct scatterlist *sg;
742
743 broken = 0;
744 if (host->flags & SDHCI_USE_ADMA) {
745 /*
746 * As we use 3 byte chunks to work around
747 * alignment problems, we need to check this
748 * quirk.
749 */
750 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
751 broken = 1;
752 } else {
753 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
754 broken = 1;
755 }
756
757 if (unlikely(broken)) {
758 for_each_sg(data->sg, sg, data->sg_len, i) {
759 if (sg->offset & 0x3) {
760 DBG("Reverting to PIO because of "
761 "bad alignment\n");
762 host->flags &= ~SDHCI_REQ_USE_DMA;
763 break;
764 }
765 }
766 }
767 }
768
769 if (host->flags & SDHCI_REQ_USE_DMA) {
770 if (host->flags & SDHCI_USE_ADMA) {
771 ret = sdhci_adma_table_pre(host, data);
772 if (ret) {
773 /*
774 * This only happens when someone fed
775 * us an invalid request.
776 */
777 WARN_ON(1);
778 host->flags &= ~SDHCI_REQ_USE_DMA;
779 } else {
780 sdhci_writel(host, host->adma_addr,
781 SDHCI_ADMA_ADDRESS);
782 }
783 } else {
784 int sg_cnt;
785
786 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
787 data->sg, data->sg_len,
788 (data->flags & MMC_DATA_READ) ?
789 DMA_FROM_DEVICE :
790 DMA_TO_DEVICE);
791 if (sg_cnt == 0) {
792 /*
793 * This only happens when someone fed
794 * us an invalid request.
795 */
796 WARN_ON(1);
797 host->flags &= ~SDHCI_REQ_USE_DMA;
798 } else {
799 WARN_ON(sg_cnt != 1);
800 sdhci_writel(host, sg_dma_address(data->sg),
801 SDHCI_DMA_ADDRESS);
802 }
803 }
804 }
805
806 /*
807 * Always adjust the DMA selection as some controllers
808 * (e.g. JMicron) can't do PIO properly when the selection
809 * is ADMA.
810 */
811 if (host->version >= SDHCI_SPEC_200) {
812 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
813 ctrl &= ~SDHCI_CTRL_DMA_MASK;
814 if ((host->flags & SDHCI_REQ_USE_DMA) &&
815 (host->flags & SDHCI_USE_ADMA))
816 ctrl |= SDHCI_CTRL_ADMA32;
817 else
818 ctrl |= SDHCI_CTRL_SDMA;
819 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
820 }
821
822 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
823 int flags;
824
825 flags = SG_MITER_ATOMIC;
826 if (host->data->flags & MMC_DATA_READ)
827 flags |= SG_MITER_TO_SG;
828 else
829 flags |= SG_MITER_FROM_SG;
830 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
831 host->blocks = data->blocks;
832 }
833
834 sdhci_set_transfer_irqs(host);
835
836 /* Set the DMA boundary value and block size */
837 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
838 data->blksz), SDHCI_BLOCK_SIZE);
839 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
840}
841
842static void sdhci_set_transfer_mode(struct sdhci_host *host,
843 struct mmc_command *cmd)
844{
845 u16 mode;
846 struct mmc_data *data = cmd->data;
847
848 if (data == NULL)
849 return;
850
851 WARN_ON(!host->data);
852
853 mode = SDHCI_TRNS_BLK_CNT_EN;
854 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
855 mode |= SDHCI_TRNS_MULTI;
856 /*
857 * If we are sending CMD23, CMD12 never gets sent
858 * on successful completion (so no Auto-CMD12).
859 */
860 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
861 mode |= SDHCI_TRNS_AUTO_CMD12;
862 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
863 mode |= SDHCI_TRNS_AUTO_CMD23;
864 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
865 }
866 }
867
868 if (data->flags & MMC_DATA_READ)
869 mode |= SDHCI_TRNS_READ;
870 if (host->flags & SDHCI_REQ_USE_DMA)
871 mode |= SDHCI_TRNS_DMA;
872
873 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
874}
875
876static void sdhci_finish_data(struct sdhci_host *host)
877{
878 struct mmc_data *data;
879
880 BUG_ON(!host->data);
881
882 data = host->data;
883 host->data = NULL;
884
885 if (host->flags & SDHCI_REQ_USE_DMA) {
886 if (host->flags & SDHCI_USE_ADMA)
887 sdhci_adma_table_post(host, data);
888 else {
889 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
890 data->sg_len, (data->flags & MMC_DATA_READ) ?
891 DMA_FROM_DEVICE : DMA_TO_DEVICE);
892 }
893 }
894
895 /*
896 * The specification states that the block count register must
897 * be updated, but it does not specify at what point in the
898 * data flow. That makes the register entirely useless to read
899 * back so we have to assume that nothing made it to the card
900 * in the event of an error.
901 */
902 if (data->error)
903 data->bytes_xfered = 0;
904 else
905 data->bytes_xfered = data->blksz * data->blocks;
906
907 /*
908 * Need to send CMD12 if -
909 * a) open-ended multiblock transfer (no CMD23)
910 * b) error in multiblock transfer
911 */
912 if (data->stop &&
913 (data->error ||
914 !host->mrq->sbc)) {
915
916 /*
917 * The controller needs a reset of internal state machines
918 * upon error conditions.
919 */
920 if (data->error) {
921 sdhci_reset(host, SDHCI_RESET_CMD);
922 sdhci_reset(host, SDHCI_RESET_DATA);
923 }
924
925 sdhci_send_command(host, data->stop);
926 } else
927 tasklet_schedule(&host->finish_tasklet);
928}
929
930static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
931{
932 int flags;
933 u32 mask;
934 unsigned long timeout;
935
936 WARN_ON(host->cmd);
937
938 /* Wait max 10 ms */
939 timeout = 10;
940
941 mask = SDHCI_CMD_INHIBIT;
942 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
943 mask |= SDHCI_DATA_INHIBIT;
944
945 /* We shouldn't wait for data inihibit for stop commands, even
946 though they might use busy signaling */
947 if (host->mrq->data && (cmd == host->mrq->data->stop))
948 mask &= ~SDHCI_DATA_INHIBIT;
949
950 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
951 if (timeout == 0) {
952 printk(KERN_ERR "%s: Controller never released "
953 "inhibit bit(s).\n", mmc_hostname(host->mmc));
954 sdhci_dumpregs(host);
955 cmd->error = -EIO;
956 tasklet_schedule(&host->finish_tasklet);
957 return;
958 }
959 timeout--;
960 mdelay(1);
961 }
962
963 mod_timer(&host->timer, jiffies + 10 * HZ);
964
965 host->cmd = cmd;
966
967 sdhci_prepare_data(host, cmd);
968
969 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
970
971 sdhci_set_transfer_mode(host, cmd);
972
973 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
974 printk(KERN_ERR "%s: Unsupported response type!\n",
975 mmc_hostname(host->mmc));
976 cmd->error = -EINVAL;
977 tasklet_schedule(&host->finish_tasklet);
978 return;
979 }
980
981 if (!(cmd->flags & MMC_RSP_PRESENT))
982 flags = SDHCI_CMD_RESP_NONE;
983 else if (cmd->flags & MMC_RSP_136)
984 flags = SDHCI_CMD_RESP_LONG;
985 else if (cmd->flags & MMC_RSP_BUSY)
986 flags = SDHCI_CMD_RESP_SHORT_BUSY;
987 else
988 flags = SDHCI_CMD_RESP_SHORT;
989
990 if (cmd->flags & MMC_RSP_CRC)
991 flags |= SDHCI_CMD_CRC;
992 if (cmd->flags & MMC_RSP_OPCODE)
993 flags |= SDHCI_CMD_INDEX;
994
995 /* CMD19 is special in that the Data Present Select should be set */
996 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
997 flags |= SDHCI_CMD_DATA;
998
999 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1000}
1001
1002static void sdhci_finish_command(struct sdhci_host *host)
1003{
1004 int i;
1005
1006 BUG_ON(host->cmd == NULL);
1007
1008 if (host->cmd->flags & MMC_RSP_PRESENT) {
1009 if (host->cmd->flags & MMC_RSP_136) {
1010 /* CRC is stripped so we need to do some shifting. */
1011 for (i = 0;i < 4;i++) {
1012 host->cmd->resp[i] = sdhci_readl(host,
1013 SDHCI_RESPONSE + (3-i)*4) << 8;
1014 if (i != 3)
1015 host->cmd->resp[i] |=
1016 sdhci_readb(host,
1017 SDHCI_RESPONSE + (3-i)*4-1);
1018 }
1019 } else {
1020 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1021 }
1022 }
1023
1024 host->cmd->error = 0;
1025
1026 /* Finished CMD23, now send actual command. */
1027 if (host->cmd == host->mrq->sbc) {
1028 host->cmd = NULL;
1029 sdhci_send_command(host, host->mrq->cmd);
1030 } else {
1031
1032 /* Processed actual command. */
1033 if (host->data && host->data_early)
1034 sdhci_finish_data(host);
1035
1036 if (!host->cmd->data)
1037 tasklet_schedule(&host->finish_tasklet);
1038
1039 host->cmd = NULL;
1040 }
1041}
1042
1043static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1044{
1045 int div = 0; /* Initialized for compiler warning */
1046 u16 clk = 0;
1047 unsigned long timeout;
1048
1049 if (clock == host->clock)
1050 return;
1051
1052 if (host->ops->set_clock) {
1053 host->ops->set_clock(host, clock);
1054 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1055 return;
1056 }
1057
1058 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1059
1060 if (clock == 0)
1061 goto out;
1062
1063 if (host->version >= SDHCI_SPEC_300) {
1064 /*
1065 * Check if the Host Controller supports Programmable Clock
1066 * Mode.
1067 */
1068 if (host->clk_mul) {
1069 u16 ctrl;
1070
1071 /*
1072 * We need to figure out whether the Host Driver needs
1073 * to select Programmable Clock Mode, or the value can
1074 * be set automatically by the Host Controller based on
1075 * the Preset Value registers.
1076 */
1077 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1078 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1079 for (div = 1; div <= 1024; div++) {
1080 if (((host->max_clk * host->clk_mul) /
1081 div) <= clock)
1082 break;
1083 }
1084 /*
1085 * Set Programmable Clock Mode in the Clock
1086 * Control register.
1087 */
1088 clk = SDHCI_PROG_CLOCK_MODE;
1089 div--;
1090 }
1091 } else {
1092 /* Version 3.00 divisors must be a multiple of 2. */
1093 if (host->max_clk <= clock)
1094 div = 1;
1095 else {
1096 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1097 div += 2) {
1098 if ((host->max_clk / div) <= clock)
1099 break;
1100 }
1101 }
1102 div >>= 1;
1103 }
1104 } else {
1105 /* Version 2.00 divisors must be a power of 2. */
1106 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1107 if ((host->max_clk / div) <= clock)
1108 break;
1109 }
1110 div >>= 1;
1111 }
1112
1113 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1114 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1115 << SDHCI_DIVIDER_HI_SHIFT;
1116 clk |= SDHCI_CLOCK_INT_EN;
1117 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1118
1119 /* Wait max 20 ms */
1120 timeout = 20;
1121 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1122 & SDHCI_CLOCK_INT_STABLE)) {
1123 if (timeout == 0) {
1124 printk(KERN_ERR "%s: Internal clock never "
1125 "stabilised.\n", mmc_hostname(host->mmc));
1126 sdhci_dumpregs(host);
1127 return;
1128 }
1129 timeout--;
1130 mdelay(1);
1131 }
1132
1133 clk |= SDHCI_CLOCK_CARD_EN;
1134 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1135
1136out:
1137 host->clock = clock;
1138}
1139
1140static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1141{
1142 u8 pwr = 0;
1143
1144 if (power != (unsigned short)-1) {
1145 switch (1 << power) {
1146 case MMC_VDD_165_195:
1147 pwr = SDHCI_POWER_180;
1148 break;
1149 case MMC_VDD_29_30:
1150 case MMC_VDD_30_31:
1151 pwr = SDHCI_POWER_300;
1152 break;
1153 case MMC_VDD_32_33:
1154 case MMC_VDD_33_34:
1155 pwr = SDHCI_POWER_330;
1156 break;
1157 default:
1158 BUG();
1159 }
1160 }
1161
1162 if (host->pwr == pwr)
1163 return;
1164
1165 host->pwr = pwr;
1166
1167 if (pwr == 0) {
1168 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1169 return;
1170 }
1171
1172 /*
1173 * Spec says that we should clear the power reg before setting
1174 * a new value. Some controllers don't seem to like this though.
1175 */
1176 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1177 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1178
1179 /*
1180 * At least the Marvell CaFe chip gets confused if we set the voltage
1181 * and set turn on power at the same time, so set the voltage first.
1182 */
1183 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1184 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1185
1186 pwr |= SDHCI_POWER_ON;
1187
1188 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1189
1190 /*
1191 * Some controllers need an extra 10ms delay of 10ms before they
1192 * can apply clock after applying power
1193 */
1194 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1195 mdelay(10);
1196}
1197
1198/*****************************************************************************\
1199 * *
1200 * MMC callbacks *
1201 * *
1202\*****************************************************************************/
1203
1204static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1205{
1206 struct sdhci_host *host;
1207 bool present;
1208 unsigned long flags;
1209
1210 host = mmc_priv(mmc);
1211
1212 spin_lock_irqsave(&host->lock, flags);
1213
1214 WARN_ON(host->mrq != NULL);
1215
1216#ifndef SDHCI_USE_LEDS_CLASS
1217 sdhci_activate_led(host);
1218#endif
1219
1220 /*
1221 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1222 * requests if Auto-CMD12 is enabled.
1223 */
1224 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1225 if (mrq->stop) {
1226 mrq->data->stop = NULL;
1227 mrq->stop = NULL;
1228 }
1229 }
1230
1231 host->mrq = mrq;
1232
1233 /* If polling, assume that the card is always present. */
1234 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1235 present = true;
1236 else
1237 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1238 SDHCI_CARD_PRESENT;
1239
1240 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1241 host->mrq->cmd->error = -ENOMEDIUM;
1242 tasklet_schedule(&host->finish_tasklet);
1243 } else {
1244 u32 present_state;
1245
1246 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1247 /*
1248 * Check if the re-tuning timer has already expired and there
1249 * is no on-going data transfer. If so, we need to execute
1250 * tuning procedure before sending command.
1251 */
1252 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1253 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1254 spin_unlock_irqrestore(&host->lock, flags);
1255 sdhci_execute_tuning(mmc);
1256 spin_lock_irqsave(&host->lock, flags);
1257
1258 /* Restore original mmc_request structure */
1259 host->mrq = mrq;
1260 }
1261
1262 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1263 sdhci_send_command(host, mrq->sbc);
1264 else
1265 sdhci_send_command(host, mrq->cmd);
1266 }
1267
1268 mmiowb();
1269 spin_unlock_irqrestore(&host->lock, flags);
1270}
1271
1272static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1273{
1274 struct sdhci_host *host;
1275 unsigned long flags;
1276 u8 ctrl;
1277
1278 host = mmc_priv(mmc);
1279
1280 spin_lock_irqsave(&host->lock, flags);
1281
1282 if (host->flags & SDHCI_DEVICE_DEAD)
1283 goto out;
1284
1285 /*
1286 * Reset the chip on each power off.
1287 * Should clear out any weird states.
1288 */
1289 if (ios->power_mode == MMC_POWER_OFF) {
1290 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1291 sdhci_reinit(host);
1292 }
1293
1294 sdhci_set_clock(host, ios->clock);
1295
1296 if (ios->power_mode == MMC_POWER_OFF)
1297 sdhci_set_power(host, -1);
1298 else
1299 sdhci_set_power(host, ios->vdd);
1300
1301 if (host->ops->platform_send_init_74_clocks)
1302 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1303
1304 /*
1305 * If your platform has 8-bit width support but is not a v3 controller,
1306 * or if it requires special setup code, you should implement that in
1307 * platform_8bit_width().
1308 */
1309 if (host->ops->platform_8bit_width)
1310 host->ops->platform_8bit_width(host, ios->bus_width);
1311 else {
1312 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1313 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1314 ctrl &= ~SDHCI_CTRL_4BITBUS;
1315 if (host->version >= SDHCI_SPEC_300)
1316 ctrl |= SDHCI_CTRL_8BITBUS;
1317 } else {
1318 if (host->version >= SDHCI_SPEC_300)
1319 ctrl &= ~SDHCI_CTRL_8BITBUS;
1320 if (ios->bus_width == MMC_BUS_WIDTH_4)
1321 ctrl |= SDHCI_CTRL_4BITBUS;
1322 else
1323 ctrl &= ~SDHCI_CTRL_4BITBUS;
1324 }
1325 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1326 }
1327
1328 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1329
1330 if ((ios->timing == MMC_TIMING_SD_HS ||
1331 ios->timing == MMC_TIMING_MMC_HS)
1332 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1333 ctrl |= SDHCI_CTRL_HISPD;
1334 else
1335 ctrl &= ~SDHCI_CTRL_HISPD;
1336
1337 if (host->version >= SDHCI_SPEC_300) {
1338 u16 clk, ctrl_2;
1339 unsigned int clock;
1340
1341 /* In case of UHS-I modes, set High Speed Enable */
1342 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1343 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1344 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1345 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1346 (ios->timing == MMC_TIMING_UHS_SDR12))
1347 ctrl |= SDHCI_CTRL_HISPD;
1348
1349 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1350 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1351 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1352 /*
1353 * We only need to set Driver Strength if the
1354 * preset value enable is not set.
1355 */
1356 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1357 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1358 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1359 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1360 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1361
1362 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1363 } else {
1364 /*
1365 * According to SDHC Spec v3.00, if the Preset Value
1366 * Enable in the Host Control 2 register is set, we
1367 * need to reset SD Clock Enable before changing High
1368 * Speed Enable to avoid generating clock gliches.
1369 */
1370
1371 /* Reset SD Clock Enable */
1372 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1373 clk &= ~SDHCI_CLOCK_CARD_EN;
1374 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1375
1376 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1377
1378 /* Re-enable SD Clock */
1379 clock = host->clock;
1380 host->clock = 0;
1381 sdhci_set_clock(host, clock);
1382 }
1383
1384
1385 /* Reset SD Clock Enable */
1386 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1387 clk &= ~SDHCI_CLOCK_CARD_EN;
1388 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1389
1390 if (host->ops->set_uhs_signaling)
1391 host->ops->set_uhs_signaling(host, ios->timing);
1392 else {
1393 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1394 /* Select Bus Speed Mode for host */
1395 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1396 if (ios->timing == MMC_TIMING_UHS_SDR12)
1397 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1398 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1399 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1400 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1401 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1402 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1403 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1404 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1405 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1406 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1407 }
1408
1409 /* Re-enable SD Clock */
1410 clock = host->clock;
1411 host->clock = 0;
1412 sdhci_set_clock(host, clock);
1413 } else
1414 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1415
1416 /*
1417 * Some (ENE) controllers go apeshit on some ios operation,
1418 * signalling timeout and CRC errors even on CMD0. Resetting
1419 * it on each ios seems to solve the problem.
1420 */
1421 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1422 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1423
1424out:
1425 mmiowb();
1426 spin_unlock_irqrestore(&host->lock, flags);
1427}
1428
1429static int check_ro(struct sdhci_host *host)
1430{
1431 unsigned long flags;
1432 int is_readonly;
1433
1434 spin_lock_irqsave(&host->lock, flags);
1435
1436 if (host->flags & SDHCI_DEVICE_DEAD)
1437 is_readonly = 0;
1438 else if (host->ops->get_ro)
1439 is_readonly = host->ops->get_ro(host);
1440 else
1441 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1442 & SDHCI_WRITE_PROTECT);
1443
1444 spin_unlock_irqrestore(&host->lock, flags);
1445
1446 /* This quirk needs to be replaced by a callback-function later */
1447 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1448 !is_readonly : is_readonly;
1449}
1450
1451#define SAMPLE_COUNT 5
1452
1453static int sdhci_get_ro(struct mmc_host *mmc)
1454{
1455 struct sdhci_host *host;
1456 int i, ro_count;
1457
1458 host = mmc_priv(mmc);
1459
1460 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1461 return check_ro(host);
1462
1463 ro_count = 0;
1464 for (i = 0; i < SAMPLE_COUNT; i++) {
1465 if (check_ro(host)) {
1466 if (++ro_count > SAMPLE_COUNT / 2)
1467 return 1;
1468 }
1469 msleep(30);
1470 }
1471 return 0;
1472}
1473
1474static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1475{
1476 struct sdhci_host *host;
1477 unsigned long flags;
1478
1479 host = mmc_priv(mmc);
1480
1481 spin_lock_irqsave(&host->lock, flags);
1482
1483 if (host->flags & SDHCI_DEVICE_DEAD)
1484 goto out;
1485
1486 if (enable)
1487 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1488 else
1489 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1490out:
1491 mmiowb();
1492
1493 spin_unlock_irqrestore(&host->lock, flags);
1494}
1495
1496static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1497 struct mmc_ios *ios)
1498{
1499 struct sdhci_host *host;
1500 u8 pwr;
1501 u16 clk, ctrl;
1502 u32 present_state;
1503
1504 host = mmc_priv(mmc);
1505
1506 /*
1507 * Signal Voltage Switching is only applicable for Host Controllers
1508 * v3.00 and above.
1509 */
1510 if (host->version < SDHCI_SPEC_300)
1511 return 0;
1512
1513 /*
1514 * We first check whether the request is to set signalling voltage
1515 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1516 */
1517 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1518 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1519 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1520 ctrl &= ~SDHCI_CTRL_VDD_180;
1521 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1522
1523 /* Wait for 5ms */
1524 usleep_range(5000, 5500);
1525
1526 /* 3.3V regulator output should be stable within 5 ms */
1527 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1528 if (!(ctrl & SDHCI_CTRL_VDD_180))
1529 return 0;
1530 else {
1531 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1532 "signalling voltage failed\n");
1533 return -EIO;
1534 }
1535 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1536 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1537 /* Stop SDCLK */
1538 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1539 clk &= ~SDHCI_CLOCK_CARD_EN;
1540 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1541
1542 /* Check whether DAT[3:0] is 0000 */
1543 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1544 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1545 SDHCI_DATA_LVL_SHIFT)) {
1546 /*
1547 * Enable 1.8V Signal Enable in the Host Control2
1548 * register
1549 */
1550 ctrl |= SDHCI_CTRL_VDD_180;
1551 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1552
1553 /* Wait for 5ms */
1554 usleep_range(5000, 5500);
1555
1556 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1557 if (ctrl & SDHCI_CTRL_VDD_180) {
1558 /* Provide SDCLK again and wait for 1ms*/
1559 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1560 clk |= SDHCI_CLOCK_CARD_EN;
1561 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1562 usleep_range(1000, 1500);
1563
1564 /*
1565 * If DAT[3:0] level is 1111b, then the card
1566 * was successfully switched to 1.8V signaling.
1567 */
1568 present_state = sdhci_readl(host,
1569 SDHCI_PRESENT_STATE);
1570 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1571 SDHCI_DATA_LVL_MASK)
1572 return 0;
1573 }
1574 }
1575
1576 /*
1577 * If we are here, that means the switch to 1.8V signaling
1578 * failed. We power cycle the card, and retry initialization
1579 * sequence by setting S18R to 0.
1580 */
1581 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1582 pwr &= ~SDHCI_POWER_ON;
1583 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1584
1585 /* Wait for 1ms as per the spec */
1586 usleep_range(1000, 1500);
1587 pwr |= SDHCI_POWER_ON;
1588 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1589
1590 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1591 "voltage failed, retrying with S18R set to 0\n");
1592 return -EAGAIN;
1593 } else
1594 /* No signal voltage switch required */
1595 return 0;
1596}
1597
1598static int sdhci_execute_tuning(struct mmc_host *mmc)
1599{
1600 struct sdhci_host *host;
1601 u16 ctrl;
1602 u32 ier;
1603 int tuning_loop_counter = MAX_TUNING_LOOP;
1604 unsigned long timeout;
1605 int err = 0;
1606
1607 host = mmc_priv(mmc);
1608
1609 disable_irq(host->irq);
1610 spin_lock(&host->lock);
1611
1612 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1613
1614 /*
1615 * Host Controller needs tuning only in case of SDR104 mode
1616 * and for SDR50 mode when Use Tuning for SDR50 is set in
1617 * Capabilities register.
1618 */
1619 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1620 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1621 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1622 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1623 else {
1624 spin_unlock(&host->lock);
1625 enable_irq(host->irq);
1626 return 0;
1627 }
1628
1629 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1630
1631 /*
1632 * As per the Host Controller spec v3.00, tuning command
1633 * generates Buffer Read Ready interrupt, so enable that.
1634 *
1635 * Note: The spec clearly says that when tuning sequence
1636 * is being performed, the controller does not generate
1637 * interrupts other than Buffer Read Ready interrupt. But
1638 * to make sure we don't hit a controller bug, we _only_
1639 * enable Buffer Read Ready interrupt here.
1640 */
1641 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1642 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1643
1644 /*
1645 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1646 * of loops reaches 40 times or a timeout of 150ms occurs.
1647 */
1648 timeout = 150;
1649 do {
1650 struct mmc_command cmd = {0};
1651 struct mmc_request mrq = {0};
1652
1653 if (!tuning_loop_counter && !timeout)
1654 break;
1655
1656 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1657 cmd.arg = 0;
1658 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1659 cmd.retries = 0;
1660 cmd.data = NULL;
1661 cmd.error = 0;
1662
1663 mrq.cmd = &cmd;
1664 host->mrq = &mrq;
1665
1666 /*
1667 * In response to CMD19, the card sends 64 bytes of tuning
1668 * block to the Host Controller. So we set the block size
1669 * to 64 here.
1670 */
1671 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1672
1673 /*
1674 * The tuning block is sent by the card to the host controller.
1675 * So we set the TRNS_READ bit in the Transfer Mode register.
1676 * This also takes care of setting DMA Enable and Multi Block
1677 * Select in the same register to 0.
1678 */
1679 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1680
1681 sdhci_send_command(host, &cmd);
1682
1683 host->cmd = NULL;
1684 host->mrq = NULL;
1685
1686 spin_unlock(&host->lock);
1687 enable_irq(host->irq);
1688
1689 /* Wait for Buffer Read Ready interrupt */
1690 wait_event_interruptible_timeout(host->buf_ready_int,
1691 (host->tuning_done == 1),
1692 msecs_to_jiffies(50));
1693 disable_irq(host->irq);
1694 spin_lock(&host->lock);
1695
1696 if (!host->tuning_done) {
1697 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1698 "Buffer Read Ready interrupt during tuning "
1699 "procedure, falling back to fixed sampling "
1700 "clock\n");
1701 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1702 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1703 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1704 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1705
1706 err = -EIO;
1707 goto out;
1708 }
1709
1710 host->tuning_done = 0;
1711
1712 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1713 tuning_loop_counter--;
1714 timeout--;
1715 mdelay(1);
1716 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1717
1718 /*
1719 * The Host Driver has exhausted the maximum number of loops allowed,
1720 * so use fixed sampling frequency.
1721 */
1722 if (!tuning_loop_counter || !timeout) {
1723 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1724 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1725 } else {
1726 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1727 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1728 " failed, falling back to fixed sampling"
1729 " clock\n");
1730 err = -EIO;
1731 }
1732 }
1733
1734out:
1735 /*
1736 * If this is the very first time we are here, we start the retuning
1737 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1738 * flag won't be set, we check this condition before actually starting
1739 * the timer.
1740 */
1741 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1742 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1743 mod_timer(&host->tuning_timer, jiffies +
1744 host->tuning_count * HZ);
1745 /* Tuning mode 1 limits the maximum data length to 4MB */
1746 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1747 } else {
1748 host->flags &= ~SDHCI_NEEDS_RETUNING;
1749 /* Reload the new initial value for timer */
1750 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1751 mod_timer(&host->tuning_timer, jiffies +
1752 host->tuning_count * HZ);
1753 }
1754
1755 /*
1756 * In case tuning fails, host controllers which support re-tuning can
1757 * try tuning again at a later time, when the re-tuning timer expires.
1758 * So for these controllers, we return 0. Since there might be other
1759 * controllers who do not have this capability, we return error for
1760 * them.
1761 */
1762 if (err && host->tuning_count &&
1763 host->tuning_mode == SDHCI_TUNING_MODE_1)
1764 err = 0;
1765
1766 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1767 spin_unlock(&host->lock);
1768 enable_irq(host->irq);
1769
1770 return err;
1771}
1772
1773static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1774{
1775 struct sdhci_host *host;
1776 u16 ctrl;
1777 unsigned long flags;
1778
1779 host = mmc_priv(mmc);
1780
1781 /* Host Controller v3.00 defines preset value registers */
1782 if (host->version < SDHCI_SPEC_300)
1783 return;
1784
1785 spin_lock_irqsave(&host->lock, flags);
1786
1787 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1788
1789 /*
1790 * We only enable or disable Preset Value if they are not already
1791 * enabled or disabled respectively. Otherwise, we bail out.
1792 */
1793 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1794 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1795 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1796 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1797 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1798 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1799 }
1800
1801 spin_unlock_irqrestore(&host->lock, flags);
1802}
1803
1804static const struct mmc_host_ops sdhci_ops = {
1805 .request = sdhci_request,
1806 .set_ios = sdhci_set_ios,
1807 .get_ro = sdhci_get_ro,
1808 .enable_sdio_irq = sdhci_enable_sdio_irq,
1809 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1810 .execute_tuning = sdhci_execute_tuning,
1811 .enable_preset_value = sdhci_enable_preset_value,
1812};
1813
1814/*****************************************************************************\
1815 * *
1816 * Tasklets *
1817 * *
1818\*****************************************************************************/
1819
1820static void sdhci_tasklet_card(unsigned long param)
1821{
1822 struct sdhci_host *host;
1823 unsigned long flags;
1824
1825 host = (struct sdhci_host*)param;
1826
1827 spin_lock_irqsave(&host->lock, flags);
1828
1829 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1830 if (host->mrq) {
1831 printk(KERN_ERR "%s: Card removed during transfer!\n",
1832 mmc_hostname(host->mmc));
1833 printk(KERN_ERR "%s: Resetting controller.\n",
1834 mmc_hostname(host->mmc));
1835
1836 sdhci_reset(host, SDHCI_RESET_CMD);
1837 sdhci_reset(host, SDHCI_RESET_DATA);
1838
1839 host->mrq->cmd->error = -ENOMEDIUM;
1840 tasklet_schedule(&host->finish_tasklet);
1841 }
1842 }
1843
1844 spin_unlock_irqrestore(&host->lock, flags);
1845
1846 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1847}
1848
1849static void sdhci_tasklet_finish(unsigned long param)
1850{
1851 struct sdhci_host *host;
1852 unsigned long flags;
1853 struct mmc_request *mrq;
1854
1855 host = (struct sdhci_host*)param;
1856
1857 /*
1858 * If this tasklet gets rescheduled while running, it will
1859 * be run again afterwards but without any active request.
1860 */
1861 if (!host->mrq)
1862 return;
1863
1864 spin_lock_irqsave(&host->lock, flags);
1865
1866 del_timer(&host->timer);
1867
1868 mrq = host->mrq;
1869
1870 /*
1871 * The controller needs a reset of internal state machines
1872 * upon error conditions.
1873 */
1874 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1875 ((mrq->cmd && mrq->cmd->error) ||
1876 (mrq->data && (mrq->data->error ||
1877 (mrq->data->stop && mrq->data->stop->error))) ||
1878 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1879
1880 /* Some controllers need this kick or reset won't work here */
1881 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1882 unsigned int clock;
1883
1884 /* This is to force an update */
1885 clock = host->clock;
1886 host->clock = 0;
1887 sdhci_set_clock(host, clock);
1888 }
1889
1890 /* Spec says we should do both at the same time, but Ricoh
1891 controllers do not like that. */
1892 sdhci_reset(host, SDHCI_RESET_CMD);
1893 sdhci_reset(host, SDHCI_RESET_DATA);
1894 }
1895
1896 host->mrq = NULL;
1897 host->cmd = NULL;
1898 host->data = NULL;
1899
1900#ifndef SDHCI_USE_LEDS_CLASS
1901 sdhci_deactivate_led(host);
1902#endif
1903
1904 mmiowb();
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 mmc_request_done(host->mmc, mrq);
1908}
1909
1910static void sdhci_timeout_timer(unsigned long data)
1911{
1912 struct sdhci_host *host;
1913 unsigned long flags;
1914
1915 host = (struct sdhci_host*)data;
1916
1917 spin_lock_irqsave(&host->lock, flags);
1918
1919 if (host->mrq) {
1920 printk(KERN_ERR "%s: Timeout waiting for hardware "
1921 "interrupt.\n", mmc_hostname(host->mmc));
1922 sdhci_dumpregs(host);
1923
1924 if (host->data) {
1925 host->data->error = -ETIMEDOUT;
1926 sdhci_finish_data(host);
1927 } else {
1928 if (host->cmd)
1929 host->cmd->error = -ETIMEDOUT;
1930 else
1931 host->mrq->cmd->error = -ETIMEDOUT;
1932
1933 tasklet_schedule(&host->finish_tasklet);
1934 }
1935 }
1936
1937 mmiowb();
1938 spin_unlock_irqrestore(&host->lock, flags);
1939}
1940
1941static void sdhci_tuning_timer(unsigned long data)
1942{
1943 struct sdhci_host *host;
1944 unsigned long flags;
1945
1946 host = (struct sdhci_host *)data;
1947
1948 spin_lock_irqsave(&host->lock, flags);
1949
1950 host->flags |= SDHCI_NEEDS_RETUNING;
1951
1952 spin_unlock_irqrestore(&host->lock, flags);
1953}
1954
1955/*****************************************************************************\
1956 * *
1957 * Interrupt handling *
1958 * *
1959\*****************************************************************************/
1960
1961static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1962{
1963 BUG_ON(intmask == 0);
1964
1965 if (!host->cmd) {
1966 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1967 "though no command operation was in progress.\n",
1968 mmc_hostname(host->mmc), (unsigned)intmask);
1969 sdhci_dumpregs(host);
1970 return;
1971 }
1972
1973 if (intmask & SDHCI_INT_TIMEOUT)
1974 host->cmd->error = -ETIMEDOUT;
1975 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1976 SDHCI_INT_INDEX))
1977 host->cmd->error = -EILSEQ;
1978
1979 if (host->cmd->error) {
1980 tasklet_schedule(&host->finish_tasklet);
1981 return;
1982 }
1983
1984 /*
1985 * The host can send and interrupt when the busy state has
1986 * ended, allowing us to wait without wasting CPU cycles.
1987 * Unfortunately this is overloaded on the "data complete"
1988 * interrupt, so we need to take some care when handling
1989 * it.
1990 *
1991 * Note: The 1.0 specification is a bit ambiguous about this
1992 * feature so there might be some problems with older
1993 * controllers.
1994 */
1995 if (host->cmd->flags & MMC_RSP_BUSY) {
1996 if (host->cmd->data)
1997 DBG("Cannot wait for busy signal when also "
1998 "doing a data transfer");
1999 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2000 return;
2001
2002 /* The controller does not support the end-of-busy IRQ,
2003 * fall through and take the SDHCI_INT_RESPONSE */
2004 }
2005
2006 if (intmask & SDHCI_INT_RESPONSE)
2007 sdhci_finish_command(host);
2008}
2009
2010#ifdef CONFIG_MMC_DEBUG
2011static void sdhci_show_adma_error(struct sdhci_host *host)
2012{
2013 const char *name = mmc_hostname(host->mmc);
2014 u8 *desc = host->adma_desc;
2015 __le32 *dma;
2016 __le16 *len;
2017 u8 attr;
2018
2019 sdhci_dumpregs(host);
2020
2021 while (true) {
2022 dma = (__le32 *)(desc + 4);
2023 len = (__le16 *)(desc + 2);
2024 attr = *desc;
2025
2026 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2027 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2028
2029 desc += 8;
2030
2031 if (attr & 2)
2032 break;
2033 }
2034}
2035#else
2036static void sdhci_show_adma_error(struct sdhci_host *host) { }
2037#endif
2038
2039static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2040{
2041 BUG_ON(intmask == 0);
2042
2043 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2044 if (intmask & SDHCI_INT_DATA_AVAIL) {
2045 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2046 MMC_SEND_TUNING_BLOCK) {
2047 host->tuning_done = 1;
2048 wake_up(&host->buf_ready_int);
2049 return;
2050 }
2051 }
2052
2053 if (!host->data) {
2054 /*
2055 * The "data complete" interrupt is also used to
2056 * indicate that a busy state has ended. See comment
2057 * above in sdhci_cmd_irq().
2058 */
2059 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2060 if (intmask & SDHCI_INT_DATA_END) {
2061 sdhci_finish_command(host);
2062 return;
2063 }
2064 }
2065
2066 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2067 "though no data operation was in progress.\n",
2068 mmc_hostname(host->mmc), (unsigned)intmask);
2069 sdhci_dumpregs(host);
2070
2071 return;
2072 }
2073
2074 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2075 host->data->error = -ETIMEDOUT;
2076 else if (intmask & SDHCI_INT_DATA_END_BIT)
2077 host->data->error = -EILSEQ;
2078 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2079 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2080 != MMC_BUS_TEST_R)
2081 host->data->error = -EILSEQ;
2082 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2083 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2084 sdhci_show_adma_error(host);
2085 host->data->error = -EIO;
2086 }
2087
2088 if (host->data->error)
2089 sdhci_finish_data(host);
2090 else {
2091 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2092 sdhci_transfer_pio(host);
2093
2094 /*
2095 * We currently don't do anything fancy with DMA
2096 * boundaries, but as we can't disable the feature
2097 * we need to at least restart the transfer.
2098 *
2099 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2100 * should return a valid address to continue from, but as
2101 * some controllers are faulty, don't trust them.
2102 */
2103 if (intmask & SDHCI_INT_DMA_END) {
2104 u32 dmastart, dmanow;
2105 dmastart = sg_dma_address(host->data->sg);
2106 dmanow = dmastart + host->data->bytes_xfered;
2107 /*
2108 * Force update to the next DMA block boundary.
2109 */
2110 dmanow = (dmanow &
2111 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2112 SDHCI_DEFAULT_BOUNDARY_SIZE;
2113 host->data->bytes_xfered = dmanow - dmastart;
2114 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2115 " next 0x%08x\n",
2116 mmc_hostname(host->mmc), dmastart,
2117 host->data->bytes_xfered, dmanow);
2118 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2119 }
2120
2121 if (intmask & SDHCI_INT_DATA_END) {
2122 if (host->cmd) {
2123 /*
2124 * Data managed to finish before the
2125 * command completed. Make sure we do
2126 * things in the proper order.
2127 */
2128 host->data_early = 1;
2129 } else {
2130 sdhci_finish_data(host);
2131 }
2132 }
2133 }
2134}
2135
2136static irqreturn_t sdhci_irq(int irq, void *dev_id)
2137{
2138 irqreturn_t result;
2139 struct sdhci_host* host = dev_id;
2140 u32 intmask;
2141 int cardint = 0;
2142
2143 spin_lock(&host->lock);
2144
2145 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2146
2147 if (!intmask || intmask == 0xffffffff) {
2148 result = IRQ_NONE;
2149 goto out;
2150 }
2151
2152 DBG("*** %s got interrupt: 0x%08x\n",
2153 mmc_hostname(host->mmc), intmask);
2154
2155 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2156 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2157 SDHCI_CARD_PRESENT;
2158
2159 /*
2160 * There is a observation on i.mx esdhc. INSERT bit will be
2161 * immediately set again when it gets cleared, if a card is
2162 * inserted. We have to mask the irq to prevent interrupt
2163 * storm which will freeze the system. And the REMOVE gets
2164 * the same situation.
2165 *
2166 * More testing are needed here to ensure it works for other
2167 * platforms though.
2168 */
2169 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2170 SDHCI_INT_CARD_REMOVE);
2171 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2172 SDHCI_INT_CARD_INSERT);
2173
2174 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2175 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2176 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2177 tasklet_schedule(&host->card_tasklet);
2178 }
2179
2180 if (intmask & SDHCI_INT_CMD_MASK) {
2181 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2182 SDHCI_INT_STATUS);
2183 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2184 }
2185
2186 if (intmask & SDHCI_INT_DATA_MASK) {
2187 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2188 SDHCI_INT_STATUS);
2189 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2190 }
2191
2192 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2193
2194 intmask &= ~SDHCI_INT_ERROR;
2195
2196 if (intmask & SDHCI_INT_BUS_POWER) {
2197 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2198 mmc_hostname(host->mmc));
2199 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2200 }
2201
2202 intmask &= ~SDHCI_INT_BUS_POWER;
2203
2204 if (intmask & SDHCI_INT_CARD_INT)
2205 cardint = 1;
2206
2207 intmask &= ~SDHCI_INT_CARD_INT;
2208
2209 if (intmask) {
2210 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2211 mmc_hostname(host->mmc), intmask);
2212 sdhci_dumpregs(host);
2213
2214 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2215 }
2216
2217 result = IRQ_HANDLED;
2218
2219 mmiowb();
2220out:
2221 spin_unlock(&host->lock);
2222
2223 /*
2224 * We have to delay this as it calls back into the driver.
2225 */
2226 if (cardint)
2227 mmc_signal_sdio_irq(host->mmc);
2228
2229 return result;
2230}
2231
2232/*****************************************************************************\
2233 * *
2234 * Suspend/resume *
2235 * *
2236\*****************************************************************************/
2237
2238#ifdef CONFIG_PM
2239
2240int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2241{
2242 int ret;
2243
2244 sdhci_disable_card_detection(host);
2245
2246 /* Disable tuning since we are suspending */
2247 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2248 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2249 host->flags &= ~SDHCI_NEEDS_RETUNING;
2250 mod_timer(&host->tuning_timer, jiffies +
2251 host->tuning_count * HZ);
2252 }
2253
2254 ret = mmc_suspend_host(host->mmc);
2255 if (ret)
2256 return ret;
2257
2258 free_irq(host->irq, host);
2259
2260 if (host->vmmc)
2261 ret = regulator_disable(host->vmmc);
2262
2263 return ret;
2264}
2265
2266EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2267
2268int sdhci_resume_host(struct sdhci_host *host)
2269{
2270 int ret;
2271
2272 if (host->vmmc) {
2273 int ret = regulator_enable(host->vmmc);
2274 if (ret)
2275 return ret;
2276 }
2277
2278
2279 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2280 if (host->ops->enable_dma)
2281 host->ops->enable_dma(host);
2282 }
2283
2284 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2285 mmc_hostname(host->mmc), host);
2286 if (ret)
2287 return ret;
2288
2289 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2290 mmiowb();
2291
2292 ret = mmc_resume_host(host->mmc);
2293 sdhci_enable_card_detection(host);
2294
2295 /* Set the re-tuning expiration flag */
2296 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2297 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2298 host->flags |= SDHCI_NEEDS_RETUNING;
2299
2300 return ret;
2301}
2302
2303EXPORT_SYMBOL_GPL(sdhci_resume_host);
2304
2305void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2306{
2307 u8 val;
2308 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2309 val |= SDHCI_WAKE_ON_INT;
2310 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2311}
2312
2313EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2314
2315#endif /* CONFIG_PM */
2316
2317/*****************************************************************************\
2318 * *
2319 * Device allocation/registration *
2320 * *
2321\*****************************************************************************/
2322
2323struct sdhci_host *sdhci_alloc_host(struct device *dev,
2324 size_t priv_size)
2325{
2326 struct mmc_host *mmc;
2327 struct sdhci_host *host;
2328
2329 WARN_ON(dev == NULL);
2330
2331 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2332 if (!mmc)
2333 return ERR_PTR(-ENOMEM);
2334
2335 host = mmc_priv(mmc);
2336 host->mmc = mmc;
2337
2338 return host;
2339}
2340
2341EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2342
2343int sdhci_add_host(struct sdhci_host *host)
2344{
2345 struct mmc_host *mmc;
2346 u32 caps[2];
2347 u32 max_current_caps;
2348 unsigned int ocr_avail;
2349 int ret;
2350
2351 WARN_ON(host == NULL);
2352 if (host == NULL)
2353 return -EINVAL;
2354
2355 mmc = host->mmc;
2356
2357 if (debug_quirks)
2358 host->quirks = debug_quirks;
2359
2360 sdhci_reset(host, SDHCI_RESET_ALL);
2361
2362 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2363 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2364 >> SDHCI_SPEC_VER_SHIFT;
2365 if (host->version > SDHCI_SPEC_300) {
2366 printk(KERN_ERR "%s: Unknown controller version (%d). "
2367 "You may experience problems.\n", mmc_hostname(mmc),
2368 host->version);
2369 }
2370
2371 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2372 sdhci_readl(host, SDHCI_CAPABILITIES);
2373
2374 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2375 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2376
2377 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2378 host->flags |= SDHCI_USE_SDMA;
2379 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2380 DBG("Controller doesn't have SDMA capability\n");
2381 else
2382 host->flags |= SDHCI_USE_SDMA;
2383
2384 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2385 (host->flags & SDHCI_USE_SDMA)) {
2386 DBG("Disabling DMA as it is marked broken\n");
2387 host->flags &= ~SDHCI_USE_SDMA;
2388 }
2389
2390 if ((host->version >= SDHCI_SPEC_200) &&
2391 (caps[0] & SDHCI_CAN_DO_ADMA2))
2392 host->flags |= SDHCI_USE_ADMA;
2393
2394 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2395 (host->flags & SDHCI_USE_ADMA)) {
2396 DBG("Disabling ADMA as it is marked broken\n");
2397 host->flags &= ~SDHCI_USE_ADMA;
2398 }
2399
2400 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2401 if (host->ops->enable_dma) {
2402 if (host->ops->enable_dma(host)) {
2403 printk(KERN_WARNING "%s: No suitable DMA "
2404 "available. Falling back to PIO.\n",
2405 mmc_hostname(mmc));
2406 host->flags &=
2407 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2408 }
2409 }
2410 }
2411
2412 if (host->flags & SDHCI_USE_ADMA) {
2413 /*
2414 * We need to allocate descriptors for all sg entries
2415 * (128) and potentially one alignment transfer for
2416 * each of those entries.
2417 */
2418 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2419 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2420 if (!host->adma_desc || !host->align_buffer) {
2421 kfree(host->adma_desc);
2422 kfree(host->align_buffer);
2423 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2424 "buffers. Falling back to standard DMA.\n",
2425 mmc_hostname(mmc));
2426 host->flags &= ~SDHCI_USE_ADMA;
2427 }
2428 }
2429
2430 /*
2431 * If we use DMA, then it's up to the caller to set the DMA
2432 * mask, but PIO does not need the hw shim so we set a new
2433 * mask here in that case.
2434 */
2435 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2436 host->dma_mask = DMA_BIT_MASK(64);
2437 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2438 }
2439
2440 if (host->version >= SDHCI_SPEC_300)
2441 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2442 >> SDHCI_CLOCK_BASE_SHIFT;
2443 else
2444 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2445 >> SDHCI_CLOCK_BASE_SHIFT;
2446
2447 host->max_clk *= 1000000;
2448 if (host->max_clk == 0 || host->quirks &
2449 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2450 if (!host->ops->get_max_clock) {
2451 printk(KERN_ERR
2452 "%s: Hardware doesn't specify base clock "
2453 "frequency.\n", mmc_hostname(mmc));
2454 return -ENODEV;
2455 }
2456 host->max_clk = host->ops->get_max_clock(host);
2457 }
2458
2459 /*
2460 * In case of Host Controller v3.00, find out whether clock
2461 * multiplier is supported.
2462 */
2463 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2464 SDHCI_CLOCK_MUL_SHIFT;
2465
2466 /*
2467 * In case the value in Clock Multiplier is 0, then programmable
2468 * clock mode is not supported, otherwise the actual clock
2469 * multiplier is one more than the value of Clock Multiplier
2470 * in the Capabilities Register.
2471 */
2472 if (host->clk_mul)
2473 host->clk_mul += 1;
2474
2475 /*
2476 * Set host parameters.
2477 */
2478 mmc->ops = &sdhci_ops;
2479 mmc->f_max = host->max_clk;
2480 if (host->ops->get_min_clock)
2481 mmc->f_min = host->ops->get_min_clock(host);
2482 else if (host->version >= SDHCI_SPEC_300) {
2483 if (host->clk_mul) {
2484 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2485 mmc->f_max = host->max_clk * host->clk_mul;
2486 } else
2487 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2488 } else
2489 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2490
2491 host->timeout_clk =
2492 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2493 if (host->timeout_clk == 0) {
2494 if (host->ops->get_timeout_clock) {
2495 host->timeout_clk = host->ops->get_timeout_clock(host);
2496 } else if (!(host->quirks &
2497 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2498 printk(KERN_ERR
2499 "%s: Hardware doesn't specify timeout clock "
2500 "frequency.\n", mmc_hostname(mmc));
2501 return -ENODEV;
2502 }
2503 }
2504 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2505 host->timeout_clk *= 1000;
2506
2507 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2508 host->timeout_clk = mmc->f_max / 1000;
2509
2510 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2511
2512 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2513
2514 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2515 host->flags |= SDHCI_AUTO_CMD12;
2516
2517 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2518 if ((host->version >= SDHCI_SPEC_300) &&
2519 ((host->flags & SDHCI_USE_ADMA) ||
2520 !(host->flags & SDHCI_USE_SDMA))) {
2521 host->flags |= SDHCI_AUTO_CMD23;
2522 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2523 } else {
2524 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2525 }
2526
2527 /*
2528 * A controller may support 8-bit width, but the board itself
2529 * might not have the pins brought out. Boards that support
2530 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2531 * their platform code before calling sdhci_add_host(), and we
2532 * won't assume 8-bit width for hosts without that CAP.
2533 */
2534 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2535 mmc->caps |= MMC_CAP_4_BIT_DATA;
2536
2537 if (caps[0] & SDHCI_CAN_DO_HISPD)
2538 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2539
2540 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2541 mmc_card_is_removable(mmc))
2542 mmc->caps |= MMC_CAP_NEEDS_POLL;
2543
2544 /* UHS-I mode(s) supported by the host controller. */
2545 if (host->version >= SDHCI_SPEC_300)
2546 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2547
2548 /* SDR104 supports also implies SDR50 support */
2549 if (caps[1] & SDHCI_SUPPORT_SDR104)
2550 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2551 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2552 mmc->caps |= MMC_CAP_UHS_SDR50;
2553
2554 if (caps[1] & SDHCI_SUPPORT_DDR50)
2555 mmc->caps |= MMC_CAP_UHS_DDR50;
2556
2557 /* Does the host needs tuning for SDR50? */
2558 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2559 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2560
2561 /* Driver Type(s) (A, C, D) supported by the host */
2562 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2563 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2564 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2565 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2566 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2567 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2568
2569 /* Initial value for re-tuning timer count */
2570 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2571 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2572
2573 /*
2574 * In case Re-tuning Timer is not disabled, the actual value of
2575 * re-tuning timer will be 2 ^ (n - 1).
2576 */
2577 if (host->tuning_count)
2578 host->tuning_count = 1 << (host->tuning_count - 1);
2579
2580 /* Re-tuning mode supported by the Host Controller */
2581 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2582 SDHCI_RETUNING_MODE_SHIFT;
2583
2584 ocr_avail = 0;
2585 /*
2586 * According to SD Host Controller spec v3.00, if the Host System
2587 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2588 * the value is meaningful only if Voltage Support in the Capabilities
2589 * register is set. The actual current value is 4 times the register
2590 * value.
2591 */
2592 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2593
2594 if (caps[0] & SDHCI_CAN_VDD_330) {
2595 int max_current_330;
2596
2597 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2598
2599 max_current_330 = ((max_current_caps &
2600 SDHCI_MAX_CURRENT_330_MASK) >>
2601 SDHCI_MAX_CURRENT_330_SHIFT) *
2602 SDHCI_MAX_CURRENT_MULTIPLIER;
2603
2604 if (max_current_330 > 150)
2605 mmc->caps |= MMC_CAP_SET_XPC_330;
2606 }
2607 if (caps[0] & SDHCI_CAN_VDD_300) {
2608 int max_current_300;
2609
2610 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2611
2612 max_current_300 = ((max_current_caps &
2613 SDHCI_MAX_CURRENT_300_MASK) >>
2614 SDHCI_MAX_CURRENT_300_SHIFT) *
2615 SDHCI_MAX_CURRENT_MULTIPLIER;
2616
2617 if (max_current_300 > 150)
2618 mmc->caps |= MMC_CAP_SET_XPC_300;
2619 }
2620 if (caps[0] & SDHCI_CAN_VDD_180) {
2621 int max_current_180;
2622
2623 ocr_avail |= MMC_VDD_165_195;
2624
2625 max_current_180 = ((max_current_caps &
2626 SDHCI_MAX_CURRENT_180_MASK) >>
2627 SDHCI_MAX_CURRENT_180_SHIFT) *
2628 SDHCI_MAX_CURRENT_MULTIPLIER;
2629
2630 if (max_current_180 > 150)
2631 mmc->caps |= MMC_CAP_SET_XPC_180;
2632
2633 /* Maximum current capabilities of the host at 1.8V */
2634 if (max_current_180 >= 800)
2635 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2636 else if (max_current_180 >= 600)
2637 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2638 else if (max_current_180 >= 400)
2639 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2640 else
2641 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2642 }
2643
2644 mmc->ocr_avail = ocr_avail;
2645 mmc->ocr_avail_sdio = ocr_avail;
2646 if (host->ocr_avail_sdio)
2647 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2648 mmc->ocr_avail_sd = ocr_avail;
2649 if (host->ocr_avail_sd)
2650 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2651 else /* normal SD controllers don't support 1.8V */
2652 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2653 mmc->ocr_avail_mmc = ocr_avail;
2654 if (host->ocr_avail_mmc)
2655 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2656
2657 if (mmc->ocr_avail == 0) {
2658 printk(KERN_ERR "%s: Hardware doesn't report any "
2659 "support voltages.\n", mmc_hostname(mmc));
2660 return -ENODEV;
2661 }
2662
2663 spin_lock_init(&host->lock);
2664
2665 /*
2666 * Maximum number of segments. Depends on if the hardware
2667 * can do scatter/gather or not.
2668 */
2669 if (host->flags & SDHCI_USE_ADMA)
2670 mmc->max_segs = 128;
2671 else if (host->flags & SDHCI_USE_SDMA)
2672 mmc->max_segs = 1;
2673 else /* PIO */
2674 mmc->max_segs = 128;
2675
2676 /*
2677 * Maximum number of sectors in one transfer. Limited by DMA boundary
2678 * size (512KiB).
2679 */
2680 mmc->max_req_size = 524288;
2681
2682 /*
2683 * Maximum segment size. Could be one segment with the maximum number
2684 * of bytes. When doing hardware scatter/gather, each entry cannot
2685 * be larger than 64 KiB though.
2686 */
2687 if (host->flags & SDHCI_USE_ADMA) {
2688 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2689 mmc->max_seg_size = 65535;
2690 else
2691 mmc->max_seg_size = 65536;
2692 } else {
2693 mmc->max_seg_size = mmc->max_req_size;
2694 }
2695
2696 /*
2697 * Maximum block size. This varies from controller to controller and
2698 * is specified in the capabilities register.
2699 */
2700 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2701 mmc->max_blk_size = 2;
2702 } else {
2703 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2704 SDHCI_MAX_BLOCK_SHIFT;
2705 if (mmc->max_blk_size >= 3) {
2706 printk(KERN_WARNING "%s: Invalid maximum block size, "
2707 "assuming 512 bytes\n", mmc_hostname(mmc));
2708 mmc->max_blk_size = 0;
2709 }
2710 }
2711
2712 mmc->max_blk_size = 512 << mmc->max_blk_size;
2713
2714 /*
2715 * Maximum block count.
2716 */
2717 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2718
2719 /*
2720 * Init tasklets.
2721 */
2722 tasklet_init(&host->card_tasklet,
2723 sdhci_tasklet_card, (unsigned long)host);
2724 tasklet_init(&host->finish_tasklet,
2725 sdhci_tasklet_finish, (unsigned long)host);
2726
2727 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2728
2729 if (host->version >= SDHCI_SPEC_300) {
2730 init_waitqueue_head(&host->buf_ready_int);
2731
2732 /* Initialize re-tuning timer */
2733 init_timer(&host->tuning_timer);
2734 host->tuning_timer.data = (unsigned long)host;
2735 host->tuning_timer.function = sdhci_tuning_timer;
2736 }
2737
2738 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2739 mmc_hostname(mmc), host);
2740 if (ret)
2741 goto untasklet;
2742
2743 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2744 if (IS_ERR(host->vmmc)) {
2745 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2746 host->vmmc = NULL;
2747 } else {
2748 regulator_enable(host->vmmc);
2749 }
2750
2751 sdhci_init(host, 0);
2752
2753#ifdef CONFIG_MMC_DEBUG
2754 sdhci_dumpregs(host);
2755#endif
2756
2757#ifdef SDHCI_USE_LEDS_CLASS
2758 snprintf(host->led_name, sizeof(host->led_name),
2759 "%s::", mmc_hostname(mmc));
2760 host->led.name = host->led_name;
2761 host->led.brightness = LED_OFF;
2762 host->led.default_trigger = mmc_hostname(mmc);
2763 host->led.brightness_set = sdhci_led_control;
2764
2765 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2766 if (ret)
2767 goto reset;
2768#endif
2769
2770 mmiowb();
2771
2772 mmc_add_host(mmc);
2773
2774 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2775 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2776 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2777 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2778
2779 sdhci_enable_card_detection(host);
2780
2781 return 0;
2782
2783#ifdef SDHCI_USE_LEDS_CLASS
2784reset:
2785 sdhci_reset(host, SDHCI_RESET_ALL);
2786 free_irq(host->irq, host);
2787#endif
2788untasklet:
2789 tasklet_kill(&host->card_tasklet);
2790 tasklet_kill(&host->finish_tasklet);
2791
2792 return ret;
2793}
2794
2795EXPORT_SYMBOL_GPL(sdhci_add_host);
2796
2797void sdhci_remove_host(struct sdhci_host *host, int dead)
2798{
2799 unsigned long flags;
2800
2801 if (dead) {
2802 spin_lock_irqsave(&host->lock, flags);
2803
2804 host->flags |= SDHCI_DEVICE_DEAD;
2805
2806 if (host->mrq) {
2807 printk(KERN_ERR "%s: Controller removed during "
2808 " transfer!\n", mmc_hostname(host->mmc));
2809
2810 host->mrq->cmd->error = -ENOMEDIUM;
2811 tasklet_schedule(&host->finish_tasklet);
2812 }
2813
2814 spin_unlock_irqrestore(&host->lock, flags);
2815 }
2816
2817 sdhci_disable_card_detection(host);
2818
2819 mmc_remove_host(host->mmc);
2820
2821#ifdef SDHCI_USE_LEDS_CLASS
2822 led_classdev_unregister(&host->led);
2823#endif
2824
2825 if (!dead)
2826 sdhci_reset(host, SDHCI_RESET_ALL);
2827
2828 free_irq(host->irq, host);
2829
2830 del_timer_sync(&host->timer);
2831 if (host->version >= SDHCI_SPEC_300)
2832 del_timer_sync(&host->tuning_timer);
2833
2834 tasklet_kill(&host->card_tasklet);
2835 tasklet_kill(&host->finish_tasklet);
2836
2837 if (host->vmmc) {
2838 regulator_disable(host->vmmc);
2839 regulator_put(host->vmmc);
2840 }
2841
2842 kfree(host->adma_desc);
2843 kfree(host->align_buffer);
2844
2845 host->adma_desc = NULL;
2846 host->align_buffer = NULL;
2847}
2848
2849EXPORT_SYMBOL_GPL(sdhci_remove_host);
2850
2851void sdhci_free_host(struct sdhci_host *host)
2852{
2853 mmc_free_host(host->mmc);
2854}
2855
2856EXPORT_SYMBOL_GPL(sdhci_free_host);
2857
2858/*****************************************************************************\
2859 * *
2860 * Driver init/exit *
2861 * *
2862\*****************************************************************************/
2863
2864static int __init sdhci_drv_init(void)
2865{
2866 printk(KERN_INFO DRIVER_NAME
2867 ": Secure Digital Host Controller Interface driver\n");
2868 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2869
2870 return 0;
2871}
2872
2873static void __exit sdhci_drv_exit(void)
2874{
2875}
2876
2877module_init(sdhci_drv_init);
2878module_exit(sdhci_drv_exit);
2879
2880module_param(debug_quirks, uint, 0444);
2881
2882MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2883MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2884MODULE_LICENSE("GPL");
2885
2886MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");