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1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/ktime.h>
18#include <linux/highmem.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/dma-mapping.h>
22#include <linux/slab.h>
23#include <linux/scatterlist.h>
24#include <linux/sizes.h>
25#include <linux/swiotlb.h>
26#include <linux/regulator/consumer.h>
27#include <linux/pm_runtime.h>
28#include <linux/of.h>
29
30#include <linux/leds.h>
31
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/card.h>
35#include <linux/mmc/sdio.h>
36#include <linux/mmc/slot-gpio.h>
37
38#include "sdhci.h"
39
40#define DRIVER_NAME "sdhci"
41
42#define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48#define MAX_TUNING_LOOP 40
49
50static unsigned int debug_quirks = 0;
51static unsigned int debug_quirks2;
52
53static void sdhci_finish_data(struct sdhci_host *);
54
55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57void sdhci_dumpregs(struct sdhci_host *host)
58{
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_ACMD12_ERR),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127{
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
129}
130
131static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
132{
133 u32 present;
134
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
137 return;
138
139 if (enable) {
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT;
142
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
145 } else {
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
147 }
148
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
151}
152
153static void sdhci_enable_card_detection(struct sdhci_host *host)
154{
155 sdhci_set_card_detection(host, true);
156}
157
158static void sdhci_disable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, false);
161}
162
163static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
164{
165 if (host->bus_on)
166 return;
167 host->bus_on = true;
168 pm_runtime_get_noresume(host->mmc->parent);
169}
170
171static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
172{
173 if (!host->bus_on)
174 return;
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
177}
178
179void sdhci_reset(struct sdhci_host *host, u8 mask)
180{
181 ktime_t timeout;
182
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184
185 if (mask & SDHCI_RESET_ALL) {
186 host->clock = 0;
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
190 }
191
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
194
195 /* hw clears the bit when it's done */
196 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 if (ktime_after(ktime_get(), timeout)) {
198 pr_err("%s: Reset 0x%x never completed.\n",
199 mmc_hostname(host->mmc), (int)mask);
200 sdhci_dumpregs(host);
201 return;
202 }
203 udelay(10);
204 }
205}
206EXPORT_SYMBOL_GPL(sdhci_reset);
207
208static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
209{
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 struct mmc_host *mmc = host->mmc;
212
213 if (!mmc->ops->get_cd(mmc))
214 return;
215 }
216
217 host->ops->reset(host, mask);
218
219 if (mask & SDHCI_RESET_ALL) {
220 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
221 if (host->ops->enable_dma)
222 host->ops->enable_dma(host);
223 }
224
225 /* Resetting the controller clears many */
226 host->preset_enabled = false;
227 }
228}
229
230static void sdhci_set_default_irqs(struct sdhci_host *host)
231{
232 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
233 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
234 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
235 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
236 SDHCI_INT_RESPONSE;
237
238 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
239 host->tuning_mode == SDHCI_TUNING_MODE_3)
240 host->ier |= SDHCI_INT_RETUNE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
244}
245
246static void sdhci_init(struct sdhci_host *host, int soft)
247{
248 struct mmc_host *mmc = host->mmc;
249
250 if (soft)
251 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
252 else
253 sdhci_do_reset(host, SDHCI_RESET_ALL);
254
255 sdhci_set_default_irqs(host);
256
257 host->cqe_on = false;
258
259 if (soft) {
260 /* force clock reconfiguration */
261 host->clock = 0;
262 mmc->ops->set_ios(mmc, &mmc->ios);
263 }
264}
265
266static void sdhci_reinit(struct sdhci_host *host)
267{
268 sdhci_init(host, 0);
269 sdhci_enable_card_detection(host);
270}
271
272static void __sdhci_led_activate(struct sdhci_host *host)
273{
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl |= SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279}
280
281static void __sdhci_led_deactivate(struct sdhci_host *host)
282{
283 u8 ctrl;
284
285 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
286 ctrl &= ~SDHCI_CTRL_LED;
287 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
288}
289
290#if IS_REACHABLE(CONFIG_LEDS_CLASS)
291static void sdhci_led_control(struct led_classdev *led,
292 enum led_brightness brightness)
293{
294 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
295 unsigned long flags;
296
297 spin_lock_irqsave(&host->lock, flags);
298
299 if (host->runtime_suspended)
300 goto out;
301
302 if (brightness == LED_OFF)
303 __sdhci_led_deactivate(host);
304 else
305 __sdhci_led_activate(host);
306out:
307 spin_unlock_irqrestore(&host->lock, flags);
308}
309
310static int sdhci_led_register(struct sdhci_host *host)
311{
312 struct mmc_host *mmc = host->mmc;
313
314 snprintf(host->led_name, sizeof(host->led_name),
315 "%s::", mmc_hostname(mmc));
316
317 host->led.name = host->led_name;
318 host->led.brightness = LED_OFF;
319 host->led.default_trigger = mmc_hostname(mmc);
320 host->led.brightness_set = sdhci_led_control;
321
322 return led_classdev_register(mmc_dev(mmc), &host->led);
323}
324
325static void sdhci_led_unregister(struct sdhci_host *host)
326{
327 led_classdev_unregister(&host->led);
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332}
333
334static inline void sdhci_led_deactivate(struct sdhci_host *host)
335{
336}
337
338#else
339
340static inline int sdhci_led_register(struct sdhci_host *host)
341{
342 return 0;
343}
344
345static inline void sdhci_led_unregister(struct sdhci_host *host)
346{
347}
348
349static inline void sdhci_led_activate(struct sdhci_host *host)
350{
351 __sdhci_led_activate(host);
352}
353
354static inline void sdhci_led_deactivate(struct sdhci_host *host)
355{
356 __sdhci_led_deactivate(host);
357}
358
359#endif
360
361/*****************************************************************************\
362 * *
363 * Core functions *
364 * *
365\*****************************************************************************/
366
367static void sdhci_read_block_pio(struct sdhci_host *host)
368{
369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 uninitialized_var(scratch);
372 u8 *buf;
373
374 DBG("PIO reading\n");
375
376 blksize = host->data->blksz;
377 chunk = 0;
378
379 local_irq_save(flags);
380
381 while (blksize) {
382 BUG_ON(!sg_miter_next(&host->sg_miter));
383
384 len = min(host->sg_miter.length, blksize);
385
386 blksize -= len;
387 host->sg_miter.consumed = len;
388
389 buf = host->sg_miter.addr;
390
391 while (len) {
392 if (chunk == 0) {
393 scratch = sdhci_readl(host, SDHCI_BUFFER);
394 chunk = 4;
395 }
396
397 *buf = scratch & 0xFF;
398
399 buf++;
400 scratch >>= 8;
401 chunk--;
402 len--;
403 }
404 }
405
406 sg_miter_stop(&host->sg_miter);
407
408 local_irq_restore(flags);
409}
410
411static void sdhci_write_block_pio(struct sdhci_host *host)
412{
413 unsigned long flags;
414 size_t blksize, len, chunk;
415 u32 scratch;
416 u8 *buf;
417
418 DBG("PIO writing\n");
419
420 blksize = host->data->blksz;
421 chunk = 0;
422 scratch = 0;
423
424 local_irq_save(flags);
425
426 while (blksize) {
427 BUG_ON(!sg_miter_next(&host->sg_miter));
428
429 len = min(host->sg_miter.length, blksize);
430
431 blksize -= len;
432 host->sg_miter.consumed = len;
433
434 buf = host->sg_miter.addr;
435
436 while (len) {
437 scratch |= (u32)*buf << (chunk * 8);
438
439 buf++;
440 chunk++;
441 len--;
442
443 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
444 sdhci_writel(host, scratch, SDHCI_BUFFER);
445 chunk = 0;
446 scratch = 0;
447 }
448 }
449 }
450
451 sg_miter_stop(&host->sg_miter);
452
453 local_irq_restore(flags);
454}
455
456static void sdhci_transfer_pio(struct sdhci_host *host)
457{
458 u32 mask;
459
460 if (host->blocks == 0)
461 return;
462
463 if (host->data->flags & MMC_DATA_READ)
464 mask = SDHCI_DATA_AVAILABLE;
465 else
466 mask = SDHCI_SPACE_AVAILABLE;
467
468 /*
469 * Some controllers (JMicron JMB38x) mess up the buffer bits
470 * for transfers < 4 bytes. As long as it is just one block,
471 * we can ignore the bits.
472 */
473 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
474 (host->data->blocks == 1))
475 mask = ~0;
476
477 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
478 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
479 udelay(100);
480
481 if (host->data->flags & MMC_DATA_READ)
482 sdhci_read_block_pio(host);
483 else
484 sdhci_write_block_pio(host);
485
486 host->blocks--;
487 if (host->blocks == 0)
488 break;
489 }
490
491 DBG("PIO transfer complete.\n");
492}
493
494static int sdhci_pre_dma_transfer(struct sdhci_host *host,
495 struct mmc_data *data, int cookie)
496{
497 int sg_count;
498
499 /*
500 * If the data buffers are already mapped, return the previous
501 * dma_map_sg() result.
502 */
503 if (data->host_cookie == COOKIE_PRE_MAPPED)
504 return data->sg_count;
505
506 /* Bounce write requests to the bounce buffer */
507 if (host->bounce_buffer) {
508 unsigned int length = data->blksz * data->blocks;
509
510 if (length > host->bounce_buffer_size) {
511 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
512 mmc_hostname(host->mmc), length,
513 host->bounce_buffer_size);
514 return -EIO;
515 }
516 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
517 /* Copy the data to the bounce buffer */
518 sg_copy_to_buffer(data->sg, data->sg_len,
519 host->bounce_buffer,
520 length);
521 }
522 /* Switch ownership to the DMA */
523 dma_sync_single_for_device(host->mmc->parent,
524 host->bounce_addr,
525 host->bounce_buffer_size,
526 mmc_get_dma_dir(data));
527 /* Just a dummy value */
528 sg_count = 1;
529 } else {
530 /* Just access the data directly from memory */
531 sg_count = dma_map_sg(mmc_dev(host->mmc),
532 data->sg, data->sg_len,
533 mmc_get_dma_dir(data));
534 }
535
536 if (sg_count == 0)
537 return -ENOSPC;
538
539 data->sg_count = sg_count;
540 data->host_cookie = cookie;
541
542 return sg_count;
543}
544
545static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
546{
547 local_irq_save(*flags);
548 return kmap_atomic(sg_page(sg)) + sg->offset;
549}
550
551static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
552{
553 kunmap_atomic(buffer);
554 local_irq_restore(*flags);
555}
556
557static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
558 dma_addr_t addr, int len, unsigned cmd)
559{
560 struct sdhci_adma2_64_desc *dma_desc = desc;
561
562 /* 32-bit and 64-bit descriptors have these members in same position */
563 dma_desc->cmd = cpu_to_le16(cmd);
564 dma_desc->len = cpu_to_le16(len);
565 dma_desc->addr_lo = cpu_to_le32((u32)addr);
566
567 if (host->flags & SDHCI_USE_64_BIT_DMA)
568 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
569}
570
571static void sdhci_adma_mark_end(void *desc)
572{
573 struct sdhci_adma2_64_desc *dma_desc = desc;
574
575 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
576 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
577}
578
579static void sdhci_adma_table_pre(struct sdhci_host *host,
580 struct mmc_data *data, int sg_count)
581{
582 struct scatterlist *sg;
583 unsigned long flags;
584 dma_addr_t addr, align_addr;
585 void *desc, *align;
586 char *buffer;
587 int len, offset, i;
588
589 /*
590 * The spec does not specify endianness of descriptor table.
591 * We currently guess that it is LE.
592 */
593
594 host->sg_count = sg_count;
595
596 desc = host->adma_table;
597 align = host->align_buffer;
598
599 align_addr = host->align_addr;
600
601 for_each_sg(data->sg, sg, host->sg_count, i) {
602 addr = sg_dma_address(sg);
603 len = sg_dma_len(sg);
604
605 /*
606 * The SDHCI specification states that ADMA addresses must
607 * be 32-bit aligned. If they aren't, then we use a bounce
608 * buffer for the (up to three) bytes that screw up the
609 * alignment.
610 */
611 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
612 SDHCI_ADMA2_MASK;
613 if (offset) {
614 if (data->flags & MMC_DATA_WRITE) {
615 buffer = sdhci_kmap_atomic(sg, &flags);
616 memcpy(align, buffer, offset);
617 sdhci_kunmap_atomic(buffer, &flags);
618 }
619
620 /* tran, valid */
621 sdhci_adma_write_desc(host, desc, align_addr, offset,
622 ADMA2_TRAN_VALID);
623
624 BUG_ON(offset > 65536);
625
626 align += SDHCI_ADMA2_ALIGN;
627 align_addr += SDHCI_ADMA2_ALIGN;
628
629 desc += host->desc_sz;
630
631 addr += offset;
632 len -= offset;
633 }
634
635 BUG_ON(len > 65536);
636
637 if (len) {
638 /* tran, valid */
639 sdhci_adma_write_desc(host, desc, addr, len,
640 ADMA2_TRAN_VALID);
641 desc += host->desc_sz;
642 }
643
644 /*
645 * If this triggers then we have a calculation bug
646 * somewhere. :/
647 */
648 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
649 }
650
651 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
652 /* Mark the last descriptor as the terminating descriptor */
653 if (desc != host->adma_table) {
654 desc -= host->desc_sz;
655 sdhci_adma_mark_end(desc);
656 }
657 } else {
658 /* Add a terminating entry - nop, end, valid */
659 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
660 }
661}
662
663static void sdhci_adma_table_post(struct sdhci_host *host,
664 struct mmc_data *data)
665{
666 struct scatterlist *sg;
667 int i, size;
668 void *align;
669 char *buffer;
670 unsigned long flags;
671
672 if (data->flags & MMC_DATA_READ) {
673 bool has_unaligned = false;
674
675 /* Do a quick scan of the SG list for any unaligned mappings */
676 for_each_sg(data->sg, sg, host->sg_count, i)
677 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
678 has_unaligned = true;
679 break;
680 }
681
682 if (has_unaligned) {
683 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
684 data->sg_len, DMA_FROM_DEVICE);
685
686 align = host->align_buffer;
687
688 for_each_sg(data->sg, sg, host->sg_count, i) {
689 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
690 size = SDHCI_ADMA2_ALIGN -
691 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
692
693 buffer = sdhci_kmap_atomic(sg, &flags);
694 memcpy(buffer, align, size);
695 sdhci_kunmap_atomic(buffer, &flags);
696
697 align += SDHCI_ADMA2_ALIGN;
698 }
699 }
700 }
701 }
702}
703
704static u32 sdhci_sdma_address(struct sdhci_host *host)
705{
706 if (host->bounce_buffer)
707 return host->bounce_addr;
708 else
709 return sg_dma_address(host->data->sg);
710}
711
712static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
713{
714 u8 count;
715 struct mmc_data *data = cmd->data;
716 unsigned target_timeout, current_timeout;
717
718 /*
719 * If the host controller provides us with an incorrect timeout
720 * value, just skip the check and use 0xE. The hardware may take
721 * longer to time out, but that's much better than having a too-short
722 * timeout value.
723 */
724 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
725 return 0xE;
726
727 /* Unspecified timeout, assume max */
728 if (!data && !cmd->busy_timeout)
729 return 0xE;
730
731 /* timeout in us */
732 if (!data)
733 target_timeout = cmd->busy_timeout * 1000;
734 else {
735 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
736 if (host->clock && data->timeout_clks) {
737 unsigned long long val;
738
739 /*
740 * data->timeout_clks is in units of clock cycles.
741 * host->clock is in Hz. target_timeout is in us.
742 * Hence, us = 1000000 * cycles / Hz. Round up.
743 */
744 val = 1000000ULL * data->timeout_clks;
745 if (do_div(val, host->clock))
746 target_timeout++;
747 target_timeout += val;
748 }
749 }
750
751 /*
752 * Figure out needed cycles.
753 * We do this in steps in order to fit inside a 32 bit int.
754 * The first step is the minimum timeout, which will have a
755 * minimum resolution of 6 bits:
756 * (1) 2^13*1000 > 2^22,
757 * (2) host->timeout_clk < 2^16
758 * =>
759 * (1) / (2) > 2^6
760 */
761 count = 0;
762 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
763 while (current_timeout < target_timeout) {
764 count++;
765 current_timeout <<= 1;
766 if (count >= 0xF)
767 break;
768 }
769
770 if (count >= 0xF) {
771 DBG("Too large timeout 0x%x requested for CMD%d!\n",
772 count, cmd->opcode);
773 count = 0xE;
774 }
775
776 return count;
777}
778
779static void sdhci_set_transfer_irqs(struct sdhci_host *host)
780{
781 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
782 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
783
784 if (host->flags & SDHCI_REQ_USE_DMA)
785 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
786 else
787 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
788
789 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
790 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
791}
792
793static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
794{
795 u8 count;
796
797 if (host->ops->set_timeout) {
798 host->ops->set_timeout(host, cmd);
799 } else {
800 count = sdhci_calc_timeout(host, cmd);
801 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
802 }
803}
804
805static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
806{
807 u8 ctrl;
808 struct mmc_data *data = cmd->data;
809
810 if (sdhci_data_line_cmd(cmd))
811 sdhci_set_timeout(host, cmd);
812
813 if (!data)
814 return;
815
816 WARN_ON(host->data);
817
818 /* Sanity checks */
819 BUG_ON(data->blksz * data->blocks > 524288);
820 BUG_ON(data->blksz > host->mmc->max_blk_size);
821 BUG_ON(data->blocks > 65535);
822
823 host->data = data;
824 host->data_early = 0;
825 host->data->bytes_xfered = 0;
826
827 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
828 struct scatterlist *sg;
829 unsigned int length_mask, offset_mask;
830 int i;
831
832 host->flags |= SDHCI_REQ_USE_DMA;
833
834 /*
835 * FIXME: This doesn't account for merging when mapping the
836 * scatterlist.
837 *
838 * The assumption here being that alignment and lengths are
839 * the same after DMA mapping to device address space.
840 */
841 length_mask = 0;
842 offset_mask = 0;
843 if (host->flags & SDHCI_USE_ADMA) {
844 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
845 length_mask = 3;
846 /*
847 * As we use up to 3 byte chunks to work
848 * around alignment problems, we need to
849 * check the offset as well.
850 */
851 offset_mask = 3;
852 }
853 } else {
854 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
855 length_mask = 3;
856 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
857 offset_mask = 3;
858 }
859
860 if (unlikely(length_mask | offset_mask)) {
861 for_each_sg(data->sg, sg, data->sg_len, i) {
862 if (sg->length & length_mask) {
863 DBG("Reverting to PIO because of transfer size (%d)\n",
864 sg->length);
865 host->flags &= ~SDHCI_REQ_USE_DMA;
866 break;
867 }
868 if (sg->offset & offset_mask) {
869 DBG("Reverting to PIO because of bad alignment\n");
870 host->flags &= ~SDHCI_REQ_USE_DMA;
871 break;
872 }
873 }
874 }
875 }
876
877 if (host->flags & SDHCI_REQ_USE_DMA) {
878 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
879
880 if (sg_cnt <= 0) {
881 /*
882 * This only happens when someone fed
883 * us an invalid request.
884 */
885 WARN_ON(1);
886 host->flags &= ~SDHCI_REQ_USE_DMA;
887 } else if (host->flags & SDHCI_USE_ADMA) {
888 sdhci_adma_table_pre(host, data, sg_cnt);
889
890 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
891 if (host->flags & SDHCI_USE_64_BIT_DMA)
892 sdhci_writel(host,
893 (u64)host->adma_addr >> 32,
894 SDHCI_ADMA_ADDRESS_HI);
895 } else {
896 WARN_ON(sg_cnt != 1);
897 sdhci_writel(host, sdhci_sdma_address(host),
898 SDHCI_DMA_ADDRESS);
899 }
900 }
901
902 /*
903 * Always adjust the DMA selection as some controllers
904 * (e.g. JMicron) can't do PIO properly when the selection
905 * is ADMA.
906 */
907 if (host->version >= SDHCI_SPEC_200) {
908 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
909 ctrl &= ~SDHCI_CTRL_DMA_MASK;
910 if ((host->flags & SDHCI_REQ_USE_DMA) &&
911 (host->flags & SDHCI_USE_ADMA)) {
912 if (host->flags & SDHCI_USE_64_BIT_DMA)
913 ctrl |= SDHCI_CTRL_ADMA64;
914 else
915 ctrl |= SDHCI_CTRL_ADMA32;
916 } else {
917 ctrl |= SDHCI_CTRL_SDMA;
918 }
919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
920 }
921
922 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
923 int flags;
924
925 flags = SG_MITER_ATOMIC;
926 if (host->data->flags & MMC_DATA_READ)
927 flags |= SG_MITER_TO_SG;
928 else
929 flags |= SG_MITER_FROM_SG;
930 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
931 host->blocks = data->blocks;
932 }
933
934 sdhci_set_transfer_irqs(host);
935
936 /* Set the DMA boundary value and block size */
937 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
938 SDHCI_BLOCK_SIZE);
939 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
940}
941
942static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
943 struct mmc_request *mrq)
944{
945 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
946 !mrq->cap_cmd_during_tfr;
947}
948
949static void sdhci_set_transfer_mode(struct sdhci_host *host,
950 struct mmc_command *cmd)
951{
952 u16 mode = 0;
953 struct mmc_data *data = cmd->data;
954
955 if (data == NULL) {
956 if (host->quirks2 &
957 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
958 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
959 } else {
960 /* clear Auto CMD settings for no data CMDs */
961 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
962 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
963 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
964 }
965 return;
966 }
967
968 WARN_ON(!host->data);
969
970 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
971 mode = SDHCI_TRNS_BLK_CNT_EN;
972
973 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
974 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
975 /*
976 * If we are sending CMD23, CMD12 never gets sent
977 * on successful completion (so no Auto-CMD12).
978 */
979 if (sdhci_auto_cmd12(host, cmd->mrq) &&
980 (cmd->opcode != SD_IO_RW_EXTENDED))
981 mode |= SDHCI_TRNS_AUTO_CMD12;
982 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
983 mode |= SDHCI_TRNS_AUTO_CMD23;
984 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
985 }
986 }
987
988 if (data->flags & MMC_DATA_READ)
989 mode |= SDHCI_TRNS_READ;
990 if (host->flags & SDHCI_REQ_USE_DMA)
991 mode |= SDHCI_TRNS_DMA;
992
993 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
994}
995
996static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
997{
998 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
999 ((mrq->cmd && mrq->cmd->error) ||
1000 (mrq->sbc && mrq->sbc->error) ||
1001 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
1002 (mrq->data->stop && mrq->data->stop->error))) ||
1003 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1004}
1005
1006static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1007{
1008 int i;
1009
1010 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1011 if (host->mrqs_done[i] == mrq) {
1012 WARN_ON(1);
1013 return;
1014 }
1015 }
1016
1017 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1018 if (!host->mrqs_done[i]) {
1019 host->mrqs_done[i] = mrq;
1020 break;
1021 }
1022 }
1023
1024 WARN_ON(i >= SDHCI_MAX_MRQS);
1025
1026 tasklet_schedule(&host->finish_tasklet);
1027}
1028
1029static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1030{
1031 if (host->cmd && host->cmd->mrq == mrq)
1032 host->cmd = NULL;
1033
1034 if (host->data_cmd && host->data_cmd->mrq == mrq)
1035 host->data_cmd = NULL;
1036
1037 if (host->data && host->data->mrq == mrq)
1038 host->data = NULL;
1039
1040 if (sdhci_needs_reset(host, mrq))
1041 host->pending_reset = true;
1042
1043 __sdhci_finish_mrq(host, mrq);
1044}
1045
1046static void sdhci_finish_data(struct sdhci_host *host)
1047{
1048 struct mmc_command *data_cmd = host->data_cmd;
1049 struct mmc_data *data = host->data;
1050
1051 host->data = NULL;
1052 host->data_cmd = NULL;
1053
1054 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1055 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1056 sdhci_adma_table_post(host, data);
1057
1058 /*
1059 * The specification states that the block count register must
1060 * be updated, but it does not specify at what point in the
1061 * data flow. That makes the register entirely useless to read
1062 * back so we have to assume that nothing made it to the card
1063 * in the event of an error.
1064 */
1065 if (data->error)
1066 data->bytes_xfered = 0;
1067 else
1068 data->bytes_xfered = data->blksz * data->blocks;
1069
1070 /*
1071 * Need to send CMD12 if -
1072 * a) open-ended multiblock transfer (no CMD23)
1073 * b) error in multiblock transfer
1074 */
1075 if (data->stop &&
1076 (data->error ||
1077 !data->mrq->sbc)) {
1078
1079 /*
1080 * The controller needs a reset of internal state machines
1081 * upon error conditions.
1082 */
1083 if (data->error) {
1084 if (!host->cmd || host->cmd == data_cmd)
1085 sdhci_do_reset(host, SDHCI_RESET_CMD);
1086 sdhci_do_reset(host, SDHCI_RESET_DATA);
1087 }
1088
1089 /*
1090 * 'cap_cmd_during_tfr' request must not use the command line
1091 * after mmc_command_done() has been called. It is upper layer's
1092 * responsibility to send the stop command if required.
1093 */
1094 if (data->mrq->cap_cmd_during_tfr) {
1095 sdhci_finish_mrq(host, data->mrq);
1096 } else {
1097 /* Avoid triggering warning in sdhci_send_command() */
1098 host->cmd = NULL;
1099 sdhci_send_command(host, data->stop);
1100 }
1101 } else {
1102 sdhci_finish_mrq(host, data->mrq);
1103 }
1104}
1105
1106static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1107 unsigned long timeout)
1108{
1109 if (sdhci_data_line_cmd(mrq->cmd))
1110 mod_timer(&host->data_timer, timeout);
1111 else
1112 mod_timer(&host->timer, timeout);
1113}
1114
1115static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1116{
1117 if (sdhci_data_line_cmd(mrq->cmd))
1118 del_timer(&host->data_timer);
1119 else
1120 del_timer(&host->timer);
1121}
1122
1123void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1124{
1125 int flags;
1126 u32 mask;
1127 unsigned long timeout;
1128
1129 WARN_ON(host->cmd);
1130
1131 /* Initially, a command has no error */
1132 cmd->error = 0;
1133
1134 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1135 cmd->opcode == MMC_STOP_TRANSMISSION)
1136 cmd->flags |= MMC_RSP_BUSY;
1137
1138 /* Wait max 10 ms */
1139 timeout = 10;
1140
1141 mask = SDHCI_CMD_INHIBIT;
1142 if (sdhci_data_line_cmd(cmd))
1143 mask |= SDHCI_DATA_INHIBIT;
1144
1145 /* We shouldn't wait for data inihibit for stop commands, even
1146 though they might use busy signaling */
1147 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1148 mask &= ~SDHCI_DATA_INHIBIT;
1149
1150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1151 if (timeout == 0) {
1152 pr_err("%s: Controller never released inhibit bit(s).\n",
1153 mmc_hostname(host->mmc));
1154 sdhci_dumpregs(host);
1155 cmd->error = -EIO;
1156 sdhci_finish_mrq(host, cmd->mrq);
1157 return;
1158 }
1159 timeout--;
1160 mdelay(1);
1161 }
1162
1163 timeout = jiffies;
1164 if (!cmd->data && cmd->busy_timeout > 9000)
1165 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1166 else
1167 timeout += 10 * HZ;
1168 sdhci_mod_timer(host, cmd->mrq, timeout);
1169
1170 host->cmd = cmd;
1171 if (sdhci_data_line_cmd(cmd)) {
1172 WARN_ON(host->data_cmd);
1173 host->data_cmd = cmd;
1174 }
1175
1176 sdhci_prepare_data(host, cmd);
1177
1178 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1179
1180 sdhci_set_transfer_mode(host, cmd);
1181
1182 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1183 pr_err("%s: Unsupported response type!\n",
1184 mmc_hostname(host->mmc));
1185 cmd->error = -EINVAL;
1186 sdhci_finish_mrq(host, cmd->mrq);
1187 return;
1188 }
1189
1190 if (!(cmd->flags & MMC_RSP_PRESENT))
1191 flags = SDHCI_CMD_RESP_NONE;
1192 else if (cmd->flags & MMC_RSP_136)
1193 flags = SDHCI_CMD_RESP_LONG;
1194 else if (cmd->flags & MMC_RSP_BUSY)
1195 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1196 else
1197 flags = SDHCI_CMD_RESP_SHORT;
1198
1199 if (cmd->flags & MMC_RSP_CRC)
1200 flags |= SDHCI_CMD_CRC;
1201 if (cmd->flags & MMC_RSP_OPCODE)
1202 flags |= SDHCI_CMD_INDEX;
1203
1204 /* CMD19 is special in that the Data Present Select should be set */
1205 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1206 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1207 flags |= SDHCI_CMD_DATA;
1208
1209 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1210}
1211EXPORT_SYMBOL_GPL(sdhci_send_command);
1212
1213static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1214{
1215 int i, reg;
1216
1217 for (i = 0; i < 4; i++) {
1218 reg = SDHCI_RESPONSE + (3 - i) * 4;
1219 cmd->resp[i] = sdhci_readl(host, reg);
1220 }
1221
1222 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1223 return;
1224
1225 /* CRC is stripped so we need to do some shifting */
1226 for (i = 0; i < 4; i++) {
1227 cmd->resp[i] <<= 8;
1228 if (i != 3)
1229 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1230 }
1231}
1232
1233static void sdhci_finish_command(struct sdhci_host *host)
1234{
1235 struct mmc_command *cmd = host->cmd;
1236
1237 host->cmd = NULL;
1238
1239 if (cmd->flags & MMC_RSP_PRESENT) {
1240 if (cmd->flags & MMC_RSP_136) {
1241 sdhci_read_rsp_136(host, cmd);
1242 } else {
1243 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1244 }
1245 }
1246
1247 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1248 mmc_command_done(host->mmc, cmd->mrq);
1249
1250 /*
1251 * The host can send and interrupt when the busy state has
1252 * ended, allowing us to wait without wasting CPU cycles.
1253 * The busy signal uses DAT0 so this is similar to waiting
1254 * for data to complete.
1255 *
1256 * Note: The 1.0 specification is a bit ambiguous about this
1257 * feature so there might be some problems with older
1258 * controllers.
1259 */
1260 if (cmd->flags & MMC_RSP_BUSY) {
1261 if (cmd->data) {
1262 DBG("Cannot wait for busy signal when also doing a data transfer");
1263 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1264 cmd == host->data_cmd) {
1265 /* Command complete before busy is ended */
1266 return;
1267 }
1268 }
1269
1270 /* Finished CMD23, now send actual command. */
1271 if (cmd == cmd->mrq->sbc) {
1272 sdhci_send_command(host, cmd->mrq->cmd);
1273 } else {
1274
1275 /* Processed actual command. */
1276 if (host->data && host->data_early)
1277 sdhci_finish_data(host);
1278
1279 if (!cmd->data)
1280 sdhci_finish_mrq(host, cmd->mrq);
1281 }
1282}
1283
1284static u16 sdhci_get_preset_value(struct sdhci_host *host)
1285{
1286 u16 preset = 0;
1287
1288 switch (host->timing) {
1289 case MMC_TIMING_UHS_SDR12:
1290 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1291 break;
1292 case MMC_TIMING_UHS_SDR25:
1293 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1294 break;
1295 case MMC_TIMING_UHS_SDR50:
1296 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1297 break;
1298 case MMC_TIMING_UHS_SDR104:
1299 case MMC_TIMING_MMC_HS200:
1300 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1301 break;
1302 case MMC_TIMING_UHS_DDR50:
1303 case MMC_TIMING_MMC_DDR52:
1304 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1305 break;
1306 case MMC_TIMING_MMC_HS400:
1307 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1308 break;
1309 default:
1310 pr_warn("%s: Invalid UHS-I mode selected\n",
1311 mmc_hostname(host->mmc));
1312 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1313 break;
1314 }
1315 return preset;
1316}
1317
1318u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1319 unsigned int *actual_clock)
1320{
1321 int div = 0; /* Initialized for compiler warning */
1322 int real_div = div, clk_mul = 1;
1323 u16 clk = 0;
1324 bool switch_base_clk = false;
1325
1326 if (host->version >= SDHCI_SPEC_300) {
1327 if (host->preset_enabled) {
1328 u16 pre_val;
1329
1330 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1331 pre_val = sdhci_get_preset_value(host);
1332 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1333 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1334 if (host->clk_mul &&
1335 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1336 clk = SDHCI_PROG_CLOCK_MODE;
1337 real_div = div + 1;
1338 clk_mul = host->clk_mul;
1339 } else {
1340 real_div = max_t(int, 1, div << 1);
1341 }
1342 goto clock_set;
1343 }
1344
1345 /*
1346 * Check if the Host Controller supports Programmable Clock
1347 * Mode.
1348 */
1349 if (host->clk_mul) {
1350 for (div = 1; div <= 1024; div++) {
1351 if ((host->max_clk * host->clk_mul / div)
1352 <= clock)
1353 break;
1354 }
1355 if ((host->max_clk * host->clk_mul / div) <= clock) {
1356 /*
1357 * Set Programmable Clock Mode in the Clock
1358 * Control register.
1359 */
1360 clk = SDHCI_PROG_CLOCK_MODE;
1361 real_div = div;
1362 clk_mul = host->clk_mul;
1363 div--;
1364 } else {
1365 /*
1366 * Divisor can be too small to reach clock
1367 * speed requirement. Then use the base clock.
1368 */
1369 switch_base_clk = true;
1370 }
1371 }
1372
1373 if (!host->clk_mul || switch_base_clk) {
1374 /* Version 3.00 divisors must be a multiple of 2. */
1375 if (host->max_clk <= clock)
1376 div = 1;
1377 else {
1378 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1379 div += 2) {
1380 if ((host->max_clk / div) <= clock)
1381 break;
1382 }
1383 }
1384 real_div = div;
1385 div >>= 1;
1386 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1387 && !div && host->max_clk <= 25000000)
1388 div = 1;
1389 }
1390 } else {
1391 /* Version 2.00 divisors must be a power of 2. */
1392 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1393 if ((host->max_clk / div) <= clock)
1394 break;
1395 }
1396 real_div = div;
1397 div >>= 1;
1398 }
1399
1400clock_set:
1401 if (real_div)
1402 *actual_clock = (host->max_clk * clk_mul) / real_div;
1403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1405 << SDHCI_DIVIDER_HI_SHIFT;
1406
1407 return clk;
1408}
1409EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1410
1411void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1412{
1413 ktime_t timeout;
1414
1415 clk |= SDHCI_CLOCK_INT_EN;
1416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1417
1418 /* Wait max 20 ms */
1419 timeout = ktime_add_ms(ktime_get(), 20);
1420 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1421 & SDHCI_CLOCK_INT_STABLE)) {
1422 if (ktime_after(ktime_get(), timeout)) {
1423 pr_err("%s: Internal clock never stabilised.\n",
1424 mmc_hostname(host->mmc));
1425 sdhci_dumpregs(host);
1426 return;
1427 }
1428 udelay(10);
1429 }
1430
1431 clk |= SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433}
1434EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1435
1436void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1437{
1438 u16 clk;
1439
1440 host->mmc->actual_clock = 0;
1441
1442 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1443
1444 if (clock == 0)
1445 return;
1446
1447 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1448 sdhci_enable_clk(host, clk);
1449}
1450EXPORT_SYMBOL_GPL(sdhci_set_clock);
1451
1452static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1453 unsigned short vdd)
1454{
1455 struct mmc_host *mmc = host->mmc;
1456
1457 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1458
1459 if (mode != MMC_POWER_OFF)
1460 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1461 else
1462 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1463}
1464
1465void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1466 unsigned short vdd)
1467{
1468 u8 pwr = 0;
1469
1470 if (mode != MMC_POWER_OFF) {
1471 switch (1 << vdd) {
1472 case MMC_VDD_165_195:
1473 /*
1474 * Without a regulator, SDHCI does not support 2.0v
1475 * so we only get here if the driver deliberately
1476 * added the 2.0v range to ocr_avail. Map it to 1.8v
1477 * for the purpose of turning on the power.
1478 */
1479 case MMC_VDD_20_21:
1480 pwr = SDHCI_POWER_180;
1481 break;
1482 case MMC_VDD_29_30:
1483 case MMC_VDD_30_31:
1484 pwr = SDHCI_POWER_300;
1485 break;
1486 case MMC_VDD_32_33:
1487 case MMC_VDD_33_34:
1488 pwr = SDHCI_POWER_330;
1489 break;
1490 default:
1491 WARN(1, "%s: Invalid vdd %#x\n",
1492 mmc_hostname(host->mmc), vdd);
1493 break;
1494 }
1495 }
1496
1497 if (host->pwr == pwr)
1498 return;
1499
1500 host->pwr = pwr;
1501
1502 if (pwr == 0) {
1503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1504 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1505 sdhci_runtime_pm_bus_off(host);
1506 } else {
1507 /*
1508 * Spec says that we should clear the power reg before setting
1509 * a new value. Some controllers don't seem to like this though.
1510 */
1511 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1512 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1513
1514 /*
1515 * At least the Marvell CaFe chip gets confused if we set the
1516 * voltage and set turn on power at the same time, so set the
1517 * voltage first.
1518 */
1519 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1520 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1521
1522 pwr |= SDHCI_POWER_ON;
1523
1524 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1525
1526 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1527 sdhci_runtime_pm_bus_on(host);
1528
1529 /*
1530 * Some controllers need an extra 10ms delay of 10ms before
1531 * they can apply clock after applying power
1532 */
1533 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1534 mdelay(10);
1535 }
1536}
1537EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1538
1539void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1540 unsigned short vdd)
1541{
1542 if (IS_ERR(host->mmc->supply.vmmc))
1543 sdhci_set_power_noreg(host, mode, vdd);
1544 else
1545 sdhci_set_power_reg(host, mode, vdd);
1546}
1547EXPORT_SYMBOL_GPL(sdhci_set_power);
1548
1549/*****************************************************************************\
1550 * *
1551 * MMC callbacks *
1552 * *
1553\*****************************************************************************/
1554
1555static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1556{
1557 struct sdhci_host *host;
1558 int present;
1559 unsigned long flags;
1560
1561 host = mmc_priv(mmc);
1562
1563 /* Firstly check card presence */
1564 present = mmc->ops->get_cd(mmc);
1565
1566 spin_lock_irqsave(&host->lock, flags);
1567
1568 sdhci_led_activate(host);
1569
1570 /*
1571 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1572 * requests if Auto-CMD12 is enabled.
1573 */
1574 if (sdhci_auto_cmd12(host, mrq)) {
1575 if (mrq->stop) {
1576 mrq->data->stop = NULL;
1577 mrq->stop = NULL;
1578 }
1579 }
1580
1581 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1582 mrq->cmd->error = -ENOMEDIUM;
1583 sdhci_finish_mrq(host, mrq);
1584 } else {
1585 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1586 sdhci_send_command(host, mrq->sbc);
1587 else
1588 sdhci_send_command(host, mrq->cmd);
1589 }
1590
1591 mmiowb();
1592 spin_unlock_irqrestore(&host->lock, flags);
1593}
1594
1595void sdhci_set_bus_width(struct sdhci_host *host, int width)
1596{
1597 u8 ctrl;
1598
1599 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1600 if (width == MMC_BUS_WIDTH_8) {
1601 ctrl &= ~SDHCI_CTRL_4BITBUS;
1602 ctrl |= SDHCI_CTRL_8BITBUS;
1603 } else {
1604 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1605 ctrl &= ~SDHCI_CTRL_8BITBUS;
1606 if (width == MMC_BUS_WIDTH_4)
1607 ctrl |= SDHCI_CTRL_4BITBUS;
1608 else
1609 ctrl &= ~SDHCI_CTRL_4BITBUS;
1610 }
1611 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1612}
1613EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1614
1615void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1616{
1617 u16 ctrl_2;
1618
1619 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1620 /* Select Bus Speed Mode for host */
1621 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1622 if ((timing == MMC_TIMING_MMC_HS200) ||
1623 (timing == MMC_TIMING_UHS_SDR104))
1624 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1625 else if (timing == MMC_TIMING_UHS_SDR12)
1626 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1627 else if (timing == MMC_TIMING_UHS_SDR25)
1628 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1629 else if (timing == MMC_TIMING_UHS_SDR50)
1630 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1631 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1632 (timing == MMC_TIMING_MMC_DDR52))
1633 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1634 else if (timing == MMC_TIMING_MMC_HS400)
1635 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1636 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1637}
1638EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1639
1640void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 u8 ctrl;
1644
1645 if (ios->power_mode == MMC_POWER_UNDEFINED)
1646 return;
1647
1648 if (host->flags & SDHCI_DEVICE_DEAD) {
1649 if (!IS_ERR(mmc->supply.vmmc) &&
1650 ios->power_mode == MMC_POWER_OFF)
1651 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1652 return;
1653 }
1654
1655 /*
1656 * Reset the chip on each power off.
1657 * Should clear out any weird states.
1658 */
1659 if (ios->power_mode == MMC_POWER_OFF) {
1660 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1661 sdhci_reinit(host);
1662 }
1663
1664 if (host->version >= SDHCI_SPEC_300 &&
1665 (ios->power_mode == MMC_POWER_UP) &&
1666 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1667 sdhci_enable_preset_value(host, false);
1668
1669 if (!ios->clock || ios->clock != host->clock) {
1670 host->ops->set_clock(host, ios->clock);
1671 host->clock = ios->clock;
1672
1673 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1674 host->clock) {
1675 host->timeout_clk = host->mmc->actual_clock ?
1676 host->mmc->actual_clock / 1000 :
1677 host->clock / 1000;
1678 host->mmc->max_busy_timeout =
1679 host->ops->get_max_timeout_count ?
1680 host->ops->get_max_timeout_count(host) :
1681 1 << 27;
1682 host->mmc->max_busy_timeout /= host->timeout_clk;
1683 }
1684 }
1685
1686 if (host->ops->set_power)
1687 host->ops->set_power(host, ios->power_mode, ios->vdd);
1688 else
1689 sdhci_set_power(host, ios->power_mode, ios->vdd);
1690
1691 if (host->ops->platform_send_init_74_clocks)
1692 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1693
1694 host->ops->set_bus_width(host, ios->bus_width);
1695
1696 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1697
1698 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1699 if (ios->timing == MMC_TIMING_SD_HS ||
1700 ios->timing == MMC_TIMING_MMC_HS ||
1701 ios->timing == MMC_TIMING_MMC_HS400 ||
1702 ios->timing == MMC_TIMING_MMC_HS200 ||
1703 ios->timing == MMC_TIMING_MMC_DDR52 ||
1704 ios->timing == MMC_TIMING_UHS_SDR50 ||
1705 ios->timing == MMC_TIMING_UHS_SDR104 ||
1706 ios->timing == MMC_TIMING_UHS_DDR50 ||
1707 ios->timing == MMC_TIMING_UHS_SDR25)
1708 ctrl |= SDHCI_CTRL_HISPD;
1709 else
1710 ctrl &= ~SDHCI_CTRL_HISPD;
1711 }
1712
1713 if (host->version >= SDHCI_SPEC_300) {
1714 u16 clk, ctrl_2;
1715
1716 if (!host->preset_enabled) {
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1718 /*
1719 * We only need to set Driver Strength if the
1720 * preset value enable is not set.
1721 */
1722 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1723 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1724 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1725 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1726 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1727 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1728 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1729 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1730 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1731 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1732 else {
1733 pr_warn("%s: invalid driver type, default to driver type B\n",
1734 mmc_hostname(mmc));
1735 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1736 }
1737
1738 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1739 } else {
1740 /*
1741 * According to SDHC Spec v3.00, if the Preset Value
1742 * Enable in the Host Control 2 register is set, we
1743 * need to reset SD Clock Enable before changing High
1744 * Speed Enable to avoid generating clock gliches.
1745 */
1746
1747 /* Reset SD Clock Enable */
1748 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1749 clk &= ~SDHCI_CLOCK_CARD_EN;
1750 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1751
1752 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1753
1754 /* Re-enable SD Clock */
1755 host->ops->set_clock(host, host->clock);
1756 }
1757
1758 /* Reset SD Clock Enable */
1759 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1760 clk &= ~SDHCI_CLOCK_CARD_EN;
1761 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1762
1763 host->ops->set_uhs_signaling(host, ios->timing);
1764 host->timing = ios->timing;
1765
1766 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1767 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1768 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1769 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1770 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1771 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1772 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1773 u16 preset;
1774
1775 sdhci_enable_preset_value(host, true);
1776 preset = sdhci_get_preset_value(host);
1777 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1778 >> SDHCI_PRESET_DRV_SHIFT;
1779 }
1780
1781 /* Re-enable SD Clock */
1782 host->ops->set_clock(host, host->clock);
1783 } else
1784 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1785
1786 /*
1787 * Some (ENE) controllers go apeshit on some ios operation,
1788 * signalling timeout and CRC errors even on CMD0. Resetting
1789 * it on each ios seems to solve the problem.
1790 */
1791 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1792 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1793
1794 mmiowb();
1795}
1796EXPORT_SYMBOL_GPL(sdhci_set_ios);
1797
1798static int sdhci_get_cd(struct mmc_host *mmc)
1799{
1800 struct sdhci_host *host = mmc_priv(mmc);
1801 int gpio_cd = mmc_gpio_get_cd(mmc);
1802
1803 if (host->flags & SDHCI_DEVICE_DEAD)
1804 return 0;
1805
1806 /* If nonremovable, assume that the card is always present. */
1807 if (!mmc_card_is_removable(host->mmc))
1808 return 1;
1809
1810 /*
1811 * Try slot gpio detect, if defined it take precedence
1812 * over build in controller functionality
1813 */
1814 if (gpio_cd >= 0)
1815 return !!gpio_cd;
1816
1817 /* If polling, assume that the card is always present. */
1818 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1819 return 1;
1820
1821 /* Host native card detect */
1822 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1823}
1824
1825static int sdhci_check_ro(struct sdhci_host *host)
1826{
1827 unsigned long flags;
1828 int is_readonly;
1829
1830 spin_lock_irqsave(&host->lock, flags);
1831
1832 if (host->flags & SDHCI_DEVICE_DEAD)
1833 is_readonly = 0;
1834 else if (host->ops->get_ro)
1835 is_readonly = host->ops->get_ro(host);
1836 else
1837 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1838 & SDHCI_WRITE_PROTECT);
1839
1840 spin_unlock_irqrestore(&host->lock, flags);
1841
1842 /* This quirk needs to be replaced by a callback-function later */
1843 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1844 !is_readonly : is_readonly;
1845}
1846
1847#define SAMPLE_COUNT 5
1848
1849static int sdhci_get_ro(struct mmc_host *mmc)
1850{
1851 struct sdhci_host *host = mmc_priv(mmc);
1852 int i, ro_count;
1853
1854 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1855 return sdhci_check_ro(host);
1856
1857 ro_count = 0;
1858 for (i = 0; i < SAMPLE_COUNT; i++) {
1859 if (sdhci_check_ro(host)) {
1860 if (++ro_count > SAMPLE_COUNT / 2)
1861 return 1;
1862 }
1863 msleep(30);
1864 }
1865 return 0;
1866}
1867
1868static void sdhci_hw_reset(struct mmc_host *mmc)
1869{
1870 struct sdhci_host *host = mmc_priv(mmc);
1871
1872 if (host->ops && host->ops->hw_reset)
1873 host->ops->hw_reset(host);
1874}
1875
1876static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1877{
1878 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1879 if (enable)
1880 host->ier |= SDHCI_INT_CARD_INT;
1881 else
1882 host->ier &= ~SDHCI_INT_CARD_INT;
1883
1884 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1885 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1886 mmiowb();
1887 }
1888}
1889
1890void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1891{
1892 struct sdhci_host *host = mmc_priv(mmc);
1893 unsigned long flags;
1894
1895 if (enable)
1896 pm_runtime_get_noresume(host->mmc->parent);
1897
1898 spin_lock_irqsave(&host->lock, flags);
1899 if (enable)
1900 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1901 else
1902 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1903
1904 sdhci_enable_sdio_irq_nolock(host, enable);
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 if (!enable)
1908 pm_runtime_put_noidle(host->mmc->parent);
1909}
1910EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1911
1912int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1913 struct mmc_ios *ios)
1914{
1915 struct sdhci_host *host = mmc_priv(mmc);
1916 u16 ctrl;
1917 int ret;
1918
1919 /*
1920 * Signal Voltage Switching is only applicable for Host Controllers
1921 * v3.00 and above.
1922 */
1923 if (host->version < SDHCI_SPEC_300)
1924 return 0;
1925
1926 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927
1928 switch (ios->signal_voltage) {
1929 case MMC_SIGNAL_VOLTAGE_330:
1930 if (!(host->flags & SDHCI_SIGNALING_330))
1931 return -EINVAL;
1932 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1933 ctrl &= ~SDHCI_CTRL_VDD_180;
1934 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1935
1936 if (!IS_ERR(mmc->supply.vqmmc)) {
1937 ret = mmc_regulator_set_vqmmc(mmc, ios);
1938 if (ret) {
1939 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1940 mmc_hostname(mmc));
1941 return -EIO;
1942 }
1943 }
1944 /* Wait for 5ms */
1945 usleep_range(5000, 5500);
1946
1947 /* 3.3V regulator output should be stable within 5 ms */
1948 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1949 if (!(ctrl & SDHCI_CTRL_VDD_180))
1950 return 0;
1951
1952 pr_warn("%s: 3.3V regulator output did not became stable\n",
1953 mmc_hostname(mmc));
1954
1955 return -EAGAIN;
1956 case MMC_SIGNAL_VOLTAGE_180:
1957 if (!(host->flags & SDHCI_SIGNALING_180))
1958 return -EINVAL;
1959 if (!IS_ERR(mmc->supply.vqmmc)) {
1960 ret = mmc_regulator_set_vqmmc(mmc, ios);
1961 if (ret) {
1962 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1963 mmc_hostname(mmc));
1964 return -EIO;
1965 }
1966 }
1967
1968 /*
1969 * Enable 1.8V Signal Enable in the Host Control2
1970 * register
1971 */
1972 ctrl |= SDHCI_CTRL_VDD_180;
1973 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1974
1975 /* Some controller need to do more when switching */
1976 if (host->ops->voltage_switch)
1977 host->ops->voltage_switch(host);
1978
1979 /* 1.8V regulator output should be stable within 5 ms */
1980 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1981 if (ctrl & SDHCI_CTRL_VDD_180)
1982 return 0;
1983
1984 pr_warn("%s: 1.8V regulator output did not became stable\n",
1985 mmc_hostname(mmc));
1986
1987 return -EAGAIN;
1988 case MMC_SIGNAL_VOLTAGE_120:
1989 if (!(host->flags & SDHCI_SIGNALING_120))
1990 return -EINVAL;
1991 if (!IS_ERR(mmc->supply.vqmmc)) {
1992 ret = mmc_regulator_set_vqmmc(mmc, ios);
1993 if (ret) {
1994 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1995 mmc_hostname(mmc));
1996 return -EIO;
1997 }
1998 }
1999 return 0;
2000 default:
2001 /* No signal voltage switch required */
2002 return 0;
2003 }
2004}
2005EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2006
2007static int sdhci_card_busy(struct mmc_host *mmc)
2008{
2009 struct sdhci_host *host = mmc_priv(mmc);
2010 u32 present_state;
2011
2012 /* Check whether DAT[0] is 0 */
2013 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2014
2015 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2016}
2017
2018static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2019{
2020 struct sdhci_host *host = mmc_priv(mmc);
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&host->lock, flags);
2024 host->flags |= SDHCI_HS400_TUNING;
2025 spin_unlock_irqrestore(&host->lock, flags);
2026
2027 return 0;
2028}
2029
2030static void sdhci_start_tuning(struct sdhci_host *host)
2031{
2032 u16 ctrl;
2033
2034 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2036 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2037 ctrl |= SDHCI_CTRL_TUNED_CLK;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039
2040 /*
2041 * As per the Host Controller spec v3.00, tuning command
2042 * generates Buffer Read Ready interrupt, so enable that.
2043 *
2044 * Note: The spec clearly says that when tuning sequence
2045 * is being performed, the controller does not generate
2046 * interrupts other than Buffer Read Ready interrupt. But
2047 * to make sure we don't hit a controller bug, we _only_
2048 * enable Buffer Read Ready interrupt here.
2049 */
2050 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2051 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2052}
2053
2054static void sdhci_end_tuning(struct sdhci_host *host)
2055{
2056 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2057 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2058}
2059
2060static void sdhci_reset_tuning(struct sdhci_host *host)
2061{
2062 u16 ctrl;
2063
2064 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068}
2069
2070static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2071{
2072 sdhci_reset_tuning(host);
2073
2074 sdhci_do_reset(host, SDHCI_RESET_CMD);
2075 sdhci_do_reset(host, SDHCI_RESET_DATA);
2076
2077 sdhci_end_tuning(host);
2078
2079 mmc_abort_tuning(host->mmc, opcode);
2080}
2081
2082/*
2083 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2084 * tuning command does not have a data payload (or rather the hardware does it
2085 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2086 * interrupt setup is different to other commands and there is no timeout
2087 * interrupt so special handling is needed.
2088 */
2089static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2090{
2091 struct mmc_host *mmc = host->mmc;
2092 struct mmc_command cmd = {};
2093 struct mmc_request mrq = {};
2094 unsigned long flags;
2095 u32 b = host->sdma_boundary;
2096
2097 spin_lock_irqsave(&host->lock, flags);
2098
2099 cmd.opcode = opcode;
2100 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2101 cmd.mrq = &mrq;
2102
2103 mrq.cmd = &cmd;
2104 /*
2105 * In response to CMD19, the card sends 64 bytes of tuning
2106 * block to the Host Controller. So we set the block size
2107 * to 64 here.
2108 */
2109 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2110 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2111 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2112 else
2113 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2114
2115 /*
2116 * The tuning block is sent by the card to the host controller.
2117 * So we set the TRNS_READ bit in the Transfer Mode register.
2118 * This also takes care of setting DMA Enable and Multi Block
2119 * Select in the same register to 0.
2120 */
2121 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2122
2123 sdhci_send_command(host, &cmd);
2124
2125 host->cmd = NULL;
2126
2127 sdhci_del_timer(host, &mrq);
2128
2129 host->tuning_done = 0;
2130
2131 mmiowb();
2132 spin_unlock_irqrestore(&host->lock, flags);
2133
2134 /* Wait for Buffer Read Ready interrupt */
2135 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2136 msecs_to_jiffies(50));
2137
2138}
2139
2140static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2141{
2142 int i;
2143
2144 /*
2145 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2146 * of loops reaches 40 times.
2147 */
2148 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2149 u16 ctrl;
2150
2151 sdhci_send_tuning(host, opcode);
2152
2153 if (!host->tuning_done) {
2154 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2155 mmc_hostname(host->mmc));
2156 sdhci_abort_tuning(host, opcode);
2157 return;
2158 }
2159
2160 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2161 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2162 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2163 return; /* Success! */
2164 break;
2165 }
2166
2167 /* Spec does not require a delay between tuning cycles */
2168 if (host->tuning_delay > 0)
2169 mdelay(host->tuning_delay);
2170 }
2171
2172 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2173 mmc_hostname(host->mmc));
2174 sdhci_reset_tuning(host);
2175}
2176
2177int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2178{
2179 struct sdhci_host *host = mmc_priv(mmc);
2180 int err = 0;
2181 unsigned int tuning_count = 0;
2182 bool hs400_tuning;
2183
2184 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2185
2186 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2187 tuning_count = host->tuning_count;
2188
2189 /*
2190 * The Host Controller needs tuning in case of SDR104 and DDR50
2191 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2192 * the Capabilities register.
2193 * If the Host Controller supports the HS200 mode then the
2194 * tuning function has to be executed.
2195 */
2196 switch (host->timing) {
2197 /* HS400 tuning is done in HS200 mode */
2198 case MMC_TIMING_MMC_HS400:
2199 err = -EINVAL;
2200 goto out;
2201
2202 case MMC_TIMING_MMC_HS200:
2203 /*
2204 * Periodic re-tuning for HS400 is not expected to be needed, so
2205 * disable it here.
2206 */
2207 if (hs400_tuning)
2208 tuning_count = 0;
2209 break;
2210
2211 case MMC_TIMING_UHS_SDR104:
2212 case MMC_TIMING_UHS_DDR50:
2213 break;
2214
2215 case MMC_TIMING_UHS_SDR50:
2216 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2217 break;
2218 /* FALLTHROUGH */
2219
2220 default:
2221 goto out;
2222 }
2223
2224 if (host->ops->platform_execute_tuning) {
2225 err = host->ops->platform_execute_tuning(host, opcode);
2226 goto out;
2227 }
2228
2229 host->mmc->retune_period = tuning_count;
2230
2231 if (host->tuning_delay < 0)
2232 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2233
2234 sdhci_start_tuning(host);
2235
2236 __sdhci_execute_tuning(host, opcode);
2237
2238 sdhci_end_tuning(host);
2239out:
2240 host->flags &= ~SDHCI_HS400_TUNING;
2241
2242 return err;
2243}
2244EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2245
2246static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2247{
2248 /* Host Controller v3.00 defines preset value registers */
2249 if (host->version < SDHCI_SPEC_300)
2250 return;
2251
2252 /*
2253 * We only enable or disable Preset Value if they are not already
2254 * enabled or disabled respectively. Otherwise, we bail out.
2255 */
2256 if (host->preset_enabled != enable) {
2257 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2258
2259 if (enable)
2260 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2261 else
2262 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2263
2264 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2265
2266 if (enable)
2267 host->flags |= SDHCI_PV_ENABLED;
2268 else
2269 host->flags &= ~SDHCI_PV_ENABLED;
2270
2271 host->preset_enabled = enable;
2272 }
2273}
2274
2275static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2276 int err)
2277{
2278 struct sdhci_host *host = mmc_priv(mmc);
2279 struct mmc_data *data = mrq->data;
2280
2281 if (data->host_cookie != COOKIE_UNMAPPED)
2282 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2283 mmc_get_dma_dir(data));
2284
2285 data->host_cookie = COOKIE_UNMAPPED;
2286}
2287
2288static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2289{
2290 struct sdhci_host *host = mmc_priv(mmc);
2291
2292 mrq->data->host_cookie = COOKIE_UNMAPPED;
2293
2294 /*
2295 * No pre-mapping in the pre hook if we're using the bounce buffer,
2296 * for that we would need two bounce buffers since one buffer is
2297 * in flight when this is getting called.
2298 */
2299 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2300 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2301}
2302
2303static inline bool sdhci_has_requests(struct sdhci_host *host)
2304{
2305 return host->cmd || host->data_cmd;
2306}
2307
2308static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2309{
2310 if (host->data_cmd) {
2311 host->data_cmd->error = err;
2312 sdhci_finish_mrq(host, host->data_cmd->mrq);
2313 }
2314
2315 if (host->cmd) {
2316 host->cmd->error = err;
2317 sdhci_finish_mrq(host, host->cmd->mrq);
2318 }
2319}
2320
2321static void sdhci_card_event(struct mmc_host *mmc)
2322{
2323 struct sdhci_host *host = mmc_priv(mmc);
2324 unsigned long flags;
2325 int present;
2326
2327 /* First check if client has provided their own card event */
2328 if (host->ops->card_event)
2329 host->ops->card_event(host);
2330
2331 present = mmc->ops->get_cd(mmc);
2332
2333 spin_lock_irqsave(&host->lock, flags);
2334
2335 /* Check sdhci_has_requests() first in case we are runtime suspended */
2336 if (sdhci_has_requests(host) && !present) {
2337 pr_err("%s: Card removed during transfer!\n",
2338 mmc_hostname(host->mmc));
2339 pr_err("%s: Resetting controller.\n",
2340 mmc_hostname(host->mmc));
2341
2342 sdhci_do_reset(host, SDHCI_RESET_CMD);
2343 sdhci_do_reset(host, SDHCI_RESET_DATA);
2344
2345 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2346 }
2347
2348 spin_unlock_irqrestore(&host->lock, flags);
2349}
2350
2351static const struct mmc_host_ops sdhci_ops = {
2352 .request = sdhci_request,
2353 .post_req = sdhci_post_req,
2354 .pre_req = sdhci_pre_req,
2355 .set_ios = sdhci_set_ios,
2356 .get_cd = sdhci_get_cd,
2357 .get_ro = sdhci_get_ro,
2358 .hw_reset = sdhci_hw_reset,
2359 .enable_sdio_irq = sdhci_enable_sdio_irq,
2360 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2361 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2362 .execute_tuning = sdhci_execute_tuning,
2363 .card_event = sdhci_card_event,
2364 .card_busy = sdhci_card_busy,
2365};
2366
2367/*****************************************************************************\
2368 * *
2369 * Tasklets *
2370 * *
2371\*****************************************************************************/
2372
2373static bool sdhci_request_done(struct sdhci_host *host)
2374{
2375 unsigned long flags;
2376 struct mmc_request *mrq;
2377 int i;
2378
2379 spin_lock_irqsave(&host->lock, flags);
2380
2381 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2382 mrq = host->mrqs_done[i];
2383 if (mrq)
2384 break;
2385 }
2386
2387 if (!mrq) {
2388 spin_unlock_irqrestore(&host->lock, flags);
2389 return true;
2390 }
2391
2392 sdhci_del_timer(host, mrq);
2393
2394 /*
2395 * Always unmap the data buffers if they were mapped by
2396 * sdhci_prepare_data() whenever we finish with a request.
2397 * This avoids leaking DMA mappings on error.
2398 */
2399 if (host->flags & SDHCI_REQ_USE_DMA) {
2400 struct mmc_data *data = mrq->data;
2401
2402 if (data && data->host_cookie == COOKIE_MAPPED) {
2403 if (host->bounce_buffer) {
2404 /*
2405 * On reads, copy the bounced data into the
2406 * sglist
2407 */
2408 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2409 unsigned int length = data->bytes_xfered;
2410
2411 if (length > host->bounce_buffer_size) {
2412 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2413 mmc_hostname(host->mmc),
2414 host->bounce_buffer_size,
2415 data->bytes_xfered);
2416 /* Cap it down and continue */
2417 length = host->bounce_buffer_size;
2418 }
2419 dma_sync_single_for_cpu(
2420 host->mmc->parent,
2421 host->bounce_addr,
2422 host->bounce_buffer_size,
2423 DMA_FROM_DEVICE);
2424 sg_copy_from_buffer(data->sg,
2425 data->sg_len,
2426 host->bounce_buffer,
2427 length);
2428 } else {
2429 /* No copying, just switch ownership */
2430 dma_sync_single_for_cpu(
2431 host->mmc->parent,
2432 host->bounce_addr,
2433 host->bounce_buffer_size,
2434 mmc_get_dma_dir(data));
2435 }
2436 } else {
2437 /* Unmap the raw data */
2438 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2439 data->sg_len,
2440 mmc_get_dma_dir(data));
2441 }
2442 data->host_cookie = COOKIE_UNMAPPED;
2443 }
2444 }
2445
2446 /*
2447 * The controller needs a reset of internal state machines
2448 * upon error conditions.
2449 */
2450 if (sdhci_needs_reset(host, mrq)) {
2451 /*
2452 * Do not finish until command and data lines are available for
2453 * reset. Note there can only be one other mrq, so it cannot
2454 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2455 * would both be null.
2456 */
2457 if (host->cmd || host->data_cmd) {
2458 spin_unlock_irqrestore(&host->lock, flags);
2459 return true;
2460 }
2461
2462 /* Some controllers need this kick or reset won't work here */
2463 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2464 /* This is to force an update */
2465 host->ops->set_clock(host, host->clock);
2466
2467 /* Spec says we should do both at the same time, but Ricoh
2468 controllers do not like that. */
2469 sdhci_do_reset(host, SDHCI_RESET_CMD);
2470 sdhci_do_reset(host, SDHCI_RESET_DATA);
2471
2472 host->pending_reset = false;
2473 }
2474
2475 if (!sdhci_has_requests(host))
2476 sdhci_led_deactivate(host);
2477
2478 host->mrqs_done[i] = NULL;
2479
2480 mmiowb();
2481 spin_unlock_irqrestore(&host->lock, flags);
2482
2483 mmc_request_done(host->mmc, mrq);
2484
2485 return false;
2486}
2487
2488static void sdhci_tasklet_finish(unsigned long param)
2489{
2490 struct sdhci_host *host = (struct sdhci_host *)param;
2491
2492 while (!sdhci_request_done(host))
2493 ;
2494}
2495
2496static void sdhci_timeout_timer(struct timer_list *t)
2497{
2498 struct sdhci_host *host;
2499 unsigned long flags;
2500
2501 host = from_timer(host, t, timer);
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2506 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2507 mmc_hostname(host->mmc));
2508 sdhci_dumpregs(host);
2509
2510 host->cmd->error = -ETIMEDOUT;
2511 sdhci_finish_mrq(host, host->cmd->mrq);
2512 }
2513
2514 mmiowb();
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518static void sdhci_timeout_data_timer(struct timer_list *t)
2519{
2520 struct sdhci_host *host;
2521 unsigned long flags;
2522
2523 host = from_timer(host, t, data_timer);
2524
2525 spin_lock_irqsave(&host->lock, flags);
2526
2527 if (host->data || host->data_cmd ||
2528 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2529 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2530 mmc_hostname(host->mmc));
2531 sdhci_dumpregs(host);
2532
2533 if (host->data) {
2534 host->data->error = -ETIMEDOUT;
2535 sdhci_finish_data(host);
2536 } else if (host->data_cmd) {
2537 host->data_cmd->error = -ETIMEDOUT;
2538 sdhci_finish_mrq(host, host->data_cmd->mrq);
2539 } else {
2540 host->cmd->error = -ETIMEDOUT;
2541 sdhci_finish_mrq(host, host->cmd->mrq);
2542 }
2543 }
2544
2545 mmiowb();
2546 spin_unlock_irqrestore(&host->lock, flags);
2547}
2548
2549/*****************************************************************************\
2550 * *
2551 * Interrupt handling *
2552 * *
2553\*****************************************************************************/
2554
2555static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2556{
2557 if (!host->cmd) {
2558 /*
2559 * SDHCI recovers from errors by resetting the cmd and data
2560 * circuits. Until that is done, there very well might be more
2561 * interrupts, so ignore them in that case.
2562 */
2563 if (host->pending_reset)
2564 return;
2565 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2566 mmc_hostname(host->mmc), (unsigned)intmask);
2567 sdhci_dumpregs(host);
2568 return;
2569 }
2570
2571 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2572 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2573 if (intmask & SDHCI_INT_TIMEOUT)
2574 host->cmd->error = -ETIMEDOUT;
2575 else
2576 host->cmd->error = -EILSEQ;
2577
2578 /*
2579 * If this command initiates a data phase and a response
2580 * CRC error is signalled, the card can start transferring
2581 * data - the card may have received the command without
2582 * error. We must not terminate the mmc_request early.
2583 *
2584 * If the card did not receive the command or returned an
2585 * error which prevented it sending data, the data phase
2586 * will time out.
2587 */
2588 if (host->cmd->data &&
2589 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2590 SDHCI_INT_CRC) {
2591 host->cmd = NULL;
2592 return;
2593 }
2594
2595 sdhci_finish_mrq(host, host->cmd->mrq);
2596 return;
2597 }
2598
2599 if (intmask & SDHCI_INT_RESPONSE)
2600 sdhci_finish_command(host);
2601}
2602
2603static void sdhci_adma_show_error(struct sdhci_host *host)
2604{
2605 void *desc = host->adma_table;
2606
2607 sdhci_dumpregs(host);
2608
2609 while (true) {
2610 struct sdhci_adma2_64_desc *dma_desc = desc;
2611
2612 if (host->flags & SDHCI_USE_64_BIT_DMA)
2613 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2614 desc, le32_to_cpu(dma_desc->addr_hi),
2615 le32_to_cpu(dma_desc->addr_lo),
2616 le16_to_cpu(dma_desc->len),
2617 le16_to_cpu(dma_desc->cmd));
2618 else
2619 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2620 desc, le32_to_cpu(dma_desc->addr_lo),
2621 le16_to_cpu(dma_desc->len),
2622 le16_to_cpu(dma_desc->cmd));
2623
2624 desc += host->desc_sz;
2625
2626 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2627 break;
2628 }
2629}
2630
2631static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2632{
2633 u32 command;
2634
2635 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2636 if (intmask & SDHCI_INT_DATA_AVAIL) {
2637 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2638 if (command == MMC_SEND_TUNING_BLOCK ||
2639 command == MMC_SEND_TUNING_BLOCK_HS200) {
2640 host->tuning_done = 1;
2641 wake_up(&host->buf_ready_int);
2642 return;
2643 }
2644 }
2645
2646 if (!host->data) {
2647 struct mmc_command *data_cmd = host->data_cmd;
2648
2649 /*
2650 * The "data complete" interrupt is also used to
2651 * indicate that a busy state has ended. See comment
2652 * above in sdhci_cmd_irq().
2653 */
2654 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2655 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2656 host->data_cmd = NULL;
2657 data_cmd->error = -ETIMEDOUT;
2658 sdhci_finish_mrq(host, data_cmd->mrq);
2659 return;
2660 }
2661 if (intmask & SDHCI_INT_DATA_END) {
2662 host->data_cmd = NULL;
2663 /*
2664 * Some cards handle busy-end interrupt
2665 * before the command completed, so make
2666 * sure we do things in the proper order.
2667 */
2668 if (host->cmd == data_cmd)
2669 return;
2670
2671 sdhci_finish_mrq(host, data_cmd->mrq);
2672 return;
2673 }
2674 }
2675
2676 /*
2677 * SDHCI recovers from errors by resetting the cmd and data
2678 * circuits. Until that is done, there very well might be more
2679 * interrupts, so ignore them in that case.
2680 */
2681 if (host->pending_reset)
2682 return;
2683
2684 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2685 mmc_hostname(host->mmc), (unsigned)intmask);
2686 sdhci_dumpregs(host);
2687
2688 return;
2689 }
2690
2691 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2692 host->data->error = -ETIMEDOUT;
2693 else if (intmask & SDHCI_INT_DATA_END_BIT)
2694 host->data->error = -EILSEQ;
2695 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2696 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2697 != MMC_BUS_TEST_R)
2698 host->data->error = -EILSEQ;
2699 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2700 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2701 sdhci_adma_show_error(host);
2702 host->data->error = -EIO;
2703 if (host->ops->adma_workaround)
2704 host->ops->adma_workaround(host, intmask);
2705 }
2706
2707 if (host->data->error)
2708 sdhci_finish_data(host);
2709 else {
2710 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2711 sdhci_transfer_pio(host);
2712
2713 /*
2714 * We currently don't do anything fancy with DMA
2715 * boundaries, but as we can't disable the feature
2716 * we need to at least restart the transfer.
2717 *
2718 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2719 * should return a valid address to continue from, but as
2720 * some controllers are faulty, don't trust them.
2721 */
2722 if (intmask & SDHCI_INT_DMA_END) {
2723 u32 dmastart, dmanow;
2724
2725 dmastart = sdhci_sdma_address(host);
2726 dmanow = dmastart + host->data->bytes_xfered;
2727 /*
2728 * Force update to the next DMA block boundary.
2729 */
2730 dmanow = (dmanow &
2731 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2732 SDHCI_DEFAULT_BOUNDARY_SIZE;
2733 host->data->bytes_xfered = dmanow - dmastart;
2734 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2735 dmastart, host->data->bytes_xfered, dmanow);
2736 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2737 }
2738
2739 if (intmask & SDHCI_INT_DATA_END) {
2740 if (host->cmd == host->data_cmd) {
2741 /*
2742 * Data managed to finish before the
2743 * command completed. Make sure we do
2744 * things in the proper order.
2745 */
2746 host->data_early = 1;
2747 } else {
2748 sdhci_finish_data(host);
2749 }
2750 }
2751 }
2752}
2753
2754static irqreturn_t sdhci_irq(int irq, void *dev_id)
2755{
2756 irqreturn_t result = IRQ_NONE;
2757 struct sdhci_host *host = dev_id;
2758 u32 intmask, mask, unexpected = 0;
2759 int max_loops = 16;
2760
2761 spin_lock(&host->lock);
2762
2763 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2764 spin_unlock(&host->lock);
2765 return IRQ_NONE;
2766 }
2767
2768 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2769 if (!intmask || intmask == 0xffffffff) {
2770 result = IRQ_NONE;
2771 goto out;
2772 }
2773
2774 do {
2775 DBG("IRQ status 0x%08x\n", intmask);
2776
2777 if (host->ops->irq) {
2778 intmask = host->ops->irq(host, intmask);
2779 if (!intmask)
2780 goto cont;
2781 }
2782
2783 /* Clear selected interrupts. */
2784 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2785 SDHCI_INT_BUS_POWER);
2786 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2787
2788 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2789 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2790 SDHCI_CARD_PRESENT;
2791
2792 /*
2793 * There is a observation on i.mx esdhc. INSERT
2794 * bit will be immediately set again when it gets
2795 * cleared, if a card is inserted. We have to mask
2796 * the irq to prevent interrupt storm which will
2797 * freeze the system. And the REMOVE gets the
2798 * same situation.
2799 *
2800 * More testing are needed here to ensure it works
2801 * for other platforms though.
2802 */
2803 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2804 SDHCI_INT_CARD_REMOVE);
2805 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2806 SDHCI_INT_CARD_INSERT;
2807 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2808 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2809
2810 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2811 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2812
2813 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2814 SDHCI_INT_CARD_REMOVE);
2815 result = IRQ_WAKE_THREAD;
2816 }
2817
2818 if (intmask & SDHCI_INT_CMD_MASK)
2819 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2820
2821 if (intmask & SDHCI_INT_DATA_MASK)
2822 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2823
2824 if (intmask & SDHCI_INT_BUS_POWER)
2825 pr_err("%s: Card is consuming too much power!\n",
2826 mmc_hostname(host->mmc));
2827
2828 if (intmask & SDHCI_INT_RETUNE)
2829 mmc_retune_needed(host->mmc);
2830
2831 if ((intmask & SDHCI_INT_CARD_INT) &&
2832 (host->ier & SDHCI_INT_CARD_INT)) {
2833 sdhci_enable_sdio_irq_nolock(host, false);
2834 host->thread_isr |= SDHCI_INT_CARD_INT;
2835 result = IRQ_WAKE_THREAD;
2836 }
2837
2838 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2839 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2840 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2841 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2842
2843 if (intmask) {
2844 unexpected |= intmask;
2845 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2846 }
2847cont:
2848 if (result == IRQ_NONE)
2849 result = IRQ_HANDLED;
2850
2851 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2852 } while (intmask && --max_loops);
2853out:
2854 spin_unlock(&host->lock);
2855
2856 if (unexpected) {
2857 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2858 mmc_hostname(host->mmc), unexpected);
2859 sdhci_dumpregs(host);
2860 }
2861
2862 return result;
2863}
2864
2865static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2866{
2867 struct sdhci_host *host = dev_id;
2868 unsigned long flags;
2869 u32 isr;
2870
2871 spin_lock_irqsave(&host->lock, flags);
2872 isr = host->thread_isr;
2873 host->thread_isr = 0;
2874 spin_unlock_irqrestore(&host->lock, flags);
2875
2876 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2877 struct mmc_host *mmc = host->mmc;
2878
2879 mmc->ops->card_event(mmc);
2880 mmc_detect_change(mmc, msecs_to_jiffies(200));
2881 }
2882
2883 if (isr & SDHCI_INT_CARD_INT) {
2884 sdio_run_irqs(host->mmc);
2885
2886 spin_lock_irqsave(&host->lock, flags);
2887 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2888 sdhci_enable_sdio_irq_nolock(host, true);
2889 spin_unlock_irqrestore(&host->lock, flags);
2890 }
2891
2892 return isr ? IRQ_HANDLED : IRQ_NONE;
2893}
2894
2895/*****************************************************************************\
2896 * *
2897 * Suspend/resume *
2898 * *
2899\*****************************************************************************/
2900
2901#ifdef CONFIG_PM
2902
2903static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
2904{
2905 return mmc_card_is_removable(host->mmc) &&
2906 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2907 !mmc_can_gpio_cd(host->mmc);
2908}
2909
2910/*
2911 * To enable wakeup events, the corresponding events have to be enabled in
2912 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2913 * Table' in the SD Host Controller Standard Specification.
2914 * It is useless to restore SDHCI_INT_ENABLE state in
2915 * sdhci_disable_irq_wakeups() since it will be set by
2916 * sdhci_enable_card_detection() or sdhci_init().
2917 */
2918static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
2919{
2920 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
2921 SDHCI_WAKE_ON_INT;
2922 u32 irq_val = 0;
2923 u8 wake_val = 0;
2924 u8 val;
2925
2926 if (sdhci_cd_irq_can_wakeup(host)) {
2927 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
2928 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
2929 }
2930
2931 if (mmc_card_wake_sdio_irq(host->mmc)) {
2932 wake_val |= SDHCI_WAKE_ON_INT;
2933 irq_val |= SDHCI_INT_CARD_INT;
2934 }
2935
2936 if (!irq_val)
2937 return false;
2938
2939 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2940 val &= ~mask;
2941 val |= wake_val;
2942 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2943
2944 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2945
2946 host->irq_wake_enabled = !enable_irq_wake(host->irq);
2947
2948 return host->irq_wake_enabled;
2949}
2950
2951static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2952{
2953 u8 val;
2954 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2955 | SDHCI_WAKE_ON_INT;
2956
2957 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2958 val &= ~mask;
2959 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2960
2961 disable_irq_wake(host->irq);
2962
2963 host->irq_wake_enabled = false;
2964}
2965
2966int sdhci_suspend_host(struct sdhci_host *host)
2967{
2968 sdhci_disable_card_detection(host);
2969
2970 mmc_retune_timer_stop(host->mmc);
2971
2972 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
2973 !sdhci_enable_irq_wakeups(host)) {
2974 host->ier = 0;
2975 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2976 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2977 free_irq(host->irq, host);
2978 }
2979
2980 return 0;
2981}
2982
2983EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2984
2985int sdhci_resume_host(struct sdhci_host *host)
2986{
2987 struct mmc_host *mmc = host->mmc;
2988 int ret = 0;
2989
2990 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2991 if (host->ops->enable_dma)
2992 host->ops->enable_dma(host);
2993 }
2994
2995 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2996 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2997 /* Card keeps power but host controller does not */
2998 sdhci_init(host, 0);
2999 host->pwr = 0;
3000 host->clock = 0;
3001 mmc->ops->set_ios(mmc, &mmc->ios);
3002 } else {
3003 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3004 mmiowb();
3005 }
3006
3007 if (host->irq_wake_enabled) {
3008 sdhci_disable_irq_wakeups(host);
3009 } else {
3010 ret = request_threaded_irq(host->irq, sdhci_irq,
3011 sdhci_thread_irq, IRQF_SHARED,
3012 mmc_hostname(host->mmc), host);
3013 if (ret)
3014 return ret;
3015 }
3016
3017 sdhci_enable_card_detection(host);
3018
3019 return ret;
3020}
3021
3022EXPORT_SYMBOL_GPL(sdhci_resume_host);
3023
3024int sdhci_runtime_suspend_host(struct sdhci_host *host)
3025{
3026 unsigned long flags;
3027
3028 mmc_retune_timer_stop(host->mmc);
3029
3030 spin_lock_irqsave(&host->lock, flags);
3031 host->ier &= SDHCI_INT_CARD_INT;
3032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3034 spin_unlock_irqrestore(&host->lock, flags);
3035
3036 synchronize_hardirq(host->irq);
3037
3038 spin_lock_irqsave(&host->lock, flags);
3039 host->runtime_suspended = true;
3040 spin_unlock_irqrestore(&host->lock, flags);
3041
3042 return 0;
3043}
3044EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3045
3046int sdhci_runtime_resume_host(struct sdhci_host *host)
3047{
3048 struct mmc_host *mmc = host->mmc;
3049 unsigned long flags;
3050 int host_flags = host->flags;
3051
3052 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3053 if (host->ops->enable_dma)
3054 host->ops->enable_dma(host);
3055 }
3056
3057 sdhci_init(host, 0);
3058
3059 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3060 mmc->ios.power_mode != MMC_POWER_OFF) {
3061 /* Force clock and power re-program */
3062 host->pwr = 0;
3063 host->clock = 0;
3064 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3065 mmc->ops->set_ios(mmc, &mmc->ios);
3066
3067 if ((host_flags & SDHCI_PV_ENABLED) &&
3068 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3069 spin_lock_irqsave(&host->lock, flags);
3070 sdhci_enable_preset_value(host, true);
3071 spin_unlock_irqrestore(&host->lock, flags);
3072 }
3073
3074 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3075 mmc->ops->hs400_enhanced_strobe)
3076 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3077 }
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 host->runtime_suspended = false;
3082
3083 /* Enable SDIO IRQ */
3084 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3085 sdhci_enable_sdio_irq_nolock(host, true);
3086
3087 /* Enable Card Detection */
3088 sdhci_enable_card_detection(host);
3089
3090 spin_unlock_irqrestore(&host->lock, flags);
3091
3092 return 0;
3093}
3094EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3095
3096#endif /* CONFIG_PM */
3097
3098/*****************************************************************************\
3099 * *
3100 * Command Queue Engine (CQE) helpers *
3101 * *
3102\*****************************************************************************/
3103
3104void sdhci_cqe_enable(struct mmc_host *mmc)
3105{
3106 struct sdhci_host *host = mmc_priv(mmc);
3107 unsigned long flags;
3108 u8 ctrl;
3109
3110 spin_lock_irqsave(&host->lock, flags);
3111
3112 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3113 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3114 if (host->flags & SDHCI_USE_64_BIT_DMA)
3115 ctrl |= SDHCI_CTRL_ADMA64;
3116 else
3117 ctrl |= SDHCI_CTRL_ADMA32;
3118 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3119
3120 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3121 SDHCI_BLOCK_SIZE);
3122
3123 /* Set maximum timeout */
3124 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3125
3126 host->ier = host->cqe_ier;
3127
3128 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3129 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3130
3131 host->cqe_on = true;
3132
3133 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3134 mmc_hostname(mmc), host->ier,
3135 sdhci_readl(host, SDHCI_INT_STATUS));
3136
3137 mmiowb();
3138 spin_unlock_irqrestore(&host->lock, flags);
3139}
3140EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3141
3142void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3143{
3144 struct sdhci_host *host = mmc_priv(mmc);
3145 unsigned long flags;
3146
3147 spin_lock_irqsave(&host->lock, flags);
3148
3149 sdhci_set_default_irqs(host);
3150
3151 host->cqe_on = false;
3152
3153 if (recovery) {
3154 sdhci_do_reset(host, SDHCI_RESET_CMD);
3155 sdhci_do_reset(host, SDHCI_RESET_DATA);
3156 }
3157
3158 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3159 mmc_hostname(mmc), host->ier,
3160 sdhci_readl(host, SDHCI_INT_STATUS));
3161
3162 mmiowb();
3163 spin_unlock_irqrestore(&host->lock, flags);
3164}
3165EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3166
3167bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3168 int *data_error)
3169{
3170 u32 mask;
3171
3172 if (!host->cqe_on)
3173 return false;
3174
3175 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3176 *cmd_error = -EILSEQ;
3177 else if (intmask & SDHCI_INT_TIMEOUT)
3178 *cmd_error = -ETIMEDOUT;
3179 else
3180 *cmd_error = 0;
3181
3182 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3183 *data_error = -EILSEQ;
3184 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3185 *data_error = -ETIMEDOUT;
3186 else if (intmask & SDHCI_INT_ADMA_ERROR)
3187 *data_error = -EIO;
3188 else
3189 *data_error = 0;
3190
3191 /* Clear selected interrupts. */
3192 mask = intmask & host->cqe_ier;
3193 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3194
3195 if (intmask & SDHCI_INT_BUS_POWER)
3196 pr_err("%s: Card is consuming too much power!\n",
3197 mmc_hostname(host->mmc));
3198
3199 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3200 if (intmask) {
3201 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3202 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3203 mmc_hostname(host->mmc), intmask);
3204 sdhci_dumpregs(host);
3205 }
3206
3207 return true;
3208}
3209EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3210
3211/*****************************************************************************\
3212 * *
3213 * Device allocation/registration *
3214 * *
3215\*****************************************************************************/
3216
3217struct sdhci_host *sdhci_alloc_host(struct device *dev,
3218 size_t priv_size)
3219{
3220 struct mmc_host *mmc;
3221 struct sdhci_host *host;
3222
3223 WARN_ON(dev == NULL);
3224
3225 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3226 if (!mmc)
3227 return ERR_PTR(-ENOMEM);
3228
3229 host = mmc_priv(mmc);
3230 host->mmc = mmc;
3231 host->mmc_host_ops = sdhci_ops;
3232 mmc->ops = &host->mmc_host_ops;
3233
3234 host->flags = SDHCI_SIGNALING_330;
3235
3236 host->cqe_ier = SDHCI_CQE_INT_MASK;
3237 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3238
3239 host->tuning_delay = -1;
3240
3241 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3242
3243 return host;
3244}
3245
3246EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3247
3248static int sdhci_set_dma_mask(struct sdhci_host *host)
3249{
3250 struct mmc_host *mmc = host->mmc;
3251 struct device *dev = mmc_dev(mmc);
3252 int ret = -EINVAL;
3253
3254 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3255 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3256
3257 /* Try 64-bit mask if hardware is capable of it */
3258 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3259 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3260 if (ret) {
3261 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3262 mmc_hostname(mmc));
3263 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3264 }
3265 }
3266
3267 /* 32-bit mask as default & fallback */
3268 if (ret) {
3269 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3270 if (ret)
3271 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3272 mmc_hostname(mmc));
3273 }
3274
3275 return ret;
3276}
3277
3278void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3279{
3280 u16 v;
3281 u64 dt_caps_mask = 0;
3282 u64 dt_caps = 0;
3283
3284 if (host->read_caps)
3285 return;
3286
3287 host->read_caps = true;
3288
3289 if (debug_quirks)
3290 host->quirks = debug_quirks;
3291
3292 if (debug_quirks2)
3293 host->quirks2 = debug_quirks2;
3294
3295 sdhci_do_reset(host, SDHCI_RESET_ALL);
3296
3297 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3298 "sdhci-caps-mask", &dt_caps_mask);
3299 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3300 "sdhci-caps", &dt_caps);
3301
3302 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3303 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3304
3305 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3306 return;
3307
3308 if (caps) {
3309 host->caps = *caps;
3310 } else {
3311 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3312 host->caps &= ~lower_32_bits(dt_caps_mask);
3313 host->caps |= lower_32_bits(dt_caps);
3314 }
3315
3316 if (host->version < SDHCI_SPEC_300)
3317 return;
3318
3319 if (caps1) {
3320 host->caps1 = *caps1;
3321 } else {
3322 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3323 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3324 host->caps1 |= upper_32_bits(dt_caps);
3325 }
3326}
3327EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3328
3329static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3330{
3331 struct mmc_host *mmc = host->mmc;
3332 unsigned int max_blocks;
3333 unsigned int bounce_size;
3334 int ret;
3335
3336 /*
3337 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3338 * has diminishing returns, this is probably because SD/MMC
3339 * cards are usually optimized to handle this size of requests.
3340 */
3341 bounce_size = SZ_64K;
3342 /*
3343 * Adjust downwards to maximum request size if this is less
3344 * than our segment size, else hammer down the maximum
3345 * request size to the maximum buffer size.
3346 */
3347 if (mmc->max_req_size < bounce_size)
3348 bounce_size = mmc->max_req_size;
3349 max_blocks = bounce_size / 512;
3350
3351 /*
3352 * When we just support one segment, we can get significant
3353 * speedups by the help of a bounce buffer to group scattered
3354 * reads/writes together.
3355 */
3356 host->bounce_buffer = devm_kmalloc(mmc->parent,
3357 bounce_size,
3358 GFP_KERNEL);
3359 if (!host->bounce_buffer) {
3360 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3361 mmc_hostname(mmc),
3362 bounce_size);
3363 /*
3364 * Exiting with zero here makes sure we proceed with
3365 * mmc->max_segs == 1.
3366 */
3367 return 0;
3368 }
3369
3370 host->bounce_addr = dma_map_single(mmc->parent,
3371 host->bounce_buffer,
3372 bounce_size,
3373 DMA_BIDIRECTIONAL);
3374 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3375 if (ret)
3376 /* Again fall back to max_segs == 1 */
3377 return 0;
3378 host->bounce_buffer_size = bounce_size;
3379
3380 /* Lie about this since we're bouncing */
3381 mmc->max_segs = max_blocks;
3382 mmc->max_seg_size = bounce_size;
3383 mmc->max_req_size = bounce_size;
3384
3385 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3386 mmc_hostname(mmc), max_blocks, bounce_size);
3387
3388 return 0;
3389}
3390
3391int sdhci_setup_host(struct sdhci_host *host)
3392{
3393 struct mmc_host *mmc;
3394 u32 max_current_caps;
3395 unsigned int ocr_avail;
3396 unsigned int override_timeout_clk;
3397 u32 max_clk;
3398 int ret;
3399
3400 WARN_ON(host == NULL);
3401 if (host == NULL)
3402 return -EINVAL;
3403
3404 mmc = host->mmc;
3405
3406 /*
3407 * If there are external regulators, get them. Note this must be done
3408 * early before resetting the host and reading the capabilities so that
3409 * the host can take the appropriate action if regulators are not
3410 * available.
3411 */
3412 ret = mmc_regulator_get_supply(mmc);
3413 if (ret)
3414 return ret;
3415
3416 DBG("Version: 0x%08x | Present: 0x%08x\n",
3417 sdhci_readw(host, SDHCI_HOST_VERSION),
3418 sdhci_readl(host, SDHCI_PRESENT_STATE));
3419 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3420 sdhci_readl(host, SDHCI_CAPABILITIES),
3421 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3422
3423 sdhci_read_caps(host);
3424
3425 override_timeout_clk = host->timeout_clk;
3426
3427 if (host->version > SDHCI_SPEC_300) {
3428 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3429 mmc_hostname(mmc), host->version);
3430 }
3431
3432 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3433 host->flags |= SDHCI_USE_SDMA;
3434 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3435 DBG("Controller doesn't have SDMA capability\n");
3436 else
3437 host->flags |= SDHCI_USE_SDMA;
3438
3439 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3440 (host->flags & SDHCI_USE_SDMA)) {
3441 DBG("Disabling DMA as it is marked broken\n");
3442 host->flags &= ~SDHCI_USE_SDMA;
3443 }
3444
3445 if ((host->version >= SDHCI_SPEC_200) &&
3446 (host->caps & SDHCI_CAN_DO_ADMA2))
3447 host->flags |= SDHCI_USE_ADMA;
3448
3449 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3450 (host->flags & SDHCI_USE_ADMA)) {
3451 DBG("Disabling ADMA as it is marked broken\n");
3452 host->flags &= ~SDHCI_USE_ADMA;
3453 }
3454
3455 /*
3456 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3457 * and *must* do 64-bit DMA. A driver has the opportunity to change
3458 * that during the first call to ->enable_dma(). Similarly
3459 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3460 * implement.
3461 */
3462 if (host->caps & SDHCI_CAN_64BIT)
3463 host->flags |= SDHCI_USE_64_BIT_DMA;
3464
3465 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3466 ret = sdhci_set_dma_mask(host);
3467
3468 if (!ret && host->ops->enable_dma)
3469 ret = host->ops->enable_dma(host);
3470
3471 if (ret) {
3472 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3473 mmc_hostname(mmc));
3474 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3475
3476 ret = 0;
3477 }
3478 }
3479
3480 /* SDMA does not support 64-bit DMA */
3481 if (host->flags & SDHCI_USE_64_BIT_DMA)
3482 host->flags &= ~SDHCI_USE_SDMA;
3483
3484 if (host->flags & SDHCI_USE_ADMA) {
3485 dma_addr_t dma;
3486 void *buf;
3487
3488 /*
3489 * The DMA descriptor table size is calculated as the maximum
3490 * number of segments times 2, to allow for an alignment
3491 * descriptor for each segment, plus 1 for a nop end descriptor,
3492 * all multipled by the descriptor size.
3493 */
3494 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3495 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3496 SDHCI_ADMA2_64_DESC_SZ;
3497 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3498 } else {
3499 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3500 SDHCI_ADMA2_32_DESC_SZ;
3501 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3502 }
3503
3504 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3505 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3506 host->adma_table_sz, &dma, GFP_KERNEL);
3507 if (!buf) {
3508 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3509 mmc_hostname(mmc));
3510 host->flags &= ~SDHCI_USE_ADMA;
3511 } else if ((dma + host->align_buffer_sz) &
3512 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3513 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3514 mmc_hostname(mmc));
3515 host->flags &= ~SDHCI_USE_ADMA;
3516 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3517 host->adma_table_sz, buf, dma);
3518 } else {
3519 host->align_buffer = buf;
3520 host->align_addr = dma;
3521
3522 host->adma_table = buf + host->align_buffer_sz;
3523 host->adma_addr = dma + host->align_buffer_sz;
3524 }
3525 }
3526
3527 /*
3528 * If we use DMA, then it's up to the caller to set the DMA
3529 * mask, but PIO does not need the hw shim so we set a new
3530 * mask here in that case.
3531 */
3532 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3533 host->dma_mask = DMA_BIT_MASK(64);
3534 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3535 }
3536
3537 if (host->version >= SDHCI_SPEC_300)
3538 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3539 >> SDHCI_CLOCK_BASE_SHIFT;
3540 else
3541 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3542 >> SDHCI_CLOCK_BASE_SHIFT;
3543
3544 host->max_clk *= 1000000;
3545 if (host->max_clk == 0 || host->quirks &
3546 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3547 if (!host->ops->get_max_clock) {
3548 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3549 mmc_hostname(mmc));
3550 ret = -ENODEV;
3551 goto undma;
3552 }
3553 host->max_clk = host->ops->get_max_clock(host);
3554 }
3555
3556 /*
3557 * In case of Host Controller v3.00, find out whether clock
3558 * multiplier is supported.
3559 */
3560 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3561 SDHCI_CLOCK_MUL_SHIFT;
3562
3563 /*
3564 * In case the value in Clock Multiplier is 0, then programmable
3565 * clock mode is not supported, otherwise the actual clock
3566 * multiplier is one more than the value of Clock Multiplier
3567 * in the Capabilities Register.
3568 */
3569 if (host->clk_mul)
3570 host->clk_mul += 1;
3571
3572 /*
3573 * Set host parameters.
3574 */
3575 max_clk = host->max_clk;
3576
3577 if (host->ops->get_min_clock)
3578 mmc->f_min = host->ops->get_min_clock(host);
3579 else if (host->version >= SDHCI_SPEC_300) {
3580 if (host->clk_mul) {
3581 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3582 max_clk = host->max_clk * host->clk_mul;
3583 } else
3584 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3585 } else
3586 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3587
3588 if (!mmc->f_max || mmc->f_max > max_clk)
3589 mmc->f_max = max_clk;
3590
3591 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3592 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3593 SDHCI_TIMEOUT_CLK_SHIFT;
3594
3595 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3596 host->timeout_clk *= 1000;
3597
3598 if (host->timeout_clk == 0) {
3599 if (!host->ops->get_timeout_clock) {
3600 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3601 mmc_hostname(mmc));
3602 ret = -ENODEV;
3603 goto undma;
3604 }
3605
3606 host->timeout_clk =
3607 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3608 1000);
3609 }
3610
3611 if (override_timeout_clk)
3612 host->timeout_clk = override_timeout_clk;
3613
3614 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3615 host->ops->get_max_timeout_count(host) : 1 << 27;
3616 mmc->max_busy_timeout /= host->timeout_clk;
3617 }
3618
3619 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3620 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3621
3622 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3623 host->flags |= SDHCI_AUTO_CMD12;
3624
3625 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3626 if ((host->version >= SDHCI_SPEC_300) &&
3627 ((host->flags & SDHCI_USE_ADMA) ||
3628 !(host->flags & SDHCI_USE_SDMA)) &&
3629 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3630 host->flags |= SDHCI_AUTO_CMD23;
3631 DBG("Auto-CMD23 available\n");
3632 } else {
3633 DBG("Auto-CMD23 unavailable\n");
3634 }
3635
3636 /*
3637 * A controller may support 8-bit width, but the board itself
3638 * might not have the pins brought out. Boards that support
3639 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3640 * their platform code before calling sdhci_add_host(), and we
3641 * won't assume 8-bit width for hosts without that CAP.
3642 */
3643 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3644 mmc->caps |= MMC_CAP_4_BIT_DATA;
3645
3646 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3647 mmc->caps &= ~MMC_CAP_CMD23;
3648
3649 if (host->caps & SDHCI_CAN_DO_HISPD)
3650 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3651
3652 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3653 mmc_card_is_removable(mmc) &&
3654 mmc_gpio_get_cd(host->mmc) < 0)
3655 mmc->caps |= MMC_CAP_NEEDS_POLL;
3656
3657 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3658 if (!IS_ERR(mmc->supply.vqmmc)) {
3659 ret = regulator_enable(mmc->supply.vqmmc);
3660 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3661 1950000))
3662 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3663 SDHCI_SUPPORT_SDR50 |
3664 SDHCI_SUPPORT_DDR50);
3665 if (ret) {
3666 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3667 mmc_hostname(mmc), ret);
3668 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3669 }
3670 }
3671
3672 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3673 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3674 SDHCI_SUPPORT_DDR50);
3675 }
3676
3677 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3678 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3679 SDHCI_SUPPORT_DDR50))
3680 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3681
3682 /* SDR104 supports also implies SDR50 support */
3683 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3684 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3685 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3686 * field can be promoted to support HS200.
3687 */
3688 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3689 mmc->caps2 |= MMC_CAP2_HS200;
3690 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3691 mmc->caps |= MMC_CAP_UHS_SDR50;
3692 }
3693
3694 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3695 (host->caps1 & SDHCI_SUPPORT_HS400))
3696 mmc->caps2 |= MMC_CAP2_HS400;
3697
3698 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3699 (IS_ERR(mmc->supply.vqmmc) ||
3700 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3701 1300000)))
3702 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3703
3704 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3705 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3706 mmc->caps |= MMC_CAP_UHS_DDR50;
3707
3708 /* Does the host need tuning for SDR50? */
3709 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3710 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3711
3712 /* Driver Type(s) (A, C, D) supported by the host */
3713 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3714 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3715 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3716 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3717 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3718 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3719
3720 /* Initial value for re-tuning timer count */
3721 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3722 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3723
3724 /*
3725 * In case Re-tuning Timer is not disabled, the actual value of
3726 * re-tuning timer will be 2 ^ (n - 1).
3727 */
3728 if (host->tuning_count)
3729 host->tuning_count = 1 << (host->tuning_count - 1);
3730
3731 /* Re-tuning mode supported by the Host Controller */
3732 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3733 SDHCI_RETUNING_MODE_SHIFT;
3734
3735 ocr_avail = 0;
3736
3737 /*
3738 * According to SD Host Controller spec v3.00, if the Host System
3739 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3740 * the value is meaningful only if Voltage Support in the Capabilities
3741 * register is set. The actual current value is 4 times the register
3742 * value.
3743 */
3744 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3745 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3746 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3747 if (curr > 0) {
3748
3749 /* convert to SDHCI_MAX_CURRENT format */
3750 curr = curr/1000; /* convert to mA */
3751 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3752
3753 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3754 max_current_caps =
3755 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3756 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3757 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3758 }
3759 }
3760
3761 if (host->caps & SDHCI_CAN_VDD_330) {
3762 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3763
3764 mmc->max_current_330 = ((max_current_caps &
3765 SDHCI_MAX_CURRENT_330_MASK) >>
3766 SDHCI_MAX_CURRENT_330_SHIFT) *
3767 SDHCI_MAX_CURRENT_MULTIPLIER;
3768 }
3769 if (host->caps & SDHCI_CAN_VDD_300) {
3770 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3771
3772 mmc->max_current_300 = ((max_current_caps &
3773 SDHCI_MAX_CURRENT_300_MASK) >>
3774 SDHCI_MAX_CURRENT_300_SHIFT) *
3775 SDHCI_MAX_CURRENT_MULTIPLIER;
3776 }
3777 if (host->caps & SDHCI_CAN_VDD_180) {
3778 ocr_avail |= MMC_VDD_165_195;
3779
3780 mmc->max_current_180 = ((max_current_caps &
3781 SDHCI_MAX_CURRENT_180_MASK) >>
3782 SDHCI_MAX_CURRENT_180_SHIFT) *
3783 SDHCI_MAX_CURRENT_MULTIPLIER;
3784 }
3785
3786 /* If OCR set by host, use it instead. */
3787 if (host->ocr_mask)
3788 ocr_avail = host->ocr_mask;
3789
3790 /* If OCR set by external regulators, give it highest prio. */
3791 if (mmc->ocr_avail)
3792 ocr_avail = mmc->ocr_avail;
3793
3794 mmc->ocr_avail = ocr_avail;
3795 mmc->ocr_avail_sdio = ocr_avail;
3796 if (host->ocr_avail_sdio)
3797 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3798 mmc->ocr_avail_sd = ocr_avail;
3799 if (host->ocr_avail_sd)
3800 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3801 else /* normal SD controllers don't support 1.8V */
3802 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3803 mmc->ocr_avail_mmc = ocr_avail;
3804 if (host->ocr_avail_mmc)
3805 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3806
3807 if (mmc->ocr_avail == 0) {
3808 pr_err("%s: Hardware doesn't report any support voltages.\n",
3809 mmc_hostname(mmc));
3810 ret = -ENODEV;
3811 goto unreg;
3812 }
3813
3814 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3815 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3816 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3817 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3818 host->flags |= SDHCI_SIGNALING_180;
3819
3820 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3821 host->flags |= SDHCI_SIGNALING_120;
3822
3823 spin_lock_init(&host->lock);
3824
3825 /*
3826 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3827 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3828 * is less anyway.
3829 */
3830 mmc->max_req_size = 524288;
3831
3832 /*
3833 * Maximum number of segments. Depends on if the hardware
3834 * can do scatter/gather or not.
3835 */
3836 if (host->flags & SDHCI_USE_ADMA) {
3837 mmc->max_segs = SDHCI_MAX_SEGS;
3838 } else if (host->flags & SDHCI_USE_SDMA) {
3839 mmc->max_segs = 1;
3840 if (swiotlb_max_segment()) {
3841 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3842 IO_TLB_SEGSIZE;
3843 mmc->max_req_size = min(mmc->max_req_size,
3844 max_req_size);
3845 }
3846 } else { /* PIO */
3847 mmc->max_segs = SDHCI_MAX_SEGS;
3848 }
3849
3850 /*
3851 * Maximum segment size. Could be one segment with the maximum number
3852 * of bytes. When doing hardware scatter/gather, each entry cannot
3853 * be larger than 64 KiB though.
3854 */
3855 if (host->flags & SDHCI_USE_ADMA) {
3856 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3857 mmc->max_seg_size = 65535;
3858 else
3859 mmc->max_seg_size = 65536;
3860 } else {
3861 mmc->max_seg_size = mmc->max_req_size;
3862 }
3863
3864 /*
3865 * Maximum block size. This varies from controller to controller and
3866 * is specified in the capabilities register.
3867 */
3868 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3869 mmc->max_blk_size = 2;
3870 } else {
3871 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3872 SDHCI_MAX_BLOCK_SHIFT;
3873 if (mmc->max_blk_size >= 3) {
3874 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3875 mmc_hostname(mmc));
3876 mmc->max_blk_size = 0;
3877 }
3878 }
3879
3880 mmc->max_blk_size = 512 << mmc->max_blk_size;
3881
3882 /*
3883 * Maximum block count.
3884 */
3885 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3886
3887 if (mmc->max_segs == 1) {
3888 /* This may alter mmc->*_blk_* parameters */
3889 ret = sdhci_allocate_bounce_buffer(host);
3890 if (ret)
3891 return ret;
3892 }
3893
3894 return 0;
3895
3896unreg:
3897 if (!IS_ERR(mmc->supply.vqmmc))
3898 regulator_disable(mmc->supply.vqmmc);
3899undma:
3900 if (host->align_buffer)
3901 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3902 host->adma_table_sz, host->align_buffer,
3903 host->align_addr);
3904 host->adma_table = NULL;
3905 host->align_buffer = NULL;
3906
3907 return ret;
3908}
3909EXPORT_SYMBOL_GPL(sdhci_setup_host);
3910
3911void sdhci_cleanup_host(struct sdhci_host *host)
3912{
3913 struct mmc_host *mmc = host->mmc;
3914
3915 if (!IS_ERR(mmc->supply.vqmmc))
3916 regulator_disable(mmc->supply.vqmmc);
3917
3918 if (host->align_buffer)
3919 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3920 host->adma_table_sz, host->align_buffer,
3921 host->align_addr);
3922 host->adma_table = NULL;
3923 host->align_buffer = NULL;
3924}
3925EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3926
3927int __sdhci_add_host(struct sdhci_host *host)
3928{
3929 struct mmc_host *mmc = host->mmc;
3930 int ret;
3931
3932 /*
3933 * Init tasklets.
3934 */
3935 tasklet_init(&host->finish_tasklet,
3936 sdhci_tasklet_finish, (unsigned long)host);
3937
3938 timer_setup(&host->timer, sdhci_timeout_timer, 0);
3939 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
3940
3941 init_waitqueue_head(&host->buf_ready_int);
3942
3943 sdhci_init(host, 0);
3944
3945 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3946 IRQF_SHARED, mmc_hostname(mmc), host);
3947 if (ret) {
3948 pr_err("%s: Failed to request IRQ %d: %d\n",
3949 mmc_hostname(mmc), host->irq, ret);
3950 goto untasklet;
3951 }
3952
3953 ret = sdhci_led_register(host);
3954 if (ret) {
3955 pr_err("%s: Failed to register LED device: %d\n",
3956 mmc_hostname(mmc), ret);
3957 goto unirq;
3958 }
3959
3960 mmiowb();
3961
3962 ret = mmc_add_host(mmc);
3963 if (ret)
3964 goto unled;
3965
3966 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3967 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3968 (host->flags & SDHCI_USE_ADMA) ?
3969 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3970 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3971
3972 sdhci_enable_card_detection(host);
3973
3974 return 0;
3975
3976unled:
3977 sdhci_led_unregister(host);
3978unirq:
3979 sdhci_do_reset(host, SDHCI_RESET_ALL);
3980 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3981 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3982 free_irq(host->irq, host);
3983untasklet:
3984 tasklet_kill(&host->finish_tasklet);
3985
3986 return ret;
3987}
3988EXPORT_SYMBOL_GPL(__sdhci_add_host);
3989
3990int sdhci_add_host(struct sdhci_host *host)
3991{
3992 int ret;
3993
3994 ret = sdhci_setup_host(host);
3995 if (ret)
3996 return ret;
3997
3998 ret = __sdhci_add_host(host);
3999 if (ret)
4000 goto cleanup;
4001
4002 return 0;
4003
4004cleanup:
4005 sdhci_cleanup_host(host);
4006
4007 return ret;
4008}
4009EXPORT_SYMBOL_GPL(sdhci_add_host);
4010
4011void sdhci_remove_host(struct sdhci_host *host, int dead)
4012{
4013 struct mmc_host *mmc = host->mmc;
4014 unsigned long flags;
4015
4016 if (dead) {
4017 spin_lock_irqsave(&host->lock, flags);
4018
4019 host->flags |= SDHCI_DEVICE_DEAD;
4020
4021 if (sdhci_has_requests(host)) {
4022 pr_err("%s: Controller removed during "
4023 " transfer!\n", mmc_hostname(mmc));
4024 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4025 }
4026
4027 spin_unlock_irqrestore(&host->lock, flags);
4028 }
4029
4030 sdhci_disable_card_detection(host);
4031
4032 mmc_remove_host(mmc);
4033
4034 sdhci_led_unregister(host);
4035
4036 if (!dead)
4037 sdhci_do_reset(host, SDHCI_RESET_ALL);
4038
4039 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4040 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4041 free_irq(host->irq, host);
4042
4043 del_timer_sync(&host->timer);
4044 del_timer_sync(&host->data_timer);
4045
4046 tasklet_kill(&host->finish_tasklet);
4047
4048 if (!IS_ERR(mmc->supply.vqmmc))
4049 regulator_disable(mmc->supply.vqmmc);
4050
4051 if (host->align_buffer)
4052 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4053 host->adma_table_sz, host->align_buffer,
4054 host->align_addr);
4055
4056 host->adma_table = NULL;
4057 host->align_buffer = NULL;
4058}
4059
4060EXPORT_SYMBOL_GPL(sdhci_remove_host);
4061
4062void sdhci_free_host(struct sdhci_host *host)
4063{
4064 mmc_free_host(host->mmc);
4065}
4066
4067EXPORT_SYMBOL_GPL(sdhci_free_host);
4068
4069/*****************************************************************************\
4070 * *
4071 * Driver init/exit *
4072 * *
4073\*****************************************************************************/
4074
4075static int __init sdhci_drv_init(void)
4076{
4077 pr_info(DRIVER_NAME
4078 ": Secure Digital Host Controller Interface driver\n");
4079 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4080
4081 return 0;
4082}
4083
4084static void __exit sdhci_drv_exit(void)
4085{
4086}
4087
4088module_init(sdhci_drv_init);
4089module_exit(sdhci_drv_exit);
4090
4091module_param(debug_quirks, uint, 0444);
4092module_param(debug_quirks2, uint, 0444);
4093
4094MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4095MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4096MODULE_LICENSE("GPL");
4097
4098MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4099MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51
52static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
53
54void sdhci_dumpregs(struct sdhci_host *host)
55{
56 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
57
58 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
61 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
79 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
92 sdhci_readl(host, SDHCI_RESPONSE),
93 sdhci_readl(host, SDHCI_RESPONSE + 4));
94 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE + 8),
96 sdhci_readl(host, SDHCI_RESPONSE + 12));
97 SDHCI_DUMP("Host ctl2: 0x%08x\n",
98 sdhci_readw(host, SDHCI_HOST_CONTROL2));
99
100 if (host->flags & SDHCI_USE_ADMA) {
101 if (host->flags & SDHCI_USE_64_BIT_DMA) {
102 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
103 sdhci_readl(host, SDHCI_ADMA_ERROR),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
106 } else {
107 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
108 sdhci_readl(host, SDHCI_ADMA_ERROR),
109 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
110 }
111 }
112
113 if (host->ops->dump_vendor_regs)
114 host->ops->dump_vendor_regs(host);
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127{
128 u16 ctrl2;
129
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return;
133
134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
136}
137
138/*
139 * This can be called before sdhci_add_host() by Vendor's host controller
140 * driver to enable v4 mode if supported.
141 */
142void sdhci_enable_v4_mode(struct sdhci_host *host)
143{
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
146}
147EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
148
149static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
150{
151 return cmd->data || cmd->flags & MMC_RSP_BUSY;
152}
153
154static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
155{
156 u32 present;
157
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
160 return;
161
162 if (enable) {
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
167 SDHCI_INT_CARD_INSERT;
168 } else {
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
170 }
171
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
174}
175
176static void sdhci_enable_card_detection(struct sdhci_host *host)
177{
178 sdhci_set_card_detection(host, true);
179}
180
181static void sdhci_disable_card_detection(struct sdhci_host *host)
182{
183 sdhci_set_card_detection(host, false);
184}
185
186static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187{
188 if (host->bus_on)
189 return;
190 host->bus_on = true;
191 pm_runtime_get_noresume(mmc_dev(host->mmc));
192}
193
194static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
195{
196 if (!host->bus_on)
197 return;
198 host->bus_on = false;
199 pm_runtime_put_noidle(mmc_dev(host->mmc));
200}
201
202void sdhci_reset(struct sdhci_host *host, u8 mask)
203{
204 ktime_t timeout;
205
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
207
208 if (mask & SDHCI_RESET_ALL) {
209 host->clock = 0;
210 /* Reset-all turns off SD Bus Power */
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
213 }
214
215 /* Wait max 100 ms */
216 timeout = ktime_add_ms(ktime_get(), 100);
217
218 /* hw clears the bit when it's done */
219 while (1) {
220 bool timedout = ktime_after(ktime_get(), timeout);
221
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
223 break;
224 if (timedout) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_dumpregs(host);
228 return;
229 }
230 udelay(10);
231 }
232}
233EXPORT_SYMBOL_GPL(sdhci_reset);
234
235static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
236{
237 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
238 struct mmc_host *mmc = host->mmc;
239
240 if (!mmc->ops->get_cd(mmc))
241 return;
242 }
243
244 host->ops->reset(host, mask);
245
246 if (mask & SDHCI_RESET_ALL) {
247 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
248 if (host->ops->enable_dma)
249 host->ops->enable_dma(host);
250 }
251
252 /* Resetting the controller clears many */
253 host->preset_enabled = false;
254 }
255}
256
257static void sdhci_set_default_irqs(struct sdhci_host *host)
258{
259 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
260 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
261 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
262 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
263 SDHCI_INT_RESPONSE;
264
265 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
266 host->tuning_mode == SDHCI_TUNING_MODE_3)
267 host->ier |= SDHCI_INT_RETUNE;
268
269 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
270 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
271}
272
273static void sdhci_config_dma(struct sdhci_host *host)
274{
275 u8 ctrl;
276 u16 ctrl2;
277
278 if (host->version < SDHCI_SPEC_200)
279 return;
280
281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
282
283 /*
284 * Always adjust the DMA selection as some controllers
285 * (e.g. JMicron) can't do PIO properly when the selection
286 * is ADMA.
287 */
288 ctrl &= ~SDHCI_CTRL_DMA_MASK;
289 if (!(host->flags & SDHCI_REQ_USE_DMA))
290 goto out;
291
292 /* Note if DMA Select is zero then SDMA is selected */
293 if (host->flags & SDHCI_USE_ADMA)
294 ctrl |= SDHCI_CTRL_ADMA32;
295
296 if (host->flags & SDHCI_USE_64_BIT_DMA) {
297 /*
298 * If v4 mode, all supported DMA can be 64-bit addressing if
299 * controller supports 64-bit system address, otherwise only
300 * ADMA can support 64-bit addressing.
301 */
302 if (host->v4_mode) {
303 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
304 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
305 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
306 } else if (host->flags & SDHCI_USE_ADMA) {
307 /*
308 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
309 * set SDHCI_CTRL_ADMA64.
310 */
311 ctrl |= SDHCI_CTRL_ADMA64;
312 }
313 }
314
315out:
316 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
317}
318
319static void sdhci_init(struct sdhci_host *host, int soft)
320{
321 struct mmc_host *mmc = host->mmc;
322 unsigned long flags;
323
324 if (soft)
325 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
326 else
327 sdhci_do_reset(host, SDHCI_RESET_ALL);
328
329 if (host->v4_mode)
330 sdhci_do_enable_v4_mode(host);
331
332 spin_lock_irqsave(&host->lock, flags);
333 sdhci_set_default_irqs(host);
334 spin_unlock_irqrestore(&host->lock, flags);
335
336 host->cqe_on = false;
337
338 if (soft) {
339 /* force clock reconfiguration */
340 host->clock = 0;
341 mmc->ops->set_ios(mmc, &mmc->ios);
342 }
343}
344
345static void sdhci_reinit(struct sdhci_host *host)
346{
347 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
348
349 sdhci_init(host, 0);
350 sdhci_enable_card_detection(host);
351
352 /*
353 * A change to the card detect bits indicates a change in present state,
354 * refer sdhci_set_card_detection(). A card detect interrupt might have
355 * been missed while the host controller was being reset, so trigger a
356 * rescan to check.
357 */
358 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
359 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
360}
361
362static void __sdhci_led_activate(struct sdhci_host *host)
363{
364 u8 ctrl;
365
366 if (host->quirks & SDHCI_QUIRK_NO_LED)
367 return;
368
369 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
370 ctrl |= SDHCI_CTRL_LED;
371 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
372}
373
374static void __sdhci_led_deactivate(struct sdhci_host *host)
375{
376 u8 ctrl;
377
378 if (host->quirks & SDHCI_QUIRK_NO_LED)
379 return;
380
381 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
382 ctrl &= ~SDHCI_CTRL_LED;
383 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
384}
385
386#if IS_REACHABLE(CONFIG_LEDS_CLASS)
387static void sdhci_led_control(struct led_classdev *led,
388 enum led_brightness brightness)
389{
390 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
391 unsigned long flags;
392
393 spin_lock_irqsave(&host->lock, flags);
394
395 if (host->runtime_suspended)
396 goto out;
397
398 if (brightness == LED_OFF)
399 __sdhci_led_deactivate(host);
400 else
401 __sdhci_led_activate(host);
402out:
403 spin_unlock_irqrestore(&host->lock, flags);
404}
405
406static int sdhci_led_register(struct sdhci_host *host)
407{
408 struct mmc_host *mmc = host->mmc;
409
410 if (host->quirks & SDHCI_QUIRK_NO_LED)
411 return 0;
412
413 snprintf(host->led_name, sizeof(host->led_name),
414 "%s::", mmc_hostname(mmc));
415
416 host->led.name = host->led_name;
417 host->led.brightness = LED_OFF;
418 host->led.default_trigger = mmc_hostname(mmc);
419 host->led.brightness_set = sdhci_led_control;
420
421 return led_classdev_register(mmc_dev(mmc), &host->led);
422}
423
424static void sdhci_led_unregister(struct sdhci_host *host)
425{
426 if (host->quirks & SDHCI_QUIRK_NO_LED)
427 return;
428
429 led_classdev_unregister(&host->led);
430}
431
432static inline void sdhci_led_activate(struct sdhci_host *host)
433{
434}
435
436static inline void sdhci_led_deactivate(struct sdhci_host *host)
437{
438}
439
440#else
441
442static inline int sdhci_led_register(struct sdhci_host *host)
443{
444 return 0;
445}
446
447static inline void sdhci_led_unregister(struct sdhci_host *host)
448{
449}
450
451static inline void sdhci_led_activate(struct sdhci_host *host)
452{
453 __sdhci_led_activate(host);
454}
455
456static inline void sdhci_led_deactivate(struct sdhci_host *host)
457{
458 __sdhci_led_deactivate(host);
459}
460
461#endif
462
463static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
464 unsigned long timeout)
465{
466 if (sdhci_data_line_cmd(mrq->cmd))
467 mod_timer(&host->data_timer, timeout);
468 else
469 mod_timer(&host->timer, timeout);
470}
471
472static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
473{
474 if (sdhci_data_line_cmd(mrq->cmd))
475 del_timer(&host->data_timer);
476 else
477 del_timer(&host->timer);
478}
479
480static inline bool sdhci_has_requests(struct sdhci_host *host)
481{
482 return host->cmd || host->data_cmd;
483}
484
485/*****************************************************************************\
486 * *
487 * Core functions *
488 * *
489\*****************************************************************************/
490
491static void sdhci_read_block_pio(struct sdhci_host *host)
492{
493 unsigned long flags;
494 size_t blksize, len, chunk;
495 u32 scratch;
496 u8 *buf;
497
498 DBG("PIO reading\n");
499
500 blksize = host->data->blksz;
501 chunk = 0;
502
503 local_irq_save(flags);
504
505 while (blksize) {
506 BUG_ON(!sg_miter_next(&host->sg_miter));
507
508 len = min(host->sg_miter.length, blksize);
509
510 blksize -= len;
511 host->sg_miter.consumed = len;
512
513 buf = host->sg_miter.addr;
514
515 while (len) {
516 if (chunk == 0) {
517 scratch = sdhci_readl(host, SDHCI_BUFFER);
518 chunk = 4;
519 }
520
521 *buf = scratch & 0xFF;
522
523 buf++;
524 scratch >>= 8;
525 chunk--;
526 len--;
527 }
528 }
529
530 sg_miter_stop(&host->sg_miter);
531
532 local_irq_restore(flags);
533}
534
535static void sdhci_write_block_pio(struct sdhci_host *host)
536{
537 unsigned long flags;
538 size_t blksize, len, chunk;
539 u32 scratch;
540 u8 *buf;
541
542 DBG("PIO writing\n");
543
544 blksize = host->data->blksz;
545 chunk = 0;
546 scratch = 0;
547
548 local_irq_save(flags);
549
550 while (blksize) {
551 BUG_ON(!sg_miter_next(&host->sg_miter));
552
553 len = min(host->sg_miter.length, blksize);
554
555 blksize -= len;
556 host->sg_miter.consumed = len;
557
558 buf = host->sg_miter.addr;
559
560 while (len) {
561 scratch |= (u32)*buf << (chunk * 8);
562
563 buf++;
564 chunk++;
565 len--;
566
567 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
568 sdhci_writel(host, scratch, SDHCI_BUFFER);
569 chunk = 0;
570 scratch = 0;
571 }
572 }
573 }
574
575 sg_miter_stop(&host->sg_miter);
576
577 local_irq_restore(flags);
578}
579
580static void sdhci_transfer_pio(struct sdhci_host *host)
581{
582 u32 mask;
583
584 if (host->blocks == 0)
585 return;
586
587 if (host->data->flags & MMC_DATA_READ)
588 mask = SDHCI_DATA_AVAILABLE;
589 else
590 mask = SDHCI_SPACE_AVAILABLE;
591
592 /*
593 * Some controllers (JMicron JMB38x) mess up the buffer bits
594 * for transfers < 4 bytes. As long as it is just one block,
595 * we can ignore the bits.
596 */
597 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
598 (host->data->blocks == 1))
599 mask = ~0;
600
601 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
602 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
603 udelay(100);
604
605 if (host->data->flags & MMC_DATA_READ)
606 sdhci_read_block_pio(host);
607 else
608 sdhci_write_block_pio(host);
609
610 host->blocks--;
611 if (host->blocks == 0)
612 break;
613 }
614
615 DBG("PIO transfer complete.\n");
616}
617
618static int sdhci_pre_dma_transfer(struct sdhci_host *host,
619 struct mmc_data *data, int cookie)
620{
621 int sg_count;
622
623 /*
624 * If the data buffers are already mapped, return the previous
625 * dma_map_sg() result.
626 */
627 if (data->host_cookie == COOKIE_PRE_MAPPED)
628 return data->sg_count;
629
630 /* Bounce write requests to the bounce buffer */
631 if (host->bounce_buffer) {
632 unsigned int length = data->blksz * data->blocks;
633
634 if (length > host->bounce_buffer_size) {
635 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
636 mmc_hostname(host->mmc), length,
637 host->bounce_buffer_size);
638 return -EIO;
639 }
640 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
641 /* Copy the data to the bounce buffer */
642 if (host->ops->copy_to_bounce_buffer) {
643 host->ops->copy_to_bounce_buffer(host,
644 data, length);
645 } else {
646 sg_copy_to_buffer(data->sg, data->sg_len,
647 host->bounce_buffer, length);
648 }
649 }
650 /* Switch ownership to the DMA */
651 dma_sync_single_for_device(mmc_dev(host->mmc),
652 host->bounce_addr,
653 host->bounce_buffer_size,
654 mmc_get_dma_dir(data));
655 /* Just a dummy value */
656 sg_count = 1;
657 } else {
658 /* Just access the data directly from memory */
659 sg_count = dma_map_sg(mmc_dev(host->mmc),
660 data->sg, data->sg_len,
661 mmc_get_dma_dir(data));
662 }
663
664 if (sg_count == 0)
665 return -ENOSPC;
666
667 data->sg_count = sg_count;
668 data->host_cookie = cookie;
669
670 return sg_count;
671}
672
673static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
674{
675 local_irq_save(*flags);
676 return kmap_atomic(sg_page(sg)) + sg->offset;
677}
678
679static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
680{
681 kunmap_atomic(buffer);
682 local_irq_restore(*flags);
683}
684
685void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
686 dma_addr_t addr, int len, unsigned int cmd)
687{
688 struct sdhci_adma2_64_desc *dma_desc = *desc;
689
690 /* 32-bit and 64-bit descriptors have these members in same position */
691 dma_desc->cmd = cpu_to_le16(cmd);
692 dma_desc->len = cpu_to_le16(len);
693 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
694
695 if (host->flags & SDHCI_USE_64_BIT_DMA)
696 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
697
698 *desc += host->desc_sz;
699}
700EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
701
702static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
703 void **desc, dma_addr_t addr,
704 int len, unsigned int cmd)
705{
706 if (host->ops->adma_write_desc)
707 host->ops->adma_write_desc(host, desc, addr, len, cmd);
708 else
709 sdhci_adma_write_desc(host, desc, addr, len, cmd);
710}
711
712static void sdhci_adma_mark_end(void *desc)
713{
714 struct sdhci_adma2_64_desc *dma_desc = desc;
715
716 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
717 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
718}
719
720static void sdhci_adma_table_pre(struct sdhci_host *host,
721 struct mmc_data *data, int sg_count)
722{
723 struct scatterlist *sg;
724 unsigned long flags;
725 dma_addr_t addr, align_addr;
726 void *desc, *align;
727 char *buffer;
728 int len, offset, i;
729
730 /*
731 * The spec does not specify endianness of descriptor table.
732 * We currently guess that it is LE.
733 */
734
735 host->sg_count = sg_count;
736
737 desc = host->adma_table;
738 align = host->align_buffer;
739
740 align_addr = host->align_addr;
741
742 for_each_sg(data->sg, sg, host->sg_count, i) {
743 addr = sg_dma_address(sg);
744 len = sg_dma_len(sg);
745
746 /*
747 * The SDHCI specification states that ADMA addresses must
748 * be 32-bit aligned. If they aren't, then we use a bounce
749 * buffer for the (up to three) bytes that screw up the
750 * alignment.
751 */
752 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
753 SDHCI_ADMA2_MASK;
754 if (offset) {
755 if (data->flags & MMC_DATA_WRITE) {
756 buffer = sdhci_kmap_atomic(sg, &flags);
757 memcpy(align, buffer, offset);
758 sdhci_kunmap_atomic(buffer, &flags);
759 }
760
761 /* tran, valid */
762 __sdhci_adma_write_desc(host, &desc, align_addr,
763 offset, ADMA2_TRAN_VALID);
764
765 BUG_ON(offset > 65536);
766
767 align += SDHCI_ADMA2_ALIGN;
768 align_addr += SDHCI_ADMA2_ALIGN;
769
770 addr += offset;
771 len -= offset;
772 }
773
774 BUG_ON(len > 65536);
775
776 /* tran, valid */
777 if (len)
778 __sdhci_adma_write_desc(host, &desc, addr, len,
779 ADMA2_TRAN_VALID);
780
781 /*
782 * If this triggers then we have a calculation bug
783 * somewhere. :/
784 */
785 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
786 }
787
788 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
789 /* Mark the last descriptor as the terminating descriptor */
790 if (desc != host->adma_table) {
791 desc -= host->desc_sz;
792 sdhci_adma_mark_end(desc);
793 }
794 } else {
795 /* Add a terminating entry - nop, end, valid */
796 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
797 }
798}
799
800static void sdhci_adma_table_post(struct sdhci_host *host,
801 struct mmc_data *data)
802{
803 struct scatterlist *sg;
804 int i, size;
805 void *align;
806 char *buffer;
807 unsigned long flags;
808
809 if (data->flags & MMC_DATA_READ) {
810 bool has_unaligned = false;
811
812 /* Do a quick scan of the SG list for any unaligned mappings */
813 for_each_sg(data->sg, sg, host->sg_count, i)
814 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
815 has_unaligned = true;
816 break;
817 }
818
819 if (has_unaligned) {
820 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
821 data->sg_len, DMA_FROM_DEVICE);
822
823 align = host->align_buffer;
824
825 for_each_sg(data->sg, sg, host->sg_count, i) {
826 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
827 size = SDHCI_ADMA2_ALIGN -
828 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
829
830 buffer = sdhci_kmap_atomic(sg, &flags);
831 memcpy(buffer, align, size);
832 sdhci_kunmap_atomic(buffer, &flags);
833
834 align += SDHCI_ADMA2_ALIGN;
835 }
836 }
837 }
838 }
839}
840
841static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
842{
843 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
844 if (host->flags & SDHCI_USE_64_BIT_DMA)
845 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
846}
847
848static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
849{
850 if (host->bounce_buffer)
851 return host->bounce_addr;
852 else
853 return sg_dma_address(host->data->sg);
854}
855
856static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
857{
858 if (host->v4_mode)
859 sdhci_set_adma_addr(host, addr);
860 else
861 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
862}
863
864static unsigned int sdhci_target_timeout(struct sdhci_host *host,
865 struct mmc_command *cmd,
866 struct mmc_data *data)
867{
868 unsigned int target_timeout;
869
870 /* timeout in us */
871 if (!data) {
872 target_timeout = cmd->busy_timeout * 1000;
873 } else {
874 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
875 if (host->clock && data->timeout_clks) {
876 unsigned long long val;
877
878 /*
879 * data->timeout_clks is in units of clock cycles.
880 * host->clock is in Hz. target_timeout is in us.
881 * Hence, us = 1000000 * cycles / Hz. Round up.
882 */
883 val = 1000000ULL * data->timeout_clks;
884 if (do_div(val, host->clock))
885 target_timeout++;
886 target_timeout += val;
887 }
888 }
889
890 return target_timeout;
891}
892
893static void sdhci_calc_sw_timeout(struct sdhci_host *host,
894 struct mmc_command *cmd)
895{
896 struct mmc_data *data = cmd->data;
897 struct mmc_host *mmc = host->mmc;
898 struct mmc_ios *ios = &mmc->ios;
899 unsigned char bus_width = 1 << ios->bus_width;
900 unsigned int blksz;
901 unsigned int freq;
902 u64 target_timeout;
903 u64 transfer_time;
904
905 target_timeout = sdhci_target_timeout(host, cmd, data);
906 target_timeout *= NSEC_PER_USEC;
907
908 if (data) {
909 blksz = data->blksz;
910 freq = mmc->actual_clock ? : host->clock;
911 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
912 do_div(transfer_time, freq);
913 /* multiply by '2' to account for any unknowns */
914 transfer_time = transfer_time * 2;
915 /* calculate timeout for the entire data */
916 host->data_timeout = data->blocks * target_timeout +
917 transfer_time;
918 } else {
919 host->data_timeout = target_timeout;
920 }
921
922 if (host->data_timeout)
923 host->data_timeout += MMC_CMD_TRANSFER_TIME;
924}
925
926static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
927 bool *too_big)
928{
929 u8 count;
930 struct mmc_data *data;
931 unsigned target_timeout, current_timeout;
932
933 *too_big = true;
934
935 /*
936 * If the host controller provides us with an incorrect timeout
937 * value, just skip the check and use 0xE. The hardware may take
938 * longer to time out, but that's much better than having a too-short
939 * timeout value.
940 */
941 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
942 return 0xE;
943
944 /* Unspecified command, asume max */
945 if (cmd == NULL)
946 return 0xE;
947
948 data = cmd->data;
949 /* Unspecified timeout, assume max */
950 if (!data && !cmd->busy_timeout)
951 return 0xE;
952
953 /* timeout in us */
954 target_timeout = sdhci_target_timeout(host, cmd, data);
955
956 /*
957 * Figure out needed cycles.
958 * We do this in steps in order to fit inside a 32 bit int.
959 * The first step is the minimum timeout, which will have a
960 * minimum resolution of 6 bits:
961 * (1) 2^13*1000 > 2^22,
962 * (2) host->timeout_clk < 2^16
963 * =>
964 * (1) / (2) > 2^6
965 */
966 count = 0;
967 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
968 while (current_timeout < target_timeout) {
969 count++;
970 current_timeout <<= 1;
971 if (count >= 0xF)
972 break;
973 }
974
975 if (count >= 0xF) {
976 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
977 DBG("Too large timeout 0x%x requested for CMD%d!\n",
978 count, cmd->opcode);
979 count = 0xE;
980 } else {
981 *too_big = false;
982 }
983
984 return count;
985}
986
987static void sdhci_set_transfer_irqs(struct sdhci_host *host)
988{
989 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
990 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
991
992 if (host->flags & SDHCI_REQ_USE_DMA)
993 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
994 else
995 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
996
997 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
998 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
999 else
1000 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1001
1002 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1003 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1004}
1005
1006void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1007{
1008 if (enable)
1009 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1010 else
1011 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1012 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1013 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1014}
1015EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1016
1017void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1018{
1019 bool too_big = false;
1020 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1021
1022 if (too_big &&
1023 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1024 sdhci_calc_sw_timeout(host, cmd);
1025 sdhci_set_data_timeout_irq(host, false);
1026 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1027 sdhci_set_data_timeout_irq(host, true);
1028 }
1029
1030 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1031}
1032EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1033
1034static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1035{
1036 if (host->ops->set_timeout)
1037 host->ops->set_timeout(host, cmd);
1038 else
1039 __sdhci_set_timeout(host, cmd);
1040}
1041
1042static void sdhci_initialize_data(struct sdhci_host *host,
1043 struct mmc_data *data)
1044{
1045 WARN_ON(host->data);
1046
1047 /* Sanity checks */
1048 BUG_ON(data->blksz * data->blocks > 524288);
1049 BUG_ON(data->blksz > host->mmc->max_blk_size);
1050 BUG_ON(data->blocks > 65535);
1051
1052 host->data = data;
1053 host->data_early = 0;
1054 host->data->bytes_xfered = 0;
1055}
1056
1057static inline void sdhci_set_block_info(struct sdhci_host *host,
1058 struct mmc_data *data)
1059{
1060 /* Set the DMA boundary value and block size */
1061 sdhci_writew(host,
1062 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1063 SDHCI_BLOCK_SIZE);
1064 /*
1065 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1066 * can be supported, in that case 16-bit block count register must be 0.
1067 */
1068 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1069 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1070 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1071 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1072 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1073 } else {
1074 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1075 }
1076}
1077
1078static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1079{
1080 struct mmc_data *data = cmd->data;
1081
1082 sdhci_initialize_data(host, data);
1083
1084 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1085 struct scatterlist *sg;
1086 unsigned int length_mask, offset_mask;
1087 int i;
1088
1089 host->flags |= SDHCI_REQ_USE_DMA;
1090
1091 /*
1092 * FIXME: This doesn't account for merging when mapping the
1093 * scatterlist.
1094 *
1095 * The assumption here being that alignment and lengths are
1096 * the same after DMA mapping to device address space.
1097 */
1098 length_mask = 0;
1099 offset_mask = 0;
1100 if (host->flags & SDHCI_USE_ADMA) {
1101 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1102 length_mask = 3;
1103 /*
1104 * As we use up to 3 byte chunks to work
1105 * around alignment problems, we need to
1106 * check the offset as well.
1107 */
1108 offset_mask = 3;
1109 }
1110 } else {
1111 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1112 length_mask = 3;
1113 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1114 offset_mask = 3;
1115 }
1116
1117 if (unlikely(length_mask | offset_mask)) {
1118 for_each_sg(data->sg, sg, data->sg_len, i) {
1119 if (sg->length & length_mask) {
1120 DBG("Reverting to PIO because of transfer size (%d)\n",
1121 sg->length);
1122 host->flags &= ~SDHCI_REQ_USE_DMA;
1123 break;
1124 }
1125 if (sg->offset & offset_mask) {
1126 DBG("Reverting to PIO because of bad alignment\n");
1127 host->flags &= ~SDHCI_REQ_USE_DMA;
1128 break;
1129 }
1130 }
1131 }
1132 }
1133
1134 if (host->flags & SDHCI_REQ_USE_DMA) {
1135 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1136
1137 if (sg_cnt <= 0) {
1138 /*
1139 * This only happens when someone fed
1140 * us an invalid request.
1141 */
1142 WARN_ON(1);
1143 host->flags &= ~SDHCI_REQ_USE_DMA;
1144 } else if (host->flags & SDHCI_USE_ADMA) {
1145 sdhci_adma_table_pre(host, data, sg_cnt);
1146 sdhci_set_adma_addr(host, host->adma_addr);
1147 } else {
1148 WARN_ON(sg_cnt != 1);
1149 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1150 }
1151 }
1152
1153 sdhci_config_dma(host);
1154
1155 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1156 int flags;
1157
1158 flags = SG_MITER_ATOMIC;
1159 if (host->data->flags & MMC_DATA_READ)
1160 flags |= SG_MITER_TO_SG;
1161 else
1162 flags |= SG_MITER_FROM_SG;
1163 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1164 host->blocks = data->blocks;
1165 }
1166
1167 sdhci_set_transfer_irqs(host);
1168
1169 sdhci_set_block_info(host, data);
1170}
1171
1172#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1173
1174static int sdhci_external_dma_init(struct sdhci_host *host)
1175{
1176 int ret = 0;
1177 struct mmc_host *mmc = host->mmc;
1178
1179 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1180 if (IS_ERR(host->tx_chan)) {
1181 ret = PTR_ERR(host->tx_chan);
1182 if (ret != -EPROBE_DEFER)
1183 pr_warn("Failed to request TX DMA channel.\n");
1184 host->tx_chan = NULL;
1185 return ret;
1186 }
1187
1188 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1189 if (IS_ERR(host->rx_chan)) {
1190 if (host->tx_chan) {
1191 dma_release_channel(host->tx_chan);
1192 host->tx_chan = NULL;
1193 }
1194
1195 ret = PTR_ERR(host->rx_chan);
1196 if (ret != -EPROBE_DEFER)
1197 pr_warn("Failed to request RX DMA channel.\n");
1198 host->rx_chan = NULL;
1199 }
1200
1201 return ret;
1202}
1203
1204static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1205 struct mmc_data *data)
1206{
1207 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1208}
1209
1210static int sdhci_external_dma_setup(struct sdhci_host *host,
1211 struct mmc_command *cmd)
1212{
1213 int ret, i;
1214 enum dma_transfer_direction dir;
1215 struct dma_async_tx_descriptor *desc;
1216 struct mmc_data *data = cmd->data;
1217 struct dma_chan *chan;
1218 struct dma_slave_config cfg;
1219 dma_cookie_t cookie;
1220 int sg_cnt;
1221
1222 if (!host->mapbase)
1223 return -EINVAL;
1224
1225 memset(&cfg, 0, sizeof(cfg));
1226 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1227 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1228 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1229 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1230 cfg.src_maxburst = data->blksz / 4;
1231 cfg.dst_maxburst = data->blksz / 4;
1232
1233 /* Sanity check: all the SG entries must be aligned by block size. */
1234 for (i = 0; i < data->sg_len; i++) {
1235 if ((data->sg + i)->length % data->blksz)
1236 return -EINVAL;
1237 }
1238
1239 chan = sdhci_external_dma_channel(host, data);
1240
1241 ret = dmaengine_slave_config(chan, &cfg);
1242 if (ret)
1243 return ret;
1244
1245 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1246 if (sg_cnt <= 0)
1247 return -EINVAL;
1248
1249 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1250 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1251 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1252 if (!desc)
1253 return -EINVAL;
1254
1255 desc->callback = NULL;
1256 desc->callback_param = NULL;
1257
1258 cookie = dmaengine_submit(desc);
1259 if (dma_submit_error(cookie))
1260 ret = cookie;
1261
1262 return ret;
1263}
1264
1265static void sdhci_external_dma_release(struct sdhci_host *host)
1266{
1267 if (host->tx_chan) {
1268 dma_release_channel(host->tx_chan);
1269 host->tx_chan = NULL;
1270 }
1271
1272 if (host->rx_chan) {
1273 dma_release_channel(host->rx_chan);
1274 host->rx_chan = NULL;
1275 }
1276
1277 sdhci_switch_external_dma(host, false);
1278}
1279
1280static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1281 struct mmc_command *cmd)
1282{
1283 struct mmc_data *data = cmd->data;
1284
1285 sdhci_initialize_data(host, data);
1286
1287 host->flags |= SDHCI_REQ_USE_DMA;
1288 sdhci_set_transfer_irqs(host);
1289
1290 sdhci_set_block_info(host, data);
1291}
1292
1293static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1294 struct mmc_command *cmd)
1295{
1296 if (!sdhci_external_dma_setup(host, cmd)) {
1297 __sdhci_external_dma_prepare_data(host, cmd);
1298 } else {
1299 sdhci_external_dma_release(host);
1300 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1301 mmc_hostname(host->mmc));
1302 sdhci_prepare_data(host, cmd);
1303 }
1304}
1305
1306static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1307 struct mmc_command *cmd)
1308{
1309 struct dma_chan *chan;
1310
1311 if (!cmd->data)
1312 return;
1313
1314 chan = sdhci_external_dma_channel(host, cmd->data);
1315 if (chan)
1316 dma_async_issue_pending(chan);
1317}
1318
1319#else
1320
1321static inline int sdhci_external_dma_init(struct sdhci_host *host)
1322{
1323 return -EOPNOTSUPP;
1324}
1325
1326static inline void sdhci_external_dma_release(struct sdhci_host *host)
1327{
1328}
1329
1330static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1331 struct mmc_command *cmd)
1332{
1333 /* This should never happen */
1334 WARN_ON_ONCE(1);
1335}
1336
1337static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1338 struct mmc_command *cmd)
1339{
1340}
1341
1342static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1343 struct mmc_data *data)
1344{
1345 return NULL;
1346}
1347
1348#endif
1349
1350void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1351{
1352 host->use_external_dma = en;
1353}
1354EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1355
1356static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1357 struct mmc_request *mrq)
1358{
1359 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1360 !mrq->cap_cmd_during_tfr;
1361}
1362
1363static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1364 struct mmc_request *mrq)
1365{
1366 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1367}
1368
1369static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1370 struct mmc_request *mrq)
1371{
1372 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1373}
1374
1375static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1376 struct mmc_command *cmd,
1377 u16 *mode)
1378{
1379 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1380 (cmd->opcode != SD_IO_RW_EXTENDED);
1381 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1382 u16 ctrl2;
1383
1384 /*
1385 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1386 * Select' is recommended rather than use of 'Auto CMD12
1387 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1388 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1389 */
1390 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1391 (use_cmd12 || use_cmd23)) {
1392 *mode |= SDHCI_TRNS_AUTO_SEL;
1393
1394 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395 if (use_cmd23)
1396 ctrl2 |= SDHCI_CMD23_ENABLE;
1397 else
1398 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1399 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1400
1401 return;
1402 }
1403
1404 /*
1405 * If we are sending CMD23, CMD12 never gets sent
1406 * on successful completion (so no Auto-CMD12).
1407 */
1408 if (use_cmd12)
1409 *mode |= SDHCI_TRNS_AUTO_CMD12;
1410 else if (use_cmd23)
1411 *mode |= SDHCI_TRNS_AUTO_CMD23;
1412}
1413
1414static void sdhci_set_transfer_mode(struct sdhci_host *host,
1415 struct mmc_command *cmd)
1416{
1417 u16 mode = 0;
1418 struct mmc_data *data = cmd->data;
1419
1420 if (data == NULL) {
1421 if (host->quirks2 &
1422 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1423 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1424 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1425 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1426 } else {
1427 /* clear Auto CMD settings for no data CMDs */
1428 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1429 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1430 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1431 }
1432 return;
1433 }
1434
1435 WARN_ON(!host->data);
1436
1437 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1438 mode = SDHCI_TRNS_BLK_CNT_EN;
1439
1440 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1441 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1442 sdhci_auto_cmd_select(host, cmd, &mode);
1443 if (sdhci_auto_cmd23(host, cmd->mrq))
1444 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1445 }
1446
1447 if (data->flags & MMC_DATA_READ)
1448 mode |= SDHCI_TRNS_READ;
1449 if (host->flags & SDHCI_REQ_USE_DMA)
1450 mode |= SDHCI_TRNS_DMA;
1451
1452 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1453}
1454
1455static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1456{
1457 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1458 ((mrq->cmd && mrq->cmd->error) ||
1459 (mrq->sbc && mrq->sbc->error) ||
1460 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1461 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1462}
1463
1464static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1465{
1466 int i;
1467
1468 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1469 if (host->mrqs_done[i] == mrq) {
1470 WARN_ON(1);
1471 return;
1472 }
1473 }
1474
1475 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1476 if (!host->mrqs_done[i]) {
1477 host->mrqs_done[i] = mrq;
1478 break;
1479 }
1480 }
1481
1482 WARN_ON(i >= SDHCI_MAX_MRQS);
1483}
1484
1485static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1486{
1487 if (host->cmd && host->cmd->mrq == mrq)
1488 host->cmd = NULL;
1489
1490 if (host->data_cmd && host->data_cmd->mrq == mrq)
1491 host->data_cmd = NULL;
1492
1493 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1494 host->deferred_cmd = NULL;
1495
1496 if (host->data && host->data->mrq == mrq)
1497 host->data = NULL;
1498
1499 if (sdhci_needs_reset(host, mrq))
1500 host->pending_reset = true;
1501
1502 sdhci_set_mrq_done(host, mrq);
1503
1504 sdhci_del_timer(host, mrq);
1505
1506 if (!sdhci_has_requests(host))
1507 sdhci_led_deactivate(host);
1508}
1509
1510static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1511{
1512 __sdhci_finish_mrq(host, mrq);
1513
1514 queue_work(host->complete_wq, &host->complete_work);
1515}
1516
1517static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1518{
1519 struct mmc_command *data_cmd = host->data_cmd;
1520 struct mmc_data *data = host->data;
1521
1522 host->data = NULL;
1523 host->data_cmd = NULL;
1524
1525 /*
1526 * The controller needs a reset of internal state machines upon error
1527 * conditions.
1528 */
1529 if (data->error) {
1530 if (!host->cmd || host->cmd == data_cmd)
1531 sdhci_do_reset(host, SDHCI_RESET_CMD);
1532 sdhci_do_reset(host, SDHCI_RESET_DATA);
1533 }
1534
1535 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1536 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1537 sdhci_adma_table_post(host, data);
1538
1539 /*
1540 * The specification states that the block count register must
1541 * be updated, but it does not specify at what point in the
1542 * data flow. That makes the register entirely useless to read
1543 * back so we have to assume that nothing made it to the card
1544 * in the event of an error.
1545 */
1546 if (data->error)
1547 data->bytes_xfered = 0;
1548 else
1549 data->bytes_xfered = data->blksz * data->blocks;
1550
1551 /*
1552 * Need to send CMD12 if -
1553 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1554 * b) error in multiblock transfer
1555 */
1556 if (data->stop &&
1557 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1558 data->error)) {
1559 /*
1560 * 'cap_cmd_during_tfr' request must not use the command line
1561 * after mmc_command_done() has been called. It is upper layer's
1562 * responsibility to send the stop command if required.
1563 */
1564 if (data->mrq->cap_cmd_during_tfr) {
1565 __sdhci_finish_mrq(host, data->mrq);
1566 } else {
1567 /* Avoid triggering warning in sdhci_send_command() */
1568 host->cmd = NULL;
1569 if (!sdhci_send_command(host, data->stop)) {
1570 if (sw_data_timeout) {
1571 /*
1572 * This is anyway a sw data timeout, so
1573 * give up now.
1574 */
1575 data->stop->error = -EIO;
1576 __sdhci_finish_mrq(host, data->mrq);
1577 } else {
1578 WARN_ON(host->deferred_cmd);
1579 host->deferred_cmd = data->stop;
1580 }
1581 }
1582 }
1583 } else {
1584 __sdhci_finish_mrq(host, data->mrq);
1585 }
1586}
1587
1588static void sdhci_finish_data(struct sdhci_host *host)
1589{
1590 __sdhci_finish_data(host, false);
1591}
1592
1593static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1594{
1595 int flags;
1596 u32 mask;
1597 unsigned long timeout;
1598
1599 WARN_ON(host->cmd);
1600
1601 /* Initially, a command has no error */
1602 cmd->error = 0;
1603
1604 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1605 cmd->opcode == MMC_STOP_TRANSMISSION)
1606 cmd->flags |= MMC_RSP_BUSY;
1607
1608 mask = SDHCI_CMD_INHIBIT;
1609 if (sdhci_data_line_cmd(cmd))
1610 mask |= SDHCI_DATA_INHIBIT;
1611
1612 /* We shouldn't wait for data inihibit for stop commands, even
1613 though they might use busy signaling */
1614 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1615 mask &= ~SDHCI_DATA_INHIBIT;
1616
1617 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1618 return false;
1619
1620 host->cmd = cmd;
1621 host->data_timeout = 0;
1622 if (sdhci_data_line_cmd(cmd)) {
1623 WARN_ON(host->data_cmd);
1624 host->data_cmd = cmd;
1625 sdhci_set_timeout(host, cmd);
1626 }
1627
1628 if (cmd->data) {
1629 if (host->use_external_dma)
1630 sdhci_external_dma_prepare_data(host, cmd);
1631 else
1632 sdhci_prepare_data(host, cmd);
1633 }
1634
1635 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1636
1637 sdhci_set_transfer_mode(host, cmd);
1638
1639 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1640 WARN_ONCE(1, "Unsupported response type!\n");
1641 /*
1642 * This does not happen in practice because 136-bit response
1643 * commands never have busy waiting, so rather than complicate
1644 * the error path, just remove busy waiting and continue.
1645 */
1646 cmd->flags &= ~MMC_RSP_BUSY;
1647 }
1648
1649 if (!(cmd->flags & MMC_RSP_PRESENT))
1650 flags = SDHCI_CMD_RESP_NONE;
1651 else if (cmd->flags & MMC_RSP_136)
1652 flags = SDHCI_CMD_RESP_LONG;
1653 else if (cmd->flags & MMC_RSP_BUSY)
1654 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1655 else
1656 flags = SDHCI_CMD_RESP_SHORT;
1657
1658 if (cmd->flags & MMC_RSP_CRC)
1659 flags |= SDHCI_CMD_CRC;
1660 if (cmd->flags & MMC_RSP_OPCODE)
1661 flags |= SDHCI_CMD_INDEX;
1662
1663 /* CMD19 is special in that the Data Present Select should be set */
1664 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1665 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1666 flags |= SDHCI_CMD_DATA;
1667
1668 timeout = jiffies;
1669 if (host->data_timeout)
1670 timeout += nsecs_to_jiffies(host->data_timeout);
1671 else if (!cmd->data && cmd->busy_timeout > 9000)
1672 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1673 else
1674 timeout += 10 * HZ;
1675 sdhci_mod_timer(host, cmd->mrq, timeout);
1676
1677 if (host->use_external_dma)
1678 sdhci_external_dma_pre_transfer(host, cmd);
1679
1680 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1681
1682 return true;
1683}
1684
1685static bool sdhci_present_error(struct sdhci_host *host,
1686 struct mmc_command *cmd, bool present)
1687{
1688 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1689 cmd->error = -ENOMEDIUM;
1690 return true;
1691 }
1692
1693 return false;
1694}
1695
1696static bool sdhci_send_command_retry(struct sdhci_host *host,
1697 struct mmc_command *cmd,
1698 unsigned long flags)
1699 __releases(host->lock)
1700 __acquires(host->lock)
1701{
1702 struct mmc_command *deferred_cmd = host->deferred_cmd;
1703 int timeout = 10; /* Approx. 10 ms */
1704 bool present;
1705
1706 while (!sdhci_send_command(host, cmd)) {
1707 if (!timeout--) {
1708 pr_err("%s: Controller never released inhibit bit(s).\n",
1709 mmc_hostname(host->mmc));
1710 sdhci_dumpregs(host);
1711 cmd->error = -EIO;
1712 return false;
1713 }
1714
1715 spin_unlock_irqrestore(&host->lock, flags);
1716
1717 usleep_range(1000, 1250);
1718
1719 present = host->mmc->ops->get_cd(host->mmc);
1720
1721 spin_lock_irqsave(&host->lock, flags);
1722
1723 /* A deferred command might disappear, handle that */
1724 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1725 return true;
1726
1727 if (sdhci_present_error(host, cmd, present))
1728 return false;
1729 }
1730
1731 if (cmd == host->deferred_cmd)
1732 host->deferred_cmd = NULL;
1733
1734 return true;
1735}
1736
1737static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1738{
1739 int i, reg;
1740
1741 for (i = 0; i < 4; i++) {
1742 reg = SDHCI_RESPONSE + (3 - i) * 4;
1743 cmd->resp[i] = sdhci_readl(host, reg);
1744 }
1745
1746 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1747 return;
1748
1749 /* CRC is stripped so we need to do some shifting */
1750 for (i = 0; i < 4; i++) {
1751 cmd->resp[i] <<= 8;
1752 if (i != 3)
1753 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1754 }
1755}
1756
1757static void sdhci_finish_command(struct sdhci_host *host)
1758{
1759 struct mmc_command *cmd = host->cmd;
1760
1761 host->cmd = NULL;
1762
1763 if (cmd->flags & MMC_RSP_PRESENT) {
1764 if (cmd->flags & MMC_RSP_136) {
1765 sdhci_read_rsp_136(host, cmd);
1766 } else {
1767 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1768 }
1769 }
1770
1771 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1772 mmc_command_done(host->mmc, cmd->mrq);
1773
1774 /*
1775 * The host can send and interrupt when the busy state has
1776 * ended, allowing us to wait without wasting CPU cycles.
1777 * The busy signal uses DAT0 so this is similar to waiting
1778 * for data to complete.
1779 *
1780 * Note: The 1.0 specification is a bit ambiguous about this
1781 * feature so there might be some problems with older
1782 * controllers.
1783 */
1784 if (cmd->flags & MMC_RSP_BUSY) {
1785 if (cmd->data) {
1786 DBG("Cannot wait for busy signal when also doing a data transfer");
1787 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1788 cmd == host->data_cmd) {
1789 /* Command complete before busy is ended */
1790 return;
1791 }
1792 }
1793
1794 /* Finished CMD23, now send actual command. */
1795 if (cmd == cmd->mrq->sbc) {
1796 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1797 WARN_ON(host->deferred_cmd);
1798 host->deferred_cmd = cmd->mrq->cmd;
1799 }
1800 } else {
1801
1802 /* Processed actual command. */
1803 if (host->data && host->data_early)
1804 sdhci_finish_data(host);
1805
1806 if (!cmd->data)
1807 __sdhci_finish_mrq(host, cmd->mrq);
1808 }
1809}
1810
1811static u16 sdhci_get_preset_value(struct sdhci_host *host)
1812{
1813 u16 preset = 0;
1814
1815 switch (host->timing) {
1816 case MMC_TIMING_MMC_HS:
1817 case MMC_TIMING_SD_HS:
1818 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1819 break;
1820 case MMC_TIMING_UHS_SDR12:
1821 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1822 break;
1823 case MMC_TIMING_UHS_SDR25:
1824 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1825 break;
1826 case MMC_TIMING_UHS_SDR50:
1827 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1828 break;
1829 case MMC_TIMING_UHS_SDR104:
1830 case MMC_TIMING_MMC_HS200:
1831 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1832 break;
1833 case MMC_TIMING_UHS_DDR50:
1834 case MMC_TIMING_MMC_DDR52:
1835 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1836 break;
1837 case MMC_TIMING_MMC_HS400:
1838 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1839 break;
1840 default:
1841 pr_warn("%s: Invalid UHS-I mode selected\n",
1842 mmc_hostname(host->mmc));
1843 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1844 break;
1845 }
1846 return preset;
1847}
1848
1849u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1850 unsigned int *actual_clock)
1851{
1852 int div = 0; /* Initialized for compiler warning */
1853 int real_div = div, clk_mul = 1;
1854 u16 clk = 0;
1855 bool switch_base_clk = false;
1856
1857 if (host->version >= SDHCI_SPEC_300) {
1858 if (host->preset_enabled) {
1859 u16 pre_val;
1860
1861 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1862 pre_val = sdhci_get_preset_value(host);
1863 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1864 if (host->clk_mul &&
1865 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1866 clk = SDHCI_PROG_CLOCK_MODE;
1867 real_div = div + 1;
1868 clk_mul = host->clk_mul;
1869 } else {
1870 real_div = max_t(int, 1, div << 1);
1871 }
1872 goto clock_set;
1873 }
1874
1875 /*
1876 * Check if the Host Controller supports Programmable Clock
1877 * Mode.
1878 */
1879 if (host->clk_mul) {
1880 for (div = 1; div <= 1024; div++) {
1881 if ((host->max_clk * host->clk_mul / div)
1882 <= clock)
1883 break;
1884 }
1885 if ((host->max_clk * host->clk_mul / div) <= clock) {
1886 /*
1887 * Set Programmable Clock Mode in the Clock
1888 * Control register.
1889 */
1890 clk = SDHCI_PROG_CLOCK_MODE;
1891 real_div = div;
1892 clk_mul = host->clk_mul;
1893 div--;
1894 } else {
1895 /*
1896 * Divisor can be too small to reach clock
1897 * speed requirement. Then use the base clock.
1898 */
1899 switch_base_clk = true;
1900 }
1901 }
1902
1903 if (!host->clk_mul || switch_base_clk) {
1904 /* Version 3.00 divisors must be a multiple of 2. */
1905 if (host->max_clk <= clock)
1906 div = 1;
1907 else {
1908 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1909 div += 2) {
1910 if ((host->max_clk / div) <= clock)
1911 break;
1912 }
1913 }
1914 real_div = div;
1915 div >>= 1;
1916 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1917 && !div && host->max_clk <= 25000000)
1918 div = 1;
1919 }
1920 } else {
1921 /* Version 2.00 divisors must be a power of 2. */
1922 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1923 if ((host->max_clk / div) <= clock)
1924 break;
1925 }
1926 real_div = div;
1927 div >>= 1;
1928 }
1929
1930clock_set:
1931 if (real_div)
1932 *actual_clock = (host->max_clk * clk_mul) / real_div;
1933 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1934 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1935 << SDHCI_DIVIDER_HI_SHIFT;
1936
1937 return clk;
1938}
1939EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1940
1941void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1942{
1943 ktime_t timeout;
1944
1945 clk |= SDHCI_CLOCK_INT_EN;
1946 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1947
1948 /* Wait max 150 ms */
1949 timeout = ktime_add_ms(ktime_get(), 150);
1950 while (1) {
1951 bool timedout = ktime_after(ktime_get(), timeout);
1952
1953 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1954 if (clk & SDHCI_CLOCK_INT_STABLE)
1955 break;
1956 if (timedout) {
1957 pr_err("%s: Internal clock never stabilised.\n",
1958 mmc_hostname(host->mmc));
1959 sdhci_dumpregs(host);
1960 return;
1961 }
1962 udelay(10);
1963 }
1964
1965 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1966 clk |= SDHCI_CLOCK_PLL_EN;
1967 clk &= ~SDHCI_CLOCK_INT_STABLE;
1968 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1969
1970 /* Wait max 150 ms */
1971 timeout = ktime_add_ms(ktime_get(), 150);
1972 while (1) {
1973 bool timedout = ktime_after(ktime_get(), timeout);
1974
1975 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1976 if (clk & SDHCI_CLOCK_INT_STABLE)
1977 break;
1978 if (timedout) {
1979 pr_err("%s: PLL clock never stabilised.\n",
1980 mmc_hostname(host->mmc));
1981 sdhci_dumpregs(host);
1982 return;
1983 }
1984 udelay(10);
1985 }
1986 }
1987
1988 clk |= SDHCI_CLOCK_CARD_EN;
1989 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1990}
1991EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1992
1993void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1994{
1995 u16 clk;
1996
1997 host->mmc->actual_clock = 0;
1998
1999 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2000
2001 if (clock == 0)
2002 return;
2003
2004 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2005 sdhci_enable_clk(host, clk);
2006}
2007EXPORT_SYMBOL_GPL(sdhci_set_clock);
2008
2009static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2010 unsigned short vdd)
2011{
2012 struct mmc_host *mmc = host->mmc;
2013
2014 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2015
2016 if (mode != MMC_POWER_OFF)
2017 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2018 else
2019 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2020}
2021
2022void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2023 unsigned short vdd)
2024{
2025 u8 pwr = 0;
2026
2027 if (mode != MMC_POWER_OFF) {
2028 switch (1 << vdd) {
2029 case MMC_VDD_165_195:
2030 /*
2031 * Without a regulator, SDHCI does not support 2.0v
2032 * so we only get here if the driver deliberately
2033 * added the 2.0v range to ocr_avail. Map it to 1.8v
2034 * for the purpose of turning on the power.
2035 */
2036 case MMC_VDD_20_21:
2037 pwr = SDHCI_POWER_180;
2038 break;
2039 case MMC_VDD_29_30:
2040 case MMC_VDD_30_31:
2041 pwr = SDHCI_POWER_300;
2042 break;
2043 case MMC_VDD_32_33:
2044 case MMC_VDD_33_34:
2045 pwr = SDHCI_POWER_330;
2046 break;
2047 default:
2048 WARN(1, "%s: Invalid vdd %#x\n",
2049 mmc_hostname(host->mmc), vdd);
2050 break;
2051 }
2052 }
2053
2054 if (host->pwr == pwr)
2055 return;
2056
2057 host->pwr = pwr;
2058
2059 if (pwr == 0) {
2060 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2061 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2062 sdhci_runtime_pm_bus_off(host);
2063 } else {
2064 /*
2065 * Spec says that we should clear the power reg before setting
2066 * a new value. Some controllers don't seem to like this though.
2067 */
2068 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2069 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2070
2071 /*
2072 * At least the Marvell CaFe chip gets confused if we set the
2073 * voltage and set turn on power at the same time, so set the
2074 * voltage first.
2075 */
2076 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2077 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2078
2079 pwr |= SDHCI_POWER_ON;
2080
2081 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2082
2083 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2084 sdhci_runtime_pm_bus_on(host);
2085
2086 /*
2087 * Some controllers need an extra 10ms delay of 10ms before
2088 * they can apply clock after applying power
2089 */
2090 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2091 mdelay(10);
2092 }
2093}
2094EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2095
2096void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2097 unsigned short vdd)
2098{
2099 if (IS_ERR(host->mmc->supply.vmmc))
2100 sdhci_set_power_noreg(host, mode, vdd);
2101 else
2102 sdhci_set_power_reg(host, mode, vdd);
2103}
2104EXPORT_SYMBOL_GPL(sdhci_set_power);
2105
2106/*
2107 * Some controllers need to configure a valid bus voltage on their power
2108 * register regardless of whether an external regulator is taking care of power
2109 * supply. This helper function takes care of it if set as the controller's
2110 * sdhci_ops.set_power callback.
2111 */
2112void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2113 unsigned char mode,
2114 unsigned short vdd)
2115{
2116 if (!IS_ERR(host->mmc->supply.vmmc)) {
2117 struct mmc_host *mmc = host->mmc;
2118
2119 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2120 }
2121 sdhci_set_power_noreg(host, mode, vdd);
2122}
2123EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2124
2125/*****************************************************************************\
2126 * *
2127 * MMC callbacks *
2128 * *
2129\*****************************************************************************/
2130
2131void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2132{
2133 struct sdhci_host *host = mmc_priv(mmc);
2134 struct mmc_command *cmd;
2135 unsigned long flags;
2136 bool present;
2137
2138 /* Firstly check card presence */
2139 present = mmc->ops->get_cd(mmc);
2140
2141 spin_lock_irqsave(&host->lock, flags);
2142
2143 sdhci_led_activate(host);
2144
2145 if (sdhci_present_error(host, mrq->cmd, present))
2146 goto out_finish;
2147
2148 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2149
2150 if (!sdhci_send_command_retry(host, cmd, flags))
2151 goto out_finish;
2152
2153 spin_unlock_irqrestore(&host->lock, flags);
2154
2155 return;
2156
2157out_finish:
2158 sdhci_finish_mrq(host, mrq);
2159 spin_unlock_irqrestore(&host->lock, flags);
2160}
2161EXPORT_SYMBOL_GPL(sdhci_request);
2162
2163int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2164{
2165 struct sdhci_host *host = mmc_priv(mmc);
2166 struct mmc_command *cmd;
2167 unsigned long flags;
2168 int ret = 0;
2169
2170 spin_lock_irqsave(&host->lock, flags);
2171
2172 if (sdhci_present_error(host, mrq->cmd, true)) {
2173 sdhci_finish_mrq(host, mrq);
2174 goto out_finish;
2175 }
2176
2177 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2178
2179 /*
2180 * The HSQ may send a command in interrupt context without polling
2181 * the busy signaling, which means we should return BUSY if controller
2182 * has not released inhibit bits to allow HSQ trying to send request
2183 * again in non-atomic context. So we should not finish this request
2184 * here.
2185 */
2186 if (!sdhci_send_command(host, cmd))
2187 ret = -EBUSY;
2188 else
2189 sdhci_led_activate(host);
2190
2191out_finish:
2192 spin_unlock_irqrestore(&host->lock, flags);
2193 return ret;
2194}
2195EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2196
2197void sdhci_set_bus_width(struct sdhci_host *host, int width)
2198{
2199 u8 ctrl;
2200
2201 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2202 if (width == MMC_BUS_WIDTH_8) {
2203 ctrl &= ~SDHCI_CTRL_4BITBUS;
2204 ctrl |= SDHCI_CTRL_8BITBUS;
2205 } else {
2206 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2207 ctrl &= ~SDHCI_CTRL_8BITBUS;
2208 if (width == MMC_BUS_WIDTH_4)
2209 ctrl |= SDHCI_CTRL_4BITBUS;
2210 else
2211 ctrl &= ~SDHCI_CTRL_4BITBUS;
2212 }
2213 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2214}
2215EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2216
2217void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2218{
2219 u16 ctrl_2;
2220
2221 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2222 /* Select Bus Speed Mode for host */
2223 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2224 if ((timing == MMC_TIMING_MMC_HS200) ||
2225 (timing == MMC_TIMING_UHS_SDR104))
2226 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2227 else if (timing == MMC_TIMING_UHS_SDR12)
2228 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2229 else if (timing == MMC_TIMING_UHS_SDR25)
2230 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2231 else if (timing == MMC_TIMING_UHS_SDR50)
2232 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2233 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2234 (timing == MMC_TIMING_MMC_DDR52))
2235 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2236 else if (timing == MMC_TIMING_MMC_HS400)
2237 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2238 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2239}
2240EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2241
2242void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2243{
2244 struct sdhci_host *host = mmc_priv(mmc);
2245 u8 ctrl;
2246
2247 if (ios->power_mode == MMC_POWER_UNDEFINED)
2248 return;
2249
2250 if (host->flags & SDHCI_DEVICE_DEAD) {
2251 if (!IS_ERR(mmc->supply.vmmc) &&
2252 ios->power_mode == MMC_POWER_OFF)
2253 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2254 return;
2255 }
2256
2257 /*
2258 * Reset the chip on each power off.
2259 * Should clear out any weird states.
2260 */
2261 if (ios->power_mode == MMC_POWER_OFF) {
2262 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2263 sdhci_reinit(host);
2264 }
2265
2266 if (host->version >= SDHCI_SPEC_300 &&
2267 (ios->power_mode == MMC_POWER_UP) &&
2268 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2269 sdhci_enable_preset_value(host, false);
2270
2271 if (!ios->clock || ios->clock != host->clock) {
2272 host->ops->set_clock(host, ios->clock);
2273 host->clock = ios->clock;
2274
2275 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2276 host->clock) {
2277 host->timeout_clk = mmc->actual_clock ?
2278 mmc->actual_clock / 1000 :
2279 host->clock / 1000;
2280 mmc->max_busy_timeout =
2281 host->ops->get_max_timeout_count ?
2282 host->ops->get_max_timeout_count(host) :
2283 1 << 27;
2284 mmc->max_busy_timeout /= host->timeout_clk;
2285 }
2286 }
2287
2288 if (host->ops->set_power)
2289 host->ops->set_power(host, ios->power_mode, ios->vdd);
2290 else
2291 sdhci_set_power(host, ios->power_mode, ios->vdd);
2292
2293 if (host->ops->platform_send_init_74_clocks)
2294 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2295
2296 host->ops->set_bus_width(host, ios->bus_width);
2297
2298 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2299
2300 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2301 if (ios->timing == MMC_TIMING_SD_HS ||
2302 ios->timing == MMC_TIMING_MMC_HS ||
2303 ios->timing == MMC_TIMING_MMC_HS400 ||
2304 ios->timing == MMC_TIMING_MMC_HS200 ||
2305 ios->timing == MMC_TIMING_MMC_DDR52 ||
2306 ios->timing == MMC_TIMING_UHS_SDR50 ||
2307 ios->timing == MMC_TIMING_UHS_SDR104 ||
2308 ios->timing == MMC_TIMING_UHS_DDR50 ||
2309 ios->timing == MMC_TIMING_UHS_SDR25)
2310 ctrl |= SDHCI_CTRL_HISPD;
2311 else
2312 ctrl &= ~SDHCI_CTRL_HISPD;
2313 }
2314
2315 if (host->version >= SDHCI_SPEC_300) {
2316 u16 clk, ctrl_2;
2317
2318 if (!host->preset_enabled) {
2319 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2320 /*
2321 * We only need to set Driver Strength if the
2322 * preset value enable is not set.
2323 */
2324 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2325 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2326 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2327 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2328 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2329 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2330 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2331 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2332 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2333 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2334 else {
2335 pr_warn("%s: invalid driver type, default to driver type B\n",
2336 mmc_hostname(mmc));
2337 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2338 }
2339
2340 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2341 } else {
2342 /*
2343 * According to SDHC Spec v3.00, if the Preset Value
2344 * Enable in the Host Control 2 register is set, we
2345 * need to reset SD Clock Enable before changing High
2346 * Speed Enable to avoid generating clock gliches.
2347 */
2348
2349 /* Reset SD Clock Enable */
2350 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2351 clk &= ~SDHCI_CLOCK_CARD_EN;
2352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2353
2354 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2355
2356 /* Re-enable SD Clock */
2357 host->ops->set_clock(host, host->clock);
2358 }
2359
2360 /* Reset SD Clock Enable */
2361 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2362 clk &= ~SDHCI_CLOCK_CARD_EN;
2363 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2364
2365 host->ops->set_uhs_signaling(host, ios->timing);
2366 host->timing = ios->timing;
2367
2368 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2369 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2370 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2371 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2372 (ios->timing == MMC_TIMING_UHS_SDR104) ||
2373 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2374 (ios->timing == MMC_TIMING_MMC_DDR52))) {
2375 u16 preset;
2376
2377 sdhci_enable_preset_value(host, true);
2378 preset = sdhci_get_preset_value(host);
2379 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2380 preset);
2381 }
2382
2383 /* Re-enable SD Clock */
2384 host->ops->set_clock(host, host->clock);
2385 } else
2386 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2387
2388 /*
2389 * Some (ENE) controllers go apeshit on some ios operation,
2390 * signalling timeout and CRC errors even on CMD0. Resetting
2391 * it on each ios seems to solve the problem.
2392 */
2393 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2394 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2395}
2396EXPORT_SYMBOL_GPL(sdhci_set_ios);
2397
2398static int sdhci_get_cd(struct mmc_host *mmc)
2399{
2400 struct sdhci_host *host = mmc_priv(mmc);
2401 int gpio_cd = mmc_gpio_get_cd(mmc);
2402
2403 if (host->flags & SDHCI_DEVICE_DEAD)
2404 return 0;
2405
2406 /* If nonremovable, assume that the card is always present. */
2407 if (!mmc_card_is_removable(mmc))
2408 return 1;
2409
2410 /*
2411 * Try slot gpio detect, if defined it take precedence
2412 * over build in controller functionality
2413 */
2414 if (gpio_cd >= 0)
2415 return !!gpio_cd;
2416
2417 /* If polling, assume that the card is always present. */
2418 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2419 return 1;
2420
2421 /* Host native card detect */
2422 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2423}
2424
2425static int sdhci_check_ro(struct sdhci_host *host)
2426{
2427 unsigned long flags;
2428 int is_readonly;
2429
2430 spin_lock_irqsave(&host->lock, flags);
2431
2432 if (host->flags & SDHCI_DEVICE_DEAD)
2433 is_readonly = 0;
2434 else if (host->ops->get_ro)
2435 is_readonly = host->ops->get_ro(host);
2436 else if (mmc_can_gpio_ro(host->mmc))
2437 is_readonly = mmc_gpio_get_ro(host->mmc);
2438 else
2439 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2440 & SDHCI_WRITE_PROTECT);
2441
2442 spin_unlock_irqrestore(&host->lock, flags);
2443
2444 /* This quirk needs to be replaced by a callback-function later */
2445 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2446 !is_readonly : is_readonly;
2447}
2448
2449#define SAMPLE_COUNT 5
2450
2451static int sdhci_get_ro(struct mmc_host *mmc)
2452{
2453 struct sdhci_host *host = mmc_priv(mmc);
2454 int i, ro_count;
2455
2456 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2457 return sdhci_check_ro(host);
2458
2459 ro_count = 0;
2460 for (i = 0; i < SAMPLE_COUNT; i++) {
2461 if (sdhci_check_ro(host)) {
2462 if (++ro_count > SAMPLE_COUNT / 2)
2463 return 1;
2464 }
2465 msleep(30);
2466 }
2467 return 0;
2468}
2469
2470static void sdhci_hw_reset(struct mmc_host *mmc)
2471{
2472 struct sdhci_host *host = mmc_priv(mmc);
2473
2474 if (host->ops && host->ops->hw_reset)
2475 host->ops->hw_reset(host);
2476}
2477
2478static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2479{
2480 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2481 if (enable)
2482 host->ier |= SDHCI_INT_CARD_INT;
2483 else
2484 host->ier &= ~SDHCI_INT_CARD_INT;
2485
2486 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2487 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2488 }
2489}
2490
2491void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2492{
2493 struct sdhci_host *host = mmc_priv(mmc);
2494 unsigned long flags;
2495
2496 if (enable)
2497 pm_runtime_get_noresume(mmc_dev(mmc));
2498
2499 spin_lock_irqsave(&host->lock, flags);
2500 sdhci_enable_sdio_irq_nolock(host, enable);
2501 spin_unlock_irqrestore(&host->lock, flags);
2502
2503 if (!enable)
2504 pm_runtime_put_noidle(mmc_dev(mmc));
2505}
2506EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2507
2508static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2509{
2510 struct sdhci_host *host = mmc_priv(mmc);
2511 unsigned long flags;
2512
2513 spin_lock_irqsave(&host->lock, flags);
2514 sdhci_enable_sdio_irq_nolock(host, true);
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2519 struct mmc_ios *ios)
2520{
2521 struct sdhci_host *host = mmc_priv(mmc);
2522 u16 ctrl;
2523 int ret;
2524
2525 /*
2526 * Signal Voltage Switching is only applicable for Host Controllers
2527 * v3.00 and above.
2528 */
2529 if (host->version < SDHCI_SPEC_300)
2530 return 0;
2531
2532 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2533
2534 switch (ios->signal_voltage) {
2535 case MMC_SIGNAL_VOLTAGE_330:
2536 if (!(host->flags & SDHCI_SIGNALING_330))
2537 return -EINVAL;
2538 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2539 ctrl &= ~SDHCI_CTRL_VDD_180;
2540 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2541
2542 if (!IS_ERR(mmc->supply.vqmmc)) {
2543 ret = mmc_regulator_set_vqmmc(mmc, ios);
2544 if (ret < 0) {
2545 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2546 mmc_hostname(mmc));
2547 return -EIO;
2548 }
2549 }
2550 /* Wait for 5ms */
2551 usleep_range(5000, 5500);
2552
2553 /* 3.3V regulator output should be stable within 5 ms */
2554 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2555 if (!(ctrl & SDHCI_CTRL_VDD_180))
2556 return 0;
2557
2558 pr_warn("%s: 3.3V regulator output did not become stable\n",
2559 mmc_hostname(mmc));
2560
2561 return -EAGAIN;
2562 case MMC_SIGNAL_VOLTAGE_180:
2563 if (!(host->flags & SDHCI_SIGNALING_180))
2564 return -EINVAL;
2565 if (!IS_ERR(mmc->supply.vqmmc)) {
2566 ret = mmc_regulator_set_vqmmc(mmc, ios);
2567 if (ret < 0) {
2568 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2569 mmc_hostname(mmc));
2570 return -EIO;
2571 }
2572 }
2573
2574 /*
2575 * Enable 1.8V Signal Enable in the Host Control2
2576 * register
2577 */
2578 ctrl |= SDHCI_CTRL_VDD_180;
2579 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2580
2581 /* Some controller need to do more when switching */
2582 if (host->ops->voltage_switch)
2583 host->ops->voltage_switch(host);
2584
2585 /* 1.8V regulator output should be stable within 5 ms */
2586 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2587 if (ctrl & SDHCI_CTRL_VDD_180)
2588 return 0;
2589
2590 pr_warn("%s: 1.8V regulator output did not become stable\n",
2591 mmc_hostname(mmc));
2592
2593 return -EAGAIN;
2594 case MMC_SIGNAL_VOLTAGE_120:
2595 if (!(host->flags & SDHCI_SIGNALING_120))
2596 return -EINVAL;
2597 if (!IS_ERR(mmc->supply.vqmmc)) {
2598 ret = mmc_regulator_set_vqmmc(mmc, ios);
2599 if (ret < 0) {
2600 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2601 mmc_hostname(mmc));
2602 return -EIO;
2603 }
2604 }
2605 return 0;
2606 default:
2607 /* No signal voltage switch required */
2608 return 0;
2609 }
2610}
2611EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2612
2613static int sdhci_card_busy(struct mmc_host *mmc)
2614{
2615 struct sdhci_host *host = mmc_priv(mmc);
2616 u32 present_state;
2617
2618 /* Check whether DAT[0] is 0 */
2619 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2620
2621 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2622}
2623
2624static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2625{
2626 struct sdhci_host *host = mmc_priv(mmc);
2627 unsigned long flags;
2628
2629 spin_lock_irqsave(&host->lock, flags);
2630 host->flags |= SDHCI_HS400_TUNING;
2631 spin_unlock_irqrestore(&host->lock, flags);
2632
2633 return 0;
2634}
2635
2636void sdhci_start_tuning(struct sdhci_host *host)
2637{
2638 u16 ctrl;
2639
2640 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2641 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2642 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2643 ctrl |= SDHCI_CTRL_TUNED_CLK;
2644 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2645
2646 /*
2647 * As per the Host Controller spec v3.00, tuning command
2648 * generates Buffer Read Ready interrupt, so enable that.
2649 *
2650 * Note: The spec clearly says that when tuning sequence
2651 * is being performed, the controller does not generate
2652 * interrupts other than Buffer Read Ready interrupt. But
2653 * to make sure we don't hit a controller bug, we _only_
2654 * enable Buffer Read Ready interrupt here.
2655 */
2656 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2657 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2658}
2659EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2660
2661void sdhci_end_tuning(struct sdhci_host *host)
2662{
2663 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2664 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2665}
2666EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2667
2668void sdhci_reset_tuning(struct sdhci_host *host)
2669{
2670 u16 ctrl;
2671
2672 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2673 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2674 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2675 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2676}
2677EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2678
2679void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2680{
2681 sdhci_reset_tuning(host);
2682
2683 sdhci_do_reset(host, SDHCI_RESET_CMD);
2684 sdhci_do_reset(host, SDHCI_RESET_DATA);
2685
2686 sdhci_end_tuning(host);
2687
2688 mmc_send_abort_tuning(host->mmc, opcode);
2689}
2690EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2691
2692/*
2693 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2694 * tuning command does not have a data payload (or rather the hardware does it
2695 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2696 * interrupt setup is different to other commands and there is no timeout
2697 * interrupt so special handling is needed.
2698 */
2699void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2700{
2701 struct mmc_host *mmc = host->mmc;
2702 struct mmc_command cmd = {};
2703 struct mmc_request mrq = {};
2704 unsigned long flags;
2705 u32 b = host->sdma_boundary;
2706
2707 spin_lock_irqsave(&host->lock, flags);
2708
2709 cmd.opcode = opcode;
2710 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2711 cmd.mrq = &mrq;
2712
2713 mrq.cmd = &cmd;
2714 /*
2715 * In response to CMD19, the card sends 64 bytes of tuning
2716 * block to the Host Controller. So we set the block size
2717 * to 64 here.
2718 */
2719 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2720 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2721 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2722 else
2723 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2724
2725 /*
2726 * The tuning block is sent by the card to the host controller.
2727 * So we set the TRNS_READ bit in the Transfer Mode register.
2728 * This also takes care of setting DMA Enable and Multi Block
2729 * Select in the same register to 0.
2730 */
2731 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2732
2733 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2734 spin_unlock_irqrestore(&host->lock, flags);
2735 host->tuning_done = 0;
2736 return;
2737 }
2738
2739 host->cmd = NULL;
2740
2741 sdhci_del_timer(host, &mrq);
2742
2743 host->tuning_done = 0;
2744
2745 spin_unlock_irqrestore(&host->lock, flags);
2746
2747 /* Wait for Buffer Read Ready interrupt */
2748 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2749 msecs_to_jiffies(50));
2750
2751}
2752EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2753
2754static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2755{
2756 int i;
2757
2758 /*
2759 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2760 * of loops reaches tuning loop count.
2761 */
2762 for (i = 0; i < host->tuning_loop_count; i++) {
2763 u16 ctrl;
2764
2765 sdhci_send_tuning(host, opcode);
2766
2767 if (!host->tuning_done) {
2768 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2769 mmc_hostname(host->mmc));
2770 sdhci_abort_tuning(host, opcode);
2771 return -ETIMEDOUT;
2772 }
2773
2774 /* Spec does not require a delay between tuning cycles */
2775 if (host->tuning_delay > 0)
2776 mdelay(host->tuning_delay);
2777
2778 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2779 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2780 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2781 return 0; /* Success! */
2782 break;
2783 }
2784
2785 }
2786
2787 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2788 mmc_hostname(host->mmc));
2789 sdhci_reset_tuning(host);
2790 return -EAGAIN;
2791}
2792
2793int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2794{
2795 struct sdhci_host *host = mmc_priv(mmc);
2796 int err = 0;
2797 unsigned int tuning_count = 0;
2798 bool hs400_tuning;
2799
2800 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2801
2802 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2803 tuning_count = host->tuning_count;
2804
2805 /*
2806 * The Host Controller needs tuning in case of SDR104 and DDR50
2807 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2808 * the Capabilities register.
2809 * If the Host Controller supports the HS200 mode then the
2810 * tuning function has to be executed.
2811 */
2812 switch (host->timing) {
2813 /* HS400 tuning is done in HS200 mode */
2814 case MMC_TIMING_MMC_HS400:
2815 err = -EINVAL;
2816 goto out;
2817
2818 case MMC_TIMING_MMC_HS200:
2819 /*
2820 * Periodic re-tuning for HS400 is not expected to be needed, so
2821 * disable it here.
2822 */
2823 if (hs400_tuning)
2824 tuning_count = 0;
2825 break;
2826
2827 case MMC_TIMING_UHS_SDR104:
2828 case MMC_TIMING_UHS_DDR50:
2829 break;
2830
2831 case MMC_TIMING_UHS_SDR50:
2832 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2833 break;
2834 fallthrough;
2835
2836 default:
2837 goto out;
2838 }
2839
2840 if (host->ops->platform_execute_tuning) {
2841 err = host->ops->platform_execute_tuning(host, opcode);
2842 goto out;
2843 }
2844
2845 mmc->retune_period = tuning_count;
2846
2847 if (host->tuning_delay < 0)
2848 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2849
2850 sdhci_start_tuning(host);
2851
2852 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2853
2854 sdhci_end_tuning(host);
2855out:
2856 host->flags &= ~SDHCI_HS400_TUNING;
2857
2858 return err;
2859}
2860EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2861
2862static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2863{
2864 /* Host Controller v3.00 defines preset value registers */
2865 if (host->version < SDHCI_SPEC_300)
2866 return;
2867
2868 /*
2869 * We only enable or disable Preset Value if they are not already
2870 * enabled or disabled respectively. Otherwise, we bail out.
2871 */
2872 if (host->preset_enabled != enable) {
2873 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2874
2875 if (enable)
2876 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2877 else
2878 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2879
2880 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2881
2882 if (enable)
2883 host->flags |= SDHCI_PV_ENABLED;
2884 else
2885 host->flags &= ~SDHCI_PV_ENABLED;
2886
2887 host->preset_enabled = enable;
2888 }
2889}
2890
2891static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2892 int err)
2893{
2894 struct mmc_data *data = mrq->data;
2895
2896 if (data->host_cookie != COOKIE_UNMAPPED)
2897 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
2898 mmc_get_dma_dir(data));
2899
2900 data->host_cookie = COOKIE_UNMAPPED;
2901}
2902
2903static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2904{
2905 struct sdhci_host *host = mmc_priv(mmc);
2906
2907 mrq->data->host_cookie = COOKIE_UNMAPPED;
2908
2909 /*
2910 * No pre-mapping in the pre hook if we're using the bounce buffer,
2911 * for that we would need two bounce buffers since one buffer is
2912 * in flight when this is getting called.
2913 */
2914 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2915 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2916}
2917
2918static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2919{
2920 if (host->data_cmd) {
2921 host->data_cmd->error = err;
2922 sdhci_finish_mrq(host, host->data_cmd->mrq);
2923 }
2924
2925 if (host->cmd) {
2926 host->cmd->error = err;
2927 sdhci_finish_mrq(host, host->cmd->mrq);
2928 }
2929}
2930
2931static void sdhci_card_event(struct mmc_host *mmc)
2932{
2933 struct sdhci_host *host = mmc_priv(mmc);
2934 unsigned long flags;
2935 int present;
2936
2937 /* First check if client has provided their own card event */
2938 if (host->ops->card_event)
2939 host->ops->card_event(host);
2940
2941 present = mmc->ops->get_cd(mmc);
2942
2943 spin_lock_irqsave(&host->lock, flags);
2944
2945 /* Check sdhci_has_requests() first in case we are runtime suspended */
2946 if (sdhci_has_requests(host) && !present) {
2947 pr_err("%s: Card removed during transfer!\n",
2948 mmc_hostname(mmc));
2949 pr_err("%s: Resetting controller.\n",
2950 mmc_hostname(mmc));
2951
2952 sdhci_do_reset(host, SDHCI_RESET_CMD);
2953 sdhci_do_reset(host, SDHCI_RESET_DATA);
2954
2955 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2956 }
2957
2958 spin_unlock_irqrestore(&host->lock, flags);
2959}
2960
2961static const struct mmc_host_ops sdhci_ops = {
2962 .request = sdhci_request,
2963 .post_req = sdhci_post_req,
2964 .pre_req = sdhci_pre_req,
2965 .set_ios = sdhci_set_ios,
2966 .get_cd = sdhci_get_cd,
2967 .get_ro = sdhci_get_ro,
2968 .hw_reset = sdhci_hw_reset,
2969 .enable_sdio_irq = sdhci_enable_sdio_irq,
2970 .ack_sdio_irq = sdhci_ack_sdio_irq,
2971 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2972 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2973 .execute_tuning = sdhci_execute_tuning,
2974 .card_event = sdhci_card_event,
2975 .card_busy = sdhci_card_busy,
2976};
2977
2978/*****************************************************************************\
2979 * *
2980 * Request done *
2981 * *
2982\*****************************************************************************/
2983
2984static bool sdhci_request_done(struct sdhci_host *host)
2985{
2986 unsigned long flags;
2987 struct mmc_request *mrq;
2988 int i;
2989
2990 spin_lock_irqsave(&host->lock, flags);
2991
2992 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2993 mrq = host->mrqs_done[i];
2994 if (mrq)
2995 break;
2996 }
2997
2998 if (!mrq) {
2999 spin_unlock_irqrestore(&host->lock, flags);
3000 return true;
3001 }
3002
3003 /*
3004 * The controller needs a reset of internal state machines
3005 * upon error conditions.
3006 */
3007 if (sdhci_needs_reset(host, mrq)) {
3008 /*
3009 * Do not finish until command and data lines are available for
3010 * reset. Note there can only be one other mrq, so it cannot
3011 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3012 * would both be null.
3013 */
3014 if (host->cmd || host->data_cmd) {
3015 spin_unlock_irqrestore(&host->lock, flags);
3016 return true;
3017 }
3018
3019 /* Some controllers need this kick or reset won't work here */
3020 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3021 /* This is to force an update */
3022 host->ops->set_clock(host, host->clock);
3023
3024 /*
3025 * Spec says we should do both at the same time, but Ricoh
3026 * controllers do not like that.
3027 */
3028 sdhci_do_reset(host, SDHCI_RESET_CMD);
3029 sdhci_do_reset(host, SDHCI_RESET_DATA);
3030
3031 host->pending_reset = false;
3032 }
3033
3034 /*
3035 * Always unmap the data buffers if they were mapped by
3036 * sdhci_prepare_data() whenever we finish with a request.
3037 * This avoids leaking DMA mappings on error.
3038 */
3039 if (host->flags & SDHCI_REQ_USE_DMA) {
3040 struct mmc_data *data = mrq->data;
3041
3042 if (host->use_external_dma && data &&
3043 (mrq->cmd->error || data->error)) {
3044 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3045
3046 host->mrqs_done[i] = NULL;
3047 spin_unlock_irqrestore(&host->lock, flags);
3048 dmaengine_terminate_sync(chan);
3049 spin_lock_irqsave(&host->lock, flags);
3050 sdhci_set_mrq_done(host, mrq);
3051 }
3052
3053 if (data && data->host_cookie == COOKIE_MAPPED) {
3054 if (host->bounce_buffer) {
3055 /*
3056 * On reads, copy the bounced data into the
3057 * sglist
3058 */
3059 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3060 unsigned int length = data->bytes_xfered;
3061
3062 if (length > host->bounce_buffer_size) {
3063 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3064 mmc_hostname(host->mmc),
3065 host->bounce_buffer_size,
3066 data->bytes_xfered);
3067 /* Cap it down and continue */
3068 length = host->bounce_buffer_size;
3069 }
3070 dma_sync_single_for_cpu(
3071 mmc_dev(host->mmc),
3072 host->bounce_addr,
3073 host->bounce_buffer_size,
3074 DMA_FROM_DEVICE);
3075 sg_copy_from_buffer(data->sg,
3076 data->sg_len,
3077 host->bounce_buffer,
3078 length);
3079 } else {
3080 /* No copying, just switch ownership */
3081 dma_sync_single_for_cpu(
3082 mmc_dev(host->mmc),
3083 host->bounce_addr,
3084 host->bounce_buffer_size,
3085 mmc_get_dma_dir(data));
3086 }
3087 } else {
3088 /* Unmap the raw data */
3089 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3090 data->sg_len,
3091 mmc_get_dma_dir(data));
3092 }
3093 data->host_cookie = COOKIE_UNMAPPED;
3094 }
3095 }
3096
3097 host->mrqs_done[i] = NULL;
3098
3099 spin_unlock_irqrestore(&host->lock, flags);
3100
3101 if (host->ops->request_done)
3102 host->ops->request_done(host, mrq);
3103 else
3104 mmc_request_done(host->mmc, mrq);
3105
3106 return false;
3107}
3108
3109static void sdhci_complete_work(struct work_struct *work)
3110{
3111 struct sdhci_host *host = container_of(work, struct sdhci_host,
3112 complete_work);
3113
3114 while (!sdhci_request_done(host))
3115 ;
3116}
3117
3118static void sdhci_timeout_timer(struct timer_list *t)
3119{
3120 struct sdhci_host *host;
3121 unsigned long flags;
3122
3123 host = from_timer(host, t, timer);
3124
3125 spin_lock_irqsave(&host->lock, flags);
3126
3127 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3128 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3129 mmc_hostname(host->mmc));
3130 sdhci_dumpregs(host);
3131
3132 host->cmd->error = -ETIMEDOUT;
3133 sdhci_finish_mrq(host, host->cmd->mrq);
3134 }
3135
3136 spin_unlock_irqrestore(&host->lock, flags);
3137}
3138
3139static void sdhci_timeout_data_timer(struct timer_list *t)
3140{
3141 struct sdhci_host *host;
3142 unsigned long flags;
3143
3144 host = from_timer(host, t, data_timer);
3145
3146 spin_lock_irqsave(&host->lock, flags);
3147
3148 if (host->data || host->data_cmd ||
3149 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3150 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3151 mmc_hostname(host->mmc));
3152 sdhci_dumpregs(host);
3153
3154 if (host->data) {
3155 host->data->error = -ETIMEDOUT;
3156 __sdhci_finish_data(host, true);
3157 queue_work(host->complete_wq, &host->complete_work);
3158 } else if (host->data_cmd) {
3159 host->data_cmd->error = -ETIMEDOUT;
3160 sdhci_finish_mrq(host, host->data_cmd->mrq);
3161 } else {
3162 host->cmd->error = -ETIMEDOUT;
3163 sdhci_finish_mrq(host, host->cmd->mrq);
3164 }
3165 }
3166
3167 spin_unlock_irqrestore(&host->lock, flags);
3168}
3169
3170/*****************************************************************************\
3171 * *
3172 * Interrupt handling *
3173 * *
3174\*****************************************************************************/
3175
3176static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3177{
3178 /* Handle auto-CMD12 error */
3179 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3180 struct mmc_request *mrq = host->data_cmd->mrq;
3181 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3182 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3183 SDHCI_INT_DATA_TIMEOUT :
3184 SDHCI_INT_DATA_CRC;
3185
3186 /* Treat auto-CMD12 error the same as data error */
3187 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3188 *intmask_p |= data_err_bit;
3189 return;
3190 }
3191 }
3192
3193 if (!host->cmd) {
3194 /*
3195 * SDHCI recovers from errors by resetting the cmd and data
3196 * circuits. Until that is done, there very well might be more
3197 * interrupts, so ignore them in that case.
3198 */
3199 if (host->pending_reset)
3200 return;
3201 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3202 mmc_hostname(host->mmc), (unsigned)intmask);
3203 sdhci_dumpregs(host);
3204 return;
3205 }
3206
3207 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3208 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3209 if (intmask & SDHCI_INT_TIMEOUT)
3210 host->cmd->error = -ETIMEDOUT;
3211 else
3212 host->cmd->error = -EILSEQ;
3213
3214 /* Treat data command CRC error the same as data CRC error */
3215 if (host->cmd->data &&
3216 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3217 SDHCI_INT_CRC) {
3218 host->cmd = NULL;
3219 *intmask_p |= SDHCI_INT_DATA_CRC;
3220 return;
3221 }
3222
3223 __sdhci_finish_mrq(host, host->cmd->mrq);
3224 return;
3225 }
3226
3227 /* Handle auto-CMD23 error */
3228 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3229 struct mmc_request *mrq = host->cmd->mrq;
3230 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3231 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3232 -ETIMEDOUT :
3233 -EILSEQ;
3234
3235 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3236 mrq->sbc->error = err;
3237 __sdhci_finish_mrq(host, mrq);
3238 return;
3239 }
3240 }
3241
3242 if (intmask & SDHCI_INT_RESPONSE)
3243 sdhci_finish_command(host);
3244}
3245
3246static void sdhci_adma_show_error(struct sdhci_host *host)
3247{
3248 void *desc = host->adma_table;
3249 dma_addr_t dma = host->adma_addr;
3250
3251 sdhci_dumpregs(host);
3252
3253 while (true) {
3254 struct sdhci_adma2_64_desc *dma_desc = desc;
3255
3256 if (host->flags & SDHCI_USE_64_BIT_DMA)
3257 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3258 (unsigned long long)dma,
3259 le32_to_cpu(dma_desc->addr_hi),
3260 le32_to_cpu(dma_desc->addr_lo),
3261 le16_to_cpu(dma_desc->len),
3262 le16_to_cpu(dma_desc->cmd));
3263 else
3264 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3265 (unsigned long long)dma,
3266 le32_to_cpu(dma_desc->addr_lo),
3267 le16_to_cpu(dma_desc->len),
3268 le16_to_cpu(dma_desc->cmd));
3269
3270 desc += host->desc_sz;
3271 dma += host->desc_sz;
3272
3273 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3274 break;
3275 }
3276}
3277
3278static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3279{
3280 u32 command;
3281
3282 /* CMD19 generates _only_ Buffer Read Ready interrupt */
3283 if (intmask & SDHCI_INT_DATA_AVAIL) {
3284 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3285 if (command == MMC_SEND_TUNING_BLOCK ||
3286 command == MMC_SEND_TUNING_BLOCK_HS200) {
3287 host->tuning_done = 1;
3288 wake_up(&host->buf_ready_int);
3289 return;
3290 }
3291 }
3292
3293 if (!host->data) {
3294 struct mmc_command *data_cmd = host->data_cmd;
3295
3296 /*
3297 * The "data complete" interrupt is also used to
3298 * indicate that a busy state has ended. See comment
3299 * above in sdhci_cmd_irq().
3300 */
3301 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3302 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3303 host->data_cmd = NULL;
3304 data_cmd->error = -ETIMEDOUT;
3305 __sdhci_finish_mrq(host, data_cmd->mrq);
3306 return;
3307 }
3308 if (intmask & SDHCI_INT_DATA_END) {
3309 host->data_cmd = NULL;
3310 /*
3311 * Some cards handle busy-end interrupt
3312 * before the command completed, so make
3313 * sure we do things in the proper order.
3314 */
3315 if (host->cmd == data_cmd)
3316 return;
3317
3318 __sdhci_finish_mrq(host, data_cmd->mrq);
3319 return;
3320 }
3321 }
3322
3323 /*
3324 * SDHCI recovers from errors by resetting the cmd and data
3325 * circuits. Until that is done, there very well might be more
3326 * interrupts, so ignore them in that case.
3327 */
3328 if (host->pending_reset)
3329 return;
3330
3331 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3332 mmc_hostname(host->mmc), (unsigned)intmask);
3333 sdhci_dumpregs(host);
3334
3335 return;
3336 }
3337
3338 if (intmask & SDHCI_INT_DATA_TIMEOUT)
3339 host->data->error = -ETIMEDOUT;
3340 else if (intmask & SDHCI_INT_DATA_END_BIT)
3341 host->data->error = -EILSEQ;
3342 else if ((intmask & SDHCI_INT_DATA_CRC) &&
3343 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3344 != MMC_BUS_TEST_R)
3345 host->data->error = -EILSEQ;
3346 else if (intmask & SDHCI_INT_ADMA_ERROR) {
3347 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3348 intmask);
3349 sdhci_adma_show_error(host);
3350 host->data->error = -EIO;
3351 if (host->ops->adma_workaround)
3352 host->ops->adma_workaround(host, intmask);
3353 }
3354
3355 if (host->data->error)
3356 sdhci_finish_data(host);
3357 else {
3358 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3359 sdhci_transfer_pio(host);
3360
3361 /*
3362 * We currently don't do anything fancy with DMA
3363 * boundaries, but as we can't disable the feature
3364 * we need to at least restart the transfer.
3365 *
3366 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3367 * should return a valid address to continue from, but as
3368 * some controllers are faulty, don't trust them.
3369 */
3370 if (intmask & SDHCI_INT_DMA_END) {
3371 dma_addr_t dmastart, dmanow;
3372
3373 dmastart = sdhci_sdma_address(host);
3374 dmanow = dmastart + host->data->bytes_xfered;
3375 /*
3376 * Force update to the next DMA block boundary.
3377 */
3378 dmanow = (dmanow &
3379 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3380 SDHCI_DEFAULT_BOUNDARY_SIZE;
3381 host->data->bytes_xfered = dmanow - dmastart;
3382 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3383 &dmastart, host->data->bytes_xfered, &dmanow);
3384 sdhci_set_sdma_addr(host, dmanow);
3385 }
3386
3387 if (intmask & SDHCI_INT_DATA_END) {
3388 if (host->cmd == host->data_cmd) {
3389 /*
3390 * Data managed to finish before the
3391 * command completed. Make sure we do
3392 * things in the proper order.
3393 */
3394 host->data_early = 1;
3395 } else {
3396 sdhci_finish_data(host);
3397 }
3398 }
3399 }
3400}
3401
3402static inline bool sdhci_defer_done(struct sdhci_host *host,
3403 struct mmc_request *mrq)
3404{
3405 struct mmc_data *data = mrq->data;
3406
3407 return host->pending_reset || host->always_defer_done ||
3408 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3409 data->host_cookie == COOKIE_MAPPED);
3410}
3411
3412static irqreturn_t sdhci_irq(int irq, void *dev_id)
3413{
3414 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3415 irqreturn_t result = IRQ_NONE;
3416 struct sdhci_host *host = dev_id;
3417 u32 intmask, mask, unexpected = 0;
3418 int max_loops = 16;
3419 int i;
3420
3421 spin_lock(&host->lock);
3422
3423 if (host->runtime_suspended) {
3424 spin_unlock(&host->lock);
3425 return IRQ_NONE;
3426 }
3427
3428 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3429 if (!intmask || intmask == 0xffffffff) {
3430 result = IRQ_NONE;
3431 goto out;
3432 }
3433
3434 do {
3435 DBG("IRQ status 0x%08x\n", intmask);
3436
3437 if (host->ops->irq) {
3438 intmask = host->ops->irq(host, intmask);
3439 if (!intmask)
3440 goto cont;
3441 }
3442
3443 /* Clear selected interrupts. */
3444 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3445 SDHCI_INT_BUS_POWER);
3446 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3447
3448 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3449 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3450 SDHCI_CARD_PRESENT;
3451
3452 /*
3453 * There is a observation on i.mx esdhc. INSERT
3454 * bit will be immediately set again when it gets
3455 * cleared, if a card is inserted. We have to mask
3456 * the irq to prevent interrupt storm which will
3457 * freeze the system. And the REMOVE gets the
3458 * same situation.
3459 *
3460 * More testing are needed here to ensure it works
3461 * for other platforms though.
3462 */
3463 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3464 SDHCI_INT_CARD_REMOVE);
3465 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3466 SDHCI_INT_CARD_INSERT;
3467 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3468 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3469
3470 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3471 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3472
3473 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3474 SDHCI_INT_CARD_REMOVE);
3475 result = IRQ_WAKE_THREAD;
3476 }
3477
3478 if (intmask & SDHCI_INT_CMD_MASK)
3479 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3480
3481 if (intmask & SDHCI_INT_DATA_MASK)
3482 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3483
3484 if (intmask & SDHCI_INT_BUS_POWER)
3485 pr_err("%s: Card is consuming too much power!\n",
3486 mmc_hostname(host->mmc));
3487
3488 if (intmask & SDHCI_INT_RETUNE)
3489 mmc_retune_needed(host->mmc);
3490
3491 if ((intmask & SDHCI_INT_CARD_INT) &&
3492 (host->ier & SDHCI_INT_CARD_INT)) {
3493 sdhci_enable_sdio_irq_nolock(host, false);
3494 sdio_signal_irq(host->mmc);
3495 }
3496
3497 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3498 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3499 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3500 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3501
3502 if (intmask) {
3503 unexpected |= intmask;
3504 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3505 }
3506cont:
3507 if (result == IRQ_NONE)
3508 result = IRQ_HANDLED;
3509
3510 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3511 } while (intmask && --max_loops);
3512
3513 /* Determine if mrqs can be completed immediately */
3514 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3515 struct mmc_request *mrq = host->mrqs_done[i];
3516
3517 if (!mrq)
3518 continue;
3519
3520 if (sdhci_defer_done(host, mrq)) {
3521 result = IRQ_WAKE_THREAD;
3522 } else {
3523 mrqs_done[i] = mrq;
3524 host->mrqs_done[i] = NULL;
3525 }
3526 }
3527out:
3528 if (host->deferred_cmd)
3529 result = IRQ_WAKE_THREAD;
3530
3531 spin_unlock(&host->lock);
3532
3533 /* Process mrqs ready for immediate completion */
3534 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3535 if (!mrqs_done[i])
3536 continue;
3537
3538 if (host->ops->request_done)
3539 host->ops->request_done(host, mrqs_done[i]);
3540 else
3541 mmc_request_done(host->mmc, mrqs_done[i]);
3542 }
3543
3544 if (unexpected) {
3545 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3546 mmc_hostname(host->mmc), unexpected);
3547 sdhci_dumpregs(host);
3548 }
3549
3550 return result;
3551}
3552
3553static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3554{
3555 struct sdhci_host *host = dev_id;
3556 struct mmc_command *cmd;
3557 unsigned long flags;
3558 u32 isr;
3559
3560 while (!sdhci_request_done(host))
3561 ;
3562
3563 spin_lock_irqsave(&host->lock, flags);
3564
3565 isr = host->thread_isr;
3566 host->thread_isr = 0;
3567
3568 cmd = host->deferred_cmd;
3569 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3570 sdhci_finish_mrq(host, cmd->mrq);
3571
3572 spin_unlock_irqrestore(&host->lock, flags);
3573
3574 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3575 struct mmc_host *mmc = host->mmc;
3576
3577 mmc->ops->card_event(mmc);
3578 mmc_detect_change(mmc, msecs_to_jiffies(200));
3579 }
3580
3581 return IRQ_HANDLED;
3582}
3583
3584/*****************************************************************************\
3585 * *
3586 * Suspend/resume *
3587 * *
3588\*****************************************************************************/
3589
3590#ifdef CONFIG_PM
3591
3592static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3593{
3594 return mmc_card_is_removable(host->mmc) &&
3595 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3596 !mmc_can_gpio_cd(host->mmc);
3597}
3598
3599/*
3600 * To enable wakeup events, the corresponding events have to be enabled in
3601 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3602 * Table' in the SD Host Controller Standard Specification.
3603 * It is useless to restore SDHCI_INT_ENABLE state in
3604 * sdhci_disable_irq_wakeups() since it will be set by
3605 * sdhci_enable_card_detection() or sdhci_init().
3606 */
3607static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3608{
3609 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3610 SDHCI_WAKE_ON_INT;
3611 u32 irq_val = 0;
3612 u8 wake_val = 0;
3613 u8 val;
3614
3615 if (sdhci_cd_irq_can_wakeup(host)) {
3616 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3617 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3618 }
3619
3620 if (mmc_card_wake_sdio_irq(host->mmc)) {
3621 wake_val |= SDHCI_WAKE_ON_INT;
3622 irq_val |= SDHCI_INT_CARD_INT;
3623 }
3624
3625 if (!irq_val)
3626 return false;
3627
3628 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3629 val &= ~mask;
3630 val |= wake_val;
3631 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3632
3633 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3634
3635 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3636
3637 return host->irq_wake_enabled;
3638}
3639
3640static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3641{
3642 u8 val;
3643 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3644 | SDHCI_WAKE_ON_INT;
3645
3646 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3647 val &= ~mask;
3648 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3649
3650 disable_irq_wake(host->irq);
3651
3652 host->irq_wake_enabled = false;
3653}
3654
3655int sdhci_suspend_host(struct sdhci_host *host)
3656{
3657 sdhci_disable_card_detection(host);
3658
3659 mmc_retune_timer_stop(host->mmc);
3660
3661 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3662 !sdhci_enable_irq_wakeups(host)) {
3663 host->ier = 0;
3664 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3665 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3666 free_irq(host->irq, host);
3667 }
3668
3669 return 0;
3670}
3671
3672EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3673
3674int sdhci_resume_host(struct sdhci_host *host)
3675{
3676 struct mmc_host *mmc = host->mmc;
3677 int ret = 0;
3678
3679 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3680 if (host->ops->enable_dma)
3681 host->ops->enable_dma(host);
3682 }
3683
3684 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3685 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3686 /* Card keeps power but host controller does not */
3687 sdhci_init(host, 0);
3688 host->pwr = 0;
3689 host->clock = 0;
3690 mmc->ops->set_ios(mmc, &mmc->ios);
3691 } else {
3692 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3693 }
3694
3695 if (host->irq_wake_enabled) {
3696 sdhci_disable_irq_wakeups(host);
3697 } else {
3698 ret = request_threaded_irq(host->irq, sdhci_irq,
3699 sdhci_thread_irq, IRQF_SHARED,
3700 mmc_hostname(mmc), host);
3701 if (ret)
3702 return ret;
3703 }
3704
3705 sdhci_enable_card_detection(host);
3706
3707 return ret;
3708}
3709
3710EXPORT_SYMBOL_GPL(sdhci_resume_host);
3711
3712int sdhci_runtime_suspend_host(struct sdhci_host *host)
3713{
3714 unsigned long flags;
3715
3716 mmc_retune_timer_stop(host->mmc);
3717
3718 spin_lock_irqsave(&host->lock, flags);
3719 host->ier &= SDHCI_INT_CARD_INT;
3720 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3721 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3722 spin_unlock_irqrestore(&host->lock, flags);
3723
3724 synchronize_hardirq(host->irq);
3725
3726 spin_lock_irqsave(&host->lock, flags);
3727 host->runtime_suspended = true;
3728 spin_unlock_irqrestore(&host->lock, flags);
3729
3730 return 0;
3731}
3732EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3733
3734int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3735{
3736 struct mmc_host *mmc = host->mmc;
3737 unsigned long flags;
3738 int host_flags = host->flags;
3739
3740 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3741 if (host->ops->enable_dma)
3742 host->ops->enable_dma(host);
3743 }
3744
3745 sdhci_init(host, soft_reset);
3746
3747 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3748 mmc->ios.power_mode != MMC_POWER_OFF) {
3749 /* Force clock and power re-program */
3750 host->pwr = 0;
3751 host->clock = 0;
3752 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3753 mmc->ops->set_ios(mmc, &mmc->ios);
3754
3755 if ((host_flags & SDHCI_PV_ENABLED) &&
3756 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3757 spin_lock_irqsave(&host->lock, flags);
3758 sdhci_enable_preset_value(host, true);
3759 spin_unlock_irqrestore(&host->lock, flags);
3760 }
3761
3762 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3763 mmc->ops->hs400_enhanced_strobe)
3764 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3765 }
3766
3767 spin_lock_irqsave(&host->lock, flags);
3768
3769 host->runtime_suspended = false;
3770
3771 /* Enable SDIO IRQ */
3772 if (sdio_irq_claimed(mmc))
3773 sdhci_enable_sdio_irq_nolock(host, true);
3774
3775 /* Enable Card Detection */
3776 sdhci_enable_card_detection(host);
3777
3778 spin_unlock_irqrestore(&host->lock, flags);
3779
3780 return 0;
3781}
3782EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3783
3784#endif /* CONFIG_PM */
3785
3786/*****************************************************************************\
3787 * *
3788 * Command Queue Engine (CQE) helpers *
3789 * *
3790\*****************************************************************************/
3791
3792void sdhci_cqe_enable(struct mmc_host *mmc)
3793{
3794 struct sdhci_host *host = mmc_priv(mmc);
3795 unsigned long flags;
3796 u8 ctrl;
3797
3798 spin_lock_irqsave(&host->lock, flags);
3799
3800 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3801 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3802 /*
3803 * Host from V4.10 supports ADMA3 DMA type.
3804 * ADMA3 performs integrated descriptor which is more suitable
3805 * for cmd queuing to fetch both command and transfer descriptors.
3806 */
3807 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3808 ctrl |= SDHCI_CTRL_ADMA3;
3809 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3810 ctrl |= SDHCI_CTRL_ADMA64;
3811 else
3812 ctrl |= SDHCI_CTRL_ADMA32;
3813 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3814
3815 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3816 SDHCI_BLOCK_SIZE);
3817
3818 /* Set maximum timeout */
3819 sdhci_set_timeout(host, NULL);
3820
3821 host->ier = host->cqe_ier;
3822
3823 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3824 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3825
3826 host->cqe_on = true;
3827
3828 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3829 mmc_hostname(mmc), host->ier,
3830 sdhci_readl(host, SDHCI_INT_STATUS));
3831
3832 spin_unlock_irqrestore(&host->lock, flags);
3833}
3834EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3835
3836void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3837{
3838 struct sdhci_host *host = mmc_priv(mmc);
3839 unsigned long flags;
3840
3841 spin_lock_irqsave(&host->lock, flags);
3842
3843 sdhci_set_default_irqs(host);
3844
3845 host->cqe_on = false;
3846
3847 if (recovery) {
3848 sdhci_do_reset(host, SDHCI_RESET_CMD);
3849 sdhci_do_reset(host, SDHCI_RESET_DATA);
3850 }
3851
3852 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3853 mmc_hostname(mmc), host->ier,
3854 sdhci_readl(host, SDHCI_INT_STATUS));
3855
3856 spin_unlock_irqrestore(&host->lock, flags);
3857}
3858EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3859
3860bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3861 int *data_error)
3862{
3863 u32 mask;
3864
3865 if (!host->cqe_on)
3866 return false;
3867
3868 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3869 *cmd_error = -EILSEQ;
3870 else if (intmask & SDHCI_INT_TIMEOUT)
3871 *cmd_error = -ETIMEDOUT;
3872 else
3873 *cmd_error = 0;
3874
3875 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3876 *data_error = -EILSEQ;
3877 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3878 *data_error = -ETIMEDOUT;
3879 else if (intmask & SDHCI_INT_ADMA_ERROR)
3880 *data_error = -EIO;
3881 else
3882 *data_error = 0;
3883
3884 /* Clear selected interrupts. */
3885 mask = intmask & host->cqe_ier;
3886 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3887
3888 if (intmask & SDHCI_INT_BUS_POWER)
3889 pr_err("%s: Card is consuming too much power!\n",
3890 mmc_hostname(host->mmc));
3891
3892 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3893 if (intmask) {
3894 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3895 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3896 mmc_hostname(host->mmc), intmask);
3897 sdhci_dumpregs(host);
3898 }
3899
3900 return true;
3901}
3902EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3903
3904/*****************************************************************************\
3905 * *
3906 * Device allocation/registration *
3907 * *
3908\*****************************************************************************/
3909
3910struct sdhci_host *sdhci_alloc_host(struct device *dev,
3911 size_t priv_size)
3912{
3913 struct mmc_host *mmc;
3914 struct sdhci_host *host;
3915
3916 WARN_ON(dev == NULL);
3917
3918 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3919 if (!mmc)
3920 return ERR_PTR(-ENOMEM);
3921
3922 host = mmc_priv(mmc);
3923 host->mmc = mmc;
3924 host->mmc_host_ops = sdhci_ops;
3925 mmc->ops = &host->mmc_host_ops;
3926
3927 host->flags = SDHCI_SIGNALING_330;
3928
3929 host->cqe_ier = SDHCI_CQE_INT_MASK;
3930 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3931
3932 host->tuning_delay = -1;
3933 host->tuning_loop_count = MAX_TUNING_LOOP;
3934
3935 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3936
3937 /*
3938 * The DMA table descriptor count is calculated as the maximum
3939 * number of segments times 2, to allow for an alignment
3940 * descriptor for each segment, plus 1 for a nop end descriptor.
3941 */
3942 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3943
3944 return host;
3945}
3946
3947EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3948
3949static int sdhci_set_dma_mask(struct sdhci_host *host)
3950{
3951 struct mmc_host *mmc = host->mmc;
3952 struct device *dev = mmc_dev(mmc);
3953 int ret = -EINVAL;
3954
3955 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3956 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3957
3958 /* Try 64-bit mask if hardware is capable of it */
3959 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3960 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3961 if (ret) {
3962 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3963 mmc_hostname(mmc));
3964 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3965 }
3966 }
3967
3968 /* 32-bit mask as default & fallback */
3969 if (ret) {
3970 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3971 if (ret)
3972 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3973 mmc_hostname(mmc));
3974 }
3975
3976 return ret;
3977}
3978
3979void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3980 const u32 *caps, const u32 *caps1)
3981{
3982 u16 v;
3983 u64 dt_caps_mask = 0;
3984 u64 dt_caps = 0;
3985
3986 if (host->read_caps)
3987 return;
3988
3989 host->read_caps = true;
3990
3991 if (debug_quirks)
3992 host->quirks = debug_quirks;
3993
3994 if (debug_quirks2)
3995 host->quirks2 = debug_quirks2;
3996
3997 sdhci_do_reset(host, SDHCI_RESET_ALL);
3998
3999 if (host->v4_mode)
4000 sdhci_do_enable_v4_mode(host);
4001
4002 device_property_read_u64(mmc_dev(host->mmc),
4003 "sdhci-caps-mask", &dt_caps_mask);
4004 device_property_read_u64(mmc_dev(host->mmc),
4005 "sdhci-caps", &dt_caps);
4006
4007 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4008 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4009
4010 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4011 return;
4012
4013 if (caps) {
4014 host->caps = *caps;
4015 } else {
4016 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4017 host->caps &= ~lower_32_bits(dt_caps_mask);
4018 host->caps |= lower_32_bits(dt_caps);
4019 }
4020
4021 if (host->version < SDHCI_SPEC_300)
4022 return;
4023
4024 if (caps1) {
4025 host->caps1 = *caps1;
4026 } else {
4027 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4028 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4029 host->caps1 |= upper_32_bits(dt_caps);
4030 }
4031}
4032EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4033
4034static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4035{
4036 struct mmc_host *mmc = host->mmc;
4037 unsigned int max_blocks;
4038 unsigned int bounce_size;
4039 int ret;
4040
4041 /*
4042 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4043 * has diminishing returns, this is probably because SD/MMC
4044 * cards are usually optimized to handle this size of requests.
4045 */
4046 bounce_size = SZ_64K;
4047 /*
4048 * Adjust downwards to maximum request size if this is less
4049 * than our segment size, else hammer down the maximum
4050 * request size to the maximum buffer size.
4051 */
4052 if (mmc->max_req_size < bounce_size)
4053 bounce_size = mmc->max_req_size;
4054 max_blocks = bounce_size / 512;
4055
4056 /*
4057 * When we just support one segment, we can get significant
4058 * speedups by the help of a bounce buffer to group scattered
4059 * reads/writes together.
4060 */
4061 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4062 bounce_size,
4063 GFP_KERNEL);
4064 if (!host->bounce_buffer) {
4065 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4066 mmc_hostname(mmc),
4067 bounce_size);
4068 /*
4069 * Exiting with zero here makes sure we proceed with
4070 * mmc->max_segs == 1.
4071 */
4072 return;
4073 }
4074
4075 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4076 host->bounce_buffer,
4077 bounce_size,
4078 DMA_BIDIRECTIONAL);
4079 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4080 if (ret) {
4081 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4082 host->bounce_buffer = NULL;
4083 /* Again fall back to max_segs == 1 */
4084 return;
4085 }
4086
4087 host->bounce_buffer_size = bounce_size;
4088
4089 /* Lie about this since we're bouncing */
4090 mmc->max_segs = max_blocks;
4091 mmc->max_seg_size = bounce_size;
4092 mmc->max_req_size = bounce_size;
4093
4094 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4095 mmc_hostname(mmc), max_blocks, bounce_size);
4096}
4097
4098static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4099{
4100 /*
4101 * According to SD Host Controller spec v4.10, bit[27] added from
4102 * version 4.10 in Capabilities Register is used as 64-bit System
4103 * Address support for V4 mode.
4104 */
4105 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4106 return host->caps & SDHCI_CAN_64BIT_V4;
4107
4108 return host->caps & SDHCI_CAN_64BIT;
4109}
4110
4111int sdhci_setup_host(struct sdhci_host *host)
4112{
4113 struct mmc_host *mmc;
4114 u32 max_current_caps;
4115 unsigned int ocr_avail;
4116 unsigned int override_timeout_clk;
4117 u32 max_clk;
4118 int ret = 0;
4119 bool enable_vqmmc = false;
4120
4121 WARN_ON(host == NULL);
4122 if (host == NULL)
4123 return -EINVAL;
4124
4125 mmc = host->mmc;
4126
4127 /*
4128 * If there are external regulators, get them. Note this must be done
4129 * early before resetting the host and reading the capabilities so that
4130 * the host can take the appropriate action if regulators are not
4131 * available.
4132 */
4133 if (!mmc->supply.vqmmc) {
4134 ret = mmc_regulator_get_supply(mmc);
4135 if (ret)
4136 return ret;
4137 enable_vqmmc = true;
4138 }
4139
4140 DBG("Version: 0x%08x | Present: 0x%08x\n",
4141 sdhci_readw(host, SDHCI_HOST_VERSION),
4142 sdhci_readl(host, SDHCI_PRESENT_STATE));
4143 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4144 sdhci_readl(host, SDHCI_CAPABILITIES),
4145 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4146
4147 sdhci_read_caps(host);
4148
4149 override_timeout_clk = host->timeout_clk;
4150
4151 if (host->version > SDHCI_SPEC_420) {
4152 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4153 mmc_hostname(mmc), host->version);
4154 }
4155
4156 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4157 host->flags |= SDHCI_USE_SDMA;
4158 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4159 DBG("Controller doesn't have SDMA capability\n");
4160 else
4161 host->flags |= SDHCI_USE_SDMA;
4162
4163 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4164 (host->flags & SDHCI_USE_SDMA)) {
4165 DBG("Disabling DMA as it is marked broken\n");
4166 host->flags &= ~SDHCI_USE_SDMA;
4167 }
4168
4169 if ((host->version >= SDHCI_SPEC_200) &&
4170 (host->caps & SDHCI_CAN_DO_ADMA2))
4171 host->flags |= SDHCI_USE_ADMA;
4172
4173 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4174 (host->flags & SDHCI_USE_ADMA)) {
4175 DBG("Disabling ADMA as it is marked broken\n");
4176 host->flags &= ~SDHCI_USE_ADMA;
4177 }
4178
4179 if (sdhci_can_64bit_dma(host))
4180 host->flags |= SDHCI_USE_64_BIT_DMA;
4181
4182 if (host->use_external_dma) {
4183 ret = sdhci_external_dma_init(host);
4184 if (ret == -EPROBE_DEFER)
4185 goto unreg;
4186 /*
4187 * Fall back to use the DMA/PIO integrated in standard SDHCI
4188 * instead of external DMA devices.
4189 */
4190 else if (ret)
4191 sdhci_switch_external_dma(host, false);
4192 /* Disable internal DMA sources */
4193 else
4194 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4195 }
4196
4197 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4198 if (host->ops->set_dma_mask)
4199 ret = host->ops->set_dma_mask(host);
4200 else
4201 ret = sdhci_set_dma_mask(host);
4202
4203 if (!ret && host->ops->enable_dma)
4204 ret = host->ops->enable_dma(host);
4205
4206 if (ret) {
4207 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4208 mmc_hostname(mmc));
4209 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4210
4211 ret = 0;
4212 }
4213 }
4214
4215 /* SDMA does not support 64-bit DMA if v4 mode not set */
4216 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4217 host->flags &= ~SDHCI_USE_SDMA;
4218
4219 if (host->flags & SDHCI_USE_ADMA) {
4220 dma_addr_t dma;
4221 void *buf;
4222
4223 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4224 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4225 else if (!host->alloc_desc_sz)
4226 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4227
4228 host->desc_sz = host->alloc_desc_sz;
4229 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4230
4231 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4232 /*
4233 * Use zalloc to zero the reserved high 32-bits of 128-bit
4234 * descriptors so that they never need to be written.
4235 */
4236 buf = dma_alloc_coherent(mmc_dev(mmc),
4237 host->align_buffer_sz + host->adma_table_sz,
4238 &dma, GFP_KERNEL);
4239 if (!buf) {
4240 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4241 mmc_hostname(mmc));
4242 host->flags &= ~SDHCI_USE_ADMA;
4243 } else if ((dma + host->align_buffer_sz) &
4244 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4245 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4246 mmc_hostname(mmc));
4247 host->flags &= ~SDHCI_USE_ADMA;
4248 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4249 host->adma_table_sz, buf, dma);
4250 } else {
4251 host->align_buffer = buf;
4252 host->align_addr = dma;
4253
4254 host->adma_table = buf + host->align_buffer_sz;
4255 host->adma_addr = dma + host->align_buffer_sz;
4256 }
4257 }
4258
4259 /*
4260 * If we use DMA, then it's up to the caller to set the DMA
4261 * mask, but PIO does not need the hw shim so we set a new
4262 * mask here in that case.
4263 */
4264 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4265 host->dma_mask = DMA_BIT_MASK(64);
4266 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4267 }
4268
4269 if (host->version >= SDHCI_SPEC_300)
4270 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4271 else
4272 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4273
4274 host->max_clk *= 1000000;
4275 if (host->max_clk == 0 || host->quirks &
4276 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4277 if (!host->ops->get_max_clock) {
4278 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4279 mmc_hostname(mmc));
4280 ret = -ENODEV;
4281 goto undma;
4282 }
4283 host->max_clk = host->ops->get_max_clock(host);
4284 }
4285
4286 /*
4287 * In case of Host Controller v3.00, find out whether clock
4288 * multiplier is supported.
4289 */
4290 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4291
4292 /*
4293 * In case the value in Clock Multiplier is 0, then programmable
4294 * clock mode is not supported, otherwise the actual clock
4295 * multiplier is one more than the value of Clock Multiplier
4296 * in the Capabilities Register.
4297 */
4298 if (host->clk_mul)
4299 host->clk_mul += 1;
4300
4301 /*
4302 * Set host parameters.
4303 */
4304 max_clk = host->max_clk;
4305
4306 if (host->ops->get_min_clock)
4307 mmc->f_min = host->ops->get_min_clock(host);
4308 else if (host->version >= SDHCI_SPEC_300) {
4309 if (host->clk_mul)
4310 max_clk = host->max_clk * host->clk_mul;
4311 /*
4312 * Divided Clock Mode minimum clock rate is always less than
4313 * Programmable Clock Mode minimum clock rate.
4314 */
4315 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4316 } else
4317 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4318
4319 if (!mmc->f_max || mmc->f_max > max_clk)
4320 mmc->f_max = max_clk;
4321
4322 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4323 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4324
4325 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4326 host->timeout_clk *= 1000;
4327
4328 if (host->timeout_clk == 0) {
4329 if (!host->ops->get_timeout_clock) {
4330 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4331 mmc_hostname(mmc));
4332 ret = -ENODEV;
4333 goto undma;
4334 }
4335
4336 host->timeout_clk =
4337 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4338 1000);
4339 }
4340
4341 if (override_timeout_clk)
4342 host->timeout_clk = override_timeout_clk;
4343
4344 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4345 host->ops->get_max_timeout_count(host) : 1 << 27;
4346 mmc->max_busy_timeout /= host->timeout_clk;
4347 }
4348
4349 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4350 !host->ops->get_max_timeout_count)
4351 mmc->max_busy_timeout = 0;
4352
4353 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4354 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4355
4356 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4357 host->flags |= SDHCI_AUTO_CMD12;
4358
4359 /*
4360 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4361 * For v4 mode, SDMA may use Auto-CMD23 as well.
4362 */
4363 if ((host->version >= SDHCI_SPEC_300) &&
4364 ((host->flags & SDHCI_USE_ADMA) ||
4365 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4366 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4367 host->flags |= SDHCI_AUTO_CMD23;
4368 DBG("Auto-CMD23 available\n");
4369 } else {
4370 DBG("Auto-CMD23 unavailable\n");
4371 }
4372
4373 /*
4374 * A controller may support 8-bit width, but the board itself
4375 * might not have the pins brought out. Boards that support
4376 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4377 * their platform code before calling sdhci_add_host(), and we
4378 * won't assume 8-bit width for hosts without that CAP.
4379 */
4380 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4381 mmc->caps |= MMC_CAP_4_BIT_DATA;
4382
4383 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4384 mmc->caps &= ~MMC_CAP_CMD23;
4385
4386 if (host->caps & SDHCI_CAN_DO_HISPD)
4387 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4388
4389 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4390 mmc_card_is_removable(mmc) &&
4391 mmc_gpio_get_cd(mmc) < 0)
4392 mmc->caps |= MMC_CAP_NEEDS_POLL;
4393
4394 if (!IS_ERR(mmc->supply.vqmmc)) {
4395 if (enable_vqmmc) {
4396 ret = regulator_enable(mmc->supply.vqmmc);
4397 host->sdhci_core_to_disable_vqmmc = !ret;
4398 }
4399
4400 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4401 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4402 1950000))
4403 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4404 SDHCI_SUPPORT_SDR50 |
4405 SDHCI_SUPPORT_DDR50);
4406
4407 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4408 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4409 3600000))
4410 host->flags &= ~SDHCI_SIGNALING_330;
4411
4412 if (ret) {
4413 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4414 mmc_hostname(mmc), ret);
4415 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4416 }
4417
4418 }
4419
4420 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4421 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4422 SDHCI_SUPPORT_DDR50);
4423 /*
4424 * The SDHCI controller in a SoC might support HS200/HS400
4425 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4426 * but if the board is modeled such that the IO lines are not
4427 * connected to 1.8v then HS200/HS400 cannot be supported.
4428 * Disable HS200/HS400 if the board does not have 1.8v connected
4429 * to the IO lines. (Applicable for other modes in 1.8v)
4430 */
4431 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4432 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4433 }
4434
4435 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4436 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4437 SDHCI_SUPPORT_DDR50))
4438 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4439
4440 /* SDR104 supports also implies SDR50 support */
4441 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4442 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4443 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4444 * field can be promoted to support HS200.
4445 */
4446 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4447 mmc->caps2 |= MMC_CAP2_HS200;
4448 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4449 mmc->caps |= MMC_CAP_UHS_SDR50;
4450 }
4451
4452 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4453 (host->caps1 & SDHCI_SUPPORT_HS400))
4454 mmc->caps2 |= MMC_CAP2_HS400;
4455
4456 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4457 (IS_ERR(mmc->supply.vqmmc) ||
4458 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4459 1300000)))
4460 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4461
4462 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4463 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4464 mmc->caps |= MMC_CAP_UHS_DDR50;
4465
4466 /* Does the host need tuning for SDR50? */
4467 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4468 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4469
4470 /* Driver Type(s) (A, C, D) supported by the host */
4471 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4472 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4473 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4474 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4475 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4476 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4477
4478 /* Initial value for re-tuning timer count */
4479 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4480 host->caps1);
4481
4482 /*
4483 * In case Re-tuning Timer is not disabled, the actual value of
4484 * re-tuning timer will be 2 ^ (n - 1).
4485 */
4486 if (host->tuning_count)
4487 host->tuning_count = 1 << (host->tuning_count - 1);
4488
4489 /* Re-tuning mode supported by the Host Controller */
4490 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4491
4492 ocr_avail = 0;
4493
4494 /*
4495 * According to SD Host Controller spec v3.00, if the Host System
4496 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4497 * the value is meaningful only if Voltage Support in the Capabilities
4498 * register is set. The actual current value is 4 times the register
4499 * value.
4500 */
4501 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4502 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4503 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4504 if (curr > 0) {
4505
4506 /* convert to SDHCI_MAX_CURRENT format */
4507 curr = curr/1000; /* convert to mA */
4508 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4509
4510 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4511 max_current_caps =
4512 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4513 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4514 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4515 }
4516 }
4517
4518 if (host->caps & SDHCI_CAN_VDD_330) {
4519 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4520
4521 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4522 max_current_caps) *
4523 SDHCI_MAX_CURRENT_MULTIPLIER;
4524 }
4525 if (host->caps & SDHCI_CAN_VDD_300) {
4526 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4527
4528 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4529 max_current_caps) *
4530 SDHCI_MAX_CURRENT_MULTIPLIER;
4531 }
4532 if (host->caps & SDHCI_CAN_VDD_180) {
4533 ocr_avail |= MMC_VDD_165_195;
4534
4535 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4536 max_current_caps) *
4537 SDHCI_MAX_CURRENT_MULTIPLIER;
4538 }
4539
4540 /* If OCR set by host, use it instead. */
4541 if (host->ocr_mask)
4542 ocr_avail = host->ocr_mask;
4543
4544 /* If OCR set by external regulators, give it highest prio. */
4545 if (mmc->ocr_avail)
4546 ocr_avail = mmc->ocr_avail;
4547
4548 mmc->ocr_avail = ocr_avail;
4549 mmc->ocr_avail_sdio = ocr_avail;
4550 if (host->ocr_avail_sdio)
4551 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4552 mmc->ocr_avail_sd = ocr_avail;
4553 if (host->ocr_avail_sd)
4554 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4555 else /* normal SD controllers don't support 1.8V */
4556 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4557 mmc->ocr_avail_mmc = ocr_avail;
4558 if (host->ocr_avail_mmc)
4559 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4560
4561 if (mmc->ocr_avail == 0) {
4562 pr_err("%s: Hardware doesn't report any support voltages.\n",
4563 mmc_hostname(mmc));
4564 ret = -ENODEV;
4565 goto unreg;
4566 }
4567
4568 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4569 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4570 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4571 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4572 host->flags |= SDHCI_SIGNALING_180;
4573
4574 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4575 host->flags |= SDHCI_SIGNALING_120;
4576
4577 spin_lock_init(&host->lock);
4578
4579 /*
4580 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4581 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4582 * is less anyway.
4583 */
4584 mmc->max_req_size = 524288;
4585
4586 /*
4587 * Maximum number of segments. Depends on if the hardware
4588 * can do scatter/gather or not.
4589 */
4590 if (host->flags & SDHCI_USE_ADMA) {
4591 mmc->max_segs = SDHCI_MAX_SEGS;
4592 } else if (host->flags & SDHCI_USE_SDMA) {
4593 mmc->max_segs = 1;
4594 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4595 dma_max_mapping_size(mmc_dev(mmc)));
4596 } else { /* PIO */
4597 mmc->max_segs = SDHCI_MAX_SEGS;
4598 }
4599
4600 /*
4601 * Maximum segment size. Could be one segment with the maximum number
4602 * of bytes. When doing hardware scatter/gather, each entry cannot
4603 * be larger than 64 KiB though.
4604 */
4605 if (host->flags & SDHCI_USE_ADMA) {
4606 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4607 mmc->max_seg_size = 65535;
4608 else
4609 mmc->max_seg_size = 65536;
4610 } else {
4611 mmc->max_seg_size = mmc->max_req_size;
4612 }
4613
4614 /*
4615 * Maximum block size. This varies from controller to controller and
4616 * is specified in the capabilities register.
4617 */
4618 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4619 mmc->max_blk_size = 2;
4620 } else {
4621 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4622 SDHCI_MAX_BLOCK_SHIFT;
4623 if (mmc->max_blk_size >= 3) {
4624 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4625 mmc_hostname(mmc));
4626 mmc->max_blk_size = 0;
4627 }
4628 }
4629
4630 mmc->max_blk_size = 512 << mmc->max_blk_size;
4631
4632 /*
4633 * Maximum block count.
4634 */
4635 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4636
4637 if (mmc->max_segs == 1)
4638 /* This may alter mmc->*_blk_* parameters */
4639 sdhci_allocate_bounce_buffer(host);
4640
4641 return 0;
4642
4643unreg:
4644 if (host->sdhci_core_to_disable_vqmmc)
4645 regulator_disable(mmc->supply.vqmmc);
4646undma:
4647 if (host->align_buffer)
4648 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4649 host->adma_table_sz, host->align_buffer,
4650 host->align_addr);
4651 host->adma_table = NULL;
4652 host->align_buffer = NULL;
4653
4654 return ret;
4655}
4656EXPORT_SYMBOL_GPL(sdhci_setup_host);
4657
4658void sdhci_cleanup_host(struct sdhci_host *host)
4659{
4660 struct mmc_host *mmc = host->mmc;
4661
4662 if (host->sdhci_core_to_disable_vqmmc)
4663 regulator_disable(mmc->supply.vqmmc);
4664
4665 if (host->align_buffer)
4666 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4667 host->adma_table_sz, host->align_buffer,
4668 host->align_addr);
4669
4670 if (host->use_external_dma)
4671 sdhci_external_dma_release(host);
4672
4673 host->adma_table = NULL;
4674 host->align_buffer = NULL;
4675}
4676EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4677
4678int __sdhci_add_host(struct sdhci_host *host)
4679{
4680 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4681 struct mmc_host *mmc = host->mmc;
4682 int ret;
4683
4684 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4685 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4686 mmc->caps2 &= ~MMC_CAP2_CQE;
4687 mmc->cqe_ops = NULL;
4688 }
4689
4690 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4691 if (!host->complete_wq)
4692 return -ENOMEM;
4693
4694 INIT_WORK(&host->complete_work, sdhci_complete_work);
4695
4696 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4697 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4698
4699 init_waitqueue_head(&host->buf_ready_int);
4700
4701 sdhci_init(host, 0);
4702
4703 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4704 IRQF_SHARED, mmc_hostname(mmc), host);
4705 if (ret) {
4706 pr_err("%s: Failed to request IRQ %d: %d\n",
4707 mmc_hostname(mmc), host->irq, ret);
4708 goto unwq;
4709 }
4710
4711 ret = sdhci_led_register(host);
4712 if (ret) {
4713 pr_err("%s: Failed to register LED device: %d\n",
4714 mmc_hostname(mmc), ret);
4715 goto unirq;
4716 }
4717
4718 ret = mmc_add_host(mmc);
4719 if (ret)
4720 goto unled;
4721
4722 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4723 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4724 host->use_external_dma ? "External DMA" :
4725 (host->flags & SDHCI_USE_ADMA) ?
4726 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4727 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4728
4729 sdhci_enable_card_detection(host);
4730
4731 return 0;
4732
4733unled:
4734 sdhci_led_unregister(host);
4735unirq:
4736 sdhci_do_reset(host, SDHCI_RESET_ALL);
4737 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4738 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4739 free_irq(host->irq, host);
4740unwq:
4741 destroy_workqueue(host->complete_wq);
4742
4743 return ret;
4744}
4745EXPORT_SYMBOL_GPL(__sdhci_add_host);
4746
4747int sdhci_add_host(struct sdhci_host *host)
4748{
4749 int ret;
4750
4751 ret = sdhci_setup_host(host);
4752 if (ret)
4753 return ret;
4754
4755 ret = __sdhci_add_host(host);
4756 if (ret)
4757 goto cleanup;
4758
4759 return 0;
4760
4761cleanup:
4762 sdhci_cleanup_host(host);
4763
4764 return ret;
4765}
4766EXPORT_SYMBOL_GPL(sdhci_add_host);
4767
4768void sdhci_remove_host(struct sdhci_host *host, int dead)
4769{
4770 struct mmc_host *mmc = host->mmc;
4771 unsigned long flags;
4772
4773 if (dead) {
4774 spin_lock_irqsave(&host->lock, flags);
4775
4776 host->flags |= SDHCI_DEVICE_DEAD;
4777
4778 if (sdhci_has_requests(host)) {
4779 pr_err("%s: Controller removed during "
4780 " transfer!\n", mmc_hostname(mmc));
4781 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4782 }
4783
4784 spin_unlock_irqrestore(&host->lock, flags);
4785 }
4786
4787 sdhci_disable_card_detection(host);
4788
4789 mmc_remove_host(mmc);
4790
4791 sdhci_led_unregister(host);
4792
4793 if (!dead)
4794 sdhci_do_reset(host, SDHCI_RESET_ALL);
4795
4796 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4797 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4798 free_irq(host->irq, host);
4799
4800 del_timer_sync(&host->timer);
4801 del_timer_sync(&host->data_timer);
4802
4803 destroy_workqueue(host->complete_wq);
4804
4805 if (host->sdhci_core_to_disable_vqmmc)
4806 regulator_disable(mmc->supply.vqmmc);
4807
4808 if (host->align_buffer)
4809 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4810 host->adma_table_sz, host->align_buffer,
4811 host->align_addr);
4812
4813 if (host->use_external_dma)
4814 sdhci_external_dma_release(host);
4815
4816 host->adma_table = NULL;
4817 host->align_buffer = NULL;
4818}
4819
4820EXPORT_SYMBOL_GPL(sdhci_remove_host);
4821
4822void sdhci_free_host(struct sdhci_host *host)
4823{
4824 mmc_free_host(host->mmc);
4825}
4826
4827EXPORT_SYMBOL_GPL(sdhci_free_host);
4828
4829/*****************************************************************************\
4830 * *
4831 * Driver init/exit *
4832 * *
4833\*****************************************************************************/
4834
4835static int __init sdhci_drv_init(void)
4836{
4837 pr_info(DRIVER_NAME
4838 ": Secure Digital Host Controller Interface driver\n");
4839 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4840
4841 return 0;
4842}
4843
4844static void __exit sdhci_drv_exit(void)
4845{
4846}
4847
4848module_init(sdhci_drv_init);
4849module_exit(sdhci_drv_exit);
4850
4851module_param(debug_quirks, uint, 0444);
4852module_param(debug_quirks2, uint, 0444);
4853
4854MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4855MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4856MODULE_LICENSE("GPL");
4857
4858MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4859MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");