Loading...
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/ktime.h>
18#include <linux/highmem.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/dma-mapping.h>
22#include <linux/slab.h>
23#include <linux/scatterlist.h>
24#include <linux/sizes.h>
25#include <linux/swiotlb.h>
26#include <linux/regulator/consumer.h>
27#include <linux/pm_runtime.h>
28#include <linux/of.h>
29
30#include <linux/leds.h>
31
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/card.h>
35#include <linux/mmc/sdio.h>
36#include <linux/mmc/slot-gpio.h>
37
38#include "sdhci.h"
39
40#define DRIVER_NAME "sdhci"
41
42#define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48#define MAX_TUNING_LOOP 40
49
50static unsigned int debug_quirks = 0;
51static unsigned int debug_quirks2;
52
53static void sdhci_finish_data(struct sdhci_host *);
54
55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57void sdhci_dumpregs(struct sdhci_host *host)
58{
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_ACMD12_ERR),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127{
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
129}
130
131static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
132{
133 u32 present;
134
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
137 return;
138
139 if (enable) {
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT;
142
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
145 } else {
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
147 }
148
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
151}
152
153static void sdhci_enable_card_detection(struct sdhci_host *host)
154{
155 sdhci_set_card_detection(host, true);
156}
157
158static void sdhci_disable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, false);
161}
162
163static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
164{
165 if (host->bus_on)
166 return;
167 host->bus_on = true;
168 pm_runtime_get_noresume(host->mmc->parent);
169}
170
171static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
172{
173 if (!host->bus_on)
174 return;
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
177}
178
179void sdhci_reset(struct sdhci_host *host, u8 mask)
180{
181 ktime_t timeout;
182
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184
185 if (mask & SDHCI_RESET_ALL) {
186 host->clock = 0;
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
190 }
191
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
194
195 /* hw clears the bit when it's done */
196 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 if (ktime_after(ktime_get(), timeout)) {
198 pr_err("%s: Reset 0x%x never completed.\n",
199 mmc_hostname(host->mmc), (int)mask);
200 sdhci_dumpregs(host);
201 return;
202 }
203 udelay(10);
204 }
205}
206EXPORT_SYMBOL_GPL(sdhci_reset);
207
208static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
209{
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 struct mmc_host *mmc = host->mmc;
212
213 if (!mmc->ops->get_cd(mmc))
214 return;
215 }
216
217 host->ops->reset(host, mask);
218
219 if (mask & SDHCI_RESET_ALL) {
220 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
221 if (host->ops->enable_dma)
222 host->ops->enable_dma(host);
223 }
224
225 /* Resetting the controller clears many */
226 host->preset_enabled = false;
227 }
228}
229
230static void sdhci_set_default_irqs(struct sdhci_host *host)
231{
232 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
233 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
234 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
235 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
236 SDHCI_INT_RESPONSE;
237
238 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
239 host->tuning_mode == SDHCI_TUNING_MODE_3)
240 host->ier |= SDHCI_INT_RETUNE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
244}
245
246static void sdhci_init(struct sdhci_host *host, int soft)
247{
248 struct mmc_host *mmc = host->mmc;
249
250 if (soft)
251 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
252 else
253 sdhci_do_reset(host, SDHCI_RESET_ALL);
254
255 sdhci_set_default_irqs(host);
256
257 host->cqe_on = false;
258
259 if (soft) {
260 /* force clock reconfiguration */
261 host->clock = 0;
262 mmc->ops->set_ios(mmc, &mmc->ios);
263 }
264}
265
266static void sdhci_reinit(struct sdhci_host *host)
267{
268 sdhci_init(host, 0);
269 sdhci_enable_card_detection(host);
270}
271
272static void __sdhci_led_activate(struct sdhci_host *host)
273{
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl |= SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279}
280
281static void __sdhci_led_deactivate(struct sdhci_host *host)
282{
283 u8 ctrl;
284
285 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
286 ctrl &= ~SDHCI_CTRL_LED;
287 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
288}
289
290#if IS_REACHABLE(CONFIG_LEDS_CLASS)
291static void sdhci_led_control(struct led_classdev *led,
292 enum led_brightness brightness)
293{
294 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
295 unsigned long flags;
296
297 spin_lock_irqsave(&host->lock, flags);
298
299 if (host->runtime_suspended)
300 goto out;
301
302 if (brightness == LED_OFF)
303 __sdhci_led_deactivate(host);
304 else
305 __sdhci_led_activate(host);
306out:
307 spin_unlock_irqrestore(&host->lock, flags);
308}
309
310static int sdhci_led_register(struct sdhci_host *host)
311{
312 struct mmc_host *mmc = host->mmc;
313
314 snprintf(host->led_name, sizeof(host->led_name),
315 "%s::", mmc_hostname(mmc));
316
317 host->led.name = host->led_name;
318 host->led.brightness = LED_OFF;
319 host->led.default_trigger = mmc_hostname(mmc);
320 host->led.brightness_set = sdhci_led_control;
321
322 return led_classdev_register(mmc_dev(mmc), &host->led);
323}
324
325static void sdhci_led_unregister(struct sdhci_host *host)
326{
327 led_classdev_unregister(&host->led);
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332}
333
334static inline void sdhci_led_deactivate(struct sdhci_host *host)
335{
336}
337
338#else
339
340static inline int sdhci_led_register(struct sdhci_host *host)
341{
342 return 0;
343}
344
345static inline void sdhci_led_unregister(struct sdhci_host *host)
346{
347}
348
349static inline void sdhci_led_activate(struct sdhci_host *host)
350{
351 __sdhci_led_activate(host);
352}
353
354static inline void sdhci_led_deactivate(struct sdhci_host *host)
355{
356 __sdhci_led_deactivate(host);
357}
358
359#endif
360
361/*****************************************************************************\
362 * *
363 * Core functions *
364 * *
365\*****************************************************************************/
366
367static void sdhci_read_block_pio(struct sdhci_host *host)
368{
369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 uninitialized_var(scratch);
372 u8 *buf;
373
374 DBG("PIO reading\n");
375
376 blksize = host->data->blksz;
377 chunk = 0;
378
379 local_irq_save(flags);
380
381 while (blksize) {
382 BUG_ON(!sg_miter_next(&host->sg_miter));
383
384 len = min(host->sg_miter.length, blksize);
385
386 blksize -= len;
387 host->sg_miter.consumed = len;
388
389 buf = host->sg_miter.addr;
390
391 while (len) {
392 if (chunk == 0) {
393 scratch = sdhci_readl(host, SDHCI_BUFFER);
394 chunk = 4;
395 }
396
397 *buf = scratch & 0xFF;
398
399 buf++;
400 scratch >>= 8;
401 chunk--;
402 len--;
403 }
404 }
405
406 sg_miter_stop(&host->sg_miter);
407
408 local_irq_restore(flags);
409}
410
411static void sdhci_write_block_pio(struct sdhci_host *host)
412{
413 unsigned long flags;
414 size_t blksize, len, chunk;
415 u32 scratch;
416 u8 *buf;
417
418 DBG("PIO writing\n");
419
420 blksize = host->data->blksz;
421 chunk = 0;
422 scratch = 0;
423
424 local_irq_save(flags);
425
426 while (blksize) {
427 BUG_ON(!sg_miter_next(&host->sg_miter));
428
429 len = min(host->sg_miter.length, blksize);
430
431 blksize -= len;
432 host->sg_miter.consumed = len;
433
434 buf = host->sg_miter.addr;
435
436 while (len) {
437 scratch |= (u32)*buf << (chunk * 8);
438
439 buf++;
440 chunk++;
441 len--;
442
443 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
444 sdhci_writel(host, scratch, SDHCI_BUFFER);
445 chunk = 0;
446 scratch = 0;
447 }
448 }
449 }
450
451 sg_miter_stop(&host->sg_miter);
452
453 local_irq_restore(flags);
454}
455
456static void sdhci_transfer_pio(struct sdhci_host *host)
457{
458 u32 mask;
459
460 if (host->blocks == 0)
461 return;
462
463 if (host->data->flags & MMC_DATA_READ)
464 mask = SDHCI_DATA_AVAILABLE;
465 else
466 mask = SDHCI_SPACE_AVAILABLE;
467
468 /*
469 * Some controllers (JMicron JMB38x) mess up the buffer bits
470 * for transfers < 4 bytes. As long as it is just one block,
471 * we can ignore the bits.
472 */
473 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
474 (host->data->blocks == 1))
475 mask = ~0;
476
477 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
478 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
479 udelay(100);
480
481 if (host->data->flags & MMC_DATA_READ)
482 sdhci_read_block_pio(host);
483 else
484 sdhci_write_block_pio(host);
485
486 host->blocks--;
487 if (host->blocks == 0)
488 break;
489 }
490
491 DBG("PIO transfer complete.\n");
492}
493
494static int sdhci_pre_dma_transfer(struct sdhci_host *host,
495 struct mmc_data *data, int cookie)
496{
497 int sg_count;
498
499 /*
500 * If the data buffers are already mapped, return the previous
501 * dma_map_sg() result.
502 */
503 if (data->host_cookie == COOKIE_PRE_MAPPED)
504 return data->sg_count;
505
506 /* Bounce write requests to the bounce buffer */
507 if (host->bounce_buffer) {
508 unsigned int length = data->blksz * data->blocks;
509
510 if (length > host->bounce_buffer_size) {
511 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
512 mmc_hostname(host->mmc), length,
513 host->bounce_buffer_size);
514 return -EIO;
515 }
516 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
517 /* Copy the data to the bounce buffer */
518 sg_copy_to_buffer(data->sg, data->sg_len,
519 host->bounce_buffer,
520 length);
521 }
522 /* Switch ownership to the DMA */
523 dma_sync_single_for_device(host->mmc->parent,
524 host->bounce_addr,
525 host->bounce_buffer_size,
526 mmc_get_dma_dir(data));
527 /* Just a dummy value */
528 sg_count = 1;
529 } else {
530 /* Just access the data directly from memory */
531 sg_count = dma_map_sg(mmc_dev(host->mmc),
532 data->sg, data->sg_len,
533 mmc_get_dma_dir(data));
534 }
535
536 if (sg_count == 0)
537 return -ENOSPC;
538
539 data->sg_count = sg_count;
540 data->host_cookie = cookie;
541
542 return sg_count;
543}
544
545static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
546{
547 local_irq_save(*flags);
548 return kmap_atomic(sg_page(sg)) + sg->offset;
549}
550
551static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
552{
553 kunmap_atomic(buffer);
554 local_irq_restore(*flags);
555}
556
557static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
558 dma_addr_t addr, int len, unsigned cmd)
559{
560 struct sdhci_adma2_64_desc *dma_desc = desc;
561
562 /* 32-bit and 64-bit descriptors have these members in same position */
563 dma_desc->cmd = cpu_to_le16(cmd);
564 dma_desc->len = cpu_to_le16(len);
565 dma_desc->addr_lo = cpu_to_le32((u32)addr);
566
567 if (host->flags & SDHCI_USE_64_BIT_DMA)
568 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
569}
570
571static void sdhci_adma_mark_end(void *desc)
572{
573 struct sdhci_adma2_64_desc *dma_desc = desc;
574
575 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
576 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
577}
578
579static void sdhci_adma_table_pre(struct sdhci_host *host,
580 struct mmc_data *data, int sg_count)
581{
582 struct scatterlist *sg;
583 unsigned long flags;
584 dma_addr_t addr, align_addr;
585 void *desc, *align;
586 char *buffer;
587 int len, offset, i;
588
589 /*
590 * The spec does not specify endianness of descriptor table.
591 * We currently guess that it is LE.
592 */
593
594 host->sg_count = sg_count;
595
596 desc = host->adma_table;
597 align = host->align_buffer;
598
599 align_addr = host->align_addr;
600
601 for_each_sg(data->sg, sg, host->sg_count, i) {
602 addr = sg_dma_address(sg);
603 len = sg_dma_len(sg);
604
605 /*
606 * The SDHCI specification states that ADMA addresses must
607 * be 32-bit aligned. If they aren't, then we use a bounce
608 * buffer for the (up to three) bytes that screw up the
609 * alignment.
610 */
611 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
612 SDHCI_ADMA2_MASK;
613 if (offset) {
614 if (data->flags & MMC_DATA_WRITE) {
615 buffer = sdhci_kmap_atomic(sg, &flags);
616 memcpy(align, buffer, offset);
617 sdhci_kunmap_atomic(buffer, &flags);
618 }
619
620 /* tran, valid */
621 sdhci_adma_write_desc(host, desc, align_addr, offset,
622 ADMA2_TRAN_VALID);
623
624 BUG_ON(offset > 65536);
625
626 align += SDHCI_ADMA2_ALIGN;
627 align_addr += SDHCI_ADMA2_ALIGN;
628
629 desc += host->desc_sz;
630
631 addr += offset;
632 len -= offset;
633 }
634
635 BUG_ON(len > 65536);
636
637 if (len) {
638 /* tran, valid */
639 sdhci_adma_write_desc(host, desc, addr, len,
640 ADMA2_TRAN_VALID);
641 desc += host->desc_sz;
642 }
643
644 /*
645 * If this triggers then we have a calculation bug
646 * somewhere. :/
647 */
648 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
649 }
650
651 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
652 /* Mark the last descriptor as the terminating descriptor */
653 if (desc != host->adma_table) {
654 desc -= host->desc_sz;
655 sdhci_adma_mark_end(desc);
656 }
657 } else {
658 /* Add a terminating entry - nop, end, valid */
659 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
660 }
661}
662
663static void sdhci_adma_table_post(struct sdhci_host *host,
664 struct mmc_data *data)
665{
666 struct scatterlist *sg;
667 int i, size;
668 void *align;
669 char *buffer;
670 unsigned long flags;
671
672 if (data->flags & MMC_DATA_READ) {
673 bool has_unaligned = false;
674
675 /* Do a quick scan of the SG list for any unaligned mappings */
676 for_each_sg(data->sg, sg, host->sg_count, i)
677 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
678 has_unaligned = true;
679 break;
680 }
681
682 if (has_unaligned) {
683 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
684 data->sg_len, DMA_FROM_DEVICE);
685
686 align = host->align_buffer;
687
688 for_each_sg(data->sg, sg, host->sg_count, i) {
689 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
690 size = SDHCI_ADMA2_ALIGN -
691 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
692
693 buffer = sdhci_kmap_atomic(sg, &flags);
694 memcpy(buffer, align, size);
695 sdhci_kunmap_atomic(buffer, &flags);
696
697 align += SDHCI_ADMA2_ALIGN;
698 }
699 }
700 }
701 }
702}
703
704static u32 sdhci_sdma_address(struct sdhci_host *host)
705{
706 if (host->bounce_buffer)
707 return host->bounce_addr;
708 else
709 return sg_dma_address(host->data->sg);
710}
711
712static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
713{
714 u8 count;
715 struct mmc_data *data = cmd->data;
716 unsigned target_timeout, current_timeout;
717
718 /*
719 * If the host controller provides us with an incorrect timeout
720 * value, just skip the check and use 0xE. The hardware may take
721 * longer to time out, but that's much better than having a too-short
722 * timeout value.
723 */
724 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
725 return 0xE;
726
727 /* Unspecified timeout, assume max */
728 if (!data && !cmd->busy_timeout)
729 return 0xE;
730
731 /* timeout in us */
732 if (!data)
733 target_timeout = cmd->busy_timeout * 1000;
734 else {
735 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
736 if (host->clock && data->timeout_clks) {
737 unsigned long long val;
738
739 /*
740 * data->timeout_clks is in units of clock cycles.
741 * host->clock is in Hz. target_timeout is in us.
742 * Hence, us = 1000000 * cycles / Hz. Round up.
743 */
744 val = 1000000ULL * data->timeout_clks;
745 if (do_div(val, host->clock))
746 target_timeout++;
747 target_timeout += val;
748 }
749 }
750
751 /*
752 * Figure out needed cycles.
753 * We do this in steps in order to fit inside a 32 bit int.
754 * The first step is the minimum timeout, which will have a
755 * minimum resolution of 6 bits:
756 * (1) 2^13*1000 > 2^22,
757 * (2) host->timeout_clk < 2^16
758 * =>
759 * (1) / (2) > 2^6
760 */
761 count = 0;
762 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
763 while (current_timeout < target_timeout) {
764 count++;
765 current_timeout <<= 1;
766 if (count >= 0xF)
767 break;
768 }
769
770 if (count >= 0xF) {
771 DBG("Too large timeout 0x%x requested for CMD%d!\n",
772 count, cmd->opcode);
773 count = 0xE;
774 }
775
776 return count;
777}
778
779static void sdhci_set_transfer_irqs(struct sdhci_host *host)
780{
781 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
782 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
783
784 if (host->flags & SDHCI_REQ_USE_DMA)
785 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
786 else
787 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
788
789 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
790 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
791}
792
793static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
794{
795 u8 count;
796
797 if (host->ops->set_timeout) {
798 host->ops->set_timeout(host, cmd);
799 } else {
800 count = sdhci_calc_timeout(host, cmd);
801 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
802 }
803}
804
805static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
806{
807 u8 ctrl;
808 struct mmc_data *data = cmd->data;
809
810 if (sdhci_data_line_cmd(cmd))
811 sdhci_set_timeout(host, cmd);
812
813 if (!data)
814 return;
815
816 WARN_ON(host->data);
817
818 /* Sanity checks */
819 BUG_ON(data->blksz * data->blocks > 524288);
820 BUG_ON(data->blksz > host->mmc->max_blk_size);
821 BUG_ON(data->blocks > 65535);
822
823 host->data = data;
824 host->data_early = 0;
825 host->data->bytes_xfered = 0;
826
827 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
828 struct scatterlist *sg;
829 unsigned int length_mask, offset_mask;
830 int i;
831
832 host->flags |= SDHCI_REQ_USE_DMA;
833
834 /*
835 * FIXME: This doesn't account for merging when mapping the
836 * scatterlist.
837 *
838 * The assumption here being that alignment and lengths are
839 * the same after DMA mapping to device address space.
840 */
841 length_mask = 0;
842 offset_mask = 0;
843 if (host->flags & SDHCI_USE_ADMA) {
844 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
845 length_mask = 3;
846 /*
847 * As we use up to 3 byte chunks to work
848 * around alignment problems, we need to
849 * check the offset as well.
850 */
851 offset_mask = 3;
852 }
853 } else {
854 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
855 length_mask = 3;
856 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
857 offset_mask = 3;
858 }
859
860 if (unlikely(length_mask | offset_mask)) {
861 for_each_sg(data->sg, sg, data->sg_len, i) {
862 if (sg->length & length_mask) {
863 DBG("Reverting to PIO because of transfer size (%d)\n",
864 sg->length);
865 host->flags &= ~SDHCI_REQ_USE_DMA;
866 break;
867 }
868 if (sg->offset & offset_mask) {
869 DBG("Reverting to PIO because of bad alignment\n");
870 host->flags &= ~SDHCI_REQ_USE_DMA;
871 break;
872 }
873 }
874 }
875 }
876
877 if (host->flags & SDHCI_REQ_USE_DMA) {
878 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
879
880 if (sg_cnt <= 0) {
881 /*
882 * This only happens when someone fed
883 * us an invalid request.
884 */
885 WARN_ON(1);
886 host->flags &= ~SDHCI_REQ_USE_DMA;
887 } else if (host->flags & SDHCI_USE_ADMA) {
888 sdhci_adma_table_pre(host, data, sg_cnt);
889
890 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
891 if (host->flags & SDHCI_USE_64_BIT_DMA)
892 sdhci_writel(host,
893 (u64)host->adma_addr >> 32,
894 SDHCI_ADMA_ADDRESS_HI);
895 } else {
896 WARN_ON(sg_cnt != 1);
897 sdhci_writel(host, sdhci_sdma_address(host),
898 SDHCI_DMA_ADDRESS);
899 }
900 }
901
902 /*
903 * Always adjust the DMA selection as some controllers
904 * (e.g. JMicron) can't do PIO properly when the selection
905 * is ADMA.
906 */
907 if (host->version >= SDHCI_SPEC_200) {
908 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
909 ctrl &= ~SDHCI_CTRL_DMA_MASK;
910 if ((host->flags & SDHCI_REQ_USE_DMA) &&
911 (host->flags & SDHCI_USE_ADMA)) {
912 if (host->flags & SDHCI_USE_64_BIT_DMA)
913 ctrl |= SDHCI_CTRL_ADMA64;
914 else
915 ctrl |= SDHCI_CTRL_ADMA32;
916 } else {
917 ctrl |= SDHCI_CTRL_SDMA;
918 }
919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
920 }
921
922 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
923 int flags;
924
925 flags = SG_MITER_ATOMIC;
926 if (host->data->flags & MMC_DATA_READ)
927 flags |= SG_MITER_TO_SG;
928 else
929 flags |= SG_MITER_FROM_SG;
930 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
931 host->blocks = data->blocks;
932 }
933
934 sdhci_set_transfer_irqs(host);
935
936 /* Set the DMA boundary value and block size */
937 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
938 SDHCI_BLOCK_SIZE);
939 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
940}
941
942static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
943 struct mmc_request *mrq)
944{
945 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
946 !mrq->cap_cmd_during_tfr;
947}
948
949static void sdhci_set_transfer_mode(struct sdhci_host *host,
950 struct mmc_command *cmd)
951{
952 u16 mode = 0;
953 struct mmc_data *data = cmd->data;
954
955 if (data == NULL) {
956 if (host->quirks2 &
957 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
958 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
959 } else {
960 /* clear Auto CMD settings for no data CMDs */
961 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
962 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
963 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
964 }
965 return;
966 }
967
968 WARN_ON(!host->data);
969
970 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
971 mode = SDHCI_TRNS_BLK_CNT_EN;
972
973 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
974 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
975 /*
976 * If we are sending CMD23, CMD12 never gets sent
977 * on successful completion (so no Auto-CMD12).
978 */
979 if (sdhci_auto_cmd12(host, cmd->mrq) &&
980 (cmd->opcode != SD_IO_RW_EXTENDED))
981 mode |= SDHCI_TRNS_AUTO_CMD12;
982 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
983 mode |= SDHCI_TRNS_AUTO_CMD23;
984 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
985 }
986 }
987
988 if (data->flags & MMC_DATA_READ)
989 mode |= SDHCI_TRNS_READ;
990 if (host->flags & SDHCI_REQ_USE_DMA)
991 mode |= SDHCI_TRNS_DMA;
992
993 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
994}
995
996static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
997{
998 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
999 ((mrq->cmd && mrq->cmd->error) ||
1000 (mrq->sbc && mrq->sbc->error) ||
1001 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
1002 (mrq->data->stop && mrq->data->stop->error))) ||
1003 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1004}
1005
1006static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1007{
1008 int i;
1009
1010 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1011 if (host->mrqs_done[i] == mrq) {
1012 WARN_ON(1);
1013 return;
1014 }
1015 }
1016
1017 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1018 if (!host->mrqs_done[i]) {
1019 host->mrqs_done[i] = mrq;
1020 break;
1021 }
1022 }
1023
1024 WARN_ON(i >= SDHCI_MAX_MRQS);
1025
1026 tasklet_schedule(&host->finish_tasklet);
1027}
1028
1029static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1030{
1031 if (host->cmd && host->cmd->mrq == mrq)
1032 host->cmd = NULL;
1033
1034 if (host->data_cmd && host->data_cmd->mrq == mrq)
1035 host->data_cmd = NULL;
1036
1037 if (host->data && host->data->mrq == mrq)
1038 host->data = NULL;
1039
1040 if (sdhci_needs_reset(host, mrq))
1041 host->pending_reset = true;
1042
1043 __sdhci_finish_mrq(host, mrq);
1044}
1045
1046static void sdhci_finish_data(struct sdhci_host *host)
1047{
1048 struct mmc_command *data_cmd = host->data_cmd;
1049 struct mmc_data *data = host->data;
1050
1051 host->data = NULL;
1052 host->data_cmd = NULL;
1053
1054 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1055 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1056 sdhci_adma_table_post(host, data);
1057
1058 /*
1059 * The specification states that the block count register must
1060 * be updated, but it does not specify at what point in the
1061 * data flow. That makes the register entirely useless to read
1062 * back so we have to assume that nothing made it to the card
1063 * in the event of an error.
1064 */
1065 if (data->error)
1066 data->bytes_xfered = 0;
1067 else
1068 data->bytes_xfered = data->blksz * data->blocks;
1069
1070 /*
1071 * Need to send CMD12 if -
1072 * a) open-ended multiblock transfer (no CMD23)
1073 * b) error in multiblock transfer
1074 */
1075 if (data->stop &&
1076 (data->error ||
1077 !data->mrq->sbc)) {
1078
1079 /*
1080 * The controller needs a reset of internal state machines
1081 * upon error conditions.
1082 */
1083 if (data->error) {
1084 if (!host->cmd || host->cmd == data_cmd)
1085 sdhci_do_reset(host, SDHCI_RESET_CMD);
1086 sdhci_do_reset(host, SDHCI_RESET_DATA);
1087 }
1088
1089 /*
1090 * 'cap_cmd_during_tfr' request must not use the command line
1091 * after mmc_command_done() has been called. It is upper layer's
1092 * responsibility to send the stop command if required.
1093 */
1094 if (data->mrq->cap_cmd_during_tfr) {
1095 sdhci_finish_mrq(host, data->mrq);
1096 } else {
1097 /* Avoid triggering warning in sdhci_send_command() */
1098 host->cmd = NULL;
1099 sdhci_send_command(host, data->stop);
1100 }
1101 } else {
1102 sdhci_finish_mrq(host, data->mrq);
1103 }
1104}
1105
1106static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1107 unsigned long timeout)
1108{
1109 if (sdhci_data_line_cmd(mrq->cmd))
1110 mod_timer(&host->data_timer, timeout);
1111 else
1112 mod_timer(&host->timer, timeout);
1113}
1114
1115static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1116{
1117 if (sdhci_data_line_cmd(mrq->cmd))
1118 del_timer(&host->data_timer);
1119 else
1120 del_timer(&host->timer);
1121}
1122
1123void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1124{
1125 int flags;
1126 u32 mask;
1127 unsigned long timeout;
1128
1129 WARN_ON(host->cmd);
1130
1131 /* Initially, a command has no error */
1132 cmd->error = 0;
1133
1134 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1135 cmd->opcode == MMC_STOP_TRANSMISSION)
1136 cmd->flags |= MMC_RSP_BUSY;
1137
1138 /* Wait max 10 ms */
1139 timeout = 10;
1140
1141 mask = SDHCI_CMD_INHIBIT;
1142 if (sdhci_data_line_cmd(cmd))
1143 mask |= SDHCI_DATA_INHIBIT;
1144
1145 /* We shouldn't wait for data inihibit for stop commands, even
1146 though they might use busy signaling */
1147 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1148 mask &= ~SDHCI_DATA_INHIBIT;
1149
1150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1151 if (timeout == 0) {
1152 pr_err("%s: Controller never released inhibit bit(s).\n",
1153 mmc_hostname(host->mmc));
1154 sdhci_dumpregs(host);
1155 cmd->error = -EIO;
1156 sdhci_finish_mrq(host, cmd->mrq);
1157 return;
1158 }
1159 timeout--;
1160 mdelay(1);
1161 }
1162
1163 timeout = jiffies;
1164 if (!cmd->data && cmd->busy_timeout > 9000)
1165 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1166 else
1167 timeout += 10 * HZ;
1168 sdhci_mod_timer(host, cmd->mrq, timeout);
1169
1170 host->cmd = cmd;
1171 if (sdhci_data_line_cmd(cmd)) {
1172 WARN_ON(host->data_cmd);
1173 host->data_cmd = cmd;
1174 }
1175
1176 sdhci_prepare_data(host, cmd);
1177
1178 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1179
1180 sdhci_set_transfer_mode(host, cmd);
1181
1182 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1183 pr_err("%s: Unsupported response type!\n",
1184 mmc_hostname(host->mmc));
1185 cmd->error = -EINVAL;
1186 sdhci_finish_mrq(host, cmd->mrq);
1187 return;
1188 }
1189
1190 if (!(cmd->flags & MMC_RSP_PRESENT))
1191 flags = SDHCI_CMD_RESP_NONE;
1192 else if (cmd->flags & MMC_RSP_136)
1193 flags = SDHCI_CMD_RESP_LONG;
1194 else if (cmd->flags & MMC_RSP_BUSY)
1195 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1196 else
1197 flags = SDHCI_CMD_RESP_SHORT;
1198
1199 if (cmd->flags & MMC_RSP_CRC)
1200 flags |= SDHCI_CMD_CRC;
1201 if (cmd->flags & MMC_RSP_OPCODE)
1202 flags |= SDHCI_CMD_INDEX;
1203
1204 /* CMD19 is special in that the Data Present Select should be set */
1205 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1206 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1207 flags |= SDHCI_CMD_DATA;
1208
1209 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1210}
1211EXPORT_SYMBOL_GPL(sdhci_send_command);
1212
1213static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1214{
1215 int i, reg;
1216
1217 for (i = 0; i < 4; i++) {
1218 reg = SDHCI_RESPONSE + (3 - i) * 4;
1219 cmd->resp[i] = sdhci_readl(host, reg);
1220 }
1221
1222 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1223 return;
1224
1225 /* CRC is stripped so we need to do some shifting */
1226 for (i = 0; i < 4; i++) {
1227 cmd->resp[i] <<= 8;
1228 if (i != 3)
1229 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1230 }
1231}
1232
1233static void sdhci_finish_command(struct sdhci_host *host)
1234{
1235 struct mmc_command *cmd = host->cmd;
1236
1237 host->cmd = NULL;
1238
1239 if (cmd->flags & MMC_RSP_PRESENT) {
1240 if (cmd->flags & MMC_RSP_136) {
1241 sdhci_read_rsp_136(host, cmd);
1242 } else {
1243 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1244 }
1245 }
1246
1247 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1248 mmc_command_done(host->mmc, cmd->mrq);
1249
1250 /*
1251 * The host can send and interrupt when the busy state has
1252 * ended, allowing us to wait without wasting CPU cycles.
1253 * The busy signal uses DAT0 so this is similar to waiting
1254 * for data to complete.
1255 *
1256 * Note: The 1.0 specification is a bit ambiguous about this
1257 * feature so there might be some problems with older
1258 * controllers.
1259 */
1260 if (cmd->flags & MMC_RSP_BUSY) {
1261 if (cmd->data) {
1262 DBG("Cannot wait for busy signal when also doing a data transfer");
1263 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1264 cmd == host->data_cmd) {
1265 /* Command complete before busy is ended */
1266 return;
1267 }
1268 }
1269
1270 /* Finished CMD23, now send actual command. */
1271 if (cmd == cmd->mrq->sbc) {
1272 sdhci_send_command(host, cmd->mrq->cmd);
1273 } else {
1274
1275 /* Processed actual command. */
1276 if (host->data && host->data_early)
1277 sdhci_finish_data(host);
1278
1279 if (!cmd->data)
1280 sdhci_finish_mrq(host, cmd->mrq);
1281 }
1282}
1283
1284static u16 sdhci_get_preset_value(struct sdhci_host *host)
1285{
1286 u16 preset = 0;
1287
1288 switch (host->timing) {
1289 case MMC_TIMING_UHS_SDR12:
1290 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1291 break;
1292 case MMC_TIMING_UHS_SDR25:
1293 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1294 break;
1295 case MMC_TIMING_UHS_SDR50:
1296 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1297 break;
1298 case MMC_TIMING_UHS_SDR104:
1299 case MMC_TIMING_MMC_HS200:
1300 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1301 break;
1302 case MMC_TIMING_UHS_DDR50:
1303 case MMC_TIMING_MMC_DDR52:
1304 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1305 break;
1306 case MMC_TIMING_MMC_HS400:
1307 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1308 break;
1309 default:
1310 pr_warn("%s: Invalid UHS-I mode selected\n",
1311 mmc_hostname(host->mmc));
1312 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1313 break;
1314 }
1315 return preset;
1316}
1317
1318u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1319 unsigned int *actual_clock)
1320{
1321 int div = 0; /* Initialized for compiler warning */
1322 int real_div = div, clk_mul = 1;
1323 u16 clk = 0;
1324 bool switch_base_clk = false;
1325
1326 if (host->version >= SDHCI_SPEC_300) {
1327 if (host->preset_enabled) {
1328 u16 pre_val;
1329
1330 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1331 pre_val = sdhci_get_preset_value(host);
1332 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1333 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1334 if (host->clk_mul &&
1335 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1336 clk = SDHCI_PROG_CLOCK_MODE;
1337 real_div = div + 1;
1338 clk_mul = host->clk_mul;
1339 } else {
1340 real_div = max_t(int, 1, div << 1);
1341 }
1342 goto clock_set;
1343 }
1344
1345 /*
1346 * Check if the Host Controller supports Programmable Clock
1347 * Mode.
1348 */
1349 if (host->clk_mul) {
1350 for (div = 1; div <= 1024; div++) {
1351 if ((host->max_clk * host->clk_mul / div)
1352 <= clock)
1353 break;
1354 }
1355 if ((host->max_clk * host->clk_mul / div) <= clock) {
1356 /*
1357 * Set Programmable Clock Mode in the Clock
1358 * Control register.
1359 */
1360 clk = SDHCI_PROG_CLOCK_MODE;
1361 real_div = div;
1362 clk_mul = host->clk_mul;
1363 div--;
1364 } else {
1365 /*
1366 * Divisor can be too small to reach clock
1367 * speed requirement. Then use the base clock.
1368 */
1369 switch_base_clk = true;
1370 }
1371 }
1372
1373 if (!host->clk_mul || switch_base_clk) {
1374 /* Version 3.00 divisors must be a multiple of 2. */
1375 if (host->max_clk <= clock)
1376 div = 1;
1377 else {
1378 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1379 div += 2) {
1380 if ((host->max_clk / div) <= clock)
1381 break;
1382 }
1383 }
1384 real_div = div;
1385 div >>= 1;
1386 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1387 && !div && host->max_clk <= 25000000)
1388 div = 1;
1389 }
1390 } else {
1391 /* Version 2.00 divisors must be a power of 2. */
1392 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1393 if ((host->max_clk / div) <= clock)
1394 break;
1395 }
1396 real_div = div;
1397 div >>= 1;
1398 }
1399
1400clock_set:
1401 if (real_div)
1402 *actual_clock = (host->max_clk * clk_mul) / real_div;
1403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1405 << SDHCI_DIVIDER_HI_SHIFT;
1406
1407 return clk;
1408}
1409EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1410
1411void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1412{
1413 ktime_t timeout;
1414
1415 clk |= SDHCI_CLOCK_INT_EN;
1416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1417
1418 /* Wait max 20 ms */
1419 timeout = ktime_add_ms(ktime_get(), 20);
1420 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1421 & SDHCI_CLOCK_INT_STABLE)) {
1422 if (ktime_after(ktime_get(), timeout)) {
1423 pr_err("%s: Internal clock never stabilised.\n",
1424 mmc_hostname(host->mmc));
1425 sdhci_dumpregs(host);
1426 return;
1427 }
1428 udelay(10);
1429 }
1430
1431 clk |= SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433}
1434EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1435
1436void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1437{
1438 u16 clk;
1439
1440 host->mmc->actual_clock = 0;
1441
1442 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1443
1444 if (clock == 0)
1445 return;
1446
1447 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1448 sdhci_enable_clk(host, clk);
1449}
1450EXPORT_SYMBOL_GPL(sdhci_set_clock);
1451
1452static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1453 unsigned short vdd)
1454{
1455 struct mmc_host *mmc = host->mmc;
1456
1457 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1458
1459 if (mode != MMC_POWER_OFF)
1460 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1461 else
1462 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1463}
1464
1465void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1466 unsigned short vdd)
1467{
1468 u8 pwr = 0;
1469
1470 if (mode != MMC_POWER_OFF) {
1471 switch (1 << vdd) {
1472 case MMC_VDD_165_195:
1473 /*
1474 * Without a regulator, SDHCI does not support 2.0v
1475 * so we only get here if the driver deliberately
1476 * added the 2.0v range to ocr_avail. Map it to 1.8v
1477 * for the purpose of turning on the power.
1478 */
1479 case MMC_VDD_20_21:
1480 pwr = SDHCI_POWER_180;
1481 break;
1482 case MMC_VDD_29_30:
1483 case MMC_VDD_30_31:
1484 pwr = SDHCI_POWER_300;
1485 break;
1486 case MMC_VDD_32_33:
1487 case MMC_VDD_33_34:
1488 pwr = SDHCI_POWER_330;
1489 break;
1490 default:
1491 WARN(1, "%s: Invalid vdd %#x\n",
1492 mmc_hostname(host->mmc), vdd);
1493 break;
1494 }
1495 }
1496
1497 if (host->pwr == pwr)
1498 return;
1499
1500 host->pwr = pwr;
1501
1502 if (pwr == 0) {
1503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1504 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1505 sdhci_runtime_pm_bus_off(host);
1506 } else {
1507 /*
1508 * Spec says that we should clear the power reg before setting
1509 * a new value. Some controllers don't seem to like this though.
1510 */
1511 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1512 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1513
1514 /*
1515 * At least the Marvell CaFe chip gets confused if we set the
1516 * voltage and set turn on power at the same time, so set the
1517 * voltage first.
1518 */
1519 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1520 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1521
1522 pwr |= SDHCI_POWER_ON;
1523
1524 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1525
1526 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1527 sdhci_runtime_pm_bus_on(host);
1528
1529 /*
1530 * Some controllers need an extra 10ms delay of 10ms before
1531 * they can apply clock after applying power
1532 */
1533 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1534 mdelay(10);
1535 }
1536}
1537EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1538
1539void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1540 unsigned short vdd)
1541{
1542 if (IS_ERR(host->mmc->supply.vmmc))
1543 sdhci_set_power_noreg(host, mode, vdd);
1544 else
1545 sdhci_set_power_reg(host, mode, vdd);
1546}
1547EXPORT_SYMBOL_GPL(sdhci_set_power);
1548
1549/*****************************************************************************\
1550 * *
1551 * MMC callbacks *
1552 * *
1553\*****************************************************************************/
1554
1555static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1556{
1557 struct sdhci_host *host;
1558 int present;
1559 unsigned long flags;
1560
1561 host = mmc_priv(mmc);
1562
1563 /* Firstly check card presence */
1564 present = mmc->ops->get_cd(mmc);
1565
1566 spin_lock_irqsave(&host->lock, flags);
1567
1568 sdhci_led_activate(host);
1569
1570 /*
1571 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1572 * requests if Auto-CMD12 is enabled.
1573 */
1574 if (sdhci_auto_cmd12(host, mrq)) {
1575 if (mrq->stop) {
1576 mrq->data->stop = NULL;
1577 mrq->stop = NULL;
1578 }
1579 }
1580
1581 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1582 mrq->cmd->error = -ENOMEDIUM;
1583 sdhci_finish_mrq(host, mrq);
1584 } else {
1585 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1586 sdhci_send_command(host, mrq->sbc);
1587 else
1588 sdhci_send_command(host, mrq->cmd);
1589 }
1590
1591 mmiowb();
1592 spin_unlock_irqrestore(&host->lock, flags);
1593}
1594
1595void sdhci_set_bus_width(struct sdhci_host *host, int width)
1596{
1597 u8 ctrl;
1598
1599 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1600 if (width == MMC_BUS_WIDTH_8) {
1601 ctrl &= ~SDHCI_CTRL_4BITBUS;
1602 ctrl |= SDHCI_CTRL_8BITBUS;
1603 } else {
1604 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1605 ctrl &= ~SDHCI_CTRL_8BITBUS;
1606 if (width == MMC_BUS_WIDTH_4)
1607 ctrl |= SDHCI_CTRL_4BITBUS;
1608 else
1609 ctrl &= ~SDHCI_CTRL_4BITBUS;
1610 }
1611 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1612}
1613EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1614
1615void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1616{
1617 u16 ctrl_2;
1618
1619 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1620 /* Select Bus Speed Mode for host */
1621 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1622 if ((timing == MMC_TIMING_MMC_HS200) ||
1623 (timing == MMC_TIMING_UHS_SDR104))
1624 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1625 else if (timing == MMC_TIMING_UHS_SDR12)
1626 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1627 else if (timing == MMC_TIMING_UHS_SDR25)
1628 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1629 else if (timing == MMC_TIMING_UHS_SDR50)
1630 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1631 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1632 (timing == MMC_TIMING_MMC_DDR52))
1633 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1634 else if (timing == MMC_TIMING_MMC_HS400)
1635 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1636 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1637}
1638EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1639
1640void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 u8 ctrl;
1644
1645 if (ios->power_mode == MMC_POWER_UNDEFINED)
1646 return;
1647
1648 if (host->flags & SDHCI_DEVICE_DEAD) {
1649 if (!IS_ERR(mmc->supply.vmmc) &&
1650 ios->power_mode == MMC_POWER_OFF)
1651 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1652 return;
1653 }
1654
1655 /*
1656 * Reset the chip on each power off.
1657 * Should clear out any weird states.
1658 */
1659 if (ios->power_mode == MMC_POWER_OFF) {
1660 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1661 sdhci_reinit(host);
1662 }
1663
1664 if (host->version >= SDHCI_SPEC_300 &&
1665 (ios->power_mode == MMC_POWER_UP) &&
1666 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1667 sdhci_enable_preset_value(host, false);
1668
1669 if (!ios->clock || ios->clock != host->clock) {
1670 host->ops->set_clock(host, ios->clock);
1671 host->clock = ios->clock;
1672
1673 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1674 host->clock) {
1675 host->timeout_clk = host->mmc->actual_clock ?
1676 host->mmc->actual_clock / 1000 :
1677 host->clock / 1000;
1678 host->mmc->max_busy_timeout =
1679 host->ops->get_max_timeout_count ?
1680 host->ops->get_max_timeout_count(host) :
1681 1 << 27;
1682 host->mmc->max_busy_timeout /= host->timeout_clk;
1683 }
1684 }
1685
1686 if (host->ops->set_power)
1687 host->ops->set_power(host, ios->power_mode, ios->vdd);
1688 else
1689 sdhci_set_power(host, ios->power_mode, ios->vdd);
1690
1691 if (host->ops->platform_send_init_74_clocks)
1692 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1693
1694 host->ops->set_bus_width(host, ios->bus_width);
1695
1696 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1697
1698 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1699 if (ios->timing == MMC_TIMING_SD_HS ||
1700 ios->timing == MMC_TIMING_MMC_HS ||
1701 ios->timing == MMC_TIMING_MMC_HS400 ||
1702 ios->timing == MMC_TIMING_MMC_HS200 ||
1703 ios->timing == MMC_TIMING_MMC_DDR52 ||
1704 ios->timing == MMC_TIMING_UHS_SDR50 ||
1705 ios->timing == MMC_TIMING_UHS_SDR104 ||
1706 ios->timing == MMC_TIMING_UHS_DDR50 ||
1707 ios->timing == MMC_TIMING_UHS_SDR25)
1708 ctrl |= SDHCI_CTRL_HISPD;
1709 else
1710 ctrl &= ~SDHCI_CTRL_HISPD;
1711 }
1712
1713 if (host->version >= SDHCI_SPEC_300) {
1714 u16 clk, ctrl_2;
1715
1716 if (!host->preset_enabled) {
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1718 /*
1719 * We only need to set Driver Strength if the
1720 * preset value enable is not set.
1721 */
1722 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1723 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1724 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1725 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1726 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1727 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1728 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1729 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1730 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1731 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1732 else {
1733 pr_warn("%s: invalid driver type, default to driver type B\n",
1734 mmc_hostname(mmc));
1735 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1736 }
1737
1738 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1739 } else {
1740 /*
1741 * According to SDHC Spec v3.00, if the Preset Value
1742 * Enable in the Host Control 2 register is set, we
1743 * need to reset SD Clock Enable before changing High
1744 * Speed Enable to avoid generating clock gliches.
1745 */
1746
1747 /* Reset SD Clock Enable */
1748 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1749 clk &= ~SDHCI_CLOCK_CARD_EN;
1750 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1751
1752 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1753
1754 /* Re-enable SD Clock */
1755 host->ops->set_clock(host, host->clock);
1756 }
1757
1758 /* Reset SD Clock Enable */
1759 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1760 clk &= ~SDHCI_CLOCK_CARD_EN;
1761 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1762
1763 host->ops->set_uhs_signaling(host, ios->timing);
1764 host->timing = ios->timing;
1765
1766 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1767 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1768 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1769 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1770 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1771 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1772 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1773 u16 preset;
1774
1775 sdhci_enable_preset_value(host, true);
1776 preset = sdhci_get_preset_value(host);
1777 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1778 >> SDHCI_PRESET_DRV_SHIFT;
1779 }
1780
1781 /* Re-enable SD Clock */
1782 host->ops->set_clock(host, host->clock);
1783 } else
1784 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1785
1786 /*
1787 * Some (ENE) controllers go apeshit on some ios operation,
1788 * signalling timeout and CRC errors even on CMD0. Resetting
1789 * it on each ios seems to solve the problem.
1790 */
1791 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1792 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1793
1794 mmiowb();
1795}
1796EXPORT_SYMBOL_GPL(sdhci_set_ios);
1797
1798static int sdhci_get_cd(struct mmc_host *mmc)
1799{
1800 struct sdhci_host *host = mmc_priv(mmc);
1801 int gpio_cd = mmc_gpio_get_cd(mmc);
1802
1803 if (host->flags & SDHCI_DEVICE_DEAD)
1804 return 0;
1805
1806 /* If nonremovable, assume that the card is always present. */
1807 if (!mmc_card_is_removable(host->mmc))
1808 return 1;
1809
1810 /*
1811 * Try slot gpio detect, if defined it take precedence
1812 * over build in controller functionality
1813 */
1814 if (gpio_cd >= 0)
1815 return !!gpio_cd;
1816
1817 /* If polling, assume that the card is always present. */
1818 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1819 return 1;
1820
1821 /* Host native card detect */
1822 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1823}
1824
1825static int sdhci_check_ro(struct sdhci_host *host)
1826{
1827 unsigned long flags;
1828 int is_readonly;
1829
1830 spin_lock_irqsave(&host->lock, flags);
1831
1832 if (host->flags & SDHCI_DEVICE_DEAD)
1833 is_readonly = 0;
1834 else if (host->ops->get_ro)
1835 is_readonly = host->ops->get_ro(host);
1836 else
1837 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1838 & SDHCI_WRITE_PROTECT);
1839
1840 spin_unlock_irqrestore(&host->lock, flags);
1841
1842 /* This quirk needs to be replaced by a callback-function later */
1843 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1844 !is_readonly : is_readonly;
1845}
1846
1847#define SAMPLE_COUNT 5
1848
1849static int sdhci_get_ro(struct mmc_host *mmc)
1850{
1851 struct sdhci_host *host = mmc_priv(mmc);
1852 int i, ro_count;
1853
1854 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1855 return sdhci_check_ro(host);
1856
1857 ro_count = 0;
1858 for (i = 0; i < SAMPLE_COUNT; i++) {
1859 if (sdhci_check_ro(host)) {
1860 if (++ro_count > SAMPLE_COUNT / 2)
1861 return 1;
1862 }
1863 msleep(30);
1864 }
1865 return 0;
1866}
1867
1868static void sdhci_hw_reset(struct mmc_host *mmc)
1869{
1870 struct sdhci_host *host = mmc_priv(mmc);
1871
1872 if (host->ops && host->ops->hw_reset)
1873 host->ops->hw_reset(host);
1874}
1875
1876static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1877{
1878 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1879 if (enable)
1880 host->ier |= SDHCI_INT_CARD_INT;
1881 else
1882 host->ier &= ~SDHCI_INT_CARD_INT;
1883
1884 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1885 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1886 mmiowb();
1887 }
1888}
1889
1890void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1891{
1892 struct sdhci_host *host = mmc_priv(mmc);
1893 unsigned long flags;
1894
1895 if (enable)
1896 pm_runtime_get_noresume(host->mmc->parent);
1897
1898 spin_lock_irqsave(&host->lock, flags);
1899 if (enable)
1900 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1901 else
1902 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1903
1904 sdhci_enable_sdio_irq_nolock(host, enable);
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 if (!enable)
1908 pm_runtime_put_noidle(host->mmc->parent);
1909}
1910EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1911
1912int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1913 struct mmc_ios *ios)
1914{
1915 struct sdhci_host *host = mmc_priv(mmc);
1916 u16 ctrl;
1917 int ret;
1918
1919 /*
1920 * Signal Voltage Switching is only applicable for Host Controllers
1921 * v3.00 and above.
1922 */
1923 if (host->version < SDHCI_SPEC_300)
1924 return 0;
1925
1926 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927
1928 switch (ios->signal_voltage) {
1929 case MMC_SIGNAL_VOLTAGE_330:
1930 if (!(host->flags & SDHCI_SIGNALING_330))
1931 return -EINVAL;
1932 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1933 ctrl &= ~SDHCI_CTRL_VDD_180;
1934 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1935
1936 if (!IS_ERR(mmc->supply.vqmmc)) {
1937 ret = mmc_regulator_set_vqmmc(mmc, ios);
1938 if (ret) {
1939 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1940 mmc_hostname(mmc));
1941 return -EIO;
1942 }
1943 }
1944 /* Wait for 5ms */
1945 usleep_range(5000, 5500);
1946
1947 /* 3.3V regulator output should be stable within 5 ms */
1948 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1949 if (!(ctrl & SDHCI_CTRL_VDD_180))
1950 return 0;
1951
1952 pr_warn("%s: 3.3V regulator output did not became stable\n",
1953 mmc_hostname(mmc));
1954
1955 return -EAGAIN;
1956 case MMC_SIGNAL_VOLTAGE_180:
1957 if (!(host->flags & SDHCI_SIGNALING_180))
1958 return -EINVAL;
1959 if (!IS_ERR(mmc->supply.vqmmc)) {
1960 ret = mmc_regulator_set_vqmmc(mmc, ios);
1961 if (ret) {
1962 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1963 mmc_hostname(mmc));
1964 return -EIO;
1965 }
1966 }
1967
1968 /*
1969 * Enable 1.8V Signal Enable in the Host Control2
1970 * register
1971 */
1972 ctrl |= SDHCI_CTRL_VDD_180;
1973 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1974
1975 /* Some controller need to do more when switching */
1976 if (host->ops->voltage_switch)
1977 host->ops->voltage_switch(host);
1978
1979 /* 1.8V regulator output should be stable within 5 ms */
1980 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1981 if (ctrl & SDHCI_CTRL_VDD_180)
1982 return 0;
1983
1984 pr_warn("%s: 1.8V regulator output did not became stable\n",
1985 mmc_hostname(mmc));
1986
1987 return -EAGAIN;
1988 case MMC_SIGNAL_VOLTAGE_120:
1989 if (!(host->flags & SDHCI_SIGNALING_120))
1990 return -EINVAL;
1991 if (!IS_ERR(mmc->supply.vqmmc)) {
1992 ret = mmc_regulator_set_vqmmc(mmc, ios);
1993 if (ret) {
1994 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1995 mmc_hostname(mmc));
1996 return -EIO;
1997 }
1998 }
1999 return 0;
2000 default:
2001 /* No signal voltage switch required */
2002 return 0;
2003 }
2004}
2005EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2006
2007static int sdhci_card_busy(struct mmc_host *mmc)
2008{
2009 struct sdhci_host *host = mmc_priv(mmc);
2010 u32 present_state;
2011
2012 /* Check whether DAT[0] is 0 */
2013 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2014
2015 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2016}
2017
2018static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2019{
2020 struct sdhci_host *host = mmc_priv(mmc);
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&host->lock, flags);
2024 host->flags |= SDHCI_HS400_TUNING;
2025 spin_unlock_irqrestore(&host->lock, flags);
2026
2027 return 0;
2028}
2029
2030static void sdhci_start_tuning(struct sdhci_host *host)
2031{
2032 u16 ctrl;
2033
2034 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2036 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2037 ctrl |= SDHCI_CTRL_TUNED_CLK;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039
2040 /*
2041 * As per the Host Controller spec v3.00, tuning command
2042 * generates Buffer Read Ready interrupt, so enable that.
2043 *
2044 * Note: The spec clearly says that when tuning sequence
2045 * is being performed, the controller does not generate
2046 * interrupts other than Buffer Read Ready interrupt. But
2047 * to make sure we don't hit a controller bug, we _only_
2048 * enable Buffer Read Ready interrupt here.
2049 */
2050 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2051 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2052}
2053
2054static void sdhci_end_tuning(struct sdhci_host *host)
2055{
2056 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2057 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2058}
2059
2060static void sdhci_reset_tuning(struct sdhci_host *host)
2061{
2062 u16 ctrl;
2063
2064 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068}
2069
2070static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2071{
2072 sdhci_reset_tuning(host);
2073
2074 sdhci_do_reset(host, SDHCI_RESET_CMD);
2075 sdhci_do_reset(host, SDHCI_RESET_DATA);
2076
2077 sdhci_end_tuning(host);
2078
2079 mmc_abort_tuning(host->mmc, opcode);
2080}
2081
2082/*
2083 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2084 * tuning command does not have a data payload (or rather the hardware does it
2085 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2086 * interrupt setup is different to other commands and there is no timeout
2087 * interrupt so special handling is needed.
2088 */
2089static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2090{
2091 struct mmc_host *mmc = host->mmc;
2092 struct mmc_command cmd = {};
2093 struct mmc_request mrq = {};
2094 unsigned long flags;
2095 u32 b = host->sdma_boundary;
2096
2097 spin_lock_irqsave(&host->lock, flags);
2098
2099 cmd.opcode = opcode;
2100 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2101 cmd.mrq = &mrq;
2102
2103 mrq.cmd = &cmd;
2104 /*
2105 * In response to CMD19, the card sends 64 bytes of tuning
2106 * block to the Host Controller. So we set the block size
2107 * to 64 here.
2108 */
2109 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2110 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2111 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2112 else
2113 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2114
2115 /*
2116 * The tuning block is sent by the card to the host controller.
2117 * So we set the TRNS_READ bit in the Transfer Mode register.
2118 * This also takes care of setting DMA Enable and Multi Block
2119 * Select in the same register to 0.
2120 */
2121 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2122
2123 sdhci_send_command(host, &cmd);
2124
2125 host->cmd = NULL;
2126
2127 sdhci_del_timer(host, &mrq);
2128
2129 host->tuning_done = 0;
2130
2131 mmiowb();
2132 spin_unlock_irqrestore(&host->lock, flags);
2133
2134 /* Wait for Buffer Read Ready interrupt */
2135 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2136 msecs_to_jiffies(50));
2137
2138}
2139
2140static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2141{
2142 int i;
2143
2144 /*
2145 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2146 * of loops reaches 40 times.
2147 */
2148 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2149 u16 ctrl;
2150
2151 sdhci_send_tuning(host, opcode);
2152
2153 if (!host->tuning_done) {
2154 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2155 mmc_hostname(host->mmc));
2156 sdhci_abort_tuning(host, opcode);
2157 return;
2158 }
2159
2160 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2161 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2162 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2163 return; /* Success! */
2164 break;
2165 }
2166
2167 /* Spec does not require a delay between tuning cycles */
2168 if (host->tuning_delay > 0)
2169 mdelay(host->tuning_delay);
2170 }
2171
2172 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2173 mmc_hostname(host->mmc));
2174 sdhci_reset_tuning(host);
2175}
2176
2177int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2178{
2179 struct sdhci_host *host = mmc_priv(mmc);
2180 int err = 0;
2181 unsigned int tuning_count = 0;
2182 bool hs400_tuning;
2183
2184 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2185
2186 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2187 tuning_count = host->tuning_count;
2188
2189 /*
2190 * The Host Controller needs tuning in case of SDR104 and DDR50
2191 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2192 * the Capabilities register.
2193 * If the Host Controller supports the HS200 mode then the
2194 * tuning function has to be executed.
2195 */
2196 switch (host->timing) {
2197 /* HS400 tuning is done in HS200 mode */
2198 case MMC_TIMING_MMC_HS400:
2199 err = -EINVAL;
2200 goto out;
2201
2202 case MMC_TIMING_MMC_HS200:
2203 /*
2204 * Periodic re-tuning for HS400 is not expected to be needed, so
2205 * disable it here.
2206 */
2207 if (hs400_tuning)
2208 tuning_count = 0;
2209 break;
2210
2211 case MMC_TIMING_UHS_SDR104:
2212 case MMC_TIMING_UHS_DDR50:
2213 break;
2214
2215 case MMC_TIMING_UHS_SDR50:
2216 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2217 break;
2218 /* FALLTHROUGH */
2219
2220 default:
2221 goto out;
2222 }
2223
2224 if (host->ops->platform_execute_tuning) {
2225 err = host->ops->platform_execute_tuning(host, opcode);
2226 goto out;
2227 }
2228
2229 host->mmc->retune_period = tuning_count;
2230
2231 if (host->tuning_delay < 0)
2232 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2233
2234 sdhci_start_tuning(host);
2235
2236 __sdhci_execute_tuning(host, opcode);
2237
2238 sdhci_end_tuning(host);
2239out:
2240 host->flags &= ~SDHCI_HS400_TUNING;
2241
2242 return err;
2243}
2244EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2245
2246static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2247{
2248 /* Host Controller v3.00 defines preset value registers */
2249 if (host->version < SDHCI_SPEC_300)
2250 return;
2251
2252 /*
2253 * We only enable or disable Preset Value if they are not already
2254 * enabled or disabled respectively. Otherwise, we bail out.
2255 */
2256 if (host->preset_enabled != enable) {
2257 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2258
2259 if (enable)
2260 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2261 else
2262 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2263
2264 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2265
2266 if (enable)
2267 host->flags |= SDHCI_PV_ENABLED;
2268 else
2269 host->flags &= ~SDHCI_PV_ENABLED;
2270
2271 host->preset_enabled = enable;
2272 }
2273}
2274
2275static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2276 int err)
2277{
2278 struct sdhci_host *host = mmc_priv(mmc);
2279 struct mmc_data *data = mrq->data;
2280
2281 if (data->host_cookie != COOKIE_UNMAPPED)
2282 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2283 mmc_get_dma_dir(data));
2284
2285 data->host_cookie = COOKIE_UNMAPPED;
2286}
2287
2288static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2289{
2290 struct sdhci_host *host = mmc_priv(mmc);
2291
2292 mrq->data->host_cookie = COOKIE_UNMAPPED;
2293
2294 /*
2295 * No pre-mapping in the pre hook if we're using the bounce buffer,
2296 * for that we would need two bounce buffers since one buffer is
2297 * in flight when this is getting called.
2298 */
2299 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2300 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2301}
2302
2303static inline bool sdhci_has_requests(struct sdhci_host *host)
2304{
2305 return host->cmd || host->data_cmd;
2306}
2307
2308static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2309{
2310 if (host->data_cmd) {
2311 host->data_cmd->error = err;
2312 sdhci_finish_mrq(host, host->data_cmd->mrq);
2313 }
2314
2315 if (host->cmd) {
2316 host->cmd->error = err;
2317 sdhci_finish_mrq(host, host->cmd->mrq);
2318 }
2319}
2320
2321static void sdhci_card_event(struct mmc_host *mmc)
2322{
2323 struct sdhci_host *host = mmc_priv(mmc);
2324 unsigned long flags;
2325 int present;
2326
2327 /* First check if client has provided their own card event */
2328 if (host->ops->card_event)
2329 host->ops->card_event(host);
2330
2331 present = mmc->ops->get_cd(mmc);
2332
2333 spin_lock_irqsave(&host->lock, flags);
2334
2335 /* Check sdhci_has_requests() first in case we are runtime suspended */
2336 if (sdhci_has_requests(host) && !present) {
2337 pr_err("%s: Card removed during transfer!\n",
2338 mmc_hostname(host->mmc));
2339 pr_err("%s: Resetting controller.\n",
2340 mmc_hostname(host->mmc));
2341
2342 sdhci_do_reset(host, SDHCI_RESET_CMD);
2343 sdhci_do_reset(host, SDHCI_RESET_DATA);
2344
2345 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2346 }
2347
2348 spin_unlock_irqrestore(&host->lock, flags);
2349}
2350
2351static const struct mmc_host_ops sdhci_ops = {
2352 .request = sdhci_request,
2353 .post_req = sdhci_post_req,
2354 .pre_req = sdhci_pre_req,
2355 .set_ios = sdhci_set_ios,
2356 .get_cd = sdhci_get_cd,
2357 .get_ro = sdhci_get_ro,
2358 .hw_reset = sdhci_hw_reset,
2359 .enable_sdio_irq = sdhci_enable_sdio_irq,
2360 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2361 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2362 .execute_tuning = sdhci_execute_tuning,
2363 .card_event = sdhci_card_event,
2364 .card_busy = sdhci_card_busy,
2365};
2366
2367/*****************************************************************************\
2368 * *
2369 * Tasklets *
2370 * *
2371\*****************************************************************************/
2372
2373static bool sdhci_request_done(struct sdhci_host *host)
2374{
2375 unsigned long flags;
2376 struct mmc_request *mrq;
2377 int i;
2378
2379 spin_lock_irqsave(&host->lock, flags);
2380
2381 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2382 mrq = host->mrqs_done[i];
2383 if (mrq)
2384 break;
2385 }
2386
2387 if (!mrq) {
2388 spin_unlock_irqrestore(&host->lock, flags);
2389 return true;
2390 }
2391
2392 sdhci_del_timer(host, mrq);
2393
2394 /*
2395 * Always unmap the data buffers if they were mapped by
2396 * sdhci_prepare_data() whenever we finish with a request.
2397 * This avoids leaking DMA mappings on error.
2398 */
2399 if (host->flags & SDHCI_REQ_USE_DMA) {
2400 struct mmc_data *data = mrq->data;
2401
2402 if (data && data->host_cookie == COOKIE_MAPPED) {
2403 if (host->bounce_buffer) {
2404 /*
2405 * On reads, copy the bounced data into the
2406 * sglist
2407 */
2408 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2409 unsigned int length = data->bytes_xfered;
2410
2411 if (length > host->bounce_buffer_size) {
2412 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2413 mmc_hostname(host->mmc),
2414 host->bounce_buffer_size,
2415 data->bytes_xfered);
2416 /* Cap it down and continue */
2417 length = host->bounce_buffer_size;
2418 }
2419 dma_sync_single_for_cpu(
2420 host->mmc->parent,
2421 host->bounce_addr,
2422 host->bounce_buffer_size,
2423 DMA_FROM_DEVICE);
2424 sg_copy_from_buffer(data->sg,
2425 data->sg_len,
2426 host->bounce_buffer,
2427 length);
2428 } else {
2429 /* No copying, just switch ownership */
2430 dma_sync_single_for_cpu(
2431 host->mmc->parent,
2432 host->bounce_addr,
2433 host->bounce_buffer_size,
2434 mmc_get_dma_dir(data));
2435 }
2436 } else {
2437 /* Unmap the raw data */
2438 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2439 data->sg_len,
2440 mmc_get_dma_dir(data));
2441 }
2442 data->host_cookie = COOKIE_UNMAPPED;
2443 }
2444 }
2445
2446 /*
2447 * The controller needs a reset of internal state machines
2448 * upon error conditions.
2449 */
2450 if (sdhci_needs_reset(host, mrq)) {
2451 /*
2452 * Do not finish until command and data lines are available for
2453 * reset. Note there can only be one other mrq, so it cannot
2454 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2455 * would both be null.
2456 */
2457 if (host->cmd || host->data_cmd) {
2458 spin_unlock_irqrestore(&host->lock, flags);
2459 return true;
2460 }
2461
2462 /* Some controllers need this kick or reset won't work here */
2463 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2464 /* This is to force an update */
2465 host->ops->set_clock(host, host->clock);
2466
2467 /* Spec says we should do both at the same time, but Ricoh
2468 controllers do not like that. */
2469 sdhci_do_reset(host, SDHCI_RESET_CMD);
2470 sdhci_do_reset(host, SDHCI_RESET_DATA);
2471
2472 host->pending_reset = false;
2473 }
2474
2475 if (!sdhci_has_requests(host))
2476 sdhci_led_deactivate(host);
2477
2478 host->mrqs_done[i] = NULL;
2479
2480 mmiowb();
2481 spin_unlock_irqrestore(&host->lock, flags);
2482
2483 mmc_request_done(host->mmc, mrq);
2484
2485 return false;
2486}
2487
2488static void sdhci_tasklet_finish(unsigned long param)
2489{
2490 struct sdhci_host *host = (struct sdhci_host *)param;
2491
2492 while (!sdhci_request_done(host))
2493 ;
2494}
2495
2496static void sdhci_timeout_timer(struct timer_list *t)
2497{
2498 struct sdhci_host *host;
2499 unsigned long flags;
2500
2501 host = from_timer(host, t, timer);
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2506 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2507 mmc_hostname(host->mmc));
2508 sdhci_dumpregs(host);
2509
2510 host->cmd->error = -ETIMEDOUT;
2511 sdhci_finish_mrq(host, host->cmd->mrq);
2512 }
2513
2514 mmiowb();
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518static void sdhci_timeout_data_timer(struct timer_list *t)
2519{
2520 struct sdhci_host *host;
2521 unsigned long flags;
2522
2523 host = from_timer(host, t, data_timer);
2524
2525 spin_lock_irqsave(&host->lock, flags);
2526
2527 if (host->data || host->data_cmd ||
2528 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2529 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2530 mmc_hostname(host->mmc));
2531 sdhci_dumpregs(host);
2532
2533 if (host->data) {
2534 host->data->error = -ETIMEDOUT;
2535 sdhci_finish_data(host);
2536 } else if (host->data_cmd) {
2537 host->data_cmd->error = -ETIMEDOUT;
2538 sdhci_finish_mrq(host, host->data_cmd->mrq);
2539 } else {
2540 host->cmd->error = -ETIMEDOUT;
2541 sdhci_finish_mrq(host, host->cmd->mrq);
2542 }
2543 }
2544
2545 mmiowb();
2546 spin_unlock_irqrestore(&host->lock, flags);
2547}
2548
2549/*****************************************************************************\
2550 * *
2551 * Interrupt handling *
2552 * *
2553\*****************************************************************************/
2554
2555static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2556{
2557 if (!host->cmd) {
2558 /*
2559 * SDHCI recovers from errors by resetting the cmd and data
2560 * circuits. Until that is done, there very well might be more
2561 * interrupts, so ignore them in that case.
2562 */
2563 if (host->pending_reset)
2564 return;
2565 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2566 mmc_hostname(host->mmc), (unsigned)intmask);
2567 sdhci_dumpregs(host);
2568 return;
2569 }
2570
2571 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2572 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2573 if (intmask & SDHCI_INT_TIMEOUT)
2574 host->cmd->error = -ETIMEDOUT;
2575 else
2576 host->cmd->error = -EILSEQ;
2577
2578 /*
2579 * If this command initiates a data phase and a response
2580 * CRC error is signalled, the card can start transferring
2581 * data - the card may have received the command without
2582 * error. We must not terminate the mmc_request early.
2583 *
2584 * If the card did not receive the command or returned an
2585 * error which prevented it sending data, the data phase
2586 * will time out.
2587 */
2588 if (host->cmd->data &&
2589 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2590 SDHCI_INT_CRC) {
2591 host->cmd = NULL;
2592 return;
2593 }
2594
2595 sdhci_finish_mrq(host, host->cmd->mrq);
2596 return;
2597 }
2598
2599 if (intmask & SDHCI_INT_RESPONSE)
2600 sdhci_finish_command(host);
2601}
2602
2603static void sdhci_adma_show_error(struct sdhci_host *host)
2604{
2605 void *desc = host->adma_table;
2606
2607 sdhci_dumpregs(host);
2608
2609 while (true) {
2610 struct sdhci_adma2_64_desc *dma_desc = desc;
2611
2612 if (host->flags & SDHCI_USE_64_BIT_DMA)
2613 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2614 desc, le32_to_cpu(dma_desc->addr_hi),
2615 le32_to_cpu(dma_desc->addr_lo),
2616 le16_to_cpu(dma_desc->len),
2617 le16_to_cpu(dma_desc->cmd));
2618 else
2619 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2620 desc, le32_to_cpu(dma_desc->addr_lo),
2621 le16_to_cpu(dma_desc->len),
2622 le16_to_cpu(dma_desc->cmd));
2623
2624 desc += host->desc_sz;
2625
2626 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2627 break;
2628 }
2629}
2630
2631static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2632{
2633 u32 command;
2634
2635 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2636 if (intmask & SDHCI_INT_DATA_AVAIL) {
2637 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2638 if (command == MMC_SEND_TUNING_BLOCK ||
2639 command == MMC_SEND_TUNING_BLOCK_HS200) {
2640 host->tuning_done = 1;
2641 wake_up(&host->buf_ready_int);
2642 return;
2643 }
2644 }
2645
2646 if (!host->data) {
2647 struct mmc_command *data_cmd = host->data_cmd;
2648
2649 /*
2650 * The "data complete" interrupt is also used to
2651 * indicate that a busy state has ended. See comment
2652 * above in sdhci_cmd_irq().
2653 */
2654 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2655 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2656 host->data_cmd = NULL;
2657 data_cmd->error = -ETIMEDOUT;
2658 sdhci_finish_mrq(host, data_cmd->mrq);
2659 return;
2660 }
2661 if (intmask & SDHCI_INT_DATA_END) {
2662 host->data_cmd = NULL;
2663 /*
2664 * Some cards handle busy-end interrupt
2665 * before the command completed, so make
2666 * sure we do things in the proper order.
2667 */
2668 if (host->cmd == data_cmd)
2669 return;
2670
2671 sdhci_finish_mrq(host, data_cmd->mrq);
2672 return;
2673 }
2674 }
2675
2676 /*
2677 * SDHCI recovers from errors by resetting the cmd and data
2678 * circuits. Until that is done, there very well might be more
2679 * interrupts, so ignore them in that case.
2680 */
2681 if (host->pending_reset)
2682 return;
2683
2684 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2685 mmc_hostname(host->mmc), (unsigned)intmask);
2686 sdhci_dumpregs(host);
2687
2688 return;
2689 }
2690
2691 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2692 host->data->error = -ETIMEDOUT;
2693 else if (intmask & SDHCI_INT_DATA_END_BIT)
2694 host->data->error = -EILSEQ;
2695 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2696 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2697 != MMC_BUS_TEST_R)
2698 host->data->error = -EILSEQ;
2699 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2700 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2701 sdhci_adma_show_error(host);
2702 host->data->error = -EIO;
2703 if (host->ops->adma_workaround)
2704 host->ops->adma_workaround(host, intmask);
2705 }
2706
2707 if (host->data->error)
2708 sdhci_finish_data(host);
2709 else {
2710 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2711 sdhci_transfer_pio(host);
2712
2713 /*
2714 * We currently don't do anything fancy with DMA
2715 * boundaries, but as we can't disable the feature
2716 * we need to at least restart the transfer.
2717 *
2718 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2719 * should return a valid address to continue from, but as
2720 * some controllers are faulty, don't trust them.
2721 */
2722 if (intmask & SDHCI_INT_DMA_END) {
2723 u32 dmastart, dmanow;
2724
2725 dmastart = sdhci_sdma_address(host);
2726 dmanow = dmastart + host->data->bytes_xfered;
2727 /*
2728 * Force update to the next DMA block boundary.
2729 */
2730 dmanow = (dmanow &
2731 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2732 SDHCI_DEFAULT_BOUNDARY_SIZE;
2733 host->data->bytes_xfered = dmanow - dmastart;
2734 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2735 dmastart, host->data->bytes_xfered, dmanow);
2736 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2737 }
2738
2739 if (intmask & SDHCI_INT_DATA_END) {
2740 if (host->cmd == host->data_cmd) {
2741 /*
2742 * Data managed to finish before the
2743 * command completed. Make sure we do
2744 * things in the proper order.
2745 */
2746 host->data_early = 1;
2747 } else {
2748 sdhci_finish_data(host);
2749 }
2750 }
2751 }
2752}
2753
2754static irqreturn_t sdhci_irq(int irq, void *dev_id)
2755{
2756 irqreturn_t result = IRQ_NONE;
2757 struct sdhci_host *host = dev_id;
2758 u32 intmask, mask, unexpected = 0;
2759 int max_loops = 16;
2760
2761 spin_lock(&host->lock);
2762
2763 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2764 spin_unlock(&host->lock);
2765 return IRQ_NONE;
2766 }
2767
2768 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2769 if (!intmask || intmask == 0xffffffff) {
2770 result = IRQ_NONE;
2771 goto out;
2772 }
2773
2774 do {
2775 DBG("IRQ status 0x%08x\n", intmask);
2776
2777 if (host->ops->irq) {
2778 intmask = host->ops->irq(host, intmask);
2779 if (!intmask)
2780 goto cont;
2781 }
2782
2783 /* Clear selected interrupts. */
2784 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2785 SDHCI_INT_BUS_POWER);
2786 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2787
2788 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2789 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2790 SDHCI_CARD_PRESENT;
2791
2792 /*
2793 * There is a observation on i.mx esdhc. INSERT
2794 * bit will be immediately set again when it gets
2795 * cleared, if a card is inserted. We have to mask
2796 * the irq to prevent interrupt storm which will
2797 * freeze the system. And the REMOVE gets the
2798 * same situation.
2799 *
2800 * More testing are needed here to ensure it works
2801 * for other platforms though.
2802 */
2803 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2804 SDHCI_INT_CARD_REMOVE);
2805 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2806 SDHCI_INT_CARD_INSERT;
2807 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2808 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2809
2810 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2811 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2812
2813 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2814 SDHCI_INT_CARD_REMOVE);
2815 result = IRQ_WAKE_THREAD;
2816 }
2817
2818 if (intmask & SDHCI_INT_CMD_MASK)
2819 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2820
2821 if (intmask & SDHCI_INT_DATA_MASK)
2822 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2823
2824 if (intmask & SDHCI_INT_BUS_POWER)
2825 pr_err("%s: Card is consuming too much power!\n",
2826 mmc_hostname(host->mmc));
2827
2828 if (intmask & SDHCI_INT_RETUNE)
2829 mmc_retune_needed(host->mmc);
2830
2831 if ((intmask & SDHCI_INT_CARD_INT) &&
2832 (host->ier & SDHCI_INT_CARD_INT)) {
2833 sdhci_enable_sdio_irq_nolock(host, false);
2834 host->thread_isr |= SDHCI_INT_CARD_INT;
2835 result = IRQ_WAKE_THREAD;
2836 }
2837
2838 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2839 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2840 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2841 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2842
2843 if (intmask) {
2844 unexpected |= intmask;
2845 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2846 }
2847cont:
2848 if (result == IRQ_NONE)
2849 result = IRQ_HANDLED;
2850
2851 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2852 } while (intmask && --max_loops);
2853out:
2854 spin_unlock(&host->lock);
2855
2856 if (unexpected) {
2857 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2858 mmc_hostname(host->mmc), unexpected);
2859 sdhci_dumpregs(host);
2860 }
2861
2862 return result;
2863}
2864
2865static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2866{
2867 struct sdhci_host *host = dev_id;
2868 unsigned long flags;
2869 u32 isr;
2870
2871 spin_lock_irqsave(&host->lock, flags);
2872 isr = host->thread_isr;
2873 host->thread_isr = 0;
2874 spin_unlock_irqrestore(&host->lock, flags);
2875
2876 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2877 struct mmc_host *mmc = host->mmc;
2878
2879 mmc->ops->card_event(mmc);
2880 mmc_detect_change(mmc, msecs_to_jiffies(200));
2881 }
2882
2883 if (isr & SDHCI_INT_CARD_INT) {
2884 sdio_run_irqs(host->mmc);
2885
2886 spin_lock_irqsave(&host->lock, flags);
2887 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2888 sdhci_enable_sdio_irq_nolock(host, true);
2889 spin_unlock_irqrestore(&host->lock, flags);
2890 }
2891
2892 return isr ? IRQ_HANDLED : IRQ_NONE;
2893}
2894
2895/*****************************************************************************\
2896 * *
2897 * Suspend/resume *
2898 * *
2899\*****************************************************************************/
2900
2901#ifdef CONFIG_PM
2902
2903static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
2904{
2905 return mmc_card_is_removable(host->mmc) &&
2906 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2907 !mmc_can_gpio_cd(host->mmc);
2908}
2909
2910/*
2911 * To enable wakeup events, the corresponding events have to be enabled in
2912 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2913 * Table' in the SD Host Controller Standard Specification.
2914 * It is useless to restore SDHCI_INT_ENABLE state in
2915 * sdhci_disable_irq_wakeups() since it will be set by
2916 * sdhci_enable_card_detection() or sdhci_init().
2917 */
2918static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
2919{
2920 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
2921 SDHCI_WAKE_ON_INT;
2922 u32 irq_val = 0;
2923 u8 wake_val = 0;
2924 u8 val;
2925
2926 if (sdhci_cd_irq_can_wakeup(host)) {
2927 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
2928 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
2929 }
2930
2931 if (mmc_card_wake_sdio_irq(host->mmc)) {
2932 wake_val |= SDHCI_WAKE_ON_INT;
2933 irq_val |= SDHCI_INT_CARD_INT;
2934 }
2935
2936 if (!irq_val)
2937 return false;
2938
2939 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2940 val &= ~mask;
2941 val |= wake_val;
2942 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2943
2944 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2945
2946 host->irq_wake_enabled = !enable_irq_wake(host->irq);
2947
2948 return host->irq_wake_enabled;
2949}
2950
2951static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2952{
2953 u8 val;
2954 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2955 | SDHCI_WAKE_ON_INT;
2956
2957 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2958 val &= ~mask;
2959 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2960
2961 disable_irq_wake(host->irq);
2962
2963 host->irq_wake_enabled = false;
2964}
2965
2966int sdhci_suspend_host(struct sdhci_host *host)
2967{
2968 sdhci_disable_card_detection(host);
2969
2970 mmc_retune_timer_stop(host->mmc);
2971
2972 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
2973 !sdhci_enable_irq_wakeups(host)) {
2974 host->ier = 0;
2975 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2976 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2977 free_irq(host->irq, host);
2978 }
2979
2980 return 0;
2981}
2982
2983EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2984
2985int sdhci_resume_host(struct sdhci_host *host)
2986{
2987 struct mmc_host *mmc = host->mmc;
2988 int ret = 0;
2989
2990 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2991 if (host->ops->enable_dma)
2992 host->ops->enable_dma(host);
2993 }
2994
2995 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2996 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2997 /* Card keeps power but host controller does not */
2998 sdhci_init(host, 0);
2999 host->pwr = 0;
3000 host->clock = 0;
3001 mmc->ops->set_ios(mmc, &mmc->ios);
3002 } else {
3003 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3004 mmiowb();
3005 }
3006
3007 if (host->irq_wake_enabled) {
3008 sdhci_disable_irq_wakeups(host);
3009 } else {
3010 ret = request_threaded_irq(host->irq, sdhci_irq,
3011 sdhci_thread_irq, IRQF_SHARED,
3012 mmc_hostname(host->mmc), host);
3013 if (ret)
3014 return ret;
3015 }
3016
3017 sdhci_enable_card_detection(host);
3018
3019 return ret;
3020}
3021
3022EXPORT_SYMBOL_GPL(sdhci_resume_host);
3023
3024int sdhci_runtime_suspend_host(struct sdhci_host *host)
3025{
3026 unsigned long flags;
3027
3028 mmc_retune_timer_stop(host->mmc);
3029
3030 spin_lock_irqsave(&host->lock, flags);
3031 host->ier &= SDHCI_INT_CARD_INT;
3032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3034 spin_unlock_irqrestore(&host->lock, flags);
3035
3036 synchronize_hardirq(host->irq);
3037
3038 spin_lock_irqsave(&host->lock, flags);
3039 host->runtime_suspended = true;
3040 spin_unlock_irqrestore(&host->lock, flags);
3041
3042 return 0;
3043}
3044EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3045
3046int sdhci_runtime_resume_host(struct sdhci_host *host)
3047{
3048 struct mmc_host *mmc = host->mmc;
3049 unsigned long flags;
3050 int host_flags = host->flags;
3051
3052 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3053 if (host->ops->enable_dma)
3054 host->ops->enable_dma(host);
3055 }
3056
3057 sdhci_init(host, 0);
3058
3059 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3060 mmc->ios.power_mode != MMC_POWER_OFF) {
3061 /* Force clock and power re-program */
3062 host->pwr = 0;
3063 host->clock = 0;
3064 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3065 mmc->ops->set_ios(mmc, &mmc->ios);
3066
3067 if ((host_flags & SDHCI_PV_ENABLED) &&
3068 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3069 spin_lock_irqsave(&host->lock, flags);
3070 sdhci_enable_preset_value(host, true);
3071 spin_unlock_irqrestore(&host->lock, flags);
3072 }
3073
3074 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3075 mmc->ops->hs400_enhanced_strobe)
3076 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3077 }
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 host->runtime_suspended = false;
3082
3083 /* Enable SDIO IRQ */
3084 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3085 sdhci_enable_sdio_irq_nolock(host, true);
3086
3087 /* Enable Card Detection */
3088 sdhci_enable_card_detection(host);
3089
3090 spin_unlock_irqrestore(&host->lock, flags);
3091
3092 return 0;
3093}
3094EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3095
3096#endif /* CONFIG_PM */
3097
3098/*****************************************************************************\
3099 * *
3100 * Command Queue Engine (CQE) helpers *
3101 * *
3102\*****************************************************************************/
3103
3104void sdhci_cqe_enable(struct mmc_host *mmc)
3105{
3106 struct sdhci_host *host = mmc_priv(mmc);
3107 unsigned long flags;
3108 u8 ctrl;
3109
3110 spin_lock_irqsave(&host->lock, flags);
3111
3112 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3113 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3114 if (host->flags & SDHCI_USE_64_BIT_DMA)
3115 ctrl |= SDHCI_CTRL_ADMA64;
3116 else
3117 ctrl |= SDHCI_CTRL_ADMA32;
3118 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3119
3120 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3121 SDHCI_BLOCK_SIZE);
3122
3123 /* Set maximum timeout */
3124 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3125
3126 host->ier = host->cqe_ier;
3127
3128 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3129 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3130
3131 host->cqe_on = true;
3132
3133 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3134 mmc_hostname(mmc), host->ier,
3135 sdhci_readl(host, SDHCI_INT_STATUS));
3136
3137 mmiowb();
3138 spin_unlock_irqrestore(&host->lock, flags);
3139}
3140EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3141
3142void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3143{
3144 struct sdhci_host *host = mmc_priv(mmc);
3145 unsigned long flags;
3146
3147 spin_lock_irqsave(&host->lock, flags);
3148
3149 sdhci_set_default_irqs(host);
3150
3151 host->cqe_on = false;
3152
3153 if (recovery) {
3154 sdhci_do_reset(host, SDHCI_RESET_CMD);
3155 sdhci_do_reset(host, SDHCI_RESET_DATA);
3156 }
3157
3158 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3159 mmc_hostname(mmc), host->ier,
3160 sdhci_readl(host, SDHCI_INT_STATUS));
3161
3162 mmiowb();
3163 spin_unlock_irqrestore(&host->lock, flags);
3164}
3165EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3166
3167bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3168 int *data_error)
3169{
3170 u32 mask;
3171
3172 if (!host->cqe_on)
3173 return false;
3174
3175 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3176 *cmd_error = -EILSEQ;
3177 else if (intmask & SDHCI_INT_TIMEOUT)
3178 *cmd_error = -ETIMEDOUT;
3179 else
3180 *cmd_error = 0;
3181
3182 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3183 *data_error = -EILSEQ;
3184 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3185 *data_error = -ETIMEDOUT;
3186 else if (intmask & SDHCI_INT_ADMA_ERROR)
3187 *data_error = -EIO;
3188 else
3189 *data_error = 0;
3190
3191 /* Clear selected interrupts. */
3192 mask = intmask & host->cqe_ier;
3193 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3194
3195 if (intmask & SDHCI_INT_BUS_POWER)
3196 pr_err("%s: Card is consuming too much power!\n",
3197 mmc_hostname(host->mmc));
3198
3199 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3200 if (intmask) {
3201 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3202 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3203 mmc_hostname(host->mmc), intmask);
3204 sdhci_dumpregs(host);
3205 }
3206
3207 return true;
3208}
3209EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3210
3211/*****************************************************************************\
3212 * *
3213 * Device allocation/registration *
3214 * *
3215\*****************************************************************************/
3216
3217struct sdhci_host *sdhci_alloc_host(struct device *dev,
3218 size_t priv_size)
3219{
3220 struct mmc_host *mmc;
3221 struct sdhci_host *host;
3222
3223 WARN_ON(dev == NULL);
3224
3225 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3226 if (!mmc)
3227 return ERR_PTR(-ENOMEM);
3228
3229 host = mmc_priv(mmc);
3230 host->mmc = mmc;
3231 host->mmc_host_ops = sdhci_ops;
3232 mmc->ops = &host->mmc_host_ops;
3233
3234 host->flags = SDHCI_SIGNALING_330;
3235
3236 host->cqe_ier = SDHCI_CQE_INT_MASK;
3237 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3238
3239 host->tuning_delay = -1;
3240
3241 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3242
3243 return host;
3244}
3245
3246EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3247
3248static int sdhci_set_dma_mask(struct sdhci_host *host)
3249{
3250 struct mmc_host *mmc = host->mmc;
3251 struct device *dev = mmc_dev(mmc);
3252 int ret = -EINVAL;
3253
3254 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3255 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3256
3257 /* Try 64-bit mask if hardware is capable of it */
3258 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3259 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3260 if (ret) {
3261 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3262 mmc_hostname(mmc));
3263 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3264 }
3265 }
3266
3267 /* 32-bit mask as default & fallback */
3268 if (ret) {
3269 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3270 if (ret)
3271 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3272 mmc_hostname(mmc));
3273 }
3274
3275 return ret;
3276}
3277
3278void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3279{
3280 u16 v;
3281 u64 dt_caps_mask = 0;
3282 u64 dt_caps = 0;
3283
3284 if (host->read_caps)
3285 return;
3286
3287 host->read_caps = true;
3288
3289 if (debug_quirks)
3290 host->quirks = debug_quirks;
3291
3292 if (debug_quirks2)
3293 host->quirks2 = debug_quirks2;
3294
3295 sdhci_do_reset(host, SDHCI_RESET_ALL);
3296
3297 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3298 "sdhci-caps-mask", &dt_caps_mask);
3299 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3300 "sdhci-caps", &dt_caps);
3301
3302 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3303 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3304
3305 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3306 return;
3307
3308 if (caps) {
3309 host->caps = *caps;
3310 } else {
3311 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3312 host->caps &= ~lower_32_bits(dt_caps_mask);
3313 host->caps |= lower_32_bits(dt_caps);
3314 }
3315
3316 if (host->version < SDHCI_SPEC_300)
3317 return;
3318
3319 if (caps1) {
3320 host->caps1 = *caps1;
3321 } else {
3322 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3323 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3324 host->caps1 |= upper_32_bits(dt_caps);
3325 }
3326}
3327EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3328
3329static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3330{
3331 struct mmc_host *mmc = host->mmc;
3332 unsigned int max_blocks;
3333 unsigned int bounce_size;
3334 int ret;
3335
3336 /*
3337 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3338 * has diminishing returns, this is probably because SD/MMC
3339 * cards are usually optimized to handle this size of requests.
3340 */
3341 bounce_size = SZ_64K;
3342 /*
3343 * Adjust downwards to maximum request size if this is less
3344 * than our segment size, else hammer down the maximum
3345 * request size to the maximum buffer size.
3346 */
3347 if (mmc->max_req_size < bounce_size)
3348 bounce_size = mmc->max_req_size;
3349 max_blocks = bounce_size / 512;
3350
3351 /*
3352 * When we just support one segment, we can get significant
3353 * speedups by the help of a bounce buffer to group scattered
3354 * reads/writes together.
3355 */
3356 host->bounce_buffer = devm_kmalloc(mmc->parent,
3357 bounce_size,
3358 GFP_KERNEL);
3359 if (!host->bounce_buffer) {
3360 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3361 mmc_hostname(mmc),
3362 bounce_size);
3363 /*
3364 * Exiting with zero here makes sure we proceed with
3365 * mmc->max_segs == 1.
3366 */
3367 return 0;
3368 }
3369
3370 host->bounce_addr = dma_map_single(mmc->parent,
3371 host->bounce_buffer,
3372 bounce_size,
3373 DMA_BIDIRECTIONAL);
3374 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3375 if (ret)
3376 /* Again fall back to max_segs == 1 */
3377 return 0;
3378 host->bounce_buffer_size = bounce_size;
3379
3380 /* Lie about this since we're bouncing */
3381 mmc->max_segs = max_blocks;
3382 mmc->max_seg_size = bounce_size;
3383 mmc->max_req_size = bounce_size;
3384
3385 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3386 mmc_hostname(mmc), max_blocks, bounce_size);
3387
3388 return 0;
3389}
3390
3391int sdhci_setup_host(struct sdhci_host *host)
3392{
3393 struct mmc_host *mmc;
3394 u32 max_current_caps;
3395 unsigned int ocr_avail;
3396 unsigned int override_timeout_clk;
3397 u32 max_clk;
3398 int ret;
3399
3400 WARN_ON(host == NULL);
3401 if (host == NULL)
3402 return -EINVAL;
3403
3404 mmc = host->mmc;
3405
3406 /*
3407 * If there are external regulators, get them. Note this must be done
3408 * early before resetting the host and reading the capabilities so that
3409 * the host can take the appropriate action if regulators are not
3410 * available.
3411 */
3412 ret = mmc_regulator_get_supply(mmc);
3413 if (ret)
3414 return ret;
3415
3416 DBG("Version: 0x%08x | Present: 0x%08x\n",
3417 sdhci_readw(host, SDHCI_HOST_VERSION),
3418 sdhci_readl(host, SDHCI_PRESENT_STATE));
3419 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3420 sdhci_readl(host, SDHCI_CAPABILITIES),
3421 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3422
3423 sdhci_read_caps(host);
3424
3425 override_timeout_clk = host->timeout_clk;
3426
3427 if (host->version > SDHCI_SPEC_300) {
3428 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3429 mmc_hostname(mmc), host->version);
3430 }
3431
3432 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3433 host->flags |= SDHCI_USE_SDMA;
3434 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3435 DBG("Controller doesn't have SDMA capability\n");
3436 else
3437 host->flags |= SDHCI_USE_SDMA;
3438
3439 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3440 (host->flags & SDHCI_USE_SDMA)) {
3441 DBG("Disabling DMA as it is marked broken\n");
3442 host->flags &= ~SDHCI_USE_SDMA;
3443 }
3444
3445 if ((host->version >= SDHCI_SPEC_200) &&
3446 (host->caps & SDHCI_CAN_DO_ADMA2))
3447 host->flags |= SDHCI_USE_ADMA;
3448
3449 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3450 (host->flags & SDHCI_USE_ADMA)) {
3451 DBG("Disabling ADMA as it is marked broken\n");
3452 host->flags &= ~SDHCI_USE_ADMA;
3453 }
3454
3455 /*
3456 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3457 * and *must* do 64-bit DMA. A driver has the opportunity to change
3458 * that during the first call to ->enable_dma(). Similarly
3459 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3460 * implement.
3461 */
3462 if (host->caps & SDHCI_CAN_64BIT)
3463 host->flags |= SDHCI_USE_64_BIT_DMA;
3464
3465 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3466 ret = sdhci_set_dma_mask(host);
3467
3468 if (!ret && host->ops->enable_dma)
3469 ret = host->ops->enable_dma(host);
3470
3471 if (ret) {
3472 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3473 mmc_hostname(mmc));
3474 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3475
3476 ret = 0;
3477 }
3478 }
3479
3480 /* SDMA does not support 64-bit DMA */
3481 if (host->flags & SDHCI_USE_64_BIT_DMA)
3482 host->flags &= ~SDHCI_USE_SDMA;
3483
3484 if (host->flags & SDHCI_USE_ADMA) {
3485 dma_addr_t dma;
3486 void *buf;
3487
3488 /*
3489 * The DMA descriptor table size is calculated as the maximum
3490 * number of segments times 2, to allow for an alignment
3491 * descriptor for each segment, plus 1 for a nop end descriptor,
3492 * all multipled by the descriptor size.
3493 */
3494 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3495 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3496 SDHCI_ADMA2_64_DESC_SZ;
3497 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3498 } else {
3499 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3500 SDHCI_ADMA2_32_DESC_SZ;
3501 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3502 }
3503
3504 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3505 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3506 host->adma_table_sz, &dma, GFP_KERNEL);
3507 if (!buf) {
3508 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3509 mmc_hostname(mmc));
3510 host->flags &= ~SDHCI_USE_ADMA;
3511 } else if ((dma + host->align_buffer_sz) &
3512 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3513 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3514 mmc_hostname(mmc));
3515 host->flags &= ~SDHCI_USE_ADMA;
3516 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3517 host->adma_table_sz, buf, dma);
3518 } else {
3519 host->align_buffer = buf;
3520 host->align_addr = dma;
3521
3522 host->adma_table = buf + host->align_buffer_sz;
3523 host->adma_addr = dma + host->align_buffer_sz;
3524 }
3525 }
3526
3527 /*
3528 * If we use DMA, then it's up to the caller to set the DMA
3529 * mask, but PIO does not need the hw shim so we set a new
3530 * mask here in that case.
3531 */
3532 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3533 host->dma_mask = DMA_BIT_MASK(64);
3534 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3535 }
3536
3537 if (host->version >= SDHCI_SPEC_300)
3538 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3539 >> SDHCI_CLOCK_BASE_SHIFT;
3540 else
3541 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3542 >> SDHCI_CLOCK_BASE_SHIFT;
3543
3544 host->max_clk *= 1000000;
3545 if (host->max_clk == 0 || host->quirks &
3546 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3547 if (!host->ops->get_max_clock) {
3548 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3549 mmc_hostname(mmc));
3550 ret = -ENODEV;
3551 goto undma;
3552 }
3553 host->max_clk = host->ops->get_max_clock(host);
3554 }
3555
3556 /*
3557 * In case of Host Controller v3.00, find out whether clock
3558 * multiplier is supported.
3559 */
3560 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3561 SDHCI_CLOCK_MUL_SHIFT;
3562
3563 /*
3564 * In case the value in Clock Multiplier is 0, then programmable
3565 * clock mode is not supported, otherwise the actual clock
3566 * multiplier is one more than the value of Clock Multiplier
3567 * in the Capabilities Register.
3568 */
3569 if (host->clk_mul)
3570 host->clk_mul += 1;
3571
3572 /*
3573 * Set host parameters.
3574 */
3575 max_clk = host->max_clk;
3576
3577 if (host->ops->get_min_clock)
3578 mmc->f_min = host->ops->get_min_clock(host);
3579 else if (host->version >= SDHCI_SPEC_300) {
3580 if (host->clk_mul) {
3581 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3582 max_clk = host->max_clk * host->clk_mul;
3583 } else
3584 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3585 } else
3586 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3587
3588 if (!mmc->f_max || mmc->f_max > max_clk)
3589 mmc->f_max = max_clk;
3590
3591 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3592 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3593 SDHCI_TIMEOUT_CLK_SHIFT;
3594
3595 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3596 host->timeout_clk *= 1000;
3597
3598 if (host->timeout_clk == 0) {
3599 if (!host->ops->get_timeout_clock) {
3600 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3601 mmc_hostname(mmc));
3602 ret = -ENODEV;
3603 goto undma;
3604 }
3605
3606 host->timeout_clk =
3607 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3608 1000);
3609 }
3610
3611 if (override_timeout_clk)
3612 host->timeout_clk = override_timeout_clk;
3613
3614 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3615 host->ops->get_max_timeout_count(host) : 1 << 27;
3616 mmc->max_busy_timeout /= host->timeout_clk;
3617 }
3618
3619 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3620 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3621
3622 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3623 host->flags |= SDHCI_AUTO_CMD12;
3624
3625 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3626 if ((host->version >= SDHCI_SPEC_300) &&
3627 ((host->flags & SDHCI_USE_ADMA) ||
3628 !(host->flags & SDHCI_USE_SDMA)) &&
3629 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3630 host->flags |= SDHCI_AUTO_CMD23;
3631 DBG("Auto-CMD23 available\n");
3632 } else {
3633 DBG("Auto-CMD23 unavailable\n");
3634 }
3635
3636 /*
3637 * A controller may support 8-bit width, but the board itself
3638 * might not have the pins brought out. Boards that support
3639 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3640 * their platform code before calling sdhci_add_host(), and we
3641 * won't assume 8-bit width for hosts without that CAP.
3642 */
3643 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3644 mmc->caps |= MMC_CAP_4_BIT_DATA;
3645
3646 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3647 mmc->caps &= ~MMC_CAP_CMD23;
3648
3649 if (host->caps & SDHCI_CAN_DO_HISPD)
3650 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3651
3652 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3653 mmc_card_is_removable(mmc) &&
3654 mmc_gpio_get_cd(host->mmc) < 0)
3655 mmc->caps |= MMC_CAP_NEEDS_POLL;
3656
3657 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3658 if (!IS_ERR(mmc->supply.vqmmc)) {
3659 ret = regulator_enable(mmc->supply.vqmmc);
3660 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3661 1950000))
3662 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3663 SDHCI_SUPPORT_SDR50 |
3664 SDHCI_SUPPORT_DDR50);
3665 if (ret) {
3666 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3667 mmc_hostname(mmc), ret);
3668 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3669 }
3670 }
3671
3672 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3673 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3674 SDHCI_SUPPORT_DDR50);
3675 }
3676
3677 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3678 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3679 SDHCI_SUPPORT_DDR50))
3680 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3681
3682 /* SDR104 supports also implies SDR50 support */
3683 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3684 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3685 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3686 * field can be promoted to support HS200.
3687 */
3688 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3689 mmc->caps2 |= MMC_CAP2_HS200;
3690 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3691 mmc->caps |= MMC_CAP_UHS_SDR50;
3692 }
3693
3694 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3695 (host->caps1 & SDHCI_SUPPORT_HS400))
3696 mmc->caps2 |= MMC_CAP2_HS400;
3697
3698 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3699 (IS_ERR(mmc->supply.vqmmc) ||
3700 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3701 1300000)))
3702 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3703
3704 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3705 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3706 mmc->caps |= MMC_CAP_UHS_DDR50;
3707
3708 /* Does the host need tuning for SDR50? */
3709 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3710 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3711
3712 /* Driver Type(s) (A, C, D) supported by the host */
3713 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3714 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3715 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3716 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3717 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3718 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3719
3720 /* Initial value for re-tuning timer count */
3721 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3722 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3723
3724 /*
3725 * In case Re-tuning Timer is not disabled, the actual value of
3726 * re-tuning timer will be 2 ^ (n - 1).
3727 */
3728 if (host->tuning_count)
3729 host->tuning_count = 1 << (host->tuning_count - 1);
3730
3731 /* Re-tuning mode supported by the Host Controller */
3732 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3733 SDHCI_RETUNING_MODE_SHIFT;
3734
3735 ocr_avail = 0;
3736
3737 /*
3738 * According to SD Host Controller spec v3.00, if the Host System
3739 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3740 * the value is meaningful only if Voltage Support in the Capabilities
3741 * register is set. The actual current value is 4 times the register
3742 * value.
3743 */
3744 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3745 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3746 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3747 if (curr > 0) {
3748
3749 /* convert to SDHCI_MAX_CURRENT format */
3750 curr = curr/1000; /* convert to mA */
3751 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3752
3753 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3754 max_current_caps =
3755 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3756 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3757 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3758 }
3759 }
3760
3761 if (host->caps & SDHCI_CAN_VDD_330) {
3762 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3763
3764 mmc->max_current_330 = ((max_current_caps &
3765 SDHCI_MAX_CURRENT_330_MASK) >>
3766 SDHCI_MAX_CURRENT_330_SHIFT) *
3767 SDHCI_MAX_CURRENT_MULTIPLIER;
3768 }
3769 if (host->caps & SDHCI_CAN_VDD_300) {
3770 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3771
3772 mmc->max_current_300 = ((max_current_caps &
3773 SDHCI_MAX_CURRENT_300_MASK) >>
3774 SDHCI_MAX_CURRENT_300_SHIFT) *
3775 SDHCI_MAX_CURRENT_MULTIPLIER;
3776 }
3777 if (host->caps & SDHCI_CAN_VDD_180) {
3778 ocr_avail |= MMC_VDD_165_195;
3779
3780 mmc->max_current_180 = ((max_current_caps &
3781 SDHCI_MAX_CURRENT_180_MASK) >>
3782 SDHCI_MAX_CURRENT_180_SHIFT) *
3783 SDHCI_MAX_CURRENT_MULTIPLIER;
3784 }
3785
3786 /* If OCR set by host, use it instead. */
3787 if (host->ocr_mask)
3788 ocr_avail = host->ocr_mask;
3789
3790 /* If OCR set by external regulators, give it highest prio. */
3791 if (mmc->ocr_avail)
3792 ocr_avail = mmc->ocr_avail;
3793
3794 mmc->ocr_avail = ocr_avail;
3795 mmc->ocr_avail_sdio = ocr_avail;
3796 if (host->ocr_avail_sdio)
3797 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3798 mmc->ocr_avail_sd = ocr_avail;
3799 if (host->ocr_avail_sd)
3800 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3801 else /* normal SD controllers don't support 1.8V */
3802 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3803 mmc->ocr_avail_mmc = ocr_avail;
3804 if (host->ocr_avail_mmc)
3805 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3806
3807 if (mmc->ocr_avail == 0) {
3808 pr_err("%s: Hardware doesn't report any support voltages.\n",
3809 mmc_hostname(mmc));
3810 ret = -ENODEV;
3811 goto unreg;
3812 }
3813
3814 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3815 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3816 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3817 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3818 host->flags |= SDHCI_SIGNALING_180;
3819
3820 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3821 host->flags |= SDHCI_SIGNALING_120;
3822
3823 spin_lock_init(&host->lock);
3824
3825 /*
3826 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3827 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3828 * is less anyway.
3829 */
3830 mmc->max_req_size = 524288;
3831
3832 /*
3833 * Maximum number of segments. Depends on if the hardware
3834 * can do scatter/gather or not.
3835 */
3836 if (host->flags & SDHCI_USE_ADMA) {
3837 mmc->max_segs = SDHCI_MAX_SEGS;
3838 } else if (host->flags & SDHCI_USE_SDMA) {
3839 mmc->max_segs = 1;
3840 if (swiotlb_max_segment()) {
3841 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3842 IO_TLB_SEGSIZE;
3843 mmc->max_req_size = min(mmc->max_req_size,
3844 max_req_size);
3845 }
3846 } else { /* PIO */
3847 mmc->max_segs = SDHCI_MAX_SEGS;
3848 }
3849
3850 /*
3851 * Maximum segment size. Could be one segment with the maximum number
3852 * of bytes. When doing hardware scatter/gather, each entry cannot
3853 * be larger than 64 KiB though.
3854 */
3855 if (host->flags & SDHCI_USE_ADMA) {
3856 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3857 mmc->max_seg_size = 65535;
3858 else
3859 mmc->max_seg_size = 65536;
3860 } else {
3861 mmc->max_seg_size = mmc->max_req_size;
3862 }
3863
3864 /*
3865 * Maximum block size. This varies from controller to controller and
3866 * is specified in the capabilities register.
3867 */
3868 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3869 mmc->max_blk_size = 2;
3870 } else {
3871 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3872 SDHCI_MAX_BLOCK_SHIFT;
3873 if (mmc->max_blk_size >= 3) {
3874 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3875 mmc_hostname(mmc));
3876 mmc->max_blk_size = 0;
3877 }
3878 }
3879
3880 mmc->max_blk_size = 512 << mmc->max_blk_size;
3881
3882 /*
3883 * Maximum block count.
3884 */
3885 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3886
3887 if (mmc->max_segs == 1) {
3888 /* This may alter mmc->*_blk_* parameters */
3889 ret = sdhci_allocate_bounce_buffer(host);
3890 if (ret)
3891 return ret;
3892 }
3893
3894 return 0;
3895
3896unreg:
3897 if (!IS_ERR(mmc->supply.vqmmc))
3898 regulator_disable(mmc->supply.vqmmc);
3899undma:
3900 if (host->align_buffer)
3901 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3902 host->adma_table_sz, host->align_buffer,
3903 host->align_addr);
3904 host->adma_table = NULL;
3905 host->align_buffer = NULL;
3906
3907 return ret;
3908}
3909EXPORT_SYMBOL_GPL(sdhci_setup_host);
3910
3911void sdhci_cleanup_host(struct sdhci_host *host)
3912{
3913 struct mmc_host *mmc = host->mmc;
3914
3915 if (!IS_ERR(mmc->supply.vqmmc))
3916 regulator_disable(mmc->supply.vqmmc);
3917
3918 if (host->align_buffer)
3919 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3920 host->adma_table_sz, host->align_buffer,
3921 host->align_addr);
3922 host->adma_table = NULL;
3923 host->align_buffer = NULL;
3924}
3925EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3926
3927int __sdhci_add_host(struct sdhci_host *host)
3928{
3929 struct mmc_host *mmc = host->mmc;
3930 int ret;
3931
3932 /*
3933 * Init tasklets.
3934 */
3935 tasklet_init(&host->finish_tasklet,
3936 sdhci_tasklet_finish, (unsigned long)host);
3937
3938 timer_setup(&host->timer, sdhci_timeout_timer, 0);
3939 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
3940
3941 init_waitqueue_head(&host->buf_ready_int);
3942
3943 sdhci_init(host, 0);
3944
3945 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3946 IRQF_SHARED, mmc_hostname(mmc), host);
3947 if (ret) {
3948 pr_err("%s: Failed to request IRQ %d: %d\n",
3949 mmc_hostname(mmc), host->irq, ret);
3950 goto untasklet;
3951 }
3952
3953 ret = sdhci_led_register(host);
3954 if (ret) {
3955 pr_err("%s: Failed to register LED device: %d\n",
3956 mmc_hostname(mmc), ret);
3957 goto unirq;
3958 }
3959
3960 mmiowb();
3961
3962 ret = mmc_add_host(mmc);
3963 if (ret)
3964 goto unled;
3965
3966 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3967 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3968 (host->flags & SDHCI_USE_ADMA) ?
3969 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3970 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3971
3972 sdhci_enable_card_detection(host);
3973
3974 return 0;
3975
3976unled:
3977 sdhci_led_unregister(host);
3978unirq:
3979 sdhci_do_reset(host, SDHCI_RESET_ALL);
3980 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3981 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3982 free_irq(host->irq, host);
3983untasklet:
3984 tasklet_kill(&host->finish_tasklet);
3985
3986 return ret;
3987}
3988EXPORT_SYMBOL_GPL(__sdhci_add_host);
3989
3990int sdhci_add_host(struct sdhci_host *host)
3991{
3992 int ret;
3993
3994 ret = sdhci_setup_host(host);
3995 if (ret)
3996 return ret;
3997
3998 ret = __sdhci_add_host(host);
3999 if (ret)
4000 goto cleanup;
4001
4002 return 0;
4003
4004cleanup:
4005 sdhci_cleanup_host(host);
4006
4007 return ret;
4008}
4009EXPORT_SYMBOL_GPL(sdhci_add_host);
4010
4011void sdhci_remove_host(struct sdhci_host *host, int dead)
4012{
4013 struct mmc_host *mmc = host->mmc;
4014 unsigned long flags;
4015
4016 if (dead) {
4017 spin_lock_irqsave(&host->lock, flags);
4018
4019 host->flags |= SDHCI_DEVICE_DEAD;
4020
4021 if (sdhci_has_requests(host)) {
4022 pr_err("%s: Controller removed during "
4023 " transfer!\n", mmc_hostname(mmc));
4024 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4025 }
4026
4027 spin_unlock_irqrestore(&host->lock, flags);
4028 }
4029
4030 sdhci_disable_card_detection(host);
4031
4032 mmc_remove_host(mmc);
4033
4034 sdhci_led_unregister(host);
4035
4036 if (!dead)
4037 sdhci_do_reset(host, SDHCI_RESET_ALL);
4038
4039 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4040 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4041 free_irq(host->irq, host);
4042
4043 del_timer_sync(&host->timer);
4044 del_timer_sync(&host->data_timer);
4045
4046 tasklet_kill(&host->finish_tasklet);
4047
4048 if (!IS_ERR(mmc->supply.vqmmc))
4049 regulator_disable(mmc->supply.vqmmc);
4050
4051 if (host->align_buffer)
4052 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4053 host->adma_table_sz, host->align_buffer,
4054 host->align_addr);
4055
4056 host->adma_table = NULL;
4057 host->align_buffer = NULL;
4058}
4059
4060EXPORT_SYMBOL_GPL(sdhci_remove_host);
4061
4062void sdhci_free_host(struct sdhci_host *host)
4063{
4064 mmc_free_host(host->mmc);
4065}
4066
4067EXPORT_SYMBOL_GPL(sdhci_free_host);
4068
4069/*****************************************************************************\
4070 * *
4071 * Driver init/exit *
4072 * *
4073\*****************************************************************************/
4074
4075static int __init sdhci_drv_init(void)
4076{
4077 pr_info(DRIVER_NAME
4078 ": Secure Digital Host Controller Interface driver\n");
4079 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4080
4081 return 0;
4082}
4083
4084static void __exit sdhci_drv_exit(void)
4085{
4086}
4087
4088module_init(sdhci_drv_init);
4089module_exit(sdhci_drv_exit);
4090
4091module_param(debug_quirks, uint, 0444);
4092module_param(debug_quirks2, uint, 0444);
4093
4094MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4095MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4096MODULE_LICENSE("GPL");
4097
4098MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4099MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26#include <linux/bug.h>
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
51
52void sdhci_dumpregs(struct sdhci_host *host)
53{
54 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
55
56 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
57 sdhci_readl(host, SDHCI_DMA_ADDRESS),
58 sdhci_readw(host, SDHCI_HOST_VERSION));
59 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
60 sdhci_readw(host, SDHCI_BLOCK_SIZE),
61 sdhci_readw(host, SDHCI_BLOCK_COUNT));
62 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
63 sdhci_readl(host, SDHCI_ARGUMENT),
64 sdhci_readw(host, SDHCI_TRANSFER_MODE));
65 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
66 sdhci_readl(host, SDHCI_PRESENT_STATE),
67 sdhci_readb(host, SDHCI_HOST_CONTROL));
68 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
69 sdhci_readb(host, SDHCI_POWER_CONTROL),
70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
71 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
74 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
76 sdhci_readl(host, SDHCI_INT_STATUS));
77 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
78 sdhci_readl(host, SDHCI_INT_ENABLE),
79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
80 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
81 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
83 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
84 sdhci_readl(host, SDHCI_CAPABILITIES),
85 sdhci_readl(host, SDHCI_CAPABILITIES_1));
86 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
87 sdhci_readw(host, SDHCI_COMMAND),
88 sdhci_readl(host, SDHCI_MAX_CURRENT));
89 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
90 sdhci_readl(host, SDHCI_RESPONSE),
91 sdhci_readl(host, SDHCI_RESPONSE + 4));
92 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
93 sdhci_readl(host, SDHCI_RESPONSE + 8),
94 sdhci_readl(host, SDHCI_RESPONSE + 12));
95 SDHCI_DUMP("Host ctl2: 0x%08x\n",
96 sdhci_readw(host, SDHCI_HOST_CONTROL2));
97
98 if (host->flags & SDHCI_USE_ADMA) {
99 if (host->flags & SDHCI_USE_64_BIT_DMA) {
100 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
101 sdhci_readl(host, SDHCI_ADMA_ERROR),
102 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
103 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
104 } else {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
108 }
109 }
110
111 if (host->ops->dump_uhs2_regs)
112 host->ops->dump_uhs2_regs(host);
113
114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
116
117 SDHCI_DUMP("============================================\n");
118}
119EXPORT_SYMBOL_GPL(sdhci_dumpregs);
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
127static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
128{
129 u16 ctrl2;
130
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
132 if (ctrl2 & SDHCI_CTRL_V4_MODE)
133 return;
134
135 ctrl2 |= SDHCI_CTRL_V4_MODE;
136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
137}
138
139/*
140 * This can be called before sdhci_add_host() by Vendor's host controller
141 * driver to enable v4 mode if supported.
142 */
143void sdhci_enable_v4_mode(struct sdhci_host *host)
144{
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
147}
148EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
149
150bool sdhci_data_line_cmd(struct mmc_command *cmd)
151{
152 return cmd->data || cmd->flags & MMC_RSP_BUSY;
153}
154EXPORT_SYMBOL_GPL(sdhci_data_line_cmd);
155
156static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
157{
158 u32 present;
159
160 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
161 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
162 return;
163
164 if (enable) {
165 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
166 SDHCI_CARD_PRESENT;
167
168 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
169 SDHCI_INT_CARD_INSERT;
170 } else {
171 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
172 }
173
174 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
175 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
176}
177
178static void sdhci_enable_card_detection(struct sdhci_host *host)
179{
180 sdhci_set_card_detection(host, true);
181}
182
183static void sdhci_disable_card_detection(struct sdhci_host *host)
184{
185 sdhci_set_card_detection(host, false);
186}
187
188static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
189{
190 if (host->bus_on)
191 return;
192 host->bus_on = true;
193 pm_runtime_get_noresume(mmc_dev(host->mmc));
194}
195
196static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
197{
198 if (!host->bus_on)
199 return;
200 host->bus_on = false;
201 pm_runtime_put_noidle(mmc_dev(host->mmc));
202}
203
204void sdhci_reset(struct sdhci_host *host, u8 mask)
205{
206 ktime_t timeout;
207
208 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
209
210 if (mask & SDHCI_RESET_ALL) {
211 host->clock = 0;
212 /* Reset-all turns off SD Bus Power */
213 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
214 sdhci_runtime_pm_bus_off(host);
215 }
216
217 /* Wait max 100 ms */
218 timeout = ktime_add_ms(ktime_get(), 100);
219
220 /* hw clears the bit when it's done */
221 while (1) {
222 bool timedout = ktime_after(ktime_get(), timeout);
223
224 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
225 break;
226 if (timedout) {
227 pr_err("%s: Reset 0x%x never completed.\n",
228 mmc_hostname(host->mmc), (int)mask);
229 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
230 sdhci_dumpregs(host);
231 return;
232 }
233 udelay(10);
234 }
235}
236EXPORT_SYMBOL_GPL(sdhci_reset);
237
238bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
239{
240 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
241 struct mmc_host *mmc = host->mmc;
242
243 if (!mmc->ops->get_cd(mmc))
244 return false;
245 }
246
247 host->ops->reset(host, mask);
248
249 return true;
250}
251EXPORT_SYMBOL_GPL(sdhci_do_reset);
252
253static void sdhci_reset_for_all(struct sdhci_host *host)
254{
255 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
256 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
257 if (host->ops->enable_dma)
258 host->ops->enable_dma(host);
259 }
260 /* Resetting the controller clears many */
261 host->preset_enabled = false;
262 }
263}
264
265enum sdhci_reset_reason {
266 SDHCI_RESET_FOR_INIT,
267 SDHCI_RESET_FOR_REQUEST_ERROR,
268 SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
269 SDHCI_RESET_FOR_TUNING_ABORT,
270 SDHCI_RESET_FOR_CARD_REMOVED,
271 SDHCI_RESET_FOR_CQE_RECOVERY,
272};
273
274static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
275{
276 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
277 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
278 return;
279 }
280
281 switch (reason) {
282 case SDHCI_RESET_FOR_INIT:
283 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
284 break;
285 case SDHCI_RESET_FOR_REQUEST_ERROR:
286 case SDHCI_RESET_FOR_TUNING_ABORT:
287 case SDHCI_RESET_FOR_CARD_REMOVED:
288 case SDHCI_RESET_FOR_CQE_RECOVERY:
289 sdhci_do_reset(host, SDHCI_RESET_CMD);
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
291 break;
292 case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
293 sdhci_do_reset(host, SDHCI_RESET_DATA);
294 break;
295 }
296}
297
298#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
299
300static void sdhci_set_default_irqs(struct sdhci_host *host)
301{
302 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
303 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
304 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
305 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
306 SDHCI_INT_RESPONSE;
307
308 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
309 host->tuning_mode == SDHCI_TUNING_MODE_3)
310 host->ier |= SDHCI_INT_RETUNE;
311
312 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
313 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
314}
315
316static void sdhci_config_dma(struct sdhci_host *host)
317{
318 u8 ctrl;
319 u16 ctrl2;
320
321 if (host->version < SDHCI_SPEC_200)
322 return;
323
324 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
325
326 /*
327 * Always adjust the DMA selection as some controllers
328 * (e.g. JMicron) can't do PIO properly when the selection
329 * is ADMA.
330 */
331 ctrl &= ~SDHCI_CTRL_DMA_MASK;
332 if (!(host->flags & SDHCI_REQ_USE_DMA))
333 goto out;
334
335 /* Note if DMA Select is zero then SDMA is selected */
336 if (host->flags & SDHCI_USE_ADMA)
337 ctrl |= SDHCI_CTRL_ADMA32;
338
339 if (host->flags & SDHCI_USE_64_BIT_DMA) {
340 /*
341 * If v4 mode, all supported DMA can be 64-bit addressing if
342 * controller supports 64-bit system address, otherwise only
343 * ADMA can support 64-bit addressing.
344 */
345 if (host->v4_mode) {
346 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
347 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
348 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
349 } else if (host->flags & SDHCI_USE_ADMA) {
350 /*
351 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
352 * set SDHCI_CTRL_ADMA64.
353 */
354 ctrl |= SDHCI_CTRL_ADMA64;
355 }
356 }
357
358out:
359 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
360}
361
362static void sdhci_init(struct sdhci_host *host, int soft)
363{
364 struct mmc_host *mmc = host->mmc;
365 unsigned long flags;
366
367 if (soft)
368 sdhci_reset_for(host, INIT);
369 else
370 sdhci_reset_for_all(host);
371
372 if (host->v4_mode)
373 sdhci_do_enable_v4_mode(host);
374
375 spin_lock_irqsave(&host->lock, flags);
376 sdhci_set_default_irqs(host);
377 spin_unlock_irqrestore(&host->lock, flags);
378
379 host->cqe_on = false;
380
381 if (soft) {
382 /* force clock reconfiguration */
383 host->clock = 0;
384 host->reinit_uhs = true;
385 mmc->ops->set_ios(mmc, &mmc->ios);
386 }
387}
388
389static void sdhci_reinit(struct sdhci_host *host)
390{
391 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
392
393 sdhci_init(host, 0);
394 sdhci_enable_card_detection(host);
395
396 /*
397 * A change to the card detect bits indicates a change in present state,
398 * refer sdhci_set_card_detection(). A card detect interrupt might have
399 * been missed while the host controller was being reset, so trigger a
400 * rescan to check.
401 */
402 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
403 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
404}
405
406static void __sdhci_led_activate(struct sdhci_host *host)
407{
408 u8 ctrl;
409
410 if (host->quirks & SDHCI_QUIRK_NO_LED)
411 return;
412
413 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
414 ctrl |= SDHCI_CTRL_LED;
415 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
416}
417
418static void __sdhci_led_deactivate(struct sdhci_host *host)
419{
420 u8 ctrl;
421
422 if (host->quirks & SDHCI_QUIRK_NO_LED)
423 return;
424
425 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
426 ctrl &= ~SDHCI_CTRL_LED;
427 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
428}
429
430#if IS_REACHABLE(CONFIG_LEDS_CLASS)
431static void sdhci_led_control(struct led_classdev *led,
432 enum led_brightness brightness)
433{
434 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
435 unsigned long flags;
436
437 spin_lock_irqsave(&host->lock, flags);
438
439 if (host->runtime_suspended)
440 goto out;
441
442 if (brightness == LED_OFF)
443 __sdhci_led_deactivate(host);
444 else
445 __sdhci_led_activate(host);
446out:
447 spin_unlock_irqrestore(&host->lock, flags);
448}
449
450static int sdhci_led_register(struct sdhci_host *host)
451{
452 struct mmc_host *mmc = host->mmc;
453
454 if (host->quirks & SDHCI_QUIRK_NO_LED)
455 return 0;
456
457 snprintf(host->led_name, sizeof(host->led_name),
458 "%s::", mmc_hostname(mmc));
459
460 host->led.name = host->led_name;
461 host->led.brightness = LED_OFF;
462 host->led.default_trigger = mmc_hostname(mmc);
463 host->led.brightness_set = sdhci_led_control;
464
465 return led_classdev_register(mmc_dev(mmc), &host->led);
466}
467
468static void sdhci_led_unregister(struct sdhci_host *host)
469{
470 if (host->quirks & SDHCI_QUIRK_NO_LED)
471 return;
472
473 led_classdev_unregister(&host->led);
474}
475
476static inline void sdhci_led_activate(struct sdhci_host *host)
477{
478}
479
480static inline void sdhci_led_deactivate(struct sdhci_host *host)
481{
482}
483
484#else
485
486static inline int sdhci_led_register(struct sdhci_host *host)
487{
488 return 0;
489}
490
491static inline void sdhci_led_unregister(struct sdhci_host *host)
492{
493}
494
495static inline void sdhci_led_activate(struct sdhci_host *host)
496{
497 __sdhci_led_activate(host);
498}
499
500static inline void sdhci_led_deactivate(struct sdhci_host *host)
501{
502 __sdhci_led_deactivate(host);
503}
504
505#endif
506
507void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
508 unsigned long timeout)
509{
510 if (sdhci_data_line_cmd(mrq->cmd))
511 mod_timer(&host->data_timer, timeout);
512 else
513 mod_timer(&host->timer, timeout);
514}
515EXPORT_SYMBOL_GPL(sdhci_mod_timer);
516
517static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
518{
519 if (sdhci_data_line_cmd(mrq->cmd))
520 del_timer(&host->data_timer);
521 else
522 del_timer(&host->timer);
523}
524
525static inline bool sdhci_has_requests(struct sdhci_host *host)
526{
527 return host->cmd || host->data_cmd;
528}
529
530/*****************************************************************************\
531 * *
532 * Core functions *
533 * *
534\*****************************************************************************/
535
536static void sdhci_read_block_pio(struct sdhci_host *host)
537{
538 size_t blksize, len, chunk;
539 u32 scratch;
540 u8 *buf;
541
542 DBG("PIO reading\n");
543
544 blksize = host->data->blksz;
545 chunk = 0;
546
547 while (blksize) {
548 BUG_ON(!sg_miter_next(&host->sg_miter));
549
550 len = min(host->sg_miter.length, blksize);
551
552 blksize -= len;
553 host->sg_miter.consumed = len;
554
555 buf = host->sg_miter.addr;
556
557 while (len) {
558 if (chunk == 0) {
559 scratch = sdhci_readl(host, SDHCI_BUFFER);
560 chunk = 4;
561 }
562
563 *buf = scratch & 0xFF;
564
565 buf++;
566 scratch >>= 8;
567 chunk--;
568 len--;
569 }
570 }
571
572 sg_miter_stop(&host->sg_miter);
573}
574
575static void sdhci_write_block_pio(struct sdhci_host *host)
576{
577 size_t blksize, len, chunk;
578 u32 scratch;
579 u8 *buf;
580
581 DBG("PIO writing\n");
582
583 blksize = host->data->blksz;
584 chunk = 0;
585 scratch = 0;
586
587 while (blksize) {
588 BUG_ON(!sg_miter_next(&host->sg_miter));
589
590 len = min(host->sg_miter.length, blksize);
591
592 blksize -= len;
593 host->sg_miter.consumed = len;
594
595 buf = host->sg_miter.addr;
596
597 while (len) {
598 scratch |= (u32)*buf << (chunk * 8);
599
600 buf++;
601 chunk++;
602 len--;
603
604 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
605 sdhci_writel(host, scratch, SDHCI_BUFFER);
606 chunk = 0;
607 scratch = 0;
608 }
609 }
610 }
611
612 sg_miter_stop(&host->sg_miter);
613}
614
615static void sdhci_transfer_pio(struct sdhci_host *host)
616{
617 u32 mask;
618
619 if (host->blocks == 0)
620 return;
621
622 if (host->data->flags & MMC_DATA_READ)
623 mask = SDHCI_DATA_AVAILABLE;
624 else
625 mask = SDHCI_SPACE_AVAILABLE;
626
627 /*
628 * Some controllers (JMicron JMB38x) mess up the buffer bits
629 * for transfers < 4 bytes. As long as it is just one block,
630 * we can ignore the bits.
631 */
632 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
633 (host->data->blocks == 1))
634 mask = ~0;
635
636 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
637 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
638 udelay(100);
639
640 if (host->data->flags & MMC_DATA_READ)
641 sdhci_read_block_pio(host);
642 else
643 sdhci_write_block_pio(host);
644
645 host->blocks--;
646 if (host->blocks == 0)
647 break;
648 }
649
650 DBG("PIO transfer complete.\n");
651}
652
653static int sdhci_pre_dma_transfer(struct sdhci_host *host,
654 struct mmc_data *data, int cookie)
655{
656 int sg_count;
657
658 /*
659 * If the data buffers are already mapped, return the previous
660 * dma_map_sg() result.
661 */
662 if (data->host_cookie == COOKIE_PRE_MAPPED)
663 return data->sg_count;
664
665 /* Bounce write requests to the bounce buffer */
666 if (host->bounce_buffer) {
667 unsigned int length = data->blksz * data->blocks;
668
669 if (length > host->bounce_buffer_size) {
670 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
671 mmc_hostname(host->mmc), length,
672 host->bounce_buffer_size);
673 return -EIO;
674 }
675 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
676 /* Copy the data to the bounce buffer */
677 if (host->ops->copy_to_bounce_buffer) {
678 host->ops->copy_to_bounce_buffer(host,
679 data, length);
680 } else {
681 sg_copy_to_buffer(data->sg, data->sg_len,
682 host->bounce_buffer, length);
683 }
684 }
685 /* Switch ownership to the DMA */
686 dma_sync_single_for_device(mmc_dev(host->mmc),
687 host->bounce_addr,
688 host->bounce_buffer_size,
689 mmc_get_dma_dir(data));
690 /* Just a dummy value */
691 sg_count = 1;
692 } else {
693 /* Just access the data directly from memory */
694 sg_count = dma_map_sg(mmc_dev(host->mmc),
695 data->sg, data->sg_len,
696 mmc_get_dma_dir(data));
697 }
698
699 if (sg_count == 0)
700 return -ENOSPC;
701
702 data->sg_count = sg_count;
703 data->host_cookie = cookie;
704
705 return sg_count;
706}
707
708static char *sdhci_kmap_atomic(struct scatterlist *sg)
709{
710 return kmap_local_page(sg_page(sg)) + sg->offset;
711}
712
713static void sdhci_kunmap_atomic(void *buffer)
714{
715 kunmap_local(buffer);
716}
717
718void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
719 dma_addr_t addr, int len, unsigned int cmd)
720{
721 struct sdhci_adma2_64_desc *dma_desc = *desc;
722
723 /* 32-bit and 64-bit descriptors have these members in same position */
724 dma_desc->cmd = cpu_to_le16(cmd);
725 dma_desc->len = cpu_to_le16(len);
726 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
727
728 if (host->flags & SDHCI_USE_64_BIT_DMA)
729 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
730
731 *desc += host->desc_sz;
732}
733EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
734
735static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
736 void **desc, dma_addr_t addr,
737 int len, unsigned int cmd)
738{
739 if (host->ops->adma_write_desc)
740 host->ops->adma_write_desc(host, desc, addr, len, cmd);
741 else
742 sdhci_adma_write_desc(host, desc, addr, len, cmd);
743}
744
745static void sdhci_adma_mark_end(void *desc)
746{
747 struct sdhci_adma2_64_desc *dma_desc = desc;
748
749 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
750 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
751}
752
753static void sdhci_adma_table_pre(struct sdhci_host *host,
754 struct mmc_data *data, int sg_count)
755{
756 struct scatterlist *sg;
757 dma_addr_t addr, align_addr;
758 void *desc, *align;
759 char *buffer;
760 int len, offset, i;
761
762 /*
763 * The spec does not specify endianness of descriptor table.
764 * We currently guess that it is LE.
765 */
766
767 host->sg_count = sg_count;
768
769 desc = host->adma_table;
770 align = host->align_buffer;
771
772 align_addr = host->align_addr;
773
774 for_each_sg(data->sg, sg, host->sg_count, i) {
775 addr = sg_dma_address(sg);
776 len = sg_dma_len(sg);
777
778 /*
779 * The SDHCI specification states that ADMA addresses must
780 * be 32-bit aligned. If they aren't, then we use a bounce
781 * buffer for the (up to three) bytes that screw up the
782 * alignment.
783 */
784 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
785 SDHCI_ADMA2_MASK;
786 if (offset) {
787 if (data->flags & MMC_DATA_WRITE) {
788 buffer = sdhci_kmap_atomic(sg);
789 memcpy(align, buffer, offset);
790 sdhci_kunmap_atomic(buffer);
791 }
792
793 /* tran, valid */
794 __sdhci_adma_write_desc(host, &desc, align_addr,
795 offset, ADMA2_TRAN_VALID);
796
797 BUG_ON(offset > 65536);
798
799 align += SDHCI_ADMA2_ALIGN;
800 align_addr += SDHCI_ADMA2_ALIGN;
801
802 addr += offset;
803 len -= offset;
804 }
805
806 /*
807 * The block layer forces a minimum segment size of PAGE_SIZE,
808 * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
809 * multiple descriptors, noting that the ADMA table is sized
810 * for 4KiB chunks anyway, so it will be big enough.
811 */
812 while (len > host->max_adma) {
813 int n = 32 * 1024; /* 32KiB*/
814
815 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
816 addr += n;
817 len -= n;
818 }
819
820 /* tran, valid */
821 if (len)
822 __sdhci_adma_write_desc(host, &desc, addr, len,
823 ADMA2_TRAN_VALID);
824
825 /*
826 * If this triggers then we have a calculation bug
827 * somewhere. :/
828 */
829 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
830 }
831
832 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
833 /* Mark the last descriptor as the terminating descriptor */
834 if (desc != host->adma_table) {
835 desc -= host->desc_sz;
836 sdhci_adma_mark_end(desc);
837 }
838 } else {
839 /* Add a terminating entry - nop, end, valid */
840 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
841 }
842}
843
844static void sdhci_adma_table_post(struct sdhci_host *host,
845 struct mmc_data *data)
846{
847 struct scatterlist *sg;
848 int i, size;
849 void *align;
850 char *buffer;
851
852 if (data->flags & MMC_DATA_READ) {
853 bool has_unaligned = false;
854
855 /* Do a quick scan of the SG list for any unaligned mappings */
856 for_each_sg(data->sg, sg, host->sg_count, i)
857 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
858 has_unaligned = true;
859 break;
860 }
861
862 if (has_unaligned) {
863 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
864 data->sg_len, DMA_FROM_DEVICE);
865
866 align = host->align_buffer;
867
868 for_each_sg(data->sg, sg, host->sg_count, i) {
869 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
870 size = SDHCI_ADMA2_ALIGN -
871 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
872
873 buffer = sdhci_kmap_atomic(sg);
874 memcpy(buffer, align, size);
875 sdhci_kunmap_atomic(buffer);
876
877 align += SDHCI_ADMA2_ALIGN;
878 }
879 }
880 }
881 }
882}
883
884static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
885{
886 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
887 if (host->flags & SDHCI_USE_64_BIT_DMA)
888 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
889}
890
891static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
892{
893 if (host->bounce_buffer)
894 return host->bounce_addr;
895 else
896 return sg_dma_address(host->data->sg);
897}
898
899static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
900{
901 if (host->v4_mode)
902 sdhci_set_adma_addr(host, addr);
903 else
904 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
905}
906
907static unsigned int sdhci_target_timeout(struct sdhci_host *host,
908 struct mmc_command *cmd,
909 struct mmc_data *data)
910{
911 unsigned int target_timeout;
912
913 /* timeout in us */
914 if (!data) {
915 target_timeout = cmd->busy_timeout * 1000;
916 } else {
917 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
918 if (host->clock && data->timeout_clks) {
919 unsigned long long val;
920
921 /*
922 * data->timeout_clks is in units of clock cycles.
923 * host->clock is in Hz. target_timeout is in us.
924 * Hence, us = 1000000 * cycles / Hz. Round up.
925 */
926 val = 1000000ULL * data->timeout_clks;
927 if (do_div(val, host->clock))
928 target_timeout++;
929 target_timeout += val;
930 }
931 }
932
933 return target_timeout;
934}
935
936static void sdhci_calc_sw_timeout(struct sdhci_host *host,
937 struct mmc_command *cmd)
938{
939 struct mmc_data *data = cmd->data;
940 struct mmc_host *mmc = host->mmc;
941 struct mmc_ios *ios = &mmc->ios;
942 unsigned char bus_width = 1 << ios->bus_width;
943 unsigned int blksz;
944 unsigned int freq;
945 u64 target_timeout;
946 u64 transfer_time;
947
948 target_timeout = sdhci_target_timeout(host, cmd, data);
949 target_timeout *= NSEC_PER_USEC;
950
951 if (data) {
952 blksz = data->blksz;
953 freq = mmc->actual_clock ? : host->clock;
954 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
955 do_div(transfer_time, freq);
956 /* multiply by '2' to account for any unknowns */
957 transfer_time = transfer_time * 2;
958 /* calculate timeout for the entire data */
959 host->data_timeout = data->blocks * target_timeout +
960 transfer_time;
961 } else {
962 host->data_timeout = target_timeout;
963 }
964
965 if (host->data_timeout)
966 host->data_timeout += MMC_CMD_TRANSFER_TIME;
967}
968
969static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
970 bool *too_big)
971{
972 u8 count;
973 struct mmc_data *data;
974 unsigned target_timeout, current_timeout;
975
976 *too_big = false;
977
978 /*
979 * If the host controller provides us with an incorrect timeout
980 * value, just skip the check and use the maximum. The hardware may take
981 * longer to time out, but that's much better than having a too-short
982 * timeout value.
983 */
984 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
985 return host->max_timeout_count;
986
987 /* Unspecified command, assume max */
988 if (cmd == NULL)
989 return host->max_timeout_count;
990
991 data = cmd->data;
992 /* Unspecified timeout, assume max */
993 if (!data && !cmd->busy_timeout)
994 return host->max_timeout_count;
995
996 /* timeout in us */
997 target_timeout = sdhci_target_timeout(host, cmd, data);
998
999 /*
1000 * Figure out needed cycles.
1001 * We do this in steps in order to fit inside a 32 bit int.
1002 * The first step is the minimum timeout, which will have a
1003 * minimum resolution of 6 bits:
1004 * (1) 2^13*1000 > 2^22,
1005 * (2) host->timeout_clk < 2^16
1006 * =>
1007 * (1) / (2) > 2^6
1008 */
1009 count = 0;
1010 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1011 while (current_timeout < target_timeout) {
1012 count++;
1013 current_timeout <<= 1;
1014 if (count > host->max_timeout_count) {
1015 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1016 DBG("Too large timeout 0x%x requested for CMD%d!\n",
1017 count, cmd->opcode);
1018 count = host->max_timeout_count;
1019 *too_big = true;
1020 break;
1021 }
1022 }
1023
1024 return count;
1025}
1026
1027static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1028{
1029 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1030 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1031
1032 if (host->flags & SDHCI_REQ_USE_DMA)
1033 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1034 else
1035 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1036
1037 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1038 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1039 else
1040 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1041
1042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1044}
1045
1046void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1047{
1048 if (enable)
1049 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1050 else
1051 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1052 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1053 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1054}
1055EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1056
1057void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1058{
1059 bool too_big = false;
1060 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1061
1062 if (too_big &&
1063 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1064 sdhci_calc_sw_timeout(host, cmd);
1065 sdhci_set_data_timeout_irq(host, false);
1066 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1067 sdhci_set_data_timeout_irq(host, true);
1068 }
1069
1070 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1071}
1072EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1073
1074static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1075{
1076 if (host->ops->set_timeout)
1077 host->ops->set_timeout(host, cmd);
1078 else
1079 __sdhci_set_timeout(host, cmd);
1080}
1081
1082void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data)
1083{
1084 WARN_ON(host->data);
1085
1086 /* Sanity checks */
1087 BUG_ON(data->blksz * data->blocks > 524288);
1088 BUG_ON(data->blksz > host->mmc->max_blk_size);
1089 BUG_ON(data->blocks > 65535);
1090
1091 host->data = data;
1092 host->data_early = 0;
1093 host->data->bytes_xfered = 0;
1094}
1095EXPORT_SYMBOL_GPL(sdhci_initialize_data);
1096
1097static inline void sdhci_set_block_info(struct sdhci_host *host,
1098 struct mmc_data *data)
1099{
1100 /* Set the DMA boundary value and block size */
1101 sdhci_writew(host,
1102 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1103 SDHCI_BLOCK_SIZE);
1104 /*
1105 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1106 * can be supported, in that case 16-bit block count register must be 0.
1107 */
1108 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1109 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1110 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1111 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1112 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1113 } else {
1114 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1115 }
1116}
1117
1118void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data)
1119{
1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1121 struct scatterlist *sg;
1122 unsigned int length_mask, offset_mask;
1123 int i;
1124
1125 host->flags |= SDHCI_REQ_USE_DMA;
1126
1127 /*
1128 * FIXME: This doesn't account for merging when mapping the
1129 * scatterlist.
1130 *
1131 * The assumption here being that alignment and lengths are
1132 * the same after DMA mapping to device address space.
1133 */
1134 length_mask = 0;
1135 offset_mask = 0;
1136 if (host->flags & SDHCI_USE_ADMA) {
1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1138 length_mask = 3;
1139 /*
1140 * As we use up to 3 byte chunks to work
1141 * around alignment problems, we need to
1142 * check the offset as well.
1143 */
1144 offset_mask = 3;
1145 }
1146 } else {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1148 length_mask = 3;
1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1150 offset_mask = 3;
1151 }
1152
1153 if (unlikely(length_mask | offset_mask)) {
1154 for_each_sg(data->sg, sg, data->sg_len, i) {
1155 if (sg->length & length_mask) {
1156 DBG("Reverting to PIO because of transfer size (%d)\n",
1157 sg->length);
1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1159 break;
1160 }
1161 if (sg->offset & offset_mask) {
1162 DBG("Reverting to PIO because of bad alignment\n");
1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1164 break;
1165 }
1166 }
1167 }
1168 }
1169
1170 sdhci_config_dma(host);
1171
1172 if (host->flags & SDHCI_REQ_USE_DMA) {
1173 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1174
1175 if (sg_cnt <= 0) {
1176 /*
1177 * This only happens when someone fed
1178 * us an invalid request.
1179 */
1180 WARN_ON(1);
1181 host->flags &= ~SDHCI_REQ_USE_DMA;
1182 } else if (host->flags & SDHCI_USE_ADMA) {
1183 sdhci_adma_table_pre(host, data, sg_cnt);
1184 sdhci_set_adma_addr(host, host->adma_addr);
1185 } else {
1186 WARN_ON(sg_cnt != 1);
1187 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1188 }
1189 }
1190
1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1192 int flags;
1193
1194 flags = SG_MITER_ATOMIC;
1195 if (host->data->flags & MMC_DATA_READ)
1196 flags |= SG_MITER_TO_SG;
1197 else
1198 flags |= SG_MITER_FROM_SG;
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200 host->blocks = data->blocks;
1201 }
1202
1203 sdhci_set_transfer_irqs(host);
1204}
1205EXPORT_SYMBOL_GPL(sdhci_prepare_dma);
1206
1207static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1208{
1209 struct mmc_data *data = cmd->data;
1210
1211 sdhci_initialize_data(host, data);
1212
1213 sdhci_prepare_dma(host, data);
1214
1215 sdhci_set_block_info(host, data);
1216}
1217
1218#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1219
1220static int sdhci_external_dma_init(struct sdhci_host *host)
1221{
1222 int ret = 0;
1223 struct mmc_host *mmc = host->mmc;
1224
1225 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1226 if (IS_ERR(host->tx_chan)) {
1227 ret = PTR_ERR(host->tx_chan);
1228 if (ret != -EPROBE_DEFER)
1229 pr_warn("Failed to request TX DMA channel.\n");
1230 host->tx_chan = NULL;
1231 return ret;
1232 }
1233
1234 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1235 if (IS_ERR(host->rx_chan)) {
1236 if (host->tx_chan) {
1237 dma_release_channel(host->tx_chan);
1238 host->tx_chan = NULL;
1239 }
1240
1241 ret = PTR_ERR(host->rx_chan);
1242 if (ret != -EPROBE_DEFER)
1243 pr_warn("Failed to request RX DMA channel.\n");
1244 host->rx_chan = NULL;
1245 }
1246
1247 return ret;
1248}
1249
1250static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1251 struct mmc_data *data)
1252{
1253 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1254}
1255
1256static int sdhci_external_dma_setup(struct sdhci_host *host,
1257 struct mmc_command *cmd)
1258{
1259 int ret, i;
1260 enum dma_transfer_direction dir;
1261 struct dma_async_tx_descriptor *desc;
1262 struct mmc_data *data = cmd->data;
1263 struct dma_chan *chan;
1264 struct dma_slave_config cfg;
1265 dma_cookie_t cookie;
1266 int sg_cnt;
1267
1268 if (!host->mapbase)
1269 return -EINVAL;
1270
1271 memset(&cfg, 0, sizeof(cfg));
1272 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1273 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1274 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1275 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1276 cfg.src_maxburst = data->blksz / 4;
1277 cfg.dst_maxburst = data->blksz / 4;
1278
1279 /* Sanity check: all the SG entries must be aligned by block size. */
1280 for (i = 0; i < data->sg_len; i++) {
1281 if ((data->sg + i)->length % data->blksz)
1282 return -EINVAL;
1283 }
1284
1285 chan = sdhci_external_dma_channel(host, data);
1286
1287 ret = dmaengine_slave_config(chan, &cfg);
1288 if (ret)
1289 return ret;
1290
1291 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1292 if (sg_cnt <= 0)
1293 return -EINVAL;
1294
1295 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1296 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1297 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1298 if (!desc)
1299 return -EINVAL;
1300
1301 desc->callback = NULL;
1302 desc->callback_param = NULL;
1303
1304 cookie = dmaengine_submit(desc);
1305 if (dma_submit_error(cookie))
1306 ret = cookie;
1307
1308 return ret;
1309}
1310
1311static void sdhci_external_dma_release(struct sdhci_host *host)
1312{
1313 if (host->tx_chan) {
1314 dma_release_channel(host->tx_chan);
1315 host->tx_chan = NULL;
1316 }
1317
1318 if (host->rx_chan) {
1319 dma_release_channel(host->rx_chan);
1320 host->rx_chan = NULL;
1321 }
1322
1323 sdhci_switch_external_dma(host, false);
1324}
1325
1326static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1327 struct mmc_command *cmd)
1328{
1329 struct mmc_data *data = cmd->data;
1330
1331 sdhci_initialize_data(host, data);
1332
1333 host->flags |= SDHCI_REQ_USE_DMA;
1334 sdhci_set_transfer_irqs(host);
1335
1336 sdhci_set_block_info(host, data);
1337}
1338
1339static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1340 struct mmc_command *cmd)
1341{
1342 if (!sdhci_external_dma_setup(host, cmd)) {
1343 __sdhci_external_dma_prepare_data(host, cmd);
1344 } else {
1345 sdhci_external_dma_release(host);
1346 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1347 mmc_hostname(host->mmc));
1348 sdhci_prepare_data(host, cmd);
1349 }
1350}
1351
1352static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1353 struct mmc_command *cmd)
1354{
1355 struct dma_chan *chan;
1356
1357 if (!cmd->data)
1358 return;
1359
1360 chan = sdhci_external_dma_channel(host, cmd->data);
1361 if (chan)
1362 dma_async_issue_pending(chan);
1363}
1364
1365#else
1366
1367static inline int sdhci_external_dma_init(struct sdhci_host *host)
1368{
1369 return -EOPNOTSUPP;
1370}
1371
1372static inline void sdhci_external_dma_release(struct sdhci_host *host)
1373{
1374}
1375
1376static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1377 struct mmc_command *cmd)
1378{
1379 /* This should never happen */
1380 WARN_ON_ONCE(1);
1381}
1382
1383static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1384 struct mmc_command *cmd)
1385{
1386}
1387
1388static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1389 struct mmc_data *data)
1390{
1391 return NULL;
1392}
1393
1394#endif
1395
1396void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1397{
1398 host->use_external_dma = en;
1399}
1400EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1401
1402static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1403 struct mmc_request *mrq)
1404{
1405 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1406 !mrq->cap_cmd_during_tfr;
1407}
1408
1409static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1410 struct mmc_request *mrq)
1411{
1412 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1413}
1414
1415static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1416 struct mmc_request *mrq)
1417{
1418 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1419}
1420
1421static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1422 struct mmc_command *cmd,
1423 u16 *mode)
1424{
1425 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1426 (cmd->opcode != SD_IO_RW_EXTENDED);
1427 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1428 u16 ctrl2;
1429
1430 /*
1431 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1432 * Select' is recommended rather than use of 'Auto CMD12
1433 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1434 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1435 */
1436 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1437 (use_cmd12 || use_cmd23)) {
1438 *mode |= SDHCI_TRNS_AUTO_SEL;
1439
1440 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1441 if (use_cmd23)
1442 ctrl2 |= SDHCI_CMD23_ENABLE;
1443 else
1444 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1445 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1446
1447 return;
1448 }
1449
1450 /*
1451 * If we are sending CMD23, CMD12 never gets sent
1452 * on successful completion (so no Auto-CMD12).
1453 */
1454 if (use_cmd12)
1455 *mode |= SDHCI_TRNS_AUTO_CMD12;
1456 else if (use_cmd23)
1457 *mode |= SDHCI_TRNS_AUTO_CMD23;
1458}
1459
1460static void sdhci_set_transfer_mode(struct sdhci_host *host,
1461 struct mmc_command *cmd)
1462{
1463 u16 mode = 0;
1464 struct mmc_data *data = cmd->data;
1465
1466 if (data == NULL) {
1467 if (host->quirks2 &
1468 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1469 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1470 if (!mmc_op_tuning(cmd->opcode))
1471 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1472 } else {
1473 /* clear Auto CMD settings for no data CMDs */
1474 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1475 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1476 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1477 }
1478 return;
1479 }
1480
1481 WARN_ON(!host->data);
1482
1483 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1484 mode = SDHCI_TRNS_BLK_CNT_EN;
1485
1486 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1487 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1488 sdhci_auto_cmd_select(host, cmd, &mode);
1489 if (sdhci_auto_cmd23(host, cmd->mrq))
1490 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1491 }
1492
1493 if (data->flags & MMC_DATA_READ)
1494 mode |= SDHCI_TRNS_READ;
1495 if (host->flags & SDHCI_REQ_USE_DMA)
1496 mode |= SDHCI_TRNS_DMA;
1497
1498 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1499}
1500
1501bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1502{
1503 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1504 ((mrq->cmd && mrq->cmd->error) ||
1505 (mrq->sbc && mrq->sbc->error) ||
1506 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1507 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1508}
1509EXPORT_SYMBOL_GPL(sdhci_needs_reset);
1510
1511static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1512{
1513 int i;
1514
1515 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1516 if (host->mrqs_done[i] == mrq) {
1517 WARN_ON(1);
1518 return;
1519 }
1520 }
1521
1522 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1523 if (!host->mrqs_done[i]) {
1524 host->mrqs_done[i] = mrq;
1525 break;
1526 }
1527 }
1528
1529 WARN_ON(i >= SDHCI_MAX_MRQS);
1530}
1531
1532void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1533{
1534 if (host->cmd && host->cmd->mrq == mrq)
1535 host->cmd = NULL;
1536
1537 if (host->data_cmd && host->data_cmd->mrq == mrq)
1538 host->data_cmd = NULL;
1539
1540 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1541 host->deferred_cmd = NULL;
1542
1543 if (host->data && host->data->mrq == mrq)
1544 host->data = NULL;
1545
1546 if (sdhci_needs_reset(host, mrq))
1547 host->pending_reset = true;
1548
1549 sdhci_set_mrq_done(host, mrq);
1550
1551 sdhci_del_timer(host, mrq);
1552
1553 if (!sdhci_has_requests(host))
1554 sdhci_led_deactivate(host);
1555}
1556EXPORT_SYMBOL_GPL(__sdhci_finish_mrq);
1557
1558void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1559{
1560 __sdhci_finish_mrq(host, mrq);
1561
1562 queue_work(host->complete_wq, &host->complete_work);
1563}
1564EXPORT_SYMBOL_GPL(sdhci_finish_mrq);
1565
1566void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset)
1567{
1568 struct mmc_command *data_cmd = host->data_cmd;
1569 struct mmc_data *data = host->data;
1570
1571 host->data = NULL;
1572 host->data_cmd = NULL;
1573
1574 /*
1575 * The controller needs a reset of internal state machines upon error
1576 * conditions.
1577 */
1578 if (data->error) {
1579 if (defer_reset)
1580 host->pending_reset = true;
1581 else if (!host->cmd || host->cmd == data_cmd)
1582 sdhci_reset_for(host, REQUEST_ERROR);
1583 else
1584 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
1585 }
1586
1587 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1588 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1589 sdhci_adma_table_post(host, data);
1590
1591 /*
1592 * The specification states that the block count register must
1593 * be updated, but it does not specify at what point in the
1594 * data flow. That makes the register entirely useless to read
1595 * back so we have to assume that nothing made it to the card
1596 * in the event of an error.
1597 */
1598 if (data->error)
1599 data->bytes_xfered = 0;
1600 else
1601 data->bytes_xfered = data->blksz * data->blocks;
1602}
1603EXPORT_SYMBOL_GPL(__sdhci_finish_data_common);
1604
1605static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1606{
1607 struct mmc_data *data = host->data;
1608
1609 __sdhci_finish_data_common(host, false);
1610
1611 /*
1612 * Need to send CMD12 if -
1613 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1614 * b) error in multiblock transfer
1615 */
1616 if (data->stop &&
1617 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1618 data->error)) {
1619 /*
1620 * 'cap_cmd_during_tfr' request must not use the command line
1621 * after mmc_command_done() has been called. It is upper layer's
1622 * responsibility to send the stop command if required.
1623 */
1624 if (data->mrq->cap_cmd_during_tfr) {
1625 __sdhci_finish_mrq(host, data->mrq);
1626 } else {
1627 /* Avoid triggering warning in sdhci_send_command() */
1628 host->cmd = NULL;
1629 if (!sdhci_send_command(host, data->stop)) {
1630 if (sw_data_timeout) {
1631 /*
1632 * This is anyway a sw data timeout, so
1633 * give up now.
1634 */
1635 data->stop->error = -EIO;
1636 __sdhci_finish_mrq(host, data->mrq);
1637 } else {
1638 WARN_ON(host->deferred_cmd);
1639 host->deferred_cmd = data->stop;
1640 }
1641 }
1642 }
1643 } else {
1644 __sdhci_finish_mrq(host, data->mrq);
1645 }
1646}
1647
1648static void sdhci_finish_data(struct sdhci_host *host)
1649{
1650 __sdhci_finish_data(host, false);
1651}
1652
1653static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1654{
1655 int flags;
1656 u32 mask;
1657 unsigned long timeout;
1658
1659 WARN_ON(host->cmd);
1660
1661 /* Initially, a command has no error */
1662 cmd->error = 0;
1663
1664 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1665 cmd->opcode == MMC_STOP_TRANSMISSION)
1666 cmd->flags |= MMC_RSP_BUSY;
1667
1668 mask = SDHCI_CMD_INHIBIT;
1669 if (sdhci_data_line_cmd(cmd))
1670 mask |= SDHCI_DATA_INHIBIT;
1671
1672 /* We shouldn't wait for data inihibit for stop commands, even
1673 though they might use busy signaling */
1674 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1675 mask &= ~SDHCI_DATA_INHIBIT;
1676
1677 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1678 return false;
1679
1680 host->cmd = cmd;
1681 host->data_timeout = 0;
1682 if (sdhci_data_line_cmd(cmd)) {
1683 WARN_ON(host->data_cmd);
1684 host->data_cmd = cmd;
1685 sdhci_set_timeout(host, cmd);
1686 }
1687
1688 if (cmd->data) {
1689 if (host->use_external_dma)
1690 sdhci_external_dma_prepare_data(host, cmd);
1691 else
1692 sdhci_prepare_data(host, cmd);
1693 }
1694
1695 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1696
1697 sdhci_set_transfer_mode(host, cmd);
1698
1699 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1700 WARN_ONCE(1, "Unsupported response type!\n");
1701 /*
1702 * This does not happen in practice because 136-bit response
1703 * commands never have busy waiting, so rather than complicate
1704 * the error path, just remove busy waiting and continue.
1705 */
1706 cmd->flags &= ~MMC_RSP_BUSY;
1707 }
1708
1709 if (!(cmd->flags & MMC_RSP_PRESENT))
1710 flags = SDHCI_CMD_RESP_NONE;
1711 else if (cmd->flags & MMC_RSP_136)
1712 flags = SDHCI_CMD_RESP_LONG;
1713 else if (cmd->flags & MMC_RSP_BUSY)
1714 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1715 else
1716 flags = SDHCI_CMD_RESP_SHORT;
1717
1718 if (cmd->flags & MMC_RSP_CRC)
1719 flags |= SDHCI_CMD_CRC;
1720 if (cmd->flags & MMC_RSP_OPCODE)
1721 flags |= SDHCI_CMD_INDEX;
1722
1723 /* CMD19 is special in that the Data Present Select should be set */
1724 if (cmd->data || mmc_op_tuning(cmd->opcode))
1725 flags |= SDHCI_CMD_DATA;
1726
1727 timeout = jiffies;
1728 if (host->data_timeout)
1729 timeout += nsecs_to_jiffies(host->data_timeout);
1730 else if (!cmd->data && cmd->busy_timeout > 9000)
1731 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1732 else
1733 timeout += 10 * HZ;
1734 sdhci_mod_timer(host, cmd->mrq, timeout);
1735
1736 if (host->use_external_dma)
1737 sdhci_external_dma_pre_transfer(host, cmd);
1738
1739 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1740
1741 return true;
1742}
1743
1744bool sdhci_present_error(struct sdhci_host *host,
1745 struct mmc_command *cmd, bool present)
1746{
1747 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1748 cmd->error = -ENOMEDIUM;
1749 return true;
1750 }
1751
1752 return false;
1753}
1754EXPORT_SYMBOL_GPL(sdhci_present_error);
1755
1756static bool sdhci_send_command_retry(struct sdhci_host *host,
1757 struct mmc_command *cmd,
1758 unsigned long flags)
1759 __releases(host->lock)
1760 __acquires(host->lock)
1761{
1762 struct mmc_command *deferred_cmd = host->deferred_cmd;
1763 int timeout = 10; /* Approx. 10 ms */
1764 bool present;
1765
1766 while (!sdhci_send_command(host, cmd)) {
1767 if (!timeout--) {
1768 pr_err("%s: Controller never released inhibit bit(s).\n",
1769 mmc_hostname(host->mmc));
1770 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1771 sdhci_dumpregs(host);
1772 cmd->error = -EIO;
1773 return false;
1774 }
1775
1776 spin_unlock_irqrestore(&host->lock, flags);
1777
1778 usleep_range(1000, 1250);
1779
1780 present = host->mmc->ops->get_cd(host->mmc);
1781
1782 spin_lock_irqsave(&host->lock, flags);
1783
1784 /* A deferred command might disappear, handle that */
1785 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1786 return true;
1787
1788 if (sdhci_present_error(host, cmd, present))
1789 return false;
1790 }
1791
1792 if (cmd == host->deferred_cmd)
1793 host->deferred_cmd = NULL;
1794
1795 return true;
1796}
1797
1798static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1799{
1800 int i, reg;
1801
1802 for (i = 0; i < 4; i++) {
1803 reg = SDHCI_RESPONSE + (3 - i) * 4;
1804 cmd->resp[i] = sdhci_readl(host, reg);
1805 }
1806
1807 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1808 return;
1809
1810 /* CRC is stripped so we need to do some shifting */
1811 for (i = 0; i < 4; i++) {
1812 cmd->resp[i] <<= 8;
1813 if (i != 3)
1814 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1815 }
1816}
1817
1818static void sdhci_finish_command(struct sdhci_host *host)
1819{
1820 struct mmc_command *cmd = host->cmd;
1821
1822 host->cmd = NULL;
1823
1824 if (cmd->flags & MMC_RSP_PRESENT) {
1825 if (cmd->flags & MMC_RSP_136) {
1826 sdhci_read_rsp_136(host, cmd);
1827 } else {
1828 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1829 }
1830 }
1831
1832 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1833 mmc_command_done(host->mmc, cmd->mrq);
1834
1835 /*
1836 * The host can send and interrupt when the busy state has
1837 * ended, allowing us to wait without wasting CPU cycles.
1838 * The busy signal uses DAT0 so this is similar to waiting
1839 * for data to complete.
1840 *
1841 * Note: The 1.0 specification is a bit ambiguous about this
1842 * feature so there might be some problems with older
1843 * controllers.
1844 */
1845 if (cmd->flags & MMC_RSP_BUSY) {
1846 if (cmd->data) {
1847 DBG("Cannot wait for busy signal when also doing a data transfer");
1848 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1849 cmd == host->data_cmd) {
1850 /* Command complete before busy is ended */
1851 return;
1852 }
1853 }
1854
1855 /* Finished CMD23, now send actual command. */
1856 if (cmd == cmd->mrq->sbc) {
1857 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1858 WARN_ON(host->deferred_cmd);
1859 host->deferred_cmd = cmd->mrq->cmd;
1860 }
1861 } else {
1862
1863 /* Processed actual command. */
1864 if (host->data && host->data_early)
1865 sdhci_finish_data(host);
1866
1867 if (!cmd->data)
1868 __sdhci_finish_mrq(host, cmd->mrq);
1869 }
1870}
1871
1872static u16 sdhci_get_preset_value(struct sdhci_host *host)
1873{
1874 u16 preset = 0;
1875
1876 switch (host->timing) {
1877 case MMC_TIMING_MMC_HS:
1878 case MMC_TIMING_SD_HS:
1879 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1880 break;
1881 case MMC_TIMING_UHS_SDR12:
1882 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1883 break;
1884 case MMC_TIMING_UHS_SDR25:
1885 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1886 break;
1887 case MMC_TIMING_UHS_SDR50:
1888 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1889 break;
1890 case MMC_TIMING_UHS_SDR104:
1891 case MMC_TIMING_MMC_HS200:
1892 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1893 break;
1894 case MMC_TIMING_UHS_DDR50:
1895 case MMC_TIMING_MMC_DDR52:
1896 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1897 break;
1898 case MMC_TIMING_MMC_HS400:
1899 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1900 break;
1901 case MMC_TIMING_UHS2_SPEED_A:
1902 case MMC_TIMING_UHS2_SPEED_A_HD:
1903 case MMC_TIMING_UHS2_SPEED_B:
1904 case MMC_TIMING_UHS2_SPEED_B_HD:
1905 preset = sdhci_readw(host, SDHCI_PRESET_FOR_UHS2);
1906 break;
1907 default:
1908 pr_warn("%s: Invalid UHS-I mode selected\n",
1909 mmc_hostname(host->mmc));
1910 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1911 break;
1912 }
1913 return preset;
1914}
1915
1916u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1917 unsigned int *actual_clock)
1918{
1919 int div = 0; /* Initialized for compiler warning */
1920 int real_div = div, clk_mul = 1;
1921 u16 clk = 0;
1922 bool switch_base_clk = false;
1923
1924 if (host->version >= SDHCI_SPEC_300) {
1925 if (host->preset_enabled) {
1926 u16 pre_val;
1927
1928 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1929 pre_val = sdhci_get_preset_value(host);
1930 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1931 if (host->clk_mul &&
1932 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1933 clk = SDHCI_PROG_CLOCK_MODE;
1934 real_div = div + 1;
1935 clk_mul = host->clk_mul;
1936 } else {
1937 real_div = max_t(int, 1, div << 1);
1938 }
1939 goto clock_set;
1940 }
1941
1942 /*
1943 * Check if the Host Controller supports Programmable Clock
1944 * Mode.
1945 */
1946 if (host->clk_mul) {
1947 for (div = 1; div <= 1024; div++) {
1948 if ((host->max_clk * host->clk_mul / div)
1949 <= clock)
1950 break;
1951 }
1952 if ((host->max_clk * host->clk_mul / div) <= clock) {
1953 /*
1954 * Set Programmable Clock Mode in the Clock
1955 * Control register.
1956 */
1957 clk = SDHCI_PROG_CLOCK_MODE;
1958 real_div = div;
1959 clk_mul = host->clk_mul;
1960 div--;
1961 } else {
1962 /*
1963 * Divisor can be too small to reach clock
1964 * speed requirement. Then use the base clock.
1965 */
1966 switch_base_clk = true;
1967 }
1968 }
1969
1970 if (!host->clk_mul || switch_base_clk) {
1971 /* Version 3.00 divisors must be a multiple of 2. */
1972 if (host->max_clk <= clock)
1973 div = 1;
1974 else {
1975 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1976 div += 2) {
1977 if ((host->max_clk / div) <= clock)
1978 break;
1979 }
1980 }
1981 real_div = div;
1982 div >>= 1;
1983 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1984 && !div && host->max_clk <= 25000000)
1985 div = 1;
1986 }
1987 } else {
1988 /* Version 2.00 divisors must be a power of 2. */
1989 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1990 if ((host->max_clk / div) <= clock)
1991 break;
1992 }
1993 real_div = div;
1994 div >>= 1;
1995 }
1996
1997clock_set:
1998 if (real_div)
1999 *actual_clock = (host->max_clk * clk_mul) / real_div;
2000 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
2001 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
2002 << SDHCI_DIVIDER_HI_SHIFT;
2003
2004 return clk;
2005}
2006EXPORT_SYMBOL_GPL(sdhci_calc_clk);
2007
2008void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
2009{
2010 ktime_t timeout;
2011
2012 clk |= SDHCI_CLOCK_INT_EN;
2013 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2014
2015 /* Wait max 150 ms */
2016 timeout = ktime_add_ms(ktime_get(), 150);
2017 while (1) {
2018 bool timedout = ktime_after(ktime_get(), timeout);
2019
2020 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2021 if (clk & SDHCI_CLOCK_INT_STABLE)
2022 break;
2023 if (timedout) {
2024 pr_err("%s: Internal clock never stabilised.\n",
2025 mmc_hostname(host->mmc));
2026 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2027 sdhci_dumpregs(host);
2028 return;
2029 }
2030 udelay(10);
2031 }
2032
2033 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2034 clk |= SDHCI_CLOCK_PLL_EN;
2035 clk &= ~SDHCI_CLOCK_INT_STABLE;
2036 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2037
2038 /* Wait max 150 ms */
2039 timeout = ktime_add_ms(ktime_get(), 150);
2040 while (1) {
2041 bool timedout = ktime_after(ktime_get(), timeout);
2042
2043 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2044 if (clk & SDHCI_CLOCK_INT_STABLE)
2045 break;
2046 if (timedout) {
2047 pr_err("%s: PLL clock never stabilised.\n",
2048 mmc_hostname(host->mmc));
2049 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2050 sdhci_dumpregs(host);
2051 return;
2052 }
2053 udelay(10);
2054 }
2055 }
2056
2057 clk |= SDHCI_CLOCK_CARD_EN;
2058 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2059}
2060EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2061
2062void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2063{
2064 u16 clk;
2065
2066 host->mmc->actual_clock = 0;
2067
2068 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2069
2070 if (clock == 0)
2071 return;
2072
2073 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2074 sdhci_enable_clk(host, clk);
2075}
2076EXPORT_SYMBOL_GPL(sdhci_set_clock);
2077
2078static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2079 unsigned short vdd)
2080{
2081 struct mmc_host *mmc = host->mmc;
2082
2083 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2084
2085 if (mode != MMC_POWER_OFF)
2086 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2087 else
2088 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2089}
2090
2091unsigned short sdhci_get_vdd_value(unsigned short vdd)
2092{
2093 switch (1 << vdd) {
2094 case MMC_VDD_165_195:
2095 /*
2096 * Without a regulator, SDHCI does not support 2.0v
2097 * so we only get here if the driver deliberately
2098 * added the 2.0v range to ocr_avail. Map it to 1.8v
2099 * for the purpose of turning on the power.
2100 */
2101 case MMC_VDD_20_21:
2102 return SDHCI_POWER_180;
2103 case MMC_VDD_29_30:
2104 case MMC_VDD_30_31:
2105 return SDHCI_POWER_300;
2106 case MMC_VDD_32_33:
2107 case MMC_VDD_33_34:
2108 /*
2109 * 3.4V ~ 3.6V are valid only for those platforms where it's
2110 * known that the voltage range is supported by hardware.
2111 */
2112 case MMC_VDD_34_35:
2113 case MMC_VDD_35_36:
2114 return SDHCI_POWER_330;
2115 default:
2116 return 0;
2117 }
2118}
2119EXPORT_SYMBOL_GPL(sdhci_get_vdd_value);
2120
2121void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2122 unsigned short vdd)
2123{
2124 u8 pwr = 0;
2125
2126 if (mode != MMC_POWER_OFF) {
2127 pwr = sdhci_get_vdd_value(vdd);
2128 if (!pwr) {
2129 WARN(1, "%s: Invalid vdd %#x\n",
2130 mmc_hostname(host->mmc), vdd);
2131 }
2132 }
2133
2134 if (host->pwr == pwr)
2135 return;
2136
2137 host->pwr = pwr;
2138
2139 if (pwr == 0) {
2140 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2141 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2142 sdhci_runtime_pm_bus_off(host);
2143 } else {
2144 /*
2145 * Spec says that we should clear the power reg before setting
2146 * a new value. Some controllers don't seem to like this though.
2147 */
2148 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2149 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2150
2151 /*
2152 * At least the Marvell CaFe chip gets confused if we set the
2153 * voltage and set turn on power at the same time, so set the
2154 * voltage first.
2155 */
2156 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2157 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2158
2159 pwr |= SDHCI_POWER_ON;
2160
2161 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2162
2163 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2164 sdhci_runtime_pm_bus_on(host);
2165
2166 /*
2167 * Some controllers need an extra 10ms delay of 10ms before
2168 * they can apply clock after applying power
2169 */
2170 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2171 mdelay(10);
2172 }
2173}
2174EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2175
2176void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2177 unsigned short vdd)
2178{
2179 if (IS_ERR(host->mmc->supply.vmmc))
2180 sdhci_set_power_noreg(host, mode, vdd);
2181 else
2182 sdhci_set_power_reg(host, mode, vdd);
2183}
2184EXPORT_SYMBOL_GPL(sdhci_set_power);
2185
2186/*
2187 * Some controllers need to configure a valid bus voltage on their power
2188 * register regardless of whether an external regulator is taking care of power
2189 * supply. This helper function takes care of it if set as the controller's
2190 * sdhci_ops.set_power callback.
2191 */
2192void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2193 unsigned char mode,
2194 unsigned short vdd)
2195{
2196 if (!IS_ERR(host->mmc->supply.vmmc)) {
2197 struct mmc_host *mmc = host->mmc;
2198
2199 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2200 }
2201 sdhci_set_power_noreg(host, mode, vdd);
2202}
2203EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2204
2205/*****************************************************************************\
2206 * *
2207 * MMC callbacks *
2208 * *
2209\*****************************************************************************/
2210
2211void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2212{
2213 struct sdhci_host *host = mmc_priv(mmc);
2214 struct mmc_command *cmd;
2215 unsigned long flags;
2216 bool present;
2217
2218 /* Firstly check card presence */
2219 present = mmc->ops->get_cd(mmc);
2220
2221 spin_lock_irqsave(&host->lock, flags);
2222
2223 sdhci_led_activate(host);
2224
2225 if (sdhci_present_error(host, mrq->cmd, present))
2226 goto out_finish;
2227
2228 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2229
2230 if (!sdhci_send_command_retry(host, cmd, flags))
2231 goto out_finish;
2232
2233 spin_unlock_irqrestore(&host->lock, flags);
2234
2235 return;
2236
2237out_finish:
2238 sdhci_finish_mrq(host, mrq);
2239 spin_unlock_irqrestore(&host->lock, flags);
2240}
2241EXPORT_SYMBOL_GPL(sdhci_request);
2242
2243int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2244{
2245 struct sdhci_host *host = mmc_priv(mmc);
2246 struct mmc_command *cmd;
2247 unsigned long flags;
2248 int ret = 0;
2249
2250 spin_lock_irqsave(&host->lock, flags);
2251
2252 if (sdhci_present_error(host, mrq->cmd, true)) {
2253 sdhci_finish_mrq(host, mrq);
2254 goto out_finish;
2255 }
2256
2257 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2258
2259 /*
2260 * The HSQ may send a command in interrupt context without polling
2261 * the busy signaling, which means we should return BUSY if controller
2262 * has not released inhibit bits to allow HSQ trying to send request
2263 * again in non-atomic context. So we should not finish this request
2264 * here.
2265 */
2266 if (!sdhci_send_command(host, cmd))
2267 ret = -EBUSY;
2268 else
2269 sdhci_led_activate(host);
2270
2271out_finish:
2272 spin_unlock_irqrestore(&host->lock, flags);
2273 return ret;
2274}
2275EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2276
2277void sdhci_set_bus_width(struct sdhci_host *host, int width)
2278{
2279 u8 ctrl;
2280
2281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2282 if (width == MMC_BUS_WIDTH_8) {
2283 ctrl &= ~SDHCI_CTRL_4BITBUS;
2284 ctrl |= SDHCI_CTRL_8BITBUS;
2285 } else {
2286 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2287 ctrl &= ~SDHCI_CTRL_8BITBUS;
2288 if (width == MMC_BUS_WIDTH_4)
2289 ctrl |= SDHCI_CTRL_4BITBUS;
2290 else
2291 ctrl &= ~SDHCI_CTRL_4BITBUS;
2292 }
2293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2294}
2295EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2296
2297void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2298{
2299 u16 ctrl_2;
2300
2301 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2302 /* Select Bus Speed Mode for host */
2303 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2304 if ((timing == MMC_TIMING_MMC_HS200) ||
2305 (timing == MMC_TIMING_UHS_SDR104))
2306 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2307 else if (timing == MMC_TIMING_UHS_SDR12)
2308 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2309 else if (timing == MMC_TIMING_UHS_SDR25)
2310 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2311 else if (timing == MMC_TIMING_UHS_SDR50)
2312 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2313 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2314 (timing == MMC_TIMING_MMC_DDR52))
2315 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2316 else if (timing == MMC_TIMING_MMC_HS400)
2317 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2318 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2319}
2320EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2321
2322static bool sdhci_timing_has_preset(unsigned char timing)
2323{
2324 switch (timing) {
2325 case MMC_TIMING_UHS_SDR12:
2326 case MMC_TIMING_UHS_SDR25:
2327 case MMC_TIMING_UHS_SDR50:
2328 case MMC_TIMING_UHS_SDR104:
2329 case MMC_TIMING_UHS_DDR50:
2330 case MMC_TIMING_MMC_DDR52:
2331 return true;
2332 }
2333 return false;
2334}
2335
2336static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2337{
2338 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2339 sdhci_timing_has_preset(timing);
2340}
2341
2342static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2343{
2344 /*
2345 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
2346 * Frequency. Check if preset values need to be enabled, or the Driver
2347 * Strength needs updating. Note, clock changes are handled separately.
2348 */
2349 return !host->preset_enabled &&
2350 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2351}
2352
2353void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios)
2354{
2355 struct sdhci_host *host = mmc_priv(mmc);
2356
2357 /*
2358 * Reset the chip on each power off.
2359 * Should clear out any weird states.
2360 */
2361 if (ios->power_mode == MMC_POWER_OFF) {
2362 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2363 sdhci_reinit(host);
2364 }
2365
2366 if (host->version >= SDHCI_SPEC_300 &&
2367 (ios->power_mode == MMC_POWER_UP) &&
2368 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2369 sdhci_enable_preset_value(host, false);
2370
2371 if (!ios->clock || ios->clock != host->clock) {
2372 host->ops->set_clock(host, ios->clock);
2373 host->clock = ios->clock;
2374
2375 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2376 host->clock) {
2377 host->timeout_clk = mmc->actual_clock ?
2378 mmc->actual_clock / 1000 :
2379 host->clock / 1000;
2380 mmc->max_busy_timeout =
2381 host->ops->get_max_timeout_count ?
2382 host->ops->get_max_timeout_count(host) :
2383 1 << 27;
2384 mmc->max_busy_timeout /= host->timeout_clk;
2385 }
2386 }
2387}
2388EXPORT_SYMBOL_GPL(sdhci_set_ios_common);
2389
2390void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2391{
2392 struct sdhci_host *host = mmc_priv(mmc);
2393 bool reinit_uhs = host->reinit_uhs;
2394 bool turning_on_clk;
2395 u8 ctrl;
2396
2397 host->reinit_uhs = false;
2398
2399 if (ios->power_mode == MMC_POWER_UNDEFINED)
2400 return;
2401
2402 if (host->flags & SDHCI_DEVICE_DEAD) {
2403 if (!IS_ERR(mmc->supply.vmmc) &&
2404 ios->power_mode == MMC_POWER_OFF)
2405 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2406 return;
2407 }
2408
2409 turning_on_clk = ios->clock != host->clock && ios->clock && !host->clock;
2410
2411 sdhci_set_ios_common(mmc, ios);
2412
2413 if (host->ops->set_power)
2414 host->ops->set_power(host, ios->power_mode, ios->vdd);
2415 else
2416 sdhci_set_power(host, ios->power_mode, ios->vdd);
2417
2418 if (host->ops->platform_send_init_74_clocks)
2419 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2420
2421 host->ops->set_bus_width(host, ios->bus_width);
2422
2423 /*
2424 * Special case to avoid multiple clock changes during voltage
2425 * switching.
2426 */
2427 if (!reinit_uhs &&
2428 turning_on_clk &&
2429 host->timing == ios->timing &&
2430 host->version >= SDHCI_SPEC_300 &&
2431 !sdhci_presetable_values_change(host, ios))
2432 return;
2433
2434 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2435
2436 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2437 if (ios->timing == MMC_TIMING_SD_HS ||
2438 ios->timing == MMC_TIMING_MMC_HS ||
2439 ios->timing == MMC_TIMING_MMC_HS400 ||
2440 ios->timing == MMC_TIMING_MMC_HS200 ||
2441 ios->timing == MMC_TIMING_MMC_DDR52 ||
2442 ios->timing == MMC_TIMING_UHS_SDR50 ||
2443 ios->timing == MMC_TIMING_UHS_SDR104 ||
2444 ios->timing == MMC_TIMING_UHS_DDR50 ||
2445 ios->timing == MMC_TIMING_UHS_SDR25)
2446 ctrl |= SDHCI_CTRL_HISPD;
2447 else
2448 ctrl &= ~SDHCI_CTRL_HISPD;
2449 }
2450
2451 if (host->version >= SDHCI_SPEC_300) {
2452 u16 clk, ctrl_2;
2453
2454 /*
2455 * According to SDHCI Spec v3.00, if the Preset Value
2456 * Enable in the Host Control 2 register is set, we
2457 * need to reset SD Clock Enable before changing High
2458 * Speed Enable to avoid generating clock glitches.
2459 */
2460 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2461 if (clk & SDHCI_CLOCK_CARD_EN) {
2462 clk &= ~SDHCI_CLOCK_CARD_EN;
2463 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2464 }
2465
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2467
2468 if (!host->preset_enabled) {
2469 /*
2470 * We only need to set Driver Strength if the
2471 * preset value enable is not set.
2472 */
2473 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2474 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2475 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2476 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2477 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2478 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2479 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2480 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2481 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2482 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2483 else {
2484 pr_warn("%s: invalid driver type, default to driver type B\n",
2485 mmc_hostname(mmc));
2486 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2487 }
2488
2489 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2490 host->drv_type = ios->drv_type;
2491 }
2492
2493 host->ops->set_uhs_signaling(host, ios->timing);
2494 host->timing = ios->timing;
2495
2496 if (sdhci_preset_needed(host, ios->timing)) {
2497 u16 preset;
2498
2499 sdhci_enable_preset_value(host, true);
2500 preset = sdhci_get_preset_value(host);
2501 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2502 preset);
2503 host->drv_type = ios->drv_type;
2504 }
2505
2506 /* Re-enable SD Clock */
2507 host->ops->set_clock(host, host->clock);
2508 } else
2509 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2510}
2511EXPORT_SYMBOL_GPL(sdhci_set_ios);
2512
2513static int sdhci_get_cd(struct mmc_host *mmc)
2514{
2515 struct sdhci_host *host = mmc_priv(mmc);
2516 int gpio_cd = mmc_gpio_get_cd(mmc);
2517
2518 if (host->flags & SDHCI_DEVICE_DEAD)
2519 return 0;
2520
2521 /* If nonremovable, assume that the card is always present. */
2522 if (!mmc_card_is_removable(mmc))
2523 return 1;
2524
2525 /*
2526 * Try slot gpio detect, if defined it take precedence
2527 * over build in controller functionality
2528 */
2529 if (gpio_cd >= 0)
2530 return !!gpio_cd;
2531
2532 /* If polling, assume that the card is always present. */
2533 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2534 return 1;
2535
2536 /* Host native card detect */
2537 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2538}
2539
2540int sdhci_get_cd_nogpio(struct mmc_host *mmc)
2541{
2542 struct sdhci_host *host = mmc_priv(mmc);
2543 unsigned long flags;
2544 int ret = 0;
2545
2546 spin_lock_irqsave(&host->lock, flags);
2547
2548 if (host->flags & SDHCI_DEVICE_DEAD)
2549 goto out;
2550
2551 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2552out:
2553 spin_unlock_irqrestore(&host->lock, flags);
2554
2555 return ret;
2556}
2557EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
2558
2559int sdhci_get_ro(struct mmc_host *mmc)
2560{
2561 struct sdhci_host *host = mmc_priv(mmc);
2562 bool allow_invert = false;
2563 int is_readonly;
2564
2565 if (host->flags & SDHCI_DEVICE_DEAD) {
2566 is_readonly = 0;
2567 } else if (host->ops->get_ro) {
2568 is_readonly = host->ops->get_ro(host);
2569 } else if (mmc_can_gpio_ro(mmc)) {
2570 is_readonly = mmc_gpio_get_ro(mmc);
2571 /* Do not invert twice */
2572 allow_invert = !(mmc->caps2 & MMC_CAP2_RO_ACTIVE_HIGH);
2573 } else {
2574 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2575 & SDHCI_WRITE_PROTECT);
2576 allow_invert = true;
2577 }
2578
2579 if (is_readonly >= 0 &&
2580 allow_invert &&
2581 (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT))
2582 is_readonly = !is_readonly;
2583
2584 return is_readonly;
2585}
2586EXPORT_SYMBOL_GPL(sdhci_get_ro);
2587
2588static void sdhci_hw_reset(struct mmc_host *mmc)
2589{
2590 struct sdhci_host *host = mmc_priv(mmc);
2591
2592 if (host->ops && host->ops->hw_reset)
2593 host->ops->hw_reset(host);
2594}
2595
2596static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2597{
2598 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2599 if (enable)
2600 host->ier |= SDHCI_INT_CARD_INT;
2601 else
2602 host->ier &= ~SDHCI_INT_CARD_INT;
2603
2604 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2605 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2606 }
2607}
2608
2609void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2610{
2611 struct sdhci_host *host = mmc_priv(mmc);
2612 unsigned long flags;
2613
2614 if (enable)
2615 pm_runtime_get_noresume(mmc_dev(mmc));
2616
2617 spin_lock_irqsave(&host->lock, flags);
2618 sdhci_enable_sdio_irq_nolock(host, enable);
2619 spin_unlock_irqrestore(&host->lock, flags);
2620
2621 if (!enable)
2622 pm_runtime_put_noidle(mmc_dev(mmc));
2623}
2624EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2625
2626static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2627{
2628 struct sdhci_host *host = mmc_priv(mmc);
2629 unsigned long flags;
2630
2631 spin_lock_irqsave(&host->lock, flags);
2632 sdhci_enable_sdio_irq_nolock(host, true);
2633 spin_unlock_irqrestore(&host->lock, flags);
2634}
2635
2636int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2637 struct mmc_ios *ios)
2638{
2639 struct sdhci_host *host = mmc_priv(mmc);
2640 u16 ctrl;
2641 int ret;
2642
2643 /*
2644 * Signal Voltage Switching is only applicable for Host Controllers
2645 * v3.00 and above.
2646 */
2647 if (host->version < SDHCI_SPEC_300)
2648 return 0;
2649
2650 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2651
2652 switch (ios->signal_voltage) {
2653 case MMC_SIGNAL_VOLTAGE_330:
2654 if (!(host->flags & SDHCI_SIGNALING_330))
2655 return -EINVAL;
2656 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2657 ctrl &= ~SDHCI_CTRL_VDD_180;
2658 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2659
2660 if (!IS_ERR(mmc->supply.vqmmc)) {
2661 ret = mmc_regulator_set_vqmmc(mmc, ios);
2662 if (ret < 0) {
2663 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2664 mmc_hostname(mmc));
2665 return -EIO;
2666 }
2667 }
2668 /* Wait for 5ms */
2669 usleep_range(5000, 5500);
2670
2671 /* 3.3V regulator output should be stable within 5 ms */
2672 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2673 if (!(ctrl & SDHCI_CTRL_VDD_180))
2674 return 0;
2675
2676 pr_warn("%s: 3.3V regulator output did not become stable\n",
2677 mmc_hostname(mmc));
2678
2679 return -EAGAIN;
2680 case MMC_SIGNAL_VOLTAGE_180:
2681 if (!(host->flags & SDHCI_SIGNALING_180))
2682 return -EINVAL;
2683 if (!IS_ERR(mmc->supply.vqmmc)) {
2684 ret = mmc_regulator_set_vqmmc(mmc, ios);
2685 if (ret < 0) {
2686 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2687 mmc_hostname(mmc));
2688 return -EIO;
2689 }
2690 }
2691
2692 /*
2693 * Enable 1.8V Signal Enable in the Host Control2
2694 * register
2695 */
2696 ctrl |= SDHCI_CTRL_VDD_180;
2697 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2698
2699 /* Some controller need to do more when switching */
2700 if (host->ops->voltage_switch)
2701 host->ops->voltage_switch(host);
2702
2703 /* 1.8V regulator output should be stable within 5 ms */
2704 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2705 if (ctrl & SDHCI_CTRL_VDD_180)
2706 return 0;
2707
2708 pr_warn("%s: 1.8V regulator output did not become stable\n",
2709 mmc_hostname(mmc));
2710
2711 return -EAGAIN;
2712 case MMC_SIGNAL_VOLTAGE_120:
2713 if (!(host->flags & SDHCI_SIGNALING_120))
2714 return -EINVAL;
2715 if (!IS_ERR(mmc->supply.vqmmc)) {
2716 ret = mmc_regulator_set_vqmmc(mmc, ios);
2717 if (ret < 0) {
2718 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2719 mmc_hostname(mmc));
2720 return -EIO;
2721 }
2722 }
2723 return 0;
2724 default:
2725 /* No signal voltage switch required */
2726 return 0;
2727 }
2728}
2729EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2730
2731static int sdhci_card_busy(struct mmc_host *mmc)
2732{
2733 struct sdhci_host *host = mmc_priv(mmc);
2734 u32 present_state;
2735
2736 /* Check whether DAT[0] is 0 */
2737 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2738
2739 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2740}
2741
2742static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2743{
2744 struct sdhci_host *host = mmc_priv(mmc);
2745 unsigned long flags;
2746
2747 spin_lock_irqsave(&host->lock, flags);
2748 host->flags |= SDHCI_HS400_TUNING;
2749 spin_unlock_irqrestore(&host->lock, flags);
2750
2751 return 0;
2752}
2753
2754void sdhci_start_tuning(struct sdhci_host *host)
2755{
2756 u16 ctrl;
2757
2758 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2759 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2760 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2761 ctrl |= SDHCI_CTRL_TUNED_CLK;
2762 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2763
2764 /*
2765 * As per the Host Controller spec v3.00, tuning command
2766 * generates Buffer Read Ready interrupt, so enable that.
2767 *
2768 * Note: The spec clearly says that when tuning sequence
2769 * is being performed, the controller does not generate
2770 * interrupts other than Buffer Read Ready interrupt. But
2771 * to make sure we don't hit a controller bug, we _only_
2772 * enable Buffer Read Ready interrupt here.
2773 */
2774 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2775 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2776}
2777EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2778
2779void sdhci_end_tuning(struct sdhci_host *host)
2780{
2781 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2782 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2783}
2784EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2785
2786void sdhci_reset_tuning(struct sdhci_host *host)
2787{
2788 u16 ctrl;
2789
2790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2791 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2792 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2793 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2794}
2795EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2796
2797void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2798{
2799 sdhci_reset_tuning(host);
2800
2801 sdhci_reset_for(host, TUNING_ABORT);
2802
2803 sdhci_end_tuning(host);
2804
2805 mmc_send_abort_tuning(host->mmc, opcode);
2806}
2807EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2808
2809/*
2810 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2811 * tuning command does not have a data payload (or rather the hardware does it
2812 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2813 * interrupt setup is different to other commands and there is no timeout
2814 * interrupt so special handling is needed.
2815 */
2816void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2817{
2818 struct mmc_host *mmc = host->mmc;
2819 struct mmc_command cmd = {};
2820 struct mmc_request mrq = {};
2821 unsigned long flags;
2822 u32 b = host->sdma_boundary;
2823
2824 spin_lock_irqsave(&host->lock, flags);
2825
2826 cmd.opcode = opcode;
2827 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2828 cmd.mrq = &mrq;
2829
2830 mrq.cmd = &cmd;
2831 /*
2832 * In response to CMD19, the card sends 64 bytes of tuning
2833 * block to the Host Controller. So we set the block size
2834 * to 64 here.
2835 */
2836 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2837 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2838 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2839 else
2840 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2841
2842 /*
2843 * The tuning block is sent by the card to the host controller.
2844 * So we set the TRNS_READ bit in the Transfer Mode register.
2845 * This also takes care of setting DMA Enable and Multi Block
2846 * Select in the same register to 0.
2847 */
2848 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2849
2850 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2851 spin_unlock_irqrestore(&host->lock, flags);
2852 host->tuning_done = 0;
2853 return;
2854 }
2855
2856 host->cmd = NULL;
2857
2858 sdhci_del_timer(host, &mrq);
2859
2860 host->tuning_done = 0;
2861
2862 spin_unlock_irqrestore(&host->lock, flags);
2863
2864 /* Wait for Buffer Read Ready interrupt */
2865 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2866 msecs_to_jiffies(50));
2867
2868}
2869EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2870
2871int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2872{
2873 int i;
2874
2875 /*
2876 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2877 * of loops reaches tuning loop count.
2878 */
2879 for (i = 0; i < host->tuning_loop_count; i++) {
2880 u16 ctrl;
2881
2882 sdhci_send_tuning(host, opcode);
2883
2884 if (!host->tuning_done) {
2885 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2886 mmc_hostname(host->mmc));
2887 sdhci_abort_tuning(host, opcode);
2888 return -ETIMEDOUT;
2889 }
2890
2891 /* Spec does not require a delay between tuning cycles */
2892 if (host->tuning_delay > 0)
2893 mdelay(host->tuning_delay);
2894
2895 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2896 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2897 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2898 return 0; /* Success! */
2899 break;
2900 }
2901
2902 }
2903
2904 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2905 mmc_hostname(host->mmc));
2906 sdhci_reset_tuning(host);
2907 return -EAGAIN;
2908}
2909EXPORT_SYMBOL_GPL(__sdhci_execute_tuning);
2910
2911int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2912{
2913 struct sdhci_host *host = mmc_priv(mmc);
2914 int err = 0;
2915 unsigned int tuning_count = 0;
2916 bool hs400_tuning;
2917
2918 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2919
2920 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2921 tuning_count = host->tuning_count;
2922
2923 /*
2924 * The Host Controller needs tuning in case of SDR104 and DDR50
2925 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2926 * the Capabilities register.
2927 * If the Host Controller supports the HS200 mode then the
2928 * tuning function has to be executed.
2929 */
2930 switch (host->timing) {
2931 /* HS400 tuning is done in HS200 mode */
2932 case MMC_TIMING_MMC_HS400:
2933 err = -EINVAL;
2934 goto out;
2935
2936 case MMC_TIMING_MMC_HS200:
2937 /*
2938 * Periodic re-tuning for HS400 is not expected to be needed, so
2939 * disable it here.
2940 */
2941 if (hs400_tuning)
2942 tuning_count = 0;
2943 break;
2944
2945 case MMC_TIMING_UHS_SDR104:
2946 case MMC_TIMING_UHS_DDR50:
2947 break;
2948
2949 case MMC_TIMING_UHS_SDR50:
2950 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2951 break;
2952 fallthrough;
2953
2954 default:
2955 goto out;
2956 }
2957
2958 if (host->ops->platform_execute_tuning) {
2959 err = host->ops->platform_execute_tuning(host, opcode);
2960 goto out;
2961 }
2962
2963 mmc->retune_period = tuning_count;
2964
2965 if (host->tuning_delay < 0)
2966 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2967
2968 sdhci_start_tuning(host);
2969
2970 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2971
2972 sdhci_end_tuning(host);
2973out:
2974 host->flags &= ~SDHCI_HS400_TUNING;
2975
2976 return err;
2977}
2978EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2979
2980void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2981{
2982 /* Host Controller v3.00 defines preset value registers */
2983 if (host->version < SDHCI_SPEC_300)
2984 return;
2985
2986 /*
2987 * We only enable or disable Preset Value if they are not already
2988 * enabled or disabled respectively. Otherwise, we bail out.
2989 */
2990 if (host->preset_enabled != enable) {
2991 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2992
2993 if (enable)
2994 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2995 else
2996 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2997
2998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2999
3000 if (enable)
3001 host->flags |= SDHCI_PV_ENABLED;
3002 else
3003 host->flags &= ~SDHCI_PV_ENABLED;
3004
3005 host->preset_enabled = enable;
3006 }
3007}
3008EXPORT_SYMBOL_GPL(sdhci_enable_preset_value);
3009
3010static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
3011 int err)
3012{
3013 struct mmc_data *data = mrq->data;
3014
3015 if (data->host_cookie != COOKIE_UNMAPPED)
3016 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
3017 mmc_get_dma_dir(data));
3018
3019 data->host_cookie = COOKIE_UNMAPPED;
3020}
3021
3022static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
3023{
3024 struct sdhci_host *host = mmc_priv(mmc);
3025
3026 mrq->data->host_cookie = COOKIE_UNMAPPED;
3027
3028 /*
3029 * No pre-mapping in the pre hook if we're using the bounce buffer,
3030 * for that we would need two bounce buffers since one buffer is
3031 * in flight when this is getting called.
3032 */
3033 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
3034 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
3035}
3036
3037static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3038{
3039 if (host->data_cmd) {
3040 host->data_cmd->error = err;
3041 sdhci_finish_mrq(host, host->data_cmd->mrq);
3042 }
3043
3044 if (host->cmd) {
3045 host->cmd->error = err;
3046 sdhci_finish_mrq(host, host->cmd->mrq);
3047 }
3048}
3049
3050static void sdhci_card_event(struct mmc_host *mmc)
3051{
3052 struct sdhci_host *host = mmc_priv(mmc);
3053 unsigned long flags;
3054 int present;
3055
3056 /* First check if client has provided their own card event */
3057 if (host->ops->card_event)
3058 host->ops->card_event(host);
3059
3060 present = mmc->ops->get_cd(mmc);
3061
3062 spin_lock_irqsave(&host->lock, flags);
3063
3064 /* Check sdhci_has_requests() first in case we are runtime suspended */
3065 if (sdhci_has_requests(host) && !present) {
3066 pr_err("%s: Card removed during transfer!\n",
3067 mmc_hostname(mmc));
3068 pr_err("%s: Resetting controller.\n",
3069 mmc_hostname(mmc));
3070
3071 sdhci_reset_for(host, CARD_REMOVED);
3072
3073 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3074 }
3075
3076 spin_unlock_irqrestore(&host->lock, flags);
3077}
3078
3079static const struct mmc_host_ops sdhci_ops = {
3080 .request = sdhci_request,
3081 .post_req = sdhci_post_req,
3082 .pre_req = sdhci_pre_req,
3083 .set_ios = sdhci_set_ios,
3084 .get_cd = sdhci_get_cd,
3085 .get_ro = sdhci_get_ro,
3086 .card_hw_reset = sdhci_hw_reset,
3087 .enable_sdio_irq = sdhci_enable_sdio_irq,
3088 .ack_sdio_irq = sdhci_ack_sdio_irq,
3089 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
3090 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
3091 .execute_tuning = sdhci_execute_tuning,
3092 .card_event = sdhci_card_event,
3093 .card_busy = sdhci_card_busy,
3094};
3095
3096/*****************************************************************************\
3097 * *
3098 * Request done *
3099 * *
3100\*****************************************************************************/
3101
3102void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq)
3103{
3104 struct mmc_data *data = mrq->data;
3105
3106 if (data && data->host_cookie == COOKIE_MAPPED) {
3107 if (host->bounce_buffer) {
3108 /*
3109 * On reads, copy the bounced data into the
3110 * sglist
3111 */
3112 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3113 unsigned int length = data->bytes_xfered;
3114
3115 if (length > host->bounce_buffer_size) {
3116 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3117 mmc_hostname(host->mmc),
3118 host->bounce_buffer_size,
3119 data->bytes_xfered);
3120 /* Cap it down and continue */
3121 length = host->bounce_buffer_size;
3122 }
3123 dma_sync_single_for_cpu(mmc_dev(host->mmc),
3124 host->bounce_addr,
3125 host->bounce_buffer_size,
3126 DMA_FROM_DEVICE);
3127 sg_copy_from_buffer(data->sg,
3128 data->sg_len,
3129 host->bounce_buffer,
3130 length);
3131 } else {
3132 /* No copying, just switch ownership */
3133 dma_sync_single_for_cpu(mmc_dev(host->mmc),
3134 host->bounce_addr,
3135 host->bounce_buffer_size,
3136 mmc_get_dma_dir(data));
3137 }
3138 } else {
3139 /* Unmap the raw data */
3140 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3141 data->sg_len,
3142 mmc_get_dma_dir(data));
3143 }
3144 data->host_cookie = COOKIE_UNMAPPED;
3145 }
3146}
3147EXPORT_SYMBOL_GPL(sdhci_request_done_dma);
3148
3149static bool sdhci_request_done(struct sdhci_host *host)
3150{
3151 unsigned long flags;
3152 struct mmc_request *mrq;
3153 int i;
3154
3155 spin_lock_irqsave(&host->lock, flags);
3156
3157 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3158 mrq = host->mrqs_done[i];
3159 if (mrq)
3160 break;
3161 }
3162
3163 if (!mrq) {
3164 spin_unlock_irqrestore(&host->lock, flags);
3165 return true;
3166 }
3167
3168 /*
3169 * The controller needs a reset of internal state machines
3170 * upon error conditions.
3171 */
3172 if (sdhci_needs_reset(host, mrq)) {
3173 /*
3174 * Do not finish until command and data lines are available for
3175 * reset. Note there can only be one other mrq, so it cannot
3176 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3177 * would both be null.
3178 */
3179 if (host->cmd || host->data_cmd) {
3180 spin_unlock_irqrestore(&host->lock, flags);
3181 return true;
3182 }
3183
3184 /* Some controllers need this kick or reset won't work here */
3185 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3186 /* This is to force an update */
3187 host->ops->set_clock(host, host->clock);
3188
3189 sdhci_reset_for(host, REQUEST_ERROR);
3190
3191 host->pending_reset = false;
3192 }
3193
3194 /*
3195 * Always unmap the data buffers if they were mapped by
3196 * sdhci_prepare_data() whenever we finish with a request.
3197 * This avoids leaking DMA mappings on error.
3198 */
3199 if (host->flags & SDHCI_REQ_USE_DMA) {
3200 struct mmc_data *data = mrq->data;
3201
3202 if (host->use_external_dma && data &&
3203 (mrq->cmd->error || data->error)) {
3204 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3205
3206 host->mrqs_done[i] = NULL;
3207 spin_unlock_irqrestore(&host->lock, flags);
3208 dmaengine_terminate_sync(chan);
3209 spin_lock_irqsave(&host->lock, flags);
3210 sdhci_set_mrq_done(host, mrq);
3211 }
3212
3213 sdhci_request_done_dma(host, mrq);
3214 }
3215
3216 host->mrqs_done[i] = NULL;
3217
3218 spin_unlock_irqrestore(&host->lock, flags);
3219
3220 if (host->ops->request_done)
3221 host->ops->request_done(host, mrq);
3222 else
3223 mmc_request_done(host->mmc, mrq);
3224
3225 return false;
3226}
3227
3228void sdhci_complete_work(struct work_struct *work)
3229{
3230 struct sdhci_host *host = container_of(work, struct sdhci_host,
3231 complete_work);
3232
3233 while (!sdhci_request_done(host))
3234 ;
3235}
3236EXPORT_SYMBOL_GPL(sdhci_complete_work);
3237
3238static void sdhci_timeout_timer(struct timer_list *t)
3239{
3240 struct sdhci_host *host;
3241 unsigned long flags;
3242
3243 host = from_timer(host, t, timer);
3244
3245 spin_lock_irqsave(&host->lock, flags);
3246
3247 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3248 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3249 mmc_hostname(host->mmc));
3250 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3251 sdhci_dumpregs(host);
3252
3253 host->cmd->error = -ETIMEDOUT;
3254 sdhci_finish_mrq(host, host->cmd->mrq);
3255 }
3256
3257 spin_unlock_irqrestore(&host->lock, flags);
3258}
3259
3260static void sdhci_timeout_data_timer(struct timer_list *t)
3261{
3262 struct sdhci_host *host;
3263 unsigned long flags;
3264
3265 host = from_timer(host, t, data_timer);
3266
3267 spin_lock_irqsave(&host->lock, flags);
3268
3269 if (host->data || host->data_cmd ||
3270 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3271 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3272 mmc_hostname(host->mmc));
3273 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3274 sdhci_dumpregs(host);
3275
3276 if (host->data) {
3277 host->data->error = -ETIMEDOUT;
3278 __sdhci_finish_data(host, true);
3279 queue_work(host->complete_wq, &host->complete_work);
3280 } else if (host->data_cmd) {
3281 host->data_cmd->error = -ETIMEDOUT;
3282 sdhci_finish_mrq(host, host->data_cmd->mrq);
3283 } else {
3284 host->cmd->error = -ETIMEDOUT;
3285 sdhci_finish_mrq(host, host->cmd->mrq);
3286 }
3287 }
3288
3289 spin_unlock_irqrestore(&host->lock, flags);
3290}
3291
3292/*****************************************************************************\
3293 * *
3294 * Interrupt handling *
3295 * *
3296\*****************************************************************************/
3297
3298static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3299{
3300 /* Handle auto-CMD12 error */
3301 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3302 struct mmc_request *mrq = host->data_cmd->mrq;
3303 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3304 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3305 SDHCI_INT_DATA_TIMEOUT :
3306 SDHCI_INT_DATA_CRC;
3307
3308 /* Treat auto-CMD12 error the same as data error */
3309 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3310 *intmask_p |= data_err_bit;
3311 return;
3312 }
3313 }
3314
3315 if (!host->cmd) {
3316 /*
3317 * SDHCI recovers from errors by resetting the cmd and data
3318 * circuits. Until that is done, there very well might be more
3319 * interrupts, so ignore them in that case.
3320 */
3321 if (host->pending_reset)
3322 return;
3323 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3324 mmc_hostname(host->mmc), (unsigned)intmask);
3325 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3326 sdhci_dumpregs(host);
3327 return;
3328 }
3329
3330 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3331 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3332 if (intmask & SDHCI_INT_TIMEOUT) {
3333 host->cmd->error = -ETIMEDOUT;
3334 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3335 } else {
3336 host->cmd->error = -EILSEQ;
3337 if (!mmc_op_tuning(host->cmd->opcode))
3338 sdhci_err_stats_inc(host, CMD_CRC);
3339 }
3340 /* Treat data command CRC error the same as data CRC error */
3341 if (host->cmd->data &&
3342 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3343 SDHCI_INT_CRC) {
3344 host->cmd = NULL;
3345 *intmask_p |= SDHCI_INT_DATA_CRC;
3346 return;
3347 }
3348
3349 __sdhci_finish_mrq(host, host->cmd->mrq);
3350 return;
3351 }
3352
3353 /* Handle auto-CMD23 error */
3354 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3355 struct mmc_request *mrq = host->cmd->mrq;
3356 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3357 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3358 -ETIMEDOUT :
3359 -EILSEQ;
3360
3361 sdhci_err_stats_inc(host, AUTO_CMD);
3362
3363 if (sdhci_auto_cmd23(host, mrq)) {
3364 mrq->sbc->error = err;
3365 __sdhci_finish_mrq(host, mrq);
3366 return;
3367 }
3368 }
3369
3370 if (intmask & SDHCI_INT_RESPONSE)
3371 sdhci_finish_command(host);
3372}
3373
3374static void sdhci_adma_show_error(struct sdhci_host *host)
3375{
3376 void *desc = host->adma_table;
3377 dma_addr_t dma = host->adma_addr;
3378
3379 sdhci_dumpregs(host);
3380
3381 while (true) {
3382 struct sdhci_adma2_64_desc *dma_desc = desc;
3383
3384 if (host->flags & SDHCI_USE_64_BIT_DMA)
3385 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3386 (unsigned long long)dma,
3387 le32_to_cpu(dma_desc->addr_hi),
3388 le32_to_cpu(dma_desc->addr_lo),
3389 le16_to_cpu(dma_desc->len),
3390 le16_to_cpu(dma_desc->cmd));
3391 else
3392 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3393 (unsigned long long)dma,
3394 le32_to_cpu(dma_desc->addr_lo),
3395 le16_to_cpu(dma_desc->len),
3396 le16_to_cpu(dma_desc->cmd));
3397
3398 desc += host->desc_sz;
3399 dma += host->desc_sz;
3400
3401 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3402 break;
3403 }
3404}
3405
3406static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3407{
3408 /*
3409 * CMD19 generates _only_ Buffer Read Ready interrupt if
3410 * use sdhci_send_tuning.
3411 * Need to exclude this case: PIO mode and use mmc_send_tuning,
3412 * If not, sdhci_transfer_pio will never be called, make the
3413 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3414 */
3415 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3416 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
3417 host->tuning_done = 1;
3418 wake_up(&host->buf_ready_int);
3419 return;
3420 }
3421 }
3422
3423 if (!host->data) {
3424 struct mmc_command *data_cmd = host->data_cmd;
3425
3426 /*
3427 * The "data complete" interrupt is also used to
3428 * indicate that a busy state has ended. See comment
3429 * above in sdhci_cmd_irq().
3430 */
3431 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3432 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3433 host->data_cmd = NULL;
3434 data_cmd->error = -ETIMEDOUT;
3435 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3436 __sdhci_finish_mrq(host, data_cmd->mrq);
3437 return;
3438 }
3439 if (intmask & SDHCI_INT_DATA_END) {
3440 host->data_cmd = NULL;
3441 /*
3442 * Some cards handle busy-end interrupt
3443 * before the command completed, so make
3444 * sure we do things in the proper order.
3445 */
3446 if (host->cmd == data_cmd)
3447 return;
3448
3449 __sdhci_finish_mrq(host, data_cmd->mrq);
3450 return;
3451 }
3452 }
3453
3454 /*
3455 * SDHCI recovers from errors by resetting the cmd and data
3456 * circuits. Until that is done, there very well might be more
3457 * interrupts, so ignore them in that case.
3458 */
3459 if (host->pending_reset)
3460 return;
3461
3462 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3463 mmc_hostname(host->mmc), (unsigned)intmask);
3464 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3465 sdhci_dumpregs(host);
3466
3467 return;
3468 }
3469
3470 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3471 host->data->error = -ETIMEDOUT;
3472 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3473 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3474 host->data->error = -EILSEQ;
3475 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3476 sdhci_err_stats_inc(host, DAT_CRC);
3477 } else if ((intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) &&
3478 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3479 != MMC_BUS_TEST_R) {
3480 host->data->error = -EILSEQ;
3481 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3482 sdhci_err_stats_inc(host, DAT_CRC);
3483 if (intmask & SDHCI_INT_TUNING_ERROR) {
3484 u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
3485
3486 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
3487 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
3488 }
3489 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3490 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3491 intmask);
3492 sdhci_adma_show_error(host);
3493 sdhci_err_stats_inc(host, ADMA);
3494 host->data->error = -EIO;
3495 if (host->ops->adma_workaround)
3496 host->ops->adma_workaround(host, intmask);
3497 }
3498
3499 if (host->data->error)
3500 sdhci_finish_data(host);
3501 else {
3502 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3503 sdhci_transfer_pio(host);
3504
3505 /*
3506 * We currently don't do anything fancy with DMA
3507 * boundaries, but as we can't disable the feature
3508 * we need to at least restart the transfer.
3509 *
3510 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3511 * should return a valid address to continue from, but as
3512 * some controllers are faulty, don't trust them.
3513 */
3514 if (intmask & SDHCI_INT_DMA_END) {
3515 dma_addr_t dmastart, dmanow;
3516
3517 dmastart = sdhci_sdma_address(host);
3518 dmanow = dmastart + host->data->bytes_xfered;
3519 /*
3520 * Force update to the next DMA block boundary.
3521 */
3522 dmanow = (dmanow &
3523 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3524 SDHCI_DEFAULT_BOUNDARY_SIZE;
3525 host->data->bytes_xfered = dmanow - dmastart;
3526 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3527 &dmastart, host->data->bytes_xfered, &dmanow);
3528 sdhci_set_sdma_addr(host, dmanow);
3529 }
3530
3531 if (intmask & SDHCI_INT_DATA_END) {
3532 if (host->cmd == host->data_cmd) {
3533 /*
3534 * Data managed to finish before the
3535 * command completed. Make sure we do
3536 * things in the proper order.
3537 */
3538 host->data_early = 1;
3539 } else {
3540 sdhci_finish_data(host);
3541 }
3542 }
3543 }
3544}
3545
3546static inline bool sdhci_defer_done(struct sdhci_host *host,
3547 struct mmc_request *mrq)
3548{
3549 struct mmc_data *data = mrq->data;
3550
3551 return host->pending_reset || host->always_defer_done ||
3552 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3553 data->host_cookie == COOKIE_MAPPED);
3554}
3555
3556static irqreturn_t sdhci_irq(int irq, void *dev_id)
3557{
3558 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3559 irqreturn_t result = IRQ_NONE;
3560 struct sdhci_host *host = dev_id;
3561 u32 intmask, mask, unexpected = 0;
3562 int max_loops = 16;
3563 int i;
3564
3565 spin_lock(&host->lock);
3566
3567 if (host->runtime_suspended) {
3568 spin_unlock(&host->lock);
3569 return IRQ_NONE;
3570 }
3571
3572 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3573 if (!intmask || intmask == 0xffffffff) {
3574 result = IRQ_NONE;
3575 goto out;
3576 }
3577
3578 do {
3579 DBG("IRQ status 0x%08x\n", intmask);
3580
3581 if (host->ops->irq) {
3582 intmask = host->ops->irq(host, intmask);
3583 if (!intmask)
3584 goto cont;
3585 }
3586
3587 /* Clear selected interrupts. */
3588 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3589 SDHCI_INT_BUS_POWER);
3590 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3591
3592 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3593 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3594 SDHCI_CARD_PRESENT;
3595
3596 /*
3597 * There is a observation on i.mx esdhc. INSERT
3598 * bit will be immediately set again when it gets
3599 * cleared, if a card is inserted. We have to mask
3600 * the irq to prevent interrupt storm which will
3601 * freeze the system. And the REMOVE gets the
3602 * same situation.
3603 *
3604 * More testing are needed here to ensure it works
3605 * for other platforms though.
3606 */
3607 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3608 SDHCI_INT_CARD_REMOVE);
3609 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3610 SDHCI_INT_CARD_INSERT;
3611 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3612 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3613
3614 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3615 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3616
3617 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3618 SDHCI_INT_CARD_REMOVE);
3619 result = IRQ_WAKE_THREAD;
3620 }
3621
3622 if (intmask & SDHCI_INT_CMD_MASK)
3623 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3624
3625 if (intmask & SDHCI_INT_DATA_MASK)
3626 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3627
3628 if (intmask & SDHCI_INT_BUS_POWER)
3629 pr_err("%s: Card is consuming too much power!\n",
3630 mmc_hostname(host->mmc));
3631
3632 if (intmask & SDHCI_INT_RETUNE)
3633 mmc_retune_needed(host->mmc);
3634
3635 if ((intmask & SDHCI_INT_CARD_INT) &&
3636 (host->ier & SDHCI_INT_CARD_INT)) {
3637 sdhci_enable_sdio_irq_nolock(host, false);
3638 sdio_signal_irq(host->mmc);
3639 }
3640
3641 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3642 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3643 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3644 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3645
3646 if (intmask) {
3647 unexpected |= intmask;
3648 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3649 }
3650cont:
3651 if (result == IRQ_NONE)
3652 result = IRQ_HANDLED;
3653
3654 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3655 } while (intmask && --max_loops);
3656
3657 /* Determine if mrqs can be completed immediately */
3658 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3659 struct mmc_request *mrq = host->mrqs_done[i];
3660
3661 if (!mrq)
3662 continue;
3663
3664 if (sdhci_defer_done(host, mrq)) {
3665 result = IRQ_WAKE_THREAD;
3666 } else {
3667 mrqs_done[i] = mrq;
3668 host->mrqs_done[i] = NULL;
3669 }
3670 }
3671out:
3672 if (host->deferred_cmd)
3673 result = IRQ_WAKE_THREAD;
3674
3675 spin_unlock(&host->lock);
3676
3677 /* Process mrqs ready for immediate completion */
3678 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3679 if (!mrqs_done[i])
3680 continue;
3681
3682 if (host->ops->request_done)
3683 host->ops->request_done(host, mrqs_done[i]);
3684 else
3685 mmc_request_done(host->mmc, mrqs_done[i]);
3686 }
3687
3688 if (unexpected) {
3689 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3690 mmc_hostname(host->mmc), unexpected);
3691 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3692 sdhci_dumpregs(host);
3693 }
3694
3695 return result;
3696}
3697
3698irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3699{
3700 struct sdhci_host *host = dev_id;
3701 struct mmc_command *cmd;
3702 unsigned long flags;
3703 u32 isr;
3704
3705 while (!sdhci_request_done(host))
3706 ;
3707
3708 spin_lock_irqsave(&host->lock, flags);
3709
3710 isr = host->thread_isr;
3711 host->thread_isr = 0;
3712
3713 cmd = host->deferred_cmd;
3714 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3715 sdhci_finish_mrq(host, cmd->mrq);
3716
3717 spin_unlock_irqrestore(&host->lock, flags);
3718
3719 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3720 struct mmc_host *mmc = host->mmc;
3721
3722 mmc->ops->card_event(mmc);
3723 mmc_detect_change(mmc, msecs_to_jiffies(200));
3724 }
3725
3726 return IRQ_HANDLED;
3727}
3728EXPORT_SYMBOL_GPL(sdhci_thread_irq);
3729
3730/*****************************************************************************\
3731 * *
3732 * Suspend/resume *
3733 * *
3734\*****************************************************************************/
3735
3736#ifdef CONFIG_PM
3737
3738static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3739{
3740 return mmc_card_is_removable(host->mmc) &&
3741 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3742 !mmc_can_gpio_cd(host->mmc);
3743}
3744
3745/*
3746 * To enable wakeup events, the corresponding events have to be enabled in
3747 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3748 * Table' in the SD Host Controller Standard Specification.
3749 * It is useless to restore SDHCI_INT_ENABLE state in
3750 * sdhci_disable_irq_wakeups() since it will be set by
3751 * sdhci_enable_card_detection() or sdhci_init().
3752 */
3753static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3754{
3755 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3756 SDHCI_WAKE_ON_INT;
3757 u32 irq_val = 0;
3758 u8 wake_val = 0;
3759 u8 val;
3760
3761 if (sdhci_cd_irq_can_wakeup(host)) {
3762 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3763 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3764 }
3765
3766 if (mmc_card_wake_sdio_irq(host->mmc)) {
3767 wake_val |= SDHCI_WAKE_ON_INT;
3768 irq_val |= SDHCI_INT_CARD_INT;
3769 }
3770
3771 if (!irq_val)
3772 return false;
3773
3774 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3775 val &= ~mask;
3776 val |= wake_val;
3777 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3778
3779 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3780
3781 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3782
3783 return host->irq_wake_enabled;
3784}
3785
3786static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3787{
3788 u8 val;
3789 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3790 | SDHCI_WAKE_ON_INT;
3791
3792 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3793 val &= ~mask;
3794 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3795
3796 disable_irq_wake(host->irq);
3797
3798 host->irq_wake_enabled = false;
3799}
3800
3801int sdhci_suspend_host(struct sdhci_host *host)
3802{
3803 sdhci_disable_card_detection(host);
3804
3805 mmc_retune_timer_stop(host->mmc);
3806
3807 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3808 !sdhci_enable_irq_wakeups(host)) {
3809 host->ier = 0;
3810 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3811 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3812 free_irq(host->irq, host);
3813 }
3814
3815 return 0;
3816}
3817
3818EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3819
3820int sdhci_resume_host(struct sdhci_host *host)
3821{
3822 struct mmc_host *mmc = host->mmc;
3823 int ret = 0;
3824
3825 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3826 if (host->ops->enable_dma)
3827 host->ops->enable_dma(host);
3828 }
3829
3830 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3831 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3832 /* Card keeps power but host controller does not */
3833 sdhci_init(host, 0);
3834 host->pwr = 0;
3835 host->clock = 0;
3836 host->reinit_uhs = true;
3837 mmc->ops->set_ios(mmc, &mmc->ios);
3838 } else {
3839 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3840 }
3841
3842 if (host->irq_wake_enabled) {
3843 sdhci_disable_irq_wakeups(host);
3844 } else {
3845 ret = request_threaded_irq(host->irq, sdhci_irq,
3846 sdhci_thread_irq, IRQF_SHARED,
3847 mmc_hostname(mmc), host);
3848 if (ret)
3849 return ret;
3850 }
3851
3852 sdhci_enable_card_detection(host);
3853
3854 return ret;
3855}
3856
3857EXPORT_SYMBOL_GPL(sdhci_resume_host);
3858
3859int sdhci_runtime_suspend_host(struct sdhci_host *host)
3860{
3861 unsigned long flags;
3862
3863 mmc_retune_timer_stop(host->mmc);
3864
3865 spin_lock_irqsave(&host->lock, flags);
3866 host->ier &= SDHCI_INT_CARD_INT;
3867 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3868 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3869 spin_unlock_irqrestore(&host->lock, flags);
3870
3871 synchronize_hardirq(host->irq);
3872
3873 spin_lock_irqsave(&host->lock, flags);
3874 host->runtime_suspended = true;
3875 spin_unlock_irqrestore(&host->lock, flags);
3876
3877 return 0;
3878}
3879EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3880
3881int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3882{
3883 struct mmc_host *mmc = host->mmc;
3884 unsigned long flags;
3885 int host_flags = host->flags;
3886
3887 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3888 if (host->ops->enable_dma)
3889 host->ops->enable_dma(host);
3890 }
3891
3892 sdhci_init(host, soft_reset);
3893
3894 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3895 mmc->ios.power_mode != MMC_POWER_OFF) {
3896 /* Force clock and power re-program */
3897 host->pwr = 0;
3898 host->clock = 0;
3899 host->reinit_uhs = true;
3900 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3901 mmc->ops->set_ios(mmc, &mmc->ios);
3902
3903 if ((host_flags & SDHCI_PV_ENABLED) &&
3904 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3905 spin_lock_irqsave(&host->lock, flags);
3906 sdhci_enable_preset_value(host, true);
3907 spin_unlock_irqrestore(&host->lock, flags);
3908 }
3909
3910 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3911 mmc->ops->hs400_enhanced_strobe)
3912 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3913 }
3914
3915 spin_lock_irqsave(&host->lock, flags);
3916
3917 host->runtime_suspended = false;
3918
3919 /* Enable SDIO IRQ */
3920 if (sdio_irq_claimed(mmc))
3921 sdhci_enable_sdio_irq_nolock(host, true);
3922
3923 /* Enable Card Detection */
3924 sdhci_enable_card_detection(host);
3925
3926 spin_unlock_irqrestore(&host->lock, flags);
3927
3928 return 0;
3929}
3930EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3931
3932#endif /* CONFIG_PM */
3933
3934/*****************************************************************************\
3935 * *
3936 * Command Queue Engine (CQE) helpers *
3937 * *
3938\*****************************************************************************/
3939
3940void sdhci_cqe_enable(struct mmc_host *mmc)
3941{
3942 struct sdhci_host *host = mmc_priv(mmc);
3943 unsigned long flags;
3944 u8 ctrl;
3945
3946 spin_lock_irqsave(&host->lock, flags);
3947
3948 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3949 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3950 /*
3951 * Host from V4.10 supports ADMA3 DMA type.
3952 * ADMA3 performs integrated descriptor which is more suitable
3953 * for cmd queuing to fetch both command and transfer descriptors.
3954 */
3955 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3956 ctrl |= SDHCI_CTRL_ADMA3;
3957 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3958 ctrl |= SDHCI_CTRL_ADMA64;
3959 else
3960 ctrl |= SDHCI_CTRL_ADMA32;
3961 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3962
3963 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3964 SDHCI_BLOCK_SIZE);
3965
3966 /* Set maximum timeout */
3967 sdhci_set_timeout(host, NULL);
3968
3969 host->ier = host->cqe_ier;
3970
3971 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3972 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3973
3974 host->cqe_on = true;
3975
3976 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3977 mmc_hostname(mmc), host->ier,
3978 sdhci_readl(host, SDHCI_INT_STATUS));
3979
3980 spin_unlock_irqrestore(&host->lock, flags);
3981}
3982EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3983
3984void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3985{
3986 struct sdhci_host *host = mmc_priv(mmc);
3987 unsigned long flags;
3988
3989 spin_lock_irqsave(&host->lock, flags);
3990
3991 sdhci_set_default_irqs(host);
3992
3993 host->cqe_on = false;
3994
3995 if (recovery)
3996 sdhci_reset_for(host, CQE_RECOVERY);
3997
3998 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3999 mmc_hostname(mmc), host->ier,
4000 sdhci_readl(host, SDHCI_INT_STATUS));
4001
4002 spin_unlock_irqrestore(&host->lock, flags);
4003}
4004EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
4005
4006bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
4007 int *data_error)
4008{
4009 u32 mask;
4010
4011 if (!host->cqe_on)
4012 return false;
4013
4014 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
4015 *cmd_error = -EILSEQ;
4016 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
4017 sdhci_err_stats_inc(host, CMD_CRC);
4018 } else if (intmask & SDHCI_INT_TIMEOUT) {
4019 *cmd_error = -ETIMEDOUT;
4020 sdhci_err_stats_inc(host, CMD_TIMEOUT);
4021 } else
4022 *cmd_error = 0;
4023
4024 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) {
4025 *data_error = -EILSEQ;
4026 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
4027 sdhci_err_stats_inc(host, DAT_CRC);
4028 } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
4029 *data_error = -ETIMEDOUT;
4030 sdhci_err_stats_inc(host, DAT_TIMEOUT);
4031 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
4032 *data_error = -EIO;
4033 sdhci_err_stats_inc(host, ADMA);
4034 } else
4035 *data_error = 0;
4036
4037 /* Clear selected interrupts. */
4038 mask = intmask & host->cqe_ier;
4039 sdhci_writel(host, mask, SDHCI_INT_STATUS);
4040
4041 if (intmask & SDHCI_INT_BUS_POWER)
4042 pr_err("%s: Card is consuming too much power!\n",
4043 mmc_hostname(host->mmc));
4044
4045 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4046 if (intmask) {
4047 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4048 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
4049 mmc_hostname(host->mmc), intmask);
4050 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
4051 sdhci_dumpregs(host);
4052 }
4053
4054 return true;
4055}
4056EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
4057
4058/*****************************************************************************\
4059 * *
4060 * Device allocation/registration *
4061 * *
4062\*****************************************************************************/
4063
4064struct sdhci_host *sdhci_alloc_host(struct device *dev,
4065 size_t priv_size)
4066{
4067 struct mmc_host *mmc;
4068 struct sdhci_host *host;
4069
4070 WARN_ON(dev == NULL);
4071
4072 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
4073 if (!mmc)
4074 return ERR_PTR(-ENOMEM);
4075
4076 host = mmc_priv(mmc);
4077 host->mmc = mmc;
4078 host->mmc_host_ops = sdhci_ops;
4079 mmc->ops = &host->mmc_host_ops;
4080
4081 host->flags = SDHCI_SIGNALING_330;
4082
4083 host->cqe_ier = SDHCI_CQE_INT_MASK;
4084 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4085
4086 host->tuning_delay = -1;
4087 host->tuning_loop_count = MAX_TUNING_LOOP;
4088
4089 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4090
4091 /*
4092 * The DMA table descriptor count is calculated as the maximum
4093 * number of segments times 2, to allow for an alignment
4094 * descriptor for each segment, plus 1 for a nop end descriptor.
4095 */
4096 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4097 host->max_adma = 65536;
4098
4099 host->max_timeout_count = 0xE;
4100
4101 host->complete_work_fn = sdhci_complete_work;
4102 host->thread_irq_fn = sdhci_thread_irq;
4103
4104 return host;
4105}
4106
4107EXPORT_SYMBOL_GPL(sdhci_alloc_host);
4108
4109static int sdhci_set_dma_mask(struct sdhci_host *host)
4110{
4111 struct mmc_host *mmc = host->mmc;
4112 struct device *dev = mmc_dev(mmc);
4113 int ret = -EINVAL;
4114
4115 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4116 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4117
4118 /* Try 64-bit mask if hardware is capable of it */
4119 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4120 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4121 if (ret) {
4122 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
4123 mmc_hostname(mmc));
4124 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4125 }
4126 }
4127
4128 /* 32-bit mask as default & fallback */
4129 if (ret) {
4130 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
4131 if (ret)
4132 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4133 mmc_hostname(mmc));
4134 }
4135
4136 return ret;
4137}
4138
4139void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4140 const u32 *caps, const u32 *caps1)
4141{
4142 u16 v;
4143 u64 dt_caps_mask = 0;
4144 u64 dt_caps = 0;
4145
4146 if (host->read_caps)
4147 return;
4148
4149 host->read_caps = true;
4150
4151 if (debug_quirks)
4152 host->quirks = debug_quirks;
4153
4154 if (debug_quirks2)
4155 host->quirks2 = debug_quirks2;
4156
4157 sdhci_reset_for_all(host);
4158
4159 if (host->v4_mode)
4160 sdhci_do_enable_v4_mode(host);
4161
4162 device_property_read_u64(mmc_dev(host->mmc),
4163 "sdhci-caps-mask", &dt_caps_mask);
4164 device_property_read_u64(mmc_dev(host->mmc),
4165 "sdhci-caps", &dt_caps);
4166
4167 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4168 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4169
4170 if (caps) {
4171 host->caps = *caps;
4172 } else {
4173 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4174 host->caps &= ~lower_32_bits(dt_caps_mask);
4175 host->caps |= lower_32_bits(dt_caps);
4176 }
4177
4178 if (host->version < SDHCI_SPEC_300)
4179 return;
4180
4181 if (caps1) {
4182 host->caps1 = *caps1;
4183 } else {
4184 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4185 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4186 host->caps1 |= upper_32_bits(dt_caps);
4187 }
4188}
4189EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4190
4191static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4192{
4193 struct mmc_host *mmc = host->mmc;
4194 unsigned int max_blocks;
4195 unsigned int bounce_size;
4196 int ret;
4197
4198 /*
4199 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4200 * has diminishing returns, this is probably because SD/MMC
4201 * cards are usually optimized to handle this size of requests.
4202 */
4203 bounce_size = SZ_64K;
4204 /*
4205 * Adjust downwards to maximum request size if this is less
4206 * than our segment size, else hammer down the maximum
4207 * request size to the maximum buffer size.
4208 */
4209 if (mmc->max_req_size < bounce_size)
4210 bounce_size = mmc->max_req_size;
4211 max_blocks = bounce_size / 512;
4212
4213 /*
4214 * When we just support one segment, we can get significant
4215 * speedups by the help of a bounce buffer to group scattered
4216 * reads/writes together.
4217 */
4218 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4219 bounce_size,
4220 GFP_KERNEL);
4221 if (!host->bounce_buffer) {
4222 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4223 mmc_hostname(mmc),
4224 bounce_size);
4225 /*
4226 * Exiting with zero here makes sure we proceed with
4227 * mmc->max_segs == 1.
4228 */
4229 return;
4230 }
4231
4232 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4233 host->bounce_buffer,
4234 bounce_size,
4235 DMA_BIDIRECTIONAL);
4236 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4237 if (ret) {
4238 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4239 host->bounce_buffer = NULL;
4240 /* Again fall back to max_segs == 1 */
4241 return;
4242 }
4243
4244 host->bounce_buffer_size = bounce_size;
4245
4246 /* Lie about this since we're bouncing */
4247 mmc->max_segs = max_blocks;
4248 mmc->max_seg_size = bounce_size;
4249 mmc->max_req_size = bounce_size;
4250
4251 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4252 mmc_hostname(mmc), max_blocks, bounce_size);
4253}
4254
4255static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4256{
4257 /*
4258 * According to SD Host Controller spec v4.10, bit[27] added from
4259 * version 4.10 in Capabilities Register is used as 64-bit System
4260 * Address support for V4 mode.
4261 */
4262 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4263 return host->caps & SDHCI_CAN_64BIT_V4;
4264
4265 return host->caps & SDHCI_CAN_64BIT;
4266}
4267
4268int sdhci_setup_host(struct sdhci_host *host)
4269{
4270 struct mmc_host *mmc;
4271 u32 max_current_caps;
4272 unsigned int ocr_avail;
4273 unsigned int override_timeout_clk;
4274 u32 max_clk;
4275 int ret = 0;
4276 bool enable_vqmmc = false;
4277
4278 WARN_ON(host == NULL);
4279 if (host == NULL)
4280 return -EINVAL;
4281
4282 mmc = host->mmc;
4283
4284 /*
4285 * If there are external regulators, get them. Note this must be done
4286 * early before resetting the host and reading the capabilities so that
4287 * the host can take the appropriate action if regulators are not
4288 * available.
4289 */
4290 if (!mmc->supply.vqmmc) {
4291 ret = mmc_regulator_get_supply(mmc);
4292 if (ret)
4293 return ret;
4294 enable_vqmmc = true;
4295 }
4296
4297 DBG("Version: 0x%08x | Present: 0x%08x\n",
4298 sdhci_readw(host, SDHCI_HOST_VERSION),
4299 sdhci_readl(host, SDHCI_PRESENT_STATE));
4300 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4301 sdhci_readl(host, SDHCI_CAPABILITIES),
4302 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4303
4304 sdhci_read_caps(host);
4305
4306 override_timeout_clk = host->timeout_clk;
4307
4308 if (host->version > SDHCI_SPEC_420) {
4309 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4310 mmc_hostname(mmc), host->version);
4311 }
4312
4313 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4314 host->flags |= SDHCI_USE_SDMA;
4315 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4316 DBG("Controller doesn't have SDMA capability\n");
4317 else
4318 host->flags |= SDHCI_USE_SDMA;
4319
4320 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4321 (host->flags & SDHCI_USE_SDMA)) {
4322 DBG("Disabling DMA as it is marked broken\n");
4323 host->flags &= ~SDHCI_USE_SDMA;
4324 }
4325
4326 if ((host->version >= SDHCI_SPEC_200) &&
4327 (host->caps & SDHCI_CAN_DO_ADMA2))
4328 host->flags |= SDHCI_USE_ADMA;
4329
4330 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4331 (host->flags & SDHCI_USE_ADMA)) {
4332 DBG("Disabling ADMA as it is marked broken\n");
4333 host->flags &= ~SDHCI_USE_ADMA;
4334 }
4335
4336 if (sdhci_can_64bit_dma(host))
4337 host->flags |= SDHCI_USE_64_BIT_DMA;
4338
4339 if (host->use_external_dma) {
4340 ret = sdhci_external_dma_init(host);
4341 if (ret == -EPROBE_DEFER)
4342 goto unreg;
4343 /*
4344 * Fall back to use the DMA/PIO integrated in standard SDHCI
4345 * instead of external DMA devices.
4346 */
4347 else if (ret)
4348 sdhci_switch_external_dma(host, false);
4349 /* Disable internal DMA sources */
4350 else
4351 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4352 }
4353
4354 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4355 if (host->ops->set_dma_mask)
4356 ret = host->ops->set_dma_mask(host);
4357 else
4358 ret = sdhci_set_dma_mask(host);
4359
4360 if (!ret && host->ops->enable_dma)
4361 ret = host->ops->enable_dma(host);
4362
4363 if (ret) {
4364 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4365 mmc_hostname(mmc));
4366 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4367
4368 ret = 0;
4369 }
4370 }
4371
4372 /* SDMA does not support 64-bit DMA if v4 mode not set */
4373 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4374 host->flags &= ~SDHCI_USE_SDMA;
4375
4376 if (host->flags & SDHCI_USE_ADMA) {
4377 dma_addr_t dma;
4378 void *buf;
4379
4380 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4381 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4382 else if (!host->alloc_desc_sz)
4383 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4384
4385 host->desc_sz = host->alloc_desc_sz;
4386 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4387
4388 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4389 /*
4390 * Use zalloc to zero the reserved high 32-bits of 128-bit
4391 * descriptors so that they never need to be written.
4392 */
4393 buf = dma_alloc_coherent(mmc_dev(mmc),
4394 host->align_buffer_sz + host->adma_table_sz,
4395 &dma, GFP_KERNEL);
4396 if (!buf) {
4397 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4398 mmc_hostname(mmc));
4399 host->flags &= ~SDHCI_USE_ADMA;
4400 } else if ((dma + host->align_buffer_sz) &
4401 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4402 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4403 mmc_hostname(mmc));
4404 host->flags &= ~SDHCI_USE_ADMA;
4405 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4406 host->adma_table_sz, buf, dma);
4407 } else {
4408 host->align_buffer = buf;
4409 host->align_addr = dma;
4410
4411 host->adma_table = buf + host->align_buffer_sz;
4412 host->adma_addr = dma + host->align_buffer_sz;
4413 }
4414 }
4415
4416 /*
4417 * If we use DMA, then it's up to the caller to set the DMA
4418 * mask, but PIO does not need the hw shim so we set a new
4419 * mask here in that case.
4420 */
4421 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4422 host->dma_mask = DMA_BIT_MASK(64);
4423 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4424 }
4425
4426 if (host->version >= SDHCI_SPEC_300)
4427 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4428 else
4429 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4430
4431 host->max_clk *= 1000000;
4432 if (host->max_clk == 0 || host->quirks &
4433 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4434 if (!host->ops->get_max_clock) {
4435 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4436 mmc_hostname(mmc));
4437 ret = -ENODEV;
4438 goto undma;
4439 }
4440 host->max_clk = host->ops->get_max_clock(host);
4441 }
4442
4443 /*
4444 * In case of Host Controller v3.00, find out whether clock
4445 * multiplier is supported.
4446 */
4447 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4448
4449 /*
4450 * In case the value in Clock Multiplier is 0, then programmable
4451 * clock mode is not supported, otherwise the actual clock
4452 * multiplier is one more than the value of Clock Multiplier
4453 * in the Capabilities Register.
4454 */
4455 if (host->clk_mul)
4456 host->clk_mul += 1;
4457
4458 /*
4459 * Set host parameters.
4460 */
4461 max_clk = host->max_clk;
4462
4463 if (host->ops->get_min_clock)
4464 mmc->f_min = host->ops->get_min_clock(host);
4465 else if (host->version >= SDHCI_SPEC_300) {
4466 if (host->clk_mul)
4467 max_clk = host->max_clk * host->clk_mul;
4468 /*
4469 * Divided Clock Mode minimum clock rate is always less than
4470 * Programmable Clock Mode minimum clock rate.
4471 */
4472 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4473 } else
4474 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4475
4476 if (!mmc->f_max || mmc->f_max > max_clk)
4477 mmc->f_max = max_clk;
4478
4479 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4480 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4481
4482 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4483 host->timeout_clk *= 1000;
4484
4485 if (host->timeout_clk == 0) {
4486 if (!host->ops->get_timeout_clock) {
4487 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4488 mmc_hostname(mmc));
4489 ret = -ENODEV;
4490 goto undma;
4491 }
4492
4493 host->timeout_clk =
4494 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4495 1000);
4496 }
4497
4498 if (override_timeout_clk)
4499 host->timeout_clk = override_timeout_clk;
4500
4501 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4502 host->ops->get_max_timeout_count(host) : 1 << 27;
4503 mmc->max_busy_timeout /= host->timeout_clk;
4504 }
4505
4506 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4507 !host->ops->get_max_timeout_count)
4508 mmc->max_busy_timeout = 0;
4509
4510 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4511 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4512
4513 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4514 host->flags |= SDHCI_AUTO_CMD12;
4515
4516 /*
4517 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4518 * For v4 mode, SDMA may use Auto-CMD23 as well.
4519 */
4520 if ((host->version >= SDHCI_SPEC_300) &&
4521 ((host->flags & SDHCI_USE_ADMA) ||
4522 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4523 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4524 host->flags |= SDHCI_AUTO_CMD23;
4525 DBG("Auto-CMD23 available\n");
4526 } else {
4527 DBG("Auto-CMD23 unavailable\n");
4528 }
4529
4530 /*
4531 * A controller may support 8-bit width, but the board itself
4532 * might not have the pins brought out. Boards that support
4533 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4534 * their platform code before calling sdhci_add_host(), and we
4535 * won't assume 8-bit width for hosts without that CAP.
4536 */
4537 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4538 mmc->caps |= MMC_CAP_4_BIT_DATA;
4539
4540 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4541 mmc->caps &= ~MMC_CAP_CMD23;
4542
4543 if (host->caps & SDHCI_CAN_DO_HISPD)
4544 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4545
4546 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4547 mmc_card_is_removable(mmc) &&
4548 mmc_gpio_get_cd(mmc) < 0)
4549 mmc->caps |= MMC_CAP_NEEDS_POLL;
4550
4551 if (!IS_ERR(mmc->supply.vqmmc)) {
4552 if (enable_vqmmc) {
4553 ret = regulator_enable(mmc->supply.vqmmc);
4554 host->sdhci_core_to_disable_vqmmc = !ret;
4555 }
4556
4557 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4558 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4559 1950000))
4560 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4561 SDHCI_SUPPORT_SDR50 |
4562 SDHCI_SUPPORT_DDR50);
4563
4564 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4565 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4566 3600000))
4567 host->flags &= ~SDHCI_SIGNALING_330;
4568
4569 if (ret) {
4570 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4571 mmc_hostname(mmc), ret);
4572 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4573 }
4574
4575 }
4576
4577 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4578 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4579 SDHCI_SUPPORT_DDR50);
4580 /*
4581 * The SDHCI controller in a SoC might support HS200/HS400
4582 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4583 * but if the board is modeled such that the IO lines are not
4584 * connected to 1.8v then HS200/HS400 cannot be supported.
4585 * Disable HS200/HS400 if the board does not have 1.8v connected
4586 * to the IO lines. (Applicable for other modes in 1.8v)
4587 */
4588 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4589 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4590 }
4591
4592 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4593 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4594 SDHCI_SUPPORT_DDR50))
4595 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4596
4597 /* SDR104 supports also implies SDR50 support */
4598 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4599 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4600 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4601 * field can be promoted to support HS200.
4602 */
4603 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4604 mmc->caps2 |= MMC_CAP2_HS200;
4605 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4606 mmc->caps |= MMC_CAP_UHS_SDR50;
4607 }
4608
4609 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4610 (host->caps1 & SDHCI_SUPPORT_HS400))
4611 mmc->caps2 |= MMC_CAP2_HS400;
4612
4613 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4614 (IS_ERR(mmc->supply.vqmmc) ||
4615 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4616 1300000)))
4617 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4618
4619 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4620 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4621 mmc->caps |= MMC_CAP_UHS_DDR50;
4622
4623 /* Does the host need tuning for SDR50? */
4624 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4625 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4626
4627 /* Driver Type(s) (A, C, D) supported by the host */
4628 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4629 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4630 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4631 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4632 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4633 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4634
4635 /* Initial value for re-tuning timer count */
4636 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4637 host->caps1);
4638
4639 /*
4640 * In case Re-tuning Timer is not disabled, the actual value of
4641 * re-tuning timer will be 2 ^ (n - 1).
4642 */
4643 if (host->tuning_count)
4644 host->tuning_count = 1 << (host->tuning_count - 1);
4645
4646 /* Re-tuning mode supported by the Host Controller */
4647 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4648
4649 ocr_avail = 0;
4650
4651 /*
4652 * According to SD Host Controller spec v3.00, if the Host System
4653 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4654 * the value is meaningful only if Voltage Support in the Capabilities
4655 * register is set. The actual current value is 4 times the register
4656 * value.
4657 */
4658 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4659 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4660 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4661 if (curr > 0) {
4662
4663 /* convert to SDHCI_MAX_CURRENT format */
4664 curr = curr/1000; /* convert to mA */
4665 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4666
4667 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4668 max_current_caps =
4669 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4670 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4671 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4672 }
4673 }
4674
4675 if (host->caps & SDHCI_CAN_VDD_330) {
4676 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4677
4678 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4679 max_current_caps) *
4680 SDHCI_MAX_CURRENT_MULTIPLIER;
4681 }
4682 if (host->caps & SDHCI_CAN_VDD_300) {
4683 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4684
4685 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4686 max_current_caps) *
4687 SDHCI_MAX_CURRENT_MULTIPLIER;
4688 }
4689 if (host->caps & SDHCI_CAN_VDD_180) {
4690 ocr_avail |= MMC_VDD_165_195;
4691
4692 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4693 max_current_caps) *
4694 SDHCI_MAX_CURRENT_MULTIPLIER;
4695 }
4696
4697 /* If OCR set by host, use it instead. */
4698 if (host->ocr_mask)
4699 ocr_avail = host->ocr_mask;
4700
4701 /* If OCR set by external regulators, give it highest prio. */
4702 if (mmc->ocr_avail)
4703 ocr_avail = mmc->ocr_avail;
4704
4705 mmc->ocr_avail = ocr_avail;
4706 mmc->ocr_avail_sdio = ocr_avail;
4707 if (host->ocr_avail_sdio)
4708 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4709 mmc->ocr_avail_sd = ocr_avail;
4710 if (host->ocr_avail_sd)
4711 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4712 else /* normal SD controllers don't support 1.8V */
4713 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4714 mmc->ocr_avail_mmc = ocr_avail;
4715 if (host->ocr_avail_mmc)
4716 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4717
4718 if (mmc->ocr_avail == 0) {
4719 pr_err("%s: Hardware doesn't report any support voltages.\n",
4720 mmc_hostname(mmc));
4721 ret = -ENODEV;
4722 goto unreg;
4723 }
4724
4725 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4726 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4727 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4728 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4729 host->flags |= SDHCI_SIGNALING_180;
4730
4731 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4732 host->flags |= SDHCI_SIGNALING_120;
4733
4734 spin_lock_init(&host->lock);
4735
4736 /*
4737 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4738 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4739 * is less anyway.
4740 */
4741 mmc->max_req_size = 524288;
4742
4743 /*
4744 * Maximum number of segments. Depends on if the hardware
4745 * can do scatter/gather or not.
4746 */
4747 if (host->flags & SDHCI_USE_ADMA) {
4748 mmc->max_segs = SDHCI_MAX_SEGS;
4749 } else if (host->flags & SDHCI_USE_SDMA) {
4750 mmc->max_segs = 1;
4751 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4752 dma_max_mapping_size(mmc_dev(mmc)));
4753 } else { /* PIO */
4754 mmc->max_segs = SDHCI_MAX_SEGS;
4755 }
4756
4757 /*
4758 * Maximum segment size. Could be one segment with the maximum number
4759 * of bytes. When doing hardware scatter/gather, each entry cannot
4760 * be larger than 64 KiB though.
4761 */
4762 if (host->flags & SDHCI_USE_ADMA) {
4763 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4764 host->max_adma = 65532; /* 32-bit alignment */
4765 mmc->max_seg_size = 65535;
4766 /*
4767 * sdhci_adma_table_pre() expects to define 1 DMA
4768 * descriptor per segment, so the maximum segment size
4769 * is set accordingly. SDHCI allows up to 64KiB per DMA
4770 * descriptor (16-bit field), but some controllers do
4771 * not support "zero means 65536" reducing the maximum
4772 * for them to 65535. That is a problem if PAGE_SIZE is
4773 * 64KiB because the block layer does not support
4774 * max_seg_size < PAGE_SIZE, however
4775 * sdhci_adma_table_pre() has a workaround to handle
4776 * that case, and split the descriptor. Refer also
4777 * comment in sdhci_adma_table_pre().
4778 */
4779 if (mmc->max_seg_size < PAGE_SIZE)
4780 mmc->max_seg_size = PAGE_SIZE;
4781 } else {
4782 mmc->max_seg_size = 65536;
4783 }
4784 } else {
4785 mmc->max_seg_size = mmc->max_req_size;
4786 }
4787
4788 /*
4789 * Maximum block size. This varies from controller to controller and
4790 * is specified in the capabilities register.
4791 */
4792 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4793 mmc->max_blk_size = 2;
4794 } else {
4795 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4796 SDHCI_MAX_BLOCK_SHIFT;
4797 if (mmc->max_blk_size >= 3) {
4798 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4799 mmc_hostname(mmc));
4800 mmc->max_blk_size = 0;
4801 }
4802 }
4803
4804 mmc->max_blk_size = 512 << mmc->max_blk_size;
4805
4806 /*
4807 * Maximum block count.
4808 */
4809 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4810
4811 if (mmc->max_segs == 1)
4812 /* This may alter mmc->*_blk_* parameters */
4813 sdhci_allocate_bounce_buffer(host);
4814
4815 return 0;
4816
4817unreg:
4818 if (host->sdhci_core_to_disable_vqmmc)
4819 regulator_disable(mmc->supply.vqmmc);
4820undma:
4821 if (host->align_buffer)
4822 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4823 host->adma_table_sz, host->align_buffer,
4824 host->align_addr);
4825 host->adma_table = NULL;
4826 host->align_buffer = NULL;
4827
4828 return ret;
4829}
4830EXPORT_SYMBOL_GPL(sdhci_setup_host);
4831
4832void sdhci_cleanup_host(struct sdhci_host *host)
4833{
4834 struct mmc_host *mmc = host->mmc;
4835
4836 if (host->sdhci_core_to_disable_vqmmc)
4837 regulator_disable(mmc->supply.vqmmc);
4838
4839 if (host->align_buffer)
4840 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4841 host->adma_table_sz, host->align_buffer,
4842 host->align_addr);
4843
4844 if (host->use_external_dma)
4845 sdhci_external_dma_release(host);
4846
4847 host->adma_table = NULL;
4848 host->align_buffer = NULL;
4849}
4850EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4851
4852int __sdhci_add_host(struct sdhci_host *host)
4853{
4854 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4855 struct mmc_host *mmc = host->mmc;
4856 int ret;
4857
4858 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4859 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4860 mmc->caps2 &= ~MMC_CAP2_CQE;
4861 mmc->cqe_ops = NULL;
4862 }
4863
4864 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4865 if (!host->complete_wq)
4866 return -ENOMEM;
4867
4868 INIT_WORK(&host->complete_work, host->complete_work_fn);
4869
4870 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4871 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4872
4873 init_waitqueue_head(&host->buf_ready_int);
4874
4875 sdhci_init(host, 0);
4876
4877 ret = request_threaded_irq(host->irq, sdhci_irq, host->thread_irq_fn,
4878 IRQF_SHARED, mmc_hostname(mmc), host);
4879 if (ret) {
4880 pr_err("%s: Failed to request IRQ %d: %d\n",
4881 mmc_hostname(mmc), host->irq, ret);
4882 goto unwq;
4883 }
4884
4885 ret = sdhci_led_register(host);
4886 if (ret) {
4887 pr_err("%s: Failed to register LED device: %d\n",
4888 mmc_hostname(mmc), ret);
4889 goto unirq;
4890 }
4891
4892 ret = mmc_add_host(mmc);
4893 if (ret)
4894 goto unled;
4895
4896 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4897 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4898 host->use_external_dma ? "External DMA" :
4899 (host->flags & SDHCI_USE_ADMA) ?
4900 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4901 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4902
4903 sdhci_enable_card_detection(host);
4904
4905 return 0;
4906
4907unled:
4908 sdhci_led_unregister(host);
4909unirq:
4910 sdhci_reset_for_all(host);
4911 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4912 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4913 free_irq(host->irq, host);
4914unwq:
4915 destroy_workqueue(host->complete_wq);
4916
4917 return ret;
4918}
4919EXPORT_SYMBOL_GPL(__sdhci_add_host);
4920
4921int sdhci_add_host(struct sdhci_host *host)
4922{
4923 int ret;
4924
4925 ret = sdhci_setup_host(host);
4926 if (ret)
4927 return ret;
4928
4929 ret = __sdhci_add_host(host);
4930 if (ret)
4931 goto cleanup;
4932
4933 return 0;
4934
4935cleanup:
4936 sdhci_cleanup_host(host);
4937
4938 return ret;
4939}
4940EXPORT_SYMBOL_GPL(sdhci_add_host);
4941
4942void sdhci_remove_host(struct sdhci_host *host, int dead)
4943{
4944 struct mmc_host *mmc = host->mmc;
4945 unsigned long flags;
4946
4947 if (dead) {
4948 spin_lock_irqsave(&host->lock, flags);
4949
4950 host->flags |= SDHCI_DEVICE_DEAD;
4951
4952 if (sdhci_has_requests(host)) {
4953 pr_err("%s: Controller removed during "
4954 " transfer!\n", mmc_hostname(mmc));
4955 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4956 }
4957
4958 spin_unlock_irqrestore(&host->lock, flags);
4959 }
4960
4961 sdhci_disable_card_detection(host);
4962
4963 mmc_remove_host(mmc);
4964
4965 sdhci_led_unregister(host);
4966
4967 if (!dead)
4968 sdhci_reset_for_all(host);
4969
4970 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4971 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4972 free_irq(host->irq, host);
4973
4974 del_timer_sync(&host->timer);
4975 del_timer_sync(&host->data_timer);
4976
4977 destroy_workqueue(host->complete_wq);
4978
4979 if (host->sdhci_core_to_disable_vqmmc)
4980 regulator_disable(mmc->supply.vqmmc);
4981
4982 if (host->align_buffer)
4983 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4984 host->adma_table_sz, host->align_buffer,
4985 host->align_addr);
4986
4987 if (host->use_external_dma)
4988 sdhci_external_dma_release(host);
4989
4990 host->adma_table = NULL;
4991 host->align_buffer = NULL;
4992}
4993
4994EXPORT_SYMBOL_GPL(sdhci_remove_host);
4995
4996void sdhci_free_host(struct sdhci_host *host)
4997{
4998 mmc_free_host(host->mmc);
4999}
5000
5001EXPORT_SYMBOL_GPL(sdhci_free_host);
5002
5003/*****************************************************************************\
5004 * *
5005 * Driver init/exit *
5006 * *
5007\*****************************************************************************/
5008
5009static int __init sdhci_drv_init(void)
5010{
5011 pr_info(DRIVER_NAME
5012 ": Secure Digital Host Controller Interface driver\n");
5013 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
5014
5015 return 0;
5016}
5017
5018static void __exit sdhci_drv_exit(void)
5019{
5020}
5021
5022module_init(sdhci_drv_init);
5023module_exit(sdhci_drv_exit);
5024
5025module_param(debug_quirks, uint, 0444);
5026module_param(debug_quirks2, uint, 0444);
5027
5028MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
5029MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
5030MODULE_LICENSE("GPL");
5031
5032MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
5033MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");