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1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/ktime.h>
18#include <linux/highmem.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/dma-mapping.h>
22#include <linux/slab.h>
23#include <linux/scatterlist.h>
24#include <linux/sizes.h>
25#include <linux/swiotlb.h>
26#include <linux/regulator/consumer.h>
27#include <linux/pm_runtime.h>
28#include <linux/of.h>
29
30#include <linux/leds.h>
31
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/card.h>
35#include <linux/mmc/sdio.h>
36#include <linux/mmc/slot-gpio.h>
37
38#include "sdhci.h"
39
40#define DRIVER_NAME "sdhci"
41
42#define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48#define MAX_TUNING_LOOP 40
49
50static unsigned int debug_quirks = 0;
51static unsigned int debug_quirks2;
52
53static void sdhci_finish_data(struct sdhci_host *);
54
55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
57void sdhci_dumpregs(struct sdhci_host *host)
58{
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("AC12 err: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_ACMD12_ERR),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127{
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
129}
130
131static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
132{
133 u32 present;
134
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
137 return;
138
139 if (enable) {
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT;
142
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
145 } else {
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
147 }
148
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
151}
152
153static void sdhci_enable_card_detection(struct sdhci_host *host)
154{
155 sdhci_set_card_detection(host, true);
156}
157
158static void sdhci_disable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, false);
161}
162
163static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
164{
165 if (host->bus_on)
166 return;
167 host->bus_on = true;
168 pm_runtime_get_noresume(host->mmc->parent);
169}
170
171static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
172{
173 if (!host->bus_on)
174 return;
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
177}
178
179void sdhci_reset(struct sdhci_host *host, u8 mask)
180{
181 ktime_t timeout;
182
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184
185 if (mask & SDHCI_RESET_ALL) {
186 host->clock = 0;
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
190 }
191
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
194
195 /* hw clears the bit when it's done */
196 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 if (ktime_after(ktime_get(), timeout)) {
198 pr_err("%s: Reset 0x%x never completed.\n",
199 mmc_hostname(host->mmc), (int)mask);
200 sdhci_dumpregs(host);
201 return;
202 }
203 udelay(10);
204 }
205}
206EXPORT_SYMBOL_GPL(sdhci_reset);
207
208static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
209{
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 struct mmc_host *mmc = host->mmc;
212
213 if (!mmc->ops->get_cd(mmc))
214 return;
215 }
216
217 host->ops->reset(host, mask);
218
219 if (mask & SDHCI_RESET_ALL) {
220 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
221 if (host->ops->enable_dma)
222 host->ops->enable_dma(host);
223 }
224
225 /* Resetting the controller clears many */
226 host->preset_enabled = false;
227 }
228}
229
230static void sdhci_set_default_irqs(struct sdhci_host *host)
231{
232 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
233 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
234 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
235 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
236 SDHCI_INT_RESPONSE;
237
238 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
239 host->tuning_mode == SDHCI_TUNING_MODE_3)
240 host->ier |= SDHCI_INT_RETUNE;
241
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
244}
245
246static void sdhci_init(struct sdhci_host *host, int soft)
247{
248 struct mmc_host *mmc = host->mmc;
249
250 if (soft)
251 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
252 else
253 sdhci_do_reset(host, SDHCI_RESET_ALL);
254
255 sdhci_set_default_irqs(host);
256
257 host->cqe_on = false;
258
259 if (soft) {
260 /* force clock reconfiguration */
261 host->clock = 0;
262 mmc->ops->set_ios(mmc, &mmc->ios);
263 }
264}
265
266static void sdhci_reinit(struct sdhci_host *host)
267{
268 sdhci_init(host, 0);
269 sdhci_enable_card_detection(host);
270}
271
272static void __sdhci_led_activate(struct sdhci_host *host)
273{
274 u8 ctrl;
275
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl |= SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
279}
280
281static void __sdhci_led_deactivate(struct sdhci_host *host)
282{
283 u8 ctrl;
284
285 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
286 ctrl &= ~SDHCI_CTRL_LED;
287 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
288}
289
290#if IS_REACHABLE(CONFIG_LEDS_CLASS)
291static void sdhci_led_control(struct led_classdev *led,
292 enum led_brightness brightness)
293{
294 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
295 unsigned long flags;
296
297 spin_lock_irqsave(&host->lock, flags);
298
299 if (host->runtime_suspended)
300 goto out;
301
302 if (brightness == LED_OFF)
303 __sdhci_led_deactivate(host);
304 else
305 __sdhci_led_activate(host);
306out:
307 spin_unlock_irqrestore(&host->lock, flags);
308}
309
310static int sdhci_led_register(struct sdhci_host *host)
311{
312 struct mmc_host *mmc = host->mmc;
313
314 snprintf(host->led_name, sizeof(host->led_name),
315 "%s::", mmc_hostname(mmc));
316
317 host->led.name = host->led_name;
318 host->led.brightness = LED_OFF;
319 host->led.default_trigger = mmc_hostname(mmc);
320 host->led.brightness_set = sdhci_led_control;
321
322 return led_classdev_register(mmc_dev(mmc), &host->led);
323}
324
325static void sdhci_led_unregister(struct sdhci_host *host)
326{
327 led_classdev_unregister(&host->led);
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332}
333
334static inline void sdhci_led_deactivate(struct sdhci_host *host)
335{
336}
337
338#else
339
340static inline int sdhci_led_register(struct sdhci_host *host)
341{
342 return 0;
343}
344
345static inline void sdhci_led_unregister(struct sdhci_host *host)
346{
347}
348
349static inline void sdhci_led_activate(struct sdhci_host *host)
350{
351 __sdhci_led_activate(host);
352}
353
354static inline void sdhci_led_deactivate(struct sdhci_host *host)
355{
356 __sdhci_led_deactivate(host);
357}
358
359#endif
360
361/*****************************************************************************\
362 * *
363 * Core functions *
364 * *
365\*****************************************************************************/
366
367static void sdhci_read_block_pio(struct sdhci_host *host)
368{
369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 uninitialized_var(scratch);
372 u8 *buf;
373
374 DBG("PIO reading\n");
375
376 blksize = host->data->blksz;
377 chunk = 0;
378
379 local_irq_save(flags);
380
381 while (blksize) {
382 BUG_ON(!sg_miter_next(&host->sg_miter));
383
384 len = min(host->sg_miter.length, blksize);
385
386 blksize -= len;
387 host->sg_miter.consumed = len;
388
389 buf = host->sg_miter.addr;
390
391 while (len) {
392 if (chunk == 0) {
393 scratch = sdhci_readl(host, SDHCI_BUFFER);
394 chunk = 4;
395 }
396
397 *buf = scratch & 0xFF;
398
399 buf++;
400 scratch >>= 8;
401 chunk--;
402 len--;
403 }
404 }
405
406 sg_miter_stop(&host->sg_miter);
407
408 local_irq_restore(flags);
409}
410
411static void sdhci_write_block_pio(struct sdhci_host *host)
412{
413 unsigned long flags;
414 size_t blksize, len, chunk;
415 u32 scratch;
416 u8 *buf;
417
418 DBG("PIO writing\n");
419
420 blksize = host->data->blksz;
421 chunk = 0;
422 scratch = 0;
423
424 local_irq_save(flags);
425
426 while (blksize) {
427 BUG_ON(!sg_miter_next(&host->sg_miter));
428
429 len = min(host->sg_miter.length, blksize);
430
431 blksize -= len;
432 host->sg_miter.consumed = len;
433
434 buf = host->sg_miter.addr;
435
436 while (len) {
437 scratch |= (u32)*buf << (chunk * 8);
438
439 buf++;
440 chunk++;
441 len--;
442
443 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
444 sdhci_writel(host, scratch, SDHCI_BUFFER);
445 chunk = 0;
446 scratch = 0;
447 }
448 }
449 }
450
451 sg_miter_stop(&host->sg_miter);
452
453 local_irq_restore(flags);
454}
455
456static void sdhci_transfer_pio(struct sdhci_host *host)
457{
458 u32 mask;
459
460 if (host->blocks == 0)
461 return;
462
463 if (host->data->flags & MMC_DATA_READ)
464 mask = SDHCI_DATA_AVAILABLE;
465 else
466 mask = SDHCI_SPACE_AVAILABLE;
467
468 /*
469 * Some controllers (JMicron JMB38x) mess up the buffer bits
470 * for transfers < 4 bytes. As long as it is just one block,
471 * we can ignore the bits.
472 */
473 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
474 (host->data->blocks == 1))
475 mask = ~0;
476
477 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
478 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
479 udelay(100);
480
481 if (host->data->flags & MMC_DATA_READ)
482 sdhci_read_block_pio(host);
483 else
484 sdhci_write_block_pio(host);
485
486 host->blocks--;
487 if (host->blocks == 0)
488 break;
489 }
490
491 DBG("PIO transfer complete.\n");
492}
493
494static int sdhci_pre_dma_transfer(struct sdhci_host *host,
495 struct mmc_data *data, int cookie)
496{
497 int sg_count;
498
499 /*
500 * If the data buffers are already mapped, return the previous
501 * dma_map_sg() result.
502 */
503 if (data->host_cookie == COOKIE_PRE_MAPPED)
504 return data->sg_count;
505
506 /* Bounce write requests to the bounce buffer */
507 if (host->bounce_buffer) {
508 unsigned int length = data->blksz * data->blocks;
509
510 if (length > host->bounce_buffer_size) {
511 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
512 mmc_hostname(host->mmc), length,
513 host->bounce_buffer_size);
514 return -EIO;
515 }
516 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
517 /* Copy the data to the bounce buffer */
518 sg_copy_to_buffer(data->sg, data->sg_len,
519 host->bounce_buffer,
520 length);
521 }
522 /* Switch ownership to the DMA */
523 dma_sync_single_for_device(host->mmc->parent,
524 host->bounce_addr,
525 host->bounce_buffer_size,
526 mmc_get_dma_dir(data));
527 /* Just a dummy value */
528 sg_count = 1;
529 } else {
530 /* Just access the data directly from memory */
531 sg_count = dma_map_sg(mmc_dev(host->mmc),
532 data->sg, data->sg_len,
533 mmc_get_dma_dir(data));
534 }
535
536 if (sg_count == 0)
537 return -ENOSPC;
538
539 data->sg_count = sg_count;
540 data->host_cookie = cookie;
541
542 return sg_count;
543}
544
545static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
546{
547 local_irq_save(*flags);
548 return kmap_atomic(sg_page(sg)) + sg->offset;
549}
550
551static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
552{
553 kunmap_atomic(buffer);
554 local_irq_restore(*flags);
555}
556
557static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
558 dma_addr_t addr, int len, unsigned cmd)
559{
560 struct sdhci_adma2_64_desc *dma_desc = desc;
561
562 /* 32-bit and 64-bit descriptors have these members in same position */
563 dma_desc->cmd = cpu_to_le16(cmd);
564 dma_desc->len = cpu_to_le16(len);
565 dma_desc->addr_lo = cpu_to_le32((u32)addr);
566
567 if (host->flags & SDHCI_USE_64_BIT_DMA)
568 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
569}
570
571static void sdhci_adma_mark_end(void *desc)
572{
573 struct sdhci_adma2_64_desc *dma_desc = desc;
574
575 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
576 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
577}
578
579static void sdhci_adma_table_pre(struct sdhci_host *host,
580 struct mmc_data *data, int sg_count)
581{
582 struct scatterlist *sg;
583 unsigned long flags;
584 dma_addr_t addr, align_addr;
585 void *desc, *align;
586 char *buffer;
587 int len, offset, i;
588
589 /*
590 * The spec does not specify endianness of descriptor table.
591 * We currently guess that it is LE.
592 */
593
594 host->sg_count = sg_count;
595
596 desc = host->adma_table;
597 align = host->align_buffer;
598
599 align_addr = host->align_addr;
600
601 for_each_sg(data->sg, sg, host->sg_count, i) {
602 addr = sg_dma_address(sg);
603 len = sg_dma_len(sg);
604
605 /*
606 * The SDHCI specification states that ADMA addresses must
607 * be 32-bit aligned. If they aren't, then we use a bounce
608 * buffer for the (up to three) bytes that screw up the
609 * alignment.
610 */
611 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
612 SDHCI_ADMA2_MASK;
613 if (offset) {
614 if (data->flags & MMC_DATA_WRITE) {
615 buffer = sdhci_kmap_atomic(sg, &flags);
616 memcpy(align, buffer, offset);
617 sdhci_kunmap_atomic(buffer, &flags);
618 }
619
620 /* tran, valid */
621 sdhci_adma_write_desc(host, desc, align_addr, offset,
622 ADMA2_TRAN_VALID);
623
624 BUG_ON(offset > 65536);
625
626 align += SDHCI_ADMA2_ALIGN;
627 align_addr += SDHCI_ADMA2_ALIGN;
628
629 desc += host->desc_sz;
630
631 addr += offset;
632 len -= offset;
633 }
634
635 BUG_ON(len > 65536);
636
637 if (len) {
638 /* tran, valid */
639 sdhci_adma_write_desc(host, desc, addr, len,
640 ADMA2_TRAN_VALID);
641 desc += host->desc_sz;
642 }
643
644 /*
645 * If this triggers then we have a calculation bug
646 * somewhere. :/
647 */
648 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
649 }
650
651 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
652 /* Mark the last descriptor as the terminating descriptor */
653 if (desc != host->adma_table) {
654 desc -= host->desc_sz;
655 sdhci_adma_mark_end(desc);
656 }
657 } else {
658 /* Add a terminating entry - nop, end, valid */
659 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
660 }
661}
662
663static void sdhci_adma_table_post(struct sdhci_host *host,
664 struct mmc_data *data)
665{
666 struct scatterlist *sg;
667 int i, size;
668 void *align;
669 char *buffer;
670 unsigned long flags;
671
672 if (data->flags & MMC_DATA_READ) {
673 bool has_unaligned = false;
674
675 /* Do a quick scan of the SG list for any unaligned mappings */
676 for_each_sg(data->sg, sg, host->sg_count, i)
677 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
678 has_unaligned = true;
679 break;
680 }
681
682 if (has_unaligned) {
683 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
684 data->sg_len, DMA_FROM_DEVICE);
685
686 align = host->align_buffer;
687
688 for_each_sg(data->sg, sg, host->sg_count, i) {
689 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
690 size = SDHCI_ADMA2_ALIGN -
691 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
692
693 buffer = sdhci_kmap_atomic(sg, &flags);
694 memcpy(buffer, align, size);
695 sdhci_kunmap_atomic(buffer, &flags);
696
697 align += SDHCI_ADMA2_ALIGN;
698 }
699 }
700 }
701 }
702}
703
704static u32 sdhci_sdma_address(struct sdhci_host *host)
705{
706 if (host->bounce_buffer)
707 return host->bounce_addr;
708 else
709 return sg_dma_address(host->data->sg);
710}
711
712static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
713{
714 u8 count;
715 struct mmc_data *data = cmd->data;
716 unsigned target_timeout, current_timeout;
717
718 /*
719 * If the host controller provides us with an incorrect timeout
720 * value, just skip the check and use 0xE. The hardware may take
721 * longer to time out, but that's much better than having a too-short
722 * timeout value.
723 */
724 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
725 return 0xE;
726
727 /* Unspecified timeout, assume max */
728 if (!data && !cmd->busy_timeout)
729 return 0xE;
730
731 /* timeout in us */
732 if (!data)
733 target_timeout = cmd->busy_timeout * 1000;
734 else {
735 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
736 if (host->clock && data->timeout_clks) {
737 unsigned long long val;
738
739 /*
740 * data->timeout_clks is in units of clock cycles.
741 * host->clock is in Hz. target_timeout is in us.
742 * Hence, us = 1000000 * cycles / Hz. Round up.
743 */
744 val = 1000000ULL * data->timeout_clks;
745 if (do_div(val, host->clock))
746 target_timeout++;
747 target_timeout += val;
748 }
749 }
750
751 /*
752 * Figure out needed cycles.
753 * We do this in steps in order to fit inside a 32 bit int.
754 * The first step is the minimum timeout, which will have a
755 * minimum resolution of 6 bits:
756 * (1) 2^13*1000 > 2^22,
757 * (2) host->timeout_clk < 2^16
758 * =>
759 * (1) / (2) > 2^6
760 */
761 count = 0;
762 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
763 while (current_timeout < target_timeout) {
764 count++;
765 current_timeout <<= 1;
766 if (count >= 0xF)
767 break;
768 }
769
770 if (count >= 0xF) {
771 DBG("Too large timeout 0x%x requested for CMD%d!\n",
772 count, cmd->opcode);
773 count = 0xE;
774 }
775
776 return count;
777}
778
779static void sdhci_set_transfer_irqs(struct sdhci_host *host)
780{
781 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
782 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
783
784 if (host->flags & SDHCI_REQ_USE_DMA)
785 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
786 else
787 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
788
789 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
790 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
791}
792
793static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
794{
795 u8 count;
796
797 if (host->ops->set_timeout) {
798 host->ops->set_timeout(host, cmd);
799 } else {
800 count = sdhci_calc_timeout(host, cmd);
801 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
802 }
803}
804
805static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
806{
807 u8 ctrl;
808 struct mmc_data *data = cmd->data;
809
810 if (sdhci_data_line_cmd(cmd))
811 sdhci_set_timeout(host, cmd);
812
813 if (!data)
814 return;
815
816 WARN_ON(host->data);
817
818 /* Sanity checks */
819 BUG_ON(data->blksz * data->blocks > 524288);
820 BUG_ON(data->blksz > host->mmc->max_blk_size);
821 BUG_ON(data->blocks > 65535);
822
823 host->data = data;
824 host->data_early = 0;
825 host->data->bytes_xfered = 0;
826
827 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
828 struct scatterlist *sg;
829 unsigned int length_mask, offset_mask;
830 int i;
831
832 host->flags |= SDHCI_REQ_USE_DMA;
833
834 /*
835 * FIXME: This doesn't account for merging when mapping the
836 * scatterlist.
837 *
838 * The assumption here being that alignment and lengths are
839 * the same after DMA mapping to device address space.
840 */
841 length_mask = 0;
842 offset_mask = 0;
843 if (host->flags & SDHCI_USE_ADMA) {
844 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
845 length_mask = 3;
846 /*
847 * As we use up to 3 byte chunks to work
848 * around alignment problems, we need to
849 * check the offset as well.
850 */
851 offset_mask = 3;
852 }
853 } else {
854 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
855 length_mask = 3;
856 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
857 offset_mask = 3;
858 }
859
860 if (unlikely(length_mask | offset_mask)) {
861 for_each_sg(data->sg, sg, data->sg_len, i) {
862 if (sg->length & length_mask) {
863 DBG("Reverting to PIO because of transfer size (%d)\n",
864 sg->length);
865 host->flags &= ~SDHCI_REQ_USE_DMA;
866 break;
867 }
868 if (sg->offset & offset_mask) {
869 DBG("Reverting to PIO because of bad alignment\n");
870 host->flags &= ~SDHCI_REQ_USE_DMA;
871 break;
872 }
873 }
874 }
875 }
876
877 if (host->flags & SDHCI_REQ_USE_DMA) {
878 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
879
880 if (sg_cnt <= 0) {
881 /*
882 * This only happens when someone fed
883 * us an invalid request.
884 */
885 WARN_ON(1);
886 host->flags &= ~SDHCI_REQ_USE_DMA;
887 } else if (host->flags & SDHCI_USE_ADMA) {
888 sdhci_adma_table_pre(host, data, sg_cnt);
889
890 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
891 if (host->flags & SDHCI_USE_64_BIT_DMA)
892 sdhci_writel(host,
893 (u64)host->adma_addr >> 32,
894 SDHCI_ADMA_ADDRESS_HI);
895 } else {
896 WARN_ON(sg_cnt != 1);
897 sdhci_writel(host, sdhci_sdma_address(host),
898 SDHCI_DMA_ADDRESS);
899 }
900 }
901
902 /*
903 * Always adjust the DMA selection as some controllers
904 * (e.g. JMicron) can't do PIO properly when the selection
905 * is ADMA.
906 */
907 if (host->version >= SDHCI_SPEC_200) {
908 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
909 ctrl &= ~SDHCI_CTRL_DMA_MASK;
910 if ((host->flags & SDHCI_REQ_USE_DMA) &&
911 (host->flags & SDHCI_USE_ADMA)) {
912 if (host->flags & SDHCI_USE_64_BIT_DMA)
913 ctrl |= SDHCI_CTRL_ADMA64;
914 else
915 ctrl |= SDHCI_CTRL_ADMA32;
916 } else {
917 ctrl |= SDHCI_CTRL_SDMA;
918 }
919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
920 }
921
922 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
923 int flags;
924
925 flags = SG_MITER_ATOMIC;
926 if (host->data->flags & MMC_DATA_READ)
927 flags |= SG_MITER_TO_SG;
928 else
929 flags |= SG_MITER_FROM_SG;
930 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
931 host->blocks = data->blocks;
932 }
933
934 sdhci_set_transfer_irqs(host);
935
936 /* Set the DMA boundary value and block size */
937 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
938 SDHCI_BLOCK_SIZE);
939 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
940}
941
942static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
943 struct mmc_request *mrq)
944{
945 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
946 !mrq->cap_cmd_during_tfr;
947}
948
949static void sdhci_set_transfer_mode(struct sdhci_host *host,
950 struct mmc_command *cmd)
951{
952 u16 mode = 0;
953 struct mmc_data *data = cmd->data;
954
955 if (data == NULL) {
956 if (host->quirks2 &
957 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
958 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
959 } else {
960 /* clear Auto CMD settings for no data CMDs */
961 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
962 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
963 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
964 }
965 return;
966 }
967
968 WARN_ON(!host->data);
969
970 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
971 mode = SDHCI_TRNS_BLK_CNT_EN;
972
973 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
974 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
975 /*
976 * If we are sending CMD23, CMD12 never gets sent
977 * on successful completion (so no Auto-CMD12).
978 */
979 if (sdhci_auto_cmd12(host, cmd->mrq) &&
980 (cmd->opcode != SD_IO_RW_EXTENDED))
981 mode |= SDHCI_TRNS_AUTO_CMD12;
982 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
983 mode |= SDHCI_TRNS_AUTO_CMD23;
984 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
985 }
986 }
987
988 if (data->flags & MMC_DATA_READ)
989 mode |= SDHCI_TRNS_READ;
990 if (host->flags & SDHCI_REQ_USE_DMA)
991 mode |= SDHCI_TRNS_DMA;
992
993 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
994}
995
996static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
997{
998 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
999 ((mrq->cmd && mrq->cmd->error) ||
1000 (mrq->sbc && mrq->sbc->error) ||
1001 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
1002 (mrq->data->stop && mrq->data->stop->error))) ||
1003 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1004}
1005
1006static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1007{
1008 int i;
1009
1010 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1011 if (host->mrqs_done[i] == mrq) {
1012 WARN_ON(1);
1013 return;
1014 }
1015 }
1016
1017 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1018 if (!host->mrqs_done[i]) {
1019 host->mrqs_done[i] = mrq;
1020 break;
1021 }
1022 }
1023
1024 WARN_ON(i >= SDHCI_MAX_MRQS);
1025
1026 tasklet_schedule(&host->finish_tasklet);
1027}
1028
1029static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1030{
1031 if (host->cmd && host->cmd->mrq == mrq)
1032 host->cmd = NULL;
1033
1034 if (host->data_cmd && host->data_cmd->mrq == mrq)
1035 host->data_cmd = NULL;
1036
1037 if (host->data && host->data->mrq == mrq)
1038 host->data = NULL;
1039
1040 if (sdhci_needs_reset(host, mrq))
1041 host->pending_reset = true;
1042
1043 __sdhci_finish_mrq(host, mrq);
1044}
1045
1046static void sdhci_finish_data(struct sdhci_host *host)
1047{
1048 struct mmc_command *data_cmd = host->data_cmd;
1049 struct mmc_data *data = host->data;
1050
1051 host->data = NULL;
1052 host->data_cmd = NULL;
1053
1054 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1055 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1056 sdhci_adma_table_post(host, data);
1057
1058 /*
1059 * The specification states that the block count register must
1060 * be updated, but it does not specify at what point in the
1061 * data flow. That makes the register entirely useless to read
1062 * back so we have to assume that nothing made it to the card
1063 * in the event of an error.
1064 */
1065 if (data->error)
1066 data->bytes_xfered = 0;
1067 else
1068 data->bytes_xfered = data->blksz * data->blocks;
1069
1070 /*
1071 * Need to send CMD12 if -
1072 * a) open-ended multiblock transfer (no CMD23)
1073 * b) error in multiblock transfer
1074 */
1075 if (data->stop &&
1076 (data->error ||
1077 !data->mrq->sbc)) {
1078
1079 /*
1080 * The controller needs a reset of internal state machines
1081 * upon error conditions.
1082 */
1083 if (data->error) {
1084 if (!host->cmd || host->cmd == data_cmd)
1085 sdhci_do_reset(host, SDHCI_RESET_CMD);
1086 sdhci_do_reset(host, SDHCI_RESET_DATA);
1087 }
1088
1089 /*
1090 * 'cap_cmd_during_tfr' request must not use the command line
1091 * after mmc_command_done() has been called. It is upper layer's
1092 * responsibility to send the stop command if required.
1093 */
1094 if (data->mrq->cap_cmd_during_tfr) {
1095 sdhci_finish_mrq(host, data->mrq);
1096 } else {
1097 /* Avoid triggering warning in sdhci_send_command() */
1098 host->cmd = NULL;
1099 sdhci_send_command(host, data->stop);
1100 }
1101 } else {
1102 sdhci_finish_mrq(host, data->mrq);
1103 }
1104}
1105
1106static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1107 unsigned long timeout)
1108{
1109 if (sdhci_data_line_cmd(mrq->cmd))
1110 mod_timer(&host->data_timer, timeout);
1111 else
1112 mod_timer(&host->timer, timeout);
1113}
1114
1115static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1116{
1117 if (sdhci_data_line_cmd(mrq->cmd))
1118 del_timer(&host->data_timer);
1119 else
1120 del_timer(&host->timer);
1121}
1122
1123void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1124{
1125 int flags;
1126 u32 mask;
1127 unsigned long timeout;
1128
1129 WARN_ON(host->cmd);
1130
1131 /* Initially, a command has no error */
1132 cmd->error = 0;
1133
1134 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1135 cmd->opcode == MMC_STOP_TRANSMISSION)
1136 cmd->flags |= MMC_RSP_BUSY;
1137
1138 /* Wait max 10 ms */
1139 timeout = 10;
1140
1141 mask = SDHCI_CMD_INHIBIT;
1142 if (sdhci_data_line_cmd(cmd))
1143 mask |= SDHCI_DATA_INHIBIT;
1144
1145 /* We shouldn't wait for data inihibit for stop commands, even
1146 though they might use busy signaling */
1147 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1148 mask &= ~SDHCI_DATA_INHIBIT;
1149
1150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1151 if (timeout == 0) {
1152 pr_err("%s: Controller never released inhibit bit(s).\n",
1153 mmc_hostname(host->mmc));
1154 sdhci_dumpregs(host);
1155 cmd->error = -EIO;
1156 sdhci_finish_mrq(host, cmd->mrq);
1157 return;
1158 }
1159 timeout--;
1160 mdelay(1);
1161 }
1162
1163 timeout = jiffies;
1164 if (!cmd->data && cmd->busy_timeout > 9000)
1165 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1166 else
1167 timeout += 10 * HZ;
1168 sdhci_mod_timer(host, cmd->mrq, timeout);
1169
1170 host->cmd = cmd;
1171 if (sdhci_data_line_cmd(cmd)) {
1172 WARN_ON(host->data_cmd);
1173 host->data_cmd = cmd;
1174 }
1175
1176 sdhci_prepare_data(host, cmd);
1177
1178 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1179
1180 sdhci_set_transfer_mode(host, cmd);
1181
1182 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1183 pr_err("%s: Unsupported response type!\n",
1184 mmc_hostname(host->mmc));
1185 cmd->error = -EINVAL;
1186 sdhci_finish_mrq(host, cmd->mrq);
1187 return;
1188 }
1189
1190 if (!(cmd->flags & MMC_RSP_PRESENT))
1191 flags = SDHCI_CMD_RESP_NONE;
1192 else if (cmd->flags & MMC_RSP_136)
1193 flags = SDHCI_CMD_RESP_LONG;
1194 else if (cmd->flags & MMC_RSP_BUSY)
1195 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1196 else
1197 flags = SDHCI_CMD_RESP_SHORT;
1198
1199 if (cmd->flags & MMC_RSP_CRC)
1200 flags |= SDHCI_CMD_CRC;
1201 if (cmd->flags & MMC_RSP_OPCODE)
1202 flags |= SDHCI_CMD_INDEX;
1203
1204 /* CMD19 is special in that the Data Present Select should be set */
1205 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1206 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1207 flags |= SDHCI_CMD_DATA;
1208
1209 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1210}
1211EXPORT_SYMBOL_GPL(sdhci_send_command);
1212
1213static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1214{
1215 int i, reg;
1216
1217 for (i = 0; i < 4; i++) {
1218 reg = SDHCI_RESPONSE + (3 - i) * 4;
1219 cmd->resp[i] = sdhci_readl(host, reg);
1220 }
1221
1222 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1223 return;
1224
1225 /* CRC is stripped so we need to do some shifting */
1226 for (i = 0; i < 4; i++) {
1227 cmd->resp[i] <<= 8;
1228 if (i != 3)
1229 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1230 }
1231}
1232
1233static void sdhci_finish_command(struct sdhci_host *host)
1234{
1235 struct mmc_command *cmd = host->cmd;
1236
1237 host->cmd = NULL;
1238
1239 if (cmd->flags & MMC_RSP_PRESENT) {
1240 if (cmd->flags & MMC_RSP_136) {
1241 sdhci_read_rsp_136(host, cmd);
1242 } else {
1243 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1244 }
1245 }
1246
1247 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1248 mmc_command_done(host->mmc, cmd->mrq);
1249
1250 /*
1251 * The host can send and interrupt when the busy state has
1252 * ended, allowing us to wait without wasting CPU cycles.
1253 * The busy signal uses DAT0 so this is similar to waiting
1254 * for data to complete.
1255 *
1256 * Note: The 1.0 specification is a bit ambiguous about this
1257 * feature so there might be some problems with older
1258 * controllers.
1259 */
1260 if (cmd->flags & MMC_RSP_BUSY) {
1261 if (cmd->data) {
1262 DBG("Cannot wait for busy signal when also doing a data transfer");
1263 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1264 cmd == host->data_cmd) {
1265 /* Command complete before busy is ended */
1266 return;
1267 }
1268 }
1269
1270 /* Finished CMD23, now send actual command. */
1271 if (cmd == cmd->mrq->sbc) {
1272 sdhci_send_command(host, cmd->mrq->cmd);
1273 } else {
1274
1275 /* Processed actual command. */
1276 if (host->data && host->data_early)
1277 sdhci_finish_data(host);
1278
1279 if (!cmd->data)
1280 sdhci_finish_mrq(host, cmd->mrq);
1281 }
1282}
1283
1284static u16 sdhci_get_preset_value(struct sdhci_host *host)
1285{
1286 u16 preset = 0;
1287
1288 switch (host->timing) {
1289 case MMC_TIMING_UHS_SDR12:
1290 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1291 break;
1292 case MMC_TIMING_UHS_SDR25:
1293 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1294 break;
1295 case MMC_TIMING_UHS_SDR50:
1296 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1297 break;
1298 case MMC_TIMING_UHS_SDR104:
1299 case MMC_TIMING_MMC_HS200:
1300 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1301 break;
1302 case MMC_TIMING_UHS_DDR50:
1303 case MMC_TIMING_MMC_DDR52:
1304 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1305 break;
1306 case MMC_TIMING_MMC_HS400:
1307 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1308 break;
1309 default:
1310 pr_warn("%s: Invalid UHS-I mode selected\n",
1311 mmc_hostname(host->mmc));
1312 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1313 break;
1314 }
1315 return preset;
1316}
1317
1318u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1319 unsigned int *actual_clock)
1320{
1321 int div = 0; /* Initialized for compiler warning */
1322 int real_div = div, clk_mul = 1;
1323 u16 clk = 0;
1324 bool switch_base_clk = false;
1325
1326 if (host->version >= SDHCI_SPEC_300) {
1327 if (host->preset_enabled) {
1328 u16 pre_val;
1329
1330 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1331 pre_val = sdhci_get_preset_value(host);
1332 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1333 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1334 if (host->clk_mul &&
1335 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1336 clk = SDHCI_PROG_CLOCK_MODE;
1337 real_div = div + 1;
1338 clk_mul = host->clk_mul;
1339 } else {
1340 real_div = max_t(int, 1, div << 1);
1341 }
1342 goto clock_set;
1343 }
1344
1345 /*
1346 * Check if the Host Controller supports Programmable Clock
1347 * Mode.
1348 */
1349 if (host->clk_mul) {
1350 for (div = 1; div <= 1024; div++) {
1351 if ((host->max_clk * host->clk_mul / div)
1352 <= clock)
1353 break;
1354 }
1355 if ((host->max_clk * host->clk_mul / div) <= clock) {
1356 /*
1357 * Set Programmable Clock Mode in the Clock
1358 * Control register.
1359 */
1360 clk = SDHCI_PROG_CLOCK_MODE;
1361 real_div = div;
1362 clk_mul = host->clk_mul;
1363 div--;
1364 } else {
1365 /*
1366 * Divisor can be too small to reach clock
1367 * speed requirement. Then use the base clock.
1368 */
1369 switch_base_clk = true;
1370 }
1371 }
1372
1373 if (!host->clk_mul || switch_base_clk) {
1374 /* Version 3.00 divisors must be a multiple of 2. */
1375 if (host->max_clk <= clock)
1376 div = 1;
1377 else {
1378 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1379 div += 2) {
1380 if ((host->max_clk / div) <= clock)
1381 break;
1382 }
1383 }
1384 real_div = div;
1385 div >>= 1;
1386 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1387 && !div && host->max_clk <= 25000000)
1388 div = 1;
1389 }
1390 } else {
1391 /* Version 2.00 divisors must be a power of 2. */
1392 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1393 if ((host->max_clk / div) <= clock)
1394 break;
1395 }
1396 real_div = div;
1397 div >>= 1;
1398 }
1399
1400clock_set:
1401 if (real_div)
1402 *actual_clock = (host->max_clk * clk_mul) / real_div;
1403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1405 << SDHCI_DIVIDER_HI_SHIFT;
1406
1407 return clk;
1408}
1409EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1410
1411void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1412{
1413 ktime_t timeout;
1414
1415 clk |= SDHCI_CLOCK_INT_EN;
1416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1417
1418 /* Wait max 20 ms */
1419 timeout = ktime_add_ms(ktime_get(), 20);
1420 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1421 & SDHCI_CLOCK_INT_STABLE)) {
1422 if (ktime_after(ktime_get(), timeout)) {
1423 pr_err("%s: Internal clock never stabilised.\n",
1424 mmc_hostname(host->mmc));
1425 sdhci_dumpregs(host);
1426 return;
1427 }
1428 udelay(10);
1429 }
1430
1431 clk |= SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433}
1434EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1435
1436void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1437{
1438 u16 clk;
1439
1440 host->mmc->actual_clock = 0;
1441
1442 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1443
1444 if (clock == 0)
1445 return;
1446
1447 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1448 sdhci_enable_clk(host, clk);
1449}
1450EXPORT_SYMBOL_GPL(sdhci_set_clock);
1451
1452static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1453 unsigned short vdd)
1454{
1455 struct mmc_host *mmc = host->mmc;
1456
1457 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1458
1459 if (mode != MMC_POWER_OFF)
1460 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1461 else
1462 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1463}
1464
1465void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1466 unsigned short vdd)
1467{
1468 u8 pwr = 0;
1469
1470 if (mode != MMC_POWER_OFF) {
1471 switch (1 << vdd) {
1472 case MMC_VDD_165_195:
1473 /*
1474 * Without a regulator, SDHCI does not support 2.0v
1475 * so we only get here if the driver deliberately
1476 * added the 2.0v range to ocr_avail. Map it to 1.8v
1477 * for the purpose of turning on the power.
1478 */
1479 case MMC_VDD_20_21:
1480 pwr = SDHCI_POWER_180;
1481 break;
1482 case MMC_VDD_29_30:
1483 case MMC_VDD_30_31:
1484 pwr = SDHCI_POWER_300;
1485 break;
1486 case MMC_VDD_32_33:
1487 case MMC_VDD_33_34:
1488 pwr = SDHCI_POWER_330;
1489 break;
1490 default:
1491 WARN(1, "%s: Invalid vdd %#x\n",
1492 mmc_hostname(host->mmc), vdd);
1493 break;
1494 }
1495 }
1496
1497 if (host->pwr == pwr)
1498 return;
1499
1500 host->pwr = pwr;
1501
1502 if (pwr == 0) {
1503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1504 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1505 sdhci_runtime_pm_bus_off(host);
1506 } else {
1507 /*
1508 * Spec says that we should clear the power reg before setting
1509 * a new value. Some controllers don't seem to like this though.
1510 */
1511 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1512 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1513
1514 /*
1515 * At least the Marvell CaFe chip gets confused if we set the
1516 * voltage and set turn on power at the same time, so set the
1517 * voltage first.
1518 */
1519 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1520 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1521
1522 pwr |= SDHCI_POWER_ON;
1523
1524 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1525
1526 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1527 sdhci_runtime_pm_bus_on(host);
1528
1529 /*
1530 * Some controllers need an extra 10ms delay of 10ms before
1531 * they can apply clock after applying power
1532 */
1533 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1534 mdelay(10);
1535 }
1536}
1537EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1538
1539void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1540 unsigned short vdd)
1541{
1542 if (IS_ERR(host->mmc->supply.vmmc))
1543 sdhci_set_power_noreg(host, mode, vdd);
1544 else
1545 sdhci_set_power_reg(host, mode, vdd);
1546}
1547EXPORT_SYMBOL_GPL(sdhci_set_power);
1548
1549/*****************************************************************************\
1550 * *
1551 * MMC callbacks *
1552 * *
1553\*****************************************************************************/
1554
1555static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1556{
1557 struct sdhci_host *host;
1558 int present;
1559 unsigned long flags;
1560
1561 host = mmc_priv(mmc);
1562
1563 /* Firstly check card presence */
1564 present = mmc->ops->get_cd(mmc);
1565
1566 spin_lock_irqsave(&host->lock, flags);
1567
1568 sdhci_led_activate(host);
1569
1570 /*
1571 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1572 * requests if Auto-CMD12 is enabled.
1573 */
1574 if (sdhci_auto_cmd12(host, mrq)) {
1575 if (mrq->stop) {
1576 mrq->data->stop = NULL;
1577 mrq->stop = NULL;
1578 }
1579 }
1580
1581 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1582 mrq->cmd->error = -ENOMEDIUM;
1583 sdhci_finish_mrq(host, mrq);
1584 } else {
1585 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1586 sdhci_send_command(host, mrq->sbc);
1587 else
1588 sdhci_send_command(host, mrq->cmd);
1589 }
1590
1591 mmiowb();
1592 spin_unlock_irqrestore(&host->lock, flags);
1593}
1594
1595void sdhci_set_bus_width(struct sdhci_host *host, int width)
1596{
1597 u8 ctrl;
1598
1599 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1600 if (width == MMC_BUS_WIDTH_8) {
1601 ctrl &= ~SDHCI_CTRL_4BITBUS;
1602 ctrl |= SDHCI_CTRL_8BITBUS;
1603 } else {
1604 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1605 ctrl &= ~SDHCI_CTRL_8BITBUS;
1606 if (width == MMC_BUS_WIDTH_4)
1607 ctrl |= SDHCI_CTRL_4BITBUS;
1608 else
1609 ctrl &= ~SDHCI_CTRL_4BITBUS;
1610 }
1611 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1612}
1613EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1614
1615void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1616{
1617 u16 ctrl_2;
1618
1619 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1620 /* Select Bus Speed Mode for host */
1621 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1622 if ((timing == MMC_TIMING_MMC_HS200) ||
1623 (timing == MMC_TIMING_UHS_SDR104))
1624 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1625 else if (timing == MMC_TIMING_UHS_SDR12)
1626 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1627 else if (timing == MMC_TIMING_UHS_SDR25)
1628 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1629 else if (timing == MMC_TIMING_UHS_SDR50)
1630 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1631 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1632 (timing == MMC_TIMING_MMC_DDR52))
1633 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1634 else if (timing == MMC_TIMING_MMC_HS400)
1635 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1636 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1637}
1638EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1639
1640void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 u8 ctrl;
1644
1645 if (ios->power_mode == MMC_POWER_UNDEFINED)
1646 return;
1647
1648 if (host->flags & SDHCI_DEVICE_DEAD) {
1649 if (!IS_ERR(mmc->supply.vmmc) &&
1650 ios->power_mode == MMC_POWER_OFF)
1651 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1652 return;
1653 }
1654
1655 /*
1656 * Reset the chip on each power off.
1657 * Should clear out any weird states.
1658 */
1659 if (ios->power_mode == MMC_POWER_OFF) {
1660 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1661 sdhci_reinit(host);
1662 }
1663
1664 if (host->version >= SDHCI_SPEC_300 &&
1665 (ios->power_mode == MMC_POWER_UP) &&
1666 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1667 sdhci_enable_preset_value(host, false);
1668
1669 if (!ios->clock || ios->clock != host->clock) {
1670 host->ops->set_clock(host, ios->clock);
1671 host->clock = ios->clock;
1672
1673 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1674 host->clock) {
1675 host->timeout_clk = host->mmc->actual_clock ?
1676 host->mmc->actual_clock / 1000 :
1677 host->clock / 1000;
1678 host->mmc->max_busy_timeout =
1679 host->ops->get_max_timeout_count ?
1680 host->ops->get_max_timeout_count(host) :
1681 1 << 27;
1682 host->mmc->max_busy_timeout /= host->timeout_clk;
1683 }
1684 }
1685
1686 if (host->ops->set_power)
1687 host->ops->set_power(host, ios->power_mode, ios->vdd);
1688 else
1689 sdhci_set_power(host, ios->power_mode, ios->vdd);
1690
1691 if (host->ops->platform_send_init_74_clocks)
1692 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1693
1694 host->ops->set_bus_width(host, ios->bus_width);
1695
1696 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1697
1698 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1699 if (ios->timing == MMC_TIMING_SD_HS ||
1700 ios->timing == MMC_TIMING_MMC_HS ||
1701 ios->timing == MMC_TIMING_MMC_HS400 ||
1702 ios->timing == MMC_TIMING_MMC_HS200 ||
1703 ios->timing == MMC_TIMING_MMC_DDR52 ||
1704 ios->timing == MMC_TIMING_UHS_SDR50 ||
1705 ios->timing == MMC_TIMING_UHS_SDR104 ||
1706 ios->timing == MMC_TIMING_UHS_DDR50 ||
1707 ios->timing == MMC_TIMING_UHS_SDR25)
1708 ctrl |= SDHCI_CTRL_HISPD;
1709 else
1710 ctrl &= ~SDHCI_CTRL_HISPD;
1711 }
1712
1713 if (host->version >= SDHCI_SPEC_300) {
1714 u16 clk, ctrl_2;
1715
1716 if (!host->preset_enabled) {
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1718 /*
1719 * We only need to set Driver Strength if the
1720 * preset value enable is not set.
1721 */
1722 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1723 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1724 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1725 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1726 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1727 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1728 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1729 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1730 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1731 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1732 else {
1733 pr_warn("%s: invalid driver type, default to driver type B\n",
1734 mmc_hostname(mmc));
1735 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1736 }
1737
1738 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1739 } else {
1740 /*
1741 * According to SDHC Spec v3.00, if the Preset Value
1742 * Enable in the Host Control 2 register is set, we
1743 * need to reset SD Clock Enable before changing High
1744 * Speed Enable to avoid generating clock gliches.
1745 */
1746
1747 /* Reset SD Clock Enable */
1748 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1749 clk &= ~SDHCI_CLOCK_CARD_EN;
1750 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1751
1752 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1753
1754 /* Re-enable SD Clock */
1755 host->ops->set_clock(host, host->clock);
1756 }
1757
1758 /* Reset SD Clock Enable */
1759 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1760 clk &= ~SDHCI_CLOCK_CARD_EN;
1761 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1762
1763 host->ops->set_uhs_signaling(host, ios->timing);
1764 host->timing = ios->timing;
1765
1766 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1767 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1768 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1769 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1770 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1771 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1772 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1773 u16 preset;
1774
1775 sdhci_enable_preset_value(host, true);
1776 preset = sdhci_get_preset_value(host);
1777 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1778 >> SDHCI_PRESET_DRV_SHIFT;
1779 }
1780
1781 /* Re-enable SD Clock */
1782 host->ops->set_clock(host, host->clock);
1783 } else
1784 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1785
1786 /*
1787 * Some (ENE) controllers go apeshit on some ios operation,
1788 * signalling timeout and CRC errors even on CMD0. Resetting
1789 * it on each ios seems to solve the problem.
1790 */
1791 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1792 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1793
1794 mmiowb();
1795}
1796EXPORT_SYMBOL_GPL(sdhci_set_ios);
1797
1798static int sdhci_get_cd(struct mmc_host *mmc)
1799{
1800 struct sdhci_host *host = mmc_priv(mmc);
1801 int gpio_cd = mmc_gpio_get_cd(mmc);
1802
1803 if (host->flags & SDHCI_DEVICE_DEAD)
1804 return 0;
1805
1806 /* If nonremovable, assume that the card is always present. */
1807 if (!mmc_card_is_removable(host->mmc))
1808 return 1;
1809
1810 /*
1811 * Try slot gpio detect, if defined it take precedence
1812 * over build in controller functionality
1813 */
1814 if (gpio_cd >= 0)
1815 return !!gpio_cd;
1816
1817 /* If polling, assume that the card is always present. */
1818 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1819 return 1;
1820
1821 /* Host native card detect */
1822 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1823}
1824
1825static int sdhci_check_ro(struct sdhci_host *host)
1826{
1827 unsigned long flags;
1828 int is_readonly;
1829
1830 spin_lock_irqsave(&host->lock, flags);
1831
1832 if (host->flags & SDHCI_DEVICE_DEAD)
1833 is_readonly = 0;
1834 else if (host->ops->get_ro)
1835 is_readonly = host->ops->get_ro(host);
1836 else
1837 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1838 & SDHCI_WRITE_PROTECT);
1839
1840 spin_unlock_irqrestore(&host->lock, flags);
1841
1842 /* This quirk needs to be replaced by a callback-function later */
1843 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1844 !is_readonly : is_readonly;
1845}
1846
1847#define SAMPLE_COUNT 5
1848
1849static int sdhci_get_ro(struct mmc_host *mmc)
1850{
1851 struct sdhci_host *host = mmc_priv(mmc);
1852 int i, ro_count;
1853
1854 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1855 return sdhci_check_ro(host);
1856
1857 ro_count = 0;
1858 for (i = 0; i < SAMPLE_COUNT; i++) {
1859 if (sdhci_check_ro(host)) {
1860 if (++ro_count > SAMPLE_COUNT / 2)
1861 return 1;
1862 }
1863 msleep(30);
1864 }
1865 return 0;
1866}
1867
1868static void sdhci_hw_reset(struct mmc_host *mmc)
1869{
1870 struct sdhci_host *host = mmc_priv(mmc);
1871
1872 if (host->ops && host->ops->hw_reset)
1873 host->ops->hw_reset(host);
1874}
1875
1876static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1877{
1878 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1879 if (enable)
1880 host->ier |= SDHCI_INT_CARD_INT;
1881 else
1882 host->ier &= ~SDHCI_INT_CARD_INT;
1883
1884 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1885 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1886 mmiowb();
1887 }
1888}
1889
1890void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1891{
1892 struct sdhci_host *host = mmc_priv(mmc);
1893 unsigned long flags;
1894
1895 if (enable)
1896 pm_runtime_get_noresume(host->mmc->parent);
1897
1898 spin_lock_irqsave(&host->lock, flags);
1899 if (enable)
1900 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1901 else
1902 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1903
1904 sdhci_enable_sdio_irq_nolock(host, enable);
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 if (!enable)
1908 pm_runtime_put_noidle(host->mmc->parent);
1909}
1910EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
1911
1912int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1913 struct mmc_ios *ios)
1914{
1915 struct sdhci_host *host = mmc_priv(mmc);
1916 u16 ctrl;
1917 int ret;
1918
1919 /*
1920 * Signal Voltage Switching is only applicable for Host Controllers
1921 * v3.00 and above.
1922 */
1923 if (host->version < SDHCI_SPEC_300)
1924 return 0;
1925
1926 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927
1928 switch (ios->signal_voltage) {
1929 case MMC_SIGNAL_VOLTAGE_330:
1930 if (!(host->flags & SDHCI_SIGNALING_330))
1931 return -EINVAL;
1932 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1933 ctrl &= ~SDHCI_CTRL_VDD_180;
1934 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1935
1936 if (!IS_ERR(mmc->supply.vqmmc)) {
1937 ret = mmc_regulator_set_vqmmc(mmc, ios);
1938 if (ret) {
1939 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1940 mmc_hostname(mmc));
1941 return -EIO;
1942 }
1943 }
1944 /* Wait for 5ms */
1945 usleep_range(5000, 5500);
1946
1947 /* 3.3V regulator output should be stable within 5 ms */
1948 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1949 if (!(ctrl & SDHCI_CTRL_VDD_180))
1950 return 0;
1951
1952 pr_warn("%s: 3.3V regulator output did not became stable\n",
1953 mmc_hostname(mmc));
1954
1955 return -EAGAIN;
1956 case MMC_SIGNAL_VOLTAGE_180:
1957 if (!(host->flags & SDHCI_SIGNALING_180))
1958 return -EINVAL;
1959 if (!IS_ERR(mmc->supply.vqmmc)) {
1960 ret = mmc_regulator_set_vqmmc(mmc, ios);
1961 if (ret) {
1962 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1963 mmc_hostname(mmc));
1964 return -EIO;
1965 }
1966 }
1967
1968 /*
1969 * Enable 1.8V Signal Enable in the Host Control2
1970 * register
1971 */
1972 ctrl |= SDHCI_CTRL_VDD_180;
1973 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1974
1975 /* Some controller need to do more when switching */
1976 if (host->ops->voltage_switch)
1977 host->ops->voltage_switch(host);
1978
1979 /* 1.8V regulator output should be stable within 5 ms */
1980 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1981 if (ctrl & SDHCI_CTRL_VDD_180)
1982 return 0;
1983
1984 pr_warn("%s: 1.8V regulator output did not became stable\n",
1985 mmc_hostname(mmc));
1986
1987 return -EAGAIN;
1988 case MMC_SIGNAL_VOLTAGE_120:
1989 if (!(host->flags & SDHCI_SIGNALING_120))
1990 return -EINVAL;
1991 if (!IS_ERR(mmc->supply.vqmmc)) {
1992 ret = mmc_regulator_set_vqmmc(mmc, ios);
1993 if (ret) {
1994 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1995 mmc_hostname(mmc));
1996 return -EIO;
1997 }
1998 }
1999 return 0;
2000 default:
2001 /* No signal voltage switch required */
2002 return 0;
2003 }
2004}
2005EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2006
2007static int sdhci_card_busy(struct mmc_host *mmc)
2008{
2009 struct sdhci_host *host = mmc_priv(mmc);
2010 u32 present_state;
2011
2012 /* Check whether DAT[0] is 0 */
2013 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2014
2015 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2016}
2017
2018static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2019{
2020 struct sdhci_host *host = mmc_priv(mmc);
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&host->lock, flags);
2024 host->flags |= SDHCI_HS400_TUNING;
2025 spin_unlock_irqrestore(&host->lock, flags);
2026
2027 return 0;
2028}
2029
2030static void sdhci_start_tuning(struct sdhci_host *host)
2031{
2032 u16 ctrl;
2033
2034 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2036 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2037 ctrl |= SDHCI_CTRL_TUNED_CLK;
2038 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2039
2040 /*
2041 * As per the Host Controller spec v3.00, tuning command
2042 * generates Buffer Read Ready interrupt, so enable that.
2043 *
2044 * Note: The spec clearly says that when tuning sequence
2045 * is being performed, the controller does not generate
2046 * interrupts other than Buffer Read Ready interrupt. But
2047 * to make sure we don't hit a controller bug, we _only_
2048 * enable Buffer Read Ready interrupt here.
2049 */
2050 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2051 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2052}
2053
2054static void sdhci_end_tuning(struct sdhci_host *host)
2055{
2056 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2057 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2058}
2059
2060static void sdhci_reset_tuning(struct sdhci_host *host)
2061{
2062 u16 ctrl;
2063
2064 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068}
2069
2070static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2071{
2072 sdhci_reset_tuning(host);
2073
2074 sdhci_do_reset(host, SDHCI_RESET_CMD);
2075 sdhci_do_reset(host, SDHCI_RESET_DATA);
2076
2077 sdhci_end_tuning(host);
2078
2079 mmc_abort_tuning(host->mmc, opcode);
2080}
2081
2082/*
2083 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2084 * tuning command does not have a data payload (or rather the hardware does it
2085 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2086 * interrupt setup is different to other commands and there is no timeout
2087 * interrupt so special handling is needed.
2088 */
2089static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2090{
2091 struct mmc_host *mmc = host->mmc;
2092 struct mmc_command cmd = {};
2093 struct mmc_request mrq = {};
2094 unsigned long flags;
2095 u32 b = host->sdma_boundary;
2096
2097 spin_lock_irqsave(&host->lock, flags);
2098
2099 cmd.opcode = opcode;
2100 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2101 cmd.mrq = &mrq;
2102
2103 mrq.cmd = &cmd;
2104 /*
2105 * In response to CMD19, the card sends 64 bytes of tuning
2106 * block to the Host Controller. So we set the block size
2107 * to 64 here.
2108 */
2109 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2110 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2111 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2112 else
2113 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2114
2115 /*
2116 * The tuning block is sent by the card to the host controller.
2117 * So we set the TRNS_READ bit in the Transfer Mode register.
2118 * This also takes care of setting DMA Enable and Multi Block
2119 * Select in the same register to 0.
2120 */
2121 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2122
2123 sdhci_send_command(host, &cmd);
2124
2125 host->cmd = NULL;
2126
2127 sdhci_del_timer(host, &mrq);
2128
2129 host->tuning_done = 0;
2130
2131 mmiowb();
2132 spin_unlock_irqrestore(&host->lock, flags);
2133
2134 /* Wait for Buffer Read Ready interrupt */
2135 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2136 msecs_to_jiffies(50));
2137
2138}
2139
2140static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2141{
2142 int i;
2143
2144 /*
2145 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2146 * of loops reaches 40 times.
2147 */
2148 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2149 u16 ctrl;
2150
2151 sdhci_send_tuning(host, opcode);
2152
2153 if (!host->tuning_done) {
2154 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2155 mmc_hostname(host->mmc));
2156 sdhci_abort_tuning(host, opcode);
2157 return;
2158 }
2159
2160 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2161 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2162 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2163 return; /* Success! */
2164 break;
2165 }
2166
2167 /* Spec does not require a delay between tuning cycles */
2168 if (host->tuning_delay > 0)
2169 mdelay(host->tuning_delay);
2170 }
2171
2172 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2173 mmc_hostname(host->mmc));
2174 sdhci_reset_tuning(host);
2175}
2176
2177int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2178{
2179 struct sdhci_host *host = mmc_priv(mmc);
2180 int err = 0;
2181 unsigned int tuning_count = 0;
2182 bool hs400_tuning;
2183
2184 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2185
2186 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2187 tuning_count = host->tuning_count;
2188
2189 /*
2190 * The Host Controller needs tuning in case of SDR104 and DDR50
2191 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2192 * the Capabilities register.
2193 * If the Host Controller supports the HS200 mode then the
2194 * tuning function has to be executed.
2195 */
2196 switch (host->timing) {
2197 /* HS400 tuning is done in HS200 mode */
2198 case MMC_TIMING_MMC_HS400:
2199 err = -EINVAL;
2200 goto out;
2201
2202 case MMC_TIMING_MMC_HS200:
2203 /*
2204 * Periodic re-tuning for HS400 is not expected to be needed, so
2205 * disable it here.
2206 */
2207 if (hs400_tuning)
2208 tuning_count = 0;
2209 break;
2210
2211 case MMC_TIMING_UHS_SDR104:
2212 case MMC_TIMING_UHS_DDR50:
2213 break;
2214
2215 case MMC_TIMING_UHS_SDR50:
2216 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2217 break;
2218 /* FALLTHROUGH */
2219
2220 default:
2221 goto out;
2222 }
2223
2224 if (host->ops->platform_execute_tuning) {
2225 err = host->ops->platform_execute_tuning(host, opcode);
2226 goto out;
2227 }
2228
2229 host->mmc->retune_period = tuning_count;
2230
2231 if (host->tuning_delay < 0)
2232 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2233
2234 sdhci_start_tuning(host);
2235
2236 __sdhci_execute_tuning(host, opcode);
2237
2238 sdhci_end_tuning(host);
2239out:
2240 host->flags &= ~SDHCI_HS400_TUNING;
2241
2242 return err;
2243}
2244EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2245
2246static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2247{
2248 /* Host Controller v3.00 defines preset value registers */
2249 if (host->version < SDHCI_SPEC_300)
2250 return;
2251
2252 /*
2253 * We only enable or disable Preset Value if they are not already
2254 * enabled or disabled respectively. Otherwise, we bail out.
2255 */
2256 if (host->preset_enabled != enable) {
2257 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2258
2259 if (enable)
2260 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2261 else
2262 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2263
2264 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2265
2266 if (enable)
2267 host->flags |= SDHCI_PV_ENABLED;
2268 else
2269 host->flags &= ~SDHCI_PV_ENABLED;
2270
2271 host->preset_enabled = enable;
2272 }
2273}
2274
2275static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2276 int err)
2277{
2278 struct sdhci_host *host = mmc_priv(mmc);
2279 struct mmc_data *data = mrq->data;
2280
2281 if (data->host_cookie != COOKIE_UNMAPPED)
2282 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2283 mmc_get_dma_dir(data));
2284
2285 data->host_cookie = COOKIE_UNMAPPED;
2286}
2287
2288static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2289{
2290 struct sdhci_host *host = mmc_priv(mmc);
2291
2292 mrq->data->host_cookie = COOKIE_UNMAPPED;
2293
2294 /*
2295 * No pre-mapping in the pre hook if we're using the bounce buffer,
2296 * for that we would need two bounce buffers since one buffer is
2297 * in flight when this is getting called.
2298 */
2299 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2300 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2301}
2302
2303static inline bool sdhci_has_requests(struct sdhci_host *host)
2304{
2305 return host->cmd || host->data_cmd;
2306}
2307
2308static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2309{
2310 if (host->data_cmd) {
2311 host->data_cmd->error = err;
2312 sdhci_finish_mrq(host, host->data_cmd->mrq);
2313 }
2314
2315 if (host->cmd) {
2316 host->cmd->error = err;
2317 sdhci_finish_mrq(host, host->cmd->mrq);
2318 }
2319}
2320
2321static void sdhci_card_event(struct mmc_host *mmc)
2322{
2323 struct sdhci_host *host = mmc_priv(mmc);
2324 unsigned long flags;
2325 int present;
2326
2327 /* First check if client has provided their own card event */
2328 if (host->ops->card_event)
2329 host->ops->card_event(host);
2330
2331 present = mmc->ops->get_cd(mmc);
2332
2333 spin_lock_irqsave(&host->lock, flags);
2334
2335 /* Check sdhci_has_requests() first in case we are runtime suspended */
2336 if (sdhci_has_requests(host) && !present) {
2337 pr_err("%s: Card removed during transfer!\n",
2338 mmc_hostname(host->mmc));
2339 pr_err("%s: Resetting controller.\n",
2340 mmc_hostname(host->mmc));
2341
2342 sdhci_do_reset(host, SDHCI_RESET_CMD);
2343 sdhci_do_reset(host, SDHCI_RESET_DATA);
2344
2345 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2346 }
2347
2348 spin_unlock_irqrestore(&host->lock, flags);
2349}
2350
2351static const struct mmc_host_ops sdhci_ops = {
2352 .request = sdhci_request,
2353 .post_req = sdhci_post_req,
2354 .pre_req = sdhci_pre_req,
2355 .set_ios = sdhci_set_ios,
2356 .get_cd = sdhci_get_cd,
2357 .get_ro = sdhci_get_ro,
2358 .hw_reset = sdhci_hw_reset,
2359 .enable_sdio_irq = sdhci_enable_sdio_irq,
2360 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2361 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2362 .execute_tuning = sdhci_execute_tuning,
2363 .card_event = sdhci_card_event,
2364 .card_busy = sdhci_card_busy,
2365};
2366
2367/*****************************************************************************\
2368 * *
2369 * Tasklets *
2370 * *
2371\*****************************************************************************/
2372
2373static bool sdhci_request_done(struct sdhci_host *host)
2374{
2375 unsigned long flags;
2376 struct mmc_request *mrq;
2377 int i;
2378
2379 spin_lock_irqsave(&host->lock, flags);
2380
2381 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2382 mrq = host->mrqs_done[i];
2383 if (mrq)
2384 break;
2385 }
2386
2387 if (!mrq) {
2388 spin_unlock_irqrestore(&host->lock, flags);
2389 return true;
2390 }
2391
2392 sdhci_del_timer(host, mrq);
2393
2394 /*
2395 * Always unmap the data buffers if they were mapped by
2396 * sdhci_prepare_data() whenever we finish with a request.
2397 * This avoids leaking DMA mappings on error.
2398 */
2399 if (host->flags & SDHCI_REQ_USE_DMA) {
2400 struct mmc_data *data = mrq->data;
2401
2402 if (data && data->host_cookie == COOKIE_MAPPED) {
2403 if (host->bounce_buffer) {
2404 /*
2405 * On reads, copy the bounced data into the
2406 * sglist
2407 */
2408 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2409 unsigned int length = data->bytes_xfered;
2410
2411 if (length > host->bounce_buffer_size) {
2412 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2413 mmc_hostname(host->mmc),
2414 host->bounce_buffer_size,
2415 data->bytes_xfered);
2416 /* Cap it down and continue */
2417 length = host->bounce_buffer_size;
2418 }
2419 dma_sync_single_for_cpu(
2420 host->mmc->parent,
2421 host->bounce_addr,
2422 host->bounce_buffer_size,
2423 DMA_FROM_DEVICE);
2424 sg_copy_from_buffer(data->sg,
2425 data->sg_len,
2426 host->bounce_buffer,
2427 length);
2428 } else {
2429 /* No copying, just switch ownership */
2430 dma_sync_single_for_cpu(
2431 host->mmc->parent,
2432 host->bounce_addr,
2433 host->bounce_buffer_size,
2434 mmc_get_dma_dir(data));
2435 }
2436 } else {
2437 /* Unmap the raw data */
2438 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2439 data->sg_len,
2440 mmc_get_dma_dir(data));
2441 }
2442 data->host_cookie = COOKIE_UNMAPPED;
2443 }
2444 }
2445
2446 /*
2447 * The controller needs a reset of internal state machines
2448 * upon error conditions.
2449 */
2450 if (sdhci_needs_reset(host, mrq)) {
2451 /*
2452 * Do not finish until command and data lines are available for
2453 * reset. Note there can only be one other mrq, so it cannot
2454 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2455 * would both be null.
2456 */
2457 if (host->cmd || host->data_cmd) {
2458 spin_unlock_irqrestore(&host->lock, flags);
2459 return true;
2460 }
2461
2462 /* Some controllers need this kick or reset won't work here */
2463 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2464 /* This is to force an update */
2465 host->ops->set_clock(host, host->clock);
2466
2467 /* Spec says we should do both at the same time, but Ricoh
2468 controllers do not like that. */
2469 sdhci_do_reset(host, SDHCI_RESET_CMD);
2470 sdhci_do_reset(host, SDHCI_RESET_DATA);
2471
2472 host->pending_reset = false;
2473 }
2474
2475 if (!sdhci_has_requests(host))
2476 sdhci_led_deactivate(host);
2477
2478 host->mrqs_done[i] = NULL;
2479
2480 mmiowb();
2481 spin_unlock_irqrestore(&host->lock, flags);
2482
2483 mmc_request_done(host->mmc, mrq);
2484
2485 return false;
2486}
2487
2488static void sdhci_tasklet_finish(unsigned long param)
2489{
2490 struct sdhci_host *host = (struct sdhci_host *)param;
2491
2492 while (!sdhci_request_done(host))
2493 ;
2494}
2495
2496static void sdhci_timeout_timer(struct timer_list *t)
2497{
2498 struct sdhci_host *host;
2499 unsigned long flags;
2500
2501 host = from_timer(host, t, timer);
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2506 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2507 mmc_hostname(host->mmc));
2508 sdhci_dumpregs(host);
2509
2510 host->cmd->error = -ETIMEDOUT;
2511 sdhci_finish_mrq(host, host->cmd->mrq);
2512 }
2513
2514 mmiowb();
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518static void sdhci_timeout_data_timer(struct timer_list *t)
2519{
2520 struct sdhci_host *host;
2521 unsigned long flags;
2522
2523 host = from_timer(host, t, data_timer);
2524
2525 spin_lock_irqsave(&host->lock, flags);
2526
2527 if (host->data || host->data_cmd ||
2528 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2529 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2530 mmc_hostname(host->mmc));
2531 sdhci_dumpregs(host);
2532
2533 if (host->data) {
2534 host->data->error = -ETIMEDOUT;
2535 sdhci_finish_data(host);
2536 } else if (host->data_cmd) {
2537 host->data_cmd->error = -ETIMEDOUT;
2538 sdhci_finish_mrq(host, host->data_cmd->mrq);
2539 } else {
2540 host->cmd->error = -ETIMEDOUT;
2541 sdhci_finish_mrq(host, host->cmd->mrq);
2542 }
2543 }
2544
2545 mmiowb();
2546 spin_unlock_irqrestore(&host->lock, flags);
2547}
2548
2549/*****************************************************************************\
2550 * *
2551 * Interrupt handling *
2552 * *
2553\*****************************************************************************/
2554
2555static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2556{
2557 if (!host->cmd) {
2558 /*
2559 * SDHCI recovers from errors by resetting the cmd and data
2560 * circuits. Until that is done, there very well might be more
2561 * interrupts, so ignore them in that case.
2562 */
2563 if (host->pending_reset)
2564 return;
2565 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2566 mmc_hostname(host->mmc), (unsigned)intmask);
2567 sdhci_dumpregs(host);
2568 return;
2569 }
2570
2571 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2572 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2573 if (intmask & SDHCI_INT_TIMEOUT)
2574 host->cmd->error = -ETIMEDOUT;
2575 else
2576 host->cmd->error = -EILSEQ;
2577
2578 /*
2579 * If this command initiates a data phase and a response
2580 * CRC error is signalled, the card can start transferring
2581 * data - the card may have received the command without
2582 * error. We must not terminate the mmc_request early.
2583 *
2584 * If the card did not receive the command or returned an
2585 * error which prevented it sending data, the data phase
2586 * will time out.
2587 */
2588 if (host->cmd->data &&
2589 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2590 SDHCI_INT_CRC) {
2591 host->cmd = NULL;
2592 return;
2593 }
2594
2595 sdhci_finish_mrq(host, host->cmd->mrq);
2596 return;
2597 }
2598
2599 if (intmask & SDHCI_INT_RESPONSE)
2600 sdhci_finish_command(host);
2601}
2602
2603static void sdhci_adma_show_error(struct sdhci_host *host)
2604{
2605 void *desc = host->adma_table;
2606
2607 sdhci_dumpregs(host);
2608
2609 while (true) {
2610 struct sdhci_adma2_64_desc *dma_desc = desc;
2611
2612 if (host->flags & SDHCI_USE_64_BIT_DMA)
2613 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2614 desc, le32_to_cpu(dma_desc->addr_hi),
2615 le32_to_cpu(dma_desc->addr_lo),
2616 le16_to_cpu(dma_desc->len),
2617 le16_to_cpu(dma_desc->cmd));
2618 else
2619 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2620 desc, le32_to_cpu(dma_desc->addr_lo),
2621 le16_to_cpu(dma_desc->len),
2622 le16_to_cpu(dma_desc->cmd));
2623
2624 desc += host->desc_sz;
2625
2626 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2627 break;
2628 }
2629}
2630
2631static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2632{
2633 u32 command;
2634
2635 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2636 if (intmask & SDHCI_INT_DATA_AVAIL) {
2637 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2638 if (command == MMC_SEND_TUNING_BLOCK ||
2639 command == MMC_SEND_TUNING_BLOCK_HS200) {
2640 host->tuning_done = 1;
2641 wake_up(&host->buf_ready_int);
2642 return;
2643 }
2644 }
2645
2646 if (!host->data) {
2647 struct mmc_command *data_cmd = host->data_cmd;
2648
2649 /*
2650 * The "data complete" interrupt is also used to
2651 * indicate that a busy state has ended. See comment
2652 * above in sdhci_cmd_irq().
2653 */
2654 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2655 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2656 host->data_cmd = NULL;
2657 data_cmd->error = -ETIMEDOUT;
2658 sdhci_finish_mrq(host, data_cmd->mrq);
2659 return;
2660 }
2661 if (intmask & SDHCI_INT_DATA_END) {
2662 host->data_cmd = NULL;
2663 /*
2664 * Some cards handle busy-end interrupt
2665 * before the command completed, so make
2666 * sure we do things in the proper order.
2667 */
2668 if (host->cmd == data_cmd)
2669 return;
2670
2671 sdhci_finish_mrq(host, data_cmd->mrq);
2672 return;
2673 }
2674 }
2675
2676 /*
2677 * SDHCI recovers from errors by resetting the cmd and data
2678 * circuits. Until that is done, there very well might be more
2679 * interrupts, so ignore them in that case.
2680 */
2681 if (host->pending_reset)
2682 return;
2683
2684 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2685 mmc_hostname(host->mmc), (unsigned)intmask);
2686 sdhci_dumpregs(host);
2687
2688 return;
2689 }
2690
2691 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2692 host->data->error = -ETIMEDOUT;
2693 else if (intmask & SDHCI_INT_DATA_END_BIT)
2694 host->data->error = -EILSEQ;
2695 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2696 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2697 != MMC_BUS_TEST_R)
2698 host->data->error = -EILSEQ;
2699 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2700 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2701 sdhci_adma_show_error(host);
2702 host->data->error = -EIO;
2703 if (host->ops->adma_workaround)
2704 host->ops->adma_workaround(host, intmask);
2705 }
2706
2707 if (host->data->error)
2708 sdhci_finish_data(host);
2709 else {
2710 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2711 sdhci_transfer_pio(host);
2712
2713 /*
2714 * We currently don't do anything fancy with DMA
2715 * boundaries, but as we can't disable the feature
2716 * we need to at least restart the transfer.
2717 *
2718 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2719 * should return a valid address to continue from, but as
2720 * some controllers are faulty, don't trust them.
2721 */
2722 if (intmask & SDHCI_INT_DMA_END) {
2723 u32 dmastart, dmanow;
2724
2725 dmastart = sdhci_sdma_address(host);
2726 dmanow = dmastart + host->data->bytes_xfered;
2727 /*
2728 * Force update to the next DMA block boundary.
2729 */
2730 dmanow = (dmanow &
2731 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2732 SDHCI_DEFAULT_BOUNDARY_SIZE;
2733 host->data->bytes_xfered = dmanow - dmastart;
2734 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2735 dmastart, host->data->bytes_xfered, dmanow);
2736 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2737 }
2738
2739 if (intmask & SDHCI_INT_DATA_END) {
2740 if (host->cmd == host->data_cmd) {
2741 /*
2742 * Data managed to finish before the
2743 * command completed. Make sure we do
2744 * things in the proper order.
2745 */
2746 host->data_early = 1;
2747 } else {
2748 sdhci_finish_data(host);
2749 }
2750 }
2751 }
2752}
2753
2754static irqreturn_t sdhci_irq(int irq, void *dev_id)
2755{
2756 irqreturn_t result = IRQ_NONE;
2757 struct sdhci_host *host = dev_id;
2758 u32 intmask, mask, unexpected = 0;
2759 int max_loops = 16;
2760
2761 spin_lock(&host->lock);
2762
2763 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2764 spin_unlock(&host->lock);
2765 return IRQ_NONE;
2766 }
2767
2768 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2769 if (!intmask || intmask == 0xffffffff) {
2770 result = IRQ_NONE;
2771 goto out;
2772 }
2773
2774 do {
2775 DBG("IRQ status 0x%08x\n", intmask);
2776
2777 if (host->ops->irq) {
2778 intmask = host->ops->irq(host, intmask);
2779 if (!intmask)
2780 goto cont;
2781 }
2782
2783 /* Clear selected interrupts. */
2784 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2785 SDHCI_INT_BUS_POWER);
2786 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2787
2788 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2789 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2790 SDHCI_CARD_PRESENT;
2791
2792 /*
2793 * There is a observation on i.mx esdhc. INSERT
2794 * bit will be immediately set again when it gets
2795 * cleared, if a card is inserted. We have to mask
2796 * the irq to prevent interrupt storm which will
2797 * freeze the system. And the REMOVE gets the
2798 * same situation.
2799 *
2800 * More testing are needed here to ensure it works
2801 * for other platforms though.
2802 */
2803 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2804 SDHCI_INT_CARD_REMOVE);
2805 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2806 SDHCI_INT_CARD_INSERT;
2807 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2808 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2809
2810 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2811 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2812
2813 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2814 SDHCI_INT_CARD_REMOVE);
2815 result = IRQ_WAKE_THREAD;
2816 }
2817
2818 if (intmask & SDHCI_INT_CMD_MASK)
2819 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2820
2821 if (intmask & SDHCI_INT_DATA_MASK)
2822 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2823
2824 if (intmask & SDHCI_INT_BUS_POWER)
2825 pr_err("%s: Card is consuming too much power!\n",
2826 mmc_hostname(host->mmc));
2827
2828 if (intmask & SDHCI_INT_RETUNE)
2829 mmc_retune_needed(host->mmc);
2830
2831 if ((intmask & SDHCI_INT_CARD_INT) &&
2832 (host->ier & SDHCI_INT_CARD_INT)) {
2833 sdhci_enable_sdio_irq_nolock(host, false);
2834 host->thread_isr |= SDHCI_INT_CARD_INT;
2835 result = IRQ_WAKE_THREAD;
2836 }
2837
2838 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2839 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2840 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2841 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2842
2843 if (intmask) {
2844 unexpected |= intmask;
2845 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2846 }
2847cont:
2848 if (result == IRQ_NONE)
2849 result = IRQ_HANDLED;
2850
2851 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2852 } while (intmask && --max_loops);
2853out:
2854 spin_unlock(&host->lock);
2855
2856 if (unexpected) {
2857 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2858 mmc_hostname(host->mmc), unexpected);
2859 sdhci_dumpregs(host);
2860 }
2861
2862 return result;
2863}
2864
2865static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2866{
2867 struct sdhci_host *host = dev_id;
2868 unsigned long flags;
2869 u32 isr;
2870
2871 spin_lock_irqsave(&host->lock, flags);
2872 isr = host->thread_isr;
2873 host->thread_isr = 0;
2874 spin_unlock_irqrestore(&host->lock, flags);
2875
2876 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2877 struct mmc_host *mmc = host->mmc;
2878
2879 mmc->ops->card_event(mmc);
2880 mmc_detect_change(mmc, msecs_to_jiffies(200));
2881 }
2882
2883 if (isr & SDHCI_INT_CARD_INT) {
2884 sdio_run_irqs(host->mmc);
2885
2886 spin_lock_irqsave(&host->lock, flags);
2887 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2888 sdhci_enable_sdio_irq_nolock(host, true);
2889 spin_unlock_irqrestore(&host->lock, flags);
2890 }
2891
2892 return isr ? IRQ_HANDLED : IRQ_NONE;
2893}
2894
2895/*****************************************************************************\
2896 * *
2897 * Suspend/resume *
2898 * *
2899\*****************************************************************************/
2900
2901#ifdef CONFIG_PM
2902
2903static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
2904{
2905 return mmc_card_is_removable(host->mmc) &&
2906 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2907 !mmc_can_gpio_cd(host->mmc);
2908}
2909
2910/*
2911 * To enable wakeup events, the corresponding events have to be enabled in
2912 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2913 * Table' in the SD Host Controller Standard Specification.
2914 * It is useless to restore SDHCI_INT_ENABLE state in
2915 * sdhci_disable_irq_wakeups() since it will be set by
2916 * sdhci_enable_card_detection() or sdhci_init().
2917 */
2918static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
2919{
2920 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
2921 SDHCI_WAKE_ON_INT;
2922 u32 irq_val = 0;
2923 u8 wake_val = 0;
2924 u8 val;
2925
2926 if (sdhci_cd_irq_can_wakeup(host)) {
2927 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
2928 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
2929 }
2930
2931 if (mmc_card_wake_sdio_irq(host->mmc)) {
2932 wake_val |= SDHCI_WAKE_ON_INT;
2933 irq_val |= SDHCI_INT_CARD_INT;
2934 }
2935
2936 if (!irq_val)
2937 return false;
2938
2939 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2940 val &= ~mask;
2941 val |= wake_val;
2942 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2943
2944 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2945
2946 host->irq_wake_enabled = !enable_irq_wake(host->irq);
2947
2948 return host->irq_wake_enabled;
2949}
2950
2951static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2952{
2953 u8 val;
2954 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2955 | SDHCI_WAKE_ON_INT;
2956
2957 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2958 val &= ~mask;
2959 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2960
2961 disable_irq_wake(host->irq);
2962
2963 host->irq_wake_enabled = false;
2964}
2965
2966int sdhci_suspend_host(struct sdhci_host *host)
2967{
2968 sdhci_disable_card_detection(host);
2969
2970 mmc_retune_timer_stop(host->mmc);
2971
2972 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
2973 !sdhci_enable_irq_wakeups(host)) {
2974 host->ier = 0;
2975 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2976 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2977 free_irq(host->irq, host);
2978 }
2979
2980 return 0;
2981}
2982
2983EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2984
2985int sdhci_resume_host(struct sdhci_host *host)
2986{
2987 struct mmc_host *mmc = host->mmc;
2988 int ret = 0;
2989
2990 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2991 if (host->ops->enable_dma)
2992 host->ops->enable_dma(host);
2993 }
2994
2995 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2996 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2997 /* Card keeps power but host controller does not */
2998 sdhci_init(host, 0);
2999 host->pwr = 0;
3000 host->clock = 0;
3001 mmc->ops->set_ios(mmc, &mmc->ios);
3002 } else {
3003 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3004 mmiowb();
3005 }
3006
3007 if (host->irq_wake_enabled) {
3008 sdhci_disable_irq_wakeups(host);
3009 } else {
3010 ret = request_threaded_irq(host->irq, sdhci_irq,
3011 sdhci_thread_irq, IRQF_SHARED,
3012 mmc_hostname(host->mmc), host);
3013 if (ret)
3014 return ret;
3015 }
3016
3017 sdhci_enable_card_detection(host);
3018
3019 return ret;
3020}
3021
3022EXPORT_SYMBOL_GPL(sdhci_resume_host);
3023
3024int sdhci_runtime_suspend_host(struct sdhci_host *host)
3025{
3026 unsigned long flags;
3027
3028 mmc_retune_timer_stop(host->mmc);
3029
3030 spin_lock_irqsave(&host->lock, flags);
3031 host->ier &= SDHCI_INT_CARD_INT;
3032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3034 spin_unlock_irqrestore(&host->lock, flags);
3035
3036 synchronize_hardirq(host->irq);
3037
3038 spin_lock_irqsave(&host->lock, flags);
3039 host->runtime_suspended = true;
3040 spin_unlock_irqrestore(&host->lock, flags);
3041
3042 return 0;
3043}
3044EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3045
3046int sdhci_runtime_resume_host(struct sdhci_host *host)
3047{
3048 struct mmc_host *mmc = host->mmc;
3049 unsigned long flags;
3050 int host_flags = host->flags;
3051
3052 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3053 if (host->ops->enable_dma)
3054 host->ops->enable_dma(host);
3055 }
3056
3057 sdhci_init(host, 0);
3058
3059 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3060 mmc->ios.power_mode != MMC_POWER_OFF) {
3061 /* Force clock and power re-program */
3062 host->pwr = 0;
3063 host->clock = 0;
3064 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3065 mmc->ops->set_ios(mmc, &mmc->ios);
3066
3067 if ((host_flags & SDHCI_PV_ENABLED) &&
3068 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3069 spin_lock_irqsave(&host->lock, flags);
3070 sdhci_enable_preset_value(host, true);
3071 spin_unlock_irqrestore(&host->lock, flags);
3072 }
3073
3074 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3075 mmc->ops->hs400_enhanced_strobe)
3076 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3077 }
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 host->runtime_suspended = false;
3082
3083 /* Enable SDIO IRQ */
3084 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3085 sdhci_enable_sdio_irq_nolock(host, true);
3086
3087 /* Enable Card Detection */
3088 sdhci_enable_card_detection(host);
3089
3090 spin_unlock_irqrestore(&host->lock, flags);
3091
3092 return 0;
3093}
3094EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3095
3096#endif /* CONFIG_PM */
3097
3098/*****************************************************************************\
3099 * *
3100 * Command Queue Engine (CQE) helpers *
3101 * *
3102\*****************************************************************************/
3103
3104void sdhci_cqe_enable(struct mmc_host *mmc)
3105{
3106 struct sdhci_host *host = mmc_priv(mmc);
3107 unsigned long flags;
3108 u8 ctrl;
3109
3110 spin_lock_irqsave(&host->lock, flags);
3111
3112 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3113 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3114 if (host->flags & SDHCI_USE_64_BIT_DMA)
3115 ctrl |= SDHCI_CTRL_ADMA64;
3116 else
3117 ctrl |= SDHCI_CTRL_ADMA32;
3118 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3119
3120 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3121 SDHCI_BLOCK_SIZE);
3122
3123 /* Set maximum timeout */
3124 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3125
3126 host->ier = host->cqe_ier;
3127
3128 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3129 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3130
3131 host->cqe_on = true;
3132
3133 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3134 mmc_hostname(mmc), host->ier,
3135 sdhci_readl(host, SDHCI_INT_STATUS));
3136
3137 mmiowb();
3138 spin_unlock_irqrestore(&host->lock, flags);
3139}
3140EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3141
3142void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3143{
3144 struct sdhci_host *host = mmc_priv(mmc);
3145 unsigned long flags;
3146
3147 spin_lock_irqsave(&host->lock, flags);
3148
3149 sdhci_set_default_irqs(host);
3150
3151 host->cqe_on = false;
3152
3153 if (recovery) {
3154 sdhci_do_reset(host, SDHCI_RESET_CMD);
3155 sdhci_do_reset(host, SDHCI_RESET_DATA);
3156 }
3157
3158 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3159 mmc_hostname(mmc), host->ier,
3160 sdhci_readl(host, SDHCI_INT_STATUS));
3161
3162 mmiowb();
3163 spin_unlock_irqrestore(&host->lock, flags);
3164}
3165EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3166
3167bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3168 int *data_error)
3169{
3170 u32 mask;
3171
3172 if (!host->cqe_on)
3173 return false;
3174
3175 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3176 *cmd_error = -EILSEQ;
3177 else if (intmask & SDHCI_INT_TIMEOUT)
3178 *cmd_error = -ETIMEDOUT;
3179 else
3180 *cmd_error = 0;
3181
3182 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3183 *data_error = -EILSEQ;
3184 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3185 *data_error = -ETIMEDOUT;
3186 else if (intmask & SDHCI_INT_ADMA_ERROR)
3187 *data_error = -EIO;
3188 else
3189 *data_error = 0;
3190
3191 /* Clear selected interrupts. */
3192 mask = intmask & host->cqe_ier;
3193 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3194
3195 if (intmask & SDHCI_INT_BUS_POWER)
3196 pr_err("%s: Card is consuming too much power!\n",
3197 mmc_hostname(host->mmc));
3198
3199 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3200 if (intmask) {
3201 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3202 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3203 mmc_hostname(host->mmc), intmask);
3204 sdhci_dumpregs(host);
3205 }
3206
3207 return true;
3208}
3209EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3210
3211/*****************************************************************************\
3212 * *
3213 * Device allocation/registration *
3214 * *
3215\*****************************************************************************/
3216
3217struct sdhci_host *sdhci_alloc_host(struct device *dev,
3218 size_t priv_size)
3219{
3220 struct mmc_host *mmc;
3221 struct sdhci_host *host;
3222
3223 WARN_ON(dev == NULL);
3224
3225 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3226 if (!mmc)
3227 return ERR_PTR(-ENOMEM);
3228
3229 host = mmc_priv(mmc);
3230 host->mmc = mmc;
3231 host->mmc_host_ops = sdhci_ops;
3232 mmc->ops = &host->mmc_host_ops;
3233
3234 host->flags = SDHCI_SIGNALING_330;
3235
3236 host->cqe_ier = SDHCI_CQE_INT_MASK;
3237 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3238
3239 host->tuning_delay = -1;
3240
3241 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3242
3243 return host;
3244}
3245
3246EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3247
3248static int sdhci_set_dma_mask(struct sdhci_host *host)
3249{
3250 struct mmc_host *mmc = host->mmc;
3251 struct device *dev = mmc_dev(mmc);
3252 int ret = -EINVAL;
3253
3254 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3255 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3256
3257 /* Try 64-bit mask if hardware is capable of it */
3258 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3259 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3260 if (ret) {
3261 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3262 mmc_hostname(mmc));
3263 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3264 }
3265 }
3266
3267 /* 32-bit mask as default & fallback */
3268 if (ret) {
3269 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3270 if (ret)
3271 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3272 mmc_hostname(mmc));
3273 }
3274
3275 return ret;
3276}
3277
3278void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3279{
3280 u16 v;
3281 u64 dt_caps_mask = 0;
3282 u64 dt_caps = 0;
3283
3284 if (host->read_caps)
3285 return;
3286
3287 host->read_caps = true;
3288
3289 if (debug_quirks)
3290 host->quirks = debug_quirks;
3291
3292 if (debug_quirks2)
3293 host->quirks2 = debug_quirks2;
3294
3295 sdhci_do_reset(host, SDHCI_RESET_ALL);
3296
3297 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3298 "sdhci-caps-mask", &dt_caps_mask);
3299 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3300 "sdhci-caps", &dt_caps);
3301
3302 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3303 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3304
3305 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3306 return;
3307
3308 if (caps) {
3309 host->caps = *caps;
3310 } else {
3311 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3312 host->caps &= ~lower_32_bits(dt_caps_mask);
3313 host->caps |= lower_32_bits(dt_caps);
3314 }
3315
3316 if (host->version < SDHCI_SPEC_300)
3317 return;
3318
3319 if (caps1) {
3320 host->caps1 = *caps1;
3321 } else {
3322 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3323 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3324 host->caps1 |= upper_32_bits(dt_caps);
3325 }
3326}
3327EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3328
3329static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3330{
3331 struct mmc_host *mmc = host->mmc;
3332 unsigned int max_blocks;
3333 unsigned int bounce_size;
3334 int ret;
3335
3336 /*
3337 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3338 * has diminishing returns, this is probably because SD/MMC
3339 * cards are usually optimized to handle this size of requests.
3340 */
3341 bounce_size = SZ_64K;
3342 /*
3343 * Adjust downwards to maximum request size if this is less
3344 * than our segment size, else hammer down the maximum
3345 * request size to the maximum buffer size.
3346 */
3347 if (mmc->max_req_size < bounce_size)
3348 bounce_size = mmc->max_req_size;
3349 max_blocks = bounce_size / 512;
3350
3351 /*
3352 * When we just support one segment, we can get significant
3353 * speedups by the help of a bounce buffer to group scattered
3354 * reads/writes together.
3355 */
3356 host->bounce_buffer = devm_kmalloc(mmc->parent,
3357 bounce_size,
3358 GFP_KERNEL);
3359 if (!host->bounce_buffer) {
3360 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3361 mmc_hostname(mmc),
3362 bounce_size);
3363 /*
3364 * Exiting with zero here makes sure we proceed with
3365 * mmc->max_segs == 1.
3366 */
3367 return 0;
3368 }
3369
3370 host->bounce_addr = dma_map_single(mmc->parent,
3371 host->bounce_buffer,
3372 bounce_size,
3373 DMA_BIDIRECTIONAL);
3374 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3375 if (ret)
3376 /* Again fall back to max_segs == 1 */
3377 return 0;
3378 host->bounce_buffer_size = bounce_size;
3379
3380 /* Lie about this since we're bouncing */
3381 mmc->max_segs = max_blocks;
3382 mmc->max_seg_size = bounce_size;
3383 mmc->max_req_size = bounce_size;
3384
3385 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3386 mmc_hostname(mmc), max_blocks, bounce_size);
3387
3388 return 0;
3389}
3390
3391int sdhci_setup_host(struct sdhci_host *host)
3392{
3393 struct mmc_host *mmc;
3394 u32 max_current_caps;
3395 unsigned int ocr_avail;
3396 unsigned int override_timeout_clk;
3397 u32 max_clk;
3398 int ret;
3399
3400 WARN_ON(host == NULL);
3401 if (host == NULL)
3402 return -EINVAL;
3403
3404 mmc = host->mmc;
3405
3406 /*
3407 * If there are external regulators, get them. Note this must be done
3408 * early before resetting the host and reading the capabilities so that
3409 * the host can take the appropriate action if regulators are not
3410 * available.
3411 */
3412 ret = mmc_regulator_get_supply(mmc);
3413 if (ret)
3414 return ret;
3415
3416 DBG("Version: 0x%08x | Present: 0x%08x\n",
3417 sdhci_readw(host, SDHCI_HOST_VERSION),
3418 sdhci_readl(host, SDHCI_PRESENT_STATE));
3419 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3420 sdhci_readl(host, SDHCI_CAPABILITIES),
3421 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3422
3423 sdhci_read_caps(host);
3424
3425 override_timeout_clk = host->timeout_clk;
3426
3427 if (host->version > SDHCI_SPEC_300) {
3428 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3429 mmc_hostname(mmc), host->version);
3430 }
3431
3432 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3433 host->flags |= SDHCI_USE_SDMA;
3434 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3435 DBG("Controller doesn't have SDMA capability\n");
3436 else
3437 host->flags |= SDHCI_USE_SDMA;
3438
3439 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3440 (host->flags & SDHCI_USE_SDMA)) {
3441 DBG("Disabling DMA as it is marked broken\n");
3442 host->flags &= ~SDHCI_USE_SDMA;
3443 }
3444
3445 if ((host->version >= SDHCI_SPEC_200) &&
3446 (host->caps & SDHCI_CAN_DO_ADMA2))
3447 host->flags |= SDHCI_USE_ADMA;
3448
3449 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3450 (host->flags & SDHCI_USE_ADMA)) {
3451 DBG("Disabling ADMA as it is marked broken\n");
3452 host->flags &= ~SDHCI_USE_ADMA;
3453 }
3454
3455 /*
3456 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3457 * and *must* do 64-bit DMA. A driver has the opportunity to change
3458 * that during the first call to ->enable_dma(). Similarly
3459 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3460 * implement.
3461 */
3462 if (host->caps & SDHCI_CAN_64BIT)
3463 host->flags |= SDHCI_USE_64_BIT_DMA;
3464
3465 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3466 ret = sdhci_set_dma_mask(host);
3467
3468 if (!ret && host->ops->enable_dma)
3469 ret = host->ops->enable_dma(host);
3470
3471 if (ret) {
3472 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3473 mmc_hostname(mmc));
3474 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3475
3476 ret = 0;
3477 }
3478 }
3479
3480 /* SDMA does not support 64-bit DMA */
3481 if (host->flags & SDHCI_USE_64_BIT_DMA)
3482 host->flags &= ~SDHCI_USE_SDMA;
3483
3484 if (host->flags & SDHCI_USE_ADMA) {
3485 dma_addr_t dma;
3486 void *buf;
3487
3488 /*
3489 * The DMA descriptor table size is calculated as the maximum
3490 * number of segments times 2, to allow for an alignment
3491 * descriptor for each segment, plus 1 for a nop end descriptor,
3492 * all multipled by the descriptor size.
3493 */
3494 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3495 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3496 SDHCI_ADMA2_64_DESC_SZ;
3497 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3498 } else {
3499 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3500 SDHCI_ADMA2_32_DESC_SZ;
3501 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3502 }
3503
3504 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3505 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3506 host->adma_table_sz, &dma, GFP_KERNEL);
3507 if (!buf) {
3508 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3509 mmc_hostname(mmc));
3510 host->flags &= ~SDHCI_USE_ADMA;
3511 } else if ((dma + host->align_buffer_sz) &
3512 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3513 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3514 mmc_hostname(mmc));
3515 host->flags &= ~SDHCI_USE_ADMA;
3516 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3517 host->adma_table_sz, buf, dma);
3518 } else {
3519 host->align_buffer = buf;
3520 host->align_addr = dma;
3521
3522 host->adma_table = buf + host->align_buffer_sz;
3523 host->adma_addr = dma + host->align_buffer_sz;
3524 }
3525 }
3526
3527 /*
3528 * If we use DMA, then it's up to the caller to set the DMA
3529 * mask, but PIO does not need the hw shim so we set a new
3530 * mask here in that case.
3531 */
3532 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3533 host->dma_mask = DMA_BIT_MASK(64);
3534 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3535 }
3536
3537 if (host->version >= SDHCI_SPEC_300)
3538 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3539 >> SDHCI_CLOCK_BASE_SHIFT;
3540 else
3541 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3542 >> SDHCI_CLOCK_BASE_SHIFT;
3543
3544 host->max_clk *= 1000000;
3545 if (host->max_clk == 0 || host->quirks &
3546 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3547 if (!host->ops->get_max_clock) {
3548 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3549 mmc_hostname(mmc));
3550 ret = -ENODEV;
3551 goto undma;
3552 }
3553 host->max_clk = host->ops->get_max_clock(host);
3554 }
3555
3556 /*
3557 * In case of Host Controller v3.00, find out whether clock
3558 * multiplier is supported.
3559 */
3560 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3561 SDHCI_CLOCK_MUL_SHIFT;
3562
3563 /*
3564 * In case the value in Clock Multiplier is 0, then programmable
3565 * clock mode is not supported, otherwise the actual clock
3566 * multiplier is one more than the value of Clock Multiplier
3567 * in the Capabilities Register.
3568 */
3569 if (host->clk_mul)
3570 host->clk_mul += 1;
3571
3572 /*
3573 * Set host parameters.
3574 */
3575 max_clk = host->max_clk;
3576
3577 if (host->ops->get_min_clock)
3578 mmc->f_min = host->ops->get_min_clock(host);
3579 else if (host->version >= SDHCI_SPEC_300) {
3580 if (host->clk_mul) {
3581 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3582 max_clk = host->max_clk * host->clk_mul;
3583 } else
3584 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3585 } else
3586 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3587
3588 if (!mmc->f_max || mmc->f_max > max_clk)
3589 mmc->f_max = max_clk;
3590
3591 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3592 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3593 SDHCI_TIMEOUT_CLK_SHIFT;
3594
3595 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3596 host->timeout_clk *= 1000;
3597
3598 if (host->timeout_clk == 0) {
3599 if (!host->ops->get_timeout_clock) {
3600 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3601 mmc_hostname(mmc));
3602 ret = -ENODEV;
3603 goto undma;
3604 }
3605
3606 host->timeout_clk =
3607 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3608 1000);
3609 }
3610
3611 if (override_timeout_clk)
3612 host->timeout_clk = override_timeout_clk;
3613
3614 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3615 host->ops->get_max_timeout_count(host) : 1 << 27;
3616 mmc->max_busy_timeout /= host->timeout_clk;
3617 }
3618
3619 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3620 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3621
3622 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3623 host->flags |= SDHCI_AUTO_CMD12;
3624
3625 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3626 if ((host->version >= SDHCI_SPEC_300) &&
3627 ((host->flags & SDHCI_USE_ADMA) ||
3628 !(host->flags & SDHCI_USE_SDMA)) &&
3629 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3630 host->flags |= SDHCI_AUTO_CMD23;
3631 DBG("Auto-CMD23 available\n");
3632 } else {
3633 DBG("Auto-CMD23 unavailable\n");
3634 }
3635
3636 /*
3637 * A controller may support 8-bit width, but the board itself
3638 * might not have the pins brought out. Boards that support
3639 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3640 * their platform code before calling sdhci_add_host(), and we
3641 * won't assume 8-bit width for hosts without that CAP.
3642 */
3643 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3644 mmc->caps |= MMC_CAP_4_BIT_DATA;
3645
3646 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3647 mmc->caps &= ~MMC_CAP_CMD23;
3648
3649 if (host->caps & SDHCI_CAN_DO_HISPD)
3650 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3651
3652 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3653 mmc_card_is_removable(mmc) &&
3654 mmc_gpio_get_cd(host->mmc) < 0)
3655 mmc->caps |= MMC_CAP_NEEDS_POLL;
3656
3657 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3658 if (!IS_ERR(mmc->supply.vqmmc)) {
3659 ret = regulator_enable(mmc->supply.vqmmc);
3660 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3661 1950000))
3662 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3663 SDHCI_SUPPORT_SDR50 |
3664 SDHCI_SUPPORT_DDR50);
3665 if (ret) {
3666 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3667 mmc_hostname(mmc), ret);
3668 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3669 }
3670 }
3671
3672 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3673 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3674 SDHCI_SUPPORT_DDR50);
3675 }
3676
3677 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3678 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3679 SDHCI_SUPPORT_DDR50))
3680 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3681
3682 /* SDR104 supports also implies SDR50 support */
3683 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3684 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3685 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3686 * field can be promoted to support HS200.
3687 */
3688 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3689 mmc->caps2 |= MMC_CAP2_HS200;
3690 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3691 mmc->caps |= MMC_CAP_UHS_SDR50;
3692 }
3693
3694 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3695 (host->caps1 & SDHCI_SUPPORT_HS400))
3696 mmc->caps2 |= MMC_CAP2_HS400;
3697
3698 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3699 (IS_ERR(mmc->supply.vqmmc) ||
3700 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3701 1300000)))
3702 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3703
3704 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3705 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3706 mmc->caps |= MMC_CAP_UHS_DDR50;
3707
3708 /* Does the host need tuning for SDR50? */
3709 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3710 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3711
3712 /* Driver Type(s) (A, C, D) supported by the host */
3713 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3714 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3715 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3716 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3717 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3718 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3719
3720 /* Initial value for re-tuning timer count */
3721 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3722 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3723
3724 /*
3725 * In case Re-tuning Timer is not disabled, the actual value of
3726 * re-tuning timer will be 2 ^ (n - 1).
3727 */
3728 if (host->tuning_count)
3729 host->tuning_count = 1 << (host->tuning_count - 1);
3730
3731 /* Re-tuning mode supported by the Host Controller */
3732 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3733 SDHCI_RETUNING_MODE_SHIFT;
3734
3735 ocr_avail = 0;
3736
3737 /*
3738 * According to SD Host Controller spec v3.00, if the Host System
3739 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3740 * the value is meaningful only if Voltage Support in the Capabilities
3741 * register is set. The actual current value is 4 times the register
3742 * value.
3743 */
3744 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3745 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3746 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3747 if (curr > 0) {
3748
3749 /* convert to SDHCI_MAX_CURRENT format */
3750 curr = curr/1000; /* convert to mA */
3751 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3752
3753 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3754 max_current_caps =
3755 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3756 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3757 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3758 }
3759 }
3760
3761 if (host->caps & SDHCI_CAN_VDD_330) {
3762 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3763
3764 mmc->max_current_330 = ((max_current_caps &
3765 SDHCI_MAX_CURRENT_330_MASK) >>
3766 SDHCI_MAX_CURRENT_330_SHIFT) *
3767 SDHCI_MAX_CURRENT_MULTIPLIER;
3768 }
3769 if (host->caps & SDHCI_CAN_VDD_300) {
3770 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3771
3772 mmc->max_current_300 = ((max_current_caps &
3773 SDHCI_MAX_CURRENT_300_MASK) >>
3774 SDHCI_MAX_CURRENT_300_SHIFT) *
3775 SDHCI_MAX_CURRENT_MULTIPLIER;
3776 }
3777 if (host->caps & SDHCI_CAN_VDD_180) {
3778 ocr_avail |= MMC_VDD_165_195;
3779
3780 mmc->max_current_180 = ((max_current_caps &
3781 SDHCI_MAX_CURRENT_180_MASK) >>
3782 SDHCI_MAX_CURRENT_180_SHIFT) *
3783 SDHCI_MAX_CURRENT_MULTIPLIER;
3784 }
3785
3786 /* If OCR set by host, use it instead. */
3787 if (host->ocr_mask)
3788 ocr_avail = host->ocr_mask;
3789
3790 /* If OCR set by external regulators, give it highest prio. */
3791 if (mmc->ocr_avail)
3792 ocr_avail = mmc->ocr_avail;
3793
3794 mmc->ocr_avail = ocr_avail;
3795 mmc->ocr_avail_sdio = ocr_avail;
3796 if (host->ocr_avail_sdio)
3797 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3798 mmc->ocr_avail_sd = ocr_avail;
3799 if (host->ocr_avail_sd)
3800 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3801 else /* normal SD controllers don't support 1.8V */
3802 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3803 mmc->ocr_avail_mmc = ocr_avail;
3804 if (host->ocr_avail_mmc)
3805 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3806
3807 if (mmc->ocr_avail == 0) {
3808 pr_err("%s: Hardware doesn't report any support voltages.\n",
3809 mmc_hostname(mmc));
3810 ret = -ENODEV;
3811 goto unreg;
3812 }
3813
3814 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3815 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3816 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3817 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3818 host->flags |= SDHCI_SIGNALING_180;
3819
3820 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3821 host->flags |= SDHCI_SIGNALING_120;
3822
3823 spin_lock_init(&host->lock);
3824
3825 /*
3826 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3827 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3828 * is less anyway.
3829 */
3830 mmc->max_req_size = 524288;
3831
3832 /*
3833 * Maximum number of segments. Depends on if the hardware
3834 * can do scatter/gather or not.
3835 */
3836 if (host->flags & SDHCI_USE_ADMA) {
3837 mmc->max_segs = SDHCI_MAX_SEGS;
3838 } else if (host->flags & SDHCI_USE_SDMA) {
3839 mmc->max_segs = 1;
3840 if (swiotlb_max_segment()) {
3841 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3842 IO_TLB_SEGSIZE;
3843 mmc->max_req_size = min(mmc->max_req_size,
3844 max_req_size);
3845 }
3846 } else { /* PIO */
3847 mmc->max_segs = SDHCI_MAX_SEGS;
3848 }
3849
3850 /*
3851 * Maximum segment size. Could be one segment with the maximum number
3852 * of bytes. When doing hardware scatter/gather, each entry cannot
3853 * be larger than 64 KiB though.
3854 */
3855 if (host->flags & SDHCI_USE_ADMA) {
3856 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3857 mmc->max_seg_size = 65535;
3858 else
3859 mmc->max_seg_size = 65536;
3860 } else {
3861 mmc->max_seg_size = mmc->max_req_size;
3862 }
3863
3864 /*
3865 * Maximum block size. This varies from controller to controller and
3866 * is specified in the capabilities register.
3867 */
3868 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3869 mmc->max_blk_size = 2;
3870 } else {
3871 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3872 SDHCI_MAX_BLOCK_SHIFT;
3873 if (mmc->max_blk_size >= 3) {
3874 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3875 mmc_hostname(mmc));
3876 mmc->max_blk_size = 0;
3877 }
3878 }
3879
3880 mmc->max_blk_size = 512 << mmc->max_blk_size;
3881
3882 /*
3883 * Maximum block count.
3884 */
3885 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3886
3887 if (mmc->max_segs == 1) {
3888 /* This may alter mmc->*_blk_* parameters */
3889 ret = sdhci_allocate_bounce_buffer(host);
3890 if (ret)
3891 return ret;
3892 }
3893
3894 return 0;
3895
3896unreg:
3897 if (!IS_ERR(mmc->supply.vqmmc))
3898 regulator_disable(mmc->supply.vqmmc);
3899undma:
3900 if (host->align_buffer)
3901 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3902 host->adma_table_sz, host->align_buffer,
3903 host->align_addr);
3904 host->adma_table = NULL;
3905 host->align_buffer = NULL;
3906
3907 return ret;
3908}
3909EXPORT_SYMBOL_GPL(sdhci_setup_host);
3910
3911void sdhci_cleanup_host(struct sdhci_host *host)
3912{
3913 struct mmc_host *mmc = host->mmc;
3914
3915 if (!IS_ERR(mmc->supply.vqmmc))
3916 regulator_disable(mmc->supply.vqmmc);
3917
3918 if (host->align_buffer)
3919 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3920 host->adma_table_sz, host->align_buffer,
3921 host->align_addr);
3922 host->adma_table = NULL;
3923 host->align_buffer = NULL;
3924}
3925EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3926
3927int __sdhci_add_host(struct sdhci_host *host)
3928{
3929 struct mmc_host *mmc = host->mmc;
3930 int ret;
3931
3932 /*
3933 * Init tasklets.
3934 */
3935 tasklet_init(&host->finish_tasklet,
3936 sdhci_tasklet_finish, (unsigned long)host);
3937
3938 timer_setup(&host->timer, sdhci_timeout_timer, 0);
3939 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
3940
3941 init_waitqueue_head(&host->buf_ready_int);
3942
3943 sdhci_init(host, 0);
3944
3945 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3946 IRQF_SHARED, mmc_hostname(mmc), host);
3947 if (ret) {
3948 pr_err("%s: Failed to request IRQ %d: %d\n",
3949 mmc_hostname(mmc), host->irq, ret);
3950 goto untasklet;
3951 }
3952
3953 ret = sdhci_led_register(host);
3954 if (ret) {
3955 pr_err("%s: Failed to register LED device: %d\n",
3956 mmc_hostname(mmc), ret);
3957 goto unirq;
3958 }
3959
3960 mmiowb();
3961
3962 ret = mmc_add_host(mmc);
3963 if (ret)
3964 goto unled;
3965
3966 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3967 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3968 (host->flags & SDHCI_USE_ADMA) ?
3969 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3970 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3971
3972 sdhci_enable_card_detection(host);
3973
3974 return 0;
3975
3976unled:
3977 sdhci_led_unregister(host);
3978unirq:
3979 sdhci_do_reset(host, SDHCI_RESET_ALL);
3980 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3981 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3982 free_irq(host->irq, host);
3983untasklet:
3984 tasklet_kill(&host->finish_tasklet);
3985
3986 return ret;
3987}
3988EXPORT_SYMBOL_GPL(__sdhci_add_host);
3989
3990int sdhci_add_host(struct sdhci_host *host)
3991{
3992 int ret;
3993
3994 ret = sdhci_setup_host(host);
3995 if (ret)
3996 return ret;
3997
3998 ret = __sdhci_add_host(host);
3999 if (ret)
4000 goto cleanup;
4001
4002 return 0;
4003
4004cleanup:
4005 sdhci_cleanup_host(host);
4006
4007 return ret;
4008}
4009EXPORT_SYMBOL_GPL(sdhci_add_host);
4010
4011void sdhci_remove_host(struct sdhci_host *host, int dead)
4012{
4013 struct mmc_host *mmc = host->mmc;
4014 unsigned long flags;
4015
4016 if (dead) {
4017 spin_lock_irqsave(&host->lock, flags);
4018
4019 host->flags |= SDHCI_DEVICE_DEAD;
4020
4021 if (sdhci_has_requests(host)) {
4022 pr_err("%s: Controller removed during "
4023 " transfer!\n", mmc_hostname(mmc));
4024 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4025 }
4026
4027 spin_unlock_irqrestore(&host->lock, flags);
4028 }
4029
4030 sdhci_disable_card_detection(host);
4031
4032 mmc_remove_host(mmc);
4033
4034 sdhci_led_unregister(host);
4035
4036 if (!dead)
4037 sdhci_do_reset(host, SDHCI_RESET_ALL);
4038
4039 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4040 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4041 free_irq(host->irq, host);
4042
4043 del_timer_sync(&host->timer);
4044 del_timer_sync(&host->data_timer);
4045
4046 tasklet_kill(&host->finish_tasklet);
4047
4048 if (!IS_ERR(mmc->supply.vqmmc))
4049 regulator_disable(mmc->supply.vqmmc);
4050
4051 if (host->align_buffer)
4052 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4053 host->adma_table_sz, host->align_buffer,
4054 host->align_addr);
4055
4056 host->adma_table = NULL;
4057 host->align_buffer = NULL;
4058}
4059
4060EXPORT_SYMBOL_GPL(sdhci_remove_host);
4061
4062void sdhci_free_host(struct sdhci_host *host)
4063{
4064 mmc_free_host(host->mmc);
4065}
4066
4067EXPORT_SYMBOL_GPL(sdhci_free_host);
4068
4069/*****************************************************************************\
4070 * *
4071 * Driver init/exit *
4072 * *
4073\*****************************************************************************/
4074
4075static int __init sdhci_drv_init(void)
4076{
4077 pr_info(DRIVER_NAME
4078 ": Secure Digital Host Controller Interface driver\n");
4079 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4080
4081 return 0;
4082}
4083
4084static void __exit sdhci_drv_exit(void)
4085{
4086}
4087
4088module_init(sdhci_drv_init);
4089module_exit(sdhci_drv_exit);
4090
4091module_param(debug_quirks, uint, 0444);
4092module_param(debug_quirks2, uint, 0444);
4093
4094MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4095MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4096MODULE_LICENSE("GPL");
4097
4098MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4099MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/dma-mapping.h>
21#include <linux/slab.h>
22#include <linux/scatterlist.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25
26#include <linux/leds.h>
27
28#include <linux/mmc/mmc.h>
29#include <linux/mmc/host.h>
30#include <linux/mmc/card.h>
31
32#include "sdhci.h"
33
34#define DRIVER_NAME "sdhci"
35
36#define DBG(f, x...) \
37 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
38
39#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40 defined(CONFIG_MMC_SDHCI_MODULE))
41#define SDHCI_USE_LEDS_CLASS
42#endif
43
44#define MAX_TUNING_LOOP 40
45
46static unsigned int debug_quirks = 0;
47static unsigned int debug_quirks2;
48
49static void sdhci_finish_data(struct sdhci_host *);
50
51static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52static void sdhci_finish_command(struct sdhci_host *);
53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54static void sdhci_tuning_timer(unsigned long data);
55
56#ifdef CONFIG_PM_RUNTIME
57static int sdhci_runtime_pm_get(struct sdhci_host *host);
58static int sdhci_runtime_pm_put(struct sdhci_host *host);
59#else
60static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
61{
62 return 0;
63}
64static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
65{
66 return 0;
67}
68#endif
69
70static void sdhci_dumpregs(struct sdhci_host *host)
71{
72 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
73 mmc_hostname(host->mmc));
74
75 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
76 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
78 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
79 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
81 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
82 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
84 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
85 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
87 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
88 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
90 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
91 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
93 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
94 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
96 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
97 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
99 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
103 sdhci_readl(host, SDHCI_CAPABILITIES),
104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
106 sdhci_readw(host, SDHCI_COMMAND),
107 sdhci_readl(host, SDHCI_MAX_CURRENT));
108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
110
111 if (host->flags & SDHCI_USE_ADMA)
112 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
113 readl(host->ioaddr + SDHCI_ADMA_ERROR),
114 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
115
116 pr_debug(DRIVER_NAME ": ===========================================\n");
117}
118
119/*****************************************************************************\
120 * *
121 * Low level functions *
122 * *
123\*****************************************************************************/
124
125static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
126{
127 u32 ier;
128
129 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
130 ier &= ~clear;
131 ier |= set;
132 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
134}
135
136static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
137{
138 sdhci_clear_set_irqs(host, 0, irqs);
139}
140
141static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
142{
143 sdhci_clear_set_irqs(host, irqs, 0);
144}
145
146static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147{
148 u32 present, irqs;
149
150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
152 return;
153
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
157
158 if (enable)
159 sdhci_unmask_irqs(host, irqs);
160 else
161 sdhci_mask_irqs(host, irqs);
162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
174static void sdhci_reset(struct sdhci_host *host, u8 mask)
175{
176 unsigned long timeout;
177 u32 uninitialized_var(ier);
178
179 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
180 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
181 SDHCI_CARD_PRESENT))
182 return;
183 }
184
185 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
187
188 if (host->ops->platform_reset_enter)
189 host->ops->platform_reset_enter(host, mask);
190
191 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
192
193 if (mask & SDHCI_RESET_ALL)
194 host->clock = 0;
195
196 /* Wait max 100 ms */
197 timeout = 100;
198
199 /* hw clears the bit when it's done */
200 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
201 if (timeout == 0) {
202 pr_err("%s: Reset 0x%x never completed.\n",
203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
205 return;
206 }
207 timeout--;
208 mdelay(1);
209 }
210
211 if (host->ops->platform_reset_exit)
212 host->ops->platform_reset_exit(host, mask);
213
214 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
216
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219 host->ops->enable_dma(host);
220 }
221}
222
223static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
224
225static void sdhci_init(struct sdhci_host *host, int soft)
226{
227 if (soft)
228 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
229 else
230 sdhci_reset(host, SDHCI_RESET_ALL);
231
232 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
236 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
237
238 if (soft) {
239 /* force clock reconfiguration */
240 host->clock = 0;
241 sdhci_set_ios(host->mmc, &host->mmc->ios);
242 }
243}
244
245static void sdhci_reinit(struct sdhci_host *host)
246{
247 sdhci_init(host, 0);
248 sdhci_enable_card_detection(host);
249}
250
251static void sdhci_activate_led(struct sdhci_host *host)
252{
253 u8 ctrl;
254
255 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
256 ctrl |= SDHCI_CTRL_LED;
257 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
258}
259
260static void sdhci_deactivate_led(struct sdhci_host *host)
261{
262 u8 ctrl;
263
264 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
265 ctrl &= ~SDHCI_CTRL_LED;
266 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
267}
268
269#ifdef SDHCI_USE_LEDS_CLASS
270static void sdhci_led_control(struct led_classdev *led,
271 enum led_brightness brightness)
272{
273 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
274 unsigned long flags;
275
276 spin_lock_irqsave(&host->lock, flags);
277
278 if (host->runtime_suspended)
279 goto out;
280
281 if (brightness == LED_OFF)
282 sdhci_deactivate_led(host);
283 else
284 sdhci_activate_led(host);
285out:
286 spin_unlock_irqrestore(&host->lock, flags);
287}
288#endif
289
290/*****************************************************************************\
291 * *
292 * Core functions *
293 * *
294\*****************************************************************************/
295
296static void sdhci_read_block_pio(struct sdhci_host *host)
297{
298 unsigned long flags;
299 size_t blksize, len, chunk;
300 u32 uninitialized_var(scratch);
301 u8 *buf;
302
303 DBG("PIO reading\n");
304
305 blksize = host->data->blksz;
306 chunk = 0;
307
308 local_irq_save(flags);
309
310 while (blksize) {
311 if (!sg_miter_next(&host->sg_miter))
312 BUG();
313
314 len = min(host->sg_miter.length, blksize);
315
316 blksize -= len;
317 host->sg_miter.consumed = len;
318
319 buf = host->sg_miter.addr;
320
321 while (len) {
322 if (chunk == 0) {
323 scratch = sdhci_readl(host, SDHCI_BUFFER);
324 chunk = 4;
325 }
326
327 *buf = scratch & 0xFF;
328
329 buf++;
330 scratch >>= 8;
331 chunk--;
332 len--;
333 }
334 }
335
336 sg_miter_stop(&host->sg_miter);
337
338 local_irq_restore(flags);
339}
340
341static void sdhci_write_block_pio(struct sdhci_host *host)
342{
343 unsigned long flags;
344 size_t blksize, len, chunk;
345 u32 scratch;
346 u8 *buf;
347
348 DBG("PIO writing\n");
349
350 blksize = host->data->blksz;
351 chunk = 0;
352 scratch = 0;
353
354 local_irq_save(flags);
355
356 while (blksize) {
357 if (!sg_miter_next(&host->sg_miter))
358 BUG();
359
360 len = min(host->sg_miter.length, blksize);
361
362 blksize -= len;
363 host->sg_miter.consumed = len;
364
365 buf = host->sg_miter.addr;
366
367 while (len) {
368 scratch |= (u32)*buf << (chunk * 8);
369
370 buf++;
371 chunk++;
372 len--;
373
374 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
375 sdhci_writel(host, scratch, SDHCI_BUFFER);
376 chunk = 0;
377 scratch = 0;
378 }
379 }
380 }
381
382 sg_miter_stop(&host->sg_miter);
383
384 local_irq_restore(flags);
385}
386
387static void sdhci_transfer_pio(struct sdhci_host *host)
388{
389 u32 mask;
390
391 BUG_ON(!host->data);
392
393 if (host->blocks == 0)
394 return;
395
396 if (host->data->flags & MMC_DATA_READ)
397 mask = SDHCI_DATA_AVAILABLE;
398 else
399 mask = SDHCI_SPACE_AVAILABLE;
400
401 /*
402 * Some controllers (JMicron JMB38x) mess up the buffer bits
403 * for transfers < 4 bytes. As long as it is just one block,
404 * we can ignore the bits.
405 */
406 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
407 (host->data->blocks == 1))
408 mask = ~0;
409
410 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
411 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
412 udelay(100);
413
414 if (host->data->flags & MMC_DATA_READ)
415 sdhci_read_block_pio(host);
416 else
417 sdhci_write_block_pio(host);
418
419 host->blocks--;
420 if (host->blocks == 0)
421 break;
422 }
423
424 DBG("PIO transfer complete.\n");
425}
426
427static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
428{
429 local_irq_save(*flags);
430 return kmap_atomic(sg_page(sg)) + sg->offset;
431}
432
433static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
434{
435 kunmap_atomic(buffer);
436 local_irq_restore(*flags);
437}
438
439static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
440{
441 __le32 *dataddr = (__le32 __force *)(desc + 4);
442 __le16 *cmdlen = (__le16 __force *)desc;
443
444 /* SDHCI specification says ADMA descriptors should be 4 byte
445 * aligned, so using 16 or 32bit operations should be safe. */
446
447 cmdlen[0] = cpu_to_le16(cmd);
448 cmdlen[1] = cpu_to_le16(len);
449
450 dataddr[0] = cpu_to_le32(addr);
451}
452
453static int sdhci_adma_table_pre(struct sdhci_host *host,
454 struct mmc_data *data)
455{
456 int direction;
457
458 u8 *desc;
459 u8 *align;
460 dma_addr_t addr;
461 dma_addr_t align_addr;
462 int len, offset;
463
464 struct scatterlist *sg;
465 int i;
466 char *buffer;
467 unsigned long flags;
468
469 /*
470 * The spec does not specify endianness of descriptor table.
471 * We currently guess that it is LE.
472 */
473
474 if (data->flags & MMC_DATA_READ)
475 direction = DMA_FROM_DEVICE;
476 else
477 direction = DMA_TO_DEVICE;
478
479 /*
480 * The ADMA descriptor table is mapped further down as we
481 * need to fill it with data first.
482 */
483
484 host->align_addr = dma_map_single(mmc_dev(host->mmc),
485 host->align_buffer, 128 * 4, direction);
486 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
487 goto fail;
488 BUG_ON(host->align_addr & 0x3);
489
490 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
491 data->sg, data->sg_len, direction);
492 if (host->sg_count == 0)
493 goto unmap_align;
494
495 desc = host->adma_desc;
496 align = host->align_buffer;
497
498 align_addr = host->align_addr;
499
500 for_each_sg(data->sg, sg, host->sg_count, i) {
501 addr = sg_dma_address(sg);
502 len = sg_dma_len(sg);
503
504 /*
505 * The SDHCI specification states that ADMA
506 * addresses must be 32-bit aligned. If they
507 * aren't, then we use a bounce buffer for
508 * the (up to three) bytes that screw up the
509 * alignment.
510 */
511 offset = (4 - (addr & 0x3)) & 0x3;
512 if (offset) {
513 if (data->flags & MMC_DATA_WRITE) {
514 buffer = sdhci_kmap_atomic(sg, &flags);
515 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
516 memcpy(align, buffer, offset);
517 sdhci_kunmap_atomic(buffer, &flags);
518 }
519
520 /* tran, valid */
521 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
522
523 BUG_ON(offset > 65536);
524
525 align += 4;
526 align_addr += 4;
527
528 desc += 8;
529
530 addr += offset;
531 len -= offset;
532 }
533
534 BUG_ON(len > 65536);
535
536 /* tran, valid */
537 sdhci_set_adma_desc(desc, addr, len, 0x21);
538 desc += 8;
539
540 /*
541 * If this triggers then we have a calculation bug
542 * somewhere. :/
543 */
544 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
545 }
546
547 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
548 /*
549 * Mark the last descriptor as the terminating descriptor
550 */
551 if (desc != host->adma_desc) {
552 desc -= 8;
553 desc[0] |= 0x2; /* end */
554 }
555 } else {
556 /*
557 * Add a terminating entry.
558 */
559
560 /* nop, end, valid */
561 sdhci_set_adma_desc(desc, 0, 0, 0x3);
562 }
563
564 /*
565 * Resync align buffer as we might have changed it.
566 */
567 if (data->flags & MMC_DATA_WRITE) {
568 dma_sync_single_for_device(mmc_dev(host->mmc),
569 host->align_addr, 128 * 4, direction);
570 }
571
572 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
573 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
574 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
575 goto unmap_entries;
576 BUG_ON(host->adma_addr & 0x3);
577
578 return 0;
579
580unmap_entries:
581 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
582 data->sg_len, direction);
583unmap_align:
584 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
585 128 * 4, direction);
586fail:
587 return -EINVAL;
588}
589
590static void sdhci_adma_table_post(struct sdhci_host *host,
591 struct mmc_data *data)
592{
593 int direction;
594
595 struct scatterlist *sg;
596 int i, size;
597 u8 *align;
598 char *buffer;
599 unsigned long flags;
600
601 if (data->flags & MMC_DATA_READ)
602 direction = DMA_FROM_DEVICE;
603 else
604 direction = DMA_TO_DEVICE;
605
606 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
607 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
608
609 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
610 128 * 4, direction);
611
612 if (data->flags & MMC_DATA_READ) {
613 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
614 data->sg_len, direction);
615
616 align = host->align_buffer;
617
618 for_each_sg(data->sg, sg, host->sg_count, i) {
619 if (sg_dma_address(sg) & 0x3) {
620 size = 4 - (sg_dma_address(sg) & 0x3);
621
622 buffer = sdhci_kmap_atomic(sg, &flags);
623 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
624 memcpy(buffer, align, size);
625 sdhci_kunmap_atomic(buffer, &flags);
626
627 align += 4;
628 }
629 }
630 }
631
632 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
633 data->sg_len, direction);
634}
635
636static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
637{
638 u8 count;
639 struct mmc_data *data = cmd->data;
640 unsigned target_timeout, current_timeout;
641
642 /*
643 * If the host controller provides us with an incorrect timeout
644 * value, just skip the check and use 0xE. The hardware may take
645 * longer to time out, but that's much better than having a too-short
646 * timeout value.
647 */
648 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
649 return 0xE;
650
651 /* Unspecified timeout, assume max */
652 if (!data && !cmd->cmd_timeout_ms)
653 return 0xE;
654
655 /* timeout in us */
656 if (!data)
657 target_timeout = cmd->cmd_timeout_ms * 1000;
658 else {
659 target_timeout = data->timeout_ns / 1000;
660 if (host->clock)
661 target_timeout += data->timeout_clks / host->clock;
662 }
663
664 /*
665 * Figure out needed cycles.
666 * We do this in steps in order to fit inside a 32 bit int.
667 * The first step is the minimum timeout, which will have a
668 * minimum resolution of 6 bits:
669 * (1) 2^13*1000 > 2^22,
670 * (2) host->timeout_clk < 2^16
671 * =>
672 * (1) / (2) > 2^6
673 */
674 count = 0;
675 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
676 while (current_timeout < target_timeout) {
677 count++;
678 current_timeout <<= 1;
679 if (count >= 0xF)
680 break;
681 }
682
683 if (count >= 0xF) {
684 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
685 mmc_hostname(host->mmc), count, cmd->opcode);
686 count = 0xE;
687 }
688
689 return count;
690}
691
692static void sdhci_set_transfer_irqs(struct sdhci_host *host)
693{
694 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
695 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
696
697 if (host->flags & SDHCI_REQ_USE_DMA)
698 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
699 else
700 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
701}
702
703static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
704{
705 u8 count;
706 u8 ctrl;
707 struct mmc_data *data = cmd->data;
708 int ret;
709
710 WARN_ON(host->data);
711
712 if (data || (cmd->flags & MMC_RSP_BUSY)) {
713 count = sdhci_calc_timeout(host, cmd);
714 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
715 }
716
717 if (!data)
718 return;
719
720 /* Sanity checks */
721 BUG_ON(data->blksz * data->blocks > 524288);
722 BUG_ON(data->blksz > host->mmc->max_blk_size);
723 BUG_ON(data->blocks > 65535);
724
725 host->data = data;
726 host->data_early = 0;
727 host->data->bytes_xfered = 0;
728
729 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
730 host->flags |= SDHCI_REQ_USE_DMA;
731
732 /*
733 * FIXME: This doesn't account for merging when mapping the
734 * scatterlist.
735 */
736 if (host->flags & SDHCI_REQ_USE_DMA) {
737 int broken, i;
738 struct scatterlist *sg;
739
740 broken = 0;
741 if (host->flags & SDHCI_USE_ADMA) {
742 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
743 broken = 1;
744 } else {
745 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
746 broken = 1;
747 }
748
749 if (unlikely(broken)) {
750 for_each_sg(data->sg, sg, data->sg_len, i) {
751 if (sg->length & 0x3) {
752 DBG("Reverting to PIO because of "
753 "transfer size (%d)\n",
754 sg->length);
755 host->flags &= ~SDHCI_REQ_USE_DMA;
756 break;
757 }
758 }
759 }
760 }
761
762 /*
763 * The assumption here being that alignment is the same after
764 * translation to device address space.
765 */
766 if (host->flags & SDHCI_REQ_USE_DMA) {
767 int broken, i;
768 struct scatterlist *sg;
769
770 broken = 0;
771 if (host->flags & SDHCI_USE_ADMA) {
772 /*
773 * As we use 3 byte chunks to work around
774 * alignment problems, we need to check this
775 * quirk.
776 */
777 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
778 broken = 1;
779 } else {
780 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
781 broken = 1;
782 }
783
784 if (unlikely(broken)) {
785 for_each_sg(data->sg, sg, data->sg_len, i) {
786 if (sg->offset & 0x3) {
787 DBG("Reverting to PIO because of "
788 "bad alignment\n");
789 host->flags &= ~SDHCI_REQ_USE_DMA;
790 break;
791 }
792 }
793 }
794 }
795
796 if (host->flags & SDHCI_REQ_USE_DMA) {
797 if (host->flags & SDHCI_USE_ADMA) {
798 ret = sdhci_adma_table_pre(host, data);
799 if (ret) {
800 /*
801 * This only happens when someone fed
802 * us an invalid request.
803 */
804 WARN_ON(1);
805 host->flags &= ~SDHCI_REQ_USE_DMA;
806 } else {
807 sdhci_writel(host, host->adma_addr,
808 SDHCI_ADMA_ADDRESS);
809 }
810 } else {
811 int sg_cnt;
812
813 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
814 data->sg, data->sg_len,
815 (data->flags & MMC_DATA_READ) ?
816 DMA_FROM_DEVICE :
817 DMA_TO_DEVICE);
818 if (sg_cnt == 0) {
819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
824 host->flags &= ~SDHCI_REQ_USE_DMA;
825 } else {
826 WARN_ON(sg_cnt != 1);
827 sdhci_writel(host, sg_dma_address(data->sg),
828 SDHCI_DMA_ADDRESS);
829 }
830 }
831 }
832
833 /*
834 * Always adjust the DMA selection as some controllers
835 * (e.g. JMicron) can't do PIO properly when the selection
836 * is ADMA.
837 */
838 if (host->version >= SDHCI_SPEC_200) {
839 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
840 ctrl &= ~SDHCI_CTRL_DMA_MASK;
841 if ((host->flags & SDHCI_REQ_USE_DMA) &&
842 (host->flags & SDHCI_USE_ADMA))
843 ctrl |= SDHCI_CTRL_ADMA32;
844 else
845 ctrl |= SDHCI_CTRL_SDMA;
846 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
847 }
848
849 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
850 int flags;
851
852 flags = SG_MITER_ATOMIC;
853 if (host->data->flags & MMC_DATA_READ)
854 flags |= SG_MITER_TO_SG;
855 else
856 flags |= SG_MITER_FROM_SG;
857 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
858 host->blocks = data->blocks;
859 }
860
861 sdhci_set_transfer_irqs(host);
862
863 /* Set the DMA boundary value and block size */
864 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
865 data->blksz), SDHCI_BLOCK_SIZE);
866 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
867}
868
869static void sdhci_set_transfer_mode(struct sdhci_host *host,
870 struct mmc_command *cmd)
871{
872 u16 mode;
873 struct mmc_data *data = cmd->data;
874
875 if (data == NULL)
876 return;
877
878 WARN_ON(!host->data);
879
880 mode = SDHCI_TRNS_BLK_CNT_EN;
881 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
882 mode |= SDHCI_TRNS_MULTI;
883 /*
884 * If we are sending CMD23, CMD12 never gets sent
885 * on successful completion (so no Auto-CMD12).
886 */
887 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
888 mode |= SDHCI_TRNS_AUTO_CMD12;
889 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
890 mode |= SDHCI_TRNS_AUTO_CMD23;
891 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
892 }
893 }
894
895 if (data->flags & MMC_DATA_READ)
896 mode |= SDHCI_TRNS_READ;
897 if (host->flags & SDHCI_REQ_USE_DMA)
898 mode |= SDHCI_TRNS_DMA;
899
900 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
901}
902
903static void sdhci_finish_data(struct sdhci_host *host)
904{
905 struct mmc_data *data;
906
907 BUG_ON(!host->data);
908
909 data = host->data;
910 host->data = NULL;
911
912 if (host->flags & SDHCI_REQ_USE_DMA) {
913 if (host->flags & SDHCI_USE_ADMA)
914 sdhci_adma_table_post(host, data);
915 else {
916 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
917 data->sg_len, (data->flags & MMC_DATA_READ) ?
918 DMA_FROM_DEVICE : DMA_TO_DEVICE);
919 }
920 }
921
922 /*
923 * The specification states that the block count register must
924 * be updated, but it does not specify at what point in the
925 * data flow. That makes the register entirely useless to read
926 * back so we have to assume that nothing made it to the card
927 * in the event of an error.
928 */
929 if (data->error)
930 data->bytes_xfered = 0;
931 else
932 data->bytes_xfered = data->blksz * data->blocks;
933
934 /*
935 * Need to send CMD12 if -
936 * a) open-ended multiblock transfer (no CMD23)
937 * b) error in multiblock transfer
938 */
939 if (data->stop &&
940 (data->error ||
941 !host->mrq->sbc)) {
942
943 /*
944 * The controller needs a reset of internal state machines
945 * upon error conditions.
946 */
947 if (data->error) {
948 sdhci_reset(host, SDHCI_RESET_CMD);
949 sdhci_reset(host, SDHCI_RESET_DATA);
950 }
951
952 sdhci_send_command(host, data->stop);
953 } else
954 tasklet_schedule(&host->finish_tasklet);
955}
956
957static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
958{
959 int flags;
960 u32 mask;
961 unsigned long timeout;
962
963 WARN_ON(host->cmd);
964
965 /* Wait max 10 ms */
966 timeout = 10;
967
968 mask = SDHCI_CMD_INHIBIT;
969 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
970 mask |= SDHCI_DATA_INHIBIT;
971
972 /* We shouldn't wait for data inihibit for stop commands, even
973 though they might use busy signaling */
974 if (host->mrq->data && (cmd == host->mrq->data->stop))
975 mask &= ~SDHCI_DATA_INHIBIT;
976
977 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
978 if (timeout == 0) {
979 pr_err("%s: Controller never released "
980 "inhibit bit(s).\n", mmc_hostname(host->mmc));
981 sdhci_dumpregs(host);
982 cmd->error = -EIO;
983 tasklet_schedule(&host->finish_tasklet);
984 return;
985 }
986 timeout--;
987 mdelay(1);
988 }
989
990 mod_timer(&host->timer, jiffies + 10 * HZ);
991
992 host->cmd = cmd;
993
994 sdhci_prepare_data(host, cmd);
995
996 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
997
998 sdhci_set_transfer_mode(host, cmd);
999
1000 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1001 pr_err("%s: Unsupported response type!\n",
1002 mmc_hostname(host->mmc));
1003 cmd->error = -EINVAL;
1004 tasklet_schedule(&host->finish_tasklet);
1005 return;
1006 }
1007
1008 if (!(cmd->flags & MMC_RSP_PRESENT))
1009 flags = SDHCI_CMD_RESP_NONE;
1010 else if (cmd->flags & MMC_RSP_136)
1011 flags = SDHCI_CMD_RESP_LONG;
1012 else if (cmd->flags & MMC_RSP_BUSY)
1013 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1014 else
1015 flags = SDHCI_CMD_RESP_SHORT;
1016
1017 if (cmd->flags & MMC_RSP_CRC)
1018 flags |= SDHCI_CMD_CRC;
1019 if (cmd->flags & MMC_RSP_OPCODE)
1020 flags |= SDHCI_CMD_INDEX;
1021
1022 /* CMD19 is special in that the Data Present Select should be set */
1023 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1024 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1025 flags |= SDHCI_CMD_DATA;
1026
1027 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1028}
1029
1030static void sdhci_finish_command(struct sdhci_host *host)
1031{
1032 int i;
1033
1034 BUG_ON(host->cmd == NULL);
1035
1036 if (host->cmd->flags & MMC_RSP_PRESENT) {
1037 if (host->cmd->flags & MMC_RSP_136) {
1038 /* CRC is stripped so we need to do some shifting. */
1039 for (i = 0;i < 4;i++) {
1040 host->cmd->resp[i] = sdhci_readl(host,
1041 SDHCI_RESPONSE + (3-i)*4) << 8;
1042 if (i != 3)
1043 host->cmd->resp[i] |=
1044 sdhci_readb(host,
1045 SDHCI_RESPONSE + (3-i)*4-1);
1046 }
1047 } else {
1048 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1049 }
1050 }
1051
1052 host->cmd->error = 0;
1053
1054 /* Finished CMD23, now send actual command. */
1055 if (host->cmd == host->mrq->sbc) {
1056 host->cmd = NULL;
1057 sdhci_send_command(host, host->mrq->cmd);
1058 } else {
1059
1060 /* Processed actual command. */
1061 if (host->data && host->data_early)
1062 sdhci_finish_data(host);
1063
1064 if (!host->cmd->data)
1065 tasklet_schedule(&host->finish_tasklet);
1066
1067 host->cmd = NULL;
1068 }
1069}
1070
1071static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1072{
1073 int div = 0; /* Initialized for compiler warning */
1074 int real_div = div, clk_mul = 1;
1075 u16 clk = 0;
1076 unsigned long timeout;
1077
1078 if (clock && clock == host->clock)
1079 return;
1080
1081 host->mmc->actual_clock = 0;
1082
1083 if (host->ops->set_clock) {
1084 host->ops->set_clock(host, clock);
1085 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1086 return;
1087 }
1088
1089 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1090
1091 if (clock == 0)
1092 goto out;
1093
1094 if (host->version >= SDHCI_SPEC_300) {
1095 /*
1096 * Check if the Host Controller supports Programmable Clock
1097 * Mode.
1098 */
1099 if (host->clk_mul) {
1100 u16 ctrl;
1101
1102 /*
1103 * We need to figure out whether the Host Driver needs
1104 * to select Programmable Clock Mode, or the value can
1105 * be set automatically by the Host Controller based on
1106 * the Preset Value registers.
1107 */
1108 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1109 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1110 for (div = 1; div <= 1024; div++) {
1111 if (((host->max_clk * host->clk_mul) /
1112 div) <= clock)
1113 break;
1114 }
1115 /*
1116 * Set Programmable Clock Mode in the Clock
1117 * Control register.
1118 */
1119 clk = SDHCI_PROG_CLOCK_MODE;
1120 real_div = div;
1121 clk_mul = host->clk_mul;
1122 div--;
1123 }
1124 } else {
1125 /* Version 3.00 divisors must be a multiple of 2. */
1126 if (host->max_clk <= clock)
1127 div = 1;
1128 else {
1129 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1130 div += 2) {
1131 if ((host->max_clk / div) <= clock)
1132 break;
1133 }
1134 }
1135 real_div = div;
1136 div >>= 1;
1137 }
1138 } else {
1139 /* Version 2.00 divisors must be a power of 2. */
1140 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1141 if ((host->max_clk / div) <= clock)
1142 break;
1143 }
1144 real_div = div;
1145 div >>= 1;
1146 }
1147
1148 if (real_div)
1149 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1150
1151 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1152 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1153 << SDHCI_DIVIDER_HI_SHIFT;
1154 clk |= SDHCI_CLOCK_INT_EN;
1155 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1156
1157 /* Wait max 20 ms */
1158 timeout = 20;
1159 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1160 & SDHCI_CLOCK_INT_STABLE)) {
1161 if (timeout == 0) {
1162 pr_err("%s: Internal clock never "
1163 "stabilised.\n", mmc_hostname(host->mmc));
1164 sdhci_dumpregs(host);
1165 return;
1166 }
1167 timeout--;
1168 mdelay(1);
1169 }
1170
1171 clk |= SDHCI_CLOCK_CARD_EN;
1172 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1173
1174out:
1175 host->clock = clock;
1176}
1177
1178static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1179{
1180 u8 pwr = 0;
1181
1182 if (power != (unsigned short)-1) {
1183 switch (1 << power) {
1184 case MMC_VDD_165_195:
1185 pwr = SDHCI_POWER_180;
1186 break;
1187 case MMC_VDD_29_30:
1188 case MMC_VDD_30_31:
1189 pwr = SDHCI_POWER_300;
1190 break;
1191 case MMC_VDD_32_33:
1192 case MMC_VDD_33_34:
1193 pwr = SDHCI_POWER_330;
1194 break;
1195 default:
1196 BUG();
1197 }
1198 }
1199
1200 if (host->pwr == pwr)
1201 return -1;
1202
1203 host->pwr = pwr;
1204
1205 if (pwr == 0) {
1206 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1207 return 0;
1208 }
1209
1210 /*
1211 * Spec says that we should clear the power reg before setting
1212 * a new value. Some controllers don't seem to like this though.
1213 */
1214 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1215 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1216
1217 /*
1218 * At least the Marvell CaFe chip gets confused if we set the voltage
1219 * and set turn on power at the same time, so set the voltage first.
1220 */
1221 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1222 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1223
1224 pwr |= SDHCI_POWER_ON;
1225
1226 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1227
1228 /*
1229 * Some controllers need an extra 10ms delay of 10ms before they
1230 * can apply clock after applying power
1231 */
1232 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1233 mdelay(10);
1234
1235 return power;
1236}
1237
1238/*****************************************************************************\
1239 * *
1240 * MMC callbacks *
1241 * *
1242\*****************************************************************************/
1243
1244static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1245{
1246 struct sdhci_host *host;
1247 bool present;
1248 unsigned long flags;
1249 u32 tuning_opcode;
1250
1251 host = mmc_priv(mmc);
1252
1253 sdhci_runtime_pm_get(host);
1254
1255 spin_lock_irqsave(&host->lock, flags);
1256
1257 WARN_ON(host->mrq != NULL);
1258
1259#ifndef SDHCI_USE_LEDS_CLASS
1260 sdhci_activate_led(host);
1261#endif
1262
1263 /*
1264 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1265 * requests if Auto-CMD12 is enabled.
1266 */
1267 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1268 if (mrq->stop) {
1269 mrq->data->stop = NULL;
1270 mrq->stop = NULL;
1271 }
1272 }
1273
1274 host->mrq = mrq;
1275
1276 /* If polling, assume that the card is always present. */
1277 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1278 present = true;
1279 else
1280 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1281 SDHCI_CARD_PRESENT;
1282
1283 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1284 host->mrq->cmd->error = -ENOMEDIUM;
1285 tasklet_schedule(&host->finish_tasklet);
1286 } else {
1287 u32 present_state;
1288
1289 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1290 /*
1291 * Check if the re-tuning timer has already expired and there
1292 * is no on-going data transfer. If so, we need to execute
1293 * tuning procedure before sending command.
1294 */
1295 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1296 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1297 /* eMMC uses cmd21 while sd and sdio use cmd19 */
1298 tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1299 MMC_SEND_TUNING_BLOCK_HS200 :
1300 MMC_SEND_TUNING_BLOCK;
1301 spin_unlock_irqrestore(&host->lock, flags);
1302 sdhci_execute_tuning(mmc, tuning_opcode);
1303 spin_lock_irqsave(&host->lock, flags);
1304
1305 /* Restore original mmc_request structure */
1306 host->mrq = mrq;
1307 }
1308
1309 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1310 sdhci_send_command(host, mrq->sbc);
1311 else
1312 sdhci_send_command(host, mrq->cmd);
1313 }
1314
1315 mmiowb();
1316 spin_unlock_irqrestore(&host->lock, flags);
1317}
1318
1319static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1320{
1321 unsigned long flags;
1322 int vdd_bit = -1;
1323 u8 ctrl;
1324
1325 spin_lock_irqsave(&host->lock, flags);
1326
1327 if (host->flags & SDHCI_DEVICE_DEAD) {
1328 spin_unlock_irqrestore(&host->lock, flags);
1329 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1330 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1331 return;
1332 }
1333
1334 /*
1335 * Reset the chip on each power off.
1336 * Should clear out any weird states.
1337 */
1338 if (ios->power_mode == MMC_POWER_OFF) {
1339 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1340 sdhci_reinit(host);
1341 }
1342
1343 sdhci_set_clock(host, ios->clock);
1344
1345 if (ios->power_mode == MMC_POWER_OFF)
1346 vdd_bit = sdhci_set_power(host, -1);
1347 else
1348 vdd_bit = sdhci_set_power(host, ios->vdd);
1349
1350 if (host->vmmc && vdd_bit != -1) {
1351 spin_unlock_irqrestore(&host->lock, flags);
1352 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1353 spin_lock_irqsave(&host->lock, flags);
1354 }
1355
1356 if (host->ops->platform_send_init_74_clocks)
1357 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1358
1359 /*
1360 * If your platform has 8-bit width support but is not a v3 controller,
1361 * or if it requires special setup code, you should implement that in
1362 * platform_8bit_width().
1363 */
1364 if (host->ops->platform_8bit_width)
1365 host->ops->platform_8bit_width(host, ios->bus_width);
1366 else {
1367 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1368 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1369 ctrl &= ~SDHCI_CTRL_4BITBUS;
1370 if (host->version >= SDHCI_SPEC_300)
1371 ctrl |= SDHCI_CTRL_8BITBUS;
1372 } else {
1373 if (host->version >= SDHCI_SPEC_300)
1374 ctrl &= ~SDHCI_CTRL_8BITBUS;
1375 if (ios->bus_width == MMC_BUS_WIDTH_4)
1376 ctrl |= SDHCI_CTRL_4BITBUS;
1377 else
1378 ctrl &= ~SDHCI_CTRL_4BITBUS;
1379 }
1380 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1381 }
1382
1383 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1384
1385 if ((ios->timing == MMC_TIMING_SD_HS ||
1386 ios->timing == MMC_TIMING_MMC_HS)
1387 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1388 ctrl |= SDHCI_CTRL_HISPD;
1389 else
1390 ctrl &= ~SDHCI_CTRL_HISPD;
1391
1392 if (host->version >= SDHCI_SPEC_300) {
1393 u16 clk, ctrl_2;
1394 unsigned int clock;
1395
1396 /* In case of UHS-I modes, set High Speed Enable */
1397 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1398 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1399 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1400 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1401 (ios->timing == MMC_TIMING_UHS_SDR25))
1402 ctrl |= SDHCI_CTRL_HISPD;
1403
1404 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1405 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1406 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1407 /*
1408 * We only need to set Driver Strength if the
1409 * preset value enable is not set.
1410 */
1411 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1412 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1413 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1414 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1415 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1416
1417 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1418 } else {
1419 /*
1420 * According to SDHC Spec v3.00, if the Preset Value
1421 * Enable in the Host Control 2 register is set, we
1422 * need to reset SD Clock Enable before changing High
1423 * Speed Enable to avoid generating clock gliches.
1424 */
1425
1426 /* Reset SD Clock Enable */
1427 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1428 clk &= ~SDHCI_CLOCK_CARD_EN;
1429 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1430
1431 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1432
1433 /* Re-enable SD Clock */
1434 clock = host->clock;
1435 host->clock = 0;
1436 sdhci_set_clock(host, clock);
1437 }
1438
1439
1440 /* Reset SD Clock Enable */
1441 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1442 clk &= ~SDHCI_CLOCK_CARD_EN;
1443 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1444
1445 if (host->ops->set_uhs_signaling)
1446 host->ops->set_uhs_signaling(host, ios->timing);
1447 else {
1448 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1449 /* Select Bus Speed Mode for host */
1450 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1451 if (ios->timing == MMC_TIMING_MMC_HS200)
1452 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1453 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1454 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1455 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1456 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1457 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1458 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1459 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1460 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1461 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1462 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1463 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1464 }
1465
1466 /* Re-enable SD Clock */
1467 clock = host->clock;
1468 host->clock = 0;
1469 sdhci_set_clock(host, clock);
1470 } else
1471 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1472
1473 /*
1474 * Some (ENE) controllers go apeshit on some ios operation,
1475 * signalling timeout and CRC errors even on CMD0. Resetting
1476 * it on each ios seems to solve the problem.
1477 */
1478 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1479 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1480
1481 mmiowb();
1482 spin_unlock_irqrestore(&host->lock, flags);
1483}
1484
1485static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1486{
1487 struct sdhci_host *host = mmc_priv(mmc);
1488
1489 sdhci_runtime_pm_get(host);
1490 sdhci_do_set_ios(host, ios);
1491 sdhci_runtime_pm_put(host);
1492}
1493
1494static int sdhci_check_ro(struct sdhci_host *host)
1495{
1496 unsigned long flags;
1497 int is_readonly;
1498
1499 spin_lock_irqsave(&host->lock, flags);
1500
1501 if (host->flags & SDHCI_DEVICE_DEAD)
1502 is_readonly = 0;
1503 else if (host->ops->get_ro)
1504 is_readonly = host->ops->get_ro(host);
1505 else
1506 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1507 & SDHCI_WRITE_PROTECT);
1508
1509 spin_unlock_irqrestore(&host->lock, flags);
1510
1511 /* This quirk needs to be replaced by a callback-function later */
1512 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1513 !is_readonly : is_readonly;
1514}
1515
1516#define SAMPLE_COUNT 5
1517
1518static int sdhci_do_get_ro(struct sdhci_host *host)
1519{
1520 int i, ro_count;
1521
1522 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1523 return sdhci_check_ro(host);
1524
1525 ro_count = 0;
1526 for (i = 0; i < SAMPLE_COUNT; i++) {
1527 if (sdhci_check_ro(host)) {
1528 if (++ro_count > SAMPLE_COUNT / 2)
1529 return 1;
1530 }
1531 msleep(30);
1532 }
1533 return 0;
1534}
1535
1536static void sdhci_hw_reset(struct mmc_host *mmc)
1537{
1538 struct sdhci_host *host = mmc_priv(mmc);
1539
1540 if (host->ops && host->ops->hw_reset)
1541 host->ops->hw_reset(host);
1542}
1543
1544static int sdhci_get_ro(struct mmc_host *mmc)
1545{
1546 struct sdhci_host *host = mmc_priv(mmc);
1547 int ret;
1548
1549 sdhci_runtime_pm_get(host);
1550 ret = sdhci_do_get_ro(host);
1551 sdhci_runtime_pm_put(host);
1552 return ret;
1553}
1554
1555static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1556{
1557 if (host->flags & SDHCI_DEVICE_DEAD)
1558 goto out;
1559
1560 if (enable)
1561 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1562 else
1563 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1564
1565 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1566 if (host->runtime_suspended)
1567 goto out;
1568
1569 if (enable)
1570 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1571 else
1572 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1573out:
1574 mmiowb();
1575}
1576
1577static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1578{
1579 struct sdhci_host *host = mmc_priv(mmc);
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(&host->lock, flags);
1583 sdhci_enable_sdio_irq_nolock(host, enable);
1584 spin_unlock_irqrestore(&host->lock, flags);
1585}
1586
1587static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1588 struct mmc_ios *ios)
1589{
1590 u8 pwr;
1591 u16 clk, ctrl;
1592 u32 present_state;
1593
1594 /*
1595 * Signal Voltage Switching is only applicable for Host Controllers
1596 * v3.00 and above.
1597 */
1598 if (host->version < SDHCI_SPEC_300)
1599 return 0;
1600
1601 /*
1602 * We first check whether the request is to set signalling voltage
1603 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1604 */
1605 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1606 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1607 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1608 ctrl &= ~SDHCI_CTRL_VDD_180;
1609 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1610
1611 /* Wait for 5ms */
1612 usleep_range(5000, 5500);
1613
1614 /* 3.3V regulator output should be stable within 5 ms */
1615 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1616 if (!(ctrl & SDHCI_CTRL_VDD_180))
1617 return 0;
1618 else {
1619 pr_info(DRIVER_NAME ": Switching to 3.3V "
1620 "signalling voltage failed\n");
1621 return -EIO;
1622 }
1623 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1624 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1625 /* Stop SDCLK */
1626 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1627 clk &= ~SDHCI_CLOCK_CARD_EN;
1628 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1629
1630 /* Check whether DAT[3:0] is 0000 */
1631 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1632 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1633 SDHCI_DATA_LVL_SHIFT)) {
1634 /*
1635 * Enable 1.8V Signal Enable in the Host Control2
1636 * register
1637 */
1638 ctrl |= SDHCI_CTRL_VDD_180;
1639 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1640
1641 /* Wait for 5ms */
1642 usleep_range(5000, 5500);
1643
1644 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1645 if (ctrl & SDHCI_CTRL_VDD_180) {
1646 /* Provide SDCLK again and wait for 1ms*/
1647 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1648 clk |= SDHCI_CLOCK_CARD_EN;
1649 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1650 usleep_range(1000, 1500);
1651
1652 /*
1653 * If DAT[3:0] level is 1111b, then the card
1654 * was successfully switched to 1.8V signaling.
1655 */
1656 present_state = sdhci_readl(host,
1657 SDHCI_PRESENT_STATE);
1658 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1659 SDHCI_DATA_LVL_MASK)
1660 return 0;
1661 }
1662 }
1663
1664 /*
1665 * If we are here, that means the switch to 1.8V signaling
1666 * failed. We power cycle the card, and retry initialization
1667 * sequence by setting S18R to 0.
1668 */
1669 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1670 pwr &= ~SDHCI_POWER_ON;
1671 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1672
1673 /* Wait for 1ms as per the spec */
1674 usleep_range(1000, 1500);
1675 pwr |= SDHCI_POWER_ON;
1676 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1677
1678 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1679 "voltage failed, retrying with S18R set to 0\n");
1680 return -EAGAIN;
1681 } else
1682 /* No signal voltage switch required */
1683 return 0;
1684}
1685
1686static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1687 struct mmc_ios *ios)
1688{
1689 struct sdhci_host *host = mmc_priv(mmc);
1690 int err;
1691
1692 if (host->version < SDHCI_SPEC_300)
1693 return 0;
1694 sdhci_runtime_pm_get(host);
1695 err = sdhci_do_start_signal_voltage_switch(host, ios);
1696 sdhci_runtime_pm_put(host);
1697 return err;
1698}
1699
1700static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1701{
1702 struct sdhci_host *host;
1703 u16 ctrl;
1704 u32 ier;
1705 int tuning_loop_counter = MAX_TUNING_LOOP;
1706 unsigned long timeout;
1707 int err = 0;
1708 bool requires_tuning_nonuhs = false;
1709
1710 host = mmc_priv(mmc);
1711
1712 sdhci_runtime_pm_get(host);
1713 disable_irq(host->irq);
1714 spin_lock(&host->lock);
1715
1716 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1717
1718 /*
1719 * The Host Controller needs tuning only in case of SDR104 mode
1720 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1721 * Capabilities register.
1722 * If the Host Controller supports the HS200 mode then the
1723 * tuning function has to be executed.
1724 */
1725 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1726 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1727 host->flags & SDHCI_HS200_NEEDS_TUNING))
1728 requires_tuning_nonuhs = true;
1729
1730 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1731 requires_tuning_nonuhs)
1732 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1733 else {
1734 spin_unlock(&host->lock);
1735 enable_irq(host->irq);
1736 sdhci_runtime_pm_put(host);
1737 return 0;
1738 }
1739
1740 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1741
1742 /*
1743 * As per the Host Controller spec v3.00, tuning command
1744 * generates Buffer Read Ready interrupt, so enable that.
1745 *
1746 * Note: The spec clearly says that when tuning sequence
1747 * is being performed, the controller does not generate
1748 * interrupts other than Buffer Read Ready interrupt. But
1749 * to make sure we don't hit a controller bug, we _only_
1750 * enable Buffer Read Ready interrupt here.
1751 */
1752 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1753 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1754
1755 /*
1756 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1757 * of loops reaches 40 times or a timeout of 150ms occurs.
1758 */
1759 timeout = 150;
1760 do {
1761 struct mmc_command cmd = {0};
1762 struct mmc_request mrq = {NULL};
1763
1764 if (!tuning_loop_counter && !timeout)
1765 break;
1766
1767 cmd.opcode = opcode;
1768 cmd.arg = 0;
1769 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1770 cmd.retries = 0;
1771 cmd.data = NULL;
1772 cmd.error = 0;
1773
1774 mrq.cmd = &cmd;
1775 host->mrq = &mrq;
1776
1777 /*
1778 * In response to CMD19, the card sends 64 bytes of tuning
1779 * block to the Host Controller. So we set the block size
1780 * to 64 here.
1781 */
1782 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1783 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1784 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1785 SDHCI_BLOCK_SIZE);
1786 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1787 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1788 SDHCI_BLOCK_SIZE);
1789 } else {
1790 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1791 SDHCI_BLOCK_SIZE);
1792 }
1793
1794 /*
1795 * The tuning block is sent by the card to the host controller.
1796 * So we set the TRNS_READ bit in the Transfer Mode register.
1797 * This also takes care of setting DMA Enable and Multi Block
1798 * Select in the same register to 0.
1799 */
1800 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1801
1802 sdhci_send_command(host, &cmd);
1803
1804 host->cmd = NULL;
1805 host->mrq = NULL;
1806
1807 spin_unlock(&host->lock);
1808 enable_irq(host->irq);
1809
1810 /* Wait for Buffer Read Ready interrupt */
1811 wait_event_interruptible_timeout(host->buf_ready_int,
1812 (host->tuning_done == 1),
1813 msecs_to_jiffies(50));
1814 disable_irq(host->irq);
1815 spin_lock(&host->lock);
1816
1817 if (!host->tuning_done) {
1818 pr_info(DRIVER_NAME ": Timeout waiting for "
1819 "Buffer Read Ready interrupt during tuning "
1820 "procedure, falling back to fixed sampling "
1821 "clock\n");
1822 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1823 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1824 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1825 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1826
1827 err = -EIO;
1828 goto out;
1829 }
1830
1831 host->tuning_done = 0;
1832
1833 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1834 tuning_loop_counter--;
1835 timeout--;
1836 mdelay(1);
1837 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1838
1839 /*
1840 * The Host Driver has exhausted the maximum number of loops allowed,
1841 * so use fixed sampling frequency.
1842 */
1843 if (!tuning_loop_counter || !timeout) {
1844 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1845 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1846 } else {
1847 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1848 pr_info(DRIVER_NAME ": Tuning procedure"
1849 " failed, falling back to fixed sampling"
1850 " clock\n");
1851 err = -EIO;
1852 }
1853 }
1854
1855out:
1856 /*
1857 * If this is the very first time we are here, we start the retuning
1858 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1859 * flag won't be set, we check this condition before actually starting
1860 * the timer.
1861 */
1862 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1863 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1864 mod_timer(&host->tuning_timer, jiffies +
1865 host->tuning_count * HZ);
1866 /* Tuning mode 1 limits the maximum data length to 4MB */
1867 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1868 } else {
1869 host->flags &= ~SDHCI_NEEDS_RETUNING;
1870 /* Reload the new initial value for timer */
1871 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1872 mod_timer(&host->tuning_timer, jiffies +
1873 host->tuning_count * HZ);
1874 }
1875
1876 /*
1877 * In case tuning fails, host controllers which support re-tuning can
1878 * try tuning again at a later time, when the re-tuning timer expires.
1879 * So for these controllers, we return 0. Since there might be other
1880 * controllers who do not have this capability, we return error for
1881 * them.
1882 */
1883 if (err && host->tuning_count &&
1884 host->tuning_mode == SDHCI_TUNING_MODE_1)
1885 err = 0;
1886
1887 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1888 spin_unlock(&host->lock);
1889 enable_irq(host->irq);
1890 sdhci_runtime_pm_put(host);
1891
1892 return err;
1893}
1894
1895static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1896{
1897 u16 ctrl;
1898 unsigned long flags;
1899
1900 /* Host Controller v3.00 defines preset value registers */
1901 if (host->version < SDHCI_SPEC_300)
1902 return;
1903
1904 spin_lock_irqsave(&host->lock, flags);
1905
1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907
1908 /*
1909 * We only enable or disable Preset Value if they are not already
1910 * enabled or disabled respectively. Otherwise, we bail out.
1911 */
1912 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1913 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1914 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1915 host->flags |= SDHCI_PV_ENABLED;
1916 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1917 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1918 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1919 host->flags &= ~SDHCI_PV_ENABLED;
1920 }
1921
1922 spin_unlock_irqrestore(&host->lock, flags);
1923}
1924
1925static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1926{
1927 struct sdhci_host *host = mmc_priv(mmc);
1928
1929 sdhci_runtime_pm_get(host);
1930 sdhci_do_enable_preset_value(host, enable);
1931 sdhci_runtime_pm_put(host);
1932}
1933
1934static const struct mmc_host_ops sdhci_ops = {
1935 .request = sdhci_request,
1936 .set_ios = sdhci_set_ios,
1937 .get_ro = sdhci_get_ro,
1938 .hw_reset = sdhci_hw_reset,
1939 .enable_sdio_irq = sdhci_enable_sdio_irq,
1940 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1941 .execute_tuning = sdhci_execute_tuning,
1942 .enable_preset_value = sdhci_enable_preset_value,
1943};
1944
1945/*****************************************************************************\
1946 * *
1947 * Tasklets *
1948 * *
1949\*****************************************************************************/
1950
1951static void sdhci_tasklet_card(unsigned long param)
1952{
1953 struct sdhci_host *host;
1954 unsigned long flags;
1955
1956 host = (struct sdhci_host*)param;
1957
1958 spin_lock_irqsave(&host->lock, flags);
1959
1960 /* Check host->mrq first in case we are runtime suspended */
1961 if (host->mrq &&
1962 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1963 pr_err("%s: Card removed during transfer!\n",
1964 mmc_hostname(host->mmc));
1965 pr_err("%s: Resetting controller.\n",
1966 mmc_hostname(host->mmc));
1967
1968 sdhci_reset(host, SDHCI_RESET_CMD);
1969 sdhci_reset(host, SDHCI_RESET_DATA);
1970
1971 host->mrq->cmd->error = -ENOMEDIUM;
1972 tasklet_schedule(&host->finish_tasklet);
1973 }
1974
1975 spin_unlock_irqrestore(&host->lock, flags);
1976
1977 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1978}
1979
1980static void sdhci_tasklet_finish(unsigned long param)
1981{
1982 struct sdhci_host *host;
1983 unsigned long flags;
1984 struct mmc_request *mrq;
1985
1986 host = (struct sdhci_host*)param;
1987
1988 spin_lock_irqsave(&host->lock, flags);
1989
1990 /*
1991 * If this tasklet gets rescheduled while running, it will
1992 * be run again afterwards but without any active request.
1993 */
1994 if (!host->mrq) {
1995 spin_unlock_irqrestore(&host->lock, flags);
1996 return;
1997 }
1998
1999 del_timer(&host->timer);
2000
2001 mrq = host->mrq;
2002
2003 /*
2004 * The controller needs a reset of internal state machines
2005 * upon error conditions.
2006 */
2007 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2008 ((mrq->cmd && mrq->cmd->error) ||
2009 (mrq->data && (mrq->data->error ||
2010 (mrq->data->stop && mrq->data->stop->error))) ||
2011 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2012
2013 /* Some controllers need this kick or reset won't work here */
2014 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2015 unsigned int clock;
2016
2017 /* This is to force an update */
2018 clock = host->clock;
2019 host->clock = 0;
2020 sdhci_set_clock(host, clock);
2021 }
2022
2023 /* Spec says we should do both at the same time, but Ricoh
2024 controllers do not like that. */
2025 sdhci_reset(host, SDHCI_RESET_CMD);
2026 sdhci_reset(host, SDHCI_RESET_DATA);
2027 }
2028
2029 host->mrq = NULL;
2030 host->cmd = NULL;
2031 host->data = NULL;
2032
2033#ifndef SDHCI_USE_LEDS_CLASS
2034 sdhci_deactivate_led(host);
2035#endif
2036
2037 mmiowb();
2038 spin_unlock_irqrestore(&host->lock, flags);
2039
2040 mmc_request_done(host->mmc, mrq);
2041 sdhci_runtime_pm_put(host);
2042}
2043
2044static void sdhci_timeout_timer(unsigned long data)
2045{
2046 struct sdhci_host *host;
2047 unsigned long flags;
2048
2049 host = (struct sdhci_host*)data;
2050
2051 spin_lock_irqsave(&host->lock, flags);
2052
2053 if (host->mrq) {
2054 pr_err("%s: Timeout waiting for hardware "
2055 "interrupt.\n", mmc_hostname(host->mmc));
2056 sdhci_dumpregs(host);
2057
2058 if (host->data) {
2059 host->data->error = -ETIMEDOUT;
2060 sdhci_finish_data(host);
2061 } else {
2062 if (host->cmd)
2063 host->cmd->error = -ETIMEDOUT;
2064 else
2065 host->mrq->cmd->error = -ETIMEDOUT;
2066
2067 tasklet_schedule(&host->finish_tasklet);
2068 }
2069 }
2070
2071 mmiowb();
2072 spin_unlock_irqrestore(&host->lock, flags);
2073}
2074
2075static void sdhci_tuning_timer(unsigned long data)
2076{
2077 struct sdhci_host *host;
2078 unsigned long flags;
2079
2080 host = (struct sdhci_host *)data;
2081
2082 spin_lock_irqsave(&host->lock, flags);
2083
2084 host->flags |= SDHCI_NEEDS_RETUNING;
2085
2086 spin_unlock_irqrestore(&host->lock, flags);
2087}
2088
2089/*****************************************************************************\
2090 * *
2091 * Interrupt handling *
2092 * *
2093\*****************************************************************************/
2094
2095static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2096{
2097 BUG_ON(intmask == 0);
2098
2099 if (!host->cmd) {
2100 pr_err("%s: Got command interrupt 0x%08x even "
2101 "though no command operation was in progress.\n",
2102 mmc_hostname(host->mmc), (unsigned)intmask);
2103 sdhci_dumpregs(host);
2104 return;
2105 }
2106
2107 if (intmask & SDHCI_INT_TIMEOUT)
2108 host->cmd->error = -ETIMEDOUT;
2109 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2110 SDHCI_INT_INDEX))
2111 host->cmd->error = -EILSEQ;
2112
2113 if (host->cmd->error) {
2114 tasklet_schedule(&host->finish_tasklet);
2115 return;
2116 }
2117
2118 /*
2119 * The host can send and interrupt when the busy state has
2120 * ended, allowing us to wait without wasting CPU cycles.
2121 * Unfortunately this is overloaded on the "data complete"
2122 * interrupt, so we need to take some care when handling
2123 * it.
2124 *
2125 * Note: The 1.0 specification is a bit ambiguous about this
2126 * feature so there might be some problems with older
2127 * controllers.
2128 */
2129 if (host->cmd->flags & MMC_RSP_BUSY) {
2130 if (host->cmd->data)
2131 DBG("Cannot wait for busy signal when also "
2132 "doing a data transfer");
2133 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2134 return;
2135
2136 /* The controller does not support the end-of-busy IRQ,
2137 * fall through and take the SDHCI_INT_RESPONSE */
2138 }
2139
2140 if (intmask & SDHCI_INT_RESPONSE)
2141 sdhci_finish_command(host);
2142}
2143
2144#ifdef CONFIG_MMC_DEBUG
2145static void sdhci_show_adma_error(struct sdhci_host *host)
2146{
2147 const char *name = mmc_hostname(host->mmc);
2148 u8 *desc = host->adma_desc;
2149 __le32 *dma;
2150 __le16 *len;
2151 u8 attr;
2152
2153 sdhci_dumpregs(host);
2154
2155 while (true) {
2156 dma = (__le32 *)(desc + 4);
2157 len = (__le16 *)(desc + 2);
2158 attr = *desc;
2159
2160 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2161 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2162
2163 desc += 8;
2164
2165 if (attr & 2)
2166 break;
2167 }
2168}
2169#else
2170static void sdhci_show_adma_error(struct sdhci_host *host) { }
2171#endif
2172
2173static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2174{
2175 u32 command;
2176 BUG_ON(intmask == 0);
2177
2178 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2179 if (intmask & SDHCI_INT_DATA_AVAIL) {
2180 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2181 if (command == MMC_SEND_TUNING_BLOCK ||
2182 command == MMC_SEND_TUNING_BLOCK_HS200) {
2183 host->tuning_done = 1;
2184 wake_up(&host->buf_ready_int);
2185 return;
2186 }
2187 }
2188
2189 if (!host->data) {
2190 /*
2191 * The "data complete" interrupt is also used to
2192 * indicate that a busy state has ended. See comment
2193 * above in sdhci_cmd_irq().
2194 */
2195 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2196 if (intmask & SDHCI_INT_DATA_END) {
2197 sdhci_finish_command(host);
2198 return;
2199 }
2200 }
2201
2202 pr_err("%s: Got data interrupt 0x%08x even "
2203 "though no data operation was in progress.\n",
2204 mmc_hostname(host->mmc), (unsigned)intmask);
2205 sdhci_dumpregs(host);
2206
2207 return;
2208 }
2209
2210 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2211 host->data->error = -ETIMEDOUT;
2212 else if (intmask & SDHCI_INT_DATA_END_BIT)
2213 host->data->error = -EILSEQ;
2214 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2215 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2216 != MMC_BUS_TEST_R)
2217 host->data->error = -EILSEQ;
2218 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2219 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2220 sdhci_show_adma_error(host);
2221 host->data->error = -EIO;
2222 }
2223
2224 if (host->data->error)
2225 sdhci_finish_data(host);
2226 else {
2227 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2228 sdhci_transfer_pio(host);
2229
2230 /*
2231 * We currently don't do anything fancy with DMA
2232 * boundaries, but as we can't disable the feature
2233 * we need to at least restart the transfer.
2234 *
2235 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2236 * should return a valid address to continue from, but as
2237 * some controllers are faulty, don't trust them.
2238 */
2239 if (intmask & SDHCI_INT_DMA_END) {
2240 u32 dmastart, dmanow;
2241 dmastart = sg_dma_address(host->data->sg);
2242 dmanow = dmastart + host->data->bytes_xfered;
2243 /*
2244 * Force update to the next DMA block boundary.
2245 */
2246 dmanow = (dmanow &
2247 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2248 SDHCI_DEFAULT_BOUNDARY_SIZE;
2249 host->data->bytes_xfered = dmanow - dmastart;
2250 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2251 " next 0x%08x\n",
2252 mmc_hostname(host->mmc), dmastart,
2253 host->data->bytes_xfered, dmanow);
2254 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2255 }
2256
2257 if (intmask & SDHCI_INT_DATA_END) {
2258 if (host->cmd) {
2259 /*
2260 * Data managed to finish before the
2261 * command completed. Make sure we do
2262 * things in the proper order.
2263 */
2264 host->data_early = 1;
2265 } else {
2266 sdhci_finish_data(host);
2267 }
2268 }
2269 }
2270}
2271
2272static irqreturn_t sdhci_irq(int irq, void *dev_id)
2273{
2274 irqreturn_t result;
2275 struct sdhci_host *host = dev_id;
2276 u32 intmask, unexpected = 0;
2277 int cardint = 0, max_loops = 16;
2278
2279 spin_lock(&host->lock);
2280
2281 if (host->runtime_suspended) {
2282 spin_unlock(&host->lock);
2283 pr_warning("%s: got irq while runtime suspended\n",
2284 mmc_hostname(host->mmc));
2285 return IRQ_HANDLED;
2286 }
2287
2288 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2289
2290 if (!intmask || intmask == 0xffffffff) {
2291 result = IRQ_NONE;
2292 goto out;
2293 }
2294
2295again:
2296 DBG("*** %s got interrupt: 0x%08x\n",
2297 mmc_hostname(host->mmc), intmask);
2298
2299 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2300 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2301 SDHCI_CARD_PRESENT;
2302
2303 /*
2304 * There is a observation on i.mx esdhc. INSERT bit will be
2305 * immediately set again when it gets cleared, if a card is
2306 * inserted. We have to mask the irq to prevent interrupt
2307 * storm which will freeze the system. And the REMOVE gets
2308 * the same situation.
2309 *
2310 * More testing are needed here to ensure it works for other
2311 * platforms though.
2312 */
2313 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2314 SDHCI_INT_CARD_REMOVE);
2315 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2316 SDHCI_INT_CARD_INSERT);
2317
2318 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2319 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2320 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2321 tasklet_schedule(&host->card_tasklet);
2322 }
2323
2324 if (intmask & SDHCI_INT_CMD_MASK) {
2325 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2326 SDHCI_INT_STATUS);
2327 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2328 }
2329
2330 if (intmask & SDHCI_INT_DATA_MASK) {
2331 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2332 SDHCI_INT_STATUS);
2333 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2334 }
2335
2336 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2337
2338 intmask &= ~SDHCI_INT_ERROR;
2339
2340 if (intmask & SDHCI_INT_BUS_POWER) {
2341 pr_err("%s: Card is consuming too much power!\n",
2342 mmc_hostname(host->mmc));
2343 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2344 }
2345
2346 intmask &= ~SDHCI_INT_BUS_POWER;
2347
2348 if (intmask & SDHCI_INT_CARD_INT)
2349 cardint = 1;
2350
2351 intmask &= ~SDHCI_INT_CARD_INT;
2352
2353 if (intmask) {
2354 unexpected |= intmask;
2355 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2356 }
2357
2358 result = IRQ_HANDLED;
2359
2360 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2361 if (intmask && --max_loops)
2362 goto again;
2363out:
2364 spin_unlock(&host->lock);
2365
2366 if (unexpected) {
2367 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2368 mmc_hostname(host->mmc), unexpected);
2369 sdhci_dumpregs(host);
2370 }
2371 /*
2372 * We have to delay this as it calls back into the driver.
2373 */
2374 if (cardint)
2375 mmc_signal_sdio_irq(host->mmc);
2376
2377 return result;
2378}
2379
2380/*****************************************************************************\
2381 * *
2382 * Suspend/resume *
2383 * *
2384\*****************************************************************************/
2385
2386#ifdef CONFIG_PM
2387
2388int sdhci_suspend_host(struct sdhci_host *host)
2389{
2390 int ret;
2391 bool has_tuning_timer;
2392
2393 if (host->ops->platform_suspend)
2394 host->ops->platform_suspend(host);
2395
2396 sdhci_disable_card_detection(host);
2397
2398 /* Disable tuning since we are suspending */
2399 has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2400 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2401 if (has_tuning_timer) {
2402 del_timer_sync(&host->tuning_timer);
2403 host->flags &= ~SDHCI_NEEDS_RETUNING;
2404 }
2405
2406 ret = mmc_suspend_host(host->mmc);
2407 if (ret) {
2408 if (has_tuning_timer) {
2409 host->flags |= SDHCI_NEEDS_RETUNING;
2410 mod_timer(&host->tuning_timer, jiffies +
2411 host->tuning_count * HZ);
2412 }
2413
2414 sdhci_enable_card_detection(host);
2415
2416 return ret;
2417 }
2418
2419 free_irq(host->irq, host);
2420
2421 return ret;
2422}
2423
2424EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2425
2426int sdhci_resume_host(struct sdhci_host *host)
2427{
2428 int ret;
2429
2430 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2431 if (host->ops->enable_dma)
2432 host->ops->enable_dma(host);
2433 }
2434
2435 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2436 mmc_hostname(host->mmc), host);
2437 if (ret)
2438 return ret;
2439
2440 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2441 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2442 /* Card keeps power but host controller does not */
2443 sdhci_init(host, 0);
2444 host->pwr = 0;
2445 host->clock = 0;
2446 sdhci_do_set_ios(host, &host->mmc->ios);
2447 } else {
2448 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2449 mmiowb();
2450 }
2451
2452 ret = mmc_resume_host(host->mmc);
2453 sdhci_enable_card_detection(host);
2454
2455 if (host->ops->platform_resume)
2456 host->ops->platform_resume(host);
2457
2458 /* Set the re-tuning expiration flag */
2459 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2460 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2461 host->flags |= SDHCI_NEEDS_RETUNING;
2462
2463 return ret;
2464}
2465
2466EXPORT_SYMBOL_GPL(sdhci_resume_host);
2467
2468void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2469{
2470 u8 val;
2471 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2472 val |= SDHCI_WAKE_ON_INT;
2473 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2474}
2475
2476EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2477
2478#endif /* CONFIG_PM */
2479
2480#ifdef CONFIG_PM_RUNTIME
2481
2482static int sdhci_runtime_pm_get(struct sdhci_host *host)
2483{
2484 return pm_runtime_get_sync(host->mmc->parent);
2485}
2486
2487static int sdhci_runtime_pm_put(struct sdhci_host *host)
2488{
2489 pm_runtime_mark_last_busy(host->mmc->parent);
2490 return pm_runtime_put_autosuspend(host->mmc->parent);
2491}
2492
2493int sdhci_runtime_suspend_host(struct sdhci_host *host)
2494{
2495 unsigned long flags;
2496 int ret = 0;
2497
2498 /* Disable tuning since we are suspending */
2499 if (host->version >= SDHCI_SPEC_300 &&
2500 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2501 del_timer_sync(&host->tuning_timer);
2502 host->flags &= ~SDHCI_NEEDS_RETUNING;
2503 }
2504
2505 spin_lock_irqsave(&host->lock, flags);
2506 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2507 spin_unlock_irqrestore(&host->lock, flags);
2508
2509 synchronize_irq(host->irq);
2510
2511 spin_lock_irqsave(&host->lock, flags);
2512 host->runtime_suspended = true;
2513 spin_unlock_irqrestore(&host->lock, flags);
2514
2515 return ret;
2516}
2517EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2518
2519int sdhci_runtime_resume_host(struct sdhci_host *host)
2520{
2521 unsigned long flags;
2522 int ret = 0, host_flags = host->flags;
2523
2524 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2525 if (host->ops->enable_dma)
2526 host->ops->enable_dma(host);
2527 }
2528
2529 sdhci_init(host, 0);
2530
2531 /* Force clock and power re-program */
2532 host->pwr = 0;
2533 host->clock = 0;
2534 sdhci_do_set_ios(host, &host->mmc->ios);
2535
2536 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2537 if (host_flags & SDHCI_PV_ENABLED)
2538 sdhci_do_enable_preset_value(host, true);
2539
2540 /* Set the re-tuning expiration flag */
2541 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2542 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2543 host->flags |= SDHCI_NEEDS_RETUNING;
2544
2545 spin_lock_irqsave(&host->lock, flags);
2546
2547 host->runtime_suspended = false;
2548
2549 /* Enable SDIO IRQ */
2550 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2551 sdhci_enable_sdio_irq_nolock(host, true);
2552
2553 /* Enable Card Detection */
2554 sdhci_enable_card_detection(host);
2555
2556 spin_unlock_irqrestore(&host->lock, flags);
2557
2558 return ret;
2559}
2560EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2561
2562#endif
2563
2564/*****************************************************************************\
2565 * *
2566 * Device allocation/registration *
2567 * *
2568\*****************************************************************************/
2569
2570struct sdhci_host *sdhci_alloc_host(struct device *dev,
2571 size_t priv_size)
2572{
2573 struct mmc_host *mmc;
2574 struct sdhci_host *host;
2575
2576 WARN_ON(dev == NULL);
2577
2578 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2579 if (!mmc)
2580 return ERR_PTR(-ENOMEM);
2581
2582 host = mmc_priv(mmc);
2583 host->mmc = mmc;
2584
2585 return host;
2586}
2587
2588EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2589
2590int sdhci_add_host(struct sdhci_host *host)
2591{
2592 struct mmc_host *mmc;
2593 u32 caps[2];
2594 u32 max_current_caps;
2595 unsigned int ocr_avail;
2596 int ret;
2597
2598 WARN_ON(host == NULL);
2599 if (host == NULL)
2600 return -EINVAL;
2601
2602 mmc = host->mmc;
2603
2604 if (debug_quirks)
2605 host->quirks = debug_quirks;
2606 if (debug_quirks2)
2607 host->quirks2 = debug_quirks2;
2608
2609 sdhci_reset(host, SDHCI_RESET_ALL);
2610
2611 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2612 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2613 >> SDHCI_SPEC_VER_SHIFT;
2614 if (host->version > SDHCI_SPEC_300) {
2615 pr_err("%s: Unknown controller version (%d). "
2616 "You may experience problems.\n", mmc_hostname(mmc),
2617 host->version);
2618 }
2619
2620 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2621 sdhci_readl(host, SDHCI_CAPABILITIES);
2622
2623 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2624 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2625
2626 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2627 host->flags |= SDHCI_USE_SDMA;
2628 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2629 DBG("Controller doesn't have SDMA capability\n");
2630 else
2631 host->flags |= SDHCI_USE_SDMA;
2632
2633 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2634 (host->flags & SDHCI_USE_SDMA)) {
2635 DBG("Disabling DMA as it is marked broken\n");
2636 host->flags &= ~SDHCI_USE_SDMA;
2637 }
2638
2639 if ((host->version >= SDHCI_SPEC_200) &&
2640 (caps[0] & SDHCI_CAN_DO_ADMA2))
2641 host->flags |= SDHCI_USE_ADMA;
2642
2643 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2644 (host->flags & SDHCI_USE_ADMA)) {
2645 DBG("Disabling ADMA as it is marked broken\n");
2646 host->flags &= ~SDHCI_USE_ADMA;
2647 }
2648
2649 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2650 if (host->ops->enable_dma) {
2651 if (host->ops->enable_dma(host)) {
2652 pr_warning("%s: No suitable DMA "
2653 "available. Falling back to PIO.\n",
2654 mmc_hostname(mmc));
2655 host->flags &=
2656 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2657 }
2658 }
2659 }
2660
2661 if (host->flags & SDHCI_USE_ADMA) {
2662 /*
2663 * We need to allocate descriptors for all sg entries
2664 * (128) and potentially one alignment transfer for
2665 * each of those entries.
2666 */
2667 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2668 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2669 if (!host->adma_desc || !host->align_buffer) {
2670 kfree(host->adma_desc);
2671 kfree(host->align_buffer);
2672 pr_warning("%s: Unable to allocate ADMA "
2673 "buffers. Falling back to standard DMA.\n",
2674 mmc_hostname(mmc));
2675 host->flags &= ~SDHCI_USE_ADMA;
2676 }
2677 }
2678
2679 /*
2680 * If we use DMA, then it's up to the caller to set the DMA
2681 * mask, but PIO does not need the hw shim so we set a new
2682 * mask here in that case.
2683 */
2684 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2685 host->dma_mask = DMA_BIT_MASK(64);
2686 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2687 }
2688
2689 if (host->version >= SDHCI_SPEC_300)
2690 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2691 >> SDHCI_CLOCK_BASE_SHIFT;
2692 else
2693 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2694 >> SDHCI_CLOCK_BASE_SHIFT;
2695
2696 host->max_clk *= 1000000;
2697 if (host->max_clk == 0 || host->quirks &
2698 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2699 if (!host->ops->get_max_clock) {
2700 pr_err("%s: Hardware doesn't specify base clock "
2701 "frequency.\n", mmc_hostname(mmc));
2702 return -ENODEV;
2703 }
2704 host->max_clk = host->ops->get_max_clock(host);
2705 }
2706
2707 /*
2708 * In case of Host Controller v3.00, find out whether clock
2709 * multiplier is supported.
2710 */
2711 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2712 SDHCI_CLOCK_MUL_SHIFT;
2713
2714 /*
2715 * In case the value in Clock Multiplier is 0, then programmable
2716 * clock mode is not supported, otherwise the actual clock
2717 * multiplier is one more than the value of Clock Multiplier
2718 * in the Capabilities Register.
2719 */
2720 if (host->clk_mul)
2721 host->clk_mul += 1;
2722
2723 /*
2724 * Set host parameters.
2725 */
2726 mmc->ops = &sdhci_ops;
2727 mmc->f_max = host->max_clk;
2728 if (host->ops->get_min_clock)
2729 mmc->f_min = host->ops->get_min_clock(host);
2730 else if (host->version >= SDHCI_SPEC_300) {
2731 if (host->clk_mul) {
2732 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2733 mmc->f_max = host->max_clk * host->clk_mul;
2734 } else
2735 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2736 } else
2737 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2738
2739 host->timeout_clk =
2740 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2741 if (host->timeout_clk == 0) {
2742 if (host->ops->get_timeout_clock) {
2743 host->timeout_clk = host->ops->get_timeout_clock(host);
2744 } else if (!(host->quirks &
2745 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2746 pr_err("%s: Hardware doesn't specify timeout clock "
2747 "frequency.\n", mmc_hostname(mmc));
2748 return -ENODEV;
2749 }
2750 }
2751 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2752 host->timeout_clk *= 1000;
2753
2754 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2755 host->timeout_clk = mmc->f_max / 1000;
2756
2757 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2758
2759 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2760
2761 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2762 host->flags |= SDHCI_AUTO_CMD12;
2763
2764 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2765 if ((host->version >= SDHCI_SPEC_300) &&
2766 ((host->flags & SDHCI_USE_ADMA) ||
2767 !(host->flags & SDHCI_USE_SDMA))) {
2768 host->flags |= SDHCI_AUTO_CMD23;
2769 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2770 } else {
2771 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2772 }
2773
2774 /*
2775 * A controller may support 8-bit width, but the board itself
2776 * might not have the pins brought out. Boards that support
2777 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2778 * their platform code before calling sdhci_add_host(), and we
2779 * won't assume 8-bit width for hosts without that CAP.
2780 */
2781 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2782 mmc->caps |= MMC_CAP_4_BIT_DATA;
2783
2784 if (caps[0] & SDHCI_CAN_DO_HISPD)
2785 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2786
2787 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2788 mmc_card_is_removable(mmc))
2789 mmc->caps |= MMC_CAP_NEEDS_POLL;
2790
2791 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2792 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2793 SDHCI_SUPPORT_DDR50))
2794 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2795
2796 /* SDR104 supports also implies SDR50 support */
2797 if (caps[1] & SDHCI_SUPPORT_SDR104)
2798 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2799 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2800 mmc->caps |= MMC_CAP_UHS_SDR50;
2801
2802 if (caps[1] & SDHCI_SUPPORT_DDR50)
2803 mmc->caps |= MMC_CAP_UHS_DDR50;
2804
2805 /* Does the host need tuning for SDR50? */
2806 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2807 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2808
2809 /* Does the host need tuning for HS200? */
2810 if (mmc->caps2 & MMC_CAP2_HS200)
2811 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2812
2813 /* Driver Type(s) (A, C, D) supported by the host */
2814 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2815 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2816 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2817 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2818 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2819 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2820
2821 /*
2822 * If Power Off Notify capability is enabled by the host,
2823 * set notify to short power off notify timeout value.
2824 */
2825 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2826 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2827 else
2828 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2829
2830 /* Initial value for re-tuning timer count */
2831 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2832 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2833
2834 /*
2835 * In case Re-tuning Timer is not disabled, the actual value of
2836 * re-tuning timer will be 2 ^ (n - 1).
2837 */
2838 if (host->tuning_count)
2839 host->tuning_count = 1 << (host->tuning_count - 1);
2840
2841 /* Re-tuning mode supported by the Host Controller */
2842 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2843 SDHCI_RETUNING_MODE_SHIFT;
2844
2845 ocr_avail = 0;
2846 /*
2847 * According to SD Host Controller spec v3.00, if the Host System
2848 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2849 * the value is meaningful only if Voltage Support in the Capabilities
2850 * register is set. The actual current value is 4 times the register
2851 * value.
2852 */
2853 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2854
2855 if (caps[0] & SDHCI_CAN_VDD_330) {
2856 int max_current_330;
2857
2858 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2859
2860 max_current_330 = ((max_current_caps &
2861 SDHCI_MAX_CURRENT_330_MASK) >>
2862 SDHCI_MAX_CURRENT_330_SHIFT) *
2863 SDHCI_MAX_CURRENT_MULTIPLIER;
2864
2865 if (max_current_330 > 150)
2866 mmc->caps |= MMC_CAP_SET_XPC_330;
2867 }
2868 if (caps[0] & SDHCI_CAN_VDD_300) {
2869 int max_current_300;
2870
2871 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2872
2873 max_current_300 = ((max_current_caps &
2874 SDHCI_MAX_CURRENT_300_MASK) >>
2875 SDHCI_MAX_CURRENT_300_SHIFT) *
2876 SDHCI_MAX_CURRENT_MULTIPLIER;
2877
2878 if (max_current_300 > 150)
2879 mmc->caps |= MMC_CAP_SET_XPC_300;
2880 }
2881 if (caps[0] & SDHCI_CAN_VDD_180) {
2882 int max_current_180;
2883
2884 ocr_avail |= MMC_VDD_165_195;
2885
2886 max_current_180 = ((max_current_caps &
2887 SDHCI_MAX_CURRENT_180_MASK) >>
2888 SDHCI_MAX_CURRENT_180_SHIFT) *
2889 SDHCI_MAX_CURRENT_MULTIPLIER;
2890
2891 if (max_current_180 > 150)
2892 mmc->caps |= MMC_CAP_SET_XPC_180;
2893
2894 /* Maximum current capabilities of the host at 1.8V */
2895 if (max_current_180 >= 800)
2896 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2897 else if (max_current_180 >= 600)
2898 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2899 else if (max_current_180 >= 400)
2900 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2901 else
2902 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2903 }
2904
2905 mmc->ocr_avail = ocr_avail;
2906 mmc->ocr_avail_sdio = ocr_avail;
2907 if (host->ocr_avail_sdio)
2908 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2909 mmc->ocr_avail_sd = ocr_avail;
2910 if (host->ocr_avail_sd)
2911 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2912 else /* normal SD controllers don't support 1.8V */
2913 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2914 mmc->ocr_avail_mmc = ocr_avail;
2915 if (host->ocr_avail_mmc)
2916 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2917
2918 if (mmc->ocr_avail == 0) {
2919 pr_err("%s: Hardware doesn't report any "
2920 "support voltages.\n", mmc_hostname(mmc));
2921 return -ENODEV;
2922 }
2923
2924 spin_lock_init(&host->lock);
2925
2926 /*
2927 * Maximum number of segments. Depends on if the hardware
2928 * can do scatter/gather or not.
2929 */
2930 if (host->flags & SDHCI_USE_ADMA)
2931 mmc->max_segs = 128;
2932 else if (host->flags & SDHCI_USE_SDMA)
2933 mmc->max_segs = 1;
2934 else /* PIO */
2935 mmc->max_segs = 128;
2936
2937 /*
2938 * Maximum number of sectors in one transfer. Limited by DMA boundary
2939 * size (512KiB).
2940 */
2941 mmc->max_req_size = 524288;
2942
2943 /*
2944 * Maximum segment size. Could be one segment with the maximum number
2945 * of bytes. When doing hardware scatter/gather, each entry cannot
2946 * be larger than 64 KiB though.
2947 */
2948 if (host->flags & SDHCI_USE_ADMA) {
2949 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2950 mmc->max_seg_size = 65535;
2951 else
2952 mmc->max_seg_size = 65536;
2953 } else {
2954 mmc->max_seg_size = mmc->max_req_size;
2955 }
2956
2957 /*
2958 * Maximum block size. This varies from controller to controller and
2959 * is specified in the capabilities register.
2960 */
2961 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2962 mmc->max_blk_size = 2;
2963 } else {
2964 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2965 SDHCI_MAX_BLOCK_SHIFT;
2966 if (mmc->max_blk_size >= 3) {
2967 pr_warning("%s: Invalid maximum block size, "
2968 "assuming 512 bytes\n", mmc_hostname(mmc));
2969 mmc->max_blk_size = 0;
2970 }
2971 }
2972
2973 mmc->max_blk_size = 512 << mmc->max_blk_size;
2974
2975 /*
2976 * Maximum block count.
2977 */
2978 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2979
2980 /*
2981 * Init tasklets.
2982 */
2983 tasklet_init(&host->card_tasklet,
2984 sdhci_tasklet_card, (unsigned long)host);
2985 tasklet_init(&host->finish_tasklet,
2986 sdhci_tasklet_finish, (unsigned long)host);
2987
2988 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2989
2990 if (host->version >= SDHCI_SPEC_300) {
2991 init_waitqueue_head(&host->buf_ready_int);
2992
2993 /* Initialize re-tuning timer */
2994 init_timer(&host->tuning_timer);
2995 host->tuning_timer.data = (unsigned long)host;
2996 host->tuning_timer.function = sdhci_tuning_timer;
2997 }
2998
2999 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3000 mmc_hostname(mmc), host);
3001 if (ret)
3002 goto untasklet;
3003
3004 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3005 if (IS_ERR(host->vmmc)) {
3006 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3007 host->vmmc = NULL;
3008 }
3009
3010 sdhci_init(host, 0);
3011
3012#ifdef CONFIG_MMC_DEBUG
3013 sdhci_dumpregs(host);
3014#endif
3015
3016#ifdef SDHCI_USE_LEDS_CLASS
3017 snprintf(host->led_name, sizeof(host->led_name),
3018 "%s::", mmc_hostname(mmc));
3019 host->led.name = host->led_name;
3020 host->led.brightness = LED_OFF;
3021 host->led.default_trigger = mmc_hostname(mmc);
3022 host->led.brightness_set = sdhci_led_control;
3023
3024 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3025 if (ret)
3026 goto reset;
3027#endif
3028
3029 mmiowb();
3030
3031 mmc_add_host(mmc);
3032
3033 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3034 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3035 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3036 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3037
3038 sdhci_enable_card_detection(host);
3039
3040 return 0;
3041
3042#ifdef SDHCI_USE_LEDS_CLASS
3043reset:
3044 sdhci_reset(host, SDHCI_RESET_ALL);
3045 free_irq(host->irq, host);
3046#endif
3047untasklet:
3048 tasklet_kill(&host->card_tasklet);
3049 tasklet_kill(&host->finish_tasklet);
3050
3051 return ret;
3052}
3053
3054EXPORT_SYMBOL_GPL(sdhci_add_host);
3055
3056void sdhci_remove_host(struct sdhci_host *host, int dead)
3057{
3058 unsigned long flags;
3059
3060 if (dead) {
3061 spin_lock_irqsave(&host->lock, flags);
3062
3063 host->flags |= SDHCI_DEVICE_DEAD;
3064
3065 if (host->mrq) {
3066 pr_err("%s: Controller removed during "
3067 " transfer!\n", mmc_hostname(host->mmc));
3068
3069 host->mrq->cmd->error = -ENOMEDIUM;
3070 tasklet_schedule(&host->finish_tasklet);
3071 }
3072
3073 spin_unlock_irqrestore(&host->lock, flags);
3074 }
3075
3076 sdhci_disable_card_detection(host);
3077
3078 mmc_remove_host(host->mmc);
3079
3080#ifdef SDHCI_USE_LEDS_CLASS
3081 led_classdev_unregister(&host->led);
3082#endif
3083
3084 if (!dead)
3085 sdhci_reset(host, SDHCI_RESET_ALL);
3086
3087 free_irq(host->irq, host);
3088
3089 del_timer_sync(&host->timer);
3090 if (host->version >= SDHCI_SPEC_300)
3091 del_timer_sync(&host->tuning_timer);
3092
3093 tasklet_kill(&host->card_tasklet);
3094 tasklet_kill(&host->finish_tasklet);
3095
3096 if (host->vmmc)
3097 regulator_put(host->vmmc);
3098
3099 kfree(host->adma_desc);
3100 kfree(host->align_buffer);
3101
3102 host->adma_desc = NULL;
3103 host->align_buffer = NULL;
3104}
3105
3106EXPORT_SYMBOL_GPL(sdhci_remove_host);
3107
3108void sdhci_free_host(struct sdhci_host *host)
3109{
3110 mmc_free_host(host->mmc);
3111}
3112
3113EXPORT_SYMBOL_GPL(sdhci_free_host);
3114
3115/*****************************************************************************\
3116 * *
3117 * Driver init/exit *
3118 * *
3119\*****************************************************************************/
3120
3121static int __init sdhci_drv_init(void)
3122{
3123 pr_info(DRIVER_NAME
3124 ": Secure Digital Host Controller Interface driver\n");
3125 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3126
3127 return 0;
3128}
3129
3130static void __exit sdhci_drv_exit(void)
3131{
3132}
3133
3134module_init(sdhci_drv_init);
3135module_exit(sdhci_drv_exit);
3136
3137module_param(debug_quirks, uint, 0444);
3138module_param(debug_quirks2, uint, 0444);
3139
3140MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3141MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3142MODULE_LICENSE("GPL");
3143
3144MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3145MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");