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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28
29/* From the VESA DisplayPort spec */
30
31#define AUX_NATIVE_WRITE 0x8
32#define AUX_NATIVE_READ 0x9
33#define AUX_I2C_WRITE 0x0
34#define AUX_I2C_READ 0x1
35#define AUX_I2C_STATUS 0x2
36#define AUX_I2C_MOT 0x4
37
38#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
39#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
40#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
41#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
42
43#define AUX_I2C_REPLY_ACK (0x0 << 6)
44#define AUX_I2C_REPLY_NACK (0x1 << 6)
45#define AUX_I2C_REPLY_DEFER (0x2 << 6)
46#define AUX_I2C_REPLY_MASK (0x3 << 6)
47
48/* AUX CH addresses */
49/* DPCD */
50#define DP_DPCD_REV 0x000
51
52#define DP_MAX_LINK_RATE 0x001
53
54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f
56# define DP_TPS3_SUPPORTED (1 << 6)
57# define DP_ENHANCED_FRAME_CAP (1 << 7)
58
59#define DP_MAX_DOWNSPREAD 0x003
60# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
61
62#define DP_NORP 0x004
63
64#define DP_DOWNSTREAMPORT_PRESENT 0x005
65# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
66# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
67/* 00b = DisplayPort */
68/* 01b = Analog */
69/* 10b = TMDS or HDMI */
70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3)
72
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
77/* link configuration */
78#define DP_LINK_BW_SET 0x100
79# define DP_LINK_BW_1_62 0x06
80# define DP_LINK_BW_2_7 0x0a
81# define DP_LINK_BW_5_4 0x14
82
83#define DP_LANE_COUNT_SET 0x101
84# define DP_LANE_COUNT_MASK 0x0f
85# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
86
87#define DP_TRAINING_PATTERN_SET 0x102
88# define DP_TRAINING_PATTERN_DISABLE 0
89# define DP_TRAINING_PATTERN_1 1
90# define DP_TRAINING_PATTERN_2 2
91# define DP_TRAINING_PATTERN_3 3
92# define DP_TRAINING_PATTERN_MASK 0x3
93
94# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
95# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
96# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
97# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
98# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
99
100# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
101# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
102
103# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
104# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
105# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
106# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
107
108#define DP_TRAINING_LANE0_SET 0x103
109#define DP_TRAINING_LANE1_SET 0x104
110#define DP_TRAINING_LANE2_SET 0x105
111#define DP_TRAINING_LANE3_SET 0x106
112
113# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
114# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
115# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
116# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
117# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
118# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
119# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
120
121# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
122# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
123# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
124# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
125# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
126
127# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
128# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
129
130#define DP_DOWNSPREAD_CTRL 0x107
131# define DP_SPREAD_AMP_0_5 (1 << 4)
132
133#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
134# define DP_SET_ANSI_8B10B (1 << 0)
135
136#define DP_LANE0_1_STATUS 0x202
137#define DP_LANE2_3_STATUS 0x203
138# define DP_LANE_CR_DONE (1 << 0)
139# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
140# define DP_LANE_SYMBOL_LOCKED (1 << 2)
141
142#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
143 DP_LANE_CHANNEL_EQ_DONE | \
144 DP_LANE_SYMBOL_LOCKED)
145
146#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
147
148#define DP_INTERLANE_ALIGN_DONE (1 << 0)
149#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
150#define DP_LINK_STATUS_UPDATED (1 << 7)
151
152#define DP_SINK_STATUS 0x205
153
154#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
155#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
156
157#define DP_ADJUST_REQUEST_LANE0_1 0x206
158#define DP_ADJUST_REQUEST_LANE2_3 0x207
159# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
160# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
161# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
162# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
163# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
164# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
165# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
166# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
167
168#define DP_SET_POWER 0x600
169# define DP_SET_POWER_D0 0x1
170# define DP_SET_POWER_D3 0x2
171
172#define MODE_I2C_START 1
173#define MODE_I2C_WRITE 2
174#define MODE_I2C_READ 4
175#define MODE_I2C_STOP 8
176
177struct i2c_algo_dp_aux_data {
178 bool running;
179 u16 address;
180 int (*aux_ch) (struct i2c_adapter *adapter,
181 int mode, uint8_t write_byte,
182 uint8_t *read_byte);
183};
184
185int
186i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
187
188#endif /* _DRM_DP_HELPER_H_ */
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
44
45#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
47#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
49#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
50#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
53
54#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
58
59#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
63
64/* AUX CH addresses */
65/* DPCD */
66#define DP_DPCD_REV 0x000
67# define DP_DPCD_REV_10 0x10
68# define DP_DPCD_REV_11 0x11
69# define DP_DPCD_REV_12 0x12
70# define DP_DPCD_REV_13 0x13
71# define DP_DPCD_REV_14 0x14
72
73#define DP_MAX_LINK_RATE 0x001
74
75#define DP_MAX_LANE_COUNT 0x002
76# define DP_MAX_LANE_COUNT_MASK 0x1f
77# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
78# define DP_ENHANCED_FRAME_CAP (1 << 7)
79
80#define DP_MAX_DOWNSPREAD 0x003
81# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
82# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
83# define DP_TPS4_SUPPORTED (1 << 7)
84
85#define DP_NORP 0x004
86
87#define DP_DOWNSTREAMPORT_PRESENT 0x005
88# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
89# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
90# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
91# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
92# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
93# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
94# define DP_FORMAT_CONVERSION (1 << 3)
95# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
96
97#define DP_MAIN_LINK_CHANNEL_CODING 0x006
98
99#define DP_DOWN_STREAM_PORT_COUNT 0x007
100# define DP_PORT_COUNT_MASK 0x0f
101# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
102# define DP_OUI_SUPPORT (1 << 7)
103
104#define DP_RECEIVE_PORT_0_CAP_0 0x008
105# define DP_LOCAL_EDID_PRESENT (1 << 1)
106# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
107
108#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
109
110#define DP_RECEIVE_PORT_1_CAP_0 0x00a
111#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
112
113#define DP_I2C_SPEED_CAP 0x00c /* DPI */
114# define DP_I2C_SPEED_1K 0x01
115# define DP_I2C_SPEED_5K 0x02
116# define DP_I2C_SPEED_10K 0x04
117# define DP_I2C_SPEED_100K 0x08
118# define DP_I2C_SPEED_400K 0x10
119# define DP_I2C_SPEED_1M 0x20
120
121#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
122# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
123# define DP_FRAMING_CHANGE_CAP (1 << 1)
124# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
125
126#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
127# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
128# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
129
130#define DP_ADAPTER_CAP 0x00f /* 1.2 */
131# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
132# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
133
134#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
135# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
136
137/* Multiple stream transport */
138#define DP_FAUX_CAP 0x020 /* 1.2 */
139# define DP_FAUX_CAP_1 (1 << 0)
140
141#define DP_MSTM_CAP 0x021 /* 1.2 */
142# define DP_MST_CAP (1 << 0)
143
144#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
145
146/* AV_SYNC_DATA_BLOCK 1.2 */
147#define DP_AV_GRANULARITY 0x023
148# define DP_AG_FACTOR_MASK (0xf << 0)
149# define DP_AG_FACTOR_3MS (0 << 0)
150# define DP_AG_FACTOR_2MS (1 << 0)
151# define DP_AG_FACTOR_1MS (2 << 0)
152# define DP_AG_FACTOR_500US (3 << 0)
153# define DP_AG_FACTOR_200US (4 << 0)
154# define DP_AG_FACTOR_100US (5 << 0)
155# define DP_AG_FACTOR_10US (6 << 0)
156# define DP_AG_FACTOR_1US (7 << 0)
157# define DP_VG_FACTOR_MASK (0xf << 4)
158# define DP_VG_FACTOR_3MS (0 << 4)
159# define DP_VG_FACTOR_2MS (1 << 4)
160# define DP_VG_FACTOR_1MS (2 << 4)
161# define DP_VG_FACTOR_500US (3 << 4)
162# define DP_VG_FACTOR_200US (4 << 4)
163# define DP_VG_FACTOR_100US (5 << 4)
164
165#define DP_AUD_DEC_LAT0 0x024
166#define DP_AUD_DEC_LAT1 0x025
167
168#define DP_AUD_PP_LAT0 0x026
169#define DP_AUD_PP_LAT1 0x027
170
171#define DP_VID_INTER_LAT 0x028
172
173#define DP_VID_PROG_LAT 0x029
174
175#define DP_REP_LAT 0x02a
176
177#define DP_AUD_DEL_INS0 0x02b
178#define DP_AUD_DEL_INS1 0x02c
179#define DP_AUD_DEL_INS2 0x02d
180/* End of AV_SYNC_DATA_BLOCK */
181
182#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
183# define DP_ALPM_CAP (1 << 0)
184
185#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
186# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
187
188#define DP_GUID 0x030 /* 1.2 */
189
190#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
191# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
192
193#define DP_DSC_REV 0x061
194# define DP_DSC_MAJOR_MASK (0xf << 0)
195# define DP_DSC_MINOR_MASK (0xf << 4)
196# define DP_DSC_MAJOR_SHIFT 0
197# define DP_DSC_MINOR_SHIFT 4
198
199#define DP_DSC_RC_BUF_BLK_SIZE 0x062
200# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
201# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
202# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
203# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
204
205#define DP_DSC_RC_BUF_SIZE 0x063
206
207#define DP_DSC_SLICE_CAP_1 0x064
208# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
209# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
210# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
211# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
212# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
213# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
214# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
215
216#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
217# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
218# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
219# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
220# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
221# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
222# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
223# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
224# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
225# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
226# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
227
228#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
229# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
230
231#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
232
233#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
234# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
235# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
236
237#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
238# define DP_DSC_RGB (1 << 0)
239# define DP_DSC_YCbCr444 (1 << 1)
240# define DP_DSC_YCbCr422_Simple (1 << 2)
241# define DP_DSC_YCbCr422_Native (1 << 3)
242# define DP_DSC_YCbCr420_Native (1 << 4)
243
244#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
245# define DP_DSC_8_BPC (1 << 1)
246# define DP_DSC_10_BPC (1 << 2)
247# define DP_DSC_12_BPC (1 << 3)
248
249#define DP_DSC_PEAK_THROUGHPUT 0x06B
250# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
251# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
252# define DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED 0
253# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
254# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
255# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
256# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
257# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
258# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
259# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
260# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
261# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
262# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
263# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
264# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
265# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
266# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
267# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 4)
268# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
269# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
270# define DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED 0
271# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
272# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
273# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
274# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
275# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
276# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
277# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
278# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
279# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
280# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
281# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
282# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
283# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
284# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
285# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
286
287#define DP_DSC_MAX_SLICE_WIDTH 0x06C
288#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
289#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
290
291#define DP_DSC_SLICE_CAP_2 0x06D
292# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
293# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
294# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
295
296#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
297# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
298# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
299# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
300# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
301# define DP_DSC_BITS_PER_PIXEL_1 0x4
302
303#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
304# define DP_PSR_IS_SUPPORTED 1
305# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
306# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
307
308#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
309# define DP_PSR_NO_TRAIN_ON_EXIT 1
310# define DP_PSR_SETUP_TIME_330 (0 << 1)
311# define DP_PSR_SETUP_TIME_275 (1 << 1)
312# define DP_PSR_SETUP_TIME_220 (2 << 1)
313# define DP_PSR_SETUP_TIME_165 (3 << 1)
314# define DP_PSR_SETUP_TIME_110 (4 << 1)
315# define DP_PSR_SETUP_TIME_55 (5 << 1)
316# define DP_PSR_SETUP_TIME_0 (6 << 1)
317# define DP_PSR_SETUP_TIME_MASK (7 << 1)
318# define DP_PSR_SETUP_TIME_SHIFT 1
319# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
320# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
321
322#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
323#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
324
325/*
326 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
327 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
328 * each port's descriptor is one byte wide. If it was set, each port's is
329 * four bytes wide, starting with the one byte from the base info. As of
330 * DP interop v1.1a only VGA defines additional detail.
331 */
332
333/* offset 0 */
334#define DP_DOWNSTREAM_PORT_0 0x80
335# define DP_DS_PORT_TYPE_MASK (7 << 0)
336# define DP_DS_PORT_TYPE_DP 0
337# define DP_DS_PORT_TYPE_VGA 1
338# define DP_DS_PORT_TYPE_DVI 2
339# define DP_DS_PORT_TYPE_HDMI 3
340# define DP_DS_PORT_TYPE_NON_EDID 4
341# define DP_DS_PORT_TYPE_DP_DUALMODE 5
342# define DP_DS_PORT_TYPE_WIRELESS 6
343# define DP_DS_PORT_HPD (1 << 3)
344/* offset 1 for VGA is maximum megapixels per second / 8 */
345/* offset 2 */
346# define DP_DS_MAX_BPC_MASK (3 << 0)
347# define DP_DS_8BPC 0
348# define DP_DS_10BPC 1
349# define DP_DS_12BPC 2
350# define DP_DS_16BPC 3
351
352/* DP Forward error Correction Registers */
353#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
354# define DP_FEC_CAPABLE (1 << 0)
355# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
356# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
357# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
358
359/* DP Extended DSC Capabilities */
360#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
361#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
362#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
363
364/* link configuration */
365#define DP_LINK_BW_SET 0x100
366# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
367# define DP_LINK_BW_1_62 0x06
368# define DP_LINK_BW_2_7 0x0a
369# define DP_LINK_BW_5_4 0x14 /* 1.2 */
370# define DP_LINK_BW_8_1 0x1e /* 1.4 */
371
372#define DP_LANE_COUNT_SET 0x101
373# define DP_LANE_COUNT_MASK 0x0f
374# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
375
376#define DP_TRAINING_PATTERN_SET 0x102
377# define DP_TRAINING_PATTERN_DISABLE 0
378# define DP_TRAINING_PATTERN_1 1
379# define DP_TRAINING_PATTERN_2 2
380# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
381# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
382# define DP_TRAINING_PATTERN_MASK 0x3
383# define DP_TRAINING_PATTERN_MASK_1_4 0xf
384
385/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
386# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
387# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
388# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
389# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
390# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
391
392# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
393# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
394
395# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
396# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
397# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
398# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
399
400#define DP_TRAINING_LANE0_SET 0x103
401#define DP_TRAINING_LANE1_SET 0x104
402#define DP_TRAINING_LANE2_SET 0x105
403#define DP_TRAINING_LANE3_SET 0x106
404
405# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
406# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
407# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
408# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
409# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
410# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
411# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
412
413# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
414# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
415# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
416# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
417# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
418
419# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
420# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
421
422#define DP_DOWNSPREAD_CTRL 0x107
423# define DP_SPREAD_AMP_0_5 (1 << 4)
424# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
425
426#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
427# define DP_SET_ANSI_8B10B (1 << 0)
428
429#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
430/* bitmask as for DP_I2C_SPEED_CAP */
431
432#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
433# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
434# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
435# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
436
437#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
438#define DP_LINK_QUAL_LANE1_SET 0x10c
439#define DP_LINK_QUAL_LANE2_SET 0x10d
440#define DP_LINK_QUAL_LANE3_SET 0x10e
441# define DP_LINK_QUAL_PATTERN_DISABLE 0
442# define DP_LINK_QUAL_PATTERN_D10_2 1
443# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
444# define DP_LINK_QUAL_PATTERN_PRBS7 3
445# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
446# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
447# define DP_LINK_QUAL_PATTERN_MASK 7
448
449#define DP_TRAINING_LANE0_1_SET2 0x10f
450#define DP_TRAINING_LANE2_3_SET2 0x110
451# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
452# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
453# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
454# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
455
456#define DP_MSTM_CTRL 0x111 /* 1.2 */
457# define DP_MST_EN (1 << 0)
458# define DP_UP_REQ_EN (1 << 1)
459# define DP_UPSTREAM_IS_SRC (1 << 2)
460
461#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
462#define DP_AUDIO_DELAY1 0x113
463#define DP_AUDIO_DELAY2 0x114
464
465#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
466# define DP_LINK_RATE_SET_SHIFT 0
467# define DP_LINK_RATE_SET_MASK (7 << 0)
468
469#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
470# define DP_ALPM_ENABLE (1 << 0)
471# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
472
473#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
474# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
475# define DP_IRQ_HPD_ENABLE (1 << 1)
476
477#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
478# define DP_PWR_NOT_NEEDED (1 << 0)
479
480#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
481# define DP_FEC_READY (1 << 0)
482# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
483# define DP_FEC_ERR_COUNT_DIS (0 << 1)
484# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
485# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
486# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
487# define DP_FEC_LANE_SELECT_MASK (3 << 4)
488# define DP_FEC_LANE_0_SELECT (0 << 4)
489# define DP_FEC_LANE_1_SELECT (1 << 4)
490# define DP_FEC_LANE_2_SELECT (2 << 4)
491# define DP_FEC_LANE_3_SELECT (3 << 4)
492
493#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
494# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
495
496#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
497# define DP_DECOMPRESSION_EN (1 << 0)
498
499#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
500# define DP_PSR_ENABLE (1 << 0)
501# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
502# define DP_PSR_CRC_VERIFICATION (1 << 2)
503# define DP_PSR_FRAME_CAPTURE (1 << 3)
504# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
505# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
506# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
507
508#define DP_ADAPTER_CTRL 0x1a0
509# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
510
511#define DP_BRANCH_DEVICE_CTRL 0x1a1
512# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
513
514#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
515#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
516#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
517
518#define DP_SINK_COUNT 0x200
519/* prior to 1.2 bit 7 was reserved mbz */
520# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
521# define DP_SINK_CP_READY (1 << 6)
522
523#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
524# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
525# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
526# define DP_CP_IRQ (1 << 2)
527# define DP_MCCS_IRQ (1 << 3)
528# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
529# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
530# define DP_SINK_SPECIFIC_IRQ (1 << 6)
531
532#define DP_LANE0_1_STATUS 0x202
533#define DP_LANE2_3_STATUS 0x203
534# define DP_LANE_CR_DONE (1 << 0)
535# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
536# define DP_LANE_SYMBOL_LOCKED (1 << 2)
537
538#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
539 DP_LANE_CHANNEL_EQ_DONE | \
540 DP_LANE_SYMBOL_LOCKED)
541
542#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
543
544#define DP_INTERLANE_ALIGN_DONE (1 << 0)
545#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
546#define DP_LINK_STATUS_UPDATED (1 << 7)
547
548#define DP_SINK_STATUS 0x205
549
550#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
551#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
552
553#define DP_ADJUST_REQUEST_LANE0_1 0x206
554#define DP_ADJUST_REQUEST_LANE2_3 0x207
555# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
556# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
557# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
558# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
559# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
560# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
561# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
562# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
563
564#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
565
566#define DP_TEST_REQUEST 0x218
567# define DP_TEST_LINK_TRAINING (1 << 0)
568# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
569# define DP_TEST_LINK_EDID_READ (1 << 2)
570# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
571# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
572# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
573# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
574
575#define DP_TEST_LINK_RATE 0x219
576# define DP_LINK_RATE_162 (0x6)
577# define DP_LINK_RATE_27 (0xa)
578
579#define DP_TEST_LANE_COUNT 0x220
580
581#define DP_TEST_PATTERN 0x221
582# define DP_NO_TEST_PATTERN 0x0
583# define DP_COLOR_RAMP 0x1
584# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
585# define DP_COLOR_SQUARE 0x3
586
587#define DP_TEST_H_TOTAL_HI 0x222
588#define DP_TEST_H_TOTAL_LO 0x223
589
590#define DP_TEST_V_TOTAL_HI 0x224
591#define DP_TEST_V_TOTAL_LO 0x225
592
593#define DP_TEST_H_START_HI 0x226
594#define DP_TEST_H_START_LO 0x227
595
596#define DP_TEST_V_START_HI 0x228
597#define DP_TEST_V_START_LO 0x229
598
599#define DP_TEST_HSYNC_HI 0x22A
600# define DP_TEST_HSYNC_POLARITY (1 << 7)
601# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
602#define DP_TEST_HSYNC_WIDTH_LO 0x22B
603
604#define DP_TEST_VSYNC_HI 0x22C
605# define DP_TEST_VSYNC_POLARITY (1 << 7)
606# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
607#define DP_TEST_VSYNC_WIDTH_LO 0x22D
608
609#define DP_TEST_H_WIDTH_HI 0x22E
610#define DP_TEST_H_WIDTH_LO 0x22F
611
612#define DP_TEST_V_HEIGHT_HI 0x230
613#define DP_TEST_V_HEIGHT_LO 0x231
614
615#define DP_TEST_MISC0 0x232
616# define DP_TEST_SYNC_CLOCK (1 << 0)
617# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
618# define DP_TEST_COLOR_FORMAT_SHIFT 1
619# define DP_COLOR_FORMAT_RGB (0 << 1)
620# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
621# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
622# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
623# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
624# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
625# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
626# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
627# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
628# define DP_TEST_BIT_DEPTH_SHIFT 5
629# define DP_TEST_BIT_DEPTH_6 (0 << 5)
630# define DP_TEST_BIT_DEPTH_8 (1 << 5)
631# define DP_TEST_BIT_DEPTH_10 (2 << 5)
632# define DP_TEST_BIT_DEPTH_12 (3 << 5)
633# define DP_TEST_BIT_DEPTH_16 (4 << 5)
634
635#define DP_TEST_MISC1 0x233
636# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
637# define DP_TEST_INTERLACED (1 << 1)
638
639#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
640
641#define DP_TEST_MISC0 0x232
642
643#define DP_TEST_CRC_R_CR 0x240
644#define DP_TEST_CRC_G_Y 0x242
645#define DP_TEST_CRC_B_CB 0x244
646
647#define DP_TEST_SINK_MISC 0x246
648# define DP_TEST_CRC_SUPPORTED (1 << 5)
649# define DP_TEST_COUNT_MASK 0xf
650
651#define DP_TEST_PHY_PATTERN 0x248
652#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
653#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
654#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
655#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
656#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
657#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
658#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
659#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
660#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
661#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
662
663#define DP_TEST_RESPONSE 0x260
664# define DP_TEST_ACK (1 << 0)
665# define DP_TEST_NAK (1 << 1)
666# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
667
668#define DP_TEST_EDID_CHECKSUM 0x261
669
670#define DP_TEST_SINK 0x270
671# define DP_TEST_SINK_START (1 << 0)
672#define DP_TEST_AUDIO_MODE 0x271
673#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
674#define DP_TEST_AUDIO_PERIOD_CH1 0x273
675#define DP_TEST_AUDIO_PERIOD_CH2 0x274
676#define DP_TEST_AUDIO_PERIOD_CH3 0x275
677#define DP_TEST_AUDIO_PERIOD_CH4 0x276
678#define DP_TEST_AUDIO_PERIOD_CH5 0x277
679#define DP_TEST_AUDIO_PERIOD_CH6 0x278
680#define DP_TEST_AUDIO_PERIOD_CH7 0x279
681#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
682
683#define DP_FEC_STATUS 0x280 /* 1.4 */
684# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
685# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
686
687#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
688
689#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
690# define DP_FEC_ERROR_COUNT_MASK 0x7F
691# define DP_FEC_ERR_COUNT_VALID (1 << 7)
692
693#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
694# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
695# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
696
697#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
698/* up to ID_SLOT_63 at 0x2ff */
699
700#define DP_SOURCE_OUI 0x300
701#define DP_SINK_OUI 0x400
702#define DP_BRANCH_OUI 0x500
703#define DP_BRANCH_ID 0x503
704#define DP_BRANCH_REVISION_START 0x509
705#define DP_BRANCH_HW_REV 0x509
706#define DP_BRANCH_SW_REV 0x50A
707
708#define DP_SET_POWER 0x600
709# define DP_SET_POWER_D0 0x1
710# define DP_SET_POWER_D3 0x2
711# define DP_SET_POWER_MASK 0x3
712# define DP_SET_POWER_D3_AUX_ON 0x5
713
714#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
715# define DP_EDP_11 0x00
716# define DP_EDP_12 0x01
717# define DP_EDP_13 0x02
718# define DP_EDP_14 0x03
719# define DP_EDP_14a 0x04 /* eDP 1.4a */
720# define DP_EDP_14b 0x05 /* eDP 1.4b */
721
722#define DP_EDP_GENERAL_CAP_1 0x701
723# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
724# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
725# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
726# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
727# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
728# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
729# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
730# define DP_EDP_SET_POWER_CAP (1 << 7)
731
732#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
733# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
734# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
735# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
736# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
737# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
738# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
739# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
740# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
741
742#define DP_EDP_GENERAL_CAP_2 0x703
743# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
744
745#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
746# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
747# define DP_EDP_X_REGION_CAP_SHIFT 0
748# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
749# define DP_EDP_Y_REGION_CAP_SHIFT 4
750
751#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
752# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
753# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
754# define DP_EDP_FRC_ENABLE (1 << 2)
755# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
756# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
757
758#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
759# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
760# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
761# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
762# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
763# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
764# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
765# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
766# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
767# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
768# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
769
770#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
771#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
772
773#define DP_EDP_PWMGEN_BIT_COUNT 0x724
774#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
775#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
776# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
777
778#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
779
780#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
781# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
782
783#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
784#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
785#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
786
787#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
788#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
789#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
790
791#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
792#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
793
794#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
795#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
796
797#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
798#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
799#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
800#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
801
802#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
803/* 0-5 sink count */
804# define DP_SINK_COUNT_CP_READY (1 << 6)
805
806#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
807
808#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
809# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
810# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
811# define DP_CEC_IRQ (1 << 2)
812
813#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
814
815#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
816# define DP_PSR_LINK_CRC_ERROR (1 << 0)
817# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
818# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
819
820#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
821# define DP_PSR_CAPS_CHANGE (1 << 0)
822
823#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
824# define DP_PSR_SINK_INACTIVE 0
825# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
826# define DP_PSR_SINK_ACTIVE_RFB 2
827# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
828# define DP_PSR_SINK_ACTIVE_RESYNC 4
829# define DP_PSR_SINK_INTERNAL_ERROR 7
830# define DP_PSR_SINK_STATE_MASK 0x07
831
832#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
833# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
834# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
835# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
836# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
837
838#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
839# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
840# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
841# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
842# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
843# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
844# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
845# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
846
847#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
848# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
849
850#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
851#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
852#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
853#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
854
855#define DP_DP13_DPCD_REV 0x2200
856#define DP_DP13_MAX_LINK_RATE 0x2201
857
858#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
859# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
860# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
861# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
862# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
863# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
864# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
865# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
866# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
867
868/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
869#define DP_CEC_TUNNELING_CAPABILITY 0x3000
870# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
871# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
872# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
873
874#define DP_CEC_TUNNELING_CONTROL 0x3001
875# define DP_CEC_TUNNELING_ENABLE (1 << 0)
876# define DP_CEC_SNOOPING_ENABLE (1 << 1)
877
878#define DP_CEC_RX_MESSAGE_INFO 0x3002
879# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
880# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
881# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
882# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
883# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
884# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
885
886#define DP_CEC_TX_MESSAGE_INFO 0x3003
887# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
888# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
889# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
890# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
891# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
892
893#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
894# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
895# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
896# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
897# define DP_CEC_TX_LINE_ERROR (1 << 5)
898# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
899# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
900
901#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
902# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
903# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
904# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
905# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
906# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
907# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
908# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
909# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
910#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
911# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
912# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
913# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
914# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
915# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
916# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
917# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
918# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
919
920#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
921#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
922#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
923
924#define DP_AUX_HDCP_BKSV 0x68000
925#define DP_AUX_HDCP_RI_PRIME 0x68005
926#define DP_AUX_HDCP_AKSV 0x68007
927#define DP_AUX_HDCP_AN 0x6800C
928#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
929#define DP_AUX_HDCP_BCAPS 0x68028
930# define DP_BCAPS_REPEATER_PRESENT BIT(1)
931# define DP_BCAPS_HDCP_CAPABLE BIT(0)
932#define DP_AUX_HDCP_BSTATUS 0x68029
933# define DP_BSTATUS_REAUTH_REQ BIT(3)
934# define DP_BSTATUS_LINK_FAILURE BIT(2)
935# define DP_BSTATUS_R0_PRIME_READY BIT(1)
936# define DP_BSTATUS_READY BIT(0)
937#define DP_AUX_HDCP_BINFO 0x6802A
938#define DP_AUX_HDCP_KSV_FIFO 0x6802C
939#define DP_AUX_HDCP_AINFO 0x6803B
940
941/* DP HDCP2.2 parameter offsets in DPCD address space */
942#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
943#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
944#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
945#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
946#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
947#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
948#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
949#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
950#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
951#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
952#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
953#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
954#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
955#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
956#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
957#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
958#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
959#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
960#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
961#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
962#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
963#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
964#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
965#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
966#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
967#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
968
969/* DP HDCP message start offsets in DPCD address space */
970#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
971#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
972#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
973#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
974#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
975#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
976 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
977#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
978#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
979#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
980#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
981#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
982#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
983#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
984
985#define HDCP_2_2_DP_RXSTATUS_LEN 1
986#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
987#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
988#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
989#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
990#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
991
992/* DP 1.2 Sideband message defines */
993/* peer device type - DP 1.2a Table 2-92 */
994#define DP_PEER_DEVICE_NONE 0x0
995#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
996#define DP_PEER_DEVICE_MST_BRANCHING 0x2
997#define DP_PEER_DEVICE_SST_SINK 0x3
998#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
999
1000/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1001#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1002#define DP_LINK_ADDRESS 0x01
1003#define DP_CONNECTION_STATUS_NOTIFY 0x02
1004#define DP_ENUM_PATH_RESOURCES 0x10
1005#define DP_ALLOCATE_PAYLOAD 0x11
1006#define DP_QUERY_PAYLOAD 0x12
1007#define DP_RESOURCE_STATUS_NOTIFY 0x13
1008#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1009#define DP_REMOTE_DPCD_READ 0x20
1010#define DP_REMOTE_DPCD_WRITE 0x21
1011#define DP_REMOTE_I2C_READ 0x22
1012#define DP_REMOTE_I2C_WRITE 0x23
1013#define DP_POWER_UP_PHY 0x24
1014#define DP_POWER_DOWN_PHY 0x25
1015#define DP_SINK_EVENT_NOTIFY 0x30
1016#define DP_QUERY_STREAM_ENC_STATUS 0x38
1017
1018/* DP 1.2 MST sideband reply types */
1019#define DP_SIDEBAND_REPLY_ACK 0x00
1020#define DP_SIDEBAND_REPLY_NAK 0x01
1021
1022/* DP 1.2 MST sideband nak reasons - table 2.84 */
1023#define DP_NAK_WRITE_FAILURE 0x01
1024#define DP_NAK_INVALID_READ 0x02
1025#define DP_NAK_CRC_FAILURE 0x03
1026#define DP_NAK_BAD_PARAM 0x04
1027#define DP_NAK_DEFER 0x05
1028#define DP_NAK_LINK_FAILURE 0x06
1029#define DP_NAK_NO_RESOURCES 0x07
1030#define DP_NAK_DPCD_FAIL 0x08
1031#define DP_NAK_I2C_NAK 0x09
1032#define DP_NAK_ALLOCATE_FAIL 0x0a
1033
1034#define MODE_I2C_START 1
1035#define MODE_I2C_WRITE 2
1036#define MODE_I2C_READ 4
1037#define MODE_I2C_STOP 8
1038
1039/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1040#define DP_MST_PHYSICAL_PORT_0 0
1041#define DP_MST_LOGICAL_PORT_0 8
1042
1043#define DP_LINK_STATUS_SIZE 6
1044bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1045 int lane_count);
1046bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1047 int lane_count);
1048u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1049 int lane);
1050u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1051 int lane);
1052
1053#define DP_BRANCH_OUI_HEADER_SIZE 0xc
1054#define DP_RECEIVER_CAP_SIZE 0xf
1055#define DP_DSC_RECEIVER_CAP_SIZE 0xf
1056#define EDP_PSR_RECEIVER_CAP_SIZE 2
1057#define EDP_DISPLAY_CTL_CAP_SIZE 3
1058
1059void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1060void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1061
1062u8 drm_dp_link_rate_to_bw_code(int link_rate);
1063int drm_dp_bw_code_to_link_rate(u8 link_bw);
1064
1065#define DP_SDP_AUDIO_TIMESTAMP 0x01
1066#define DP_SDP_AUDIO_STREAM 0x02
1067#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1068#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1069#define DP_SDP_ISRC 0x06 /* DP 1.2 */
1070#define DP_SDP_VSC 0x07 /* DP 1.2 */
1071#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1072#define DP_SDP_PPS 0x10 /* DP 1.4 */
1073#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1074#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1075/* 0x80+ CEA-861 infoframe types */
1076
1077/**
1078 * struct dp_sdp_header - DP secondary data packet header
1079 * @HB0: Secondary Data Packet ID
1080 * @HB1: Secondary Data Packet Type
1081 * @HB2: Secondary Data Packet Specific header, Byte 0
1082 * @HB3: Secondary Data packet Specific header, Byte 1
1083 */
1084struct dp_sdp_header {
1085 u8 HB0;
1086 u8 HB1;
1087 u8 HB2;
1088 u8 HB3;
1089} __packed;
1090
1091#define EDP_SDP_HEADER_REVISION_MASK 0x1F
1092#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1093#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1094
1095/**
1096 * struct dp_sdp - DP secondary data packet
1097 * @sdp_header: DP secondary data packet header
1098 * @db: DP secondaray data packet data blocks
1099 * VSC SDP Payload for PSR
1100 * db[0]: Stereo Interface
1101 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1102 * db[2]: CRC value bits 7:0 of the R or Cr component
1103 * db[3]: CRC value bits 15:8 of the R or Cr component
1104 * db[4]: CRC value bits 7:0 of the G or Y component
1105 * db[5]: CRC value bits 15:8 of the G or Y component
1106 * db[6]: CRC value bits 7:0 of the B or Cb component
1107 * db[7]: CRC value bits 15:8 of the B or Cb component
1108 * db[8] - db[31]: Reserved
1109 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1110 * db[0] - db[15]: Reserved
1111 * db[16]: Pixel Encoding and Colorimetry Formats
1112 * db[17]: Dynamic Range and Component Bit Depth
1113 * db[18]: Content Type
1114 * db[19] - db[31]: Reserved
1115 */
1116struct dp_sdp {
1117 struct dp_sdp_header sdp_header;
1118 u8 db[32];
1119} __packed;
1120
1121#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1122#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1123#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1124
1125int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1126
1127static inline int
1128drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1129{
1130 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1131}
1132
1133static inline u8
1134drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1135{
1136 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1137}
1138
1139static inline bool
1140drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1141{
1142 return dpcd[DP_DPCD_REV] >= 0x11 &&
1143 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1144}
1145
1146static inline bool
1147drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1148{
1149 return dpcd[DP_DPCD_REV] >= 0x12 &&
1150 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1151}
1152
1153static inline bool
1154drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1155{
1156 return dpcd[DP_DPCD_REV] >= 0x14 &&
1157 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1158}
1159
1160static inline u8
1161drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1162{
1163 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1164 DP_TRAINING_PATTERN_MASK;
1165}
1166
1167static inline bool
1168drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1169{
1170 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1171}
1172
1173/* DP/eDP DSC support */
1174u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1175 bool is_edp);
1176u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1177int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1178 u8 dsc_bpc[3]);
1179
1180static inline bool
1181drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1182{
1183 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1184 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1185}
1186
1187static inline u16
1188drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1189{
1190 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1191 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1192 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1193 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1194}
1195
1196static inline u32
1197drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1198{
1199 /* Max Slicewidth = Number of Pixels * 320 */
1200 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1201 DP_DSC_SLICE_WIDTH_MULTIPLIER;
1202}
1203
1204/* Forward Error Correction Support on DP 1.4 */
1205static inline bool
1206drm_dp_sink_supports_fec(const u8 fec_capable)
1207{
1208 return fec_capable & DP_FEC_CAPABLE;
1209}
1210
1211/*
1212 * DisplayPort AUX channel
1213 */
1214
1215/**
1216 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1217 * @address: address of the (first) register to access
1218 * @request: contains the type of transaction (see DP_AUX_* macros)
1219 * @reply: upon completion, contains the reply type of the transaction
1220 * @buffer: pointer to a transmission or reception buffer
1221 * @size: size of @buffer
1222 */
1223struct drm_dp_aux_msg {
1224 unsigned int address;
1225 u8 request;
1226 u8 reply;
1227 void *buffer;
1228 size_t size;
1229};
1230
1231struct cec_adapter;
1232struct edid;
1233
1234/**
1235 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1236 * @lock: mutex protecting this struct
1237 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1238 * @name: name of the CEC adapter
1239 * @parent: parent device of the CEC adapter
1240 * @unregister_work: unregister the CEC adapter
1241 */
1242struct drm_dp_aux_cec {
1243 struct mutex lock;
1244 struct cec_adapter *adap;
1245 const char *name;
1246 struct device *parent;
1247 struct delayed_work unregister_work;
1248};
1249
1250/**
1251 * struct drm_dp_aux - DisplayPort AUX channel
1252 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1253 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1254 * @dev: pointer to struct device that is the parent for this AUX channel
1255 * @crtc: backpointer to the crtc that is currently using this AUX channel
1256 * @hw_mutex: internal mutex used for locking transfers
1257 * @crc_work: worker that captures CRCs for each frame
1258 * @crc_count: counter of captured frame CRCs
1259 * @transfer: transfers a message representing a single AUX transaction
1260 *
1261 * The .dev field should be set to a pointer to the device that implements
1262 * the AUX channel.
1263 *
1264 * The .name field may be used to specify the name of the I2C adapter. If set to
1265 * NULL, dev_name() of .dev will be used.
1266 *
1267 * Drivers provide a hardware-specific implementation of how transactions
1268 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1269 * structure describing the transaction is passed into this function. Upon
1270 * success, the implementation should return the number of payload bytes
1271 * that were transferred, or a negative error-code on failure. Helpers
1272 * propagate errors from the .transfer() function, with the exception of
1273 * the -EBUSY error, which causes a transaction to be retried. On a short,
1274 * helpers will return -EPROTO to make it simpler to check for failure.
1275 *
1276 * An AUX channel can also be used to transport I2C messages to a sink. A
1277 * typical application of that is to access an EDID that's present in the
1278 * sink device. The .transfer() function can also be used to execute such
1279 * transactions. The drm_dp_aux_register() function registers an I2C
1280 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1281 * should call drm_dp_aux_unregister() to remove the I2C adapter.
1282 * The I2C adapter uses long transfers by default; if a partial response is
1283 * received, the adapter will drop down to the size given by the partial
1284 * response for this transaction only.
1285 *
1286 * Note that the aux helper code assumes that the .transfer() function
1287 * only modifies the reply field of the drm_dp_aux_msg structure. The
1288 * retry logic and i2c helpers assume this is the case.
1289 */
1290struct drm_dp_aux {
1291 const char *name;
1292 struct i2c_adapter ddc;
1293 struct device *dev;
1294 struct drm_crtc *crtc;
1295 struct mutex hw_mutex;
1296 struct work_struct crc_work;
1297 u8 crc_count;
1298 ssize_t (*transfer)(struct drm_dp_aux *aux,
1299 struct drm_dp_aux_msg *msg);
1300 /**
1301 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1302 */
1303 unsigned i2c_nack_count;
1304 /**
1305 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1306 */
1307 unsigned i2c_defer_count;
1308 /**
1309 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1310 */
1311 struct drm_dp_aux_cec cec;
1312 /**
1313 * @is_remote: Is this AUX CH actually using sideband messaging.
1314 */
1315 bool is_remote;
1316};
1317
1318ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1319 void *buffer, size_t size);
1320ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1321 void *buffer, size_t size);
1322
1323/**
1324 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1325 * @aux: DisplayPort AUX channel
1326 * @offset: address of the register to read
1327 * @valuep: location where the value of the register will be stored
1328 *
1329 * Returns the number of bytes transferred (1) on success, or a negative
1330 * error code on failure.
1331 */
1332static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1333 unsigned int offset, u8 *valuep)
1334{
1335 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1336}
1337
1338/**
1339 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1340 * @aux: DisplayPort AUX channel
1341 * @offset: address of the register to write
1342 * @value: value to write to the register
1343 *
1344 * Returns the number of bytes transferred (1) on success, or a negative
1345 * error code on failure.
1346 */
1347static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1348 unsigned int offset, u8 value)
1349{
1350 return drm_dp_dpcd_write(aux, offset, &value, 1);
1351}
1352
1353int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1354 u8 status[DP_LINK_STATUS_SIZE]);
1355
1356/*
1357 * DisplayPort link
1358 */
1359#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
1360
1361struct drm_dp_link {
1362 unsigned char revision;
1363 unsigned int rate;
1364 unsigned int num_lanes;
1365 unsigned long capabilities;
1366};
1367
1368int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1369int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1370int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1371int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1372int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1373 const u8 port_cap[4]);
1374int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1375 const u8 port_cap[4]);
1376int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1377void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1378 const u8 port_cap[4], struct drm_dp_aux *aux);
1379
1380void drm_dp_aux_init(struct drm_dp_aux *aux);
1381int drm_dp_aux_register(struct drm_dp_aux *aux);
1382void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1383
1384int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1385int drm_dp_stop_crc(struct drm_dp_aux *aux);
1386
1387struct drm_dp_dpcd_ident {
1388 u8 oui[3];
1389 u8 device_id[6];
1390 u8 hw_rev;
1391 u8 sw_major_rev;
1392 u8 sw_minor_rev;
1393} __packed;
1394
1395/**
1396 * struct drm_dp_desc - DP branch/sink device descriptor
1397 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1398 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1399 */
1400struct drm_dp_desc {
1401 struct drm_dp_dpcd_ident ident;
1402 u32 quirks;
1403};
1404
1405int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1406 bool is_branch);
1407
1408/**
1409 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1410 *
1411 * Display Port sink and branch devices in the wild have a variety of bugs, try
1412 * to collect them here. The quirks are shared, but it's up to the drivers to
1413 * implement workarounds for them.
1414 */
1415enum drm_dp_quirk {
1416 /**
1417 * @DP_DPCD_QUIRK_CONSTANT_N:
1418 *
1419 * The device requires main link attributes Mvid and Nvid to be limited
1420 * to 16 bits. So will give a constant value (0x8000) for compatability.
1421 */
1422 DP_DPCD_QUIRK_CONSTANT_N,
1423 /**
1424 * @DP_DPCD_QUIRK_NO_PSR:
1425 *
1426 * The device does not support PSR even if reports that it supports or
1427 * driver still need to implement proper handling for such device.
1428 */
1429 DP_DPCD_QUIRK_NO_PSR,
1430 /**
1431 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
1432 *
1433 * The device does not set SINK_COUNT to a non-zero value.
1434 * The driver should ignore SINK_COUNT during detection.
1435 */
1436 DP_DPCD_QUIRK_NO_SINK_COUNT,
1437};
1438
1439/**
1440 * drm_dp_has_quirk() - does the DP device have a specific quirk
1441 * @desc: Device decriptor filled by drm_dp_read_desc()
1442 * @quirk: Quirk to query for
1443 *
1444 * Return true if DP device identified by @desc has @quirk.
1445 */
1446static inline bool
1447drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1448{
1449 return desc->quirks & BIT(quirk);
1450}
1451
1452#ifdef CONFIG_DRM_DP_CEC
1453void drm_dp_cec_irq(struct drm_dp_aux *aux);
1454void drm_dp_cec_register_connector(struct drm_dp_aux *aux, const char *name,
1455 struct device *parent);
1456void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
1457void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
1458void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
1459#else
1460static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
1461{
1462}
1463
1464static inline void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1465 const char *name,
1466 struct device *parent)
1467{
1468}
1469
1470static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
1471{
1472}
1473
1474static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
1475 const struct edid *edid)
1476{
1477}
1478
1479static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
1480{
1481}
1482
1483#endif
1484
1485#endif /* _DRM_DP_HELPER_H_ */