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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28
29/* From the VESA DisplayPort spec */
30
31#define AUX_NATIVE_WRITE 0x8
32#define AUX_NATIVE_READ 0x9
33#define AUX_I2C_WRITE 0x0
34#define AUX_I2C_READ 0x1
35#define AUX_I2C_STATUS 0x2
36#define AUX_I2C_MOT 0x4
37
38#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
39#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
40#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
41#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
42
43#define AUX_I2C_REPLY_ACK (0x0 << 6)
44#define AUX_I2C_REPLY_NACK (0x1 << 6)
45#define AUX_I2C_REPLY_DEFER (0x2 << 6)
46#define AUX_I2C_REPLY_MASK (0x3 << 6)
47
48/* AUX CH addresses */
49/* DPCD */
50#define DP_DPCD_REV 0x000
51
52#define DP_MAX_LINK_RATE 0x001
53
54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f
56# define DP_TPS3_SUPPORTED (1 << 6)
57# define DP_ENHANCED_FRAME_CAP (1 << 7)
58
59#define DP_MAX_DOWNSPREAD 0x003
60# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
61
62#define DP_NORP 0x004
63
64#define DP_DOWNSTREAMPORT_PRESENT 0x005
65# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
66# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
67/* 00b = DisplayPort */
68/* 01b = Analog */
69/* 10b = TMDS or HDMI */
70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3)
72
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
77/* link configuration */
78#define DP_LINK_BW_SET 0x100
79# define DP_LINK_BW_1_62 0x06
80# define DP_LINK_BW_2_7 0x0a
81# define DP_LINK_BW_5_4 0x14
82
83#define DP_LANE_COUNT_SET 0x101
84# define DP_LANE_COUNT_MASK 0x0f
85# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
86
87#define DP_TRAINING_PATTERN_SET 0x102
88# define DP_TRAINING_PATTERN_DISABLE 0
89# define DP_TRAINING_PATTERN_1 1
90# define DP_TRAINING_PATTERN_2 2
91# define DP_TRAINING_PATTERN_3 3
92# define DP_TRAINING_PATTERN_MASK 0x3
93
94# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
95# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
96# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
97# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
98# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
99
100# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
101# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
102
103# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
104# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
105# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
106# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
107
108#define DP_TRAINING_LANE0_SET 0x103
109#define DP_TRAINING_LANE1_SET 0x104
110#define DP_TRAINING_LANE2_SET 0x105
111#define DP_TRAINING_LANE3_SET 0x106
112
113# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
114# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
115# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
116# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
117# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
118# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
119# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
120
121# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
122# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
123# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
124# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
125# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
126
127# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
128# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
129
130#define DP_DOWNSPREAD_CTRL 0x107
131# define DP_SPREAD_AMP_0_5 (1 << 4)
132
133#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
134# define DP_SET_ANSI_8B10B (1 << 0)
135
136#define DP_LANE0_1_STATUS 0x202
137#define DP_LANE2_3_STATUS 0x203
138# define DP_LANE_CR_DONE (1 << 0)
139# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
140# define DP_LANE_SYMBOL_LOCKED (1 << 2)
141
142#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
143 DP_LANE_CHANNEL_EQ_DONE | \
144 DP_LANE_SYMBOL_LOCKED)
145
146#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
147
148#define DP_INTERLANE_ALIGN_DONE (1 << 0)
149#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
150#define DP_LINK_STATUS_UPDATED (1 << 7)
151
152#define DP_SINK_STATUS 0x205
153
154#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
155#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
156
157#define DP_ADJUST_REQUEST_LANE0_1 0x206
158#define DP_ADJUST_REQUEST_LANE2_3 0x207
159# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
160# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
161# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
162# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
163# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
164# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
165# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
166# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
167
168#define DP_SET_POWER 0x600
169# define DP_SET_POWER_D0 0x1
170# define DP_SET_POWER_D3 0x2
171
172#define MODE_I2C_START 1
173#define MODE_I2C_WRITE 2
174#define MODE_I2C_READ 4
175#define MODE_I2C_STOP 8
176
177struct i2c_algo_dp_aux_data {
178 bool running;
179 u16 address;
180 int (*aux_ch) (struct i2c_adapter *adapter,
181 int mode, uint8_t write_byte,
182 uint8_t *read_byte);
183};
184
185int
186i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
187
188#endif /* _DRM_DP_HELPER_H_ */
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 *
41 * 1.2 formally includes both eDP and DPI definitions.
42 */
43
44#define DP_AUX_I2C_WRITE 0x0
45#define DP_AUX_I2C_READ 0x1
46#define DP_AUX_I2C_STATUS 0x2
47#define DP_AUX_I2C_MOT 0x4
48#define DP_AUX_NATIVE_WRITE 0x8
49#define DP_AUX_NATIVE_READ 0x9
50
51#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
52#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
53#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
54#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
55
56#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
57#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
58#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
59#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
60
61/* AUX CH addresses */
62/* DPCD */
63#define DP_DPCD_REV 0x000
64
65#define DP_MAX_LINK_RATE 0x001
66
67#define DP_MAX_LANE_COUNT 0x002
68# define DP_MAX_LANE_COUNT_MASK 0x1f
69# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
70# define DP_ENHANCED_FRAME_CAP (1 << 7)
71
72#define DP_MAX_DOWNSPREAD 0x003
73# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
74
75#define DP_NORP 0x004
76
77#define DP_DOWNSTREAMPORT_PRESENT 0x005
78# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
79# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
80# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
81# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
82# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
83# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
84# define DP_FORMAT_CONVERSION (1 << 3)
85# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
86
87#define DP_MAIN_LINK_CHANNEL_CODING 0x006
88
89#define DP_DOWN_STREAM_PORT_COUNT 0x007
90# define DP_PORT_COUNT_MASK 0x0f
91# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
92# define DP_OUI_SUPPORT (1 << 7)
93
94#define DP_I2C_SPEED_CAP 0x00c /* DPI */
95# define DP_I2C_SPEED_1K 0x01
96# define DP_I2C_SPEED_5K 0x02
97# define DP_I2C_SPEED_10K 0x04
98# define DP_I2C_SPEED_100K 0x08
99# define DP_I2C_SPEED_400K 0x10
100# define DP_I2C_SPEED_1M 0x20
101
102#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
103#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
104
105/* Multiple stream transport */
106#define DP_MSTM_CAP 0x021 /* 1.2 */
107# define DP_MST_CAP (1 << 0)
108
109#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
110# define DP_PSR_IS_SUPPORTED 1
111#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
112# define DP_PSR_NO_TRAIN_ON_EXIT 1
113# define DP_PSR_SETUP_TIME_330 (0 << 1)
114# define DP_PSR_SETUP_TIME_275 (1 << 1)
115# define DP_PSR_SETUP_TIME_220 (2 << 1)
116# define DP_PSR_SETUP_TIME_165 (3 << 1)
117# define DP_PSR_SETUP_TIME_110 (4 << 1)
118# define DP_PSR_SETUP_TIME_55 (5 << 1)
119# define DP_PSR_SETUP_TIME_0 (6 << 1)
120# define DP_PSR_SETUP_TIME_MASK (7 << 1)
121# define DP_PSR_SETUP_TIME_SHIFT 1
122
123/*
124 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
125 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
126 * each port's descriptor is one byte wide. If it was set, each port's is
127 * four bytes wide, starting with the one byte from the base info. As of
128 * DP interop v1.1a only VGA defines additional detail.
129 */
130
131/* offset 0 */
132#define DP_DOWNSTREAM_PORT_0 0x80
133# define DP_DS_PORT_TYPE_MASK (7 << 0)
134# define DP_DS_PORT_TYPE_DP 0
135# define DP_DS_PORT_TYPE_VGA 1
136# define DP_DS_PORT_TYPE_DVI 2
137# define DP_DS_PORT_TYPE_HDMI 3
138# define DP_DS_PORT_TYPE_NON_EDID 4
139# define DP_DS_PORT_HPD (1 << 3)
140/* offset 1 for VGA is maximum megapixels per second / 8 */
141/* offset 2 */
142# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
143# define DP_DS_VGA_8BPC 0
144# define DP_DS_VGA_10BPC 1
145# define DP_DS_VGA_12BPC 2
146# define DP_DS_VGA_16BPC 3
147
148/* link configuration */
149#define DP_LINK_BW_SET 0x100
150# define DP_LINK_BW_1_62 0x06
151# define DP_LINK_BW_2_7 0x0a
152# define DP_LINK_BW_5_4 0x14 /* 1.2 */
153
154#define DP_LANE_COUNT_SET 0x101
155# define DP_LANE_COUNT_MASK 0x0f
156# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
157
158#define DP_TRAINING_PATTERN_SET 0x102
159# define DP_TRAINING_PATTERN_DISABLE 0
160# define DP_TRAINING_PATTERN_1 1
161# define DP_TRAINING_PATTERN_2 2
162# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
163# define DP_TRAINING_PATTERN_MASK 0x3
164
165# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
166# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
167# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
168# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
169# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
170
171# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
172# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
173
174# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
175# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
176# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
177# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
178
179#define DP_TRAINING_LANE0_SET 0x103
180#define DP_TRAINING_LANE1_SET 0x104
181#define DP_TRAINING_LANE2_SET 0x105
182#define DP_TRAINING_LANE3_SET 0x106
183
184# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
185# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
186# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
187# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
188# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
189# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
190# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
191
192# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
193# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
194# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
195# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
196# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
197
198# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
199# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
200
201#define DP_DOWNSPREAD_CTRL 0x107
202# define DP_SPREAD_AMP_0_5 (1 << 4)
203# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
204
205#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
206# define DP_SET_ANSI_8B10B (1 << 0)
207
208#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
209/* bitmask as for DP_I2C_SPEED_CAP */
210
211#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
212
213#define DP_MSTM_CTRL 0x111 /* 1.2 */
214# define DP_MST_EN (1 << 0)
215# define DP_UP_REQ_EN (1 << 1)
216# define DP_UPSTREAM_IS_SRC (1 << 2)
217
218#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
219# define DP_PSR_ENABLE (1 << 0)
220# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
221# define DP_PSR_CRC_VERIFICATION (1 << 2)
222# define DP_PSR_FRAME_CAPTURE (1 << 3)
223
224#define DP_SINK_COUNT 0x200
225/* prior to 1.2 bit 7 was reserved mbz */
226# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
227# define DP_SINK_CP_READY (1 << 6)
228
229#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
230# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
231# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
232# define DP_CP_IRQ (1 << 2)
233# define DP_SINK_SPECIFIC_IRQ (1 << 6)
234
235#define DP_LANE0_1_STATUS 0x202
236#define DP_LANE2_3_STATUS 0x203
237# define DP_LANE_CR_DONE (1 << 0)
238# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
239# define DP_LANE_SYMBOL_LOCKED (1 << 2)
240
241#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
242 DP_LANE_CHANNEL_EQ_DONE | \
243 DP_LANE_SYMBOL_LOCKED)
244
245#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
246
247#define DP_INTERLANE_ALIGN_DONE (1 << 0)
248#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
249#define DP_LINK_STATUS_UPDATED (1 << 7)
250
251#define DP_SINK_STATUS 0x205
252
253#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
254#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
255
256#define DP_ADJUST_REQUEST_LANE0_1 0x206
257#define DP_ADJUST_REQUEST_LANE2_3 0x207
258# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
259# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
260# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
261# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
262# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
263# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
264# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
265# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
266
267#define DP_TEST_REQUEST 0x218
268# define DP_TEST_LINK_TRAINING (1 << 0)
269# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
270# define DP_TEST_LINK_EDID_READ (1 << 2)
271# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
272# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
273
274#define DP_TEST_LINK_RATE 0x219
275# define DP_LINK_RATE_162 (0x6)
276# define DP_LINK_RATE_27 (0xa)
277
278#define DP_TEST_LANE_COUNT 0x220
279
280#define DP_TEST_PATTERN 0x221
281
282#define DP_TEST_CRC_R_CR 0x240
283#define DP_TEST_CRC_G_Y 0x242
284#define DP_TEST_CRC_B_CB 0x244
285
286#define DP_TEST_SINK_MISC 0x246
287#define DP_TEST_CRC_SUPPORTED (1 << 5)
288
289#define DP_TEST_RESPONSE 0x260
290# define DP_TEST_ACK (1 << 0)
291# define DP_TEST_NAK (1 << 1)
292# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
293
294#define DP_TEST_SINK 0x270
295#define DP_TEST_SINK_START (1 << 0)
296
297#define DP_SOURCE_OUI 0x300
298#define DP_SINK_OUI 0x400
299#define DP_BRANCH_OUI 0x500
300
301#define DP_SET_POWER 0x600
302# define DP_SET_POWER_D0 0x1
303# define DP_SET_POWER_D3 0x2
304# define DP_SET_POWER_MASK 0x3
305
306#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
307# define DP_PSR_LINK_CRC_ERROR (1 << 0)
308# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
309
310#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
311# define DP_PSR_CAPS_CHANGE (1 << 0)
312
313#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
314# define DP_PSR_SINK_INACTIVE 0
315# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
316# define DP_PSR_SINK_ACTIVE_RFB 2
317# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
318# define DP_PSR_SINK_ACTIVE_RESYNC 4
319# define DP_PSR_SINK_INTERNAL_ERROR 7
320# define DP_PSR_SINK_STATE_MASK 0x07
321
322#define MODE_I2C_START 1
323#define MODE_I2C_WRITE 2
324#define MODE_I2C_READ 4
325#define MODE_I2C_STOP 8
326
327/**
328 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
329 * aux algorithm
330 * @running: set by the algo indicating whether an i2c is ongoing or whether
331 * the i2c bus is quiescent
332 * @address: i2c target address for the currently ongoing transfer
333 * @aux_ch: driver callback to transfer a single byte of the i2c payload
334 */
335struct i2c_algo_dp_aux_data {
336 bool running;
337 u16 address;
338 int (*aux_ch) (struct i2c_adapter *adapter,
339 int mode, uint8_t write_byte,
340 uint8_t *read_byte);
341};
342
343int
344i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
345
346
347#define DP_LINK_STATUS_SIZE 6
348bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
349 int lane_count);
350bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
351 int lane_count);
352u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
353 int lane);
354u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
355 int lane);
356
357#define DP_RECEIVER_CAP_SIZE 0xf
358#define EDP_PSR_RECEIVER_CAP_SIZE 2
359
360void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
361void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
362
363u8 drm_dp_link_rate_to_bw_code(int link_rate);
364int drm_dp_bw_code_to_link_rate(u8 link_bw);
365
366struct edp_sdp_header {
367 u8 HB0; /* Secondary Data Packet ID */
368 u8 HB1; /* Secondary Data Packet Type */
369 u8 HB2; /* 7:5 reserved, 4:0 revision number */
370 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
371} __packed;
372
373#define EDP_SDP_HEADER_REVISION_MASK 0x1F
374#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
375
376struct edp_vsc_psr {
377 struct edp_sdp_header sdp_header;
378 u8 DB0; /* Stereo Interface */
379 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
380 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
381 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
382 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
383 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
384 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
385 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
386 u8 DB8_31[24]; /* Reserved */
387} __packed;
388
389#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
390#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
391#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
392
393static inline int
394drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
395{
396 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
397}
398
399static inline u8
400drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
401{
402 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
403}
404
405static inline bool
406drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
407{
408 return dpcd[DP_DPCD_REV] >= 0x11 &&
409 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
410}
411
412/*
413 * DisplayPort AUX channel
414 */
415
416/**
417 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
418 * @address: address of the (first) register to access
419 * @request: contains the type of transaction (see DP_AUX_* macros)
420 * @reply: upon completion, contains the reply type of the transaction
421 * @buffer: pointer to a transmission or reception buffer
422 * @size: size of @buffer
423 */
424struct drm_dp_aux_msg {
425 unsigned int address;
426 u8 request;
427 u8 reply;
428 void *buffer;
429 size_t size;
430};
431
432/**
433 * struct drm_dp_aux - DisplayPort AUX channel
434 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
435 * @dev: pointer to struct device that is the parent for this AUX channel
436 * @transfer: transfers a message representing a single AUX transaction
437 *
438 * The .dev field should be set to a pointer to the device that implements
439 * the AUX channel.
440 *
441 * The .name field may be used to specify the name of the I2C adapter. If set to
442 * NULL, dev_name() of .dev will be used.
443 *
444 * Drivers provide a hardware-specific implementation of how transactions
445 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
446 * structure describing the transaction is passed into this function. Upon
447 * success, the implementation should return the number of payload bytes
448 * that were transferred, or a negative error-code on failure. Helpers
449 * propagate errors from the .transfer() function, with the exception of
450 * the -EBUSY error, which causes a transaction to be retried. On a short,
451 * helpers will return -EPROTO to make it simpler to check for failure.
452 *
453 * An AUX channel can also be used to transport I2C messages to a sink. A
454 * typical application of that is to access an EDID that's present in the
455 * sink device. The .transfer() function can also be used to execute such
456 * transactions. The drm_dp_aux_register_i2c_bus() function registers an
457 * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
458 * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter.
459 *
460 * Note that the aux helper code assumes that the .transfer() function
461 * only modifies the reply field of the drm_dp_aux_msg structure. The
462 * retry logic and i2c helpers assume this is the case.
463 */
464struct drm_dp_aux {
465 const char *name;
466 struct i2c_adapter ddc;
467 struct device *dev;
468
469 ssize_t (*transfer)(struct drm_dp_aux *aux,
470 struct drm_dp_aux_msg *msg);
471};
472
473ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
474 void *buffer, size_t size);
475ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
476 void *buffer, size_t size);
477
478/**
479 * drm_dp_dpcd_readb() - read a single byte from the DPCD
480 * @aux: DisplayPort AUX channel
481 * @offset: address of the register to read
482 * @valuep: location where the value of the register will be stored
483 *
484 * Returns the number of bytes transferred (1) on success, or a negative
485 * error code on failure.
486 */
487static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
488 unsigned int offset, u8 *valuep)
489{
490 return drm_dp_dpcd_read(aux, offset, valuep, 1);
491}
492
493/**
494 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
495 * @aux: DisplayPort AUX channel
496 * @offset: address of the register to write
497 * @value: value to write to the register
498 *
499 * Returns the number of bytes transferred (1) on success, or a negative
500 * error code on failure.
501 */
502static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
503 unsigned int offset, u8 value)
504{
505 return drm_dp_dpcd_write(aux, offset, &value, 1);
506}
507
508int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
509 u8 status[DP_LINK_STATUS_SIZE]);
510
511/*
512 * DisplayPort link
513 */
514#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
515
516struct drm_dp_link {
517 unsigned char revision;
518 unsigned int rate;
519 unsigned int num_lanes;
520 unsigned long capabilities;
521};
522
523int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
524int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
525int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
526
527int drm_dp_aux_register_i2c_bus(struct drm_dp_aux *aux);
528void drm_dp_aux_unregister_i2c_bus(struct drm_dp_aux *aux);
529
530#endif /* _DRM_DP_HELPER_H_ */