Loading...
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28
29/* From the VESA DisplayPort spec */
30
31#define AUX_NATIVE_WRITE 0x8
32#define AUX_NATIVE_READ 0x9
33#define AUX_I2C_WRITE 0x0
34#define AUX_I2C_READ 0x1
35#define AUX_I2C_STATUS 0x2
36#define AUX_I2C_MOT 0x4
37
38#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
39#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
40#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
41#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
42
43#define AUX_I2C_REPLY_ACK (0x0 << 6)
44#define AUX_I2C_REPLY_NACK (0x1 << 6)
45#define AUX_I2C_REPLY_DEFER (0x2 << 6)
46#define AUX_I2C_REPLY_MASK (0x3 << 6)
47
48/* AUX CH addresses */
49/* DPCD */
50#define DP_DPCD_REV 0x000
51
52#define DP_MAX_LINK_RATE 0x001
53
54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f
56# define DP_TPS3_SUPPORTED (1 << 6)
57# define DP_ENHANCED_FRAME_CAP (1 << 7)
58
59#define DP_MAX_DOWNSPREAD 0x003
60# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
61
62#define DP_NORP 0x004
63
64#define DP_DOWNSTREAMPORT_PRESENT 0x005
65# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
66# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
67/* 00b = DisplayPort */
68/* 01b = Analog */
69/* 10b = TMDS or HDMI */
70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3)
72
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
77/* link configuration */
78#define DP_LINK_BW_SET 0x100
79# define DP_LINK_BW_1_62 0x06
80# define DP_LINK_BW_2_7 0x0a
81# define DP_LINK_BW_5_4 0x14
82
83#define DP_LANE_COUNT_SET 0x101
84# define DP_LANE_COUNT_MASK 0x0f
85# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
86
87#define DP_TRAINING_PATTERN_SET 0x102
88# define DP_TRAINING_PATTERN_DISABLE 0
89# define DP_TRAINING_PATTERN_1 1
90# define DP_TRAINING_PATTERN_2 2
91# define DP_TRAINING_PATTERN_3 3
92# define DP_TRAINING_PATTERN_MASK 0x3
93
94# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
95# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
96# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
97# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
98# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
99
100# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
101# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
102
103# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
104# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
105# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
106# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
107
108#define DP_TRAINING_LANE0_SET 0x103
109#define DP_TRAINING_LANE1_SET 0x104
110#define DP_TRAINING_LANE2_SET 0x105
111#define DP_TRAINING_LANE3_SET 0x106
112
113# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
114# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
115# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
116# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
117# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
118# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
119# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
120
121# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
122# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
123# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
124# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
125# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
126
127# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
128# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
129
130#define DP_DOWNSPREAD_CTRL 0x107
131# define DP_SPREAD_AMP_0_5 (1 << 4)
132
133#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
134# define DP_SET_ANSI_8B10B (1 << 0)
135
136#define DP_LANE0_1_STATUS 0x202
137#define DP_LANE2_3_STATUS 0x203
138# define DP_LANE_CR_DONE (1 << 0)
139# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
140# define DP_LANE_SYMBOL_LOCKED (1 << 2)
141
142#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
143 DP_LANE_CHANNEL_EQ_DONE | \
144 DP_LANE_SYMBOL_LOCKED)
145
146#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
147
148#define DP_INTERLANE_ALIGN_DONE (1 << 0)
149#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
150#define DP_LINK_STATUS_UPDATED (1 << 7)
151
152#define DP_SINK_STATUS 0x205
153
154#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
155#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
156
157#define DP_ADJUST_REQUEST_LANE0_1 0x206
158#define DP_ADJUST_REQUEST_LANE2_3 0x207
159# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
160# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
161# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
162# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
163# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
164# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
165# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
166# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
167
168#define DP_SET_POWER 0x600
169# define DP_SET_POWER_D0 0x1
170# define DP_SET_POWER_D3 0x2
171
172#define MODE_I2C_START 1
173#define MODE_I2C_WRITE 2
174#define MODE_I2C_READ 4
175#define MODE_I2C_STOP 8
176
177struct i2c_algo_dp_aux_data {
178 bool running;
179 u16 address;
180 int (*aux_ch) (struct i2c_adapter *adapter,
181 int mode, uint8_t write_byte,
182 uint8_t *read_byte);
183};
184
185int
186i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
187
188#endif /* _DRM_DP_HELPER_H_ */
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
44
45#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
47#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
49#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
50#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
53
54#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
58
59#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
63
64/* AUX CH addresses */
65/* DPCD */
66#define DP_DPCD_REV 0x000
67
68#define DP_MAX_LINK_RATE 0x001
69
70#define DP_MAX_LANE_COUNT 0x002
71# define DP_MAX_LANE_COUNT_MASK 0x1f
72# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
73# define DP_ENHANCED_FRAME_CAP (1 << 7)
74
75#define DP_MAX_DOWNSPREAD 0x003
76# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
77
78#define DP_NORP 0x004
79
80#define DP_DOWNSTREAMPORT_PRESENT 0x005
81# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
82# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
83# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
84# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
85# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
86# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
87# define DP_FORMAT_CONVERSION (1 << 3)
88# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
89
90#define DP_MAIN_LINK_CHANNEL_CODING 0x006
91
92#define DP_DOWN_STREAM_PORT_COUNT 0x007
93# define DP_PORT_COUNT_MASK 0x0f
94# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
95# define DP_OUI_SUPPORT (1 << 7)
96
97#define DP_RECEIVE_PORT_0_CAP_0 0x008
98# define DP_LOCAL_EDID_PRESENT (1 << 1)
99# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
100
101#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
102
103#define DP_RECEIVE_PORT_1_CAP_0 0x00a
104#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
105
106#define DP_I2C_SPEED_CAP 0x00c /* DPI */
107# define DP_I2C_SPEED_1K 0x01
108# define DP_I2C_SPEED_5K 0x02
109# define DP_I2C_SPEED_10K 0x04
110# define DP_I2C_SPEED_100K 0x08
111# define DP_I2C_SPEED_400K 0x10
112# define DP_I2C_SPEED_1M 0x20
113
114#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
115# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
116# define DP_FRAMING_CHANGE_CAP (1 << 1)
117# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
118
119#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
120
121#define DP_ADAPTER_CAP 0x00f /* 1.2 */
122# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
123# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
124
125#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
126# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
127
128/* Multiple stream transport */
129#define DP_FAUX_CAP 0x020 /* 1.2 */
130# define DP_FAUX_CAP_1 (1 << 0)
131
132#define DP_MSTM_CAP 0x021 /* 1.2 */
133# define DP_MST_CAP (1 << 0)
134
135#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
136
137/* AV_SYNC_DATA_BLOCK 1.2 */
138#define DP_AV_GRANULARITY 0x023
139# define DP_AG_FACTOR_MASK (0xf << 0)
140# define DP_AG_FACTOR_3MS (0 << 0)
141# define DP_AG_FACTOR_2MS (1 << 0)
142# define DP_AG_FACTOR_1MS (2 << 0)
143# define DP_AG_FACTOR_500US (3 << 0)
144# define DP_AG_FACTOR_200US (4 << 0)
145# define DP_AG_FACTOR_100US (5 << 0)
146# define DP_AG_FACTOR_10US (6 << 0)
147# define DP_AG_FACTOR_1US (7 << 0)
148# define DP_VG_FACTOR_MASK (0xf << 4)
149# define DP_VG_FACTOR_3MS (0 << 4)
150# define DP_VG_FACTOR_2MS (1 << 4)
151# define DP_VG_FACTOR_1MS (2 << 4)
152# define DP_VG_FACTOR_500US (3 << 4)
153# define DP_VG_FACTOR_200US (4 << 4)
154# define DP_VG_FACTOR_100US (5 << 4)
155
156#define DP_AUD_DEC_LAT0 0x024
157#define DP_AUD_DEC_LAT1 0x025
158
159#define DP_AUD_PP_LAT0 0x026
160#define DP_AUD_PP_LAT1 0x027
161
162#define DP_VID_INTER_LAT 0x028
163
164#define DP_VID_PROG_LAT 0x029
165
166#define DP_REP_LAT 0x02a
167
168#define DP_AUD_DEL_INS0 0x02b
169#define DP_AUD_DEL_INS1 0x02c
170#define DP_AUD_DEL_INS2 0x02d
171/* End of AV_SYNC_DATA_BLOCK */
172
173#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
174# define DP_ALPM_CAP (1 << 0)
175
176#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
177# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
178
179#define DP_GUID 0x030 /* 1.2 */
180
181#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
182# define DP_PSR_IS_SUPPORTED 1
183# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
184
185#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
186# define DP_PSR_NO_TRAIN_ON_EXIT 1
187# define DP_PSR_SETUP_TIME_330 (0 << 1)
188# define DP_PSR_SETUP_TIME_275 (1 << 1)
189# define DP_PSR_SETUP_TIME_220 (2 << 1)
190# define DP_PSR_SETUP_TIME_165 (3 << 1)
191# define DP_PSR_SETUP_TIME_110 (4 << 1)
192# define DP_PSR_SETUP_TIME_55 (5 << 1)
193# define DP_PSR_SETUP_TIME_0 (6 << 1)
194# define DP_PSR_SETUP_TIME_MASK (7 << 1)
195# define DP_PSR_SETUP_TIME_SHIFT 1
196
197/*
198 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
199 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
200 * each port's descriptor is one byte wide. If it was set, each port's is
201 * four bytes wide, starting with the one byte from the base info. As of
202 * DP interop v1.1a only VGA defines additional detail.
203 */
204
205/* offset 0 */
206#define DP_DOWNSTREAM_PORT_0 0x80
207# define DP_DS_PORT_TYPE_MASK (7 << 0)
208# define DP_DS_PORT_TYPE_DP 0
209# define DP_DS_PORT_TYPE_VGA 1
210# define DP_DS_PORT_TYPE_DVI 2
211# define DP_DS_PORT_TYPE_HDMI 3
212# define DP_DS_PORT_TYPE_NON_EDID 4
213# define DP_DS_PORT_HPD (1 << 3)
214/* offset 1 for VGA is maximum megapixels per second / 8 */
215/* offset 2 */
216# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
217# define DP_DS_VGA_8BPC 0
218# define DP_DS_VGA_10BPC 1
219# define DP_DS_VGA_12BPC 2
220# define DP_DS_VGA_16BPC 3
221
222/* link configuration */
223#define DP_LINK_BW_SET 0x100
224# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
225# define DP_LINK_BW_1_62 0x06
226# define DP_LINK_BW_2_7 0x0a
227# define DP_LINK_BW_5_4 0x14 /* 1.2 */
228
229#define DP_LANE_COUNT_SET 0x101
230# define DP_LANE_COUNT_MASK 0x0f
231# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
232
233#define DP_TRAINING_PATTERN_SET 0x102
234# define DP_TRAINING_PATTERN_DISABLE 0
235# define DP_TRAINING_PATTERN_1 1
236# define DP_TRAINING_PATTERN_2 2
237# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
238# define DP_TRAINING_PATTERN_MASK 0x3
239
240/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
241# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
242# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
243# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
244# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
245# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
246
247# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
248# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
249
250# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
251# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
252# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
253# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
254
255#define DP_TRAINING_LANE0_SET 0x103
256#define DP_TRAINING_LANE1_SET 0x104
257#define DP_TRAINING_LANE2_SET 0x105
258#define DP_TRAINING_LANE3_SET 0x106
259
260# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
261# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
262# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
263# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
264# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
265# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
266# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
267
268# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
269# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
270# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
271# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
272# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
273
274# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
275# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
276
277#define DP_DOWNSPREAD_CTRL 0x107
278# define DP_SPREAD_AMP_0_5 (1 << 4)
279# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
280
281#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
282# define DP_SET_ANSI_8B10B (1 << 0)
283
284#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
285/* bitmask as for DP_I2C_SPEED_CAP */
286
287#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
288# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
289# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
290# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
291
292#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
293#define DP_LINK_QUAL_LANE1_SET 0x10c
294#define DP_LINK_QUAL_LANE2_SET 0x10d
295#define DP_LINK_QUAL_LANE3_SET 0x10e
296# define DP_LINK_QUAL_PATTERN_DISABLE 0
297# define DP_LINK_QUAL_PATTERN_D10_2 1
298# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
299# define DP_LINK_QUAL_PATTERN_PRBS7 3
300# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
301# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
302# define DP_LINK_QUAL_PATTERN_MASK 7
303
304#define DP_TRAINING_LANE0_1_SET2 0x10f
305#define DP_TRAINING_LANE2_3_SET2 0x110
306# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
307# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
308# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
309# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
310
311#define DP_MSTM_CTRL 0x111 /* 1.2 */
312# define DP_MST_EN (1 << 0)
313# define DP_UP_REQ_EN (1 << 1)
314# define DP_UPSTREAM_IS_SRC (1 << 2)
315
316#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
317#define DP_AUDIO_DELAY1 0x113
318#define DP_AUDIO_DELAY2 0x114
319
320#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
321# define DP_LINK_RATE_SET_SHIFT 0
322# define DP_LINK_RATE_SET_MASK (7 << 0)
323
324#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
325# define DP_ALPM_ENABLE (1 << 0)
326# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
327
328#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
329# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
330# define DP_IRQ_HPD_ENABLE (1 << 1)
331
332#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
333# define DP_PWR_NOT_NEEDED (1 << 0)
334
335#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
336# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
337
338#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
339# define DP_PSR_ENABLE (1 << 0)
340# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
341# define DP_PSR_CRC_VERIFICATION (1 << 2)
342# define DP_PSR_FRAME_CAPTURE (1 << 3)
343# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
344# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
345
346#define DP_ADAPTER_CTRL 0x1a0
347# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
348
349#define DP_BRANCH_DEVICE_CTRL 0x1a1
350# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
351
352#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
353#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
354#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
355
356#define DP_SINK_COUNT 0x200
357/* prior to 1.2 bit 7 was reserved mbz */
358# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
359# define DP_SINK_CP_READY (1 << 6)
360
361#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
362# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
363# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
364# define DP_CP_IRQ (1 << 2)
365# define DP_MCCS_IRQ (1 << 3)
366# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
367# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
368# define DP_SINK_SPECIFIC_IRQ (1 << 6)
369
370#define DP_LANE0_1_STATUS 0x202
371#define DP_LANE2_3_STATUS 0x203
372# define DP_LANE_CR_DONE (1 << 0)
373# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
374# define DP_LANE_SYMBOL_LOCKED (1 << 2)
375
376#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
377 DP_LANE_CHANNEL_EQ_DONE | \
378 DP_LANE_SYMBOL_LOCKED)
379
380#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
381
382#define DP_INTERLANE_ALIGN_DONE (1 << 0)
383#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
384#define DP_LINK_STATUS_UPDATED (1 << 7)
385
386#define DP_SINK_STATUS 0x205
387
388#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
389#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
390
391#define DP_ADJUST_REQUEST_LANE0_1 0x206
392#define DP_ADJUST_REQUEST_LANE2_3 0x207
393# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
394# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
395# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
396# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
397# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
398# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
399# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
400# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
401
402#define DP_TEST_REQUEST 0x218
403# define DP_TEST_LINK_TRAINING (1 << 0)
404# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
405# define DP_TEST_LINK_EDID_READ (1 << 2)
406# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
407# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
408
409#define DP_TEST_LINK_RATE 0x219
410# define DP_LINK_RATE_162 (0x6)
411# define DP_LINK_RATE_27 (0xa)
412
413#define DP_TEST_LANE_COUNT 0x220
414
415#define DP_TEST_PATTERN 0x221
416
417#define DP_TEST_CRC_R_CR 0x240
418#define DP_TEST_CRC_G_Y 0x242
419#define DP_TEST_CRC_B_CB 0x244
420
421#define DP_TEST_SINK_MISC 0x246
422# define DP_TEST_CRC_SUPPORTED (1 << 5)
423# define DP_TEST_COUNT_MASK 0xf
424
425#define DP_TEST_RESPONSE 0x260
426# define DP_TEST_ACK (1 << 0)
427# define DP_TEST_NAK (1 << 1)
428# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
429
430#define DP_TEST_EDID_CHECKSUM 0x261
431
432#define DP_TEST_SINK 0x270
433# define DP_TEST_SINK_START (1 << 0)
434
435#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
436# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
437# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
438
439#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
440/* up to ID_SLOT_63 at 0x2ff */
441
442#define DP_SOURCE_OUI 0x300
443#define DP_SINK_OUI 0x400
444#define DP_BRANCH_OUI 0x500
445
446#define DP_SET_POWER 0x600
447# define DP_SET_POWER_D0 0x1
448# define DP_SET_POWER_D3 0x2
449# define DP_SET_POWER_MASK 0x3
450
451#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
452# define DP_EDP_11 0x00
453# define DP_EDP_12 0x01
454# define DP_EDP_13 0x02
455# define DP_EDP_14 0x03
456
457#define DP_EDP_GENERAL_CAP_1 0x701
458# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
459# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
460# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
461# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
462# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
463# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
464# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
465# define DP_EDP_SET_POWER_CAP (1 << 7)
466
467#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
468# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
469# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
470# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
471# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
472# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
473# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
474# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
475# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
476
477#define DP_EDP_GENERAL_CAP_2 0x703
478# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
479
480#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
481# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
482# define DP_EDP_X_REGION_CAP_SHIFT 0
483# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
484# define DP_EDP_Y_REGION_CAP_SHIFT 4
485
486#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
487# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
488# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
489# define DP_EDP_FRC_ENABLE (1 << 2)
490# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
491# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
492
493#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
494# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
495# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
496# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
497# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
498# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
499# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
500# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
501# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
502# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
503# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
504
505#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
506#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
507
508#define DP_EDP_PWMGEN_BIT_COUNT 0x724
509#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
510#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
511
512#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
513
514#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
515
516#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
517#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
518#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
519
520#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
521#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
522#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
523
524#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
525#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
526
527#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
528#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
529
530#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
531#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
532#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
533#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
534
535#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
536/* 0-5 sink count */
537# define DP_SINK_COUNT_CP_READY (1 << 6)
538
539#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
540
541#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
542
543#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
544
545#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
546# define DP_PSR_LINK_CRC_ERROR (1 << 0)
547# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
548# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
549
550#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
551# define DP_PSR_CAPS_CHANGE (1 << 0)
552
553#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
554# define DP_PSR_SINK_INACTIVE 0
555# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
556# define DP_PSR_SINK_ACTIVE_RFB 2
557# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
558# define DP_PSR_SINK_ACTIVE_RESYNC 4
559# define DP_PSR_SINK_INTERNAL_ERROR 7
560# define DP_PSR_SINK_STATE_MASK 0x07
561
562#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
563# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
564
565/* DP 1.2 Sideband message defines */
566/* peer device type - DP 1.2a Table 2-92 */
567#define DP_PEER_DEVICE_NONE 0x0
568#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
569#define DP_PEER_DEVICE_MST_BRANCHING 0x2
570#define DP_PEER_DEVICE_SST_SINK 0x3
571#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
572
573/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
574#define DP_LINK_ADDRESS 0x01
575#define DP_CONNECTION_STATUS_NOTIFY 0x02
576#define DP_ENUM_PATH_RESOURCES 0x10
577#define DP_ALLOCATE_PAYLOAD 0x11
578#define DP_QUERY_PAYLOAD 0x12
579#define DP_RESOURCE_STATUS_NOTIFY 0x13
580#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
581#define DP_REMOTE_DPCD_READ 0x20
582#define DP_REMOTE_DPCD_WRITE 0x21
583#define DP_REMOTE_I2C_READ 0x22
584#define DP_REMOTE_I2C_WRITE 0x23
585#define DP_POWER_UP_PHY 0x24
586#define DP_POWER_DOWN_PHY 0x25
587#define DP_SINK_EVENT_NOTIFY 0x30
588#define DP_QUERY_STREAM_ENC_STATUS 0x38
589
590/* DP 1.2 MST sideband nak reasons - table 2.84 */
591#define DP_NAK_WRITE_FAILURE 0x01
592#define DP_NAK_INVALID_READ 0x02
593#define DP_NAK_CRC_FAILURE 0x03
594#define DP_NAK_BAD_PARAM 0x04
595#define DP_NAK_DEFER 0x05
596#define DP_NAK_LINK_FAILURE 0x06
597#define DP_NAK_NO_RESOURCES 0x07
598#define DP_NAK_DPCD_FAIL 0x08
599#define DP_NAK_I2C_NAK 0x09
600#define DP_NAK_ALLOCATE_FAIL 0x0a
601
602#define MODE_I2C_START 1
603#define MODE_I2C_WRITE 2
604#define MODE_I2C_READ 4
605#define MODE_I2C_STOP 8
606
607/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
608#define DP_MST_PHYSICAL_PORT_0 0
609#define DP_MST_LOGICAL_PORT_0 8
610
611#define DP_LINK_STATUS_SIZE 6
612bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
613 int lane_count);
614bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
615 int lane_count);
616u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
617 int lane);
618u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
619 int lane);
620
621#define DP_BRANCH_OUI_HEADER_SIZE 0xc
622#define DP_RECEIVER_CAP_SIZE 0xf
623#define EDP_PSR_RECEIVER_CAP_SIZE 2
624
625void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
626void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
627
628u8 drm_dp_link_rate_to_bw_code(int link_rate);
629int drm_dp_bw_code_to_link_rate(u8 link_bw);
630
631struct edp_sdp_header {
632 u8 HB0; /* Secondary Data Packet ID */
633 u8 HB1; /* Secondary Data Packet Type */
634 u8 HB2; /* 7:5 reserved, 4:0 revision number */
635 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
636} __packed;
637
638#define EDP_SDP_HEADER_REVISION_MASK 0x1F
639#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
640
641struct edp_vsc_psr {
642 struct edp_sdp_header sdp_header;
643 u8 DB0; /* Stereo Interface */
644 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
645 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
646 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
647 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
648 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
649 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
650 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
651 u8 DB8_31[24]; /* Reserved */
652} __packed;
653
654#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
655#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
656#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
657
658static inline int
659drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
660{
661 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
662}
663
664static inline u8
665drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
666{
667 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
668}
669
670static inline bool
671drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
672{
673 return dpcd[DP_DPCD_REV] >= 0x11 &&
674 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
675}
676
677static inline bool
678drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
679{
680 return dpcd[DP_DPCD_REV] >= 0x12 &&
681 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
682}
683
684/*
685 * DisplayPort AUX channel
686 */
687
688/**
689 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
690 * @address: address of the (first) register to access
691 * @request: contains the type of transaction (see DP_AUX_* macros)
692 * @reply: upon completion, contains the reply type of the transaction
693 * @buffer: pointer to a transmission or reception buffer
694 * @size: size of @buffer
695 */
696struct drm_dp_aux_msg {
697 unsigned int address;
698 u8 request;
699 u8 reply;
700 void *buffer;
701 size_t size;
702};
703
704/**
705 * struct drm_dp_aux - DisplayPort AUX channel
706 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
707 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
708 * @dev: pointer to struct device that is the parent for this AUX channel
709 * @hw_mutex: internal mutex used for locking transfers
710 * @transfer: transfers a message representing a single AUX transaction
711 *
712 * The .dev field should be set to a pointer to the device that implements
713 * the AUX channel.
714 *
715 * The .name field may be used to specify the name of the I2C adapter. If set to
716 * NULL, dev_name() of .dev will be used.
717 *
718 * Drivers provide a hardware-specific implementation of how transactions
719 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
720 * structure describing the transaction is passed into this function. Upon
721 * success, the implementation should return the number of payload bytes
722 * that were transferred, or a negative error-code on failure. Helpers
723 * propagate errors from the .transfer() function, with the exception of
724 * the -EBUSY error, which causes a transaction to be retried. On a short,
725 * helpers will return -EPROTO to make it simpler to check for failure.
726 *
727 * An AUX channel can also be used to transport I2C messages to a sink. A
728 * typical application of that is to access an EDID that's present in the
729 * sink device. The .transfer() function can also be used to execute such
730 * transactions. The drm_dp_aux_register() function registers an I2C
731 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
732 * should call drm_dp_aux_unregister() to remove the I2C adapter.
733 * The I2C adapter uses long transfers by default; if a partial response is
734 * received, the adapter will drop down to the size given by the partial
735 * response for this transaction only.
736 *
737 * Note that the aux helper code assumes that the .transfer() function
738 * only modifies the reply field of the drm_dp_aux_msg structure. The
739 * retry logic and i2c helpers assume this is the case.
740 */
741struct drm_dp_aux {
742 const char *name;
743 struct i2c_adapter ddc;
744 struct device *dev;
745 struct mutex hw_mutex;
746 ssize_t (*transfer)(struct drm_dp_aux *aux,
747 struct drm_dp_aux_msg *msg);
748 unsigned i2c_nack_count, i2c_defer_count;
749};
750
751ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
752 void *buffer, size_t size);
753ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
754 void *buffer, size_t size);
755
756/**
757 * drm_dp_dpcd_readb() - read a single byte from the DPCD
758 * @aux: DisplayPort AUX channel
759 * @offset: address of the register to read
760 * @valuep: location where the value of the register will be stored
761 *
762 * Returns the number of bytes transferred (1) on success, or a negative
763 * error code on failure.
764 */
765static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
766 unsigned int offset, u8 *valuep)
767{
768 return drm_dp_dpcd_read(aux, offset, valuep, 1);
769}
770
771/**
772 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
773 * @aux: DisplayPort AUX channel
774 * @offset: address of the register to write
775 * @value: value to write to the register
776 *
777 * Returns the number of bytes transferred (1) on success, or a negative
778 * error code on failure.
779 */
780static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
781 unsigned int offset, u8 value)
782{
783 return drm_dp_dpcd_write(aux, offset, &value, 1);
784}
785
786int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
787 u8 status[DP_LINK_STATUS_SIZE]);
788
789/*
790 * DisplayPort link
791 */
792#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
793
794struct drm_dp_link {
795 unsigned char revision;
796 unsigned int rate;
797 unsigned int num_lanes;
798 unsigned long capabilities;
799};
800
801int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
802int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
803int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
804int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
805
806int drm_dp_aux_register(struct drm_dp_aux *aux);
807void drm_dp_aux_unregister(struct drm_dp_aux *aux);
808
809#endif /* _DRM_DP_HELPER_H_ */