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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28
29/* From the VESA DisplayPort spec */
30
31#define AUX_NATIVE_WRITE 0x8
32#define AUX_NATIVE_READ 0x9
33#define AUX_I2C_WRITE 0x0
34#define AUX_I2C_READ 0x1
35#define AUX_I2C_STATUS 0x2
36#define AUX_I2C_MOT 0x4
37
38#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
39#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
40#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
41#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
42
43#define AUX_I2C_REPLY_ACK (0x0 << 6)
44#define AUX_I2C_REPLY_NACK (0x1 << 6)
45#define AUX_I2C_REPLY_DEFER (0x2 << 6)
46#define AUX_I2C_REPLY_MASK (0x3 << 6)
47
48/* AUX CH addresses */
49/* DPCD */
50#define DP_DPCD_REV 0x000
51
52#define DP_MAX_LINK_RATE 0x001
53
54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f
56# define DP_TPS3_SUPPORTED (1 << 6)
57# define DP_ENHANCED_FRAME_CAP (1 << 7)
58
59#define DP_MAX_DOWNSPREAD 0x003
60# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
61
62#define DP_NORP 0x004
63
64#define DP_DOWNSTREAMPORT_PRESENT 0x005
65# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
66# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
67/* 00b = DisplayPort */
68/* 01b = Analog */
69/* 10b = TMDS or HDMI */
70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3)
72
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
77/* link configuration */
78#define DP_LINK_BW_SET 0x100
79# define DP_LINK_BW_1_62 0x06
80# define DP_LINK_BW_2_7 0x0a
81# define DP_LINK_BW_5_4 0x14
82
83#define DP_LANE_COUNT_SET 0x101
84# define DP_LANE_COUNT_MASK 0x0f
85# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
86
87#define DP_TRAINING_PATTERN_SET 0x102
88# define DP_TRAINING_PATTERN_DISABLE 0
89# define DP_TRAINING_PATTERN_1 1
90# define DP_TRAINING_PATTERN_2 2
91# define DP_TRAINING_PATTERN_3 3
92# define DP_TRAINING_PATTERN_MASK 0x3
93
94# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
95# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
96# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
97# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
98# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
99
100# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
101# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
102
103# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
104# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
105# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
106# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
107
108#define DP_TRAINING_LANE0_SET 0x103
109#define DP_TRAINING_LANE1_SET 0x104
110#define DP_TRAINING_LANE2_SET 0x105
111#define DP_TRAINING_LANE3_SET 0x106
112
113# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
114# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
115# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
116# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
117# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
118# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
119# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
120
121# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
122# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
123# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
124# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
125# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
126
127# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
128# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
129
130#define DP_DOWNSPREAD_CTRL 0x107
131# define DP_SPREAD_AMP_0_5 (1 << 4)
132
133#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
134# define DP_SET_ANSI_8B10B (1 << 0)
135
136#define DP_LANE0_1_STATUS 0x202
137#define DP_LANE2_3_STATUS 0x203
138# define DP_LANE_CR_DONE (1 << 0)
139# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
140# define DP_LANE_SYMBOL_LOCKED (1 << 2)
141
142#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
143 DP_LANE_CHANNEL_EQ_DONE | \
144 DP_LANE_SYMBOL_LOCKED)
145
146#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
147
148#define DP_INTERLANE_ALIGN_DONE (1 << 0)
149#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
150#define DP_LINK_STATUS_UPDATED (1 << 7)
151
152#define DP_SINK_STATUS 0x205
153
154#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
155#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
156
157#define DP_ADJUST_REQUEST_LANE0_1 0x206
158#define DP_ADJUST_REQUEST_LANE2_3 0x207
159# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
160# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
161# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
162# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
163# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
164# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
165# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
166# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
167
168#define DP_SET_POWER 0x600
169# define DP_SET_POWER_D0 0x1
170# define DP_SET_POWER_D3 0x2
171
172#define MODE_I2C_START 1
173#define MODE_I2C_WRITE 2
174#define MODE_I2C_READ 4
175#define MODE_I2C_STOP 8
176
177struct i2c_algo_dp_aux_data {
178 bool running;
179 u16 address;
180 int (*aux_ch) (struct i2c_adapter *adapter,
181 int mode, uint8_t write_byte,
182 uint8_t *read_byte);
183};
184
185int
186i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
187
188#endif /* _DRM_DP_HELPER_H_ */
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
44
45#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
47#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
49#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
50#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
53
54#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
58
59#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
63
64/* AUX CH addresses */
65/* DPCD */
66#define DP_DPCD_REV 0x000
67
68#define DP_MAX_LINK_RATE 0x001
69
70#define DP_MAX_LANE_COUNT 0x002
71# define DP_MAX_LANE_COUNT_MASK 0x1f
72# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
73# define DP_ENHANCED_FRAME_CAP (1 << 7)
74
75#define DP_MAX_DOWNSPREAD 0x003
76# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
77# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
78# define DP_TPS4_SUPPORTED (1 << 7)
79
80#define DP_NORP 0x004
81
82#define DP_DOWNSTREAMPORT_PRESENT 0x005
83# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
84# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
85# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
86# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
87# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
88# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
89# define DP_FORMAT_CONVERSION (1 << 3)
90# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
91
92#define DP_MAIN_LINK_CHANNEL_CODING 0x006
93
94#define DP_DOWN_STREAM_PORT_COUNT 0x007
95# define DP_PORT_COUNT_MASK 0x0f
96# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
97# define DP_OUI_SUPPORT (1 << 7)
98
99#define DP_RECEIVE_PORT_0_CAP_0 0x008
100# define DP_LOCAL_EDID_PRESENT (1 << 1)
101# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
102
103#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
104
105#define DP_RECEIVE_PORT_1_CAP_0 0x00a
106#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
107
108#define DP_I2C_SPEED_CAP 0x00c /* DPI */
109# define DP_I2C_SPEED_1K 0x01
110# define DP_I2C_SPEED_5K 0x02
111# define DP_I2C_SPEED_10K 0x04
112# define DP_I2C_SPEED_100K 0x08
113# define DP_I2C_SPEED_400K 0x10
114# define DP_I2C_SPEED_1M 0x20
115
116#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
117# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
118# define DP_FRAMING_CHANGE_CAP (1 << 1)
119# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
120
121#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
122
123#define DP_ADAPTER_CAP 0x00f /* 1.2 */
124# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
125# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
126
127#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
128# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
129
130/* Multiple stream transport */
131#define DP_FAUX_CAP 0x020 /* 1.2 */
132# define DP_FAUX_CAP_1 (1 << 0)
133
134#define DP_MSTM_CAP 0x021 /* 1.2 */
135# define DP_MST_CAP (1 << 0)
136
137#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
138
139/* AV_SYNC_DATA_BLOCK 1.2 */
140#define DP_AV_GRANULARITY 0x023
141# define DP_AG_FACTOR_MASK (0xf << 0)
142# define DP_AG_FACTOR_3MS (0 << 0)
143# define DP_AG_FACTOR_2MS (1 << 0)
144# define DP_AG_FACTOR_1MS (2 << 0)
145# define DP_AG_FACTOR_500US (3 << 0)
146# define DP_AG_FACTOR_200US (4 << 0)
147# define DP_AG_FACTOR_100US (5 << 0)
148# define DP_AG_FACTOR_10US (6 << 0)
149# define DP_AG_FACTOR_1US (7 << 0)
150# define DP_VG_FACTOR_MASK (0xf << 4)
151# define DP_VG_FACTOR_3MS (0 << 4)
152# define DP_VG_FACTOR_2MS (1 << 4)
153# define DP_VG_FACTOR_1MS (2 << 4)
154# define DP_VG_FACTOR_500US (3 << 4)
155# define DP_VG_FACTOR_200US (4 << 4)
156# define DP_VG_FACTOR_100US (5 << 4)
157
158#define DP_AUD_DEC_LAT0 0x024
159#define DP_AUD_DEC_LAT1 0x025
160
161#define DP_AUD_PP_LAT0 0x026
162#define DP_AUD_PP_LAT1 0x027
163
164#define DP_VID_INTER_LAT 0x028
165
166#define DP_VID_PROG_LAT 0x029
167
168#define DP_REP_LAT 0x02a
169
170#define DP_AUD_DEL_INS0 0x02b
171#define DP_AUD_DEL_INS1 0x02c
172#define DP_AUD_DEL_INS2 0x02d
173/* End of AV_SYNC_DATA_BLOCK */
174
175#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
176# define DP_ALPM_CAP (1 << 0)
177
178#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
179# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
180
181#define DP_GUID 0x030 /* 1.2 */
182
183#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
184# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
185
186#define DP_DSC_REV 0x061
187# define DP_DSC_MAJOR_MASK (0xf << 0)
188# define DP_DSC_MINOR_MASK (0xf << 4)
189# define DP_DSC_MAJOR_SHIFT 0
190# define DP_DSC_MINOR_SHIFT 4
191
192#define DP_DSC_RC_BUF_BLK_SIZE 0x062
193# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
194# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
195# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
196# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
197
198#define DP_DSC_RC_BUF_SIZE 0x063
199
200#define DP_DSC_SLICE_CAP_1 0x064
201# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
202# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
203# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
204# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
205# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
206# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
207# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
208
209#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
210# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
211# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
212# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
213# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
214# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
215# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
216# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
217# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
218# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
219# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
220
221#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
222# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
223
224#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
225
226#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
227
228#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
229# define DP_DSC_RGB (1 << 0)
230# define DP_DSC_YCbCr444 (1 << 1)
231# define DP_DSC_YCbCr422_Simple (1 << 2)
232# define DP_DSC_YCbCr422_Native (1 << 3)
233# define DP_DSC_YCbCr420_Native (1 << 4)
234
235#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
236# define DP_DSC_8_BPC (1 << 1)
237# define DP_DSC_10_BPC (1 << 2)
238# define DP_DSC_12_BPC (1 << 3)
239
240#define DP_DSC_PEAK_THROUGHPUT 0x06B
241# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
242# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
243# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
244# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
245# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
246# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
247# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
248# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
249# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
250# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
251# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
252# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
253# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
254# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
255# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
256# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
257# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
258# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
259# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
260# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
261# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
262# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
263# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
264# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
265# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
266# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
267# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
268# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
269# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
270# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
271# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
272# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
273
274#define DP_DSC_MAX_SLICE_WIDTH 0x06C
275
276#define DP_DSC_SLICE_CAP_2 0x06D
277# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
278# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
279# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
280
281#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
282# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
283# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
284# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
285# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
286# define DP_DSC_BITS_PER_PIXEL_1 0x4
287
288#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
289# define DP_PSR_IS_SUPPORTED 1
290# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
291# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
292
293#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
294# define DP_PSR_NO_TRAIN_ON_EXIT 1
295# define DP_PSR_SETUP_TIME_330 (0 << 1)
296# define DP_PSR_SETUP_TIME_275 (1 << 1)
297# define DP_PSR_SETUP_TIME_220 (2 << 1)
298# define DP_PSR_SETUP_TIME_165 (3 << 1)
299# define DP_PSR_SETUP_TIME_110 (4 << 1)
300# define DP_PSR_SETUP_TIME_55 (5 << 1)
301# define DP_PSR_SETUP_TIME_0 (6 << 1)
302# define DP_PSR_SETUP_TIME_MASK (7 << 1)
303# define DP_PSR_SETUP_TIME_SHIFT 1
304# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
305# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
306/*
307 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
308 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
309 * each port's descriptor is one byte wide. If it was set, each port's is
310 * four bytes wide, starting with the one byte from the base info. As of
311 * DP interop v1.1a only VGA defines additional detail.
312 */
313
314/* offset 0 */
315#define DP_DOWNSTREAM_PORT_0 0x80
316# define DP_DS_PORT_TYPE_MASK (7 << 0)
317# define DP_DS_PORT_TYPE_DP 0
318# define DP_DS_PORT_TYPE_VGA 1
319# define DP_DS_PORT_TYPE_DVI 2
320# define DP_DS_PORT_TYPE_HDMI 3
321# define DP_DS_PORT_TYPE_NON_EDID 4
322# define DP_DS_PORT_TYPE_DP_DUALMODE 5
323# define DP_DS_PORT_TYPE_WIRELESS 6
324# define DP_DS_PORT_HPD (1 << 3)
325/* offset 1 for VGA is maximum megapixels per second / 8 */
326/* offset 2 */
327# define DP_DS_MAX_BPC_MASK (3 << 0)
328# define DP_DS_8BPC 0
329# define DP_DS_10BPC 1
330# define DP_DS_12BPC 2
331# define DP_DS_16BPC 3
332
333/* DP Forward error Correction Registers */
334#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
335# define DP_FEC_CAPABLE (1 << 0)
336# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
337# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
338# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
339
340/* link configuration */
341#define DP_LINK_BW_SET 0x100
342# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
343# define DP_LINK_BW_1_62 0x06
344# define DP_LINK_BW_2_7 0x0a
345# define DP_LINK_BW_5_4 0x14 /* 1.2 */
346# define DP_LINK_BW_8_1 0x1e /* 1.4 */
347
348#define DP_LANE_COUNT_SET 0x101
349# define DP_LANE_COUNT_MASK 0x0f
350# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
351
352#define DP_TRAINING_PATTERN_SET 0x102
353# define DP_TRAINING_PATTERN_DISABLE 0
354# define DP_TRAINING_PATTERN_1 1
355# define DP_TRAINING_PATTERN_2 2
356# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
357# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
358# define DP_TRAINING_PATTERN_MASK 0x3
359# define DP_TRAINING_PATTERN_MASK_1_4 0xf
360
361/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
362# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
363# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
364# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
365# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
366# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
367
368# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
369# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
370
371# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
372# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
373# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
374# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
375
376#define DP_TRAINING_LANE0_SET 0x103
377#define DP_TRAINING_LANE1_SET 0x104
378#define DP_TRAINING_LANE2_SET 0x105
379#define DP_TRAINING_LANE3_SET 0x106
380
381# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
382# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
383# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
384# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
385# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
386# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
387# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
388
389# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
390# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
391# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
392# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
393# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
394
395# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
396# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
397
398#define DP_DOWNSPREAD_CTRL 0x107
399# define DP_SPREAD_AMP_0_5 (1 << 4)
400# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
401
402#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
403# define DP_SET_ANSI_8B10B (1 << 0)
404
405#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
406/* bitmask as for DP_I2C_SPEED_CAP */
407
408#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
409# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
410# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
411# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
412
413#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
414#define DP_LINK_QUAL_LANE1_SET 0x10c
415#define DP_LINK_QUAL_LANE2_SET 0x10d
416#define DP_LINK_QUAL_LANE3_SET 0x10e
417# define DP_LINK_QUAL_PATTERN_DISABLE 0
418# define DP_LINK_QUAL_PATTERN_D10_2 1
419# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
420# define DP_LINK_QUAL_PATTERN_PRBS7 3
421# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
422# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
423# define DP_LINK_QUAL_PATTERN_MASK 7
424
425#define DP_TRAINING_LANE0_1_SET2 0x10f
426#define DP_TRAINING_LANE2_3_SET2 0x110
427# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
428# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
429# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
430# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
431
432#define DP_MSTM_CTRL 0x111 /* 1.2 */
433# define DP_MST_EN (1 << 0)
434# define DP_UP_REQ_EN (1 << 1)
435# define DP_UPSTREAM_IS_SRC (1 << 2)
436
437#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
438#define DP_AUDIO_DELAY1 0x113
439#define DP_AUDIO_DELAY2 0x114
440
441#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
442# define DP_LINK_RATE_SET_SHIFT 0
443# define DP_LINK_RATE_SET_MASK (7 << 0)
444
445#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
446# define DP_ALPM_ENABLE (1 << 0)
447# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
448
449#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
450# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
451# define DP_IRQ_HPD_ENABLE (1 << 1)
452
453#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
454# define DP_PWR_NOT_NEEDED (1 << 0)
455
456#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
457# define DP_FEC_READY (1 << 0)
458# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
459# define DP_FEC_ERR_COUNT_DIS (0 << 1)
460# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
461# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
462# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
463# define DP_FEC_LANE_SELECT_MASK (3 << 4)
464# define DP_FEC_LANE_0_SELECT (0 << 4)
465# define DP_FEC_LANE_1_SELECT (1 << 4)
466# define DP_FEC_LANE_2_SELECT (2 << 4)
467# define DP_FEC_LANE_3_SELECT (3 << 4)
468
469#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
470# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
471
472#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
473
474#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
475# define DP_PSR_ENABLE (1 << 0)
476# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
477# define DP_PSR_CRC_VERIFICATION (1 << 2)
478# define DP_PSR_FRAME_CAPTURE (1 << 3)
479# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
480# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
481
482#define DP_ADAPTER_CTRL 0x1a0
483# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
484
485#define DP_BRANCH_DEVICE_CTRL 0x1a1
486# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
487
488#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
489#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
490#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
491
492#define DP_SINK_COUNT 0x200
493/* prior to 1.2 bit 7 was reserved mbz */
494# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
495# define DP_SINK_CP_READY (1 << 6)
496
497#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
498# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
499# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
500# define DP_CP_IRQ (1 << 2)
501# define DP_MCCS_IRQ (1 << 3)
502# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
503# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
504# define DP_SINK_SPECIFIC_IRQ (1 << 6)
505
506#define DP_LANE0_1_STATUS 0x202
507#define DP_LANE2_3_STATUS 0x203
508# define DP_LANE_CR_DONE (1 << 0)
509# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
510# define DP_LANE_SYMBOL_LOCKED (1 << 2)
511
512#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
513 DP_LANE_CHANNEL_EQ_DONE | \
514 DP_LANE_SYMBOL_LOCKED)
515
516#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
517
518#define DP_INTERLANE_ALIGN_DONE (1 << 0)
519#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
520#define DP_LINK_STATUS_UPDATED (1 << 7)
521
522#define DP_SINK_STATUS 0x205
523
524#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
525#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
526
527#define DP_ADJUST_REQUEST_LANE0_1 0x206
528#define DP_ADJUST_REQUEST_LANE2_3 0x207
529# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
530# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
531# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
532# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
533# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
534# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
535# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
536# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
537
538#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
539
540#define DP_TEST_REQUEST 0x218
541# define DP_TEST_LINK_TRAINING (1 << 0)
542# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
543# define DP_TEST_LINK_EDID_READ (1 << 2)
544# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
545# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
546
547#define DP_TEST_LINK_RATE 0x219
548# define DP_LINK_RATE_162 (0x6)
549# define DP_LINK_RATE_27 (0xa)
550
551#define DP_TEST_LANE_COUNT 0x220
552
553#define DP_TEST_PATTERN 0x221
554# define DP_NO_TEST_PATTERN 0x0
555# define DP_COLOR_RAMP 0x1
556# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
557# define DP_COLOR_SQUARE 0x3
558
559#define DP_TEST_H_TOTAL_HI 0x222
560#define DP_TEST_H_TOTAL_LO 0x223
561
562#define DP_TEST_V_TOTAL_HI 0x224
563#define DP_TEST_V_TOTAL_LO 0x225
564
565#define DP_TEST_H_START_HI 0x226
566#define DP_TEST_H_START_LO 0x227
567
568#define DP_TEST_V_START_HI 0x228
569#define DP_TEST_V_START_LO 0x229
570
571#define DP_TEST_HSYNC_HI 0x22A
572# define DP_TEST_HSYNC_POLARITY (1 << 7)
573# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
574#define DP_TEST_HSYNC_WIDTH_LO 0x22B
575
576#define DP_TEST_VSYNC_HI 0x22C
577# define DP_TEST_VSYNC_POLARITY (1 << 7)
578# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
579#define DP_TEST_VSYNC_WIDTH_LO 0x22D
580
581#define DP_TEST_H_WIDTH_HI 0x22E
582#define DP_TEST_H_WIDTH_LO 0x22F
583
584#define DP_TEST_V_HEIGHT_HI 0x230
585#define DP_TEST_V_HEIGHT_LO 0x231
586
587#define DP_TEST_MISC0 0x232
588# define DP_TEST_SYNC_CLOCK (1 << 0)
589# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
590# define DP_TEST_COLOR_FORMAT_SHIFT 1
591# define DP_COLOR_FORMAT_RGB (0 << 1)
592# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
593# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
594# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
595# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
596# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
597# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
598# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
599# define DP_TEST_BIT_DEPTH_SHIFT 5
600# define DP_TEST_BIT_DEPTH_6 (0 << 5)
601# define DP_TEST_BIT_DEPTH_8 (1 << 5)
602# define DP_TEST_BIT_DEPTH_10 (2 << 5)
603# define DP_TEST_BIT_DEPTH_12 (3 << 5)
604# define DP_TEST_BIT_DEPTH_16 (4 << 5)
605
606#define DP_TEST_MISC1 0x233
607# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
608# define DP_TEST_INTERLACED (1 << 1)
609
610#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
611
612#define DP_TEST_MISC0 0x232
613
614#define DP_TEST_CRC_R_CR 0x240
615#define DP_TEST_CRC_G_Y 0x242
616#define DP_TEST_CRC_B_CB 0x244
617
618#define DP_TEST_SINK_MISC 0x246
619# define DP_TEST_CRC_SUPPORTED (1 << 5)
620# define DP_TEST_COUNT_MASK 0xf
621
622#define DP_TEST_PHY_PATTERN 0x248
623#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
624#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
625#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
626#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
627#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
628#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
629#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
630#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
631#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
632#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
633
634#define DP_TEST_RESPONSE 0x260
635# define DP_TEST_ACK (1 << 0)
636# define DP_TEST_NAK (1 << 1)
637# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
638
639#define DP_TEST_EDID_CHECKSUM 0x261
640
641#define DP_TEST_SINK 0x270
642# define DP_TEST_SINK_START (1 << 0)
643
644#define DP_FEC_STATUS 0x280 /* 1.4 */
645# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
646# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
647
648#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
649
650#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
651# define DP_FEC_ERROR_COUNT_MASK 0x7F
652# define DP_FEC_ERR_COUNT_VALID (1 << 7)
653
654#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
655# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
656# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
657
658#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
659/* up to ID_SLOT_63 at 0x2ff */
660
661#define DP_SOURCE_OUI 0x300
662#define DP_SINK_OUI 0x400
663#define DP_BRANCH_OUI 0x500
664#define DP_BRANCH_ID 0x503
665#define DP_BRANCH_REVISION_START 0x509
666#define DP_BRANCH_HW_REV 0x509
667#define DP_BRANCH_SW_REV 0x50A
668
669#define DP_SET_POWER 0x600
670# define DP_SET_POWER_D0 0x1
671# define DP_SET_POWER_D3 0x2
672# define DP_SET_POWER_MASK 0x3
673# define DP_SET_POWER_D3_AUX_ON 0x5
674
675#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
676# define DP_EDP_11 0x00
677# define DP_EDP_12 0x01
678# define DP_EDP_13 0x02
679# define DP_EDP_14 0x03
680
681#define DP_EDP_GENERAL_CAP_1 0x701
682# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
683# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
684# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
685# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
686# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
687# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
688# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
689# define DP_EDP_SET_POWER_CAP (1 << 7)
690
691#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
692# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
693# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
694# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
695# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
696# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
697# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
698# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
699# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
700
701#define DP_EDP_GENERAL_CAP_2 0x703
702# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
703
704#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
705# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
706# define DP_EDP_X_REGION_CAP_SHIFT 0
707# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
708# define DP_EDP_Y_REGION_CAP_SHIFT 4
709
710#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
711# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
712# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
713# define DP_EDP_FRC_ENABLE (1 << 2)
714# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
715# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
716
717#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
718# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
719# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
720# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
721# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
722# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
723# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
724# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
725# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
726# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
727# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
728
729#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
730#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
731
732#define DP_EDP_PWMGEN_BIT_COUNT 0x724
733#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
734#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
735# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
736
737#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
738
739#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
740# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
741
742#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
743#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
744#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
745
746#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
747#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
748#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
749
750#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
751#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
752
753#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
754#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
755
756#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
757#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
758#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
759#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
760
761#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
762/* 0-5 sink count */
763# define DP_SINK_COUNT_CP_READY (1 << 6)
764
765#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
766
767#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
768# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
769# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
770# define DP_CEC_IRQ (1 << 2)
771
772#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
773
774#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
775# define DP_PSR_LINK_CRC_ERROR (1 << 0)
776# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
777# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
778
779#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
780# define DP_PSR_CAPS_CHANGE (1 << 0)
781
782#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
783# define DP_PSR_SINK_INACTIVE 0
784# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
785# define DP_PSR_SINK_ACTIVE_RFB 2
786# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
787# define DP_PSR_SINK_ACTIVE_RESYNC 4
788# define DP_PSR_SINK_INTERNAL_ERROR 7
789# define DP_PSR_SINK_STATE_MASK 0x07
790
791#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
792# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
793# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
794# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
795# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
796
797#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
798# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
799
800#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
801#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
802#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
803#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
804
805#define DP_DP13_DPCD_REV 0x2200
806#define DP_DP13_MAX_LINK_RATE 0x2201
807
808#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
809# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
810# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
811# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
812# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
813# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
814# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
815# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
816# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
817
818/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
819#define DP_CEC_TUNNELING_CAPABILITY 0x3000
820# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
821# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
822# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
823
824#define DP_CEC_TUNNELING_CONTROL 0x3001
825# define DP_CEC_TUNNELING_ENABLE (1 << 0)
826# define DP_CEC_SNOOPING_ENABLE (1 << 1)
827
828#define DP_CEC_RX_MESSAGE_INFO 0x3002
829# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
830# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
831# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
832# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
833# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
834# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
835
836#define DP_CEC_TX_MESSAGE_INFO 0x3003
837# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
838# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
839# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
840# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
841# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
842
843#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
844# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
845# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
846# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
847# define DP_CEC_TX_LINE_ERROR (1 << 5)
848# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
849# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
850
851#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
852# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
853# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
854# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
855# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
856# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
857# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
858# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
859# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
860#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
861# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
862# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
863# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
864# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
865# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
866# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
867# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
868# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
869
870#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
871#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
872#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
873
874#define DP_AUX_HDCP_BKSV 0x68000
875#define DP_AUX_HDCP_RI_PRIME 0x68005
876#define DP_AUX_HDCP_AKSV 0x68007
877#define DP_AUX_HDCP_AN 0x6800C
878#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
879#define DP_AUX_HDCP_BCAPS 0x68028
880# define DP_BCAPS_REPEATER_PRESENT BIT(1)
881# define DP_BCAPS_HDCP_CAPABLE BIT(0)
882#define DP_AUX_HDCP_BSTATUS 0x68029
883# define DP_BSTATUS_REAUTH_REQ BIT(3)
884# define DP_BSTATUS_LINK_FAILURE BIT(2)
885# define DP_BSTATUS_R0_PRIME_READY BIT(1)
886# define DP_BSTATUS_READY BIT(0)
887#define DP_AUX_HDCP_BINFO 0x6802A
888#define DP_AUX_HDCP_KSV_FIFO 0x6802C
889#define DP_AUX_HDCP_AINFO 0x6803B
890
891/* DP 1.2 Sideband message defines */
892/* peer device type - DP 1.2a Table 2-92 */
893#define DP_PEER_DEVICE_NONE 0x0
894#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
895#define DP_PEER_DEVICE_MST_BRANCHING 0x2
896#define DP_PEER_DEVICE_SST_SINK 0x3
897#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
898
899/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
900#define DP_LINK_ADDRESS 0x01
901#define DP_CONNECTION_STATUS_NOTIFY 0x02
902#define DP_ENUM_PATH_RESOURCES 0x10
903#define DP_ALLOCATE_PAYLOAD 0x11
904#define DP_QUERY_PAYLOAD 0x12
905#define DP_RESOURCE_STATUS_NOTIFY 0x13
906#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
907#define DP_REMOTE_DPCD_READ 0x20
908#define DP_REMOTE_DPCD_WRITE 0x21
909#define DP_REMOTE_I2C_READ 0x22
910#define DP_REMOTE_I2C_WRITE 0x23
911#define DP_POWER_UP_PHY 0x24
912#define DP_POWER_DOWN_PHY 0x25
913#define DP_SINK_EVENT_NOTIFY 0x30
914#define DP_QUERY_STREAM_ENC_STATUS 0x38
915
916/* DP 1.2 MST sideband nak reasons - table 2.84 */
917#define DP_NAK_WRITE_FAILURE 0x01
918#define DP_NAK_INVALID_READ 0x02
919#define DP_NAK_CRC_FAILURE 0x03
920#define DP_NAK_BAD_PARAM 0x04
921#define DP_NAK_DEFER 0x05
922#define DP_NAK_LINK_FAILURE 0x06
923#define DP_NAK_NO_RESOURCES 0x07
924#define DP_NAK_DPCD_FAIL 0x08
925#define DP_NAK_I2C_NAK 0x09
926#define DP_NAK_ALLOCATE_FAIL 0x0a
927
928#define MODE_I2C_START 1
929#define MODE_I2C_WRITE 2
930#define MODE_I2C_READ 4
931#define MODE_I2C_STOP 8
932
933/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
934#define DP_MST_PHYSICAL_PORT_0 0
935#define DP_MST_LOGICAL_PORT_0 8
936
937#define DP_LINK_STATUS_SIZE 6
938bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
939 int lane_count);
940bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
941 int lane_count);
942u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
943 int lane);
944u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
945 int lane);
946
947#define DP_BRANCH_OUI_HEADER_SIZE 0xc
948#define DP_RECEIVER_CAP_SIZE 0xf
949#define EDP_PSR_RECEIVER_CAP_SIZE 2
950#define EDP_DISPLAY_CTL_CAP_SIZE 3
951
952void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
953void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
954
955u8 drm_dp_link_rate_to_bw_code(int link_rate);
956int drm_dp_bw_code_to_link_rate(u8 link_bw);
957
958#define DP_SDP_AUDIO_TIMESTAMP 0x01
959#define DP_SDP_AUDIO_STREAM 0x02
960#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
961#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
962#define DP_SDP_ISRC 0x06 /* DP 1.2 */
963#define DP_SDP_VSC 0x07 /* DP 1.2 */
964#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
965#define DP_SDP_PPS 0x10 /* DP 1.4 */
966#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
967#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
968/* 0x80+ CEA-861 infoframe types */
969
970struct edp_sdp_header {
971 u8 HB0; /* Secondary Data Packet ID */
972 u8 HB1; /* Secondary Data Packet Type */
973 u8 HB2; /* 7:5 reserved, 4:0 revision number */
974 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
975} __packed;
976
977#define EDP_SDP_HEADER_REVISION_MASK 0x1F
978#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
979
980struct edp_vsc_psr {
981 struct edp_sdp_header sdp_header;
982 u8 DB0; /* Stereo Interface */
983 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
984 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
985 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
986 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
987 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
988 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
989 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
990 u8 DB8_31[24]; /* Reserved */
991} __packed;
992
993#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
994#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
995#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
996
997int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
998
999static inline int
1000drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1001{
1002 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1003}
1004
1005static inline u8
1006drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1007{
1008 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1009}
1010
1011static inline bool
1012drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1013{
1014 return dpcd[DP_DPCD_REV] >= 0x11 &&
1015 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1016}
1017
1018static inline bool
1019drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1020{
1021 return dpcd[DP_DPCD_REV] >= 0x12 &&
1022 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1023}
1024
1025static inline bool
1026drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1027{
1028 return dpcd[DP_DPCD_REV] >= 0x14 &&
1029 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1030}
1031
1032static inline u8
1033drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1034{
1035 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1036 DP_TRAINING_PATTERN_MASK;
1037}
1038
1039static inline bool
1040drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1041{
1042 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1043}
1044
1045/*
1046 * DisplayPort AUX channel
1047 */
1048
1049/**
1050 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1051 * @address: address of the (first) register to access
1052 * @request: contains the type of transaction (see DP_AUX_* macros)
1053 * @reply: upon completion, contains the reply type of the transaction
1054 * @buffer: pointer to a transmission or reception buffer
1055 * @size: size of @buffer
1056 */
1057struct drm_dp_aux_msg {
1058 unsigned int address;
1059 u8 request;
1060 u8 reply;
1061 void *buffer;
1062 size_t size;
1063};
1064
1065/**
1066 * struct drm_dp_aux - DisplayPort AUX channel
1067 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1068 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1069 * @dev: pointer to struct device that is the parent for this AUX channel
1070 * @crtc: backpointer to the crtc that is currently using this AUX channel
1071 * @hw_mutex: internal mutex used for locking transfers
1072 * @crc_work: worker that captures CRCs for each frame
1073 * @crc_count: counter of captured frame CRCs
1074 * @transfer: transfers a message representing a single AUX transaction
1075 *
1076 * The .dev field should be set to a pointer to the device that implements
1077 * the AUX channel.
1078 *
1079 * The .name field may be used to specify the name of the I2C adapter. If set to
1080 * NULL, dev_name() of .dev will be used.
1081 *
1082 * Drivers provide a hardware-specific implementation of how transactions
1083 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1084 * structure describing the transaction is passed into this function. Upon
1085 * success, the implementation should return the number of payload bytes
1086 * that were transferred, or a negative error-code on failure. Helpers
1087 * propagate errors from the .transfer() function, with the exception of
1088 * the -EBUSY error, which causes a transaction to be retried. On a short,
1089 * helpers will return -EPROTO to make it simpler to check for failure.
1090 *
1091 * An AUX channel can also be used to transport I2C messages to a sink. A
1092 * typical application of that is to access an EDID that's present in the
1093 * sink device. The .transfer() function can also be used to execute such
1094 * transactions. The drm_dp_aux_register() function registers an I2C
1095 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1096 * should call drm_dp_aux_unregister() to remove the I2C adapter.
1097 * The I2C adapter uses long transfers by default; if a partial response is
1098 * received, the adapter will drop down to the size given by the partial
1099 * response for this transaction only.
1100 *
1101 * Note that the aux helper code assumes that the .transfer() function
1102 * only modifies the reply field of the drm_dp_aux_msg structure. The
1103 * retry logic and i2c helpers assume this is the case.
1104 */
1105struct drm_dp_aux {
1106 const char *name;
1107 struct i2c_adapter ddc;
1108 struct device *dev;
1109 struct drm_crtc *crtc;
1110 struct mutex hw_mutex;
1111 struct work_struct crc_work;
1112 u8 crc_count;
1113 ssize_t (*transfer)(struct drm_dp_aux *aux,
1114 struct drm_dp_aux_msg *msg);
1115 /**
1116 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1117 */
1118 unsigned i2c_nack_count;
1119 /**
1120 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1121 */
1122 unsigned i2c_defer_count;
1123};
1124
1125ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1126 void *buffer, size_t size);
1127ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1128 void *buffer, size_t size);
1129
1130/**
1131 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1132 * @aux: DisplayPort AUX channel
1133 * @offset: address of the register to read
1134 * @valuep: location where the value of the register will be stored
1135 *
1136 * Returns the number of bytes transferred (1) on success, or a negative
1137 * error code on failure.
1138 */
1139static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1140 unsigned int offset, u8 *valuep)
1141{
1142 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1143}
1144
1145/**
1146 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1147 * @aux: DisplayPort AUX channel
1148 * @offset: address of the register to write
1149 * @value: value to write to the register
1150 *
1151 * Returns the number of bytes transferred (1) on success, or a negative
1152 * error code on failure.
1153 */
1154static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1155 unsigned int offset, u8 value)
1156{
1157 return drm_dp_dpcd_write(aux, offset, &value, 1);
1158}
1159
1160int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1161 u8 status[DP_LINK_STATUS_SIZE]);
1162
1163/*
1164 * DisplayPort link
1165 */
1166#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
1167
1168struct drm_dp_link {
1169 unsigned char revision;
1170 unsigned int rate;
1171 unsigned int num_lanes;
1172 unsigned long capabilities;
1173};
1174
1175int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1176int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1177int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1178int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1179int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1180 const u8 port_cap[4]);
1181int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1182 const u8 port_cap[4]);
1183int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1184void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1185 const u8 port_cap[4], struct drm_dp_aux *aux);
1186
1187void drm_dp_aux_init(struct drm_dp_aux *aux);
1188int drm_dp_aux_register(struct drm_dp_aux *aux);
1189void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1190
1191int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1192int drm_dp_stop_crc(struct drm_dp_aux *aux);
1193
1194struct drm_dp_dpcd_ident {
1195 u8 oui[3];
1196 u8 device_id[6];
1197 u8 hw_rev;
1198 u8 sw_major_rev;
1199 u8 sw_minor_rev;
1200} __packed;
1201
1202/**
1203 * struct drm_dp_desc - DP branch/sink device descriptor
1204 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1205 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1206 */
1207struct drm_dp_desc {
1208 struct drm_dp_dpcd_ident ident;
1209 u32 quirks;
1210};
1211
1212int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1213 bool is_branch);
1214
1215/**
1216 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1217 *
1218 * Display Port sink and branch devices in the wild have a variety of bugs, try
1219 * to collect them here. The quirks are shared, but it's up to the drivers to
1220 * implement workarounds for them.
1221 */
1222enum drm_dp_quirk {
1223 /**
1224 * @DP_DPCD_QUIRK_LIMITED_M_N:
1225 *
1226 * The device requires main link attributes Mvid and Nvid to be limited
1227 * to 16 bits.
1228 */
1229 DP_DPCD_QUIRK_LIMITED_M_N,
1230};
1231
1232/**
1233 * drm_dp_has_quirk() - does the DP device have a specific quirk
1234 * @desc: Device decriptor filled by drm_dp_read_desc()
1235 * @quirk: Quirk to query for
1236 *
1237 * Return true if DP device identified by @desc has @quirk.
1238 */
1239static inline bool
1240drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1241{
1242 return desc->quirks & BIT(quirk);
1243}
1244
1245#endif /* _DRM_DP_HELPER_H_ */