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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28
29/* From the VESA DisplayPort spec */
30
31#define AUX_NATIVE_WRITE 0x8
32#define AUX_NATIVE_READ 0x9
33#define AUX_I2C_WRITE 0x0
34#define AUX_I2C_READ 0x1
35#define AUX_I2C_STATUS 0x2
36#define AUX_I2C_MOT 0x4
37
38#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
39#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
40#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
41#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
42
43#define AUX_I2C_REPLY_ACK (0x0 << 6)
44#define AUX_I2C_REPLY_NACK (0x1 << 6)
45#define AUX_I2C_REPLY_DEFER (0x2 << 6)
46#define AUX_I2C_REPLY_MASK (0x3 << 6)
47
48/* AUX CH addresses */
49/* DPCD */
50#define DP_DPCD_REV 0x000
51
52#define DP_MAX_LINK_RATE 0x001
53
54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f
56# define DP_TPS3_SUPPORTED (1 << 6)
57# define DP_ENHANCED_FRAME_CAP (1 << 7)
58
59#define DP_MAX_DOWNSPREAD 0x003
60# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
61
62#define DP_NORP 0x004
63
64#define DP_DOWNSTREAMPORT_PRESENT 0x005
65# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
66# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
67/* 00b = DisplayPort */
68/* 01b = Analog */
69/* 10b = TMDS or HDMI */
70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3)
72
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
77/* link configuration */
78#define DP_LINK_BW_SET 0x100
79# define DP_LINK_BW_1_62 0x06
80# define DP_LINK_BW_2_7 0x0a
81# define DP_LINK_BW_5_4 0x14
82
83#define DP_LANE_COUNT_SET 0x101
84# define DP_LANE_COUNT_MASK 0x0f
85# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
86
87#define DP_TRAINING_PATTERN_SET 0x102
88# define DP_TRAINING_PATTERN_DISABLE 0
89# define DP_TRAINING_PATTERN_1 1
90# define DP_TRAINING_PATTERN_2 2
91# define DP_TRAINING_PATTERN_3 3
92# define DP_TRAINING_PATTERN_MASK 0x3
93
94# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
95# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
96# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
97# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
98# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
99
100# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
101# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
102
103# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
104# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
105# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
106# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
107
108#define DP_TRAINING_LANE0_SET 0x103
109#define DP_TRAINING_LANE1_SET 0x104
110#define DP_TRAINING_LANE2_SET 0x105
111#define DP_TRAINING_LANE3_SET 0x106
112
113# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
114# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
115# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
116# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
117# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
118# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
119# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
120
121# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
122# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
123# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
124# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
125# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
126
127# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
128# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
129
130#define DP_DOWNSPREAD_CTRL 0x107
131# define DP_SPREAD_AMP_0_5 (1 << 4)
132
133#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
134# define DP_SET_ANSI_8B10B (1 << 0)
135
136#define DP_LANE0_1_STATUS 0x202
137#define DP_LANE2_3_STATUS 0x203
138# define DP_LANE_CR_DONE (1 << 0)
139# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
140# define DP_LANE_SYMBOL_LOCKED (1 << 2)
141
142#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
143 DP_LANE_CHANNEL_EQ_DONE | \
144 DP_LANE_SYMBOL_LOCKED)
145
146#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
147
148#define DP_INTERLANE_ALIGN_DONE (1 << 0)
149#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
150#define DP_LINK_STATUS_UPDATED (1 << 7)
151
152#define DP_SINK_STATUS 0x205
153
154#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
155#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
156
157#define DP_ADJUST_REQUEST_LANE0_1 0x206
158#define DP_ADJUST_REQUEST_LANE2_3 0x207
159# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
160# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
161# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
162# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
163# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
164# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
165# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
166# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
167
168#define DP_SET_POWER 0x600
169# define DP_SET_POWER_D0 0x1
170# define DP_SET_POWER_D3 0x2
171
172#define MODE_I2C_START 1
173#define MODE_I2C_WRITE 2
174#define MODE_I2C_READ 4
175#define MODE_I2C_STOP 8
176
177struct i2c_algo_dp_aux_data {
178 bool running;
179 u16 address;
180 int (*aux_ch) (struct i2c_adapter *adapter,
181 int mode, uint8_t write_byte,
182 uint8_t *read_byte);
183};
184
185int
186i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
187
188#endif /* _DRM_DP_HELPER_H_ */
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/delay.h>
27#include <linux/i2c.h>
28#include <linux/types.h>
29
30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
44
45/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
46#define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
47#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
48#define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
49#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
50#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
51/* bits per component for non-RAW */
52#define DP_MSA_MISC_6_BPC (0 << 5)
53#define DP_MSA_MISC_8_BPC (1 << 5)
54#define DP_MSA_MISC_10_BPC (2 << 5)
55#define DP_MSA_MISC_12_BPC (3 << 5)
56#define DP_MSA_MISC_16_BPC (4 << 5)
57/* bits per component for RAW */
58#define DP_MSA_MISC_RAW_6_BPC (1 << 5)
59#define DP_MSA_MISC_RAW_7_BPC (2 << 5)
60#define DP_MSA_MISC_RAW_8_BPC (3 << 5)
61#define DP_MSA_MISC_RAW_10_BPC (4 << 5)
62#define DP_MSA_MISC_RAW_12_BPC (5 << 5)
63#define DP_MSA_MISC_RAW_14_BPC (6 << 5)
64#define DP_MSA_MISC_RAW_16_BPC (7 << 5)
65/* pixel encoding/colorimetry format */
66#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
67 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
68#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
69#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
70#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
71#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
72#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
73#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
74#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
75#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
76#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
77#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
78#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
79#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
80#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
81#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
82#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
83#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
84#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
85#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
86
87#define DP_AUX_MAX_PAYLOAD_BYTES 16
88
89#define DP_AUX_I2C_WRITE 0x0
90#define DP_AUX_I2C_READ 0x1
91#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
92#define DP_AUX_I2C_MOT 0x4
93#define DP_AUX_NATIVE_WRITE 0x8
94#define DP_AUX_NATIVE_READ 0x9
95
96#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
97#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
98#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
99#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
100
101#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
102#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
103#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
104#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
105
106/* AUX CH addresses */
107/* DPCD */
108#define DP_DPCD_REV 0x000
109# define DP_DPCD_REV_10 0x10
110# define DP_DPCD_REV_11 0x11
111# define DP_DPCD_REV_12 0x12
112# define DP_DPCD_REV_13 0x13
113# define DP_DPCD_REV_14 0x14
114
115#define DP_MAX_LINK_RATE 0x001
116
117#define DP_MAX_LANE_COUNT 0x002
118# define DP_MAX_LANE_COUNT_MASK 0x1f
119# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
120# define DP_ENHANCED_FRAME_CAP (1 << 7)
121
122#define DP_MAX_DOWNSPREAD 0x003
123# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
124# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
125# define DP_TPS4_SUPPORTED (1 << 7)
126
127#define DP_NORP 0x004
128
129#define DP_DOWNSTREAMPORT_PRESENT 0x005
130# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
131# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
132# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
133# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
134# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
135# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
136# define DP_FORMAT_CONVERSION (1 << 3)
137# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
138
139#define DP_MAIN_LINK_CHANNEL_CODING 0x006
140# define DP_CAP_ANSI_8B10B (1 << 0)
141
142#define DP_DOWN_STREAM_PORT_COUNT 0x007
143# define DP_PORT_COUNT_MASK 0x0f
144# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
145# define DP_OUI_SUPPORT (1 << 7)
146
147#define DP_RECEIVE_PORT_0_CAP_0 0x008
148# define DP_LOCAL_EDID_PRESENT (1 << 1)
149# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
150
151#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
152
153#define DP_RECEIVE_PORT_1_CAP_0 0x00a
154#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
155
156#define DP_I2C_SPEED_CAP 0x00c /* DPI */
157# define DP_I2C_SPEED_1K 0x01
158# define DP_I2C_SPEED_5K 0x02
159# define DP_I2C_SPEED_10K 0x04
160# define DP_I2C_SPEED_100K 0x08
161# define DP_I2C_SPEED_400K 0x10
162# define DP_I2C_SPEED_1M 0x20
163
164#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
165# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
166# define DP_FRAMING_CHANGE_CAP (1 << 1)
167# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
168
169#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
170# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
171# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
172
173#define DP_ADAPTER_CAP 0x00f /* 1.2 */
174# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
175# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
176
177#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
178# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
179
180/* Multiple stream transport */
181#define DP_FAUX_CAP 0x020 /* 1.2 */
182# define DP_FAUX_CAP_1 (1 << 0)
183
184#define DP_MSTM_CAP 0x021 /* 1.2 */
185# define DP_MST_CAP (1 << 0)
186
187#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
188
189/* AV_SYNC_DATA_BLOCK 1.2 */
190#define DP_AV_GRANULARITY 0x023
191# define DP_AG_FACTOR_MASK (0xf << 0)
192# define DP_AG_FACTOR_3MS (0 << 0)
193# define DP_AG_FACTOR_2MS (1 << 0)
194# define DP_AG_FACTOR_1MS (2 << 0)
195# define DP_AG_FACTOR_500US (3 << 0)
196# define DP_AG_FACTOR_200US (4 << 0)
197# define DP_AG_FACTOR_100US (5 << 0)
198# define DP_AG_FACTOR_10US (6 << 0)
199# define DP_AG_FACTOR_1US (7 << 0)
200# define DP_VG_FACTOR_MASK (0xf << 4)
201# define DP_VG_FACTOR_3MS (0 << 4)
202# define DP_VG_FACTOR_2MS (1 << 4)
203# define DP_VG_FACTOR_1MS (2 << 4)
204# define DP_VG_FACTOR_500US (3 << 4)
205# define DP_VG_FACTOR_200US (4 << 4)
206# define DP_VG_FACTOR_100US (5 << 4)
207
208#define DP_AUD_DEC_LAT0 0x024
209#define DP_AUD_DEC_LAT1 0x025
210
211#define DP_AUD_PP_LAT0 0x026
212#define DP_AUD_PP_LAT1 0x027
213
214#define DP_VID_INTER_LAT 0x028
215
216#define DP_VID_PROG_LAT 0x029
217
218#define DP_REP_LAT 0x02a
219
220#define DP_AUD_DEL_INS0 0x02b
221#define DP_AUD_DEL_INS1 0x02c
222#define DP_AUD_DEL_INS2 0x02d
223/* End of AV_SYNC_DATA_BLOCK */
224
225#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
226# define DP_ALPM_CAP (1 << 0)
227
228#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
229# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
230
231#define DP_GUID 0x030 /* 1.2 */
232
233#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
234# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
235
236#define DP_DSC_REV 0x061
237# define DP_DSC_MAJOR_MASK (0xf << 0)
238# define DP_DSC_MINOR_MASK (0xf << 4)
239# define DP_DSC_MAJOR_SHIFT 0
240# define DP_DSC_MINOR_SHIFT 4
241
242#define DP_DSC_RC_BUF_BLK_SIZE 0x062
243# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
244# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
245# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
246# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
247
248#define DP_DSC_RC_BUF_SIZE 0x063
249
250#define DP_DSC_SLICE_CAP_1 0x064
251# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
252# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
253# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
254# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
255# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
256# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
257# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
258
259#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
260# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
261# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
262# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
263# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
264# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
265# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
266# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
267# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
268# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
269# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
270
271#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
272# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
273
274#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
275
276#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
277# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
278# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
279
280#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
281# define DP_DSC_RGB (1 << 0)
282# define DP_DSC_YCbCr444 (1 << 1)
283# define DP_DSC_YCbCr422_Simple (1 << 2)
284# define DP_DSC_YCbCr422_Native (1 << 3)
285# define DP_DSC_YCbCr420_Native (1 << 4)
286
287#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
288# define DP_DSC_8_BPC (1 << 1)
289# define DP_DSC_10_BPC (1 << 2)
290# define DP_DSC_12_BPC (1 << 3)
291
292#define DP_DSC_PEAK_THROUGHPUT 0x06B
293# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
294# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
295# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
296# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
297# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
298# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
299# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
300# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
301# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
302# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
303# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
304# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
305# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
306# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
307# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
308# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
309# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
310# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
311# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
312# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
313# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
314# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
315# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
316# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
317# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
318# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
319# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
320# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
321# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
322# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
323# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
324# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
325# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
326# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
327# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
328# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
329
330#define DP_DSC_MAX_SLICE_WIDTH 0x06C
331#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
332#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
333
334#define DP_DSC_SLICE_CAP_2 0x06D
335# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
336# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
337# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
338
339#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
340# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
341# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
342# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
343# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
344# define DP_DSC_BITS_PER_PIXEL_1 0x4
345
346#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
347# define DP_PSR_IS_SUPPORTED 1
348# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
349# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
350
351#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
352# define DP_PSR_NO_TRAIN_ON_EXIT 1
353# define DP_PSR_SETUP_TIME_330 (0 << 1)
354# define DP_PSR_SETUP_TIME_275 (1 << 1)
355# define DP_PSR_SETUP_TIME_220 (2 << 1)
356# define DP_PSR_SETUP_TIME_165 (3 << 1)
357# define DP_PSR_SETUP_TIME_110 (4 << 1)
358# define DP_PSR_SETUP_TIME_55 (5 << 1)
359# define DP_PSR_SETUP_TIME_0 (6 << 1)
360# define DP_PSR_SETUP_TIME_MASK (7 << 1)
361# define DP_PSR_SETUP_TIME_SHIFT 1
362# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
363# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
364
365#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
366#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
367
368/*
369 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
370 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
371 * each port's descriptor is one byte wide. If it was set, each port's is
372 * four bytes wide, starting with the one byte from the base info. As of
373 * DP interop v1.1a only VGA defines additional detail.
374 */
375
376/* offset 0 */
377#define DP_DOWNSTREAM_PORT_0 0x80
378# define DP_DS_PORT_TYPE_MASK (7 << 0)
379# define DP_DS_PORT_TYPE_DP 0
380# define DP_DS_PORT_TYPE_VGA 1
381# define DP_DS_PORT_TYPE_DVI 2
382# define DP_DS_PORT_TYPE_HDMI 3
383# define DP_DS_PORT_TYPE_NON_EDID 4
384# define DP_DS_PORT_TYPE_DP_DUALMODE 5
385# define DP_DS_PORT_TYPE_WIRELESS 6
386# define DP_DS_PORT_HPD (1 << 3)
387/* offset 1 for VGA is maximum megapixels per second / 8 */
388/* offset 2 */
389# define DP_DS_MAX_BPC_MASK (3 << 0)
390# define DP_DS_8BPC 0
391# define DP_DS_10BPC 1
392# define DP_DS_12BPC 2
393# define DP_DS_16BPC 3
394
395#define DP_MAX_DOWNSTREAM_PORTS 0x10
396
397/* DP Forward error Correction Registers */
398#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
399# define DP_FEC_CAPABLE (1 << 0)
400# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
401# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
402# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
403
404/* DP Extended DSC Capabilities */
405#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
406#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
407#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
408
409/* link configuration */
410#define DP_LINK_BW_SET 0x100
411# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
412# define DP_LINK_BW_1_62 0x06
413# define DP_LINK_BW_2_7 0x0a
414# define DP_LINK_BW_5_4 0x14 /* 1.2 */
415# define DP_LINK_BW_8_1 0x1e /* 1.4 */
416
417#define DP_LANE_COUNT_SET 0x101
418# define DP_LANE_COUNT_MASK 0x0f
419# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
420
421#define DP_TRAINING_PATTERN_SET 0x102
422# define DP_TRAINING_PATTERN_DISABLE 0
423# define DP_TRAINING_PATTERN_1 1
424# define DP_TRAINING_PATTERN_2 2
425# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
426# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
427# define DP_TRAINING_PATTERN_MASK 0x3
428# define DP_TRAINING_PATTERN_MASK_1_4 0xf
429
430/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
431# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
432# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
433# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
434# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
435# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
436
437# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
438# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
439
440# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
441# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
442# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
443# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
444
445#define DP_TRAINING_LANE0_SET 0x103
446#define DP_TRAINING_LANE1_SET 0x104
447#define DP_TRAINING_LANE2_SET 0x105
448#define DP_TRAINING_LANE3_SET 0x106
449
450# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
451# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
452# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
453# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
454# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
455# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
456# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
457
458# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
459# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
460# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
461# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
462# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
463
464# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
465# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
466
467#define DP_DOWNSPREAD_CTRL 0x107
468# define DP_SPREAD_AMP_0_5 (1 << 4)
469# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
470
471#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
472# define DP_SET_ANSI_8B10B (1 << 0)
473
474#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
475/* bitmask as for DP_I2C_SPEED_CAP */
476
477#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
478# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
479# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
480# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
481
482#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
483#define DP_LINK_QUAL_LANE1_SET 0x10c
484#define DP_LINK_QUAL_LANE2_SET 0x10d
485#define DP_LINK_QUAL_LANE3_SET 0x10e
486# define DP_LINK_QUAL_PATTERN_DISABLE 0
487# define DP_LINK_QUAL_PATTERN_D10_2 1
488# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
489# define DP_LINK_QUAL_PATTERN_PRBS7 3
490# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
491# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
492# define DP_LINK_QUAL_PATTERN_MASK 7
493
494#define DP_TRAINING_LANE0_1_SET2 0x10f
495#define DP_TRAINING_LANE2_3_SET2 0x110
496# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
497# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
498# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
499# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
500
501#define DP_MSTM_CTRL 0x111 /* 1.2 */
502# define DP_MST_EN (1 << 0)
503# define DP_UP_REQ_EN (1 << 1)
504# define DP_UPSTREAM_IS_SRC (1 << 2)
505
506#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
507#define DP_AUDIO_DELAY1 0x113
508#define DP_AUDIO_DELAY2 0x114
509
510#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
511# define DP_LINK_RATE_SET_SHIFT 0
512# define DP_LINK_RATE_SET_MASK (7 << 0)
513
514#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
515# define DP_ALPM_ENABLE (1 << 0)
516# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
517
518#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
519# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
520# define DP_IRQ_HPD_ENABLE (1 << 1)
521
522#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
523# define DP_PWR_NOT_NEEDED (1 << 0)
524
525#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
526# define DP_FEC_READY (1 << 0)
527# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
528# define DP_FEC_ERR_COUNT_DIS (0 << 1)
529# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
530# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
531# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
532# define DP_FEC_LANE_SELECT_MASK (3 << 4)
533# define DP_FEC_LANE_0_SELECT (0 << 4)
534# define DP_FEC_LANE_1_SELECT (1 << 4)
535# define DP_FEC_LANE_2_SELECT (2 << 4)
536# define DP_FEC_LANE_3_SELECT (3 << 4)
537
538#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
539# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
540
541#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
542# define DP_DECOMPRESSION_EN (1 << 0)
543
544#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
545# define DP_PSR_ENABLE (1 << 0)
546# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
547# define DP_PSR_CRC_VERIFICATION (1 << 2)
548# define DP_PSR_FRAME_CAPTURE (1 << 3)
549# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
550# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
551# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
552
553#define DP_ADAPTER_CTRL 0x1a0
554# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
555
556#define DP_BRANCH_DEVICE_CTRL 0x1a1
557# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
558
559#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
560#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
561#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
562
563#define DP_SINK_COUNT 0x200
564/* prior to 1.2 bit 7 was reserved mbz */
565# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
566# define DP_SINK_CP_READY (1 << 6)
567
568#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
569# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
570# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
571# define DP_CP_IRQ (1 << 2)
572# define DP_MCCS_IRQ (1 << 3)
573# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
574# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
575# define DP_SINK_SPECIFIC_IRQ (1 << 6)
576
577#define DP_LANE0_1_STATUS 0x202
578#define DP_LANE2_3_STATUS 0x203
579# define DP_LANE_CR_DONE (1 << 0)
580# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
581# define DP_LANE_SYMBOL_LOCKED (1 << 2)
582
583#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
584 DP_LANE_CHANNEL_EQ_DONE | \
585 DP_LANE_SYMBOL_LOCKED)
586
587#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
588
589#define DP_INTERLANE_ALIGN_DONE (1 << 0)
590#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
591#define DP_LINK_STATUS_UPDATED (1 << 7)
592
593#define DP_SINK_STATUS 0x205
594
595#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
596#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
597
598#define DP_ADJUST_REQUEST_LANE0_1 0x206
599#define DP_ADJUST_REQUEST_LANE2_3 0x207
600# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
601# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
602# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
603# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
604# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
605# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
606# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
607# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
608
609#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
610# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
611# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
612# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
613# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
614# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
615# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
616# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
617# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
618
619#define DP_TEST_REQUEST 0x218
620# define DP_TEST_LINK_TRAINING (1 << 0)
621# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
622# define DP_TEST_LINK_EDID_READ (1 << 2)
623# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
624# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
625# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
626# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
627
628#define DP_TEST_LINK_RATE 0x219
629# define DP_LINK_RATE_162 (0x6)
630# define DP_LINK_RATE_27 (0xa)
631
632#define DP_TEST_LANE_COUNT 0x220
633
634#define DP_TEST_PATTERN 0x221
635# define DP_NO_TEST_PATTERN 0x0
636# define DP_COLOR_RAMP 0x1
637# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
638# define DP_COLOR_SQUARE 0x3
639
640#define DP_TEST_H_TOTAL_HI 0x222
641#define DP_TEST_H_TOTAL_LO 0x223
642
643#define DP_TEST_V_TOTAL_HI 0x224
644#define DP_TEST_V_TOTAL_LO 0x225
645
646#define DP_TEST_H_START_HI 0x226
647#define DP_TEST_H_START_LO 0x227
648
649#define DP_TEST_V_START_HI 0x228
650#define DP_TEST_V_START_LO 0x229
651
652#define DP_TEST_HSYNC_HI 0x22A
653# define DP_TEST_HSYNC_POLARITY (1 << 7)
654# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
655#define DP_TEST_HSYNC_WIDTH_LO 0x22B
656
657#define DP_TEST_VSYNC_HI 0x22C
658# define DP_TEST_VSYNC_POLARITY (1 << 7)
659# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
660#define DP_TEST_VSYNC_WIDTH_LO 0x22D
661
662#define DP_TEST_H_WIDTH_HI 0x22E
663#define DP_TEST_H_WIDTH_LO 0x22F
664
665#define DP_TEST_V_HEIGHT_HI 0x230
666#define DP_TEST_V_HEIGHT_LO 0x231
667
668#define DP_TEST_MISC0 0x232
669# define DP_TEST_SYNC_CLOCK (1 << 0)
670# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
671# define DP_TEST_COLOR_FORMAT_SHIFT 1
672# define DP_COLOR_FORMAT_RGB (0 << 1)
673# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
674# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
675# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
676# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
677# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
678# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
679# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
680# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
681# define DP_TEST_BIT_DEPTH_SHIFT 5
682# define DP_TEST_BIT_DEPTH_6 (0 << 5)
683# define DP_TEST_BIT_DEPTH_8 (1 << 5)
684# define DP_TEST_BIT_DEPTH_10 (2 << 5)
685# define DP_TEST_BIT_DEPTH_12 (3 << 5)
686# define DP_TEST_BIT_DEPTH_16 (4 << 5)
687
688#define DP_TEST_MISC1 0x233
689# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
690# define DP_TEST_INTERLACED (1 << 1)
691
692#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
693
694#define DP_TEST_MISC0 0x232
695
696#define DP_TEST_CRC_R_CR 0x240
697#define DP_TEST_CRC_G_Y 0x242
698#define DP_TEST_CRC_B_CB 0x244
699
700#define DP_TEST_SINK_MISC 0x246
701# define DP_TEST_CRC_SUPPORTED (1 << 5)
702# define DP_TEST_COUNT_MASK 0xf
703
704#define DP_PHY_TEST_PATTERN 0x248
705# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
706# define DP_PHY_TEST_PATTERN_NONE 0x0
707# define DP_PHY_TEST_PATTERN_D10_2 0x1
708# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
709# define DP_PHY_TEST_PATTERN_PRBS7 0x3
710# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
711# define DP_PHY_TEST_PATTERN_CP2520 0x5
712
713#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
714#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
715#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
716#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
717#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
718#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
719#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
720#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
721#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
722#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
723#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
724
725#define DP_TEST_RESPONSE 0x260
726# define DP_TEST_ACK (1 << 0)
727# define DP_TEST_NAK (1 << 1)
728# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
729
730#define DP_TEST_EDID_CHECKSUM 0x261
731
732#define DP_TEST_SINK 0x270
733# define DP_TEST_SINK_START (1 << 0)
734#define DP_TEST_AUDIO_MODE 0x271
735#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
736#define DP_TEST_AUDIO_PERIOD_CH1 0x273
737#define DP_TEST_AUDIO_PERIOD_CH2 0x274
738#define DP_TEST_AUDIO_PERIOD_CH3 0x275
739#define DP_TEST_AUDIO_PERIOD_CH4 0x276
740#define DP_TEST_AUDIO_PERIOD_CH5 0x277
741#define DP_TEST_AUDIO_PERIOD_CH6 0x278
742#define DP_TEST_AUDIO_PERIOD_CH7 0x279
743#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
744
745#define DP_FEC_STATUS 0x280 /* 1.4 */
746# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
747# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
748
749#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
750
751#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
752# define DP_FEC_ERROR_COUNT_MASK 0x7F
753# define DP_FEC_ERR_COUNT_VALID (1 << 7)
754
755#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
756# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
757# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
758
759#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
760/* up to ID_SLOT_63 at 0x2ff */
761
762#define DP_SOURCE_OUI 0x300
763#define DP_SINK_OUI 0x400
764#define DP_BRANCH_OUI 0x500
765#define DP_BRANCH_ID 0x503
766#define DP_BRANCH_REVISION_START 0x509
767#define DP_BRANCH_HW_REV 0x509
768#define DP_BRANCH_SW_REV 0x50A
769
770#define DP_SET_POWER 0x600
771# define DP_SET_POWER_D0 0x1
772# define DP_SET_POWER_D3 0x2
773# define DP_SET_POWER_MASK 0x3
774# define DP_SET_POWER_D3_AUX_ON 0x5
775
776#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
777# define DP_EDP_11 0x00
778# define DP_EDP_12 0x01
779# define DP_EDP_13 0x02
780# define DP_EDP_14 0x03
781# define DP_EDP_14a 0x04 /* eDP 1.4a */
782# define DP_EDP_14b 0x05 /* eDP 1.4b */
783
784#define DP_EDP_GENERAL_CAP_1 0x701
785# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
786# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
787# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
788# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
789# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
790# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
791# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
792# define DP_EDP_SET_POWER_CAP (1 << 7)
793
794#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
795# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
796# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
797# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
798# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
799# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
800# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
801# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
802# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
803
804#define DP_EDP_GENERAL_CAP_2 0x703
805# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
806
807#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
808# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
809# define DP_EDP_X_REGION_CAP_SHIFT 0
810# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
811# define DP_EDP_Y_REGION_CAP_SHIFT 4
812
813#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
814# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
815# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
816# define DP_EDP_FRC_ENABLE (1 << 2)
817# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
818# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
819
820#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
821# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
822# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
823# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
824# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
825# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
826# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
827# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
828# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
829# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
830# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
831
832#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
833#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
834
835#define DP_EDP_PWMGEN_BIT_COUNT 0x724
836#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
837#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
838# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
839
840#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
841
842#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
843# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
844
845#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
846#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
847#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
848
849#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
850#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
851#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
852
853#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
854#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
855
856#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
857#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
858
859#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
860#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
861#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
862#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
863
864#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
865/* 0-5 sink count */
866# define DP_SINK_COUNT_CP_READY (1 << 6)
867
868#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
869
870#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
871# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
872# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
873# define DP_CEC_IRQ (1 << 2)
874
875#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
876
877#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
878# define DP_PSR_LINK_CRC_ERROR (1 << 0)
879# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
880# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
881
882#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
883# define DP_PSR_CAPS_CHANGE (1 << 0)
884
885#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
886# define DP_PSR_SINK_INACTIVE 0
887# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
888# define DP_PSR_SINK_ACTIVE_RFB 2
889# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
890# define DP_PSR_SINK_ACTIVE_RESYNC 4
891# define DP_PSR_SINK_INTERNAL_ERROR 7
892# define DP_PSR_SINK_STATE_MASK 0x07
893
894#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
895# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
896# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
897# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
898# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
899
900#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
901# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
902# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
903# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
904# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
905# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
906# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
907# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
908
909#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
910# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
911
912#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
913#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
914#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
915#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
916
917#define DP_DP13_DPCD_REV 0x2200
918#define DP_DP13_MAX_LINK_RATE 0x2201
919
920#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
921# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
922# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
923# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
924# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
925# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
926# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
927# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
928# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
929
930/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
931#define DP_CEC_TUNNELING_CAPABILITY 0x3000
932# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
933# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
934# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
935
936#define DP_CEC_TUNNELING_CONTROL 0x3001
937# define DP_CEC_TUNNELING_ENABLE (1 << 0)
938# define DP_CEC_SNOOPING_ENABLE (1 << 1)
939
940#define DP_CEC_RX_MESSAGE_INFO 0x3002
941# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
942# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
943# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
944# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
945# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
946# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
947
948#define DP_CEC_TX_MESSAGE_INFO 0x3003
949# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
950# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
951# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
952# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
953# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
954
955#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
956# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
957# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
958# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
959# define DP_CEC_TX_LINE_ERROR (1 << 5)
960# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
961# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
962
963#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
964# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
965# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
966# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
967# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
968# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
969# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
970# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
971# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
972#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
973# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
974# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
975# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
976# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
977# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
978# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
979# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
980# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
981
982#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
983#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
984#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
985
986#define DP_AUX_HDCP_BKSV 0x68000
987#define DP_AUX_HDCP_RI_PRIME 0x68005
988#define DP_AUX_HDCP_AKSV 0x68007
989#define DP_AUX_HDCP_AN 0x6800C
990#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
991#define DP_AUX_HDCP_BCAPS 0x68028
992# define DP_BCAPS_REPEATER_PRESENT BIT(1)
993# define DP_BCAPS_HDCP_CAPABLE BIT(0)
994#define DP_AUX_HDCP_BSTATUS 0x68029
995# define DP_BSTATUS_REAUTH_REQ BIT(3)
996# define DP_BSTATUS_LINK_FAILURE BIT(2)
997# define DP_BSTATUS_R0_PRIME_READY BIT(1)
998# define DP_BSTATUS_READY BIT(0)
999#define DP_AUX_HDCP_BINFO 0x6802A
1000#define DP_AUX_HDCP_KSV_FIFO 0x6802C
1001#define DP_AUX_HDCP_AINFO 0x6803B
1002
1003/* DP HDCP2.2 parameter offsets in DPCD address space */
1004#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1005#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1006#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1007#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1008#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1009#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1010#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1011#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1012#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1013#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1014#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1015#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1016#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1017#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1018#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1019#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1020#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1021#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1022#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1023#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1024#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1025#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1026#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1027#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1028#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1029#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1030
1031/* Link Training (LT)-tunable PHY Repeaters */
1032#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1033#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1034#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1035#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1036#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1037#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1038#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1039#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1040#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1041#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1042#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1043#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1044#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1045#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1046#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1047#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1048#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1049#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1050#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1051#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1052#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1053#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1054#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1055#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1056#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1057#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1058
1059/* Repeater modes */
1060#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1061#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1062
1063/* DP HDCP message start offsets in DPCD address space */
1064#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1065#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1066#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1067#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1068#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1069#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1070 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1071#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1072#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1073#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1074#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1075#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1076#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1077#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1078
1079#define HDCP_2_2_DP_RXSTATUS_LEN 1
1080#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1081#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1082#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1083#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1084#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1085
1086/* DP 1.2 Sideband message defines */
1087/* peer device type - DP 1.2a Table 2-92 */
1088#define DP_PEER_DEVICE_NONE 0x0
1089#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1090#define DP_PEER_DEVICE_MST_BRANCHING 0x2
1091#define DP_PEER_DEVICE_SST_SINK 0x3
1092#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1093
1094/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1095#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1096#define DP_LINK_ADDRESS 0x01
1097#define DP_CONNECTION_STATUS_NOTIFY 0x02
1098#define DP_ENUM_PATH_RESOURCES 0x10
1099#define DP_ALLOCATE_PAYLOAD 0x11
1100#define DP_QUERY_PAYLOAD 0x12
1101#define DP_RESOURCE_STATUS_NOTIFY 0x13
1102#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1103#define DP_REMOTE_DPCD_READ 0x20
1104#define DP_REMOTE_DPCD_WRITE 0x21
1105#define DP_REMOTE_I2C_READ 0x22
1106#define DP_REMOTE_I2C_WRITE 0x23
1107#define DP_POWER_UP_PHY 0x24
1108#define DP_POWER_DOWN_PHY 0x25
1109#define DP_SINK_EVENT_NOTIFY 0x30
1110#define DP_QUERY_STREAM_ENC_STATUS 0x38
1111
1112/* DP 1.2 MST sideband reply types */
1113#define DP_SIDEBAND_REPLY_ACK 0x00
1114#define DP_SIDEBAND_REPLY_NAK 0x01
1115
1116/* DP 1.2 MST sideband nak reasons - table 2.84 */
1117#define DP_NAK_WRITE_FAILURE 0x01
1118#define DP_NAK_INVALID_READ 0x02
1119#define DP_NAK_CRC_FAILURE 0x03
1120#define DP_NAK_BAD_PARAM 0x04
1121#define DP_NAK_DEFER 0x05
1122#define DP_NAK_LINK_FAILURE 0x06
1123#define DP_NAK_NO_RESOURCES 0x07
1124#define DP_NAK_DPCD_FAIL 0x08
1125#define DP_NAK_I2C_NAK 0x09
1126#define DP_NAK_ALLOCATE_FAIL 0x0a
1127
1128#define MODE_I2C_START 1
1129#define MODE_I2C_WRITE 2
1130#define MODE_I2C_READ 4
1131#define MODE_I2C_STOP 8
1132
1133/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1134#define DP_MST_PHYSICAL_PORT_0 0
1135#define DP_MST_LOGICAL_PORT_0 8
1136
1137#define DP_LINK_STATUS_SIZE 6
1138bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1139 int lane_count);
1140bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1141 int lane_count);
1142u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1143 int lane);
1144u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1145 int lane);
1146u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
1147 unsigned int lane);
1148
1149#define DP_BRANCH_OUI_HEADER_SIZE 0xc
1150#define DP_RECEIVER_CAP_SIZE 0xf
1151#define DP_DSC_RECEIVER_CAP_SIZE 0xf
1152#define EDP_PSR_RECEIVER_CAP_SIZE 2
1153#define EDP_DISPLAY_CTL_CAP_SIZE 3
1154
1155void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1156void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1157
1158u8 drm_dp_link_rate_to_bw_code(int link_rate);
1159int drm_dp_bw_code_to_link_rate(u8 link_bw);
1160
1161#define DP_SDP_AUDIO_TIMESTAMP 0x01
1162#define DP_SDP_AUDIO_STREAM 0x02
1163#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1164#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1165#define DP_SDP_ISRC 0x06 /* DP 1.2 */
1166#define DP_SDP_VSC 0x07 /* DP 1.2 */
1167#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1168#define DP_SDP_PPS 0x10 /* DP 1.4 */
1169#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1170#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1171/* 0x80+ CEA-861 infoframe types */
1172
1173/**
1174 * struct dp_sdp_header - DP secondary data packet header
1175 * @HB0: Secondary Data Packet ID
1176 * @HB1: Secondary Data Packet Type
1177 * @HB2: Secondary Data Packet Specific header, Byte 0
1178 * @HB3: Secondary Data packet Specific header, Byte 1
1179 */
1180struct dp_sdp_header {
1181 u8 HB0;
1182 u8 HB1;
1183 u8 HB2;
1184 u8 HB3;
1185} __packed;
1186
1187#define EDP_SDP_HEADER_REVISION_MASK 0x1F
1188#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1189#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1190
1191/**
1192 * struct dp_sdp - DP secondary data packet
1193 * @sdp_header: DP secondary data packet header
1194 * @db: DP secondaray data packet data blocks
1195 * VSC SDP Payload for PSR
1196 * db[0]: Stereo Interface
1197 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1198 * db[2]: CRC value bits 7:0 of the R or Cr component
1199 * db[3]: CRC value bits 15:8 of the R or Cr component
1200 * db[4]: CRC value bits 7:0 of the G or Y component
1201 * db[5]: CRC value bits 15:8 of the G or Y component
1202 * db[6]: CRC value bits 7:0 of the B or Cb component
1203 * db[7]: CRC value bits 15:8 of the B or Cb component
1204 * db[8] - db[31]: Reserved
1205 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1206 * db[0] - db[15]: Reserved
1207 * db[16]: Pixel Encoding and Colorimetry Formats
1208 * db[17]: Dynamic Range and Component Bit Depth
1209 * db[18]: Content Type
1210 * db[19] - db[31]: Reserved
1211 */
1212struct dp_sdp {
1213 struct dp_sdp_header sdp_header;
1214 u8 db[32];
1215} __packed;
1216
1217#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1218#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1219#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1220
1221/**
1222 * enum dp_pixelformat - drm DP Pixel encoding formats
1223 *
1224 * This enum is used to indicate DP VSC SDP Pixel encoding formats.
1225 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1226 * DB18]
1227 *
1228 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1229 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1230 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1231 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1232 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1233 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1234 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1235 */
1236enum dp_pixelformat {
1237 DP_PIXELFORMAT_RGB = 0,
1238 DP_PIXELFORMAT_YUV444 = 0x1,
1239 DP_PIXELFORMAT_YUV422 = 0x2,
1240 DP_PIXELFORMAT_YUV420 = 0x3,
1241 DP_PIXELFORMAT_Y_ONLY = 0x4,
1242 DP_PIXELFORMAT_RAW = 0x5,
1243 DP_PIXELFORMAT_RESERVED = 0x6,
1244};
1245
1246/**
1247 * enum dp_colorimetry - drm DP Colorimetry formats
1248 *
1249 * This enum is used to indicate DP VSC SDP Colorimetry formats.
1250 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1251 * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
1252 *
1253 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1254 * ITU-R BT.601 colorimetry format
1255 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1256 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1257 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1258 * (scRGB (IEC 61966-2-2)) colorimetry format
1259 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1260 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1261 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1262 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1263 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1264 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1265 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1266 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1267 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1268 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1269 */
1270enum dp_colorimetry {
1271 DP_COLORIMETRY_DEFAULT = 0,
1272 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1273 DP_COLORIMETRY_BT709_YCC = 0x1,
1274 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1275 DP_COLORIMETRY_XVYCC_601 = 0x2,
1276 DP_COLORIMETRY_OPRGB = 0x3,
1277 DP_COLORIMETRY_XVYCC_709 = 0x3,
1278 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1279 DP_COLORIMETRY_SYCC_601 = 0x4,
1280 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1281 DP_COLORIMETRY_OPYCC_601 = 0x5,
1282 DP_COLORIMETRY_BT2020_RGB = 0x6,
1283 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1284 DP_COLORIMETRY_BT2020_YCC = 0x7,
1285};
1286
1287/**
1288 * enum dp_dynamic_range - drm DP Dynamic Range
1289 *
1290 * This enum is used to indicate DP VSC SDP Dynamic Range.
1291 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1292 * DB18]
1293 *
1294 * @DP_DYNAMIC_RANGE_VESA: VESA range
1295 * @DP_DYNAMIC_RANGE_CTA: CTA range
1296 */
1297enum dp_dynamic_range {
1298 DP_DYNAMIC_RANGE_VESA = 0,
1299 DP_DYNAMIC_RANGE_CTA = 1,
1300};
1301
1302/**
1303 * enum dp_content_type - drm DP Content Type
1304 *
1305 * This enum is used to indicate DP VSC SDP Content Types.
1306 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1307 * DB18]
1308 * CTA-861-G defines content types and expected processing by a sink device
1309 *
1310 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1311 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1312 * @DP_CONTENT_TYPE_PHOTO: Photo type
1313 * @DP_CONTENT_TYPE_VIDEO: Video type
1314 * @DP_CONTENT_TYPE_GAME: Game type
1315 */
1316enum dp_content_type {
1317 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1318 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1319 DP_CONTENT_TYPE_PHOTO = 0x02,
1320 DP_CONTENT_TYPE_VIDEO = 0x03,
1321 DP_CONTENT_TYPE_GAME = 0x04,
1322};
1323
1324/**
1325 * struct drm_dp_vsc_sdp - drm DP VSC SDP
1326 *
1327 * This structure represents a DP VSC SDP of drm
1328 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
1329 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
1330 *
1331 * @sdp_type: secondary-data packet type
1332 * @revision: revision number
1333 * @length: number of valid data bytes
1334 * @pixelformat: pixel encoding format
1335 * @colorimetry: colorimetry format
1336 * @bpc: bit per color
1337 * @dynamic_range: dynamic range information
1338 * @content_type: CTA-861-G defines content types and expected processing by a sink device
1339 */
1340struct drm_dp_vsc_sdp {
1341 unsigned char sdp_type;
1342 unsigned char revision;
1343 unsigned char length;
1344 enum dp_pixelformat pixelformat;
1345 enum dp_colorimetry colorimetry;
1346 int bpc;
1347 enum dp_dynamic_range dynamic_range;
1348 enum dp_content_type content_type;
1349};
1350
1351void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1352 const struct drm_dp_vsc_sdp *vsc);
1353
1354int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1355
1356static inline int
1357drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1358{
1359 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1360}
1361
1362static inline u8
1363drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1364{
1365 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1366}
1367
1368static inline bool
1369drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1370{
1371 return dpcd[DP_DPCD_REV] >= 0x11 &&
1372 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1373}
1374
1375static inline bool
1376drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1377{
1378 return dpcd[DP_DPCD_REV] >= 0x11 &&
1379 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1380}
1381
1382static inline bool
1383drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1384{
1385 return dpcd[DP_DPCD_REV] >= 0x12 &&
1386 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1387}
1388
1389static inline bool
1390drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1391{
1392 return dpcd[DP_DPCD_REV] >= 0x14 &&
1393 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1394}
1395
1396static inline u8
1397drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1398{
1399 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1400 DP_TRAINING_PATTERN_MASK;
1401}
1402
1403static inline bool
1404drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1405{
1406 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1407}
1408
1409/* DP/eDP DSC support */
1410u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1411 bool is_edp);
1412u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1413int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1414 u8 dsc_bpc[3]);
1415
1416static inline bool
1417drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1418{
1419 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1420 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1421}
1422
1423static inline u16
1424drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1425{
1426 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1427 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1428 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1429 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1430}
1431
1432static inline u32
1433drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1434{
1435 /* Max Slicewidth = Number of Pixels * 320 */
1436 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1437 DP_DSC_SLICE_WIDTH_MULTIPLIER;
1438}
1439
1440/* Forward Error Correction Support on DP 1.4 */
1441static inline bool
1442drm_dp_sink_supports_fec(const u8 fec_capable)
1443{
1444 return fec_capable & DP_FEC_CAPABLE;
1445}
1446
1447static inline bool
1448drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1449{
1450 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1451}
1452
1453static inline bool
1454drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1455{
1456 return dpcd[DP_EDP_CONFIGURATION_CAP] &
1457 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1458}
1459
1460/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
1461static inline bool
1462drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1463{
1464 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1465 DP_MSA_TIMING_PAR_IGNORED;
1466}
1467
1468/*
1469 * DisplayPort AUX channel
1470 */
1471
1472/**
1473 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1474 * @address: address of the (first) register to access
1475 * @request: contains the type of transaction (see DP_AUX_* macros)
1476 * @reply: upon completion, contains the reply type of the transaction
1477 * @buffer: pointer to a transmission or reception buffer
1478 * @size: size of @buffer
1479 */
1480struct drm_dp_aux_msg {
1481 unsigned int address;
1482 u8 request;
1483 u8 reply;
1484 void *buffer;
1485 size_t size;
1486};
1487
1488struct cec_adapter;
1489struct edid;
1490struct drm_connector;
1491
1492/**
1493 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1494 * @lock: mutex protecting this struct
1495 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1496 * @connector: the connector this CEC adapter is associated with
1497 * @unregister_work: unregister the CEC adapter
1498 */
1499struct drm_dp_aux_cec {
1500 struct mutex lock;
1501 struct cec_adapter *adap;
1502 struct drm_connector *connector;
1503 struct delayed_work unregister_work;
1504};
1505
1506/**
1507 * struct drm_dp_aux - DisplayPort AUX channel
1508 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1509 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1510 * @dev: pointer to struct device that is the parent for this AUX channel
1511 * @crtc: backpointer to the crtc that is currently using this AUX channel
1512 * @hw_mutex: internal mutex used for locking transfers
1513 * @crc_work: worker that captures CRCs for each frame
1514 * @crc_count: counter of captured frame CRCs
1515 * @transfer: transfers a message representing a single AUX transaction
1516 *
1517 * The .dev field should be set to a pointer to the device that implements
1518 * the AUX channel.
1519 *
1520 * The .name field may be used to specify the name of the I2C adapter. If set to
1521 * NULL, dev_name() of .dev will be used.
1522 *
1523 * Drivers provide a hardware-specific implementation of how transactions
1524 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1525 * structure describing the transaction is passed into this function. Upon
1526 * success, the implementation should return the number of payload bytes
1527 * that were transferred, or a negative error-code on failure. Helpers
1528 * propagate errors from the .transfer() function, with the exception of
1529 * the -EBUSY error, which causes a transaction to be retried. On a short,
1530 * helpers will return -EPROTO to make it simpler to check for failure.
1531 *
1532 * An AUX channel can also be used to transport I2C messages to a sink. A
1533 * typical application of that is to access an EDID that's present in the
1534 * sink device. The .transfer() function can also be used to execute such
1535 * transactions. The drm_dp_aux_register() function registers an I2C
1536 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1537 * should call drm_dp_aux_unregister() to remove the I2C adapter.
1538 * The I2C adapter uses long transfers by default; if a partial response is
1539 * received, the adapter will drop down to the size given by the partial
1540 * response for this transaction only.
1541 *
1542 * Note that the aux helper code assumes that the .transfer() function
1543 * only modifies the reply field of the drm_dp_aux_msg structure. The
1544 * retry logic and i2c helpers assume this is the case.
1545 */
1546struct drm_dp_aux {
1547 const char *name;
1548 struct i2c_adapter ddc;
1549 struct device *dev;
1550 struct drm_crtc *crtc;
1551 struct mutex hw_mutex;
1552 struct work_struct crc_work;
1553 u8 crc_count;
1554 ssize_t (*transfer)(struct drm_dp_aux *aux,
1555 struct drm_dp_aux_msg *msg);
1556 /**
1557 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1558 */
1559 unsigned i2c_nack_count;
1560 /**
1561 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1562 */
1563 unsigned i2c_defer_count;
1564 /**
1565 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1566 */
1567 struct drm_dp_aux_cec cec;
1568 /**
1569 * @is_remote: Is this AUX CH actually using sideband messaging.
1570 */
1571 bool is_remote;
1572};
1573
1574ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1575 void *buffer, size_t size);
1576ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1577 void *buffer, size_t size);
1578
1579/**
1580 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1581 * @aux: DisplayPort AUX channel
1582 * @offset: address of the register to read
1583 * @valuep: location where the value of the register will be stored
1584 *
1585 * Returns the number of bytes transferred (1) on success, or a negative
1586 * error code on failure.
1587 */
1588static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1589 unsigned int offset, u8 *valuep)
1590{
1591 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1592}
1593
1594/**
1595 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1596 * @aux: DisplayPort AUX channel
1597 * @offset: address of the register to write
1598 * @value: value to write to the register
1599 *
1600 * Returns the number of bytes transferred (1) on success, or a negative
1601 * error code on failure.
1602 */
1603static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1604 unsigned int offset, u8 value)
1605{
1606 return drm_dp_dpcd_write(aux, offset, &value, 1);
1607}
1608
1609int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1610 u8 status[DP_LINK_STATUS_SIZE]);
1611
1612bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
1613 u8 real_edid_checksum);
1614
1615int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1616 const u8 port_cap[4]);
1617int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1618 const u8 port_cap[4]);
1619int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1620void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1621 const u8 port_cap[4], struct drm_dp_aux *aux);
1622
1623void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
1624void drm_dp_aux_init(struct drm_dp_aux *aux);
1625int drm_dp_aux_register(struct drm_dp_aux *aux);
1626void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1627
1628int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1629int drm_dp_stop_crc(struct drm_dp_aux *aux);
1630
1631struct drm_dp_dpcd_ident {
1632 u8 oui[3];
1633 u8 device_id[6];
1634 u8 hw_rev;
1635 u8 sw_major_rev;
1636 u8 sw_minor_rev;
1637} __packed;
1638
1639/**
1640 * struct drm_dp_desc - DP branch/sink device descriptor
1641 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1642 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1643 */
1644struct drm_dp_desc {
1645 struct drm_dp_dpcd_ident ident;
1646 u32 quirks;
1647};
1648
1649int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1650 bool is_branch);
1651u32 drm_dp_get_edid_quirks(const struct edid *edid);
1652
1653/**
1654 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1655 *
1656 * Display Port sink and branch devices in the wild have a variety of bugs, try
1657 * to collect them here. The quirks are shared, but it's up to the drivers to
1658 * implement workarounds for them. Note that because some devices have
1659 * unreliable OUIDs, the EDID of sinks should also be checked for quirks using
1660 * drm_dp_get_edid_quirks().
1661 */
1662enum drm_dp_quirk {
1663 /**
1664 * @DP_DPCD_QUIRK_CONSTANT_N:
1665 *
1666 * The device requires main link attributes Mvid and Nvid to be limited
1667 * to 16 bits. So will give a constant value (0x8000) for compatability.
1668 */
1669 DP_DPCD_QUIRK_CONSTANT_N,
1670 /**
1671 * @DP_DPCD_QUIRK_NO_PSR:
1672 *
1673 * The device does not support PSR even if reports that it supports or
1674 * driver still need to implement proper handling for such device.
1675 */
1676 DP_DPCD_QUIRK_NO_PSR,
1677 /**
1678 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
1679 *
1680 * The device does not set SINK_COUNT to a non-zero value.
1681 * The driver should ignore SINK_COUNT during detection.
1682 */
1683 DP_DPCD_QUIRK_NO_SINK_COUNT,
1684 /**
1685 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
1686 *
1687 * The device supports MST DSC despite not supporting Virtual DPCD.
1688 * The DSC caps can be read from the physical aux instead.
1689 */
1690 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
1691 /**
1692 * @DP_QUIRK_FORCE_DPCD_BACKLIGHT:
1693 *
1694 * The device is telling the truth when it says that it uses DPCD
1695 * backlight controls, even if the system's firmware disagrees. This
1696 * quirk should be checked against both the ident and panel EDID.
1697 * When present, the driver should honor the DPCD backlight
1698 * capabilities advertised.
1699 */
1700 DP_QUIRK_FORCE_DPCD_BACKLIGHT,
1701 /**
1702 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
1703 *
1704 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
1705 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
1706 */
1707 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
1708};
1709
1710/**
1711 * drm_dp_has_quirk() - does the DP device have a specific quirk
1712 * @desc: Device descriptor filled by drm_dp_read_desc()
1713 * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks()
1714 * @quirk: Quirk to query for
1715 *
1716 * Return true if DP device identified by @desc has @quirk.
1717 */
1718static inline bool
1719drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks,
1720 enum drm_dp_quirk quirk)
1721{
1722 return (desc->quirks | edid_quirks) & BIT(quirk);
1723}
1724
1725#ifdef CONFIG_DRM_DP_CEC
1726void drm_dp_cec_irq(struct drm_dp_aux *aux);
1727void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1728 struct drm_connector *connector);
1729void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
1730void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
1731void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
1732#else
1733static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
1734{
1735}
1736
1737static inline void
1738drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1739 struct drm_connector *connector)
1740{
1741}
1742
1743static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
1744{
1745}
1746
1747static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
1748 const struct edid *edid)
1749{
1750}
1751
1752static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
1753{
1754}
1755
1756#endif
1757
1758/**
1759 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
1760 * @link_rate: Requested Link rate from DPCD 0x219
1761 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
1762 * @phy_pattern: DP Phy test pattern from DPCD 0x248
1763 * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
1764 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
1765 * @enhanced_frame_cap: flag for enhanced frame capability.
1766 */
1767struct drm_dp_phy_test_params {
1768 int link_rate;
1769 u8 num_lanes;
1770 u8 phy_pattern;
1771 u8 hbr2_reset[2];
1772 u8 custom80[10];
1773 bool enhanced_frame_cap;
1774};
1775
1776int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
1777 struct drm_dp_phy_test_params *data);
1778int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
1779 struct drm_dp_phy_test_params *data, u8 dp_rev);
1780#endif /* _DRM_DP_HELPER_H_ */