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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53
54#include <drm/ttm/ttm_bo.h>
55#include <drm/ttm/ttm_placement.h>
56
57#include <drm/amdgpu_drm.h>
58#include <drm/drm_gem.h>
59#include <drm/drm_ioctl.h>
60
61#include <kgd_kfd_interface.h>
62#include "dm_pp_interface.h"
63#include "kgd_pp_interface.h"
64
65#include "amd_shared.h"
66#include "amdgpu_mode.h"
67#include "amdgpu_ih.h"
68#include "amdgpu_irq.h"
69#include "amdgpu_ucode.h"
70#include "amdgpu_ttm.h"
71#include "amdgpu_psp.h"
72#include "amdgpu_gds.h"
73#include "amdgpu_sync.h"
74#include "amdgpu_ring.h"
75#include "amdgpu_vm.h"
76#include "amdgpu_dpm.h"
77#include "amdgpu_acp.h"
78#include "amdgpu_uvd.h"
79#include "amdgpu_vce.h"
80#include "amdgpu_vcn.h"
81#include "amdgpu_jpeg.h"
82#include "amdgpu_vpe.h"
83#include "amdgpu_umsch_mm.h"
84#include "amdgpu_gmc.h"
85#include "amdgpu_gfx.h"
86#include "amdgpu_sdma.h"
87#include "amdgpu_lsdma.h"
88#include "amdgpu_nbio.h"
89#include "amdgpu_hdp.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_mes_ctx.h"
94#include "amdgpu_gart.h"
95#include "amdgpu_debugfs.h"
96#include "amdgpu_job.h"
97#include "amdgpu_bo_list.h"
98#include "amdgpu_gem.h"
99#include "amdgpu_doorbell.h"
100#include "amdgpu_amdkfd.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_gfxhub.h"
106#include "amdgpu_df.h"
107#include "amdgpu_smuio.h"
108#include "amdgpu_fdinfo.h"
109#include "amdgpu_mca.h"
110#include "amdgpu_aca.h"
111#include "amdgpu_ras.h"
112#include "amdgpu_xcp.h"
113#include "amdgpu_seq64.h"
114#include "amdgpu_reg_state.h"
115
116#define MAX_GPU_INSTANCE 64
117
118struct amdgpu_gpu_instance {
119 struct amdgpu_device *adev;
120 int mgpu_fan_enabled;
121};
122
123struct amdgpu_mgpu_info {
124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
125 struct mutex mutex;
126 uint32_t num_gpu;
127 uint32_t num_dgpu;
128 uint32_t num_apu;
129
130 /* delayed reset_func for XGMI configuration if necessary */
131 struct delayed_work delayed_reset_work;
132 bool pending_reset;
133};
134
135enum amdgpu_ss {
136 AMDGPU_SS_DRV_LOAD,
137 AMDGPU_SS_DEV_D0,
138 AMDGPU_SS_DEV_D3,
139 AMDGPU_SS_DRV_UNLOAD
140};
141
142struct amdgpu_watchdog_timer {
143 bool timeout_fatal_disable;
144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
145};
146
147#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
148
149/*
150 * Modules parameters.
151 */
152extern int amdgpu_modeset;
153extern unsigned int amdgpu_vram_limit;
154extern int amdgpu_vis_vram_limit;
155extern int amdgpu_gart_size;
156extern int amdgpu_gtt_size;
157extern int amdgpu_moverate;
158extern int amdgpu_audio;
159extern int amdgpu_disp_priority;
160extern int amdgpu_hw_i2c;
161extern int amdgpu_pcie_gen2;
162extern int amdgpu_msi;
163extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
164extern int amdgpu_dpm;
165extern int amdgpu_fw_load_type;
166extern int amdgpu_aspm;
167extern int amdgpu_runtime_pm;
168extern uint amdgpu_ip_block_mask;
169extern int amdgpu_bapm;
170extern int amdgpu_deep_color;
171extern int amdgpu_vm_size;
172extern int amdgpu_vm_block_size;
173extern int amdgpu_vm_fragment_size;
174extern int amdgpu_vm_fault_stop;
175extern int amdgpu_vm_debug;
176extern int amdgpu_vm_update_mode;
177extern int amdgpu_exp_hw_support;
178extern int amdgpu_dc;
179extern int amdgpu_sched_jobs;
180extern int amdgpu_sched_hw_submission;
181extern uint amdgpu_pcie_gen_cap;
182extern uint amdgpu_pcie_lane_cap;
183extern u64 amdgpu_cg_mask;
184extern uint amdgpu_pg_mask;
185extern uint amdgpu_sdma_phase_quantum;
186extern char *amdgpu_disable_cu;
187extern char *amdgpu_virtual_display;
188extern uint amdgpu_pp_feature_mask;
189extern uint amdgpu_force_long_training;
190extern int amdgpu_lbpw;
191extern int amdgpu_compute_multipipe;
192extern int amdgpu_gpu_recovery;
193extern int amdgpu_emu_mode;
194extern uint amdgpu_smu_memory_pool_size;
195extern int amdgpu_smu_pptable_id;
196extern uint amdgpu_dc_feature_mask;
197extern uint amdgpu_freesync_vid_mode;
198extern uint amdgpu_dc_debug_mask;
199extern uint amdgpu_dc_visual_confirm;
200extern int amdgpu_dm_abm_level;
201extern int amdgpu_backlight;
202extern int amdgpu_damage_clips;
203extern struct amdgpu_mgpu_info mgpu_info;
204extern int amdgpu_ras_enable;
205extern uint amdgpu_ras_mask;
206extern int amdgpu_bad_page_threshold;
207extern bool amdgpu_ignore_bad_page_threshold;
208extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
209extern int amdgpu_async_gfx_ring;
210extern int amdgpu_mcbp;
211extern int amdgpu_discovery;
212extern int amdgpu_mes;
213extern int amdgpu_mes_log_enable;
214extern int amdgpu_mes_kiq;
215extern int amdgpu_noretry;
216extern int amdgpu_force_asic_type;
217extern int amdgpu_smartshift_bias;
218extern int amdgpu_use_xgmi_p2p;
219extern int amdgpu_mtype_local;
220extern bool enforce_isolation;
221#ifdef CONFIG_HSA_AMD
222extern int sched_policy;
223extern bool debug_evictions;
224extern bool no_system_mem_limit;
225extern int halt_if_hws_hang;
226#else
227static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
228static const bool __maybe_unused debug_evictions; /* = false */
229static const bool __maybe_unused no_system_mem_limit;
230static const int __maybe_unused halt_if_hws_hang;
231#endif
232#ifdef CONFIG_HSA_AMD_P2P
233extern bool pcie_p2p;
234#endif
235
236extern int amdgpu_tmz;
237extern int amdgpu_reset_method;
238
239#ifdef CONFIG_DRM_AMDGPU_SI
240extern int amdgpu_si_support;
241#endif
242#ifdef CONFIG_DRM_AMDGPU_CIK
243extern int amdgpu_cik_support;
244#endif
245extern int amdgpu_num_kcq;
246
247#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
248extern int amdgpu_vcnfw_log;
249extern int amdgpu_sg_display;
250extern int amdgpu_umsch_mm;
251extern int amdgpu_seamless;
252
253extern int amdgpu_user_partt_mode;
254extern int amdgpu_agp;
255
256extern int amdgpu_wbrf;
257
258#define AMDGPU_VM_MAX_NUM_CTX 4096
259#define AMDGPU_SG_THRESHOLD (256*1024*1024)
260#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
261#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
262#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
263#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
264#define AMDGPUFB_CONN_LIMIT 4
265#define AMDGPU_BIOS_NUM_SCRATCH 16
266
267#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
268
269/* hard reset data */
270#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
271
272/* reset flags */
273#define AMDGPU_RESET_GFX (1 << 0)
274#define AMDGPU_RESET_COMPUTE (1 << 1)
275#define AMDGPU_RESET_DMA (1 << 2)
276#define AMDGPU_RESET_CP (1 << 3)
277#define AMDGPU_RESET_GRBM (1 << 4)
278#define AMDGPU_RESET_DMA1 (1 << 5)
279#define AMDGPU_RESET_RLC (1 << 6)
280#define AMDGPU_RESET_SEM (1 << 7)
281#define AMDGPU_RESET_IH (1 << 8)
282#define AMDGPU_RESET_VMC (1 << 9)
283#define AMDGPU_RESET_MC (1 << 10)
284#define AMDGPU_RESET_DISPLAY (1 << 11)
285#define AMDGPU_RESET_UVD (1 << 12)
286#define AMDGPU_RESET_VCE (1 << 13)
287#define AMDGPU_RESET_VCE1 (1 << 14)
288
289/* max cursor sizes (in pixels) */
290#define CIK_CURSOR_WIDTH 128
291#define CIK_CURSOR_HEIGHT 128
292
293/* smart shift bias level limits */
294#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
295#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
296
297/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
298#define AMDGPU_SWCTF_EXTRA_DELAY 50
299
300struct amdgpu_xcp_mgr;
301struct amdgpu_device;
302struct amdgpu_irq_src;
303struct amdgpu_fpriv;
304struct amdgpu_bo_va_mapping;
305struct kfd_vm_fault_info;
306struct amdgpu_hive_info;
307struct amdgpu_reset_context;
308struct amdgpu_reset_control;
309
310enum amdgpu_cp_irq {
311 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
312 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
313 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
314 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
315 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
316 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
317 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
318 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
319 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
320 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
321
322 AMDGPU_CP_IRQ_LAST
323};
324
325enum amdgpu_thermal_irq {
326 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
327 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
328
329 AMDGPU_THERMAL_IRQ_LAST
330};
331
332enum amdgpu_kiq_irq {
333 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
334 AMDGPU_CP_KIQ_IRQ_LAST
335};
336#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
337#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
338#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
339#define MAX_KIQ_REG_TRY 1000
340
341int amdgpu_device_ip_set_clockgating_state(void *dev,
342 enum amd_ip_block_type block_type,
343 enum amd_clockgating_state state);
344int amdgpu_device_ip_set_powergating_state(void *dev,
345 enum amd_ip_block_type block_type,
346 enum amd_powergating_state state);
347void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
348 u64 *flags);
349int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
350 enum amd_ip_block_type block_type);
351bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
352 enum amd_ip_block_type block_type);
353
354#define AMDGPU_MAX_IP_NUM 16
355
356struct amdgpu_ip_block_status {
357 bool valid;
358 bool sw;
359 bool hw;
360 bool late_initialized;
361 bool hang;
362};
363
364struct amdgpu_ip_block_version {
365 const enum amd_ip_block_type type;
366 const u32 major;
367 const u32 minor;
368 const u32 rev;
369 const struct amd_ip_funcs *funcs;
370};
371
372struct amdgpu_ip_block {
373 struct amdgpu_ip_block_status status;
374 const struct amdgpu_ip_block_version *version;
375};
376
377int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
378 enum amd_ip_block_type type,
379 u32 major, u32 minor);
380
381struct amdgpu_ip_block *
382amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
383 enum amd_ip_block_type type);
384
385int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
386 const struct amdgpu_ip_block_version *ip_block_version);
387
388/*
389 * BIOS.
390 */
391bool amdgpu_get_bios(struct amdgpu_device *adev);
392bool amdgpu_read_bios(struct amdgpu_device *adev);
393bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
394 u8 *bios, u32 length_bytes);
395/*
396 * Clocks
397 */
398
399#define AMDGPU_MAX_PPLL 3
400
401struct amdgpu_clock {
402 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
403 struct amdgpu_pll spll;
404 struct amdgpu_pll mpll;
405 /* 10 Khz units */
406 uint32_t default_mclk;
407 uint32_t default_sclk;
408 uint32_t default_dispclk;
409 uint32_t current_dispclk;
410 uint32_t dp_extclk;
411 uint32_t max_pixel_clock;
412};
413
414/* sub-allocation manager, it has to be protected by another lock.
415 * By conception this is an helper for other part of the driver
416 * like the indirect buffer or semaphore, which both have their
417 * locking.
418 *
419 * Principe is simple, we keep a list of sub allocation in offset
420 * order (first entry has offset == 0, last entry has the highest
421 * offset).
422 *
423 * When allocating new object we first check if there is room at
424 * the end total_size - (last_object_offset + last_object_size) >=
425 * alloc_size. If so we allocate new object there.
426 *
427 * When there is not enough room at the end, we start waiting for
428 * each sub object until we reach object_offset+object_size >=
429 * alloc_size, this object then become the sub object we return.
430 *
431 * Alignment can't be bigger than page size.
432 *
433 * Hole are not considered for allocation to keep things simple.
434 * Assumption is that there won't be hole (all object on same
435 * alignment).
436 */
437
438struct amdgpu_sa_manager {
439 struct drm_suballoc_manager base;
440 struct amdgpu_bo *bo;
441 uint64_t gpu_addr;
442 void *cpu_ptr;
443};
444
445int amdgpu_fence_slab_init(void);
446void amdgpu_fence_slab_fini(void);
447
448/*
449 * IRQS.
450 */
451
452struct amdgpu_flip_work {
453 struct delayed_work flip_work;
454 struct work_struct unpin_work;
455 struct amdgpu_device *adev;
456 int crtc_id;
457 u32 target_vblank;
458 uint64_t base;
459 struct drm_pending_vblank_event *event;
460 struct amdgpu_bo *old_abo;
461 unsigned shared_count;
462 struct dma_fence **shared;
463 struct dma_fence_cb cb;
464 bool async;
465};
466
467
468/*
469 * file private structure
470 */
471
472struct amdgpu_fpriv {
473 struct amdgpu_vm vm;
474 struct amdgpu_bo_va *prt_va;
475 struct amdgpu_bo_va *csa_va;
476 struct amdgpu_bo_va *seq64_va;
477 struct mutex bo_list_lock;
478 struct idr bo_list_handles;
479 struct amdgpu_ctx_mgr ctx_mgr;
480 /** GPU partition selection */
481 uint32_t xcp_id;
482};
483
484int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
485
486/*
487 * Writeback
488 */
489#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
490
491struct amdgpu_wb {
492 struct amdgpu_bo *wb_obj;
493 volatile uint32_t *wb;
494 uint64_t gpu_addr;
495 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
496 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
497};
498
499int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
500void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
501
502/*
503 * Benchmarking
504 */
505int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
506
507/*
508 * ASIC specific register table accessible by UMD
509 */
510struct amdgpu_allowed_register_entry {
511 uint32_t reg_offset;
512 bool grbm_indexed;
513};
514
515/**
516 * enum amd_reset_method - Methods for resetting AMD GPU devices
517 *
518 * @AMD_RESET_METHOD_NONE: The device will not be reset.
519 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
520 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
521 * any device.
522 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
523 * individually. Suitable only for some discrete GPU, not
524 * available for all ASICs.
525 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
526 * are reset depends on the ASIC. Notably doesn't reset IPs
527 * shared with the CPU on APUs or the memory controllers (so
528 * VRAM is not lost). Not available on all ASICs.
529 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
530 * but without powering off the PCI bus. Suitable only for
531 * discrete GPUs.
532 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
533 * and does a secondary bus reset or FLR, depending on what the
534 * underlying hardware supports.
535 *
536 * Methods available for AMD GPU driver for resetting the device. Not all
537 * methods are suitable for every device. User can override the method using
538 * module parameter `reset_method`.
539 */
540enum amd_reset_method {
541 AMD_RESET_METHOD_NONE = -1,
542 AMD_RESET_METHOD_LEGACY = 0,
543 AMD_RESET_METHOD_MODE0,
544 AMD_RESET_METHOD_MODE1,
545 AMD_RESET_METHOD_MODE2,
546 AMD_RESET_METHOD_BACO,
547 AMD_RESET_METHOD_PCI,
548};
549
550struct amdgpu_video_codec_info {
551 u32 codec_type;
552 u32 max_width;
553 u32 max_height;
554 u32 max_pixels_per_frame;
555 u32 max_level;
556};
557
558#define codec_info_build(type, width, height, level) \
559 .codec_type = type,\
560 .max_width = width,\
561 .max_height = height,\
562 .max_pixels_per_frame = height * width,\
563 .max_level = level,
564
565struct amdgpu_video_codecs {
566 const u32 codec_count;
567 const struct amdgpu_video_codec_info *codec_array;
568};
569
570/*
571 * ASIC specific functions.
572 */
573struct amdgpu_asic_funcs {
574 bool (*read_disabled_bios)(struct amdgpu_device *adev);
575 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
576 u8 *bios, u32 length_bytes);
577 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
578 u32 sh_num, u32 reg_offset, u32 *value);
579 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
580 int (*reset)(struct amdgpu_device *adev);
581 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
582 /* get the reference clock */
583 u32 (*get_xclk)(struct amdgpu_device *adev);
584 /* MM block clocks */
585 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
586 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
587 /* static power management */
588 int (*get_pcie_lanes)(struct amdgpu_device *adev);
589 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
590 /* get config memsize register */
591 u32 (*get_config_memsize)(struct amdgpu_device *adev);
592 /* flush hdp write queue */
593 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
594 /* invalidate hdp read cache */
595 void (*invalidate_hdp)(struct amdgpu_device *adev,
596 struct amdgpu_ring *ring);
597 /* check if the asic needs a full reset of if soft reset will work */
598 bool (*need_full_reset)(struct amdgpu_device *adev);
599 /* initialize doorbell layout for specific asic*/
600 void (*init_doorbell_index)(struct amdgpu_device *adev);
601 /* PCIe bandwidth usage */
602 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
603 uint64_t *count1);
604 /* do we need to reset the asic at init time (e.g., kexec) */
605 bool (*need_reset_on_init)(struct amdgpu_device *adev);
606 /* PCIe replay counter */
607 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
608 /* device supports BACO */
609 bool (*supports_baco)(struct amdgpu_device *adev);
610 /* pre asic_init quirks */
611 void (*pre_asic_init)(struct amdgpu_device *adev);
612 /* enter/exit umd stable pstate */
613 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
614 /* query video codecs */
615 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
616 const struct amdgpu_video_codecs **codecs);
617 /* encode "> 32bits" smn addressing */
618 u64 (*encode_ext_smn_addressing)(int ext_id);
619
620 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
621 enum amdgpu_reg_state reg_state, void *buf,
622 size_t max_size);
623};
624
625/*
626 * IOCTL.
627 */
628int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
629 struct drm_file *filp);
630
631int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
632int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
633 struct drm_file *filp);
634int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
635int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
636 struct drm_file *filp);
637
638/* VRAM scratch page for HDP bug, default vram page */
639struct amdgpu_mem_scratch {
640 struct amdgpu_bo *robj;
641 volatile uint32_t *ptr;
642 u64 gpu_addr;
643};
644
645/*
646 * CGS
647 */
648struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
649void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
650
651/*
652 * Core structure, functions and helpers.
653 */
654typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
655typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
656
657typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
658typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
659
660typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
661typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
662
663typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
664typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
665
666typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
667typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
668
669struct amdgpu_mmio_remap {
670 u32 reg_offset;
671 resource_size_t bus_addr;
672};
673
674/* Define the HW IP blocks will be used in driver , add more if necessary */
675enum amd_hw_ip_block_type {
676 GC_HWIP = 1,
677 HDP_HWIP,
678 SDMA0_HWIP,
679 SDMA1_HWIP,
680 SDMA2_HWIP,
681 SDMA3_HWIP,
682 SDMA4_HWIP,
683 SDMA5_HWIP,
684 SDMA6_HWIP,
685 SDMA7_HWIP,
686 LSDMA_HWIP,
687 MMHUB_HWIP,
688 ATHUB_HWIP,
689 NBIO_HWIP,
690 MP0_HWIP,
691 MP1_HWIP,
692 UVD_HWIP,
693 VCN_HWIP = UVD_HWIP,
694 JPEG_HWIP = VCN_HWIP,
695 VCN1_HWIP,
696 VCE_HWIP,
697 VPE_HWIP,
698 DF_HWIP,
699 DCE_HWIP,
700 OSSSYS_HWIP,
701 SMUIO_HWIP,
702 PWR_HWIP,
703 NBIF_HWIP,
704 THM_HWIP,
705 CLK_HWIP,
706 UMC_HWIP,
707 RSMU_HWIP,
708 XGMI_HWIP,
709 DCI_HWIP,
710 PCIE_HWIP,
711 MAX_HWIP
712};
713
714#define HWIP_MAX_INSTANCE 44
715
716#define HW_ID_MAX 300
717#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
718 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
719#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
720#define IP_VERSION_MAJ(ver) ((ver) >> 24)
721#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
722#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
723#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
724#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
725#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
726
727struct amdgpu_ip_map_info {
728 /* Map of logical to actual dev instances/mask */
729 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
730 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
731 enum amd_hw_ip_block_type block,
732 int8_t inst);
733 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
734 enum amd_hw_ip_block_type block,
735 uint32_t mask);
736};
737
738struct amd_powerplay {
739 void *pp_handle;
740 const struct amd_pm_funcs *pp_funcs;
741};
742
743struct ip_discovery_top;
744
745/* polaris10 kickers */
746#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
747 ((rid == 0xE3) || \
748 (rid == 0xE4) || \
749 (rid == 0xE5) || \
750 (rid == 0xE7) || \
751 (rid == 0xEF))) || \
752 ((did == 0x6FDF) && \
753 ((rid == 0xE7) || \
754 (rid == 0xEF) || \
755 (rid == 0xFF))))
756
757#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
758 ((rid == 0xE1) || \
759 (rid == 0xF7)))
760
761/* polaris11 kickers */
762#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
763 ((rid == 0xE0) || \
764 (rid == 0xE5))) || \
765 ((did == 0x67FF) && \
766 ((rid == 0xCF) || \
767 (rid == 0xEF) || \
768 (rid == 0xFF))))
769
770#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
771 ((rid == 0xE2)))
772
773/* polaris12 kickers */
774#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
775 ((rid == 0xC0) || \
776 (rid == 0xC1) || \
777 (rid == 0xC3) || \
778 (rid == 0xC7))) || \
779 ((did == 0x6981) && \
780 ((rid == 0x00) || \
781 (rid == 0x01) || \
782 (rid == 0x10))))
783
784struct amdgpu_mqd_prop {
785 uint64_t mqd_gpu_addr;
786 uint64_t hqd_base_gpu_addr;
787 uint64_t rptr_gpu_addr;
788 uint64_t wptr_gpu_addr;
789 uint32_t queue_size;
790 bool use_doorbell;
791 uint32_t doorbell_index;
792 uint64_t eop_gpu_addr;
793 uint32_t hqd_pipe_priority;
794 uint32_t hqd_queue_priority;
795 bool allow_tunneling;
796 bool hqd_active;
797};
798
799struct amdgpu_mqd {
800 unsigned mqd_size;
801 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
802 struct amdgpu_mqd_prop *p);
803};
804
805#define AMDGPU_RESET_MAGIC_NUM 64
806#define AMDGPU_MAX_DF_PERFMONS 4
807struct amdgpu_reset_domain;
808struct amdgpu_fru_info;
809
810struct amdgpu_reset_info {
811 /* reset dump register */
812 u32 *reset_dump_reg_list;
813 u32 *reset_dump_reg_value;
814 int num_regs;
815
816#ifdef CONFIG_DEV_COREDUMP
817 struct amdgpu_coredump_info *coredump_info;
818#endif
819};
820
821/*
822 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
823 */
824#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
825
826struct amdgpu_device {
827 struct device *dev;
828 struct pci_dev *pdev;
829 struct drm_device ddev;
830
831#ifdef CONFIG_DRM_AMD_ACP
832 struct amdgpu_acp acp;
833#endif
834 struct amdgpu_hive_info *hive;
835 struct amdgpu_xcp_mgr *xcp_mgr;
836 /* ASIC */
837 enum amd_asic_type asic_type;
838 uint32_t family;
839 uint32_t rev_id;
840 uint32_t external_rev_id;
841 unsigned long flags;
842 unsigned long apu_flags;
843 int usec_timeout;
844 const struct amdgpu_asic_funcs *asic_funcs;
845 bool shutdown;
846 bool need_swiotlb;
847 bool accel_working;
848 struct notifier_block acpi_nb;
849 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
850 struct debugfs_blob_wrapper debugfs_vbios_blob;
851 struct debugfs_blob_wrapper debugfs_discovery_blob;
852 struct mutex srbm_mutex;
853 /* GRBM index mutex. Protects concurrent access to GRBM index */
854 struct mutex grbm_idx_mutex;
855 struct dev_pm_domain vga_pm_domain;
856 bool have_disp_power_ref;
857 bool have_atomics_support;
858
859 /* BIOS */
860 bool is_atom_fw;
861 uint8_t *bios;
862 uint32_t bios_size;
863 uint32_t bios_scratch_reg_offset;
864 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
865
866 /* Register/doorbell mmio */
867 resource_size_t rmmio_base;
868 resource_size_t rmmio_size;
869 void __iomem *rmmio;
870 /* protects concurrent MM_INDEX/DATA based register access */
871 spinlock_t mmio_idx_lock;
872 struct amdgpu_mmio_remap rmmio_remap;
873 /* protects concurrent SMC based register access */
874 spinlock_t smc_idx_lock;
875 amdgpu_rreg_t smc_rreg;
876 amdgpu_wreg_t smc_wreg;
877 /* protects concurrent PCIE register access */
878 spinlock_t pcie_idx_lock;
879 amdgpu_rreg_t pcie_rreg;
880 amdgpu_wreg_t pcie_wreg;
881 amdgpu_rreg_t pciep_rreg;
882 amdgpu_wreg_t pciep_wreg;
883 amdgpu_rreg_ext_t pcie_rreg_ext;
884 amdgpu_wreg_ext_t pcie_wreg_ext;
885 amdgpu_rreg64_t pcie_rreg64;
886 amdgpu_wreg64_t pcie_wreg64;
887 amdgpu_rreg64_ext_t pcie_rreg64_ext;
888 amdgpu_wreg64_ext_t pcie_wreg64_ext;
889 /* protects concurrent UVD register access */
890 spinlock_t uvd_ctx_idx_lock;
891 amdgpu_rreg_t uvd_ctx_rreg;
892 amdgpu_wreg_t uvd_ctx_wreg;
893 /* protects concurrent DIDT register access */
894 spinlock_t didt_idx_lock;
895 amdgpu_rreg_t didt_rreg;
896 amdgpu_wreg_t didt_wreg;
897 /* protects concurrent gc_cac register access */
898 spinlock_t gc_cac_idx_lock;
899 amdgpu_rreg_t gc_cac_rreg;
900 amdgpu_wreg_t gc_cac_wreg;
901 /* protects concurrent se_cac register access */
902 spinlock_t se_cac_idx_lock;
903 amdgpu_rreg_t se_cac_rreg;
904 amdgpu_wreg_t se_cac_wreg;
905 /* protects concurrent ENDPOINT (audio) register access */
906 spinlock_t audio_endpt_idx_lock;
907 amdgpu_block_rreg_t audio_endpt_rreg;
908 amdgpu_block_wreg_t audio_endpt_wreg;
909 struct amdgpu_doorbell doorbell;
910
911 /* clock/pll info */
912 struct amdgpu_clock clock;
913
914 /* MC */
915 struct amdgpu_gmc gmc;
916 struct amdgpu_gart gart;
917 dma_addr_t dummy_page_addr;
918 struct amdgpu_vm_manager vm_manager;
919 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
920 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
921
922 /* memory management */
923 struct amdgpu_mman mman;
924 struct amdgpu_mem_scratch mem_scratch;
925 struct amdgpu_wb wb;
926 atomic64_t num_bytes_moved;
927 atomic64_t num_evictions;
928 atomic64_t num_vram_cpu_page_faults;
929 atomic_t gpu_reset_counter;
930 atomic_t vram_lost_counter;
931
932 /* data for buffer migration throttling */
933 struct {
934 spinlock_t lock;
935 s64 last_update_us;
936 s64 accum_us; /* accumulated microseconds */
937 s64 accum_us_vis; /* for visible VRAM */
938 u32 log2_max_MBps;
939 } mm_stats;
940
941 /* display */
942 bool enable_virtual_display;
943 struct amdgpu_vkms_output *amdgpu_vkms_output;
944 struct amdgpu_mode_info mode_info;
945 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
946 struct delayed_work hotplug_work;
947 struct amdgpu_irq_src crtc_irq;
948 struct amdgpu_irq_src vline0_irq;
949 struct amdgpu_irq_src vupdate_irq;
950 struct amdgpu_irq_src pageflip_irq;
951 struct amdgpu_irq_src hpd_irq;
952 struct amdgpu_irq_src dmub_trace_irq;
953 struct amdgpu_irq_src dmub_outbox_irq;
954
955 /* rings */
956 u64 fence_context;
957 unsigned num_rings;
958 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
959 struct dma_fence __rcu *gang_submit;
960 bool ib_pool_ready;
961 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
962 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
963
964 /* interrupts */
965 struct amdgpu_irq irq;
966
967 /* powerplay */
968 struct amd_powerplay powerplay;
969 struct amdgpu_pm pm;
970 u64 cg_flags;
971 u32 pg_flags;
972
973 /* nbio */
974 struct amdgpu_nbio nbio;
975
976 /* hdp */
977 struct amdgpu_hdp hdp;
978
979 /* smuio */
980 struct amdgpu_smuio smuio;
981
982 /* mmhub */
983 struct amdgpu_mmhub mmhub;
984
985 /* gfxhub */
986 struct amdgpu_gfxhub gfxhub;
987
988 /* gfx */
989 struct amdgpu_gfx gfx;
990
991 /* sdma */
992 struct amdgpu_sdma sdma;
993
994 /* lsdma */
995 struct amdgpu_lsdma lsdma;
996
997 /* uvd */
998 struct amdgpu_uvd uvd;
999
1000 /* vce */
1001 struct amdgpu_vce vce;
1002
1003 /* vcn */
1004 struct amdgpu_vcn vcn;
1005
1006 /* jpeg */
1007 struct amdgpu_jpeg jpeg;
1008
1009 /* vpe */
1010 struct amdgpu_vpe vpe;
1011
1012 /* umsch */
1013 struct amdgpu_umsch_mm umsch_mm;
1014 bool enable_umsch_mm;
1015
1016 /* firmwares */
1017 struct amdgpu_firmware firmware;
1018
1019 /* PSP */
1020 struct psp_context psp;
1021
1022 /* GDS */
1023 struct amdgpu_gds gds;
1024
1025 /* for userq and VM fences */
1026 struct amdgpu_seq64 seq64;
1027
1028 /* KFD */
1029 struct amdgpu_kfd_dev kfd;
1030
1031 /* UMC */
1032 struct amdgpu_umc umc;
1033
1034 /* display related functionality */
1035 struct amdgpu_display_manager dm;
1036
1037 /* mes */
1038 bool enable_mes;
1039 bool enable_mes_kiq;
1040 struct amdgpu_mes mes;
1041 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1042
1043 /* df */
1044 struct amdgpu_df df;
1045
1046 /* MCA */
1047 struct amdgpu_mca mca;
1048
1049 /* ACA */
1050 struct amdgpu_aca aca;
1051
1052 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1053 uint32_t harvest_ip_mask;
1054 int num_ip_blocks;
1055 struct mutex mn_lock;
1056 DECLARE_HASHTABLE(mn_hash, 7);
1057
1058 /* tracking pinned memory */
1059 atomic64_t vram_pin_size;
1060 atomic64_t visible_pin_size;
1061 atomic64_t gart_pin_size;
1062
1063 /* soc15 register offset based on ip, instance and segment */
1064 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1065 struct amdgpu_ip_map_info ip_map;
1066
1067 /* delayed work_func for deferring clockgating during resume */
1068 struct delayed_work delayed_init_work;
1069
1070 struct amdgpu_virt virt;
1071
1072 /* link all shadow bo */
1073 struct list_head shadow_list;
1074 struct mutex shadow_list_lock;
1075
1076 /* record hw reset is performed */
1077 bool has_hw_reset;
1078 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1079
1080 /* s3/s4 mask */
1081 bool in_suspend;
1082 bool in_s3;
1083 bool in_s4;
1084 bool in_s0ix;
1085 /* indicate amdgpu suspension status */
1086 bool suspend_complete;
1087
1088 enum pp_mp1_state mp1_state;
1089 struct amdgpu_doorbell_index doorbell_index;
1090
1091 struct mutex notifier_lock;
1092
1093 int asic_reset_res;
1094 struct work_struct xgmi_reset_work;
1095 struct list_head reset_list;
1096
1097 long gfx_timeout;
1098 long sdma_timeout;
1099 long video_timeout;
1100 long compute_timeout;
1101 long psp_timeout;
1102
1103 uint64_t unique_id;
1104 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1105
1106 /* enable runtime pm on the device */
1107 bool in_runpm;
1108 bool has_pr3;
1109
1110 bool ucode_sysfs_en;
1111
1112 struct amdgpu_fru_info *fru_info;
1113 atomic_t throttling_logging_enabled;
1114 struct ratelimit_state throttling_logging_rs;
1115 uint32_t ras_hw_enabled;
1116 uint32_t ras_enabled;
1117
1118 bool no_hw_access;
1119 struct pci_saved_state *pci_state;
1120 pci_channel_state_t pci_channel_state;
1121
1122 /* Track auto wait count on s_barrier settings */
1123 bool barrier_has_auto_waitcnt;
1124
1125 struct amdgpu_reset_control *reset_cntl;
1126 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1127
1128 bool ram_is_direct_mapped;
1129
1130 struct list_head ras_list;
1131
1132 struct ip_discovery_top *ip_top;
1133
1134 struct amdgpu_reset_domain *reset_domain;
1135
1136 struct mutex benchmark_mutex;
1137
1138 struct amdgpu_reset_info reset_info;
1139
1140 bool scpm_enabled;
1141 uint32_t scpm_status;
1142
1143 struct work_struct reset_work;
1144
1145 bool job_hang;
1146 bool dc_enabled;
1147 /* Mask of active clusters */
1148 uint32_t aid_mask;
1149
1150 /* Debug */
1151 bool debug_vm;
1152 bool debug_largebar;
1153 bool debug_disable_soft_recovery;
1154 bool debug_use_vram_fw_buf;
1155};
1156
1157static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1158 uint8_t ip, uint8_t inst)
1159{
1160 /* This considers only major/minor/rev and ignores
1161 * subrevision/variant fields.
1162 */
1163 return adev->ip_versions[ip][inst] & ~0xFFU;
1164}
1165
1166static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1167 uint8_t ip, uint8_t inst)
1168{
1169 /* This returns full version - major/minor/rev/variant/subrevision */
1170 return adev->ip_versions[ip][inst];
1171}
1172
1173static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1174{
1175 return container_of(ddev, struct amdgpu_device, ddev);
1176}
1177
1178static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1179{
1180 return &adev->ddev;
1181}
1182
1183static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1184{
1185 return container_of(bdev, struct amdgpu_device, mman.bdev);
1186}
1187
1188int amdgpu_device_init(struct amdgpu_device *adev,
1189 uint32_t flags);
1190void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1191void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1192
1193int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1194
1195void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1196 void *buf, size_t size, bool write);
1197size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1198 void *buf, size_t size, bool write);
1199
1200void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1201 void *buf, size_t size, bool write);
1202uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1203 uint32_t inst, uint32_t reg_addr, char reg_name[],
1204 uint32_t expected_value, uint32_t mask);
1205uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1206 uint32_t reg, uint32_t acc_flags);
1207u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1208 u64 reg_addr);
1209uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1210 uint32_t reg, uint32_t acc_flags,
1211 uint32_t xcc_id);
1212void amdgpu_device_wreg(struct amdgpu_device *adev,
1213 uint32_t reg, uint32_t v,
1214 uint32_t acc_flags);
1215void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1216 u64 reg_addr, u32 reg_data);
1217void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1218 uint32_t reg, uint32_t v,
1219 uint32_t acc_flags,
1220 uint32_t xcc_id);
1221void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1222 uint32_t reg, uint32_t v, uint32_t xcc_id);
1223void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1224uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1225
1226u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1227 u32 reg_addr);
1228u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1229 u32 reg_addr);
1230u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1231 u64 reg_addr);
1232void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1233 u32 reg_addr, u32 reg_data);
1234void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1235 u32 reg_addr, u64 reg_data);
1236void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1237 u64 reg_addr, u64 reg_data);
1238u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1239bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1240bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1241
1242void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1243
1244int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1245 struct amdgpu_reset_context *reset_context);
1246
1247int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1248 struct amdgpu_reset_context *reset_context);
1249
1250int emu_soc_asic_init(struct amdgpu_device *adev);
1251
1252/*
1253 * Registers read & write functions.
1254 */
1255#define AMDGPU_REGS_NO_KIQ (1<<1)
1256#define AMDGPU_REGS_RLC (1<<2)
1257
1258#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1259#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1260
1261#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1262#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1263
1264#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1265#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1266
1267#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1268#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1269#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1270#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1271#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1272#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1273#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1274#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1275#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1276#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1277#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1278#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1279#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1280#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1281#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1282#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1283#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1284#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1285#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1286#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1287#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1288#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1289#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1290#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1291#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1292#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1293#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1294#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1295#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1296#define WREG32_P(reg, val, mask) \
1297 do { \
1298 uint32_t tmp_ = RREG32(reg); \
1299 tmp_ &= (mask); \
1300 tmp_ |= ((val) & ~(mask)); \
1301 WREG32(reg, tmp_); \
1302 } while (0)
1303#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1304#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1305#define WREG32_PLL_P(reg, val, mask) \
1306 do { \
1307 uint32_t tmp_ = RREG32_PLL(reg); \
1308 tmp_ &= (mask); \
1309 tmp_ |= ((val) & ~(mask)); \
1310 WREG32_PLL(reg, tmp_); \
1311 } while (0)
1312
1313#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1314 do { \
1315 u32 tmp = RREG32_SMC(_Reg); \
1316 tmp &= (_Mask); \
1317 tmp |= ((_Val) & ~(_Mask)); \
1318 WREG32_SMC(_Reg, tmp); \
1319 } while (0)
1320
1321#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1322
1323#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1324#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1325
1326#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1327 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1328 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1329
1330#define REG_GET_FIELD(value, reg, field) \
1331 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1332
1333#define WREG32_FIELD(reg, field, val) \
1334 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1335
1336#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1337 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1338
1339#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1340/*
1341 * BIOS helpers.
1342 */
1343#define RBIOS8(i) (adev->bios[i])
1344#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1345#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1346
1347/*
1348 * ASICs macro.
1349 */
1350#define amdgpu_asic_set_vga_state(adev, state) \
1351 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1352#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1353#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1354#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1355#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1356#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1357#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1358#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1359#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1360#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1361#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1362#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1363#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1364#define amdgpu_asic_flush_hdp(adev, r) \
1365 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1366#define amdgpu_asic_invalidate_hdp(adev, r) \
1367 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1368 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1369#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1370#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1371#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1372#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1373#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1374#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1375#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1376#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1377 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1378#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1379
1380#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1381
1382#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1383#define for_each_inst(i, inst_mask) \
1384 for (i = ffs(inst_mask); i-- != 0; \
1385 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1386
1387/* Common functions */
1388bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1389bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1390int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1391 struct amdgpu_job *job,
1392 struct amdgpu_reset_context *reset_context);
1393void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1394int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1395bool amdgpu_device_need_post(struct amdgpu_device *adev);
1396bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1397bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1398
1399void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1400 u64 num_vis_bytes);
1401int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1402void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1403 const u32 *registers,
1404 const u32 array_size);
1405
1406int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1407bool amdgpu_device_supports_atpx(struct drm_device *dev);
1408bool amdgpu_device_supports_px(struct drm_device *dev);
1409bool amdgpu_device_supports_boco(struct drm_device *dev);
1410bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1411bool amdgpu_device_supports_baco(struct drm_device *dev);
1412bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1413 struct amdgpu_device *peer_adev);
1414int amdgpu_device_baco_enter(struct drm_device *dev);
1415int amdgpu_device_baco_exit(struct drm_device *dev);
1416
1417void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1418 struct amdgpu_ring *ring);
1419void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1420 struct amdgpu_ring *ring);
1421
1422void amdgpu_device_halt(struct amdgpu_device *adev);
1423u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1424 u32 reg);
1425void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1426 u32 reg, u32 v);
1427struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1428 struct dma_fence *gang);
1429bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1430
1431/* atpx handler */
1432#if defined(CONFIG_VGA_SWITCHEROO)
1433void amdgpu_register_atpx_handler(void);
1434void amdgpu_unregister_atpx_handler(void);
1435bool amdgpu_has_atpx_dgpu_power_cntl(void);
1436bool amdgpu_is_atpx_hybrid(void);
1437bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1438bool amdgpu_has_atpx(void);
1439#else
1440static inline void amdgpu_register_atpx_handler(void) {}
1441static inline void amdgpu_unregister_atpx_handler(void) {}
1442static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1443static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1444static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1445static inline bool amdgpu_has_atpx(void) { return false; }
1446#endif
1447
1448#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1449void *amdgpu_atpx_get_dhandle(void);
1450#else
1451static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1452#endif
1453
1454/*
1455 * KMS
1456 */
1457extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1458extern const int amdgpu_max_kms_ioctl;
1459
1460int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1461void amdgpu_driver_unload_kms(struct drm_device *dev);
1462void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1463int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1464void amdgpu_driver_postclose_kms(struct drm_device *dev,
1465 struct drm_file *file_priv);
1466void amdgpu_driver_release_kms(struct drm_device *dev);
1467
1468int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1469int amdgpu_device_prepare(struct drm_device *dev);
1470int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1471int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1472u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1473int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1474void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1475int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1476 struct drm_file *filp);
1477
1478/*
1479 * functions used by amdgpu_encoder.c
1480 */
1481struct amdgpu_afmt_acr {
1482 u32 clock;
1483
1484 int n_32khz;
1485 int cts_32khz;
1486
1487 int n_44_1khz;
1488 int cts_44_1khz;
1489
1490 int n_48khz;
1491 int cts_48khz;
1492
1493};
1494
1495struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1496
1497/* amdgpu_acpi.c */
1498
1499struct amdgpu_numa_info {
1500 uint64_t size;
1501 int pxm;
1502 int nid;
1503};
1504
1505/* ATCS Device/Driver State */
1506#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1507#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1508#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1509#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1510
1511#if defined(CONFIG_ACPI)
1512int amdgpu_acpi_init(struct amdgpu_device *adev);
1513void amdgpu_acpi_fini(struct amdgpu_device *adev);
1514bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1515bool amdgpu_acpi_is_power_shift_control_supported(void);
1516int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1517 u8 perf_req, bool advertise);
1518int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1519 u8 dev_state, bool drv_state);
1520int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1521int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1522int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1523 u64 *tmr_size);
1524int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1525 struct amdgpu_numa_info *numa_info);
1526
1527void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1528bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1529void amdgpu_acpi_detect(void);
1530void amdgpu_acpi_release(void);
1531#else
1532static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1533static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1534 u64 *tmr_offset, u64 *tmr_size)
1535{
1536 return -EINVAL;
1537}
1538static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1539 int xcc_id,
1540 struct amdgpu_numa_info *numa_info)
1541{
1542 return -EINVAL;
1543}
1544static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1545static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1546static inline void amdgpu_acpi_detect(void) { }
1547static inline void amdgpu_acpi_release(void) { }
1548static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1549static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1550 u8 dev_state, bool drv_state) { return 0; }
1551static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1552 enum amdgpu_ss ss_state) { return 0; }
1553#endif
1554
1555#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1556bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1557bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1558void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
1559#else
1560static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1561static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1562static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
1563#endif
1564
1565#if defined(CONFIG_DRM_AMD_DC)
1566int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1567#else
1568static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1569#endif
1570
1571
1572void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1573void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1574
1575pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1576 pci_channel_state_t state);
1577pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1578pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1579void amdgpu_pci_resume(struct pci_dev *pdev);
1580
1581bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1582bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1583
1584bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1585
1586int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1587 enum amd_clockgating_state state);
1588int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1589 enum amd_powergating_state state);
1590
1591static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1592{
1593 return amdgpu_gpu_recovery != 0 &&
1594 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1595 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1596 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1597 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1598}
1599
1600#include "amdgpu_object.h"
1601
1602static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1603{
1604 return adev->gmc.tmz_enabled;
1605}
1606
1607int amdgpu_in_reset(struct amdgpu_device *adev);
1608
1609extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1610extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1611extern const struct attribute_group amdgpu_flash_attr_group;
1612
1613#endif