1/*
  2 * Copyright 2014 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef __AMDGPU_IH_H__
 25#define __AMDGPU_IH_H__
 26
 27/* Maximum number of IVs processed at once */
 28#define AMDGPU_IH_MAX_NUM_IVS	32
 29
 30#define IH_RING_SIZE	(256 * 1024)
 31#define IH_SW_RING_SIZE	(16 * 1024)	/* enough for 512 CAM entries */
 32
 33struct amdgpu_device;
 34struct amdgpu_iv_entry;
 35
 36struct amdgpu_ih_regs {
 37	uint32_t ih_rb_base;
 38	uint32_t ih_rb_base_hi;
 39	uint32_t ih_rb_cntl;
 40	uint32_t ih_rb_wptr;
 41	uint32_t ih_rb_rptr;
 42	uint32_t ih_doorbell_rptr;
 43	uint32_t ih_rb_wptr_addr_lo;
 44	uint32_t ih_rb_wptr_addr_hi;
 45	uint32_t psp_reg_id;
 46};
 47
 48/*
 49 * R6xx+ IH ring
 50 */
 51struct amdgpu_ih_ring {
 52	unsigned		ring_size;
 53	uint32_t		ptr_mask;
 54	u32			doorbell_index;
 55	bool			use_doorbell;
 56	bool			use_bus_addr;
 57
 58	struct amdgpu_bo	*ring_obj;
 59	volatile uint32_t	*ring;
 60	uint64_t		gpu_addr;
 61
 62	uint64_t		wptr_addr;
 63	volatile uint32_t	*wptr_cpu;
 64
 65	uint64_t		rptr_addr;
 66	volatile uint32_t	*rptr_cpu;
 67
 68	bool                    enabled;
 69	unsigned		rptr;
 70	struct amdgpu_ih_regs	ih_regs;
 71
 72	/* For waiting on IH processing at checkpoint. */
 73	wait_queue_head_t wait_process;
 74	uint64_t		processed_timestamp;
 75};
 76
 77/* return true if time stamp t2 is after t1 with 48bit wrap around */
 78#define amdgpu_ih_ts_after(t1, t2) \
 79		(((int64_t)((t2) << 16) - (int64_t)((t1) << 16)) > 0LL)
 80
 81/* provided by the ih block */
 82struct amdgpu_ih_funcs {
 83	/* ring read/write ptr handling, called from interrupt context */
 84	u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
 85	void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
 86			  struct amdgpu_iv_entry *entry);
 87	uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
 88				 signed int offset);
 89	void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
 90};
 91
 92#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
 93#define amdgpu_ih_decode_iv(adev, iv) \
 94	(adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
 95#define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \
 96	(WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \
 97	(adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset)))
 98#define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
 99
100int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
101			unsigned ring_size, bool use_bus_addr);
102void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
103void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
104			  const uint32_t *iv, unsigned int num_dw);
105int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
106					    struct amdgpu_ih_ring *ih);
107int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
108void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
109				struct amdgpu_ih_ring *ih,
110				struct amdgpu_iv_entry *entry);
111uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
112				       signed int offset);
113#endif