1/*
  2 * Copyright (C) 2019  Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included
 12 * in all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 20 */
 21#ifndef __AMDGPU_UMC_H__
 22#define __AMDGPU_UMC_H__
 23#include "amdgpu_ras.h"
 24#include "amdgpu_mca.h"
 25/*
 26 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
 27 * is the index of 4KB block
 28 */
 29#define ADDR_OF_4KB_BLOCK(addr)			(((addr) & ~0xffULL) << 4)
 30/*
 31 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
 32 * is the index of 8KB block
 33 */
 34#define ADDR_OF_8KB_BLOCK(addr)			(((addr) & ~0xffULL) << 5)
 35/*
 36 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr
 37 * is the index of 8KB block
 38 */
 39#define ADDR_OF_32KB_BLOCK(addr)			(((addr) & ~0xffULL) << 7)
 40/* channel index is the index of 256B block */
 41#define ADDR_OF_256B_BLOCK(channel_index)	((channel_index) << 8)
 42/* offset in 256B block */
 43#define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)
 44
 45#define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
 46#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
 47#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
 48
 49#define LOOP_UMC_NODE_INST(node_inst) \
 50		for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
 51
 52#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
 53		LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
 54
 55
 56typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
 57			uint32_t umc_inst, uint32_t ch_inst, void *data);
 58
 59struct amdgpu_umc_ras {
 60	struct amdgpu_ras_block_object ras_block;
 61	void (*err_cnt_init)(struct amdgpu_device *adev);
 62	bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
 63	void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
 64				      void *ras_error_status);
 65	void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
 66					void *ras_error_status);
 67	bool (*check_ecc_err_status)(struct amdgpu_device *adev,
 68			enum amdgpu_mca_error_type type, void *ras_error_status);
 69	/* support different eeprom table version for different asic */
 70	void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr);
 71};
 72
 73struct amdgpu_umc_funcs {
 74	void (*init_registers)(struct amdgpu_device *adev);
 75};
 76
 77struct amdgpu_umc {
 78	/* max error count in one ras query call */
 79	uint32_t max_ras_err_cnt_per_query;
 80	/* number of umc channel instance with memory map register access */
 81	uint32_t channel_inst_num;
 82	/* number of umc instance with memory map register access */
 83	uint32_t umc_inst_num;
 84
 85	/* Total number of umc node instance including harvest one */
 86	uint32_t node_inst_num;
 87
 88	/* UMC regiser per channel offset */
 89	uint32_t channel_offs;
 90	/* how many pages are retired in one UE */
 91	uint32_t retire_unit;
 92	/* channel index table of interleaved memory */
 93	const uint32_t *channel_idx_tbl;
 94	struct ras_common_if *ras_if;
 95
 96	const struct amdgpu_umc_funcs *funcs;
 97	struct amdgpu_umc_ras *ras;
 98
 99	/* active mask for umc node instance */
100	unsigned long active_mask;
101};
102
103int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);
104int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
105int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
106			enum amdgpu_ras_block block, bool reset);
107int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
108		struct amdgpu_irq_src *source,
109		struct amdgpu_iv_entry *entry);
110void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
111		uint64_t err_addr,
112		uint64_t retired_page,
113		uint32_t channel_index,
114		uint32_t umc_inst);
115
116int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
117		void *ras_error_status,
118		struct amdgpu_iv_entry *entry);
119int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
120			uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);
121
122int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
123			umc_func func, void *data);
124
125int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,
126			bool reset, uint32_t timeout_ms);
127#endif