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1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/led.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
36
37#define DRV_NAME "flexcan"
38
39/* 8 for RX fifo and 2 error handling */
40#define FLEXCAN_NAPI_WEIGHT (8 + 2)
41
42/* FLEXCAN module configuration register (CANMCR) bits */
43#define FLEXCAN_MCR_MDIS BIT(31)
44#define FLEXCAN_MCR_FRZ BIT(30)
45#define FLEXCAN_MCR_FEN BIT(29)
46#define FLEXCAN_MCR_HALT BIT(28)
47#define FLEXCAN_MCR_NOT_RDY BIT(27)
48#define FLEXCAN_MCR_WAK_MSK BIT(26)
49#define FLEXCAN_MCR_SOFTRST BIT(25)
50#define FLEXCAN_MCR_FRZ_ACK BIT(24)
51#define FLEXCAN_MCR_SUPV BIT(23)
52#define FLEXCAN_MCR_SLF_WAK BIT(22)
53#define FLEXCAN_MCR_WRN_EN BIT(21)
54#define FLEXCAN_MCR_LPM_ACK BIT(20)
55#define FLEXCAN_MCR_WAK_SRC BIT(19)
56#define FLEXCAN_MCR_DOZE BIT(18)
57#define FLEXCAN_MCR_SRX_DIS BIT(17)
58#define FLEXCAN_MCR_BCC BIT(16)
59#define FLEXCAN_MCR_LPRIO_EN BIT(13)
60#define FLEXCAN_MCR_AEN BIT(12)
61#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
62#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
63#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
64#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
65#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
66
67/* FLEXCAN control register (CANCTRL) bits */
68#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
69#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
70#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
71#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
72#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
73#define FLEXCAN_CTRL_ERR_MSK BIT(14)
74#define FLEXCAN_CTRL_CLK_SRC BIT(13)
75#define FLEXCAN_CTRL_LPB BIT(12)
76#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
77#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
78#define FLEXCAN_CTRL_SMP BIT(7)
79#define FLEXCAN_CTRL_BOFF_REC BIT(6)
80#define FLEXCAN_CTRL_TSYN BIT(5)
81#define FLEXCAN_CTRL_LBUF BIT(4)
82#define FLEXCAN_CTRL_LOM BIT(3)
83#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
84#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
85#define FLEXCAN_CTRL_ERR_STATE \
86 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
87 FLEXCAN_CTRL_BOFF_MSK)
88#define FLEXCAN_CTRL_ERR_ALL \
89 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
90
91/* FLEXCAN control register 2 (CTRL2) bits */
92#define FLEXCAN_CTRL2_ECRWRE BIT(29)
93#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
94#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
95#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
96#define FLEXCAN_CTRL2_MRP BIT(18)
97#define FLEXCAN_CTRL2_RRS BIT(17)
98#define FLEXCAN_CTRL2_EACEN BIT(16)
99
100/* FLEXCAN memory error control register (MECR) bits */
101#define FLEXCAN_MECR_ECRWRDIS BIT(31)
102#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
103#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
104#define FLEXCAN_MECR_CEI_MSK BIT(16)
105#define FLEXCAN_MECR_HAERRIE BIT(15)
106#define FLEXCAN_MECR_FAERRIE BIT(14)
107#define FLEXCAN_MECR_EXTERRIE BIT(13)
108#define FLEXCAN_MECR_RERRDIS BIT(9)
109#define FLEXCAN_MECR_ECCDIS BIT(8)
110#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
111
112/* FLEXCAN error and status register (ESR) bits */
113#define FLEXCAN_ESR_TWRN_INT BIT(17)
114#define FLEXCAN_ESR_RWRN_INT BIT(16)
115#define FLEXCAN_ESR_BIT1_ERR BIT(15)
116#define FLEXCAN_ESR_BIT0_ERR BIT(14)
117#define FLEXCAN_ESR_ACK_ERR BIT(13)
118#define FLEXCAN_ESR_CRC_ERR BIT(12)
119#define FLEXCAN_ESR_FRM_ERR BIT(11)
120#define FLEXCAN_ESR_STF_ERR BIT(10)
121#define FLEXCAN_ESR_TX_WRN BIT(9)
122#define FLEXCAN_ESR_RX_WRN BIT(8)
123#define FLEXCAN_ESR_IDLE BIT(7)
124#define FLEXCAN_ESR_TXRX BIT(6)
125#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
126#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
127#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
128#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
129#define FLEXCAN_ESR_BOFF_INT BIT(2)
130#define FLEXCAN_ESR_ERR_INT BIT(1)
131#define FLEXCAN_ESR_WAK_INT BIT(0)
132#define FLEXCAN_ESR_ERR_BUS \
133 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
134 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
135 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
136#define FLEXCAN_ESR_ERR_STATE \
137 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
138#define FLEXCAN_ESR_ERR_ALL \
139 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
140#define FLEXCAN_ESR_ALL_INT \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
142 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
143
144/* FLEXCAN interrupt flag register (IFLAG) bits */
145/* Errata ERR005829 step7: Reserve first valid MB */
146#define FLEXCAN_TX_BUF_RESERVED 8
147#define FLEXCAN_TX_BUF_ID 9
148#define FLEXCAN_IFLAG_BUF(x) BIT(x)
149#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
150#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
151#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
152#define FLEXCAN_IFLAG_DEFAULT \
153 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
154 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
155
156/* FLEXCAN message buffers */
157#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
158#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
159#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
160#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
161#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
162
163#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
164#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
165#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
166#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
167
168#define FLEXCAN_MB_CNT_SRR BIT(22)
169#define FLEXCAN_MB_CNT_IDE BIT(21)
170#define FLEXCAN_MB_CNT_RTR BIT(20)
171#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
172#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
173
174#define FLEXCAN_TIMEOUT_US (50)
175
176/* FLEXCAN hardware feature flags
177 *
178 * Below is some version info we got:
179 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
180 * Filter? connected? detection ception in MB
181 * MX25 FlexCAN2 03.00.00.00 no no no no
182 * MX28 FlexCAN2 03.00.04.00 yes yes no no
183 * MX35 FlexCAN2 03.00.00.00 no no no no
184 * MX53 FlexCAN2 03.00.00.00 yes no no no
185 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
186 * VF610 FlexCAN3 ? no yes yes yes?
187 *
188 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
189 */
190#define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
191#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
192#define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
193
194/* Structure of the message buffer */
195struct flexcan_mb {
196 u32 can_ctrl;
197 u32 can_id;
198 u32 data[2];
199};
200
201/* Structure of the hardware registers */
202struct flexcan_regs {
203 u32 mcr; /* 0x00 */
204 u32 ctrl; /* 0x04 */
205 u32 timer; /* 0x08 */
206 u32 _reserved1; /* 0x0c */
207 u32 rxgmask; /* 0x10 */
208 u32 rx14mask; /* 0x14 */
209 u32 rx15mask; /* 0x18 */
210 u32 ecr; /* 0x1c */
211 u32 esr; /* 0x20 */
212 u32 imask2; /* 0x24 */
213 u32 imask1; /* 0x28 */
214 u32 iflag2; /* 0x2c */
215 u32 iflag1; /* 0x30 */
216 u32 ctrl2; /* 0x34 */
217 u32 esr2; /* 0x38 */
218 u32 imeur; /* 0x3c */
219 u32 lrfr; /* 0x40 */
220 u32 crcr; /* 0x44 */
221 u32 rxfgmask; /* 0x48 */
222 u32 rxfir; /* 0x4c */
223 u32 _reserved3[12]; /* 0x50 */
224 struct flexcan_mb mb[64]; /* 0x80 */
225 /* FIFO-mode:
226 * MB
227 * 0x080...0x08f 0 RX message buffer
228 * 0x090...0x0df 1-5 reserverd
229 * 0x0e0...0x0ff 6-7 8 entry ID table
230 * (mx25, mx28, mx35, mx53)
231 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
232 * size conf'ed via ctrl2::RFFN
233 * (mx6, vf610)
234 */
235 u32 _reserved4[408];
236 u32 mecr; /* 0xae0 */
237 u32 erriar; /* 0xae4 */
238 u32 erridpr; /* 0xae8 */
239 u32 errippr; /* 0xaec */
240 u32 rerrar; /* 0xaf0 */
241 u32 rerrdr; /* 0xaf4 */
242 u32 rerrsynr; /* 0xaf8 */
243 u32 errsr; /* 0xafc */
244};
245
246struct flexcan_devtype_data {
247 u32 quirks; /* quirks needed for different IP cores */
248};
249
250struct flexcan_priv {
251 struct can_priv can;
252 struct napi_struct napi;
253
254 struct flexcan_regs __iomem *regs;
255 u32 reg_esr;
256 u32 reg_ctrl_default;
257
258 struct clk *clk_ipg;
259 struct clk *clk_per;
260 struct flexcan_platform_data *pdata;
261 const struct flexcan_devtype_data *devtype_data;
262 struct regulator *reg_xceiver;
263};
264
265static struct flexcan_devtype_data fsl_p1010_devtype_data = {
266 .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
267};
268
269static struct flexcan_devtype_data fsl_imx28_devtype_data;
270
271static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
272 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
273};
274
275static struct flexcan_devtype_data fsl_vf610_devtype_data = {
276 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
277};
278
279static const struct can_bittiming_const flexcan_bittiming_const = {
280 .name = DRV_NAME,
281 .tseg1_min = 4,
282 .tseg1_max = 16,
283 .tseg2_min = 2,
284 .tseg2_max = 8,
285 .sjw_max = 4,
286 .brp_min = 1,
287 .brp_max = 256,
288 .brp_inc = 1,
289};
290
291/* Abstract off the read/write for arm versus ppc. This
292 * assumes that PPC uses big-endian registers and everything
293 * else uses little-endian registers, independent of CPU
294 * endianness.
295 */
296#if defined(CONFIG_PPC)
297static inline u32 flexcan_read(void __iomem *addr)
298{
299 return in_be32(addr);
300}
301
302static inline void flexcan_write(u32 val, void __iomem *addr)
303{
304 out_be32(addr, val);
305}
306#else
307static inline u32 flexcan_read(void __iomem *addr)
308{
309 return readl(addr);
310}
311
312static inline void flexcan_write(u32 val, void __iomem *addr)
313{
314 writel(val, addr);
315}
316#endif
317
318static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
319{
320 if (!priv->reg_xceiver)
321 return 0;
322
323 return regulator_enable(priv->reg_xceiver);
324}
325
326static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
327{
328 if (!priv->reg_xceiver)
329 return 0;
330
331 return regulator_disable(priv->reg_xceiver);
332}
333
334static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
335 u32 reg_esr)
336{
337 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
338 (reg_esr & FLEXCAN_ESR_ERR_BUS);
339}
340
341static int flexcan_chip_enable(struct flexcan_priv *priv)
342{
343 struct flexcan_regs __iomem *regs = priv->regs;
344 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
345 u32 reg;
346
347 reg = flexcan_read(®s->mcr);
348 reg &= ~FLEXCAN_MCR_MDIS;
349 flexcan_write(reg, ®s->mcr);
350
351 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
352 udelay(10);
353
354 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
355 return -ETIMEDOUT;
356
357 return 0;
358}
359
360static int flexcan_chip_disable(struct flexcan_priv *priv)
361{
362 struct flexcan_regs __iomem *regs = priv->regs;
363 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
364 u32 reg;
365
366 reg = flexcan_read(®s->mcr);
367 reg |= FLEXCAN_MCR_MDIS;
368 flexcan_write(reg, ®s->mcr);
369
370 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
371 udelay(10);
372
373 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
374 return -ETIMEDOUT;
375
376 return 0;
377}
378
379static int flexcan_chip_freeze(struct flexcan_priv *priv)
380{
381 struct flexcan_regs __iomem *regs = priv->regs;
382 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
383 u32 reg;
384
385 reg = flexcan_read(®s->mcr);
386 reg |= FLEXCAN_MCR_HALT;
387 flexcan_write(reg, ®s->mcr);
388
389 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
390 udelay(100);
391
392 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
393 return -ETIMEDOUT;
394
395 return 0;
396}
397
398static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
399{
400 struct flexcan_regs __iomem *regs = priv->regs;
401 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
402 u32 reg;
403
404 reg = flexcan_read(®s->mcr);
405 reg &= ~FLEXCAN_MCR_HALT;
406 flexcan_write(reg, ®s->mcr);
407
408 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
409 udelay(10);
410
411 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
412 return -ETIMEDOUT;
413
414 return 0;
415}
416
417static int flexcan_chip_softreset(struct flexcan_priv *priv)
418{
419 struct flexcan_regs __iomem *regs = priv->regs;
420 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
421
422 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
423 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
424 udelay(10);
425
426 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
427 return -ETIMEDOUT;
428
429 return 0;
430}
431
432static int __flexcan_get_berr_counter(const struct net_device *dev,
433 struct can_berr_counter *bec)
434{
435 const struct flexcan_priv *priv = netdev_priv(dev);
436 struct flexcan_regs __iomem *regs = priv->regs;
437 u32 reg = flexcan_read(®s->ecr);
438
439 bec->txerr = (reg >> 0) & 0xff;
440 bec->rxerr = (reg >> 8) & 0xff;
441
442 return 0;
443}
444
445static int flexcan_get_berr_counter(const struct net_device *dev,
446 struct can_berr_counter *bec)
447{
448 const struct flexcan_priv *priv = netdev_priv(dev);
449 int err;
450
451 err = clk_prepare_enable(priv->clk_ipg);
452 if (err)
453 return err;
454
455 err = clk_prepare_enable(priv->clk_per);
456 if (err)
457 goto out_disable_ipg;
458
459 err = __flexcan_get_berr_counter(dev, bec);
460
461 clk_disable_unprepare(priv->clk_per);
462 out_disable_ipg:
463 clk_disable_unprepare(priv->clk_ipg);
464
465 return err;
466}
467
468static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
469{
470 const struct flexcan_priv *priv = netdev_priv(dev);
471 struct flexcan_regs __iomem *regs = priv->regs;
472 struct can_frame *cf = (struct can_frame *)skb->data;
473 u32 can_id;
474 u32 data;
475 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
476
477 if (can_dropped_invalid_skb(dev, skb))
478 return NETDEV_TX_OK;
479
480 netif_stop_queue(dev);
481
482 if (cf->can_id & CAN_EFF_FLAG) {
483 can_id = cf->can_id & CAN_EFF_MASK;
484 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
485 } else {
486 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
487 }
488
489 if (cf->can_id & CAN_RTR_FLAG)
490 ctrl |= FLEXCAN_MB_CNT_RTR;
491
492 if (cf->can_dlc > 0) {
493 data = be32_to_cpup((__be32 *)&cf->data[0]);
494 flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[0]);
495 }
496 if (cf->can_dlc > 3) {
497 data = be32_to_cpup((__be32 *)&cf->data[4]);
498 flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[1]);
499 }
500
501 can_put_echo_skb(skb, dev, 0);
502
503 flexcan_write(can_id, ®s->mb[FLEXCAN_TX_BUF_ID].can_id);
504 flexcan_write(ctrl, ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
505
506 /* Errata ERR005829 step8:
507 * Write twice INACTIVE(0x8) code to first MB.
508 */
509 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
510 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
511 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
512 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
513
514 return NETDEV_TX_OK;
515}
516
517static void do_bus_err(struct net_device *dev,
518 struct can_frame *cf, u32 reg_esr)
519{
520 struct flexcan_priv *priv = netdev_priv(dev);
521 int rx_errors = 0, tx_errors = 0;
522
523 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
524
525 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
526 netdev_dbg(dev, "BIT1_ERR irq\n");
527 cf->data[2] |= CAN_ERR_PROT_BIT1;
528 tx_errors = 1;
529 }
530 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
531 netdev_dbg(dev, "BIT0_ERR irq\n");
532 cf->data[2] |= CAN_ERR_PROT_BIT0;
533 tx_errors = 1;
534 }
535 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
536 netdev_dbg(dev, "ACK_ERR irq\n");
537 cf->can_id |= CAN_ERR_ACK;
538 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
539 tx_errors = 1;
540 }
541 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
542 netdev_dbg(dev, "CRC_ERR irq\n");
543 cf->data[2] |= CAN_ERR_PROT_BIT;
544 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
545 rx_errors = 1;
546 }
547 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
548 netdev_dbg(dev, "FRM_ERR irq\n");
549 cf->data[2] |= CAN_ERR_PROT_FORM;
550 rx_errors = 1;
551 }
552 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
553 netdev_dbg(dev, "STF_ERR irq\n");
554 cf->data[2] |= CAN_ERR_PROT_STUFF;
555 rx_errors = 1;
556 }
557
558 priv->can.can_stats.bus_error++;
559 if (rx_errors)
560 dev->stats.rx_errors++;
561 if (tx_errors)
562 dev->stats.tx_errors++;
563}
564
565static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
566{
567 struct sk_buff *skb;
568 struct can_frame *cf;
569
570 skb = alloc_can_err_skb(dev, &cf);
571 if (unlikely(!skb))
572 return 0;
573
574 do_bus_err(dev, cf, reg_esr);
575
576 dev->stats.rx_packets++;
577 dev->stats.rx_bytes += cf->can_dlc;
578 netif_receive_skb(skb);
579
580 return 1;
581}
582
583static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
584{
585 struct flexcan_priv *priv = netdev_priv(dev);
586 struct sk_buff *skb;
587 struct can_frame *cf;
588 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
589 int flt;
590 struct can_berr_counter bec;
591
592 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
593 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
594 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
595 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
596 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
597 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
598 new_state = max(tx_state, rx_state);
599 } else {
600 __flexcan_get_berr_counter(dev, &bec);
601 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
602 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
603 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
604 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
605 }
606
607 /* state hasn't changed */
608 if (likely(new_state == priv->can.state))
609 return 0;
610
611 skb = alloc_can_err_skb(dev, &cf);
612 if (unlikely(!skb))
613 return 0;
614
615 can_change_state(dev, cf, tx_state, rx_state);
616
617 if (unlikely(new_state == CAN_STATE_BUS_OFF))
618 can_bus_off(dev);
619
620 dev->stats.rx_packets++;
621 dev->stats.rx_bytes += cf->can_dlc;
622 netif_receive_skb(skb);
623
624 return 1;
625}
626
627static void flexcan_read_fifo(const struct net_device *dev,
628 struct can_frame *cf)
629{
630 const struct flexcan_priv *priv = netdev_priv(dev);
631 struct flexcan_regs __iomem *regs = priv->regs;
632 struct flexcan_mb __iomem *mb = ®s->mb[0];
633 u32 reg_ctrl, reg_id;
634
635 reg_ctrl = flexcan_read(&mb->can_ctrl);
636 reg_id = flexcan_read(&mb->can_id);
637 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
638 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
639 else
640 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
641
642 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
643 cf->can_id |= CAN_RTR_FLAG;
644 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
645
646 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
647 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
648
649 /* mark as read */
650 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
651 flexcan_read(®s->timer);
652}
653
654static int flexcan_read_frame(struct net_device *dev)
655{
656 struct net_device_stats *stats = &dev->stats;
657 struct can_frame *cf;
658 struct sk_buff *skb;
659
660 skb = alloc_can_skb(dev, &cf);
661 if (unlikely(!skb)) {
662 stats->rx_dropped++;
663 return 0;
664 }
665
666 flexcan_read_fifo(dev, cf);
667
668 stats->rx_packets++;
669 stats->rx_bytes += cf->can_dlc;
670 netif_receive_skb(skb);
671
672 can_led_event(dev, CAN_LED_EVENT_RX);
673
674 return 1;
675}
676
677static int flexcan_poll(struct napi_struct *napi, int quota)
678{
679 struct net_device *dev = napi->dev;
680 const struct flexcan_priv *priv = netdev_priv(dev);
681 struct flexcan_regs __iomem *regs = priv->regs;
682 u32 reg_iflag1, reg_esr;
683 int work_done = 0;
684
685 /* The error bits are cleared on read,
686 * use saved value from irq handler.
687 */
688 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
689
690 /* handle state changes */
691 work_done += flexcan_poll_state(dev, reg_esr);
692
693 /* handle RX-FIFO */
694 reg_iflag1 = flexcan_read(®s->iflag1);
695 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
696 work_done < quota) {
697 work_done += flexcan_read_frame(dev);
698 reg_iflag1 = flexcan_read(®s->iflag1);
699 }
700
701 /* report bus errors */
702 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
703 work_done += flexcan_poll_bus_err(dev, reg_esr);
704
705 if (work_done < quota) {
706 napi_complete(napi);
707 /* enable IRQs */
708 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
709 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
710 }
711
712 return work_done;
713}
714
715static irqreturn_t flexcan_irq(int irq, void *dev_id)
716{
717 struct net_device *dev = dev_id;
718 struct net_device_stats *stats = &dev->stats;
719 struct flexcan_priv *priv = netdev_priv(dev);
720 struct flexcan_regs __iomem *regs = priv->regs;
721 u32 reg_iflag1, reg_esr;
722
723 reg_iflag1 = flexcan_read(®s->iflag1);
724 reg_esr = flexcan_read(®s->esr);
725
726 /* ACK all bus error and state change IRQ sources */
727 if (reg_esr & FLEXCAN_ESR_ALL_INT)
728 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
729
730 /* schedule NAPI in case of:
731 * - rx IRQ
732 * - state change IRQ
733 * - bus error IRQ and bus error reporting is activated
734 */
735 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
736 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
737 flexcan_has_and_handle_berr(priv, reg_esr)) {
738 /* The error bits are cleared on read,
739 * save them for later use.
740 */
741 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
742 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
743 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
744 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
745 ®s->ctrl);
746 napi_schedule(&priv->napi);
747 }
748
749 /* FIFO overflow */
750 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
751 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
752 dev->stats.rx_over_errors++;
753 dev->stats.rx_errors++;
754 }
755
756 /* transmission complete interrupt */
757 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
758 stats->tx_bytes += can_get_echo_skb(dev, 0);
759 stats->tx_packets++;
760 can_led_event(dev, CAN_LED_EVENT_TX);
761
762 /* after sending a RTR frame MB is in RX mode */
763 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
764 ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
765 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
766 netif_wake_queue(dev);
767 }
768
769 return IRQ_HANDLED;
770}
771
772static void flexcan_set_bittiming(struct net_device *dev)
773{
774 const struct flexcan_priv *priv = netdev_priv(dev);
775 const struct can_bittiming *bt = &priv->can.bittiming;
776 struct flexcan_regs __iomem *regs = priv->regs;
777 u32 reg;
778
779 reg = flexcan_read(®s->ctrl);
780 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
781 FLEXCAN_CTRL_RJW(0x3) |
782 FLEXCAN_CTRL_PSEG1(0x7) |
783 FLEXCAN_CTRL_PSEG2(0x7) |
784 FLEXCAN_CTRL_PROPSEG(0x7) |
785 FLEXCAN_CTRL_LPB |
786 FLEXCAN_CTRL_SMP |
787 FLEXCAN_CTRL_LOM);
788
789 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
790 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
791 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
792 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
793 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
794
795 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
796 reg |= FLEXCAN_CTRL_LPB;
797 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
798 reg |= FLEXCAN_CTRL_LOM;
799 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
800 reg |= FLEXCAN_CTRL_SMP;
801
802 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
803 flexcan_write(reg, ®s->ctrl);
804
805 /* print chip status */
806 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
807 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
808}
809
810/* flexcan_chip_start
811 *
812 * this functions is entered with clocks enabled
813 *
814 */
815static int flexcan_chip_start(struct net_device *dev)
816{
817 struct flexcan_priv *priv = netdev_priv(dev);
818 struct flexcan_regs __iomem *regs = priv->regs;
819 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
820 int err, i;
821
822 /* enable module */
823 err = flexcan_chip_enable(priv);
824 if (err)
825 return err;
826
827 /* soft reset */
828 err = flexcan_chip_softreset(priv);
829 if (err)
830 goto out_chip_disable;
831
832 flexcan_set_bittiming(dev);
833
834 /* MCR
835 *
836 * enable freeze
837 * enable fifo
838 * halt now
839 * only supervisor access
840 * enable warning int
841 * disable local echo
842 * choose format C
843 * set max mailbox number
844 */
845 reg_mcr = flexcan_read(®s->mcr);
846 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
847 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
848 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
849 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
850 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
851 flexcan_write(reg_mcr, ®s->mcr);
852
853 /* CTRL
854 *
855 * disable timer sync feature
856 *
857 * disable auto busoff recovery
858 * transmit lowest buffer first
859 *
860 * enable tx and rx warning interrupt
861 * enable bus off interrupt
862 * (== FLEXCAN_CTRL_ERR_STATE)
863 */
864 reg_ctrl = flexcan_read(®s->ctrl);
865 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
866 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
867 FLEXCAN_CTRL_ERR_STATE;
868
869 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
870 * on most Flexcan cores, too. Otherwise we don't get
871 * any error warning or passive interrupts.
872 */
873 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
874 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
875 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
876 else
877 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
878
879 /* save for later use */
880 priv->reg_ctrl_default = reg_ctrl;
881 /* leave interrupts disabled for now */
882 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
883 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
884 flexcan_write(reg_ctrl, ®s->ctrl);
885
886 /* clear and invalidate all mailboxes first */
887 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
888 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
889 ®s->mb[i].can_ctrl);
890 }
891
892 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
893 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
894 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
895
896 /* mark TX mailbox as INACTIVE */
897 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
898 ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
899
900 /* acceptance mask/acceptance code (accept everything) */
901 flexcan_write(0x0, ®s->rxgmask);
902 flexcan_write(0x0, ®s->rx14mask);
903 flexcan_write(0x0, ®s->rx15mask);
904
905 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
906 flexcan_write(0x0, ®s->rxfgmask);
907
908 /* On Vybrid, disable memory error detection interrupts
909 * and freeze mode.
910 * This also works around errata e5295 which generates
911 * false positive memory errors and put the device in
912 * freeze mode.
913 */
914 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
915 /* Follow the protocol as described in "Detection
916 * and Correction of Memory Errors" to write to
917 * MECR register
918 */
919 reg_ctrl2 = flexcan_read(®s->ctrl2);
920 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
921 flexcan_write(reg_ctrl2, ®s->ctrl2);
922
923 reg_mecr = flexcan_read(®s->mecr);
924 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
925 flexcan_write(reg_mecr, ®s->mecr);
926 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
927 FLEXCAN_MECR_FANCEI_MSK);
928 flexcan_write(reg_mecr, ®s->mecr);
929 }
930
931 err = flexcan_transceiver_enable(priv);
932 if (err)
933 goto out_chip_disable;
934
935 /* synchronize with the can bus */
936 err = flexcan_chip_unfreeze(priv);
937 if (err)
938 goto out_transceiver_disable;
939
940 priv->can.state = CAN_STATE_ERROR_ACTIVE;
941
942 /* enable interrupts atomically */
943 disable_irq(dev->irq);
944 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
945 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
946 enable_irq(dev->irq);
947
948 /* print chip status */
949 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
950 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
951
952 return 0;
953
954 out_transceiver_disable:
955 flexcan_transceiver_disable(priv);
956 out_chip_disable:
957 flexcan_chip_disable(priv);
958 return err;
959}
960
961/* flexcan_chip_stop
962 *
963 * this functions is entered with clocks enabled
964 */
965static void flexcan_chip_stop(struct net_device *dev)
966{
967 struct flexcan_priv *priv = netdev_priv(dev);
968 struct flexcan_regs __iomem *regs = priv->regs;
969
970 /* freeze + disable module */
971 flexcan_chip_freeze(priv);
972 flexcan_chip_disable(priv);
973
974 /* Disable all interrupts */
975 flexcan_write(0, ®s->imask1);
976 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
977 ®s->ctrl);
978
979 flexcan_transceiver_disable(priv);
980 priv->can.state = CAN_STATE_STOPPED;
981}
982
983static int flexcan_open(struct net_device *dev)
984{
985 struct flexcan_priv *priv = netdev_priv(dev);
986 int err;
987
988 err = clk_prepare_enable(priv->clk_ipg);
989 if (err)
990 return err;
991
992 err = clk_prepare_enable(priv->clk_per);
993 if (err)
994 goto out_disable_ipg;
995
996 err = open_candev(dev);
997 if (err)
998 goto out_disable_per;
999
1000 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1001 if (err)
1002 goto out_close;
1003
1004 /* start chip and queuing */
1005 err = flexcan_chip_start(dev);
1006 if (err)
1007 goto out_free_irq;
1008
1009 can_led_event(dev, CAN_LED_EVENT_OPEN);
1010
1011 napi_enable(&priv->napi);
1012 netif_start_queue(dev);
1013
1014 return 0;
1015
1016 out_free_irq:
1017 free_irq(dev->irq, dev);
1018 out_close:
1019 close_candev(dev);
1020 out_disable_per:
1021 clk_disable_unprepare(priv->clk_per);
1022 out_disable_ipg:
1023 clk_disable_unprepare(priv->clk_ipg);
1024
1025 return err;
1026}
1027
1028static int flexcan_close(struct net_device *dev)
1029{
1030 struct flexcan_priv *priv = netdev_priv(dev);
1031
1032 netif_stop_queue(dev);
1033 napi_disable(&priv->napi);
1034 flexcan_chip_stop(dev);
1035
1036 free_irq(dev->irq, dev);
1037 clk_disable_unprepare(priv->clk_per);
1038 clk_disable_unprepare(priv->clk_ipg);
1039
1040 close_candev(dev);
1041
1042 can_led_event(dev, CAN_LED_EVENT_STOP);
1043
1044 return 0;
1045}
1046
1047static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1048{
1049 int err;
1050
1051 switch (mode) {
1052 case CAN_MODE_START:
1053 err = flexcan_chip_start(dev);
1054 if (err)
1055 return err;
1056
1057 netif_wake_queue(dev);
1058 break;
1059
1060 default:
1061 return -EOPNOTSUPP;
1062 }
1063
1064 return 0;
1065}
1066
1067static const struct net_device_ops flexcan_netdev_ops = {
1068 .ndo_open = flexcan_open,
1069 .ndo_stop = flexcan_close,
1070 .ndo_start_xmit = flexcan_start_xmit,
1071 .ndo_change_mtu = can_change_mtu,
1072};
1073
1074static int register_flexcandev(struct net_device *dev)
1075{
1076 struct flexcan_priv *priv = netdev_priv(dev);
1077 struct flexcan_regs __iomem *regs = priv->regs;
1078 u32 reg, err;
1079
1080 err = clk_prepare_enable(priv->clk_ipg);
1081 if (err)
1082 return err;
1083
1084 err = clk_prepare_enable(priv->clk_per);
1085 if (err)
1086 goto out_disable_ipg;
1087
1088 /* select "bus clock", chip must be disabled */
1089 err = flexcan_chip_disable(priv);
1090 if (err)
1091 goto out_disable_per;
1092 reg = flexcan_read(®s->ctrl);
1093 reg |= FLEXCAN_CTRL_CLK_SRC;
1094 flexcan_write(reg, ®s->ctrl);
1095
1096 err = flexcan_chip_enable(priv);
1097 if (err)
1098 goto out_chip_disable;
1099
1100 /* set freeze, halt and activate FIFO, restrict register access */
1101 reg = flexcan_read(®s->mcr);
1102 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1103 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1104 flexcan_write(reg, ®s->mcr);
1105
1106 /* Currently we only support newer versions of this core
1107 * featuring a RX FIFO. Older cores found on some Coldfire
1108 * derivates are not yet supported.
1109 */
1110 reg = flexcan_read(®s->mcr);
1111 if (!(reg & FLEXCAN_MCR_FEN)) {
1112 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1113 err = -ENODEV;
1114 goto out_chip_disable;
1115 }
1116
1117 err = register_candev(dev);
1118
1119 /* disable core and turn off clocks */
1120 out_chip_disable:
1121 flexcan_chip_disable(priv);
1122 out_disable_per:
1123 clk_disable_unprepare(priv->clk_per);
1124 out_disable_ipg:
1125 clk_disable_unprepare(priv->clk_ipg);
1126
1127 return err;
1128}
1129
1130static void unregister_flexcandev(struct net_device *dev)
1131{
1132 unregister_candev(dev);
1133}
1134
1135static const struct of_device_id flexcan_of_match[] = {
1136 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1137 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1138 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1139 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1140 { /* sentinel */ },
1141};
1142MODULE_DEVICE_TABLE(of, flexcan_of_match);
1143
1144static const struct platform_device_id flexcan_id_table[] = {
1145 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1146 { /* sentinel */ },
1147};
1148MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1149
1150static int flexcan_probe(struct platform_device *pdev)
1151{
1152 const struct of_device_id *of_id;
1153 const struct flexcan_devtype_data *devtype_data;
1154 struct net_device *dev;
1155 struct flexcan_priv *priv;
1156 struct regulator *reg_xceiver;
1157 struct resource *mem;
1158 struct clk *clk_ipg = NULL, *clk_per = NULL;
1159 struct flexcan_regs __iomem *regs;
1160 int err, irq;
1161 u32 clock_freq = 0;
1162
1163 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1164 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1165 return -EPROBE_DEFER;
1166 else if (IS_ERR(reg_xceiver))
1167 reg_xceiver = NULL;
1168
1169 if (pdev->dev.of_node)
1170 of_property_read_u32(pdev->dev.of_node,
1171 "clock-frequency", &clock_freq);
1172
1173 if (!clock_freq) {
1174 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1175 if (IS_ERR(clk_ipg)) {
1176 dev_err(&pdev->dev, "no ipg clock defined\n");
1177 return PTR_ERR(clk_ipg);
1178 }
1179
1180 clk_per = devm_clk_get(&pdev->dev, "per");
1181 if (IS_ERR(clk_per)) {
1182 dev_err(&pdev->dev, "no per clock defined\n");
1183 return PTR_ERR(clk_per);
1184 }
1185 clock_freq = clk_get_rate(clk_per);
1186 }
1187
1188 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189 irq = platform_get_irq(pdev, 0);
1190 if (irq <= 0)
1191 return -ENODEV;
1192
1193 regs = devm_ioremap_resource(&pdev->dev, mem);
1194 if (IS_ERR(regs))
1195 return PTR_ERR(regs);
1196
1197 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1198 if (of_id) {
1199 devtype_data = of_id->data;
1200 } else if (platform_get_device_id(pdev)->driver_data) {
1201 devtype_data = (struct flexcan_devtype_data *)
1202 platform_get_device_id(pdev)->driver_data;
1203 } else {
1204 return -ENODEV;
1205 }
1206
1207 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1208 if (!dev)
1209 return -ENOMEM;
1210
1211 dev->netdev_ops = &flexcan_netdev_ops;
1212 dev->irq = irq;
1213 dev->flags |= IFF_ECHO;
1214
1215 priv = netdev_priv(dev);
1216 priv->can.clock.freq = clock_freq;
1217 priv->can.bittiming_const = &flexcan_bittiming_const;
1218 priv->can.do_set_mode = flexcan_set_mode;
1219 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1220 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1221 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1222 CAN_CTRLMODE_BERR_REPORTING;
1223 priv->regs = regs;
1224 priv->clk_ipg = clk_ipg;
1225 priv->clk_per = clk_per;
1226 priv->pdata = dev_get_platdata(&pdev->dev);
1227 priv->devtype_data = devtype_data;
1228 priv->reg_xceiver = reg_xceiver;
1229
1230 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1231
1232 platform_set_drvdata(pdev, dev);
1233 SET_NETDEV_DEV(dev, &pdev->dev);
1234
1235 err = register_flexcandev(dev);
1236 if (err) {
1237 dev_err(&pdev->dev, "registering netdev failed\n");
1238 goto failed_register;
1239 }
1240
1241 devm_can_led_init(dev);
1242
1243 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1244 priv->regs, dev->irq);
1245
1246 return 0;
1247
1248 failed_register:
1249 free_candev(dev);
1250 return err;
1251}
1252
1253static int flexcan_remove(struct platform_device *pdev)
1254{
1255 struct net_device *dev = platform_get_drvdata(pdev);
1256 struct flexcan_priv *priv = netdev_priv(dev);
1257
1258 unregister_flexcandev(dev);
1259 netif_napi_del(&priv->napi);
1260 free_candev(dev);
1261
1262 return 0;
1263}
1264
1265static int __maybe_unused flexcan_suspend(struct device *device)
1266{
1267 struct net_device *dev = dev_get_drvdata(device);
1268 struct flexcan_priv *priv = netdev_priv(dev);
1269 int err;
1270
1271 err = flexcan_chip_disable(priv);
1272 if (err)
1273 return err;
1274
1275 if (netif_running(dev)) {
1276 netif_stop_queue(dev);
1277 netif_device_detach(dev);
1278 }
1279 priv->can.state = CAN_STATE_SLEEPING;
1280
1281 return 0;
1282}
1283
1284static int __maybe_unused flexcan_resume(struct device *device)
1285{
1286 struct net_device *dev = dev_get_drvdata(device);
1287 struct flexcan_priv *priv = netdev_priv(dev);
1288
1289 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1290 if (netif_running(dev)) {
1291 netif_device_attach(dev);
1292 netif_start_queue(dev);
1293 }
1294 return flexcan_chip_enable(priv);
1295}
1296
1297static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1298
1299static struct platform_driver flexcan_driver = {
1300 .driver = {
1301 .name = DRV_NAME,
1302 .pm = &flexcan_pm_ops,
1303 .of_match_table = flexcan_of_match,
1304 },
1305 .probe = flexcan_probe,
1306 .remove = flexcan_remove,
1307 .id_table = flexcan_id_table,
1308};
1309
1310module_platform_driver(flexcan_driver);
1311
1312MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1313 "Marc Kleine-Budde <kernel@pengutronix.de>");
1314MODULE_LICENSE("GPL v2");
1315MODULE_DESCRIPTION("CAN port driver for flexcan based chip");