Loading...
Note: File does not exist in v6.8.
1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
7 * Copyright (c) 2014 David Jander, Protonic Holland
8 *
9 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
10 *
11 * LICENCE:
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23#include <linux/netdevice.h>
24#include <linux/can.h>
25#include <linux/can/dev.h>
26#include <linux/can/error.h>
27#include <linux/can/led.h>
28#include <linux/can/rx-offload.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/module.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/platform_device.h>
37#include <linux/regulator/consumer.h>
38
39#define DRV_NAME "flexcan"
40
41/* 8 for RX fifo and 2 error handling */
42#define FLEXCAN_NAPI_WEIGHT (8 + 2)
43
44/* FLEXCAN module configuration register (CANMCR) bits */
45#define FLEXCAN_MCR_MDIS BIT(31)
46#define FLEXCAN_MCR_FRZ BIT(30)
47#define FLEXCAN_MCR_FEN BIT(29)
48#define FLEXCAN_MCR_HALT BIT(28)
49#define FLEXCAN_MCR_NOT_RDY BIT(27)
50#define FLEXCAN_MCR_WAK_MSK BIT(26)
51#define FLEXCAN_MCR_SOFTRST BIT(25)
52#define FLEXCAN_MCR_FRZ_ACK BIT(24)
53#define FLEXCAN_MCR_SUPV BIT(23)
54#define FLEXCAN_MCR_SLF_WAK BIT(22)
55#define FLEXCAN_MCR_WRN_EN BIT(21)
56#define FLEXCAN_MCR_LPM_ACK BIT(20)
57#define FLEXCAN_MCR_WAK_SRC BIT(19)
58#define FLEXCAN_MCR_DOZE BIT(18)
59#define FLEXCAN_MCR_SRX_DIS BIT(17)
60#define FLEXCAN_MCR_IRMQ BIT(16)
61#define FLEXCAN_MCR_LPRIO_EN BIT(13)
62#define FLEXCAN_MCR_AEN BIT(12)
63/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
64#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
65#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
66#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
67#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
68#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69
70/* FLEXCAN control register (CANCTRL) bits */
71#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76#define FLEXCAN_CTRL_ERR_MSK BIT(14)
77#define FLEXCAN_CTRL_CLK_SRC BIT(13)
78#define FLEXCAN_CTRL_LPB BIT(12)
79#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81#define FLEXCAN_CTRL_SMP BIT(7)
82#define FLEXCAN_CTRL_BOFF_REC BIT(6)
83#define FLEXCAN_CTRL_TSYN BIT(5)
84#define FLEXCAN_CTRL_LBUF BIT(4)
85#define FLEXCAN_CTRL_LOM BIT(3)
86#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88#define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91#define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
93
94/* FLEXCAN control register 2 (CTRL2) bits */
95#define FLEXCAN_CTRL2_ECRWRE BIT(29)
96#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
97#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
98#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
99#define FLEXCAN_CTRL2_MRP BIT(18)
100#define FLEXCAN_CTRL2_RRS BIT(17)
101#define FLEXCAN_CTRL2_EACEN BIT(16)
102
103/* FLEXCAN memory error control register (MECR) bits */
104#define FLEXCAN_MECR_ECRWRDIS BIT(31)
105#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107#define FLEXCAN_MECR_CEI_MSK BIT(16)
108#define FLEXCAN_MECR_HAERRIE BIT(15)
109#define FLEXCAN_MECR_FAERRIE BIT(14)
110#define FLEXCAN_MECR_EXTERRIE BIT(13)
111#define FLEXCAN_MECR_RERRDIS BIT(9)
112#define FLEXCAN_MECR_ECCDIS BIT(8)
113#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
114
115/* FLEXCAN error and status register (ESR) bits */
116#define FLEXCAN_ESR_TWRN_INT BIT(17)
117#define FLEXCAN_ESR_RWRN_INT BIT(16)
118#define FLEXCAN_ESR_BIT1_ERR BIT(15)
119#define FLEXCAN_ESR_BIT0_ERR BIT(14)
120#define FLEXCAN_ESR_ACK_ERR BIT(13)
121#define FLEXCAN_ESR_CRC_ERR BIT(12)
122#define FLEXCAN_ESR_FRM_ERR BIT(11)
123#define FLEXCAN_ESR_STF_ERR BIT(10)
124#define FLEXCAN_ESR_TX_WRN BIT(9)
125#define FLEXCAN_ESR_RX_WRN BIT(8)
126#define FLEXCAN_ESR_IDLE BIT(7)
127#define FLEXCAN_ESR_TXRX BIT(6)
128#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132#define FLEXCAN_ESR_BOFF_INT BIT(2)
133#define FLEXCAN_ESR_ERR_INT BIT(1)
134#define FLEXCAN_ESR_WAK_INT BIT(0)
135#define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139#define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141#define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143#define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
146
147/* FLEXCAN interrupt flag register (IFLAG) bits */
148/* Errata ERR005829 step7: Reserve first valid MB */
149#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
150#define FLEXCAN_TX_MB_OFF_FIFO 9
151#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
152#define FLEXCAN_TX_MB_OFF_TIMESTAMP 1
153#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
154#define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST 63
155#define FLEXCAN_IFLAG_MB(x) BIT(x)
156#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
157#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
158#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
159
160/* FLEXCAN message buffers */
161#define FLEXCAN_MB_CODE_MASK (0xf << 24)
162#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
163#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
164#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
165#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
166#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
167#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
168
169#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
170#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
171#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
172#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
173
174#define FLEXCAN_MB_CNT_SRR BIT(22)
175#define FLEXCAN_MB_CNT_IDE BIT(21)
176#define FLEXCAN_MB_CNT_RTR BIT(20)
177#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
178#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
179
180#define FLEXCAN_TIMEOUT_US (50)
181
182/* FLEXCAN hardware feature flags
183 *
184 * Below is some version info we got:
185 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
186 * Filter? connected? Passive detection ception in MB
187 * MX25 FlexCAN2 03.00.00.00 no no no no no
188 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
189 * MX35 FlexCAN2 03.00.00.00 no no no no no
190 * MX53 FlexCAN2 03.00.00.00 yes no no no no
191 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
192 * VF610 FlexCAN3 ? no yes no yes yes?
193 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
194 *
195 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
196 */
197#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
198#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
199#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
200#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
201#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
202#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
203#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
204
205/* Structure of the message buffer */
206struct flexcan_mb {
207 u32 can_ctrl;
208 u32 can_id;
209 u32 data[2];
210};
211
212/* Structure of the hardware registers */
213struct flexcan_regs {
214 u32 mcr; /* 0x00 */
215 u32 ctrl; /* 0x04 */
216 u32 timer; /* 0x08 */
217 u32 _reserved1; /* 0x0c */
218 u32 rxgmask; /* 0x10 */
219 u32 rx14mask; /* 0x14 */
220 u32 rx15mask; /* 0x18 */
221 u32 ecr; /* 0x1c */
222 u32 esr; /* 0x20 */
223 u32 imask2; /* 0x24 */
224 u32 imask1; /* 0x28 */
225 u32 iflag2; /* 0x2c */
226 u32 iflag1; /* 0x30 */
227 union { /* 0x34 */
228 u32 gfwr_mx28; /* MX28, MX53 */
229 u32 ctrl2; /* MX6, VF610 */
230 };
231 u32 esr2; /* 0x38 */
232 u32 imeur; /* 0x3c */
233 u32 lrfr; /* 0x40 */
234 u32 crcr; /* 0x44 */
235 u32 rxfgmask; /* 0x48 */
236 u32 rxfir; /* 0x4c */
237 u32 _reserved3[12]; /* 0x50 */
238 struct flexcan_mb mb[64]; /* 0x80 */
239 /* FIFO-mode:
240 * MB
241 * 0x080...0x08f 0 RX message buffer
242 * 0x090...0x0df 1-5 reserverd
243 * 0x0e0...0x0ff 6-7 8 entry ID table
244 * (mx25, mx28, mx35, mx53)
245 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
246 * size conf'ed via ctrl2::RFFN
247 * (mx6, vf610)
248 */
249 u32 _reserved4[256]; /* 0x480 */
250 u32 rximr[64]; /* 0x880 */
251 u32 _reserved5[24]; /* 0x980 */
252 u32 gfwr_mx6; /* 0x9e0 - MX6 */
253 u32 _reserved6[63]; /* 0x9e4 */
254 u32 mecr; /* 0xae0 */
255 u32 erriar; /* 0xae4 */
256 u32 erridpr; /* 0xae8 */
257 u32 errippr; /* 0xaec */
258 u32 rerrar; /* 0xaf0 */
259 u32 rerrdr; /* 0xaf4 */
260 u32 rerrsynr; /* 0xaf8 */
261 u32 errsr; /* 0xafc */
262};
263
264struct flexcan_devtype_data {
265 u32 quirks; /* quirks needed for different IP cores */
266};
267
268struct flexcan_priv {
269 struct can_priv can;
270 struct can_rx_offload offload;
271
272 struct flexcan_regs __iomem *regs;
273 struct flexcan_mb __iomem *tx_mb;
274 struct flexcan_mb __iomem *tx_mb_reserved;
275 u8 tx_mb_idx;
276 u32 reg_ctrl_default;
277 u32 reg_imask1_default;
278 u32 reg_imask2_default;
279
280 struct clk *clk_ipg;
281 struct clk *clk_per;
282 const struct flexcan_devtype_data *devtype_data;
283 struct regulator *reg_xceiver;
284
285 /* Read and Write APIs */
286 u32 (*read)(void __iomem *addr);
287 void (*write)(u32 val, void __iomem *addr);
288};
289
290static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
291 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
292 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
293 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
294};
295
296static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
297 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
298 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
299};
300
301static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
302 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
303};
304
305static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
306 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
307 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
308};
309
310static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
311 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
312 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
313 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
314};
315
316static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
317 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
318 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
319 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
320};
321
322static const struct can_bittiming_const flexcan_bittiming_const = {
323 .name = DRV_NAME,
324 .tseg1_min = 4,
325 .tseg1_max = 16,
326 .tseg2_min = 2,
327 .tseg2_max = 8,
328 .sjw_max = 4,
329 .brp_min = 1,
330 .brp_max = 256,
331 .brp_inc = 1,
332};
333
334/* FlexCAN module is essentially modelled as a little-endian IP in most
335 * SoCs, i.e the registers as well as the message buffer areas are
336 * implemented in a little-endian fashion.
337 *
338 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
339 * module in a big-endian fashion (i.e the registers as well as the
340 * message buffer areas are implemented in a big-endian way).
341 *
342 * In addition, the FlexCAN module can be found on SoCs having ARM or
343 * PPC cores. So, we need to abstract off the register read/write
344 * functions, ensuring that these cater to all the combinations of module
345 * endianness and underlying CPU endianness.
346 */
347static inline u32 flexcan_read_be(void __iomem *addr)
348{
349 return ioread32be(addr);
350}
351
352static inline void flexcan_write_be(u32 val, void __iomem *addr)
353{
354 iowrite32be(val, addr);
355}
356
357static inline u32 flexcan_read_le(void __iomem *addr)
358{
359 return ioread32(addr);
360}
361
362static inline void flexcan_write_le(u32 val, void __iomem *addr)
363{
364 iowrite32(val, addr);
365}
366
367static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
368{
369 struct flexcan_regs __iomem *regs = priv->regs;
370 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
371
372 priv->write(reg_ctrl, ®s->ctrl);
373}
374
375static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
376{
377 struct flexcan_regs __iomem *regs = priv->regs;
378 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
379
380 priv->write(reg_ctrl, ®s->ctrl);
381}
382
383static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
384{
385 if (!priv->reg_xceiver)
386 return 0;
387
388 return regulator_enable(priv->reg_xceiver);
389}
390
391static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
392{
393 if (!priv->reg_xceiver)
394 return 0;
395
396 return regulator_disable(priv->reg_xceiver);
397}
398
399static int flexcan_chip_enable(struct flexcan_priv *priv)
400{
401 struct flexcan_regs __iomem *regs = priv->regs;
402 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
403 u32 reg;
404
405 reg = priv->read(®s->mcr);
406 reg &= ~FLEXCAN_MCR_MDIS;
407 priv->write(reg, ®s->mcr);
408
409 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
410 udelay(10);
411
412 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
413 return -ETIMEDOUT;
414
415 return 0;
416}
417
418static int flexcan_chip_disable(struct flexcan_priv *priv)
419{
420 struct flexcan_regs __iomem *regs = priv->regs;
421 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
422 u32 reg;
423
424 reg = priv->read(®s->mcr);
425 reg |= FLEXCAN_MCR_MDIS;
426 priv->write(reg, ®s->mcr);
427
428 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
429 udelay(10);
430
431 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
432 return -ETIMEDOUT;
433
434 return 0;
435}
436
437static int flexcan_chip_freeze(struct flexcan_priv *priv)
438{
439 struct flexcan_regs __iomem *regs = priv->regs;
440 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
441 u32 reg;
442
443 reg = priv->read(®s->mcr);
444 reg |= FLEXCAN_MCR_HALT;
445 priv->write(reg, ®s->mcr);
446
447 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
448 udelay(100);
449
450 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
451 return -ETIMEDOUT;
452
453 return 0;
454}
455
456static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
457{
458 struct flexcan_regs __iomem *regs = priv->regs;
459 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
460 u32 reg;
461
462 reg = priv->read(®s->mcr);
463 reg &= ~FLEXCAN_MCR_HALT;
464 priv->write(reg, ®s->mcr);
465
466 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
467 udelay(10);
468
469 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
470 return -ETIMEDOUT;
471
472 return 0;
473}
474
475static int flexcan_chip_softreset(struct flexcan_priv *priv)
476{
477 struct flexcan_regs __iomem *regs = priv->regs;
478 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
479
480 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
481 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
482 udelay(10);
483
484 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
485 return -ETIMEDOUT;
486
487 return 0;
488}
489
490static int __flexcan_get_berr_counter(const struct net_device *dev,
491 struct can_berr_counter *bec)
492{
493 const struct flexcan_priv *priv = netdev_priv(dev);
494 struct flexcan_regs __iomem *regs = priv->regs;
495 u32 reg = priv->read(®s->ecr);
496
497 bec->txerr = (reg >> 0) & 0xff;
498 bec->rxerr = (reg >> 8) & 0xff;
499
500 return 0;
501}
502
503static int flexcan_get_berr_counter(const struct net_device *dev,
504 struct can_berr_counter *bec)
505{
506 const struct flexcan_priv *priv = netdev_priv(dev);
507 int err;
508
509 err = clk_prepare_enable(priv->clk_ipg);
510 if (err)
511 return err;
512
513 err = clk_prepare_enable(priv->clk_per);
514 if (err)
515 goto out_disable_ipg;
516
517 err = __flexcan_get_berr_counter(dev, bec);
518
519 clk_disable_unprepare(priv->clk_per);
520 out_disable_ipg:
521 clk_disable_unprepare(priv->clk_ipg);
522
523 return err;
524}
525
526static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
527{
528 const struct flexcan_priv *priv = netdev_priv(dev);
529 struct can_frame *cf = (struct can_frame *)skb->data;
530 u32 can_id;
531 u32 data;
532 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
533
534 if (can_dropped_invalid_skb(dev, skb))
535 return NETDEV_TX_OK;
536
537 netif_stop_queue(dev);
538
539 if (cf->can_id & CAN_EFF_FLAG) {
540 can_id = cf->can_id & CAN_EFF_MASK;
541 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
542 } else {
543 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
544 }
545
546 if (cf->can_id & CAN_RTR_FLAG)
547 ctrl |= FLEXCAN_MB_CNT_RTR;
548
549 if (cf->can_dlc > 0) {
550 data = be32_to_cpup((__be32 *)&cf->data[0]);
551 priv->write(data, &priv->tx_mb->data[0]);
552 }
553 if (cf->can_dlc > 4) {
554 data = be32_to_cpup((__be32 *)&cf->data[4]);
555 priv->write(data, &priv->tx_mb->data[1]);
556 }
557
558 can_put_echo_skb(skb, dev, 0);
559
560 priv->write(can_id, &priv->tx_mb->can_id);
561 priv->write(ctrl, &priv->tx_mb->can_ctrl);
562
563 /* Errata ERR005829 step8:
564 * Write twice INACTIVE(0x8) code to first MB.
565 */
566 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
567 &priv->tx_mb_reserved->can_ctrl);
568 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
569 &priv->tx_mb_reserved->can_ctrl);
570
571 return NETDEV_TX_OK;
572}
573
574static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
575{
576 struct flexcan_priv *priv = netdev_priv(dev);
577 struct sk_buff *skb;
578 struct can_frame *cf;
579 bool rx_errors = false, tx_errors = false;
580
581 skb = alloc_can_err_skb(dev, &cf);
582 if (unlikely(!skb))
583 return;
584
585 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
586
587 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
588 netdev_dbg(dev, "BIT1_ERR irq\n");
589 cf->data[2] |= CAN_ERR_PROT_BIT1;
590 tx_errors = true;
591 }
592 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
593 netdev_dbg(dev, "BIT0_ERR irq\n");
594 cf->data[2] |= CAN_ERR_PROT_BIT0;
595 tx_errors = true;
596 }
597 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
598 netdev_dbg(dev, "ACK_ERR irq\n");
599 cf->can_id |= CAN_ERR_ACK;
600 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
601 tx_errors = true;
602 }
603 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
604 netdev_dbg(dev, "CRC_ERR irq\n");
605 cf->data[2] |= CAN_ERR_PROT_BIT;
606 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
607 rx_errors = true;
608 }
609 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
610 netdev_dbg(dev, "FRM_ERR irq\n");
611 cf->data[2] |= CAN_ERR_PROT_FORM;
612 rx_errors = true;
613 }
614 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
615 netdev_dbg(dev, "STF_ERR irq\n");
616 cf->data[2] |= CAN_ERR_PROT_STUFF;
617 rx_errors = true;
618 }
619
620 priv->can.can_stats.bus_error++;
621 if (rx_errors)
622 dev->stats.rx_errors++;
623 if (tx_errors)
624 dev->stats.tx_errors++;
625
626 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
627}
628
629static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
630{
631 struct flexcan_priv *priv = netdev_priv(dev);
632 struct sk_buff *skb;
633 struct can_frame *cf;
634 enum can_state new_state, rx_state, tx_state;
635 int flt;
636 struct can_berr_counter bec;
637
638 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
639 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
640 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
641 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
642 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
643 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
644 new_state = max(tx_state, rx_state);
645 } else {
646 __flexcan_get_berr_counter(dev, &bec);
647 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
648 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
649 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
650 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
651 }
652
653 /* state hasn't changed */
654 if (likely(new_state == priv->can.state))
655 return;
656
657 skb = alloc_can_err_skb(dev, &cf);
658 if (unlikely(!skb))
659 return;
660
661 can_change_state(dev, cf, tx_state, rx_state);
662
663 if (unlikely(new_state == CAN_STATE_BUS_OFF))
664 can_bus_off(dev);
665
666 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
667}
668
669static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
670{
671 return container_of(offload, struct flexcan_priv, offload);
672}
673
674static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
675 struct can_frame *cf,
676 u32 *timestamp, unsigned int n)
677{
678 struct flexcan_priv *priv = rx_offload_to_priv(offload);
679 struct flexcan_regs __iomem *regs = priv->regs;
680 struct flexcan_mb __iomem *mb = ®s->mb[n];
681 u32 reg_ctrl, reg_id, reg_iflag1;
682
683 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
684 u32 code;
685
686 do {
687 reg_ctrl = priv->read(&mb->can_ctrl);
688 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
689
690 /* is this MB empty? */
691 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
692 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
693 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
694 return 0;
695
696 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
697 /* This MB was overrun, we lost data */
698 offload->dev->stats.rx_over_errors++;
699 offload->dev->stats.rx_errors++;
700 }
701 } else {
702 reg_iflag1 = priv->read(®s->iflag1);
703 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
704 return 0;
705
706 reg_ctrl = priv->read(&mb->can_ctrl);
707 }
708
709 /* increase timstamp to full 32 bit */
710 *timestamp = reg_ctrl << 16;
711
712 reg_id = priv->read(&mb->can_id);
713 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
714 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
715 else
716 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
717
718 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
719 cf->can_id |= CAN_RTR_FLAG;
720 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
721
722 *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
723 *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
724
725 /* mark as read */
726 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
727 /* Clear IRQ */
728 if (n < 32)
729 priv->write(BIT(n), ®s->iflag1);
730 else
731 priv->write(BIT(n - 32), ®s->iflag2);
732 } else {
733 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
734 priv->read(®s->timer);
735 }
736
737 return 1;
738}
739
740
741static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
742{
743 struct flexcan_regs __iomem *regs = priv->regs;
744 u32 iflag1, iflag2;
745
746 iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default;
747 iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default &
748 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
749
750 return (u64)iflag2 << 32 | iflag1;
751}
752
753static irqreturn_t flexcan_irq(int irq, void *dev_id)
754{
755 struct net_device *dev = dev_id;
756 struct net_device_stats *stats = &dev->stats;
757 struct flexcan_priv *priv = netdev_priv(dev);
758 struct flexcan_regs __iomem *regs = priv->regs;
759 irqreturn_t handled = IRQ_NONE;
760 u32 reg_iflag1, reg_esr;
761 enum can_state last_state = priv->can.state;
762
763 reg_iflag1 = priv->read(®s->iflag1);
764
765 /* reception interrupt */
766 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
767 u64 reg_iflag;
768 int ret;
769
770 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
771 handled = IRQ_HANDLED;
772 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
773 reg_iflag);
774 if (!ret)
775 break;
776 }
777 } else {
778 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
779 handled = IRQ_HANDLED;
780 can_rx_offload_irq_offload_fifo(&priv->offload);
781 }
782
783 /* FIFO overflow interrupt */
784 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
785 handled = IRQ_HANDLED;
786 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
787 ®s->iflag1);
788 dev->stats.rx_over_errors++;
789 dev->stats.rx_errors++;
790 }
791 }
792
793 /* transmission complete interrupt */
794 if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
795 handled = IRQ_HANDLED;
796 stats->tx_bytes += can_get_echo_skb(dev, 0);
797 stats->tx_packets++;
798 can_led_event(dev, CAN_LED_EVENT_TX);
799
800 /* after sending a RTR frame MB is in RX mode */
801 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
802 &priv->tx_mb->can_ctrl);
803 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
804 netif_wake_queue(dev);
805 }
806
807 reg_esr = priv->read(®s->esr);
808
809 /* ACK all bus error and state change IRQ sources */
810 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
811 handled = IRQ_HANDLED;
812 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
813 }
814
815 /* state change interrupt or broken error state quirk fix is enabled */
816 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
817 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
818 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
819 flexcan_irq_state(dev, reg_esr);
820
821 /* bus error IRQ - handle if bus error reporting is activated */
822 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
823 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
824 flexcan_irq_bus_err(dev, reg_esr);
825
826 /* availability of error interrupt among state transitions in case
827 * bus error reporting is de-activated and
828 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
829 * +--------------------------------------------------------------+
830 * | +----------------------------------------------+ [stopped / |
831 * | | | sleeping] -+
832 * +-+-> active <-> warning <-> passive -> bus off -+
833 * ___________^^^^^^^^^^^^_______________________________
834 * disabled(1) enabled disabled
835 *
836 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
837 */
838 if ((last_state != priv->can.state) &&
839 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
840 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
841 switch (priv->can.state) {
842 case CAN_STATE_ERROR_ACTIVE:
843 if (priv->devtype_data->quirks &
844 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
845 flexcan_error_irq_enable(priv);
846 else
847 flexcan_error_irq_disable(priv);
848 break;
849
850 case CAN_STATE_ERROR_WARNING:
851 flexcan_error_irq_enable(priv);
852 break;
853
854 case CAN_STATE_ERROR_PASSIVE:
855 case CAN_STATE_BUS_OFF:
856 flexcan_error_irq_disable(priv);
857 break;
858
859 default:
860 break;
861 }
862 }
863
864 return handled;
865}
866
867static void flexcan_set_bittiming(struct net_device *dev)
868{
869 const struct flexcan_priv *priv = netdev_priv(dev);
870 const struct can_bittiming *bt = &priv->can.bittiming;
871 struct flexcan_regs __iomem *regs = priv->regs;
872 u32 reg;
873
874 reg = priv->read(®s->ctrl);
875 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
876 FLEXCAN_CTRL_RJW(0x3) |
877 FLEXCAN_CTRL_PSEG1(0x7) |
878 FLEXCAN_CTRL_PSEG2(0x7) |
879 FLEXCAN_CTRL_PROPSEG(0x7) |
880 FLEXCAN_CTRL_LPB |
881 FLEXCAN_CTRL_SMP |
882 FLEXCAN_CTRL_LOM);
883
884 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
885 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
886 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
887 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
888 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
889
890 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
891 reg |= FLEXCAN_CTRL_LPB;
892 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
893 reg |= FLEXCAN_CTRL_LOM;
894 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
895 reg |= FLEXCAN_CTRL_SMP;
896
897 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
898 priv->write(reg, ®s->ctrl);
899
900 /* print chip status */
901 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
902 priv->read(®s->mcr), priv->read(®s->ctrl));
903}
904
905/* flexcan_chip_start
906 *
907 * this functions is entered with clocks enabled
908 *
909 */
910static int flexcan_chip_start(struct net_device *dev)
911{
912 struct flexcan_priv *priv = netdev_priv(dev);
913 struct flexcan_regs __iomem *regs = priv->regs;
914 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
915 int err, i;
916
917 /* enable module */
918 err = flexcan_chip_enable(priv);
919 if (err)
920 return err;
921
922 /* soft reset */
923 err = flexcan_chip_softreset(priv);
924 if (err)
925 goto out_chip_disable;
926
927 flexcan_set_bittiming(dev);
928
929 /* MCR
930 *
931 * enable freeze
932 * enable fifo
933 * halt now
934 * only supervisor access
935 * enable warning int
936 * disable local echo
937 * enable individual RX masking
938 * choose format C
939 * set max mailbox number
940 */
941 reg_mcr = priv->read(®s->mcr);
942 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
943 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
944 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
945 FLEXCAN_MCR_IDAM_C;
946
947 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
948 reg_mcr &= ~FLEXCAN_MCR_FEN;
949 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
950 } else {
951 reg_mcr |= FLEXCAN_MCR_FEN |
952 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
953 }
954 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
955 priv->write(reg_mcr, ®s->mcr);
956
957 /* CTRL
958 *
959 * disable timer sync feature
960 *
961 * disable auto busoff recovery
962 * transmit lowest buffer first
963 *
964 * enable tx and rx warning interrupt
965 * enable bus off interrupt
966 * (== FLEXCAN_CTRL_ERR_STATE)
967 */
968 reg_ctrl = priv->read(®s->ctrl);
969 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
970 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
971 FLEXCAN_CTRL_ERR_STATE;
972
973 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
974 * on most Flexcan cores, too. Otherwise we don't get
975 * any error warning or passive interrupts.
976 */
977 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
978 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
979 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
980 else
981 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
982
983 /* save for later use */
984 priv->reg_ctrl_default = reg_ctrl;
985 /* leave interrupts disabled for now */
986 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
987 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
988 priv->write(reg_ctrl, ®s->ctrl);
989
990 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
991 reg_ctrl2 = priv->read(®s->ctrl2);
992 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
993 priv->write(reg_ctrl2, ®s->ctrl2);
994 }
995
996 /* clear and invalidate all mailboxes first */
997 for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
998 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
999 ®s->mb[i].can_ctrl);
1000 }
1001
1002 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1003 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
1004 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1005 ®s->mb[i].can_ctrl);
1006 }
1007
1008 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1009 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1010 &priv->tx_mb_reserved->can_ctrl);
1011
1012 /* mark TX mailbox as INACTIVE */
1013 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1014 &priv->tx_mb->can_ctrl);
1015
1016 /* acceptance mask/acceptance code (accept everything) */
1017 priv->write(0x0, ®s->rxgmask);
1018 priv->write(0x0, ®s->rx14mask);
1019 priv->write(0x0, ®s->rx15mask);
1020
1021 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1022 priv->write(0x0, ®s->rxfgmask);
1023
1024 /* clear acceptance filters */
1025 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1026 priv->write(0, ®s->rximr[i]);
1027
1028 /* On Vybrid, disable memory error detection interrupts
1029 * and freeze mode.
1030 * This also works around errata e5295 which generates
1031 * false positive memory errors and put the device in
1032 * freeze mode.
1033 */
1034 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1035 /* Follow the protocol as described in "Detection
1036 * and Correction of Memory Errors" to write to
1037 * MECR register
1038 */
1039 reg_ctrl2 = priv->read(®s->ctrl2);
1040 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1041 priv->write(reg_ctrl2, ®s->ctrl2);
1042
1043 reg_mecr = priv->read(®s->mecr);
1044 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1045 priv->write(reg_mecr, ®s->mecr);
1046 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1047 FLEXCAN_MECR_FANCEI_MSK);
1048 priv->write(reg_mecr, ®s->mecr);
1049 }
1050
1051 err = flexcan_transceiver_enable(priv);
1052 if (err)
1053 goto out_chip_disable;
1054
1055 /* synchronize with the can bus */
1056 err = flexcan_chip_unfreeze(priv);
1057 if (err)
1058 goto out_transceiver_disable;
1059
1060 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1061
1062 /* enable interrupts atomically */
1063 disable_irq(dev->irq);
1064 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1065 priv->write(priv->reg_imask1_default, ®s->imask1);
1066 priv->write(priv->reg_imask2_default, ®s->imask2);
1067 enable_irq(dev->irq);
1068
1069 /* print chip status */
1070 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1071 priv->read(®s->mcr), priv->read(®s->ctrl));
1072
1073 return 0;
1074
1075 out_transceiver_disable:
1076 flexcan_transceiver_disable(priv);
1077 out_chip_disable:
1078 flexcan_chip_disable(priv);
1079 return err;
1080}
1081
1082/* flexcan_chip_stop
1083 *
1084 * this functions is entered with clocks enabled
1085 */
1086static void flexcan_chip_stop(struct net_device *dev)
1087{
1088 struct flexcan_priv *priv = netdev_priv(dev);
1089 struct flexcan_regs __iomem *regs = priv->regs;
1090
1091 /* freeze + disable module */
1092 flexcan_chip_freeze(priv);
1093 flexcan_chip_disable(priv);
1094
1095 /* Disable all interrupts */
1096 priv->write(0, ®s->imask2);
1097 priv->write(0, ®s->imask1);
1098 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1099 ®s->ctrl);
1100
1101 flexcan_transceiver_disable(priv);
1102 priv->can.state = CAN_STATE_STOPPED;
1103}
1104
1105static int flexcan_open(struct net_device *dev)
1106{
1107 struct flexcan_priv *priv = netdev_priv(dev);
1108 int err;
1109
1110 err = clk_prepare_enable(priv->clk_ipg);
1111 if (err)
1112 return err;
1113
1114 err = clk_prepare_enable(priv->clk_per);
1115 if (err)
1116 goto out_disable_ipg;
1117
1118 err = open_candev(dev);
1119 if (err)
1120 goto out_disable_per;
1121
1122 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1123 if (err)
1124 goto out_close;
1125
1126 /* start chip and queuing */
1127 err = flexcan_chip_start(dev);
1128 if (err)
1129 goto out_free_irq;
1130
1131 can_led_event(dev, CAN_LED_EVENT_OPEN);
1132
1133 can_rx_offload_enable(&priv->offload);
1134 netif_start_queue(dev);
1135
1136 return 0;
1137
1138 out_free_irq:
1139 free_irq(dev->irq, dev);
1140 out_close:
1141 close_candev(dev);
1142 out_disable_per:
1143 clk_disable_unprepare(priv->clk_per);
1144 out_disable_ipg:
1145 clk_disable_unprepare(priv->clk_ipg);
1146
1147 return err;
1148}
1149
1150static int flexcan_close(struct net_device *dev)
1151{
1152 struct flexcan_priv *priv = netdev_priv(dev);
1153
1154 netif_stop_queue(dev);
1155 can_rx_offload_disable(&priv->offload);
1156 flexcan_chip_stop(dev);
1157
1158 free_irq(dev->irq, dev);
1159 clk_disable_unprepare(priv->clk_per);
1160 clk_disable_unprepare(priv->clk_ipg);
1161
1162 close_candev(dev);
1163
1164 can_led_event(dev, CAN_LED_EVENT_STOP);
1165
1166 return 0;
1167}
1168
1169static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1170{
1171 int err;
1172
1173 switch (mode) {
1174 case CAN_MODE_START:
1175 err = flexcan_chip_start(dev);
1176 if (err)
1177 return err;
1178
1179 netif_wake_queue(dev);
1180 break;
1181
1182 default:
1183 return -EOPNOTSUPP;
1184 }
1185
1186 return 0;
1187}
1188
1189static const struct net_device_ops flexcan_netdev_ops = {
1190 .ndo_open = flexcan_open,
1191 .ndo_stop = flexcan_close,
1192 .ndo_start_xmit = flexcan_start_xmit,
1193 .ndo_change_mtu = can_change_mtu,
1194};
1195
1196static int register_flexcandev(struct net_device *dev)
1197{
1198 struct flexcan_priv *priv = netdev_priv(dev);
1199 struct flexcan_regs __iomem *regs = priv->regs;
1200 u32 reg, err;
1201
1202 err = clk_prepare_enable(priv->clk_ipg);
1203 if (err)
1204 return err;
1205
1206 err = clk_prepare_enable(priv->clk_per);
1207 if (err)
1208 goto out_disable_ipg;
1209
1210 /* select "bus clock", chip must be disabled */
1211 err = flexcan_chip_disable(priv);
1212 if (err)
1213 goto out_disable_per;
1214 reg = priv->read(®s->ctrl);
1215 reg |= FLEXCAN_CTRL_CLK_SRC;
1216 priv->write(reg, ®s->ctrl);
1217
1218 err = flexcan_chip_enable(priv);
1219 if (err)
1220 goto out_chip_disable;
1221
1222 /* set freeze, halt and activate FIFO, restrict register access */
1223 reg = priv->read(®s->mcr);
1224 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1225 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1226 priv->write(reg, ®s->mcr);
1227
1228 /* Currently we only support newer versions of this core
1229 * featuring a RX hardware FIFO (although this driver doesn't
1230 * make use of it on some cores). Older cores, found on some
1231 * Coldfire derivates are not tested.
1232 */
1233 reg = priv->read(®s->mcr);
1234 if (!(reg & FLEXCAN_MCR_FEN)) {
1235 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1236 err = -ENODEV;
1237 goto out_chip_disable;
1238 }
1239
1240 err = register_candev(dev);
1241
1242 /* disable core and turn off clocks */
1243 out_chip_disable:
1244 flexcan_chip_disable(priv);
1245 out_disable_per:
1246 clk_disable_unprepare(priv->clk_per);
1247 out_disable_ipg:
1248 clk_disable_unprepare(priv->clk_ipg);
1249
1250 return err;
1251}
1252
1253static void unregister_flexcandev(struct net_device *dev)
1254{
1255 unregister_candev(dev);
1256}
1257
1258static const struct of_device_id flexcan_of_match[] = {
1259 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1260 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1261 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1262 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1263 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1264 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1265 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1266 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1267 { /* sentinel */ },
1268};
1269MODULE_DEVICE_TABLE(of, flexcan_of_match);
1270
1271static const struct platform_device_id flexcan_id_table[] = {
1272 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1273 { /* sentinel */ },
1274};
1275MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1276
1277static int flexcan_probe(struct platform_device *pdev)
1278{
1279 const struct of_device_id *of_id;
1280 const struct flexcan_devtype_data *devtype_data;
1281 struct net_device *dev;
1282 struct flexcan_priv *priv;
1283 struct regulator *reg_xceiver;
1284 struct resource *mem;
1285 struct clk *clk_ipg = NULL, *clk_per = NULL;
1286 struct flexcan_regs __iomem *regs;
1287 int err, irq;
1288 u32 clock_freq = 0;
1289
1290 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1291 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1292 return -EPROBE_DEFER;
1293 else if (IS_ERR(reg_xceiver))
1294 reg_xceiver = NULL;
1295
1296 if (pdev->dev.of_node)
1297 of_property_read_u32(pdev->dev.of_node,
1298 "clock-frequency", &clock_freq);
1299
1300 if (!clock_freq) {
1301 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1302 if (IS_ERR(clk_ipg)) {
1303 dev_err(&pdev->dev, "no ipg clock defined\n");
1304 return PTR_ERR(clk_ipg);
1305 }
1306
1307 clk_per = devm_clk_get(&pdev->dev, "per");
1308 if (IS_ERR(clk_per)) {
1309 dev_err(&pdev->dev, "no per clock defined\n");
1310 return PTR_ERR(clk_per);
1311 }
1312 clock_freq = clk_get_rate(clk_per);
1313 }
1314
1315 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316 irq = platform_get_irq(pdev, 0);
1317 if (irq <= 0)
1318 return -ENODEV;
1319
1320 regs = devm_ioremap_resource(&pdev->dev, mem);
1321 if (IS_ERR(regs))
1322 return PTR_ERR(regs);
1323
1324 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1325 if (of_id) {
1326 devtype_data = of_id->data;
1327 } else if (platform_get_device_id(pdev)->driver_data) {
1328 devtype_data = (struct flexcan_devtype_data *)
1329 platform_get_device_id(pdev)->driver_data;
1330 } else {
1331 return -ENODEV;
1332 }
1333
1334 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1335 if (!dev)
1336 return -ENOMEM;
1337
1338 platform_set_drvdata(pdev, dev);
1339 SET_NETDEV_DEV(dev, &pdev->dev);
1340
1341 dev->netdev_ops = &flexcan_netdev_ops;
1342 dev->irq = irq;
1343 dev->flags |= IFF_ECHO;
1344
1345 priv = netdev_priv(dev);
1346
1347 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1348 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1349 priv->read = flexcan_read_be;
1350 priv->write = flexcan_write_be;
1351 } else {
1352 priv->read = flexcan_read_le;
1353 priv->write = flexcan_write_le;
1354 }
1355
1356 priv->can.clock.freq = clock_freq;
1357 priv->can.bittiming_const = &flexcan_bittiming_const;
1358 priv->can.do_set_mode = flexcan_set_mode;
1359 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1360 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1361 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1362 CAN_CTRLMODE_BERR_REPORTING;
1363 priv->regs = regs;
1364 priv->clk_ipg = clk_ipg;
1365 priv->clk_per = clk_per;
1366 priv->devtype_data = devtype_data;
1367 priv->reg_xceiver = reg_xceiver;
1368
1369 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1370 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1371 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1372 } else {
1373 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1374 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1375 }
1376 priv->tx_mb = ®s->mb[priv->tx_mb_idx];
1377
1378 priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1379 priv->reg_imask2_default = 0;
1380
1381 priv->offload.mailbox_read = flexcan_mailbox_read;
1382
1383 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1384 u64 imask;
1385
1386 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1387 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1388
1389 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1390 priv->reg_imask1_default |= imask;
1391 priv->reg_imask2_default |= imask >> 32;
1392
1393 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1394 } else {
1395 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1396 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1397 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1398 }
1399 if (err)
1400 goto failed_offload;
1401
1402 err = register_flexcandev(dev);
1403 if (err) {
1404 dev_err(&pdev->dev, "registering netdev failed\n");
1405 goto failed_register;
1406 }
1407
1408 devm_can_led_init(dev);
1409
1410 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1411 priv->regs, dev->irq);
1412
1413 return 0;
1414
1415 failed_offload:
1416 failed_register:
1417 free_candev(dev);
1418 return err;
1419}
1420
1421static int flexcan_remove(struct platform_device *pdev)
1422{
1423 struct net_device *dev = platform_get_drvdata(pdev);
1424 struct flexcan_priv *priv = netdev_priv(dev);
1425
1426 unregister_flexcandev(dev);
1427 can_rx_offload_del(&priv->offload);
1428 free_candev(dev);
1429
1430 return 0;
1431}
1432
1433static int __maybe_unused flexcan_suspend(struct device *device)
1434{
1435 struct net_device *dev = dev_get_drvdata(device);
1436 struct flexcan_priv *priv = netdev_priv(dev);
1437 int err;
1438
1439 if (netif_running(dev)) {
1440 err = flexcan_chip_disable(priv);
1441 if (err)
1442 return err;
1443 netif_stop_queue(dev);
1444 netif_device_detach(dev);
1445 }
1446 priv->can.state = CAN_STATE_SLEEPING;
1447
1448 return 0;
1449}
1450
1451static int __maybe_unused flexcan_resume(struct device *device)
1452{
1453 struct net_device *dev = dev_get_drvdata(device);
1454 struct flexcan_priv *priv = netdev_priv(dev);
1455 int err;
1456
1457 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1458 if (netif_running(dev)) {
1459 netif_device_attach(dev);
1460 netif_start_queue(dev);
1461 err = flexcan_chip_enable(priv);
1462 if (err)
1463 return err;
1464 }
1465 return 0;
1466}
1467
1468static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1469
1470static struct platform_driver flexcan_driver = {
1471 .driver = {
1472 .name = DRV_NAME,
1473 .pm = &flexcan_pm_ops,
1474 .of_match_table = flexcan_of_match,
1475 },
1476 .probe = flexcan_probe,
1477 .remove = flexcan_remove,
1478 .id_table = flexcan_id_table,
1479};
1480
1481module_platform_driver(flexcan_driver);
1482
1483MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1484 "Marc Kleine-Budde <kernel@pengutronix.de>");
1485MODULE_LICENSE("GPL v2");
1486MODULE_DESCRIPTION("CAN port driver for flexcan based chip");