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1// SPDX-License-Identifier: GPL-2.0
2//
3// flexcan.c - FLEXCAN CAN controller driver
4//
5// Copyright (c) 2005-2006 Varma Electronics Oy
6// Copyright (c) 2009 Sascha Hauer, Pengutronix
7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8// Copyright (c) 2014 David Jander, Protonic Holland
9//
10// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12#include <dt-bindings/firmware/imx/rsrc.h>
13#include <linux/bitfield.h>
14#include <linux/can.h>
15#include <linux/can/dev.h>
16#include <linux/can/error.h>
17#include <linux/can/led.h>
18#include <linux/can/rx-offload.h>
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/firmware/imx/sci.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/mfd/syscon.h>
25#include <linux/module.h>
26#include <linux/netdevice.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/regmap.h>
33#include <linux/regulator/consumer.h>
34
35#define DRV_NAME "flexcan"
36
37/* 8 for RX fifo and 2 error handling */
38#define FLEXCAN_NAPI_WEIGHT (8 + 2)
39
40/* FLEXCAN module configuration register (CANMCR) bits */
41#define FLEXCAN_MCR_MDIS BIT(31)
42#define FLEXCAN_MCR_FRZ BIT(30)
43#define FLEXCAN_MCR_FEN BIT(29)
44#define FLEXCAN_MCR_HALT BIT(28)
45#define FLEXCAN_MCR_NOT_RDY BIT(27)
46#define FLEXCAN_MCR_WAK_MSK BIT(26)
47#define FLEXCAN_MCR_SOFTRST BIT(25)
48#define FLEXCAN_MCR_FRZ_ACK BIT(24)
49#define FLEXCAN_MCR_SUPV BIT(23)
50#define FLEXCAN_MCR_SLF_WAK BIT(22)
51#define FLEXCAN_MCR_WRN_EN BIT(21)
52#define FLEXCAN_MCR_LPM_ACK BIT(20)
53#define FLEXCAN_MCR_WAK_SRC BIT(19)
54#define FLEXCAN_MCR_DOZE BIT(18)
55#define FLEXCAN_MCR_SRX_DIS BIT(17)
56#define FLEXCAN_MCR_IRMQ BIT(16)
57#define FLEXCAN_MCR_LPRIO_EN BIT(13)
58#define FLEXCAN_MCR_AEN BIT(12)
59#define FLEXCAN_MCR_FDEN BIT(11)
60/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
61#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
62#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
63#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
64#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
65#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
66
67/* FLEXCAN control register (CANCTRL) bits */
68#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
69#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
70#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
71#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
72#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
73#define FLEXCAN_CTRL_ERR_MSK BIT(14)
74#define FLEXCAN_CTRL_CLK_SRC BIT(13)
75#define FLEXCAN_CTRL_LPB BIT(12)
76#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
77#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
78#define FLEXCAN_CTRL_SMP BIT(7)
79#define FLEXCAN_CTRL_BOFF_REC BIT(6)
80#define FLEXCAN_CTRL_TSYN BIT(5)
81#define FLEXCAN_CTRL_LBUF BIT(4)
82#define FLEXCAN_CTRL_LOM BIT(3)
83#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
84#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
85#define FLEXCAN_CTRL_ERR_STATE \
86 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
87 FLEXCAN_CTRL_BOFF_MSK)
88#define FLEXCAN_CTRL_ERR_ALL \
89 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
90
91/* FLEXCAN control register 2 (CTRL2) bits */
92#define FLEXCAN_CTRL2_ECRWRE BIT(29)
93#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
94#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
95#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
96#define FLEXCAN_CTRL2_MRP BIT(18)
97#define FLEXCAN_CTRL2_RRS BIT(17)
98#define FLEXCAN_CTRL2_EACEN BIT(16)
99#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
100
101/* FLEXCAN memory error control register (MECR) bits */
102#define FLEXCAN_MECR_ECRWRDIS BIT(31)
103#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
104#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
105#define FLEXCAN_MECR_CEI_MSK BIT(16)
106#define FLEXCAN_MECR_HAERRIE BIT(15)
107#define FLEXCAN_MECR_FAERRIE BIT(14)
108#define FLEXCAN_MECR_EXTERRIE BIT(13)
109#define FLEXCAN_MECR_RERRDIS BIT(9)
110#define FLEXCAN_MECR_ECCDIS BIT(8)
111#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
112
113/* FLEXCAN error and status register (ESR) bits */
114#define FLEXCAN_ESR_TWRN_INT BIT(17)
115#define FLEXCAN_ESR_RWRN_INT BIT(16)
116#define FLEXCAN_ESR_BIT1_ERR BIT(15)
117#define FLEXCAN_ESR_BIT0_ERR BIT(14)
118#define FLEXCAN_ESR_ACK_ERR BIT(13)
119#define FLEXCAN_ESR_CRC_ERR BIT(12)
120#define FLEXCAN_ESR_FRM_ERR BIT(11)
121#define FLEXCAN_ESR_STF_ERR BIT(10)
122#define FLEXCAN_ESR_TX_WRN BIT(9)
123#define FLEXCAN_ESR_RX_WRN BIT(8)
124#define FLEXCAN_ESR_IDLE BIT(7)
125#define FLEXCAN_ESR_TXRX BIT(6)
126#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
127#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
128#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
129#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
130#define FLEXCAN_ESR_BOFF_INT BIT(2)
131#define FLEXCAN_ESR_ERR_INT BIT(1)
132#define FLEXCAN_ESR_WAK_INT BIT(0)
133#define FLEXCAN_ESR_ERR_BUS \
134 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
135 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
136 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
137#define FLEXCAN_ESR_ERR_STATE \
138 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
139#define FLEXCAN_ESR_ERR_ALL \
140 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
141#define FLEXCAN_ESR_ALL_INT \
142 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
143 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
144
145/* FLEXCAN Bit Timing register (CBT) bits */
146#define FLEXCAN_CBT_BTF BIT(31)
147#define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
148#define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
149#define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
150#define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
151#define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
152
153/* FLEXCAN FD control register (FDCTRL) bits */
154#define FLEXCAN_FDCTRL_FDRATE BIT(31)
155#define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
156#define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
157#define FLEXCAN_FDCTRL_MBDSR_8 0x0
158#define FLEXCAN_FDCTRL_MBDSR_12 0x1
159#define FLEXCAN_FDCTRL_MBDSR_32 0x2
160#define FLEXCAN_FDCTRL_MBDSR_64 0x3
161#define FLEXCAN_FDCTRL_TDCEN BIT(15)
162#define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
163#define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
164#define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
165
166/* FLEXCAN FD Bit Timing register (FDCBT) bits */
167#define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
168#define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
169#define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
170#define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
171#define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
172
173/* FLEXCAN interrupt flag register (IFLAG) bits */
174/* Errata ERR005829 step7: Reserve first valid MB */
175#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
176#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
177#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
178#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
179#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
180#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
181#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
182
183/* FLEXCAN message buffers */
184#define FLEXCAN_MB_CODE_MASK (0xf << 24)
185#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
186#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
187#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
188#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
189#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
190#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
191
192#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
193#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
194#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
195#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
196
197#define FLEXCAN_MB_CNT_EDL BIT(31)
198#define FLEXCAN_MB_CNT_BRS BIT(30)
199#define FLEXCAN_MB_CNT_ESI BIT(29)
200#define FLEXCAN_MB_CNT_SRR BIT(22)
201#define FLEXCAN_MB_CNT_IDE BIT(21)
202#define FLEXCAN_MB_CNT_RTR BIT(20)
203#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
204#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
205
206#define FLEXCAN_TIMEOUT_US (250)
207
208/* FLEXCAN hardware feature flags
209 *
210 * Below is some version info we got:
211 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
212 * Filter? connected? Passive detection ption in MB Supported?
213 * MX25 FlexCAN2 03.00.00.00 no no no no no no
214 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no
215 * MX35 FlexCAN2 03.00.00.00 no no no no no no
216 * MX53 FlexCAN2 03.00.00.00 yes no no no no no
217 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no
218 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes
219 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes
220 * VF610 FlexCAN3 ? no yes no yes yes? no
221 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
222 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes
223 *
224 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
225 */
226
227/* [TR]WRN_INT not connected */
228#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
229 /* Disable RX FIFO Global mask */
230#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
231/* Enable EACEN and RRS bit in ctrl2 */
232#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
233/* Disable non-correctable errors interrupt and freeze mode */
234#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
235/* Use timestamp based offloading */
236#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
237/* No interrupt for error passive */
238#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
239/* default to BE register access */
240#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
241/* Setup stop mode with GPR to support wakeup */
242#define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
243/* Support CAN-FD mode */
244#define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
245/* support memory detection and correction */
246#define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
247/* Setup stop mode with SCU firmware to support wakeup */
248#define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
249
250/* Structure of the message buffer */
251struct flexcan_mb {
252 u32 can_ctrl;
253 u32 can_id;
254 u32 data[];
255};
256
257/* Structure of the hardware registers */
258struct flexcan_regs {
259 u32 mcr; /* 0x00 */
260 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
261 u32 timer; /* 0x08 */
262 u32 tcr; /* 0x0c */
263 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
264 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
265 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
266 u32 ecr; /* 0x1c */
267 u32 esr; /* 0x20 */
268 u32 imask2; /* 0x24 */
269 u32 imask1; /* 0x28 */
270 u32 iflag2; /* 0x2c */
271 u32 iflag1; /* 0x30 */
272 union { /* 0x34 */
273 u32 gfwr_mx28; /* MX28, MX53 */
274 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
275 };
276 u32 esr2; /* 0x38 */
277 u32 imeur; /* 0x3c */
278 u32 lrfr; /* 0x40 */
279 u32 crcr; /* 0x44 */
280 u32 rxfgmask; /* 0x48 */
281 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
282 u32 cbt; /* 0x50 - Not affected by Soft Reset */
283 u32 _reserved2; /* 0x54 */
284 u32 dbg1; /* 0x58 */
285 u32 dbg2; /* 0x5c */
286 u32 _reserved3[8]; /* 0x60 */
287 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
288 /* FIFO-mode:
289 * MB
290 * 0x080...0x08f 0 RX message buffer
291 * 0x090...0x0df 1-5 reserved
292 * 0x0e0...0x0ff 6-7 8 entry ID table
293 * (mx25, mx28, mx35, mx53)
294 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
295 * size conf'ed via ctrl2::RFFN
296 * (mx6, vf610)
297 */
298 u32 _reserved4[256]; /* 0x480 */
299 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
300 u32 _reserved5[24]; /* 0x980 */
301 u32 gfwr_mx6; /* 0x9e0 - MX6 */
302 u32 _reserved6[39]; /* 0x9e4 */
303 u32 _rxfir[6]; /* 0xa80 */
304 u32 _reserved8[2]; /* 0xa98 */
305 u32 _rxmgmask; /* 0xaa0 */
306 u32 _rxfgmask; /* 0xaa4 */
307 u32 _rx14mask; /* 0xaa8 */
308 u32 _rx15mask; /* 0xaac */
309 u32 tx_smb[4]; /* 0xab0 */
310 u32 rx_smb0[4]; /* 0xac0 */
311 u32 rx_smb1[4]; /* 0xad0 */
312 u32 mecr; /* 0xae0 */
313 u32 erriar; /* 0xae4 */
314 u32 erridpr; /* 0xae8 */
315 u32 errippr; /* 0xaec */
316 u32 rerrar; /* 0xaf0 */
317 u32 rerrdr; /* 0xaf4 */
318 u32 rerrsynr; /* 0xaf8 */
319 u32 errsr; /* 0xafc */
320 u32 _reserved7[64]; /* 0xb00 */
321 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
322 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
323 u32 fdcrc; /* 0xc08 */
324 u32 _reserved9[199]; /* 0xc0c */
325 u32 tx_smb_fd[18]; /* 0xf28 */
326 u32 rx_smb0_fd[18]; /* 0xf70 */
327 u32 rx_smb1_fd[18]; /* 0xfb8 */
328};
329
330static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
331
332struct flexcan_devtype_data {
333 u32 quirks; /* quirks needed for different IP cores */
334};
335
336struct flexcan_stop_mode {
337 struct regmap *gpr;
338 u8 req_gpr;
339 u8 req_bit;
340};
341
342struct flexcan_priv {
343 struct can_priv can;
344 struct can_rx_offload offload;
345 struct device *dev;
346
347 struct flexcan_regs __iomem *regs;
348 struct flexcan_mb __iomem *tx_mb;
349 struct flexcan_mb __iomem *tx_mb_reserved;
350 u8 tx_mb_idx;
351 u8 mb_count;
352 u8 mb_size;
353 u8 clk_src; /* clock source of CAN Protocol Engine */
354 u8 scu_idx;
355
356 u64 rx_mask;
357 u64 tx_mask;
358 u32 reg_ctrl_default;
359
360 struct clk *clk_ipg;
361 struct clk *clk_per;
362 const struct flexcan_devtype_data *devtype_data;
363 struct regulator *reg_xceiver;
364 struct flexcan_stop_mode stm;
365
366 /* IPC handle when setup stop mode by System Controller firmware(scfw) */
367 struct imx_sc_ipc *sc_ipc_handle;
368
369 /* Read and Write APIs */
370 u32 (*read)(void __iomem *addr);
371 void (*write)(u32 val, void __iomem *addr);
372};
373
374static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
375 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
376 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
377 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
378};
379
380static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
381 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
382 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
383};
384
385static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
386 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
387};
388
389static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
390 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
391 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
392 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR,
393};
394
395static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
396 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
397 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
398 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW,
399};
400
401static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
402 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
403 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
404 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
405 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
406};
407
408static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
409 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
410 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
411 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
412};
413
414static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
415 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
416 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
417};
418
419static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
420 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
421 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
422 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
423 FLEXCAN_QUIRK_SUPPORT_ECC,
424};
425
426static const struct can_bittiming_const flexcan_bittiming_const = {
427 .name = DRV_NAME,
428 .tseg1_min = 4,
429 .tseg1_max = 16,
430 .tseg2_min = 2,
431 .tseg2_max = 8,
432 .sjw_max = 4,
433 .brp_min = 1,
434 .brp_max = 256,
435 .brp_inc = 1,
436};
437
438static const struct can_bittiming_const flexcan_fd_bittiming_const = {
439 .name = DRV_NAME,
440 .tseg1_min = 2,
441 .tseg1_max = 96,
442 .tseg2_min = 2,
443 .tseg2_max = 32,
444 .sjw_max = 16,
445 .brp_min = 1,
446 .brp_max = 1024,
447 .brp_inc = 1,
448};
449
450static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
451 .name = DRV_NAME,
452 .tseg1_min = 2,
453 .tseg1_max = 39,
454 .tseg2_min = 2,
455 .tseg2_max = 8,
456 .sjw_max = 4,
457 .brp_min = 1,
458 .brp_max = 1024,
459 .brp_inc = 1,
460};
461
462/* FlexCAN module is essentially modelled as a little-endian IP in most
463 * SoCs, i.e the registers as well as the message buffer areas are
464 * implemented in a little-endian fashion.
465 *
466 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
467 * module in a big-endian fashion (i.e the registers as well as the
468 * message buffer areas are implemented in a big-endian way).
469 *
470 * In addition, the FlexCAN module can be found on SoCs having ARM or
471 * PPC cores. So, we need to abstract off the register read/write
472 * functions, ensuring that these cater to all the combinations of module
473 * endianness and underlying CPU endianness.
474 */
475static inline u32 flexcan_read_be(void __iomem *addr)
476{
477 return ioread32be(addr);
478}
479
480static inline void flexcan_write_be(u32 val, void __iomem *addr)
481{
482 iowrite32be(val, addr);
483}
484
485static inline u32 flexcan_read_le(void __iomem *addr)
486{
487 return ioread32(addr);
488}
489
490static inline void flexcan_write_le(u32 val, void __iomem *addr)
491{
492 iowrite32(val, addr);
493}
494
495static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
496 u8 mb_index)
497{
498 u8 bank_size;
499 bool bank;
500
501 if (WARN_ON(mb_index >= priv->mb_count))
502 return NULL;
503
504 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
505
506 bank = mb_index >= bank_size;
507 if (bank)
508 mb_index -= bank_size;
509
510 return (struct flexcan_mb __iomem *)
511 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
512}
513
514static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
515{
516 struct flexcan_regs __iomem *regs = priv->regs;
517 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
518
519 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
520 udelay(10);
521
522 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
523 return -ETIMEDOUT;
524
525 return 0;
526}
527
528static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
529{
530 struct flexcan_regs __iomem *regs = priv->regs;
531 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
532
533 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
534 udelay(10);
535
536 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
537 return -ETIMEDOUT;
538
539 return 0;
540}
541
542static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
543{
544 struct flexcan_regs __iomem *regs = priv->regs;
545 u32 reg_mcr;
546
547 reg_mcr = priv->read(®s->mcr);
548
549 if (enable)
550 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
551 else
552 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
553
554 priv->write(reg_mcr, ®s->mcr);
555}
556
557static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
558{
559 u8 idx = priv->scu_idx;
560 u32 rsrc_id, val;
561
562 rsrc_id = IMX_SC_R_CAN(idx);
563
564 if (enabled)
565 val = 1;
566 else
567 val = 0;
568
569 /* stop mode request via scu firmware */
570 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
571 IMX_SC_C_IPG_STOP, val);
572}
573
574static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
575{
576 struct flexcan_regs __iomem *regs = priv->regs;
577 u32 reg_mcr;
578 int ret;
579
580 reg_mcr = priv->read(®s->mcr);
581 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
582 priv->write(reg_mcr, ®s->mcr);
583
584 /* enable stop request */
585 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
586 ret = flexcan_stop_mode_enable_scfw(priv, true);
587 if (ret < 0)
588 return ret;
589 } else {
590 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
591 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
592 }
593
594 return flexcan_low_power_enter_ack(priv);
595}
596
597static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
598{
599 struct flexcan_regs __iomem *regs = priv->regs;
600 u32 reg_mcr;
601 int ret;
602
603 /* remove stop request */
604 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
605 ret = flexcan_stop_mode_enable_scfw(priv, false);
606 if (ret < 0)
607 return ret;
608 } else {
609 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
610 1 << priv->stm.req_bit, 0);
611 }
612
613 reg_mcr = priv->read(®s->mcr);
614 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
615 priv->write(reg_mcr, ®s->mcr);
616
617 return flexcan_low_power_exit_ack(priv);
618}
619
620static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
621{
622 struct flexcan_regs __iomem *regs = priv->regs;
623 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
624
625 priv->write(reg_ctrl, ®s->ctrl);
626}
627
628static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
629{
630 struct flexcan_regs __iomem *regs = priv->regs;
631 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
632
633 priv->write(reg_ctrl, ®s->ctrl);
634}
635
636static int flexcan_clks_enable(const struct flexcan_priv *priv)
637{
638 int err;
639
640 err = clk_prepare_enable(priv->clk_ipg);
641 if (err)
642 return err;
643
644 err = clk_prepare_enable(priv->clk_per);
645 if (err)
646 clk_disable_unprepare(priv->clk_ipg);
647
648 return err;
649}
650
651static void flexcan_clks_disable(const struct flexcan_priv *priv)
652{
653 clk_disable_unprepare(priv->clk_per);
654 clk_disable_unprepare(priv->clk_ipg);
655}
656
657static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
658{
659 if (!priv->reg_xceiver)
660 return 0;
661
662 return regulator_enable(priv->reg_xceiver);
663}
664
665static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
666{
667 if (!priv->reg_xceiver)
668 return 0;
669
670 return regulator_disable(priv->reg_xceiver);
671}
672
673static int flexcan_chip_enable(struct flexcan_priv *priv)
674{
675 struct flexcan_regs __iomem *regs = priv->regs;
676 u32 reg;
677
678 reg = priv->read(®s->mcr);
679 reg &= ~FLEXCAN_MCR_MDIS;
680 priv->write(reg, ®s->mcr);
681
682 return flexcan_low_power_exit_ack(priv);
683}
684
685static int flexcan_chip_disable(struct flexcan_priv *priv)
686{
687 struct flexcan_regs __iomem *regs = priv->regs;
688 u32 reg;
689
690 reg = priv->read(®s->mcr);
691 reg |= FLEXCAN_MCR_MDIS;
692 priv->write(reg, ®s->mcr);
693
694 return flexcan_low_power_enter_ack(priv);
695}
696
697static int flexcan_chip_freeze(struct flexcan_priv *priv)
698{
699 struct flexcan_regs __iomem *regs = priv->regs;
700 unsigned int timeout;
701 u32 bitrate = priv->can.bittiming.bitrate;
702 u32 reg;
703
704 if (bitrate)
705 timeout = 1000 * 1000 * 10 / bitrate;
706 else
707 timeout = FLEXCAN_TIMEOUT_US / 10;
708
709 reg = priv->read(®s->mcr);
710 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
711 priv->write(reg, ®s->mcr);
712
713 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
714 udelay(100);
715
716 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
717 return -ETIMEDOUT;
718
719 return 0;
720}
721
722static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
723{
724 struct flexcan_regs __iomem *regs = priv->regs;
725 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
726 u32 reg;
727
728 reg = priv->read(®s->mcr);
729 reg &= ~FLEXCAN_MCR_HALT;
730 priv->write(reg, ®s->mcr);
731
732 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
733 udelay(10);
734
735 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
736 return -ETIMEDOUT;
737
738 return 0;
739}
740
741static int flexcan_chip_softreset(struct flexcan_priv *priv)
742{
743 struct flexcan_regs __iomem *regs = priv->regs;
744 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
745
746 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
747 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
748 udelay(10);
749
750 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
751 return -ETIMEDOUT;
752
753 return 0;
754}
755
756static int __flexcan_get_berr_counter(const struct net_device *dev,
757 struct can_berr_counter *bec)
758{
759 const struct flexcan_priv *priv = netdev_priv(dev);
760 struct flexcan_regs __iomem *regs = priv->regs;
761 u32 reg = priv->read(®s->ecr);
762
763 bec->txerr = (reg >> 0) & 0xff;
764 bec->rxerr = (reg >> 8) & 0xff;
765
766 return 0;
767}
768
769static int flexcan_get_berr_counter(const struct net_device *dev,
770 struct can_berr_counter *bec)
771{
772 const struct flexcan_priv *priv = netdev_priv(dev);
773 int err;
774
775 err = pm_runtime_get_sync(priv->dev);
776 if (err < 0) {
777 pm_runtime_put_noidle(priv->dev);
778 return err;
779 }
780
781 err = __flexcan_get_berr_counter(dev, bec);
782
783 pm_runtime_put(priv->dev);
784
785 return err;
786}
787
788static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
789{
790 const struct flexcan_priv *priv = netdev_priv(dev);
791 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
792 u32 can_id;
793 u32 data;
794 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
795 int i;
796
797 if (can_dropped_invalid_skb(dev, skb))
798 return NETDEV_TX_OK;
799
800 netif_stop_queue(dev);
801
802 if (cfd->can_id & CAN_EFF_FLAG) {
803 can_id = cfd->can_id & CAN_EFF_MASK;
804 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
805 } else {
806 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
807 }
808
809 if (cfd->can_id & CAN_RTR_FLAG)
810 ctrl |= FLEXCAN_MB_CNT_RTR;
811
812 if (can_is_canfd_skb(skb)) {
813 ctrl |= FLEXCAN_MB_CNT_EDL;
814
815 if (cfd->flags & CANFD_BRS)
816 ctrl |= FLEXCAN_MB_CNT_BRS;
817 }
818
819 for (i = 0; i < cfd->len; i += sizeof(u32)) {
820 data = be32_to_cpup((__be32 *)&cfd->data[i]);
821 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
822 }
823
824 can_put_echo_skb(skb, dev, 0, 0);
825
826 priv->write(can_id, &priv->tx_mb->can_id);
827 priv->write(ctrl, &priv->tx_mb->can_ctrl);
828
829 /* Errata ERR005829 step8:
830 * Write twice INACTIVE(0x8) code to first MB.
831 */
832 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
833 &priv->tx_mb_reserved->can_ctrl);
834 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
835 &priv->tx_mb_reserved->can_ctrl);
836
837 return NETDEV_TX_OK;
838}
839
840static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
841{
842 struct flexcan_priv *priv = netdev_priv(dev);
843 struct flexcan_regs __iomem *regs = priv->regs;
844 struct sk_buff *skb;
845 struct can_frame *cf;
846 bool rx_errors = false, tx_errors = false;
847 u32 timestamp;
848 int err;
849
850 timestamp = priv->read(®s->timer) << 16;
851
852 skb = alloc_can_err_skb(dev, &cf);
853 if (unlikely(!skb))
854 return;
855
856 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
857
858 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
859 netdev_dbg(dev, "BIT1_ERR irq\n");
860 cf->data[2] |= CAN_ERR_PROT_BIT1;
861 tx_errors = true;
862 }
863 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
864 netdev_dbg(dev, "BIT0_ERR irq\n");
865 cf->data[2] |= CAN_ERR_PROT_BIT0;
866 tx_errors = true;
867 }
868 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
869 netdev_dbg(dev, "ACK_ERR irq\n");
870 cf->can_id |= CAN_ERR_ACK;
871 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
872 tx_errors = true;
873 }
874 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
875 netdev_dbg(dev, "CRC_ERR irq\n");
876 cf->data[2] |= CAN_ERR_PROT_BIT;
877 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
878 rx_errors = true;
879 }
880 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
881 netdev_dbg(dev, "FRM_ERR irq\n");
882 cf->data[2] |= CAN_ERR_PROT_FORM;
883 rx_errors = true;
884 }
885 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
886 netdev_dbg(dev, "STF_ERR irq\n");
887 cf->data[2] |= CAN_ERR_PROT_STUFF;
888 rx_errors = true;
889 }
890
891 priv->can.can_stats.bus_error++;
892 if (rx_errors)
893 dev->stats.rx_errors++;
894 if (tx_errors)
895 dev->stats.tx_errors++;
896
897 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
898 if (err)
899 dev->stats.rx_fifo_errors++;
900}
901
902static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
903{
904 struct flexcan_priv *priv = netdev_priv(dev);
905 struct flexcan_regs __iomem *regs = priv->regs;
906 struct sk_buff *skb;
907 struct can_frame *cf;
908 enum can_state new_state, rx_state, tx_state;
909 int flt;
910 struct can_berr_counter bec;
911 u32 timestamp;
912 int err;
913
914 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
915 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
916 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
917 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
918 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
919 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
920 new_state = max(tx_state, rx_state);
921 } else {
922 __flexcan_get_berr_counter(dev, &bec);
923 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
924 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
925 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
926 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
927 }
928
929 /* state hasn't changed */
930 if (likely(new_state == priv->can.state))
931 return;
932
933 timestamp = priv->read(®s->timer) << 16;
934
935 skb = alloc_can_err_skb(dev, &cf);
936 if (unlikely(!skb))
937 return;
938
939 can_change_state(dev, cf, tx_state, rx_state);
940
941 if (unlikely(new_state == CAN_STATE_BUS_OFF))
942 can_bus_off(dev);
943
944 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
945 if (err)
946 dev->stats.rx_fifo_errors++;
947}
948
949static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
950{
951 u64 reg = 0;
952
953 if (upper_32_bits(mask))
954 reg = (u64)priv->read(addr - 4) << 32;
955 if (lower_32_bits(mask))
956 reg |= priv->read(addr);
957
958 return reg & mask;
959}
960
961static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
962{
963 if (upper_32_bits(val))
964 priv->write(upper_32_bits(val), addr - 4);
965 if (lower_32_bits(val))
966 priv->write(lower_32_bits(val), addr);
967}
968
969static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
970{
971 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
972}
973
974static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
975{
976 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
977}
978
979static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
980{
981 return container_of(offload, struct flexcan_priv, offload);
982}
983
984static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
985 unsigned int n, u32 *timestamp,
986 bool drop)
987{
988 struct flexcan_priv *priv = rx_offload_to_priv(offload);
989 struct flexcan_regs __iomem *regs = priv->regs;
990 struct flexcan_mb __iomem *mb;
991 struct sk_buff *skb;
992 struct canfd_frame *cfd;
993 u32 reg_ctrl, reg_id, reg_iflag1;
994 int i;
995
996 if (unlikely(drop)) {
997 skb = ERR_PTR(-ENOBUFS);
998 goto mark_as_read;
999 }
1000
1001 mb = flexcan_get_mb(priv, n);
1002
1003 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1004 u32 code;
1005
1006 do {
1007 reg_ctrl = priv->read(&mb->can_ctrl);
1008 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
1009
1010 /* is this MB empty? */
1011 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
1012 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
1013 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
1014 return NULL;
1015
1016 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
1017 /* This MB was overrun, we lost data */
1018 offload->dev->stats.rx_over_errors++;
1019 offload->dev->stats.rx_errors++;
1020 }
1021 } else {
1022 reg_iflag1 = priv->read(®s->iflag1);
1023 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
1024 return NULL;
1025
1026 reg_ctrl = priv->read(&mb->can_ctrl);
1027 }
1028
1029 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1030 skb = alloc_canfd_skb(offload->dev, &cfd);
1031 else
1032 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1033 if (unlikely(!skb)) {
1034 skb = ERR_PTR(-ENOMEM);
1035 goto mark_as_read;
1036 }
1037
1038 /* increase timstamp to full 32 bit */
1039 *timestamp = reg_ctrl << 16;
1040
1041 reg_id = priv->read(&mb->can_id);
1042 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1043 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1044 else
1045 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1046
1047 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1048 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1049
1050 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1051 cfd->flags |= CANFD_BRS;
1052 } else {
1053 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1054
1055 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1056 cfd->can_id |= CAN_RTR_FLAG;
1057 }
1058
1059 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1060 cfd->flags |= CANFD_ESI;
1061
1062 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1063 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1064 *(__be32 *)(cfd->data + i) = data;
1065 }
1066
1067 mark_as_read:
1068 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1069 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1070 else
1071 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1072
1073 /* Read the Free Running Timer. It is optional but recommended
1074 * to unlock Mailbox as soon as possible and make it available
1075 * for reception.
1076 */
1077 priv->read(®s->timer);
1078
1079 return skb;
1080}
1081
1082static irqreturn_t flexcan_irq(int irq, void *dev_id)
1083{
1084 struct net_device *dev = dev_id;
1085 struct net_device_stats *stats = &dev->stats;
1086 struct flexcan_priv *priv = netdev_priv(dev);
1087 struct flexcan_regs __iomem *regs = priv->regs;
1088 irqreturn_t handled = IRQ_NONE;
1089 u64 reg_iflag_tx;
1090 u32 reg_esr;
1091 enum can_state last_state = priv->can.state;
1092
1093 /* reception interrupt */
1094 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1095 u64 reg_iflag_rx;
1096 int ret;
1097
1098 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1099 handled = IRQ_HANDLED;
1100 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1101 reg_iflag_rx);
1102 if (!ret)
1103 break;
1104 }
1105 } else {
1106 u32 reg_iflag1;
1107
1108 reg_iflag1 = priv->read(®s->iflag1);
1109 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1110 handled = IRQ_HANDLED;
1111 can_rx_offload_irq_offload_fifo(&priv->offload);
1112 }
1113
1114 /* FIFO overflow interrupt */
1115 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1116 handled = IRQ_HANDLED;
1117 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1118 ®s->iflag1);
1119 dev->stats.rx_over_errors++;
1120 dev->stats.rx_errors++;
1121 }
1122 }
1123
1124 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1125
1126 /* transmission complete interrupt */
1127 if (reg_iflag_tx & priv->tx_mask) {
1128 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1129
1130 handled = IRQ_HANDLED;
1131 stats->tx_bytes +=
1132 can_rx_offload_get_echo_skb(&priv->offload, 0,
1133 reg_ctrl << 16, NULL);
1134 stats->tx_packets++;
1135 can_led_event(dev, CAN_LED_EVENT_TX);
1136
1137 /* after sending a RTR frame MB is in RX mode */
1138 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1139 &priv->tx_mb->can_ctrl);
1140 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1141 netif_wake_queue(dev);
1142 }
1143
1144 reg_esr = priv->read(®s->esr);
1145
1146 /* ACK all bus error, state change and wake IRQ sources */
1147 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1148 handled = IRQ_HANDLED;
1149 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1150 }
1151
1152 /* state change interrupt or broken error state quirk fix is enabled */
1153 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1154 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1155 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1156 flexcan_irq_state(dev, reg_esr);
1157
1158 /* bus error IRQ - handle if bus error reporting is activated */
1159 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1160 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1161 flexcan_irq_bus_err(dev, reg_esr);
1162
1163 /* availability of error interrupt among state transitions in case
1164 * bus error reporting is de-activated and
1165 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1166 * +--------------------------------------------------------------+
1167 * | +----------------------------------------------+ [stopped / |
1168 * | | | sleeping] -+
1169 * +-+-> active <-> warning <-> passive -> bus off -+
1170 * ___________^^^^^^^^^^^^_______________________________
1171 * disabled(1) enabled disabled
1172 *
1173 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1174 */
1175 if ((last_state != priv->can.state) &&
1176 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1177 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1178 switch (priv->can.state) {
1179 case CAN_STATE_ERROR_ACTIVE:
1180 if (priv->devtype_data->quirks &
1181 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1182 flexcan_error_irq_enable(priv);
1183 else
1184 flexcan_error_irq_disable(priv);
1185 break;
1186
1187 case CAN_STATE_ERROR_WARNING:
1188 flexcan_error_irq_enable(priv);
1189 break;
1190
1191 case CAN_STATE_ERROR_PASSIVE:
1192 case CAN_STATE_BUS_OFF:
1193 flexcan_error_irq_disable(priv);
1194 break;
1195
1196 default:
1197 break;
1198 }
1199 }
1200
1201 return handled;
1202}
1203
1204static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1205{
1206 const struct flexcan_priv *priv = netdev_priv(dev);
1207 const struct can_bittiming *bt = &priv->can.bittiming;
1208 struct flexcan_regs __iomem *regs = priv->regs;
1209 u32 reg;
1210
1211 reg = priv->read(®s->ctrl);
1212 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1213 FLEXCAN_CTRL_RJW(0x3) |
1214 FLEXCAN_CTRL_PSEG1(0x7) |
1215 FLEXCAN_CTRL_PSEG2(0x7) |
1216 FLEXCAN_CTRL_PROPSEG(0x7));
1217
1218 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1219 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1220 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1221 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1222 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1223
1224 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1225 priv->write(reg, ®s->ctrl);
1226
1227 /* print chip status */
1228 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1229 priv->read(®s->mcr), priv->read(®s->ctrl));
1230}
1231
1232static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1233{
1234 struct flexcan_priv *priv = netdev_priv(dev);
1235 struct can_bittiming *bt = &priv->can.bittiming;
1236 struct can_bittiming *dbt = &priv->can.data_bittiming;
1237 struct flexcan_regs __iomem *regs = priv->regs;
1238 u32 reg_cbt, reg_fdctrl;
1239
1240 /* CBT */
1241 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1242 * long. The can_calc_bittiming() tries to divide the tseg1
1243 * equally between phase_seg1 and prop_seg, which may not fit
1244 * in CBT register. Therefore, if phase_seg1 is more than
1245 * possible value, increase prop_seg and decrease phase_seg1.
1246 */
1247 if (bt->phase_seg1 > 0x20) {
1248 bt->prop_seg += (bt->phase_seg1 - 0x20);
1249 bt->phase_seg1 = 0x20;
1250 }
1251
1252 reg_cbt = FLEXCAN_CBT_BTF |
1253 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1254 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1255 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1256 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1257 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1258
1259 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1260 priv->write(reg_cbt, ®s->cbt);
1261
1262 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1263 u32 reg_fdcbt, reg_ctrl2;
1264
1265 if (bt->brp != dbt->brp)
1266 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1267 dbt->brp, bt->brp);
1268
1269 /* FDCBT */
1270 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1271 * 5 bit long. The can_calc_bittiming tries to divide
1272 * the tseg1 equally between phase_seg1 and prop_seg,
1273 * which may not fit in FDCBT register. Therefore, if
1274 * phase_seg1 is more than possible value, increase
1275 * prop_seg and decrease phase_seg1
1276 */
1277 if (dbt->phase_seg1 > 0x8) {
1278 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1279 dbt->phase_seg1 = 0x8;
1280 }
1281
1282 reg_fdcbt = priv->read(®s->fdcbt);
1283 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1284 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1285 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1286 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1287 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1288
1289 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1290 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1291 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1292 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1293 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1294
1295 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1296 priv->write(reg_fdcbt, ®s->fdcbt);
1297
1298 /* CTRL2 */
1299 reg_ctrl2 = priv->read(®s->ctrl2);
1300 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1301 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1302 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1303
1304 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1305 priv->write(reg_ctrl2, ®s->ctrl2);
1306 }
1307
1308 /* FDCTRL */
1309 reg_fdctrl = priv->read(®s->fdctrl);
1310 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1311 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1312
1313 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1314 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1315
1316 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1317 /* TDC must be disabled for Loop Back mode */
1318 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1319 } else {
1320 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1321 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1322 ((dbt->phase_seg1 - 1) +
1323 dbt->prop_seg + 2) *
1324 ((dbt->brp - 1 ) + 1));
1325 }
1326 }
1327
1328 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1329 priv->write(reg_fdctrl, ®s->fdctrl);
1330
1331 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1332 __func__,
1333 priv->read(®s->mcr), priv->read(®s->ctrl),
1334 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1335 priv->read(®s->cbt), priv->read(®s->fdcbt));
1336}
1337
1338static void flexcan_set_bittiming(struct net_device *dev)
1339{
1340 const struct flexcan_priv *priv = netdev_priv(dev);
1341 struct flexcan_regs __iomem *regs = priv->regs;
1342 u32 reg;
1343
1344 reg = priv->read(®s->ctrl);
1345 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1346 FLEXCAN_CTRL_LOM);
1347
1348 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1349 reg |= FLEXCAN_CTRL_LPB;
1350 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1351 reg |= FLEXCAN_CTRL_LOM;
1352 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1353 reg |= FLEXCAN_CTRL_SMP;
1354
1355 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1356 priv->write(reg, ®s->ctrl);
1357
1358 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1359 return flexcan_set_bittiming_cbt(dev);
1360 else
1361 return flexcan_set_bittiming_ctrl(dev);
1362}
1363
1364static void flexcan_ram_init(struct net_device *dev)
1365{
1366 struct flexcan_priv *priv = netdev_priv(dev);
1367 struct flexcan_regs __iomem *regs = priv->regs;
1368 u32 reg_ctrl2;
1369
1370 /* 11.8.3.13 Detection and correction of memory errors:
1371 * CTRL2[WRMFRZ] grants write access to all memory positions
1372 * that require initialization, ranging from 0x080 to 0xADF
1373 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1374 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1375 * need to be initialized as well. MCR[RFEN] must not be set
1376 * during memory initialization.
1377 */
1378 reg_ctrl2 = priv->read(®s->ctrl2);
1379 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1380 priv->write(reg_ctrl2, ®s->ctrl2);
1381
1382 memset_io(®s->mb[0][0], 0,
1383 offsetof(struct flexcan_regs, rx_smb1[3]) -
1384 offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1385
1386 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1387 memset_io(®s->tx_smb_fd[0], 0,
1388 offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1389 offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1390
1391 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1392 priv->write(reg_ctrl2, ®s->ctrl2);
1393}
1394
1395static int flexcan_rx_offload_setup(struct net_device *dev)
1396{
1397 struct flexcan_priv *priv = netdev_priv(dev);
1398 int err;
1399
1400 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1401 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1402 else
1403 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1404 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1405 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1406
1407 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1408 priv->tx_mb_reserved =
1409 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1410 else
1411 priv->tx_mb_reserved =
1412 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1413 priv->tx_mb_idx = priv->mb_count - 1;
1414 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1415 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1416
1417 priv->offload.mailbox_read = flexcan_mailbox_read;
1418
1419 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1420 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1421 priv->offload.mb_last = priv->mb_count - 2;
1422
1423 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1424 priv->offload.mb_first);
1425 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1426 } else {
1427 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1428 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1429 err = can_rx_offload_add_fifo(dev, &priv->offload,
1430 FLEXCAN_NAPI_WEIGHT);
1431 }
1432
1433 return err;
1434}
1435
1436static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1437{
1438 const struct flexcan_priv *priv = netdev_priv(dev);
1439 struct flexcan_regs __iomem *regs = priv->regs;
1440 u64 reg_imask;
1441
1442 disable_irq(dev->irq);
1443 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1444 reg_imask = priv->rx_mask | priv->tx_mask;
1445 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1446 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1447 enable_irq(dev->irq);
1448}
1449
1450static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1451{
1452 const struct flexcan_priv *priv = netdev_priv(dev);
1453 struct flexcan_regs __iomem *regs = priv->regs;
1454
1455 priv->write(0, ®s->imask2);
1456 priv->write(0, ®s->imask1);
1457 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1458 ®s->ctrl);
1459}
1460
1461/* flexcan_chip_start
1462 *
1463 * this functions is entered with clocks enabled
1464 *
1465 */
1466static int flexcan_chip_start(struct net_device *dev)
1467{
1468 struct flexcan_priv *priv = netdev_priv(dev);
1469 struct flexcan_regs __iomem *regs = priv->regs;
1470 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1471 int err, i;
1472 struct flexcan_mb __iomem *mb;
1473
1474 /* enable module */
1475 err = flexcan_chip_enable(priv);
1476 if (err)
1477 return err;
1478
1479 /* soft reset */
1480 err = flexcan_chip_softreset(priv);
1481 if (err)
1482 goto out_chip_disable;
1483
1484 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1485 flexcan_ram_init(dev);
1486
1487 flexcan_set_bittiming(dev);
1488
1489 /* set freeze, halt */
1490 err = flexcan_chip_freeze(priv);
1491 if (err)
1492 goto out_chip_disable;
1493
1494 /* MCR
1495 *
1496 * only supervisor access
1497 * enable warning int
1498 * enable individual RX masking
1499 * choose format C
1500 * set max mailbox number
1501 */
1502 reg_mcr = priv->read(®s->mcr);
1503 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1504 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1505 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1506
1507 /* MCR
1508 *
1509 * FIFO:
1510 * - disable for timestamp mode
1511 * - enable for FIFO mode
1512 */
1513 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1514 reg_mcr &= ~FLEXCAN_MCR_FEN;
1515 else
1516 reg_mcr |= FLEXCAN_MCR_FEN;
1517
1518 /* MCR
1519 *
1520 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1521 * asserted because this will impede the self reception
1522 * of a transmitted message. This is not documented in
1523 * earlier versions of flexcan block guide.
1524 *
1525 * Self Reception:
1526 * - enable Self Reception for loopback mode
1527 * (by clearing "Self Reception Disable" bit)
1528 * - disable for normal operation
1529 */
1530 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1531 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1532 else
1533 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1534
1535 /* MCR - CAN-FD */
1536 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1537 reg_mcr |= FLEXCAN_MCR_FDEN;
1538 else
1539 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1540
1541 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1542 priv->write(reg_mcr, ®s->mcr);
1543
1544 /* CTRL
1545 *
1546 * disable timer sync feature
1547 *
1548 * disable auto busoff recovery
1549 * transmit lowest buffer first
1550 *
1551 * enable tx and rx warning interrupt
1552 * enable bus off interrupt
1553 * (== FLEXCAN_CTRL_ERR_STATE)
1554 */
1555 reg_ctrl = priv->read(®s->ctrl);
1556 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1557 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1558 FLEXCAN_CTRL_ERR_STATE;
1559
1560 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1561 * on most Flexcan cores, too. Otherwise we don't get
1562 * any error warning or passive interrupts.
1563 */
1564 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1565 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1566 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1567 else
1568 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1569
1570 /* save for later use */
1571 priv->reg_ctrl_default = reg_ctrl;
1572 /* leave interrupts disabled for now */
1573 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1574 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1575 priv->write(reg_ctrl, ®s->ctrl);
1576
1577 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1578 reg_ctrl2 = priv->read(®s->ctrl2);
1579 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1580 priv->write(reg_ctrl2, ®s->ctrl2);
1581 }
1582
1583 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1584 u32 reg_fdctrl;
1585
1586 reg_fdctrl = priv->read(®s->fdctrl);
1587 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1588 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1589
1590 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1591 reg_fdctrl |=
1592 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1593 FLEXCAN_FDCTRL_MBDSR_64) |
1594 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1595 FLEXCAN_FDCTRL_MBDSR_64);
1596 } else {
1597 reg_fdctrl |=
1598 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1599 FLEXCAN_FDCTRL_MBDSR_8) |
1600 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1601 FLEXCAN_FDCTRL_MBDSR_8);
1602 }
1603
1604 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1605 __func__, reg_fdctrl);
1606 priv->write(reg_fdctrl, ®s->fdctrl);
1607 }
1608
1609 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1610 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1611 mb = flexcan_get_mb(priv, i);
1612 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1613 &mb->can_ctrl);
1614 }
1615 } else {
1616 /* clear and invalidate unused mailboxes first */
1617 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1618 mb = flexcan_get_mb(priv, i);
1619 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1620 &mb->can_ctrl);
1621 }
1622 }
1623
1624 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1625 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1626 &priv->tx_mb_reserved->can_ctrl);
1627
1628 /* mark TX mailbox as INACTIVE */
1629 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1630 &priv->tx_mb->can_ctrl);
1631
1632 /* acceptance mask/acceptance code (accept everything) */
1633 priv->write(0x0, ®s->rxgmask);
1634 priv->write(0x0, ®s->rx14mask);
1635 priv->write(0x0, ®s->rx15mask);
1636
1637 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1638 priv->write(0x0, ®s->rxfgmask);
1639
1640 /* clear acceptance filters */
1641 for (i = 0; i < priv->mb_count; i++)
1642 priv->write(0, ®s->rximr[i]);
1643
1644 /* On Vybrid, disable non-correctable errors interrupt and
1645 * freeze mode. It still can correct the correctable errors
1646 * when HW supports ECC.
1647 *
1648 * This also works around errata e5295 which generates false
1649 * positive memory errors and put the device in freeze mode.
1650 */
1651 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1652 /* Follow the protocol as described in "Detection
1653 * and Correction of Memory Errors" to write to
1654 * MECR register (step 1 - 5)
1655 *
1656 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1657 * 2. set CTRL2[ECRWRE]
1658 */
1659 reg_ctrl2 = priv->read(®s->ctrl2);
1660 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1661 priv->write(reg_ctrl2, ®s->ctrl2);
1662
1663 /* 3. clear MECR[ECRWRDIS] */
1664 reg_mecr = priv->read(®s->mecr);
1665 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1666 priv->write(reg_mecr, ®s->mecr);
1667
1668 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1669 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1670 FLEXCAN_MECR_FANCEI_MSK);
1671 priv->write(reg_mecr, ®s->mecr);
1672
1673 /* 5. after configuration done, lock MECR by either
1674 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1675 */
1676 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1677 priv->write(reg_mecr, ®s->mecr);
1678
1679 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1680 priv->write(reg_ctrl2, ®s->ctrl2);
1681 }
1682
1683 /* synchronize with the can bus */
1684 err = flexcan_chip_unfreeze(priv);
1685 if (err)
1686 goto out_chip_disable;
1687
1688 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1689
1690 /* print chip status */
1691 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1692 priv->read(®s->mcr), priv->read(®s->ctrl));
1693
1694 return 0;
1695
1696 out_chip_disable:
1697 flexcan_chip_disable(priv);
1698 return err;
1699}
1700
1701/* __flexcan_chip_stop
1702 *
1703 * this function is entered with clocks enabled
1704 */
1705static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1706{
1707 struct flexcan_priv *priv = netdev_priv(dev);
1708 int err;
1709
1710 /* freeze + disable module */
1711 err = flexcan_chip_freeze(priv);
1712 if (err && !disable_on_error)
1713 return err;
1714 err = flexcan_chip_disable(priv);
1715 if (err && !disable_on_error)
1716 goto out_chip_unfreeze;
1717
1718 priv->can.state = CAN_STATE_STOPPED;
1719
1720 return 0;
1721
1722 out_chip_unfreeze:
1723 flexcan_chip_unfreeze(priv);
1724
1725 return err;
1726}
1727
1728static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1729{
1730 return __flexcan_chip_stop(dev, true);
1731}
1732
1733static inline int flexcan_chip_stop(struct net_device *dev)
1734{
1735 return __flexcan_chip_stop(dev, false);
1736}
1737
1738static int flexcan_open(struct net_device *dev)
1739{
1740 struct flexcan_priv *priv = netdev_priv(dev);
1741 int err;
1742
1743 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1744 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1745 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1746 return -EINVAL;
1747 }
1748
1749 err = pm_runtime_get_sync(priv->dev);
1750 if (err < 0) {
1751 pm_runtime_put_noidle(priv->dev);
1752 return err;
1753 }
1754
1755 err = open_candev(dev);
1756 if (err)
1757 goto out_runtime_put;
1758
1759 err = flexcan_transceiver_enable(priv);
1760 if (err)
1761 goto out_close;
1762
1763 err = flexcan_rx_offload_setup(dev);
1764 if (err)
1765 goto out_transceiver_disable;
1766
1767 err = flexcan_chip_start(dev);
1768 if (err)
1769 goto out_can_rx_offload_del;
1770
1771 can_rx_offload_enable(&priv->offload);
1772
1773 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1774 if (err)
1775 goto out_can_rx_offload_disable;
1776
1777 flexcan_chip_interrupts_enable(dev);
1778
1779 can_led_event(dev, CAN_LED_EVENT_OPEN);
1780
1781 netif_start_queue(dev);
1782
1783 return 0;
1784
1785 out_can_rx_offload_disable:
1786 can_rx_offload_disable(&priv->offload);
1787 flexcan_chip_stop(dev);
1788 out_can_rx_offload_del:
1789 can_rx_offload_del(&priv->offload);
1790 out_transceiver_disable:
1791 flexcan_transceiver_disable(priv);
1792 out_close:
1793 close_candev(dev);
1794 out_runtime_put:
1795 pm_runtime_put(priv->dev);
1796
1797 return err;
1798}
1799
1800static int flexcan_close(struct net_device *dev)
1801{
1802 struct flexcan_priv *priv = netdev_priv(dev);
1803
1804 netif_stop_queue(dev);
1805 flexcan_chip_interrupts_disable(dev);
1806 free_irq(dev->irq, dev);
1807 can_rx_offload_disable(&priv->offload);
1808 flexcan_chip_stop_disable_on_error(dev);
1809
1810 can_rx_offload_del(&priv->offload);
1811 flexcan_transceiver_disable(priv);
1812 close_candev(dev);
1813
1814 pm_runtime_put(priv->dev);
1815
1816 can_led_event(dev, CAN_LED_EVENT_STOP);
1817
1818 return 0;
1819}
1820
1821static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1822{
1823 int err;
1824
1825 switch (mode) {
1826 case CAN_MODE_START:
1827 err = flexcan_chip_start(dev);
1828 if (err)
1829 return err;
1830
1831 flexcan_chip_interrupts_enable(dev);
1832
1833 netif_wake_queue(dev);
1834 break;
1835
1836 default:
1837 return -EOPNOTSUPP;
1838 }
1839
1840 return 0;
1841}
1842
1843static const struct net_device_ops flexcan_netdev_ops = {
1844 .ndo_open = flexcan_open,
1845 .ndo_stop = flexcan_close,
1846 .ndo_start_xmit = flexcan_start_xmit,
1847 .ndo_change_mtu = can_change_mtu,
1848};
1849
1850static int register_flexcandev(struct net_device *dev)
1851{
1852 struct flexcan_priv *priv = netdev_priv(dev);
1853 struct flexcan_regs __iomem *regs = priv->regs;
1854 u32 reg, err;
1855
1856 err = flexcan_clks_enable(priv);
1857 if (err)
1858 return err;
1859
1860 /* select "bus clock", chip must be disabled */
1861 err = flexcan_chip_disable(priv);
1862 if (err)
1863 goto out_clks_disable;
1864
1865 reg = priv->read(®s->ctrl);
1866 if (priv->clk_src)
1867 reg |= FLEXCAN_CTRL_CLK_SRC;
1868 else
1869 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1870 priv->write(reg, ®s->ctrl);
1871
1872 err = flexcan_chip_enable(priv);
1873 if (err)
1874 goto out_chip_disable;
1875
1876 /* set freeze, halt */
1877 err = flexcan_chip_freeze(priv);
1878 if (err)
1879 goto out_chip_disable;
1880
1881 /* activate FIFO, restrict register access */
1882 reg = priv->read(®s->mcr);
1883 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1884 priv->write(reg, ®s->mcr);
1885
1886 /* Currently we only support newer versions of this core
1887 * featuring a RX hardware FIFO (although this driver doesn't
1888 * make use of it on some cores). Older cores, found on some
1889 * Coldfire derivates are not tested.
1890 */
1891 reg = priv->read(®s->mcr);
1892 if (!(reg & FLEXCAN_MCR_FEN)) {
1893 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1894 err = -ENODEV;
1895 goto out_chip_disable;
1896 }
1897
1898 err = register_candev(dev);
1899 if (err)
1900 goto out_chip_disable;
1901
1902 /* Disable core and let pm_runtime_put() disable the clocks.
1903 * If CONFIG_PM is not enabled, the clocks will stay powered.
1904 */
1905 flexcan_chip_disable(priv);
1906 pm_runtime_put(priv->dev);
1907
1908 return 0;
1909
1910 out_chip_disable:
1911 flexcan_chip_disable(priv);
1912 out_clks_disable:
1913 flexcan_clks_disable(priv);
1914 return err;
1915}
1916
1917static void unregister_flexcandev(struct net_device *dev)
1918{
1919 unregister_candev(dev);
1920}
1921
1922static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1923{
1924 struct net_device *dev = platform_get_drvdata(pdev);
1925 struct device_node *np = pdev->dev.of_node;
1926 struct device_node *gpr_np;
1927 struct flexcan_priv *priv;
1928 phandle phandle;
1929 u32 out_val[3];
1930 int ret;
1931
1932 if (!np)
1933 return -EINVAL;
1934
1935 /* stop mode property format is:
1936 * <&gpr req_gpr req_bit>.
1937 */
1938 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1939 ARRAY_SIZE(out_val));
1940 if (ret) {
1941 dev_dbg(&pdev->dev, "no stop-mode property\n");
1942 return ret;
1943 }
1944 phandle = *out_val;
1945
1946 gpr_np = of_find_node_by_phandle(phandle);
1947 if (!gpr_np) {
1948 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1949 return -ENODEV;
1950 }
1951
1952 priv = netdev_priv(dev);
1953 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1954 if (IS_ERR(priv->stm.gpr)) {
1955 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1956 ret = PTR_ERR(priv->stm.gpr);
1957 goto out_put_node;
1958 }
1959
1960 priv->stm.req_gpr = out_val[1];
1961 priv->stm.req_bit = out_val[2];
1962
1963 dev_dbg(&pdev->dev,
1964 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1965 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1966
1967 return 0;
1968
1969out_put_node:
1970 of_node_put(gpr_np);
1971 return ret;
1972}
1973
1974static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1975{
1976 struct net_device *dev = platform_get_drvdata(pdev);
1977 struct flexcan_priv *priv;
1978 u8 scu_idx;
1979 int ret;
1980
1981 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1982 if (ret < 0) {
1983 dev_dbg(&pdev->dev, "failed to get scu index\n");
1984 return ret;
1985 }
1986
1987 priv = netdev_priv(dev);
1988 priv->scu_idx = scu_idx;
1989
1990 /* this function could be deferred probe, return -EPROBE_DEFER */
1991 return imx_scu_get_handle(&priv->sc_ipc_handle);
1992}
1993
1994/* flexcan_setup_stop_mode - Setup stop mode for wakeup
1995 *
1996 * Return: = 0 setup stop mode successfully or doesn't support this feature
1997 * < 0 fail to setup stop mode (could be deferred probe)
1998 */
1999static int flexcan_setup_stop_mode(struct platform_device *pdev)
2000{
2001 struct net_device *dev = platform_get_drvdata(pdev);
2002 struct flexcan_priv *priv;
2003 int ret;
2004
2005 priv = netdev_priv(dev);
2006
2007 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
2008 ret = flexcan_setup_stop_mode_scfw(pdev);
2009 else if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
2010 ret = flexcan_setup_stop_mode_gpr(pdev);
2011 else
2012 /* return 0 directly if doesn't support stop mode feature */
2013 return 0;
2014
2015 if (ret)
2016 return ret;
2017
2018 device_set_wakeup_capable(&pdev->dev, true);
2019
2020 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2021 device_set_wakeup_enable(&pdev->dev, true);
2022
2023 return 0;
2024}
2025
2026static const struct of_device_id flexcan_of_match[] = {
2027 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2028 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2029 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2030 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2031 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2032 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2033 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2034 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2035 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2036 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2037 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2038 { /* sentinel */ },
2039};
2040MODULE_DEVICE_TABLE(of, flexcan_of_match);
2041
2042static int flexcan_probe(struct platform_device *pdev)
2043{
2044 const struct flexcan_devtype_data *devtype_data;
2045 struct net_device *dev;
2046 struct flexcan_priv *priv;
2047 struct regulator *reg_xceiver;
2048 struct clk *clk_ipg = NULL, *clk_per = NULL;
2049 struct flexcan_regs __iomem *regs;
2050 int err, irq;
2051 u8 clk_src = 1;
2052 u32 clock_freq = 0;
2053
2054 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2055 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2056 return -EPROBE_DEFER;
2057 else if (PTR_ERR(reg_xceiver) == -ENODEV)
2058 reg_xceiver = NULL;
2059 else if (IS_ERR(reg_xceiver))
2060 return PTR_ERR(reg_xceiver);
2061
2062 if (pdev->dev.of_node) {
2063 of_property_read_u32(pdev->dev.of_node,
2064 "clock-frequency", &clock_freq);
2065 of_property_read_u8(pdev->dev.of_node,
2066 "fsl,clk-source", &clk_src);
2067 }
2068
2069 if (!clock_freq) {
2070 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2071 if (IS_ERR(clk_ipg)) {
2072 dev_err(&pdev->dev, "no ipg clock defined\n");
2073 return PTR_ERR(clk_ipg);
2074 }
2075
2076 clk_per = devm_clk_get(&pdev->dev, "per");
2077 if (IS_ERR(clk_per)) {
2078 dev_err(&pdev->dev, "no per clock defined\n");
2079 return PTR_ERR(clk_per);
2080 }
2081 clock_freq = clk_get_rate(clk_per);
2082 }
2083
2084 irq = platform_get_irq(pdev, 0);
2085 if (irq <= 0)
2086 return -ENODEV;
2087
2088 regs = devm_platform_ioremap_resource(pdev, 0);
2089 if (IS_ERR(regs))
2090 return PTR_ERR(regs);
2091
2092 devtype_data = of_device_get_match_data(&pdev->dev);
2093
2094 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2095 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
2096 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
2097 return -EINVAL;
2098 }
2099
2100 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2101 if (!dev)
2102 return -ENOMEM;
2103
2104 platform_set_drvdata(pdev, dev);
2105 SET_NETDEV_DEV(dev, &pdev->dev);
2106
2107 dev->netdev_ops = &flexcan_netdev_ops;
2108 dev->irq = irq;
2109 dev->flags |= IFF_ECHO;
2110
2111 priv = netdev_priv(dev);
2112
2113 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2114 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2115 priv->read = flexcan_read_be;
2116 priv->write = flexcan_write_be;
2117 } else {
2118 priv->read = flexcan_read_le;
2119 priv->write = flexcan_write_le;
2120 }
2121
2122 priv->dev = &pdev->dev;
2123 priv->can.clock.freq = clock_freq;
2124 priv->can.do_set_mode = flexcan_set_mode;
2125 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2126 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2127 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2128 CAN_CTRLMODE_BERR_REPORTING;
2129 priv->regs = regs;
2130 priv->clk_ipg = clk_ipg;
2131 priv->clk_per = clk_per;
2132 priv->clk_src = clk_src;
2133 priv->devtype_data = devtype_data;
2134 priv->reg_xceiver = reg_xceiver;
2135
2136 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2137 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2138 CAN_CTRLMODE_FD_NON_ISO;
2139 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2140 priv->can.data_bittiming_const =
2141 &flexcan_fd_data_bittiming_const;
2142 } else {
2143 priv->can.bittiming_const = &flexcan_bittiming_const;
2144 }
2145
2146 pm_runtime_get_noresume(&pdev->dev);
2147 pm_runtime_set_active(&pdev->dev);
2148 pm_runtime_enable(&pdev->dev);
2149
2150 err = register_flexcandev(dev);
2151 if (err) {
2152 dev_err(&pdev->dev, "registering netdev failed\n");
2153 goto failed_register;
2154 }
2155
2156 err = flexcan_setup_stop_mode(pdev);
2157 if (err < 0) {
2158 if (err != -EPROBE_DEFER)
2159 dev_err(&pdev->dev, "setup stop mode failed\n");
2160 goto failed_setup_stop_mode;
2161 }
2162
2163 of_can_transceiver(dev);
2164 devm_can_led_init(dev);
2165
2166 return 0;
2167
2168 failed_setup_stop_mode:
2169 unregister_flexcandev(dev);
2170 failed_register:
2171 pm_runtime_put_noidle(&pdev->dev);
2172 pm_runtime_disable(&pdev->dev);
2173 free_candev(dev);
2174 return err;
2175}
2176
2177static int flexcan_remove(struct platform_device *pdev)
2178{
2179 struct net_device *dev = platform_get_drvdata(pdev);
2180
2181 device_set_wakeup_enable(&pdev->dev, false);
2182 device_set_wakeup_capable(&pdev->dev, false);
2183 unregister_flexcandev(dev);
2184 pm_runtime_disable(&pdev->dev);
2185 free_candev(dev);
2186
2187 return 0;
2188}
2189
2190static int __maybe_unused flexcan_suspend(struct device *device)
2191{
2192 struct net_device *dev = dev_get_drvdata(device);
2193 struct flexcan_priv *priv = netdev_priv(dev);
2194 int err;
2195
2196 if (netif_running(dev)) {
2197 /* if wakeup is enabled, enter stop mode
2198 * else enter disabled mode.
2199 */
2200 if (device_may_wakeup(device)) {
2201 enable_irq_wake(dev->irq);
2202 err = flexcan_enter_stop_mode(priv);
2203 if (err)
2204 return err;
2205 } else {
2206 err = flexcan_chip_stop(dev);
2207 if (err)
2208 return err;
2209
2210 flexcan_chip_interrupts_disable(dev);
2211
2212 err = pinctrl_pm_select_sleep_state(device);
2213 if (err)
2214 return err;
2215 }
2216 netif_stop_queue(dev);
2217 netif_device_detach(dev);
2218 }
2219 priv->can.state = CAN_STATE_SLEEPING;
2220
2221 return 0;
2222}
2223
2224static int __maybe_unused flexcan_resume(struct device *device)
2225{
2226 struct net_device *dev = dev_get_drvdata(device);
2227 struct flexcan_priv *priv = netdev_priv(dev);
2228 int err;
2229
2230 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2231 if (netif_running(dev)) {
2232 netif_device_attach(dev);
2233 netif_start_queue(dev);
2234 if (device_may_wakeup(device)) {
2235 disable_irq_wake(dev->irq);
2236 err = flexcan_exit_stop_mode(priv);
2237 if (err)
2238 return err;
2239 } else {
2240 err = pinctrl_pm_select_default_state(device);
2241 if (err)
2242 return err;
2243
2244 err = flexcan_chip_start(dev);
2245 if (err)
2246 return err;
2247
2248 flexcan_chip_interrupts_enable(dev);
2249 }
2250 }
2251
2252 return 0;
2253}
2254
2255static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2256{
2257 struct net_device *dev = dev_get_drvdata(device);
2258 struct flexcan_priv *priv = netdev_priv(dev);
2259
2260 flexcan_clks_disable(priv);
2261
2262 return 0;
2263}
2264
2265static int __maybe_unused flexcan_runtime_resume(struct device *device)
2266{
2267 struct net_device *dev = dev_get_drvdata(device);
2268 struct flexcan_priv *priv = netdev_priv(dev);
2269
2270 return flexcan_clks_enable(priv);
2271}
2272
2273static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2274{
2275 struct net_device *dev = dev_get_drvdata(device);
2276 struct flexcan_priv *priv = netdev_priv(dev);
2277
2278 if (netif_running(dev)) {
2279 int err;
2280
2281 if (device_may_wakeup(device))
2282 flexcan_enable_wakeup_irq(priv, true);
2283
2284 err = pm_runtime_force_suspend(device);
2285 if (err)
2286 return err;
2287 }
2288
2289 return 0;
2290}
2291
2292static int __maybe_unused flexcan_noirq_resume(struct device *device)
2293{
2294 struct net_device *dev = dev_get_drvdata(device);
2295 struct flexcan_priv *priv = netdev_priv(dev);
2296
2297 if (netif_running(dev)) {
2298 int err;
2299
2300 err = pm_runtime_force_resume(device);
2301 if (err)
2302 return err;
2303
2304 if (device_may_wakeup(device))
2305 flexcan_enable_wakeup_irq(priv, false);
2306 }
2307
2308 return 0;
2309}
2310
2311static const struct dev_pm_ops flexcan_pm_ops = {
2312 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2313 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2314 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2315};
2316
2317static struct platform_driver flexcan_driver = {
2318 .driver = {
2319 .name = DRV_NAME,
2320 .pm = &flexcan_pm_ops,
2321 .of_match_table = flexcan_of_match,
2322 },
2323 .probe = flexcan_probe,
2324 .remove = flexcan_remove,
2325};
2326
2327module_platform_driver(flexcan_driver);
2328
2329MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2330 "Marc Kleine-Budde <kernel@pengutronix.de>");
2331MODULE_LICENSE("GPL v2");
2332MODULE_DESCRIPTION("CAN port driver for flexcan based chip");