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1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/led.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/platform_device.h>
39#include <linux/regulator/consumer.h>
40
41#define DRV_NAME "flexcan"
42
43/* 8 for RX fifo and 2 error handling */
44#define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46/* FLEXCAN module configuration register (CANMCR) bits */
47#define FLEXCAN_MCR_MDIS BIT(31)
48#define FLEXCAN_MCR_FRZ BIT(30)
49#define FLEXCAN_MCR_FEN BIT(29)
50#define FLEXCAN_MCR_HALT BIT(28)
51#define FLEXCAN_MCR_NOT_RDY BIT(27)
52#define FLEXCAN_MCR_WAK_MSK BIT(26)
53#define FLEXCAN_MCR_SOFTRST BIT(25)
54#define FLEXCAN_MCR_FRZ_ACK BIT(24)
55#define FLEXCAN_MCR_SUPV BIT(23)
56#define FLEXCAN_MCR_SLF_WAK BIT(22)
57#define FLEXCAN_MCR_WRN_EN BIT(21)
58#define FLEXCAN_MCR_LPM_ACK BIT(20)
59#define FLEXCAN_MCR_WAK_SRC BIT(19)
60#define FLEXCAN_MCR_DOZE BIT(18)
61#define FLEXCAN_MCR_SRX_DIS BIT(17)
62#define FLEXCAN_MCR_BCC BIT(16)
63#define FLEXCAN_MCR_LPRIO_EN BIT(13)
64#define FLEXCAN_MCR_AEN BIT(12)
65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
66#define FLEXCAN_MCR_IDAM_A (0 << 8)
67#define FLEXCAN_MCR_IDAM_B (1 << 8)
68#define FLEXCAN_MCR_IDAM_C (2 << 8)
69#define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71/* FLEXCAN control register (CANCTRL) bits */
72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77#define FLEXCAN_CTRL_ERR_MSK BIT(14)
78#define FLEXCAN_CTRL_CLK_SRC BIT(13)
79#define FLEXCAN_CTRL_LPB BIT(12)
80#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82#define FLEXCAN_CTRL_SMP BIT(7)
83#define FLEXCAN_CTRL_BOFF_REC BIT(6)
84#define FLEXCAN_CTRL_TSYN BIT(5)
85#define FLEXCAN_CTRL_LBUF BIT(4)
86#define FLEXCAN_CTRL_LOM BIT(3)
87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89#define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92#define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95/* FLEXCAN error and status register (ESR) bits */
96#define FLEXCAN_ESR_TWRN_INT BIT(17)
97#define FLEXCAN_ESR_RWRN_INT BIT(16)
98#define FLEXCAN_ESR_BIT1_ERR BIT(15)
99#define FLEXCAN_ESR_BIT0_ERR BIT(14)
100#define FLEXCAN_ESR_ACK_ERR BIT(13)
101#define FLEXCAN_ESR_CRC_ERR BIT(12)
102#define FLEXCAN_ESR_FRM_ERR BIT(11)
103#define FLEXCAN_ESR_STF_ERR BIT(10)
104#define FLEXCAN_ESR_TX_WRN BIT(9)
105#define FLEXCAN_ESR_RX_WRN BIT(8)
106#define FLEXCAN_ESR_IDLE BIT(7)
107#define FLEXCAN_ESR_TXRX BIT(6)
108#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_BOFF_INT BIT(2)
113#define FLEXCAN_ESR_ERR_INT BIT(1)
114#define FLEXCAN_ESR_WAK_INT BIT(0)
115#define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119#define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121#define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
123#define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
126
127/* FLEXCAN interrupt flag register (IFLAG) bits */
128#define FLEXCAN_TX_BUF_ID 8
129#define FLEXCAN_IFLAG_BUF(x) BIT(x)
130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133#define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137/* FLEXCAN message buffers */
138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139#define FLEXCAN_MB_CNT_SRR BIT(22)
140#define FLEXCAN_MB_CNT_IDE BIT(21)
141#define FLEXCAN_MB_CNT_RTR BIT(20)
142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144
145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146
147#define FLEXCAN_TIMEOUT_US (50)
148
149/*
150 * FLEXCAN hardware feature flags
151 *
152 * Below is some version info we got:
153 * SOC Version IP-Version Glitch- [TR]WRN_INT
154 * Filter? connected?
155 * MX25 FlexCAN2 03.00.00.00 no no
156 * MX28 FlexCAN2 03.00.04.00 yes yes
157 * MX35 FlexCAN2 03.00.00.00 no no
158 * MX53 FlexCAN2 03.00.00.00 yes no
159 * MX6s FlexCAN3 10.00.12.00 yes yes
160 *
161 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
162 */
163#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
164#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
165
166/* Structure of the message buffer */
167struct flexcan_mb {
168 u32 can_ctrl;
169 u32 can_id;
170 u32 data[2];
171};
172
173/* Structure of the hardware registers */
174struct flexcan_regs {
175 u32 mcr; /* 0x00 */
176 u32 ctrl; /* 0x04 */
177 u32 timer; /* 0x08 */
178 u32 _reserved1; /* 0x0c */
179 u32 rxgmask; /* 0x10 */
180 u32 rx14mask; /* 0x14 */
181 u32 rx15mask; /* 0x18 */
182 u32 ecr; /* 0x1c */
183 u32 esr; /* 0x20 */
184 u32 imask2; /* 0x24 */
185 u32 imask1; /* 0x28 */
186 u32 iflag2; /* 0x2c */
187 u32 iflag1; /* 0x30 */
188 u32 crl2; /* 0x34 */
189 u32 esr2; /* 0x38 */
190 u32 imeur; /* 0x3c */
191 u32 lrfr; /* 0x40 */
192 u32 crcr; /* 0x44 */
193 u32 rxfgmask; /* 0x48 */
194 u32 rxfir; /* 0x4c */
195 u32 _reserved3[12];
196 struct flexcan_mb cantxfg[64];
197};
198
199struct flexcan_devtype_data {
200 u32 features; /* hardware controller features */
201};
202
203struct flexcan_priv {
204 struct can_priv can;
205 struct net_device *dev;
206 struct napi_struct napi;
207
208 void __iomem *base;
209 u32 reg_esr;
210 u32 reg_ctrl_default;
211
212 struct clk *clk_ipg;
213 struct clk *clk_per;
214 struct flexcan_platform_data *pdata;
215 const struct flexcan_devtype_data *devtype_data;
216 struct regulator *reg_xceiver;
217};
218
219static struct flexcan_devtype_data fsl_p1010_devtype_data = {
220 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
221};
222static struct flexcan_devtype_data fsl_imx28_devtype_data;
223static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
224 .features = FLEXCAN_HAS_V10_FEATURES,
225};
226
227static const struct can_bittiming_const flexcan_bittiming_const = {
228 .name = DRV_NAME,
229 .tseg1_min = 4,
230 .tseg1_max = 16,
231 .tseg2_min = 2,
232 .tseg2_max = 8,
233 .sjw_max = 4,
234 .brp_min = 1,
235 .brp_max = 256,
236 .brp_inc = 1,
237};
238
239/*
240 * Abstract off the read/write for arm versus ppc. This
241 * assumes that PPC uses big-endian registers and everything
242 * else uses little-endian registers, independent of CPU
243 * endianess.
244 */
245#if defined(CONFIG_PPC)
246static inline u32 flexcan_read(void __iomem *addr)
247{
248 return in_be32(addr);
249}
250
251static inline void flexcan_write(u32 val, void __iomem *addr)
252{
253 out_be32(addr, val);
254}
255#else
256static inline u32 flexcan_read(void __iomem *addr)
257{
258 return readl(addr);
259}
260
261static inline void flexcan_write(u32 val, void __iomem *addr)
262{
263 writel(val, addr);
264}
265#endif
266
267static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
268{
269 if (!priv->reg_xceiver)
270 return 0;
271
272 return regulator_enable(priv->reg_xceiver);
273}
274
275static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
276{
277 if (!priv->reg_xceiver)
278 return 0;
279
280 return regulator_disable(priv->reg_xceiver);
281}
282
283static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
284 u32 reg_esr)
285{
286 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
287 (reg_esr & FLEXCAN_ESR_ERR_BUS);
288}
289
290static int flexcan_chip_enable(struct flexcan_priv *priv)
291{
292 struct flexcan_regs __iomem *regs = priv->base;
293 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
294 u32 reg;
295
296 reg = flexcan_read(®s->mcr);
297 reg &= ~FLEXCAN_MCR_MDIS;
298 flexcan_write(reg, ®s->mcr);
299
300 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
301 usleep_range(10, 20);
302
303 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
304 return -ETIMEDOUT;
305
306 return 0;
307}
308
309static int flexcan_chip_disable(struct flexcan_priv *priv)
310{
311 struct flexcan_regs __iomem *regs = priv->base;
312 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
313 u32 reg;
314
315 reg = flexcan_read(®s->mcr);
316 reg |= FLEXCAN_MCR_MDIS;
317 flexcan_write(reg, ®s->mcr);
318
319 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
320 usleep_range(10, 20);
321
322 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
323 return -ETIMEDOUT;
324
325 return 0;
326}
327
328static int flexcan_chip_freeze(struct flexcan_priv *priv)
329{
330 struct flexcan_regs __iomem *regs = priv->base;
331 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
332 u32 reg;
333
334 reg = flexcan_read(®s->mcr);
335 reg |= FLEXCAN_MCR_HALT;
336 flexcan_write(reg, ®s->mcr);
337
338 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
339 usleep_range(100, 200);
340
341 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
342 return -ETIMEDOUT;
343
344 return 0;
345}
346
347static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
348{
349 struct flexcan_regs __iomem *regs = priv->base;
350 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
351 u32 reg;
352
353 reg = flexcan_read(®s->mcr);
354 reg &= ~FLEXCAN_MCR_HALT;
355 flexcan_write(reg, ®s->mcr);
356
357 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
358 usleep_range(10, 20);
359
360 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
361 return -ETIMEDOUT;
362
363 return 0;
364}
365
366static int flexcan_chip_softreset(struct flexcan_priv *priv)
367{
368 struct flexcan_regs __iomem *regs = priv->base;
369 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
370
371 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
372 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
373 usleep_range(10, 20);
374
375 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
376 return -ETIMEDOUT;
377
378 return 0;
379}
380
381static int flexcan_get_berr_counter(const struct net_device *dev,
382 struct can_berr_counter *bec)
383{
384 const struct flexcan_priv *priv = netdev_priv(dev);
385 struct flexcan_regs __iomem *regs = priv->base;
386 u32 reg = flexcan_read(®s->ecr);
387
388 bec->txerr = (reg >> 0) & 0xff;
389 bec->rxerr = (reg >> 8) & 0xff;
390
391 return 0;
392}
393
394static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
395{
396 const struct flexcan_priv *priv = netdev_priv(dev);
397 struct flexcan_regs __iomem *regs = priv->base;
398 struct can_frame *cf = (struct can_frame *)skb->data;
399 u32 can_id;
400 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
401
402 if (can_dropped_invalid_skb(dev, skb))
403 return NETDEV_TX_OK;
404
405 netif_stop_queue(dev);
406
407 if (cf->can_id & CAN_EFF_FLAG) {
408 can_id = cf->can_id & CAN_EFF_MASK;
409 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
410 } else {
411 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
412 }
413
414 if (cf->can_id & CAN_RTR_FLAG)
415 ctrl |= FLEXCAN_MB_CNT_RTR;
416
417 if (cf->can_dlc > 0) {
418 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
419 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
420 }
421 if (cf->can_dlc > 3) {
422 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
423 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
424 }
425
426 can_put_echo_skb(skb, dev, 0);
427
428 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
429 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
430
431 return NETDEV_TX_OK;
432}
433
434static void do_bus_err(struct net_device *dev,
435 struct can_frame *cf, u32 reg_esr)
436{
437 struct flexcan_priv *priv = netdev_priv(dev);
438 int rx_errors = 0, tx_errors = 0;
439
440 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
441
442 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
443 netdev_dbg(dev, "BIT1_ERR irq\n");
444 cf->data[2] |= CAN_ERR_PROT_BIT1;
445 tx_errors = 1;
446 }
447 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
448 netdev_dbg(dev, "BIT0_ERR irq\n");
449 cf->data[2] |= CAN_ERR_PROT_BIT0;
450 tx_errors = 1;
451 }
452 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
453 netdev_dbg(dev, "ACK_ERR irq\n");
454 cf->can_id |= CAN_ERR_ACK;
455 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
456 tx_errors = 1;
457 }
458 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
459 netdev_dbg(dev, "CRC_ERR irq\n");
460 cf->data[2] |= CAN_ERR_PROT_BIT;
461 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
462 rx_errors = 1;
463 }
464 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
465 netdev_dbg(dev, "FRM_ERR irq\n");
466 cf->data[2] |= CAN_ERR_PROT_FORM;
467 rx_errors = 1;
468 }
469 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
470 netdev_dbg(dev, "STF_ERR irq\n");
471 cf->data[2] |= CAN_ERR_PROT_STUFF;
472 rx_errors = 1;
473 }
474
475 priv->can.can_stats.bus_error++;
476 if (rx_errors)
477 dev->stats.rx_errors++;
478 if (tx_errors)
479 dev->stats.tx_errors++;
480}
481
482static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
483{
484 struct sk_buff *skb;
485 struct can_frame *cf;
486
487 skb = alloc_can_err_skb(dev, &cf);
488 if (unlikely(!skb))
489 return 0;
490
491 do_bus_err(dev, cf, reg_esr);
492 netif_receive_skb(skb);
493
494 dev->stats.rx_packets++;
495 dev->stats.rx_bytes += cf->can_dlc;
496
497 return 1;
498}
499
500static void do_state(struct net_device *dev,
501 struct can_frame *cf, enum can_state new_state)
502{
503 struct flexcan_priv *priv = netdev_priv(dev);
504 struct can_berr_counter bec;
505
506 flexcan_get_berr_counter(dev, &bec);
507
508 switch (priv->can.state) {
509 case CAN_STATE_ERROR_ACTIVE:
510 /*
511 * from: ERROR_ACTIVE
512 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
513 * => : there was a warning int
514 */
515 if (new_state >= CAN_STATE_ERROR_WARNING &&
516 new_state <= CAN_STATE_BUS_OFF) {
517 netdev_dbg(dev, "Error Warning IRQ\n");
518 priv->can.can_stats.error_warning++;
519
520 cf->can_id |= CAN_ERR_CRTL;
521 cf->data[1] = (bec.txerr > bec.rxerr) ?
522 CAN_ERR_CRTL_TX_WARNING :
523 CAN_ERR_CRTL_RX_WARNING;
524 }
525 case CAN_STATE_ERROR_WARNING: /* fallthrough */
526 /*
527 * from: ERROR_ACTIVE, ERROR_WARNING
528 * to : ERROR_PASSIVE, BUS_OFF
529 * => : error passive int
530 */
531 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
532 new_state <= CAN_STATE_BUS_OFF) {
533 netdev_dbg(dev, "Error Passive IRQ\n");
534 priv->can.can_stats.error_passive++;
535
536 cf->can_id |= CAN_ERR_CRTL;
537 cf->data[1] = (bec.txerr > bec.rxerr) ?
538 CAN_ERR_CRTL_TX_PASSIVE :
539 CAN_ERR_CRTL_RX_PASSIVE;
540 }
541 break;
542 case CAN_STATE_BUS_OFF:
543 netdev_err(dev, "BUG! "
544 "hardware recovered automatically from BUS_OFF\n");
545 break;
546 default:
547 break;
548 }
549
550 /* process state changes depending on the new state */
551 switch (new_state) {
552 case CAN_STATE_ERROR_ACTIVE:
553 netdev_dbg(dev, "Error Active\n");
554 cf->can_id |= CAN_ERR_PROT;
555 cf->data[2] = CAN_ERR_PROT_ACTIVE;
556 break;
557 case CAN_STATE_BUS_OFF:
558 cf->can_id |= CAN_ERR_BUSOFF;
559 can_bus_off(dev);
560 break;
561 default:
562 break;
563 }
564}
565
566static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
567{
568 struct flexcan_priv *priv = netdev_priv(dev);
569 struct sk_buff *skb;
570 struct can_frame *cf;
571 enum can_state new_state;
572 int flt;
573
574 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
575 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
576 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
577 FLEXCAN_ESR_RX_WRN))))
578 new_state = CAN_STATE_ERROR_ACTIVE;
579 else
580 new_state = CAN_STATE_ERROR_WARNING;
581 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
582 new_state = CAN_STATE_ERROR_PASSIVE;
583 else
584 new_state = CAN_STATE_BUS_OFF;
585
586 /* state hasn't changed */
587 if (likely(new_state == priv->can.state))
588 return 0;
589
590 skb = alloc_can_err_skb(dev, &cf);
591 if (unlikely(!skb))
592 return 0;
593
594 do_state(dev, cf, new_state);
595 priv->can.state = new_state;
596 netif_receive_skb(skb);
597
598 dev->stats.rx_packets++;
599 dev->stats.rx_bytes += cf->can_dlc;
600
601 return 1;
602}
603
604static void flexcan_read_fifo(const struct net_device *dev,
605 struct can_frame *cf)
606{
607 const struct flexcan_priv *priv = netdev_priv(dev);
608 struct flexcan_regs __iomem *regs = priv->base;
609 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
610 u32 reg_ctrl, reg_id;
611
612 reg_ctrl = flexcan_read(&mb->can_ctrl);
613 reg_id = flexcan_read(&mb->can_id);
614 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
615 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
616 else
617 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
618
619 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
620 cf->can_id |= CAN_RTR_FLAG;
621 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
622
623 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
624 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
625
626 /* mark as read */
627 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
628 flexcan_read(®s->timer);
629}
630
631static int flexcan_read_frame(struct net_device *dev)
632{
633 struct net_device_stats *stats = &dev->stats;
634 struct can_frame *cf;
635 struct sk_buff *skb;
636
637 skb = alloc_can_skb(dev, &cf);
638 if (unlikely(!skb)) {
639 stats->rx_dropped++;
640 return 0;
641 }
642
643 flexcan_read_fifo(dev, cf);
644 netif_receive_skb(skb);
645
646 stats->rx_packets++;
647 stats->rx_bytes += cf->can_dlc;
648
649 can_led_event(dev, CAN_LED_EVENT_RX);
650
651 return 1;
652}
653
654static int flexcan_poll(struct napi_struct *napi, int quota)
655{
656 struct net_device *dev = napi->dev;
657 const struct flexcan_priv *priv = netdev_priv(dev);
658 struct flexcan_regs __iomem *regs = priv->base;
659 u32 reg_iflag1, reg_esr;
660 int work_done = 0;
661
662 /*
663 * The error bits are cleared on read,
664 * use saved value from irq handler.
665 */
666 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
667
668 /* handle state changes */
669 work_done += flexcan_poll_state(dev, reg_esr);
670
671 /* handle RX-FIFO */
672 reg_iflag1 = flexcan_read(®s->iflag1);
673 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
674 work_done < quota) {
675 work_done += flexcan_read_frame(dev);
676 reg_iflag1 = flexcan_read(®s->iflag1);
677 }
678
679 /* report bus errors */
680 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
681 work_done += flexcan_poll_bus_err(dev, reg_esr);
682
683 if (work_done < quota) {
684 napi_complete(napi);
685 /* enable IRQs */
686 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
687 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
688 }
689
690 return work_done;
691}
692
693static irqreturn_t flexcan_irq(int irq, void *dev_id)
694{
695 struct net_device *dev = dev_id;
696 struct net_device_stats *stats = &dev->stats;
697 struct flexcan_priv *priv = netdev_priv(dev);
698 struct flexcan_regs __iomem *regs = priv->base;
699 u32 reg_iflag1, reg_esr;
700
701 reg_iflag1 = flexcan_read(®s->iflag1);
702 reg_esr = flexcan_read(®s->esr);
703 /* ACK all bus error and state change IRQ sources */
704 if (reg_esr & FLEXCAN_ESR_ALL_INT)
705 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
706
707 /*
708 * schedule NAPI in case of:
709 * - rx IRQ
710 * - state change IRQ
711 * - bus error IRQ and bus error reporting is activated
712 */
713 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
714 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
715 flexcan_has_and_handle_berr(priv, reg_esr)) {
716 /*
717 * The error bits are cleared on read,
718 * save them for later use.
719 */
720 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
721 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
722 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
723 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
724 ®s->ctrl);
725 napi_schedule(&priv->napi);
726 }
727
728 /* FIFO overflow */
729 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
730 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
731 dev->stats.rx_over_errors++;
732 dev->stats.rx_errors++;
733 }
734
735 /* transmission complete interrupt */
736 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
737 stats->tx_bytes += can_get_echo_skb(dev, 0);
738 stats->tx_packets++;
739 can_led_event(dev, CAN_LED_EVENT_TX);
740 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
741 netif_wake_queue(dev);
742 }
743
744 return IRQ_HANDLED;
745}
746
747static void flexcan_set_bittiming(struct net_device *dev)
748{
749 const struct flexcan_priv *priv = netdev_priv(dev);
750 const struct can_bittiming *bt = &priv->can.bittiming;
751 struct flexcan_regs __iomem *regs = priv->base;
752 u32 reg;
753
754 reg = flexcan_read(®s->ctrl);
755 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
756 FLEXCAN_CTRL_RJW(0x3) |
757 FLEXCAN_CTRL_PSEG1(0x7) |
758 FLEXCAN_CTRL_PSEG2(0x7) |
759 FLEXCAN_CTRL_PROPSEG(0x7) |
760 FLEXCAN_CTRL_LPB |
761 FLEXCAN_CTRL_SMP |
762 FLEXCAN_CTRL_LOM);
763
764 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
765 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
766 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
767 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
768 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
769
770 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
771 reg |= FLEXCAN_CTRL_LPB;
772 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
773 reg |= FLEXCAN_CTRL_LOM;
774 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
775 reg |= FLEXCAN_CTRL_SMP;
776
777 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
778 flexcan_write(reg, ®s->ctrl);
779
780 /* print chip status */
781 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
782 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
783}
784
785/*
786 * flexcan_chip_start
787 *
788 * this functions is entered with clocks enabled
789 *
790 */
791static int flexcan_chip_start(struct net_device *dev)
792{
793 struct flexcan_priv *priv = netdev_priv(dev);
794 struct flexcan_regs __iomem *regs = priv->base;
795 int err;
796 u32 reg_mcr, reg_ctrl;
797
798 /* enable module */
799 err = flexcan_chip_enable(priv);
800 if (err)
801 return err;
802
803 /* soft reset */
804 err = flexcan_chip_softreset(priv);
805 if (err)
806 goto out_chip_disable;
807
808 flexcan_set_bittiming(dev);
809
810 /*
811 * MCR
812 *
813 * enable freeze
814 * enable fifo
815 * halt now
816 * only supervisor access
817 * enable warning int
818 * choose format C
819 * disable local echo
820 *
821 */
822 reg_mcr = flexcan_read(®s->mcr);
823 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
824 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
825 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
826 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
827 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
828 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
829 flexcan_write(reg_mcr, ®s->mcr);
830
831 /*
832 * CTRL
833 *
834 * disable timer sync feature
835 *
836 * disable auto busoff recovery
837 * transmit lowest buffer first
838 *
839 * enable tx and rx warning interrupt
840 * enable bus off interrupt
841 * (== FLEXCAN_CTRL_ERR_STATE)
842 */
843 reg_ctrl = flexcan_read(®s->ctrl);
844 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
845 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
846 FLEXCAN_CTRL_ERR_STATE;
847 /*
848 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
849 * on most Flexcan cores, too. Otherwise we don't get
850 * any error warning or passive interrupts.
851 */
852 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
853 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
854 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
855
856 /* save for later use */
857 priv->reg_ctrl_default = reg_ctrl;
858 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
859 flexcan_write(reg_ctrl, ®s->ctrl);
860
861 /* Abort any pending TX, mark Mailbox as INACTIVE */
862 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
863 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
864
865 /* acceptance mask/acceptance code (accept everything) */
866 flexcan_write(0x0, ®s->rxgmask);
867 flexcan_write(0x0, ®s->rx14mask);
868 flexcan_write(0x0, ®s->rx15mask);
869
870 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
871 flexcan_write(0x0, ®s->rxfgmask);
872
873 err = flexcan_transceiver_enable(priv);
874 if (err)
875 goto out_chip_disable;
876
877 /* synchronize with the can bus */
878 err = flexcan_chip_unfreeze(priv);
879 if (err)
880 goto out_transceiver_disable;
881
882 priv->can.state = CAN_STATE_ERROR_ACTIVE;
883
884 /* enable FIFO interrupts */
885 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
886
887 /* print chip status */
888 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
889 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
890
891 return 0;
892
893 out_transceiver_disable:
894 flexcan_transceiver_disable(priv);
895 out_chip_disable:
896 flexcan_chip_disable(priv);
897 return err;
898}
899
900/*
901 * flexcan_chip_stop
902 *
903 * this functions is entered with clocks enabled
904 *
905 */
906static void flexcan_chip_stop(struct net_device *dev)
907{
908 struct flexcan_priv *priv = netdev_priv(dev);
909 struct flexcan_regs __iomem *regs = priv->base;
910
911 /* freeze + disable module */
912 flexcan_chip_freeze(priv);
913 flexcan_chip_disable(priv);
914
915 /* Disable all interrupts */
916 flexcan_write(0, ®s->imask1);
917 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
918 ®s->ctrl);
919
920 flexcan_transceiver_disable(priv);
921 priv->can.state = CAN_STATE_STOPPED;
922
923 return;
924}
925
926static int flexcan_open(struct net_device *dev)
927{
928 struct flexcan_priv *priv = netdev_priv(dev);
929 int err;
930
931 err = clk_prepare_enable(priv->clk_ipg);
932 if (err)
933 return err;
934
935 err = clk_prepare_enable(priv->clk_per);
936 if (err)
937 goto out_disable_ipg;
938
939 err = open_candev(dev);
940 if (err)
941 goto out_disable_per;
942
943 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
944 if (err)
945 goto out_close;
946
947 /* start chip and queuing */
948 err = flexcan_chip_start(dev);
949 if (err)
950 goto out_free_irq;
951
952 can_led_event(dev, CAN_LED_EVENT_OPEN);
953
954 napi_enable(&priv->napi);
955 netif_start_queue(dev);
956
957 return 0;
958
959 out_free_irq:
960 free_irq(dev->irq, dev);
961 out_close:
962 close_candev(dev);
963 out_disable_per:
964 clk_disable_unprepare(priv->clk_per);
965 out_disable_ipg:
966 clk_disable_unprepare(priv->clk_ipg);
967
968 return err;
969}
970
971static int flexcan_close(struct net_device *dev)
972{
973 struct flexcan_priv *priv = netdev_priv(dev);
974
975 netif_stop_queue(dev);
976 napi_disable(&priv->napi);
977 flexcan_chip_stop(dev);
978
979 free_irq(dev->irq, dev);
980 clk_disable_unprepare(priv->clk_per);
981 clk_disable_unprepare(priv->clk_ipg);
982
983 close_candev(dev);
984
985 can_led_event(dev, CAN_LED_EVENT_STOP);
986
987 return 0;
988}
989
990static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
991{
992 int err;
993
994 switch (mode) {
995 case CAN_MODE_START:
996 err = flexcan_chip_start(dev);
997 if (err)
998 return err;
999
1000 netif_wake_queue(dev);
1001 break;
1002
1003 default:
1004 return -EOPNOTSUPP;
1005 }
1006
1007 return 0;
1008}
1009
1010static const struct net_device_ops flexcan_netdev_ops = {
1011 .ndo_open = flexcan_open,
1012 .ndo_stop = flexcan_close,
1013 .ndo_start_xmit = flexcan_start_xmit,
1014 .ndo_change_mtu = can_change_mtu,
1015};
1016
1017static int register_flexcandev(struct net_device *dev)
1018{
1019 struct flexcan_priv *priv = netdev_priv(dev);
1020 struct flexcan_regs __iomem *regs = priv->base;
1021 u32 reg, err;
1022
1023 err = clk_prepare_enable(priv->clk_ipg);
1024 if (err)
1025 return err;
1026
1027 err = clk_prepare_enable(priv->clk_per);
1028 if (err)
1029 goto out_disable_ipg;
1030
1031 /* select "bus clock", chip must be disabled */
1032 err = flexcan_chip_disable(priv);
1033 if (err)
1034 goto out_disable_per;
1035 reg = flexcan_read(®s->ctrl);
1036 reg |= FLEXCAN_CTRL_CLK_SRC;
1037 flexcan_write(reg, ®s->ctrl);
1038
1039 err = flexcan_chip_enable(priv);
1040 if (err)
1041 goto out_chip_disable;
1042
1043 /* set freeze, halt and activate FIFO, restrict register access */
1044 reg = flexcan_read(®s->mcr);
1045 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1046 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1047 flexcan_write(reg, ®s->mcr);
1048
1049 /*
1050 * Currently we only support newer versions of this core
1051 * featuring a RX FIFO. Older cores found on some Coldfire
1052 * derivates are not yet supported.
1053 */
1054 reg = flexcan_read(®s->mcr);
1055 if (!(reg & FLEXCAN_MCR_FEN)) {
1056 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1057 err = -ENODEV;
1058 goto out_chip_disable;
1059 }
1060
1061 err = register_candev(dev);
1062
1063 /* disable core and turn off clocks */
1064 out_chip_disable:
1065 flexcan_chip_disable(priv);
1066 out_disable_per:
1067 clk_disable_unprepare(priv->clk_per);
1068 out_disable_ipg:
1069 clk_disable_unprepare(priv->clk_ipg);
1070
1071 return err;
1072}
1073
1074static void unregister_flexcandev(struct net_device *dev)
1075{
1076 unregister_candev(dev);
1077}
1078
1079static const struct of_device_id flexcan_of_match[] = {
1080 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1081 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1082 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1083 { /* sentinel */ },
1084};
1085MODULE_DEVICE_TABLE(of, flexcan_of_match);
1086
1087static const struct platform_device_id flexcan_id_table[] = {
1088 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1089 { /* sentinel */ },
1090};
1091MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1092
1093static int flexcan_probe(struct platform_device *pdev)
1094{
1095 const struct of_device_id *of_id;
1096 const struct flexcan_devtype_data *devtype_data;
1097 struct net_device *dev;
1098 struct flexcan_priv *priv;
1099 struct resource *mem;
1100 struct clk *clk_ipg = NULL, *clk_per = NULL;
1101 void __iomem *base;
1102 int err, irq;
1103 u32 clock_freq = 0;
1104
1105 if (pdev->dev.of_node)
1106 of_property_read_u32(pdev->dev.of_node,
1107 "clock-frequency", &clock_freq);
1108
1109 if (!clock_freq) {
1110 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1111 if (IS_ERR(clk_ipg)) {
1112 dev_err(&pdev->dev, "no ipg clock defined\n");
1113 return PTR_ERR(clk_ipg);
1114 }
1115
1116 clk_per = devm_clk_get(&pdev->dev, "per");
1117 if (IS_ERR(clk_per)) {
1118 dev_err(&pdev->dev, "no per clock defined\n");
1119 return PTR_ERR(clk_per);
1120 }
1121 clock_freq = clk_get_rate(clk_per);
1122 }
1123
1124 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1125 irq = platform_get_irq(pdev, 0);
1126 if (irq <= 0)
1127 return -ENODEV;
1128
1129 base = devm_ioremap_resource(&pdev->dev, mem);
1130 if (IS_ERR(base))
1131 return PTR_ERR(base);
1132
1133 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1134 if (of_id) {
1135 devtype_data = of_id->data;
1136 } else if (platform_get_device_id(pdev)->driver_data) {
1137 devtype_data = (struct flexcan_devtype_data *)
1138 platform_get_device_id(pdev)->driver_data;
1139 } else {
1140 return -ENODEV;
1141 }
1142
1143 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1144 if (!dev)
1145 return -ENOMEM;
1146
1147 dev->netdev_ops = &flexcan_netdev_ops;
1148 dev->irq = irq;
1149 dev->flags |= IFF_ECHO;
1150
1151 priv = netdev_priv(dev);
1152 priv->can.clock.freq = clock_freq;
1153 priv->can.bittiming_const = &flexcan_bittiming_const;
1154 priv->can.do_set_mode = flexcan_set_mode;
1155 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1156 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1157 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1158 CAN_CTRLMODE_BERR_REPORTING;
1159 priv->base = base;
1160 priv->dev = dev;
1161 priv->clk_ipg = clk_ipg;
1162 priv->clk_per = clk_per;
1163 priv->pdata = dev_get_platdata(&pdev->dev);
1164 priv->devtype_data = devtype_data;
1165
1166 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1167 if (IS_ERR(priv->reg_xceiver))
1168 priv->reg_xceiver = NULL;
1169
1170 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1171
1172 platform_set_drvdata(pdev, dev);
1173 SET_NETDEV_DEV(dev, &pdev->dev);
1174
1175 err = register_flexcandev(dev);
1176 if (err) {
1177 dev_err(&pdev->dev, "registering netdev failed\n");
1178 goto failed_register;
1179 }
1180
1181 devm_can_led_init(dev);
1182
1183 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1184 priv->base, dev->irq);
1185
1186 return 0;
1187
1188 failed_register:
1189 free_candev(dev);
1190 return err;
1191}
1192
1193static int flexcan_remove(struct platform_device *pdev)
1194{
1195 struct net_device *dev = platform_get_drvdata(pdev);
1196 struct flexcan_priv *priv = netdev_priv(dev);
1197
1198 unregister_flexcandev(dev);
1199 netif_napi_del(&priv->napi);
1200 free_candev(dev);
1201
1202 return 0;
1203}
1204
1205static int __maybe_unused flexcan_suspend(struct device *device)
1206{
1207 struct net_device *dev = dev_get_drvdata(device);
1208 struct flexcan_priv *priv = netdev_priv(dev);
1209 int err;
1210
1211 err = flexcan_chip_disable(priv);
1212 if (err)
1213 return err;
1214
1215 if (netif_running(dev)) {
1216 netif_stop_queue(dev);
1217 netif_device_detach(dev);
1218 }
1219 priv->can.state = CAN_STATE_SLEEPING;
1220
1221 return 0;
1222}
1223
1224static int __maybe_unused flexcan_resume(struct device *device)
1225{
1226 struct net_device *dev = dev_get_drvdata(device);
1227 struct flexcan_priv *priv = netdev_priv(dev);
1228
1229 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1230 if (netif_running(dev)) {
1231 netif_device_attach(dev);
1232 netif_start_queue(dev);
1233 }
1234 return flexcan_chip_enable(priv);
1235}
1236
1237static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1238
1239static struct platform_driver flexcan_driver = {
1240 .driver = {
1241 .name = DRV_NAME,
1242 .owner = THIS_MODULE,
1243 .pm = &flexcan_pm_ops,
1244 .of_match_table = flexcan_of_match,
1245 },
1246 .probe = flexcan_probe,
1247 .remove = flexcan_remove,
1248 .id_table = flexcan_id_table,
1249};
1250
1251module_platform_driver(flexcan_driver);
1252
1253MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1254 "Marc Kleine-Budde <kernel@pengutronix.de>");
1255MODULE_LICENSE("GPL v2");
1256MODULE_DESCRIPTION("CAN port driver for flexcan based chip");