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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
34 struct usb_ctrlrequest *ctrl);
35
36static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
37 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
38{
39 struct dwc3_trb *trb;
40 struct dwc3 *dwc;
41
42 dwc = dep->dwc;
43 trb = &dwc->ep0_trb[dep->trb_enqueue];
44
45 if (chain)
46 dep->trb_enqueue++;
47
48 trb->bpl = lower_32_bits(buf_dma);
49 trb->bph = upper_32_bits(buf_dma);
50 trb->size = len;
51 trb->ctrl = type;
52
53 trb->ctrl |= (DWC3_TRB_CTRL_HWO
54 | DWC3_TRB_CTRL_ISP_IMI);
55
56 if (chain)
57 trb->ctrl |= DWC3_TRB_CTRL_CHN;
58 else
59 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 | DWC3_TRB_CTRL_LST);
61
62 trace_dwc3_prepare_trb(dep, trb);
63}
64
65static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
66{
67 struct dwc3_gadget_ep_cmd_params params;
68 struct dwc3 *dwc;
69 int ret;
70
71 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
72 return 0;
73
74 dwc = dep->dwc;
75
76 memset(¶ms, 0, sizeof(params));
77 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
78 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
79
80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
81 if (ret < 0)
82 return ret;
83
84 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
85
86 return 0;
87}
88
89static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
90 struct dwc3_request *req)
91{
92 struct dwc3 *dwc = dep->dwc;
93
94 req->request.actual = 0;
95 req->request.status = -EINPROGRESS;
96 req->epnum = dep->number;
97
98 list_add_tail(&req->list, &dep->pending_list);
99
100 /*
101 * Gadget driver might not be quick enough to queue a request
102 * before we get a Transfer Not Ready event on this endpoint.
103 *
104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
105 * flag is set, it's telling us that as soon as Gadget queues the
106 * required request, we should kick the transfer here because the
107 * IRQ we were waiting for is long gone.
108 */
109 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 unsigned int direction;
111
112 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
113
114 if (dwc->ep0state != EP0_DATA_PHASE) {
115 dev_WARN(dwc->dev, "Unexpected pending request\n");
116 return 0;
117 }
118
119 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
120
121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
122 DWC3_EP0_DIR_IN);
123
124 return 0;
125 }
126
127 /*
128 * In case gadget driver asked us to delay the STATUS phase,
129 * handle it here.
130 */
131 if (dwc->delayed_status) {
132 unsigned int direction;
133
134 direction = !dwc->ep0_expect_in;
135 dwc->delayed_status = false;
136 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
137
138 if (dwc->ep0state == EP0_STATUS_PHASE)
139 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
140
141 return 0;
142 }
143
144 /*
145 * Unfortunately we have uncovered a limitation wrt the Data Phase.
146 *
147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
148 * come before issueing Start Transfer command, but if we do, we will
149 * miss situations where the host starts another SETUP phase instead of
150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
151 * Layer Compliance Suite.
152 *
153 * The problem surfaces due to the fact that in case of back-to-back
154 * SETUP packets there will be no XferNotReady(DATA) generated and we
155 * will be stuck waiting for XferNotReady(DATA) forever.
156 *
157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
158 * it tells us to start Data Phase right away. It also mentions that if
159 * we receive a SETUP phase instead of the DATA phase, core will issue
160 * XferComplete for the DATA phase, before actually initiating it in
161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
162 * can only be used to print some debugging logs, as the core expects
163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
164 * just so it completes right away, without transferring anything and,
165 * only then, we can go back to the SETUP phase.
166 *
167 * Because of this scenario, SNPS decided to change the programming
168 * model of control transfers and support on-demand transfers only for
169 * the STATUS phase. To fix the issue we have now, we will always wait
170 * for gadget driver to queue the DATA phase's struct usb_request, then
171 * start it right away.
172 *
173 * If we're actually in a 2-stage transfer, we will wait for
174 * XferNotReady(STATUS).
175 */
176 if (dwc->three_stage_setup) {
177 unsigned int direction;
178
179 direction = dwc->ep0_expect_in;
180 dwc->ep0state = EP0_DATA_PHASE;
181
182 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
183
184 dep->flags &= ~DWC3_EP0_DIR_IN;
185 }
186
187 return 0;
188}
189
190int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 gfp_t gfp_flags)
192{
193 struct dwc3_request *req = to_dwc3_request(request);
194 struct dwc3_ep *dep = to_dwc3_ep(ep);
195 struct dwc3 *dwc = dep->dwc;
196
197 unsigned long flags;
198
199 int ret;
200
201 spin_lock_irqsave(&dwc->lock, flags);
202 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
204 dep->name);
205 ret = -ESHUTDOWN;
206 goto out;
207 }
208
209 /* we share one TRB for ep0/1 */
210 if (!list_empty(&dep->pending_list)) {
211 ret = -EBUSY;
212 goto out;
213 }
214
215 ret = __dwc3_gadget_ep0_queue(dep, req);
216
217out:
218 spin_unlock_irqrestore(&dwc->lock, flags);
219
220 return ret;
221}
222
223void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
224{
225 struct dwc3_ep *dep;
226
227 /* reinitialize physical ep1 */
228 dep = dwc->eps[1];
229 dep->flags = DWC3_EP_ENABLED;
230
231 /* stall is always issued on EP0 */
232 dep = dwc->eps[0];
233 __dwc3_gadget_ep_set_halt(dep, 1, false);
234 dep->flags = DWC3_EP_ENABLED;
235 dwc->delayed_status = false;
236
237 if (!list_empty(&dep->pending_list)) {
238 struct dwc3_request *req;
239
240 req = next_request(&dep->pending_list);
241 if (!dwc->connected)
242 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
243 else
244 dwc3_gadget_giveback(dep, req, -ECONNRESET);
245 }
246
247 dwc->eps[0]->trb_enqueue = 0;
248 dwc->eps[1]->trb_enqueue = 0;
249 dwc->ep0state = EP0_SETUP_PHASE;
250 dwc3_ep0_out_start(dwc);
251}
252
253int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
254{
255 struct dwc3_ep *dep = to_dwc3_ep(ep);
256 struct dwc3 *dwc = dep->dwc;
257
258 dwc3_ep0_stall_and_restart(dwc);
259
260 return 0;
261}
262
263int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
264{
265 struct dwc3_ep *dep = to_dwc3_ep(ep);
266 struct dwc3 *dwc = dep->dwc;
267 unsigned long flags;
268 int ret;
269
270 spin_lock_irqsave(&dwc->lock, flags);
271 ret = __dwc3_gadget_ep0_set_halt(ep, value);
272 spin_unlock_irqrestore(&dwc->lock, flags);
273
274 return ret;
275}
276
277void dwc3_ep0_out_start(struct dwc3 *dwc)
278{
279 struct dwc3_ep *dep;
280 int ret;
281 int i;
282
283 complete(&dwc->ep0_in_setup);
284
285 dep = dwc->eps[0];
286 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
287 DWC3_TRBCTL_CONTROL_SETUP, false);
288 ret = dwc3_ep0_start_trans(dep);
289 WARN_ON(ret < 0);
290 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
291 struct dwc3_ep *dwc3_ep;
292
293 dwc3_ep = dwc->eps[i];
294 if (!dwc3_ep)
295 continue;
296
297 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
298 continue;
299
300 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
301 if (dwc->connected)
302 dwc3_stop_active_transfer(dwc3_ep, true, true);
303 else
304 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
305 }
306}
307
308static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
309{
310 struct dwc3_ep *dep;
311 u32 windex = le16_to_cpu(wIndex_le);
312 u32 epnum;
313
314 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
315 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
316 epnum |= 1;
317
318 dep = dwc->eps[epnum];
319 if (dep == NULL)
320 return NULL;
321
322 if (dep->flags & DWC3_EP_ENABLED)
323 return dep;
324
325 return NULL;
326}
327
328static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
329{
330}
331/*
332 * ch 9.4.5
333 */
334static int dwc3_ep0_handle_status(struct dwc3 *dwc,
335 struct usb_ctrlrequest *ctrl)
336{
337 struct dwc3_ep *dep;
338 u32 recip;
339 u32 value;
340 u32 reg;
341 u16 usb_status = 0;
342 __le16 *response_pkt;
343
344 /* We don't support PTM_STATUS */
345 value = le16_to_cpu(ctrl->wValue);
346 if (value != 0)
347 return -EINVAL;
348
349 recip = ctrl->bRequestType & USB_RECIP_MASK;
350 switch (recip) {
351 case USB_RECIP_DEVICE:
352 /*
353 * LTM will be set once we know how to set this in HW.
354 */
355 usb_status |= dwc->gadget->is_selfpowered;
356
357 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
358 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
359 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
360 if (reg & DWC3_DCTL_INITU1ENA)
361 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
362 if (reg & DWC3_DCTL_INITU2ENA)
363 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
364 } else {
365 usb_status |= dwc->gadget->wakeup_armed <<
366 USB_DEVICE_REMOTE_WAKEUP;
367 }
368
369 break;
370
371 case USB_RECIP_INTERFACE:
372 /*
373 * Function Remote Wake Capable D0
374 * Function Remote Wakeup D1
375 */
376 return dwc3_ep0_delegate_req(dwc, ctrl);
377
378 case USB_RECIP_ENDPOINT:
379 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
380 if (!dep)
381 return -EINVAL;
382
383 if (dep->flags & DWC3_EP_STALL)
384 usb_status = 1 << USB_ENDPOINT_HALT;
385 break;
386 default:
387 return -EINVAL;
388 }
389
390 response_pkt = (__le16 *) dwc->setup_buf;
391 *response_pkt = cpu_to_le16(usb_status);
392
393 dep = dwc->eps[0];
394 dwc->ep0_usb_req.dep = dep;
395 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
396 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
397 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
398
399 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
400}
401
402static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
403 int set)
404{
405 u32 reg;
406
407 if (state != USB_STATE_CONFIGURED)
408 return -EINVAL;
409 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
410 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
411 return -EINVAL;
412 if (set && dwc->dis_u1_entry_quirk)
413 return -EINVAL;
414
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
416 if (set)
417 reg |= DWC3_DCTL_INITU1ENA;
418 else
419 reg &= ~DWC3_DCTL_INITU1ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
421
422 return 0;
423}
424
425static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
426 int set)
427{
428 u32 reg;
429
430
431 if (state != USB_STATE_CONFIGURED)
432 return -EINVAL;
433 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
434 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
435 return -EINVAL;
436 if (set && dwc->dis_u2_entry_quirk)
437 return -EINVAL;
438
439 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
440 if (set)
441 reg |= DWC3_DCTL_INITU2ENA;
442 else
443 reg &= ~DWC3_DCTL_INITU2ENA;
444 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
445
446 return 0;
447}
448
449static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
450 u32 wIndex, int set)
451{
452 if ((wIndex & 0xff) != 0)
453 return -EINVAL;
454 if (!set)
455 return -EINVAL;
456
457 switch (wIndex >> 8) {
458 case USB_TEST_J:
459 case USB_TEST_K:
460 case USB_TEST_SE0_NAK:
461 case USB_TEST_PACKET:
462 case USB_TEST_FORCE_ENABLE:
463 dwc->test_mode_nr = wIndex >> 8;
464 dwc->test_mode = true;
465 break;
466 default:
467 return -EINVAL;
468 }
469
470 return 0;
471}
472
473static int dwc3_ep0_handle_device(struct dwc3 *dwc,
474 struct usb_ctrlrequest *ctrl, int set)
475{
476 enum usb_device_state state;
477 u32 wValue;
478 u32 wIndex;
479 int ret = 0;
480
481 wValue = le16_to_cpu(ctrl->wValue);
482 wIndex = le16_to_cpu(ctrl->wIndex);
483 state = dwc->gadget->state;
484
485 switch (wValue) {
486 case USB_DEVICE_REMOTE_WAKEUP:
487 if (dwc->wakeup_configured)
488 dwc->gadget->wakeup_armed = set;
489 else
490 ret = -EINVAL;
491 break;
492 /*
493 * 9.4.1 says only for SS, in AddressState only for
494 * default control pipe
495 */
496 case USB_DEVICE_U1_ENABLE:
497 ret = dwc3_ep0_handle_u1(dwc, state, set);
498 break;
499 case USB_DEVICE_U2_ENABLE:
500 ret = dwc3_ep0_handle_u2(dwc, state, set);
501 break;
502 case USB_DEVICE_LTM_ENABLE:
503 ret = -EINVAL;
504 break;
505 case USB_DEVICE_TEST_MODE:
506 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
507 break;
508 default:
509 ret = -EINVAL;
510 }
511
512 return ret;
513}
514
515static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
516 struct usb_ctrlrequest *ctrl, int set)
517{
518 u32 wValue;
519 int ret = 0;
520
521 wValue = le16_to_cpu(ctrl->wValue);
522
523 switch (wValue) {
524 case USB_INTRF_FUNC_SUSPEND:
525 ret = dwc3_ep0_delegate_req(dwc, ctrl);
526 break;
527 default:
528 ret = -EINVAL;
529 }
530
531 return ret;
532}
533
534static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
535 struct usb_ctrlrequest *ctrl, int set)
536{
537 struct dwc3_ep *dep;
538 u32 wValue;
539 int ret;
540
541 wValue = le16_to_cpu(ctrl->wValue);
542
543 switch (wValue) {
544 case USB_ENDPOINT_HALT:
545 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
546 if (!dep)
547 return -EINVAL;
548
549 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
550 break;
551
552 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
553 if (ret)
554 return -EINVAL;
555
556 /* ClearFeature(Halt) may need delayed status */
557 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
558 return USB_GADGET_DELAYED_STATUS;
559
560 break;
561 default:
562 return -EINVAL;
563 }
564
565 return 0;
566}
567
568static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
569 struct usb_ctrlrequest *ctrl, int set)
570{
571 u32 recip;
572 int ret;
573
574 recip = ctrl->bRequestType & USB_RECIP_MASK;
575
576 switch (recip) {
577 case USB_RECIP_DEVICE:
578 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
579 break;
580 case USB_RECIP_INTERFACE:
581 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
582 break;
583 case USB_RECIP_ENDPOINT:
584 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
585 break;
586 default:
587 ret = -EINVAL;
588 }
589
590 return ret;
591}
592
593static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
594{
595 enum usb_device_state state = dwc->gadget->state;
596 u32 addr;
597 u32 reg;
598
599 addr = le16_to_cpu(ctrl->wValue);
600 if (addr > 127) {
601 dev_err(dwc->dev, "invalid device address %d\n", addr);
602 return -EINVAL;
603 }
604
605 if (state == USB_STATE_CONFIGURED) {
606 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
607 return -EINVAL;
608 }
609
610 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
611 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
612 reg |= DWC3_DCFG_DEVADDR(addr);
613 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
614
615 if (addr)
616 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
617 else
618 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
619
620 return 0;
621}
622
623static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
624{
625 int ret = -EINVAL;
626
627 if (dwc->async_callbacks) {
628 spin_unlock(&dwc->lock);
629 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
630 spin_lock(&dwc->lock);
631 }
632 return ret;
633}
634
635static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
636{
637 enum usb_device_state state = dwc->gadget->state;
638 u32 cfg;
639 int ret;
640 u32 reg;
641
642 cfg = le16_to_cpu(ctrl->wValue);
643
644 switch (state) {
645 case USB_STATE_DEFAULT:
646 return -EINVAL;
647
648 case USB_STATE_ADDRESS:
649 dwc3_gadget_clear_tx_fifos(dwc);
650
651 ret = dwc3_ep0_delegate_req(dwc, ctrl);
652 /* if the cfg matches and the cfg is non zero */
653 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
654
655 /*
656 * only change state if set_config has already
657 * been processed. If gadget driver returns
658 * USB_GADGET_DELAYED_STATUS, we will wait
659 * to change the state on the next usb_ep_queue()
660 */
661 if (ret == 0)
662 usb_gadget_set_state(dwc->gadget,
663 USB_STATE_CONFIGURED);
664
665 /*
666 * Enable transition to U1/U2 state when
667 * nothing is pending from application.
668 */
669 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
670 if (!dwc->dis_u1_entry_quirk)
671 reg |= DWC3_DCTL_ACCEPTU1ENA;
672 if (!dwc->dis_u2_entry_quirk)
673 reg |= DWC3_DCTL_ACCEPTU2ENA;
674 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
675 }
676 break;
677
678 case USB_STATE_CONFIGURED:
679 ret = dwc3_ep0_delegate_req(dwc, ctrl);
680 if (!cfg && !ret)
681 usb_gadget_set_state(dwc->gadget,
682 USB_STATE_ADDRESS);
683 break;
684 default:
685 ret = -EINVAL;
686 }
687 return ret;
688}
689
690static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
691{
692 struct dwc3_ep *dep = to_dwc3_ep(ep);
693 struct dwc3 *dwc = dep->dwc;
694
695 u32 param = 0;
696 u32 reg;
697
698 struct timing {
699 u8 u1sel;
700 u8 u1pel;
701 __le16 u2sel;
702 __le16 u2pel;
703 } __packed timing;
704
705 int ret;
706
707 memcpy(&timing, req->buf, sizeof(timing));
708
709 dwc->u1sel = timing.u1sel;
710 dwc->u1pel = timing.u1pel;
711 dwc->u2sel = le16_to_cpu(timing.u2sel);
712 dwc->u2pel = le16_to_cpu(timing.u2pel);
713
714 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
715 if (reg & DWC3_DCTL_INITU2ENA)
716 param = dwc->u2pel;
717 if (reg & DWC3_DCTL_INITU1ENA)
718 param = dwc->u1pel;
719
720 /*
721 * According to Synopsys Databook, if parameter is
722 * greater than 125, a value of zero should be
723 * programmed in the register.
724 */
725 if (param > 125)
726 param = 0;
727
728 /* now that we have the time, issue DGCMD Set Sel */
729 ret = dwc3_send_gadget_generic_command(dwc,
730 DWC3_DGCMD_SET_PERIODIC_PAR, param);
731 WARN_ON(ret < 0);
732}
733
734static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
735{
736 struct dwc3_ep *dep;
737 enum usb_device_state state = dwc->gadget->state;
738 u16 wLength;
739
740 if (state == USB_STATE_DEFAULT)
741 return -EINVAL;
742
743 wLength = le16_to_cpu(ctrl->wLength);
744
745 if (wLength != 6) {
746 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
747 wLength);
748 return -EINVAL;
749 }
750
751 /*
752 * To handle Set SEL we need to receive 6 bytes from Host. So let's
753 * queue a usb_request for 6 bytes.
754 *
755 * Remember, though, this controller can't handle non-wMaxPacketSize
756 * aligned transfers on the OUT direction, so we queue a request for
757 * wMaxPacketSize instead.
758 */
759 dep = dwc->eps[0];
760 dwc->ep0_usb_req.dep = dep;
761 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
762 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
763 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
764
765 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
766}
767
768static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
769{
770 u16 wLength;
771 u16 wValue;
772 u16 wIndex;
773
774 wValue = le16_to_cpu(ctrl->wValue);
775 wLength = le16_to_cpu(ctrl->wLength);
776 wIndex = le16_to_cpu(ctrl->wIndex);
777
778 if (wIndex || wLength)
779 return -EINVAL;
780
781 dwc->gadget->isoch_delay = wValue;
782
783 return 0;
784}
785
786static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
787{
788 int ret;
789
790 switch (ctrl->bRequest) {
791 case USB_REQ_GET_STATUS:
792 ret = dwc3_ep0_handle_status(dwc, ctrl);
793 break;
794 case USB_REQ_CLEAR_FEATURE:
795 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
796 break;
797 case USB_REQ_SET_FEATURE:
798 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
799 break;
800 case USB_REQ_SET_ADDRESS:
801 ret = dwc3_ep0_set_address(dwc, ctrl);
802 break;
803 case USB_REQ_SET_CONFIGURATION:
804 ret = dwc3_ep0_set_config(dwc, ctrl);
805 break;
806 case USB_REQ_SET_SEL:
807 ret = dwc3_ep0_set_sel(dwc, ctrl);
808 break;
809 case USB_REQ_SET_ISOCH_DELAY:
810 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
811 break;
812 default:
813 ret = dwc3_ep0_delegate_req(dwc, ctrl);
814 break;
815 }
816
817 return ret;
818}
819
820static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
821 const struct dwc3_event_depevt *event)
822{
823 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
824 int ret = -EINVAL;
825 u32 len;
826
827 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
828 goto out;
829
830 trace_dwc3_ctrl_req(ctrl);
831
832 len = le16_to_cpu(ctrl->wLength);
833 if (!len) {
834 dwc->three_stage_setup = false;
835 dwc->ep0_expect_in = false;
836 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
837 } else {
838 dwc->three_stage_setup = true;
839 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
840 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
841 }
842
843 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
844 ret = dwc3_ep0_std_request(dwc, ctrl);
845 else
846 ret = dwc3_ep0_delegate_req(dwc, ctrl);
847
848 if (ret == USB_GADGET_DELAYED_STATUS)
849 dwc->delayed_status = true;
850
851out:
852 if (ret < 0)
853 dwc3_ep0_stall_and_restart(dwc);
854}
855
856static void dwc3_ep0_complete_data(struct dwc3 *dwc,
857 const struct dwc3_event_depevt *event)
858{
859 struct dwc3_request *r;
860 struct usb_request *ur;
861 struct dwc3_trb *trb;
862 struct dwc3_ep *ep0;
863 u32 transferred = 0;
864 u32 status;
865 u32 length;
866 u8 epnum;
867
868 epnum = event->endpoint_number;
869 ep0 = dwc->eps[0];
870
871 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
872 trb = dwc->ep0_trb;
873 trace_dwc3_complete_trb(ep0, trb);
874
875 r = next_request(&ep0->pending_list);
876 if (!r)
877 return;
878
879 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
880 if (status == DWC3_TRBSTS_SETUP_PENDING) {
881 dwc->setup_packet_pending = true;
882 if (r)
883 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
884
885 return;
886 }
887
888 ur = &r->request;
889
890 length = trb->size & DWC3_TRB_SIZE_MASK;
891 transferred = ur->length - length;
892 ur->actual += transferred;
893
894 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
895 ur->length && ur->zero) || dwc->ep0_bounced) {
896 trb++;
897 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
898 trace_dwc3_complete_trb(ep0, trb);
899
900 if (r->direction)
901 dwc->eps[1]->trb_enqueue = 0;
902 else
903 dwc->eps[0]->trb_enqueue = 0;
904
905 dwc->ep0_bounced = false;
906 }
907
908 if ((epnum & 1) && ur->actual < ur->length)
909 dwc3_ep0_stall_and_restart(dwc);
910 else
911 dwc3_gadget_giveback(ep0, r, 0);
912}
913
914static void dwc3_ep0_complete_status(struct dwc3 *dwc,
915 const struct dwc3_event_depevt *event)
916{
917 struct dwc3_request *r;
918 struct dwc3_ep *dep;
919 struct dwc3_trb *trb;
920 u32 status;
921
922 dep = dwc->eps[0];
923 trb = dwc->ep0_trb;
924
925 trace_dwc3_complete_trb(dep, trb);
926
927 if (!list_empty(&dep->pending_list)) {
928 r = next_request(&dep->pending_list);
929
930 dwc3_gadget_giveback(dep, r, 0);
931 }
932
933 if (dwc->test_mode) {
934 int ret;
935
936 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
937 if (ret < 0) {
938 dev_err(dwc->dev, "invalid test #%d\n",
939 dwc->test_mode_nr);
940 dwc3_ep0_stall_and_restart(dwc);
941 return;
942 }
943 }
944
945 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
946 if (status == DWC3_TRBSTS_SETUP_PENDING)
947 dwc->setup_packet_pending = true;
948
949 dwc->ep0state = EP0_SETUP_PHASE;
950 dwc3_ep0_out_start(dwc);
951}
952
953static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
954 const struct dwc3_event_depevt *event)
955{
956 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
957
958 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
959 dep->resource_index = 0;
960 dwc->setup_packet_pending = false;
961
962 switch (dwc->ep0state) {
963 case EP0_SETUP_PHASE:
964 dwc3_ep0_inspect_setup(dwc, event);
965 break;
966
967 case EP0_DATA_PHASE:
968 dwc3_ep0_complete_data(dwc, event);
969 break;
970
971 case EP0_STATUS_PHASE:
972 dwc3_ep0_complete_status(dwc, event);
973 break;
974 default:
975 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
976 }
977}
978
979static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
980 struct dwc3_ep *dep, struct dwc3_request *req)
981{
982 unsigned int trb_length = 0;
983 int ret;
984
985 req->direction = !!dep->number;
986
987 if (req->request.length == 0) {
988 if (!req->direction)
989 trb_length = dep->endpoint.maxpacket;
990
991 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
992 DWC3_TRBCTL_CONTROL_DATA, false);
993 ret = dwc3_ep0_start_trans(dep);
994 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
995 && (dep->number == 0)) {
996 u32 maxpacket;
997 u32 rem;
998
999 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1000 &req->request, dep->number);
1001 if (ret)
1002 return;
1003
1004 maxpacket = dep->endpoint.maxpacket;
1005 rem = req->request.length % maxpacket;
1006 dwc->ep0_bounced = true;
1007
1008 /* prepare normal TRB */
1009 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1010 req->request.length,
1011 DWC3_TRBCTL_CONTROL_DATA,
1012 true);
1013
1014 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1015
1016 /* Now prepare one extra TRB to align transfer size */
1017 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1018 maxpacket - rem,
1019 DWC3_TRBCTL_CONTROL_DATA,
1020 false);
1021 ret = dwc3_ep0_start_trans(dep);
1022 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1023 req->request.length && req->request.zero) {
1024
1025 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1026 &req->request, dep->number);
1027 if (ret)
1028 return;
1029
1030 /* prepare normal TRB */
1031 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1032 req->request.length,
1033 DWC3_TRBCTL_CONTROL_DATA,
1034 true);
1035
1036 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1037
1038 if (!req->direction)
1039 trb_length = dep->endpoint.maxpacket;
1040
1041 /* Now prepare one extra TRB to align transfer size */
1042 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1043 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1044 false);
1045 ret = dwc3_ep0_start_trans(dep);
1046 } else {
1047 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1048 &req->request, dep->number);
1049 if (ret)
1050 return;
1051
1052 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1053 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1054 false);
1055
1056 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1057
1058 ret = dwc3_ep0_start_trans(dep);
1059 }
1060
1061 WARN_ON(ret < 0);
1062}
1063
1064static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1065{
1066 struct dwc3 *dwc = dep->dwc;
1067 u32 type;
1068
1069 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1070 : DWC3_TRBCTL_CONTROL_STATUS2;
1071
1072 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1073 return dwc3_ep0_start_trans(dep);
1074}
1075
1076static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1077{
1078 WARN_ON(dwc3_ep0_start_control_status(dep));
1079}
1080
1081static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1082 const struct dwc3_event_depevt *event)
1083{
1084 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1085
1086 __dwc3_ep0_do_control_status(dwc, dep);
1087}
1088
1089void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1090{
1091 unsigned int direction = !dwc->ep0_expect_in;
1092
1093 dwc->delayed_status = false;
1094 dwc->clear_stall_protocol = 0;
1095
1096 if (dwc->ep0state != EP0_STATUS_PHASE)
1097 return;
1098
1099 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1100}
1101
1102void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1103{
1104 struct dwc3_gadget_ep_cmd_params params;
1105 u32 cmd;
1106 int ret;
1107
1108 /*
1109 * For status/DATA OUT stage, TRB will be queued on ep0 out
1110 * endpoint for which resource index is zero. Hence allow
1111 * queuing ENDXFER command for ep0 out endpoint.
1112 */
1113 if (!dep->resource_index && dep->number)
1114 return;
1115
1116 cmd = DWC3_DEPCMD_ENDTRANSFER;
1117 cmd |= DWC3_DEPCMD_CMDIOC;
1118 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1119 memset(¶ms, 0, sizeof(params));
1120 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1121 WARN_ON_ONCE(ret);
1122 dep->resource_index = 0;
1123}
1124
1125static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1126 const struct dwc3_event_depevt *event)
1127{
1128 switch (event->status) {
1129 case DEPEVT_STATUS_CONTROL_DATA:
1130 if (!dwc->softconnect || !dwc->connected)
1131 return;
1132 /*
1133 * We already have a DATA transfer in the controller's cache,
1134 * if we receive a XferNotReady(DATA) we will ignore it, unless
1135 * it's for the wrong direction.
1136 *
1137 * In that case, we must issue END_TRANSFER command to the Data
1138 * Phase we already have started and issue SetStall on the
1139 * control endpoint.
1140 */
1141 if (dwc->ep0_expect_in != event->endpoint_number) {
1142 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1143
1144 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1145 dwc3_ep0_end_control_data(dwc, dep);
1146 dwc3_ep0_stall_and_restart(dwc);
1147 return;
1148 }
1149
1150 break;
1151
1152 case DEPEVT_STATUS_CONTROL_STATUS:
1153 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1154 return;
1155
1156 if (dwc->setup_packet_pending) {
1157 dwc3_ep0_stall_and_restart(dwc);
1158 return;
1159 }
1160
1161 dwc->ep0state = EP0_STATUS_PHASE;
1162
1163 if (dwc->delayed_status) {
1164 struct dwc3_ep *dep = dwc->eps[0];
1165
1166 WARN_ON_ONCE(event->endpoint_number != 1);
1167 /*
1168 * We should handle the delay STATUS phase here if the
1169 * request for handling delay STATUS has been queued
1170 * into the list.
1171 */
1172 if (!list_empty(&dep->pending_list)) {
1173 dwc->delayed_status = false;
1174 usb_gadget_set_state(dwc->gadget,
1175 USB_STATE_CONFIGURED);
1176 dwc3_ep0_do_control_status(dwc, event);
1177 }
1178
1179 return;
1180 }
1181
1182 dwc3_ep0_do_control_status(dwc, event);
1183 }
1184}
1185
1186void dwc3_ep0_interrupt(struct dwc3 *dwc,
1187 const struct dwc3_event_depevt *event)
1188{
1189 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1190 u8 cmd;
1191
1192 switch (event->endpoint_event) {
1193 case DWC3_DEPEVT_XFERCOMPLETE:
1194 dwc3_ep0_xfer_complete(dwc, event);
1195 break;
1196
1197 case DWC3_DEPEVT_XFERNOTREADY:
1198 dwc3_ep0_xfernotready(dwc, event);
1199 break;
1200
1201 case DWC3_DEPEVT_XFERINPROGRESS:
1202 case DWC3_DEPEVT_RXTXFIFOEVT:
1203 case DWC3_DEPEVT_STREAMEVT:
1204 break;
1205 case DWC3_DEPEVT_EPCMDCMPLT:
1206 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1207
1208 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1209 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1210 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1211 }
1212 break;
1213 default:
1214 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
1215 break;
1216 }
1217}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33
34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
36{
37 struct dwc3_trb *trb;
38 struct dwc3 *dwc;
39
40 dwc = dep->dwc;
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
42
43 if (chain)
44 dep->trb_enqueue++;
45
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
48 trb->size = len;
49 trb->ctrl = type;
50
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
53
54 if (chain)
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
56 else
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
58 | DWC3_TRB_CTRL_LST);
59
60 trace_dwc3_prepare_trb(dep, trb);
61}
62
63static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
64{
65 struct dwc3_gadget_ep_cmd_params params;
66 struct dwc3 *dwc;
67 int ret;
68
69 if (dep->flags & DWC3_EP_BUSY)
70 return 0;
71
72 dwc = dep->dwc;
73
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
77
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
79 if (ret < 0)
80 return ret;
81
82 dep->flags |= DWC3_EP_BUSY;
83 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
84 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
85
86 return 0;
87}
88
89static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
90 struct dwc3_request *req)
91{
92 struct dwc3 *dwc = dep->dwc;
93
94 req->request.actual = 0;
95 req->request.status = -EINPROGRESS;
96 req->epnum = dep->number;
97
98 list_add_tail(&req->list, &dep->pending_list);
99
100 /*
101 * Gadget driver might not be quick enough to queue a request
102 * before we get a Transfer Not Ready event on this endpoint.
103 *
104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
105 * flag is set, it's telling us that as soon as Gadget queues the
106 * required request, we should kick the transfer here because the
107 * IRQ we were waiting for is long gone.
108 */
109 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 unsigned direction;
111
112 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
113
114 if (dwc->ep0state != EP0_DATA_PHASE) {
115 dev_WARN(dwc->dev, "Unexpected pending request\n");
116 return 0;
117 }
118
119 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
120
121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
122 DWC3_EP0_DIR_IN);
123
124 return 0;
125 }
126
127 /*
128 * In case gadget driver asked us to delay the STATUS phase,
129 * handle it here.
130 */
131 if (dwc->delayed_status) {
132 unsigned direction;
133
134 direction = !dwc->ep0_expect_in;
135 dwc->delayed_status = false;
136 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
137
138 if (dwc->ep0state == EP0_STATUS_PHASE)
139 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
140
141 return 0;
142 }
143
144 /*
145 * Unfortunately we have uncovered a limitation wrt the Data Phase.
146 *
147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
148 * come before issueing Start Transfer command, but if we do, we will
149 * miss situations where the host starts another SETUP phase instead of
150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
151 * Layer Compliance Suite.
152 *
153 * The problem surfaces due to the fact that in case of back-to-back
154 * SETUP packets there will be no XferNotReady(DATA) generated and we
155 * will be stuck waiting for XferNotReady(DATA) forever.
156 *
157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
158 * it tells us to start Data Phase right away. It also mentions that if
159 * we receive a SETUP phase instead of the DATA phase, core will issue
160 * XferComplete for the DATA phase, before actually initiating it in
161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
162 * can only be used to print some debugging logs, as the core expects
163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
164 * just so it completes right away, without transferring anything and,
165 * only then, we can go back to the SETUP phase.
166 *
167 * Because of this scenario, SNPS decided to change the programming
168 * model of control transfers and support on-demand transfers only for
169 * the STATUS phase. To fix the issue we have now, we will always wait
170 * for gadget driver to queue the DATA phase's struct usb_request, then
171 * start it right away.
172 *
173 * If we're actually in a 2-stage transfer, we will wait for
174 * XferNotReady(STATUS).
175 */
176 if (dwc->three_stage_setup) {
177 unsigned direction;
178
179 direction = dwc->ep0_expect_in;
180 dwc->ep0state = EP0_DATA_PHASE;
181
182 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
183
184 dep->flags &= ~DWC3_EP0_DIR_IN;
185 }
186
187 return 0;
188}
189
190int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 gfp_t gfp_flags)
192{
193 struct dwc3_request *req = to_dwc3_request(request);
194 struct dwc3_ep *dep = to_dwc3_ep(ep);
195 struct dwc3 *dwc = dep->dwc;
196
197 unsigned long flags;
198
199 int ret;
200
201 spin_lock_irqsave(&dwc->lock, flags);
202 if (!dep->endpoint.desc) {
203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
204 dep->name);
205 ret = -ESHUTDOWN;
206 goto out;
207 }
208
209 /* we share one TRB for ep0/1 */
210 if (!list_empty(&dep->pending_list)) {
211 ret = -EBUSY;
212 goto out;
213 }
214
215 ret = __dwc3_gadget_ep0_queue(dep, req);
216
217out:
218 spin_unlock_irqrestore(&dwc->lock, flags);
219
220 return ret;
221}
222
223static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
224{
225 struct dwc3_ep *dep;
226
227 /* reinitialize physical ep1 */
228 dep = dwc->eps[1];
229 dep->flags = DWC3_EP_ENABLED;
230
231 /* stall is always issued on EP0 */
232 dep = dwc->eps[0];
233 __dwc3_gadget_ep_set_halt(dep, 1, false);
234 dep->flags = DWC3_EP_ENABLED;
235 dwc->delayed_status = false;
236
237 if (!list_empty(&dep->pending_list)) {
238 struct dwc3_request *req;
239
240 req = next_request(&dep->pending_list);
241 dwc3_gadget_giveback(dep, req, -ECONNRESET);
242 }
243
244 dwc->ep0state = EP0_SETUP_PHASE;
245 dwc3_ep0_out_start(dwc);
246}
247
248int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
249{
250 struct dwc3_ep *dep = to_dwc3_ep(ep);
251 struct dwc3 *dwc = dep->dwc;
252
253 dwc3_ep0_stall_and_restart(dwc);
254
255 return 0;
256}
257
258int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
259{
260 struct dwc3_ep *dep = to_dwc3_ep(ep);
261 struct dwc3 *dwc = dep->dwc;
262 unsigned long flags;
263 int ret;
264
265 spin_lock_irqsave(&dwc->lock, flags);
266 ret = __dwc3_gadget_ep0_set_halt(ep, value);
267 spin_unlock_irqrestore(&dwc->lock, flags);
268
269 return ret;
270}
271
272void dwc3_ep0_out_start(struct dwc3 *dwc)
273{
274 struct dwc3_ep *dep;
275 int ret;
276
277 complete(&dwc->ep0_in_setup);
278
279 dep = dwc->eps[0];
280 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
281 DWC3_TRBCTL_CONTROL_SETUP, false);
282 ret = dwc3_ep0_start_trans(dep);
283 WARN_ON(ret < 0);
284}
285
286static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
287{
288 struct dwc3_ep *dep;
289 u32 windex = le16_to_cpu(wIndex_le);
290 u32 epnum;
291
292 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
293 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
294 epnum |= 1;
295
296 dep = dwc->eps[epnum];
297 if (dep->flags & DWC3_EP_ENABLED)
298 return dep;
299
300 return NULL;
301}
302
303static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
304{
305}
306/*
307 * ch 9.4.5
308 */
309static int dwc3_ep0_handle_status(struct dwc3 *dwc,
310 struct usb_ctrlrequest *ctrl)
311{
312 struct dwc3_ep *dep;
313 u32 recip;
314 u32 value;
315 u32 reg;
316 u16 usb_status = 0;
317 __le16 *response_pkt;
318
319 /* We don't support PTM_STATUS */
320 value = le16_to_cpu(ctrl->wValue);
321 if (value != 0)
322 return -EINVAL;
323
324 recip = ctrl->bRequestType & USB_RECIP_MASK;
325 switch (recip) {
326 case USB_RECIP_DEVICE:
327 /*
328 * LTM will be set once we know how to set this in HW.
329 */
330 usb_status |= dwc->gadget.is_selfpowered;
331
332 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
333 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
334 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
335 if (reg & DWC3_DCTL_INITU1ENA)
336 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
337 if (reg & DWC3_DCTL_INITU2ENA)
338 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
339 }
340
341 break;
342
343 case USB_RECIP_INTERFACE:
344 /*
345 * Function Remote Wake Capable D0
346 * Function Remote Wakeup D1
347 */
348 break;
349
350 case USB_RECIP_ENDPOINT:
351 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
352 if (!dep)
353 return -EINVAL;
354
355 if (dep->flags & DWC3_EP_STALL)
356 usb_status = 1 << USB_ENDPOINT_HALT;
357 break;
358 default:
359 return -EINVAL;
360 }
361
362 response_pkt = (__le16 *) dwc->setup_buf;
363 *response_pkt = cpu_to_le16(usb_status);
364
365 dep = dwc->eps[0];
366 dwc->ep0_usb_req.dep = dep;
367 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
368 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
369 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
370
371 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
372}
373
374static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
375 int set)
376{
377 u32 reg;
378
379 if (state != USB_STATE_CONFIGURED)
380 return -EINVAL;
381 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
382 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
383 return -EINVAL;
384
385 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
386 if (set)
387 reg |= DWC3_DCTL_INITU1ENA;
388 else
389 reg &= ~DWC3_DCTL_INITU1ENA;
390 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
391
392 return 0;
393}
394
395static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
396 int set)
397{
398 u32 reg;
399
400
401 if (state != USB_STATE_CONFIGURED)
402 return -EINVAL;
403 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
404 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
405 return -EINVAL;
406
407 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
408 if (set)
409 reg |= DWC3_DCTL_INITU2ENA;
410 else
411 reg &= ~DWC3_DCTL_INITU2ENA;
412 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
413
414 return 0;
415}
416
417static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
418 u32 wIndex, int set)
419{
420 if ((wIndex & 0xff) != 0)
421 return -EINVAL;
422 if (!set)
423 return -EINVAL;
424
425 switch (wIndex >> 8) {
426 case TEST_J:
427 case TEST_K:
428 case TEST_SE0_NAK:
429 case TEST_PACKET:
430 case TEST_FORCE_EN:
431 dwc->test_mode_nr = wIndex >> 8;
432 dwc->test_mode = true;
433 break;
434 default:
435 return -EINVAL;
436 }
437
438 return 0;
439}
440
441static int dwc3_ep0_handle_device(struct dwc3 *dwc,
442 struct usb_ctrlrequest *ctrl, int set)
443{
444 enum usb_device_state state;
445 u32 wValue;
446 u32 wIndex;
447 int ret = 0;
448
449 wValue = le16_to_cpu(ctrl->wValue);
450 wIndex = le16_to_cpu(ctrl->wIndex);
451 state = dwc->gadget.state;
452
453 switch (wValue) {
454 case USB_DEVICE_REMOTE_WAKEUP:
455 break;
456 /*
457 * 9.4.1 says only only for SS, in AddressState only for
458 * default control pipe
459 */
460 case USB_DEVICE_U1_ENABLE:
461 ret = dwc3_ep0_handle_u1(dwc, state, set);
462 break;
463 case USB_DEVICE_U2_ENABLE:
464 ret = dwc3_ep0_handle_u2(dwc, state, set);
465 break;
466 case USB_DEVICE_LTM_ENABLE:
467 ret = -EINVAL;
468 break;
469 case USB_DEVICE_TEST_MODE:
470 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
471 break;
472 default:
473 ret = -EINVAL;
474 }
475
476 return ret;
477}
478
479static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
480 struct usb_ctrlrequest *ctrl, int set)
481{
482 u32 wValue;
483 int ret = 0;
484
485 wValue = le16_to_cpu(ctrl->wValue);
486
487 switch (wValue) {
488 case USB_INTRF_FUNC_SUSPEND:
489 /*
490 * REVISIT: Ideally we would enable some low power mode here,
491 * however it's unclear what we should be doing here.
492 *
493 * For now, we're not doing anything, just making sure we return
494 * 0 so USB Command Verifier tests pass without any errors.
495 */
496 break;
497 default:
498 ret = -EINVAL;
499 }
500
501 return ret;
502}
503
504static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
505 struct usb_ctrlrequest *ctrl, int set)
506{
507 struct dwc3_ep *dep;
508 u32 wValue;
509 int ret;
510
511 wValue = le16_to_cpu(ctrl->wValue);
512
513 switch (wValue) {
514 case USB_ENDPOINT_HALT:
515 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
516 if (!dep)
517 return -EINVAL;
518
519 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
520 break;
521
522 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
523 if (ret)
524 return -EINVAL;
525 break;
526 default:
527 return -EINVAL;
528 }
529
530 return 0;
531}
532
533static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
534 struct usb_ctrlrequest *ctrl, int set)
535{
536 u32 recip;
537 int ret;
538
539 recip = ctrl->bRequestType & USB_RECIP_MASK;
540
541 switch (recip) {
542 case USB_RECIP_DEVICE:
543 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
544 break;
545 case USB_RECIP_INTERFACE:
546 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
547 break;
548 case USB_RECIP_ENDPOINT:
549 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
550 break;
551 default:
552 ret = -EINVAL;
553 }
554
555 return ret;
556}
557
558static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
559{
560 enum usb_device_state state = dwc->gadget.state;
561 u32 addr;
562 u32 reg;
563
564 addr = le16_to_cpu(ctrl->wValue);
565 if (addr > 127) {
566 dev_err(dwc->dev, "invalid device address %d\n", addr);
567 return -EINVAL;
568 }
569
570 if (state == USB_STATE_CONFIGURED) {
571 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
572 return -EINVAL;
573 }
574
575 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
576 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
577 reg |= DWC3_DCFG_DEVADDR(addr);
578 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
579
580 if (addr)
581 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
582 else
583 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
584
585 return 0;
586}
587
588static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
589{
590 int ret;
591
592 spin_unlock(&dwc->lock);
593 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
594 spin_lock(&dwc->lock);
595 return ret;
596}
597
598static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
599{
600 enum usb_device_state state = dwc->gadget.state;
601 u32 cfg;
602 int ret;
603 u32 reg;
604
605 cfg = le16_to_cpu(ctrl->wValue);
606
607 switch (state) {
608 case USB_STATE_DEFAULT:
609 return -EINVAL;
610
611 case USB_STATE_ADDRESS:
612 ret = dwc3_ep0_delegate_req(dwc, ctrl);
613 /* if the cfg matches and the cfg is non zero */
614 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
615
616 /*
617 * only change state if set_config has already
618 * been processed. If gadget driver returns
619 * USB_GADGET_DELAYED_STATUS, we will wait
620 * to change the state on the next usb_ep_queue()
621 */
622 if (ret == 0)
623 usb_gadget_set_state(&dwc->gadget,
624 USB_STATE_CONFIGURED);
625
626 /*
627 * Enable transition to U1/U2 state when
628 * nothing is pending from application.
629 */
630 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
631 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
632 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
633 }
634 break;
635
636 case USB_STATE_CONFIGURED:
637 ret = dwc3_ep0_delegate_req(dwc, ctrl);
638 if (!cfg && !ret)
639 usb_gadget_set_state(&dwc->gadget,
640 USB_STATE_ADDRESS);
641 break;
642 default:
643 ret = -EINVAL;
644 }
645 return ret;
646}
647
648static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
649{
650 struct dwc3_ep *dep = to_dwc3_ep(ep);
651 struct dwc3 *dwc = dep->dwc;
652
653 u32 param = 0;
654 u32 reg;
655
656 struct timing {
657 u8 u1sel;
658 u8 u1pel;
659 __le16 u2sel;
660 __le16 u2pel;
661 } __packed timing;
662
663 int ret;
664
665 memcpy(&timing, req->buf, sizeof(timing));
666
667 dwc->u1sel = timing.u1sel;
668 dwc->u1pel = timing.u1pel;
669 dwc->u2sel = le16_to_cpu(timing.u2sel);
670 dwc->u2pel = le16_to_cpu(timing.u2pel);
671
672 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
673 if (reg & DWC3_DCTL_INITU2ENA)
674 param = dwc->u2pel;
675 if (reg & DWC3_DCTL_INITU1ENA)
676 param = dwc->u1pel;
677
678 /*
679 * According to Synopsys Databook, if parameter is
680 * greater than 125, a value of zero should be
681 * programmed in the register.
682 */
683 if (param > 125)
684 param = 0;
685
686 /* now that we have the time, issue DGCMD Set Sel */
687 ret = dwc3_send_gadget_generic_command(dwc,
688 DWC3_DGCMD_SET_PERIODIC_PAR, param);
689 WARN_ON(ret < 0);
690}
691
692static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
693{
694 struct dwc3_ep *dep;
695 enum usb_device_state state = dwc->gadget.state;
696 u16 wLength;
697
698 if (state == USB_STATE_DEFAULT)
699 return -EINVAL;
700
701 wLength = le16_to_cpu(ctrl->wLength);
702
703 if (wLength != 6) {
704 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
705 wLength);
706 return -EINVAL;
707 }
708
709 /*
710 * To handle Set SEL we need to receive 6 bytes from Host. So let's
711 * queue a usb_request for 6 bytes.
712 *
713 * Remember, though, this controller can't handle non-wMaxPacketSize
714 * aligned transfers on the OUT direction, so we queue a request for
715 * wMaxPacketSize instead.
716 */
717 dep = dwc->eps[0];
718 dwc->ep0_usb_req.dep = dep;
719 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
720 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
721 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
722
723 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
724}
725
726static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
727{
728 u16 wLength;
729 u16 wValue;
730 u16 wIndex;
731
732 wValue = le16_to_cpu(ctrl->wValue);
733 wLength = le16_to_cpu(ctrl->wLength);
734 wIndex = le16_to_cpu(ctrl->wIndex);
735
736 if (wIndex || wLength)
737 return -EINVAL;
738
739 dwc->gadget.isoch_delay = wValue;
740
741 return 0;
742}
743
744static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
745{
746 int ret;
747
748 switch (ctrl->bRequest) {
749 case USB_REQ_GET_STATUS:
750 ret = dwc3_ep0_handle_status(dwc, ctrl);
751 break;
752 case USB_REQ_CLEAR_FEATURE:
753 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
754 break;
755 case USB_REQ_SET_FEATURE:
756 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
757 break;
758 case USB_REQ_SET_ADDRESS:
759 ret = dwc3_ep0_set_address(dwc, ctrl);
760 break;
761 case USB_REQ_SET_CONFIGURATION:
762 ret = dwc3_ep0_set_config(dwc, ctrl);
763 break;
764 case USB_REQ_SET_SEL:
765 ret = dwc3_ep0_set_sel(dwc, ctrl);
766 break;
767 case USB_REQ_SET_ISOCH_DELAY:
768 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
769 break;
770 default:
771 ret = dwc3_ep0_delegate_req(dwc, ctrl);
772 break;
773 }
774
775 return ret;
776}
777
778static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
779 const struct dwc3_event_depevt *event)
780{
781 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
782 int ret = -EINVAL;
783 u32 len;
784
785 if (!dwc->gadget_driver)
786 goto out;
787
788 trace_dwc3_ctrl_req(ctrl);
789
790 len = le16_to_cpu(ctrl->wLength);
791 if (!len) {
792 dwc->three_stage_setup = false;
793 dwc->ep0_expect_in = false;
794 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
795 } else {
796 dwc->three_stage_setup = true;
797 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
798 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
799 }
800
801 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
802 ret = dwc3_ep0_std_request(dwc, ctrl);
803 else
804 ret = dwc3_ep0_delegate_req(dwc, ctrl);
805
806 if (ret == USB_GADGET_DELAYED_STATUS)
807 dwc->delayed_status = true;
808
809out:
810 if (ret < 0)
811 dwc3_ep0_stall_and_restart(dwc);
812}
813
814static void dwc3_ep0_complete_data(struct dwc3 *dwc,
815 const struct dwc3_event_depevt *event)
816{
817 struct dwc3_request *r;
818 struct usb_request *ur;
819 struct dwc3_trb *trb;
820 struct dwc3_ep *ep0;
821 u32 transferred = 0;
822 u32 status;
823 u32 length;
824 u8 epnum;
825
826 epnum = event->endpoint_number;
827 ep0 = dwc->eps[0];
828
829 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
830 trb = dwc->ep0_trb;
831 trace_dwc3_complete_trb(ep0, trb);
832
833 r = next_request(&ep0->pending_list);
834 if (!r)
835 return;
836
837 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
838 if (status == DWC3_TRBSTS_SETUP_PENDING) {
839 dwc->setup_packet_pending = true;
840 if (r)
841 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
842
843 return;
844 }
845
846 ur = &r->request;
847
848 length = trb->size & DWC3_TRB_SIZE_MASK;
849 transferred = ur->length - length;
850 ur->actual += transferred;
851
852 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
853 ur->length && ur->zero) || dwc->ep0_bounced) {
854 trb++;
855 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
856 trace_dwc3_complete_trb(ep0, trb);
857
858 if (r->direction)
859 dwc->eps[1]->trb_enqueue = 0;
860 else
861 dwc->eps[0]->trb_enqueue = 0;
862
863 dwc->ep0_bounced = false;
864 }
865
866 if ((epnum & 1) && ur->actual < ur->length)
867 dwc3_ep0_stall_and_restart(dwc);
868 else
869 dwc3_gadget_giveback(ep0, r, 0);
870}
871
872static void dwc3_ep0_complete_status(struct dwc3 *dwc,
873 const struct dwc3_event_depevt *event)
874{
875 struct dwc3_request *r;
876 struct dwc3_ep *dep;
877 struct dwc3_trb *trb;
878 u32 status;
879
880 dep = dwc->eps[0];
881 trb = dwc->ep0_trb;
882
883 trace_dwc3_complete_trb(dep, trb);
884
885 if (!list_empty(&dep->pending_list)) {
886 r = next_request(&dep->pending_list);
887
888 dwc3_gadget_giveback(dep, r, 0);
889 }
890
891 if (dwc->test_mode) {
892 int ret;
893
894 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
895 if (ret < 0) {
896 dev_err(dwc->dev, "invalid test #%d\n",
897 dwc->test_mode_nr);
898 dwc3_ep0_stall_and_restart(dwc);
899 return;
900 }
901 }
902
903 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
904 if (status == DWC3_TRBSTS_SETUP_PENDING)
905 dwc->setup_packet_pending = true;
906
907 dwc->ep0state = EP0_SETUP_PHASE;
908 dwc3_ep0_out_start(dwc);
909}
910
911static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
912 const struct dwc3_event_depevt *event)
913{
914 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
915
916 dep->flags &= ~DWC3_EP_BUSY;
917 dep->resource_index = 0;
918 dwc->setup_packet_pending = false;
919
920 switch (dwc->ep0state) {
921 case EP0_SETUP_PHASE:
922 dwc3_ep0_inspect_setup(dwc, event);
923 break;
924
925 case EP0_DATA_PHASE:
926 dwc3_ep0_complete_data(dwc, event);
927 break;
928
929 case EP0_STATUS_PHASE:
930 dwc3_ep0_complete_status(dwc, event);
931 break;
932 default:
933 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
934 }
935}
936
937static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
938 struct dwc3_ep *dep, struct dwc3_request *req)
939{
940 int ret;
941
942 req->direction = !!dep->number;
943
944 if (req->request.length == 0) {
945 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0,
946 DWC3_TRBCTL_CONTROL_DATA, false);
947 ret = dwc3_ep0_start_trans(dep);
948 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
949 && (dep->number == 0)) {
950 u32 maxpacket;
951 u32 rem;
952
953 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
954 &req->request, dep->number);
955 if (ret)
956 return;
957
958 maxpacket = dep->endpoint.maxpacket;
959 rem = req->request.length % maxpacket;
960 dwc->ep0_bounced = true;
961
962 /* prepare normal TRB */
963 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
964 req->request.length,
965 DWC3_TRBCTL_CONTROL_DATA,
966 true);
967
968 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
969
970 /* Now prepare one extra TRB to align transfer size */
971 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
972 maxpacket - rem,
973 DWC3_TRBCTL_CONTROL_DATA,
974 false);
975 ret = dwc3_ep0_start_trans(dep);
976 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
977 req->request.length && req->request.zero) {
978 u32 maxpacket;
979
980 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
981 &req->request, dep->number);
982 if (ret)
983 return;
984
985 maxpacket = dep->endpoint.maxpacket;
986
987 /* prepare normal TRB */
988 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
989 req->request.length,
990 DWC3_TRBCTL_CONTROL_DATA,
991 true);
992
993 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
994
995 /* Now prepare one extra TRB to align transfer size */
996 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
997 0, DWC3_TRBCTL_CONTROL_DATA,
998 false);
999 ret = dwc3_ep0_start_trans(dep);
1000 } else {
1001 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1002 &req->request, dep->number);
1003 if (ret)
1004 return;
1005
1006 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1007 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1008 false);
1009
1010 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1011
1012 ret = dwc3_ep0_start_trans(dep);
1013 }
1014
1015 WARN_ON(ret < 0);
1016}
1017
1018static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1019{
1020 struct dwc3 *dwc = dep->dwc;
1021 u32 type;
1022
1023 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1024 : DWC3_TRBCTL_CONTROL_STATUS2;
1025
1026 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1027 return dwc3_ep0_start_trans(dep);
1028}
1029
1030static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1031{
1032 WARN_ON(dwc3_ep0_start_control_status(dep));
1033}
1034
1035static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1036 const struct dwc3_event_depevt *event)
1037{
1038 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1039
1040 __dwc3_ep0_do_control_status(dwc, dep);
1041}
1042
1043static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1044{
1045 struct dwc3_gadget_ep_cmd_params params;
1046 u32 cmd;
1047 int ret;
1048
1049 if (!dep->resource_index)
1050 return;
1051
1052 cmd = DWC3_DEPCMD_ENDTRANSFER;
1053 cmd |= DWC3_DEPCMD_CMDIOC;
1054 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1055 memset(¶ms, 0, sizeof(params));
1056 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1057 WARN_ON_ONCE(ret);
1058 dep->resource_index = 0;
1059}
1060
1061static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1062 const struct dwc3_event_depevt *event)
1063{
1064 switch (event->status) {
1065 case DEPEVT_STATUS_CONTROL_DATA:
1066 /*
1067 * We already have a DATA transfer in the controller's cache,
1068 * if we receive a XferNotReady(DATA) we will ignore it, unless
1069 * it's for the wrong direction.
1070 *
1071 * In that case, we must issue END_TRANSFER command to the Data
1072 * Phase we already have started and issue SetStall on the
1073 * control endpoint.
1074 */
1075 if (dwc->ep0_expect_in != event->endpoint_number) {
1076 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1077
1078 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1079 dwc3_ep0_end_control_data(dwc, dep);
1080 dwc3_ep0_stall_and_restart(dwc);
1081 return;
1082 }
1083
1084 break;
1085
1086 case DEPEVT_STATUS_CONTROL_STATUS:
1087 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1088 return;
1089
1090 dwc->ep0state = EP0_STATUS_PHASE;
1091
1092 if (dwc->delayed_status) {
1093 struct dwc3_ep *dep = dwc->eps[0];
1094
1095 WARN_ON_ONCE(event->endpoint_number != 1);
1096 /*
1097 * We should handle the delay STATUS phase here if the
1098 * request for handling delay STATUS has been queued
1099 * into the list.
1100 */
1101 if (!list_empty(&dep->pending_list)) {
1102 dwc->delayed_status = false;
1103 usb_gadget_set_state(&dwc->gadget,
1104 USB_STATE_CONFIGURED);
1105 dwc3_ep0_do_control_status(dwc, event);
1106 }
1107
1108 return;
1109 }
1110
1111 dwc3_ep0_do_control_status(dwc, event);
1112 }
1113}
1114
1115void dwc3_ep0_interrupt(struct dwc3 *dwc,
1116 const struct dwc3_event_depevt *event)
1117{
1118 switch (event->endpoint_event) {
1119 case DWC3_DEPEVT_XFERCOMPLETE:
1120 dwc3_ep0_xfer_complete(dwc, event);
1121 break;
1122
1123 case DWC3_DEPEVT_XFERNOTREADY:
1124 dwc3_ep0_xfernotready(dwc, event);
1125 break;
1126
1127 case DWC3_DEPEVT_XFERINPROGRESS:
1128 case DWC3_DEPEVT_RXTXFIFOEVT:
1129 case DWC3_DEPEVT_STREAMEVT:
1130 case DWC3_DEPEVT_EPCMDCMPLT:
1131 break;
1132 }
1133}