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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
34 struct usb_ctrlrequest *ctrl);
35
36static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
37 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
38{
39 struct dwc3_trb *trb;
40 struct dwc3 *dwc;
41
42 dwc = dep->dwc;
43 trb = &dwc->ep0_trb[dep->trb_enqueue];
44
45 if (chain)
46 dep->trb_enqueue++;
47
48 trb->bpl = lower_32_bits(buf_dma);
49 trb->bph = upper_32_bits(buf_dma);
50 trb->size = len;
51 trb->ctrl = type;
52
53 trb->ctrl |= (DWC3_TRB_CTRL_HWO
54 | DWC3_TRB_CTRL_ISP_IMI);
55
56 if (chain)
57 trb->ctrl |= DWC3_TRB_CTRL_CHN;
58 else
59 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 | DWC3_TRB_CTRL_LST);
61
62 trace_dwc3_prepare_trb(dep, trb);
63}
64
65static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
66{
67 struct dwc3_gadget_ep_cmd_params params;
68 struct dwc3 *dwc;
69 int ret;
70
71 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
72 return 0;
73
74 dwc = dep->dwc;
75
76 memset(¶ms, 0, sizeof(params));
77 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
78 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
79
80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
81 if (ret < 0)
82 return ret;
83
84 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
85
86 return 0;
87}
88
89static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
90 struct dwc3_request *req)
91{
92 struct dwc3 *dwc = dep->dwc;
93
94 req->request.actual = 0;
95 req->request.status = -EINPROGRESS;
96 req->epnum = dep->number;
97
98 list_add_tail(&req->list, &dep->pending_list);
99
100 /*
101 * Gadget driver might not be quick enough to queue a request
102 * before we get a Transfer Not Ready event on this endpoint.
103 *
104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
105 * flag is set, it's telling us that as soon as Gadget queues the
106 * required request, we should kick the transfer here because the
107 * IRQ we were waiting for is long gone.
108 */
109 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 unsigned int direction;
111
112 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
113
114 if (dwc->ep0state != EP0_DATA_PHASE) {
115 dev_WARN(dwc->dev, "Unexpected pending request\n");
116 return 0;
117 }
118
119 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
120
121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
122 DWC3_EP0_DIR_IN);
123
124 return 0;
125 }
126
127 /*
128 * In case gadget driver asked us to delay the STATUS phase,
129 * handle it here.
130 */
131 if (dwc->delayed_status) {
132 unsigned int direction;
133
134 direction = !dwc->ep0_expect_in;
135 dwc->delayed_status = false;
136 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
137
138 if (dwc->ep0state == EP0_STATUS_PHASE)
139 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
140
141 return 0;
142 }
143
144 /*
145 * Unfortunately we have uncovered a limitation wrt the Data Phase.
146 *
147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
148 * come before issueing Start Transfer command, but if we do, we will
149 * miss situations where the host starts another SETUP phase instead of
150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
151 * Layer Compliance Suite.
152 *
153 * The problem surfaces due to the fact that in case of back-to-back
154 * SETUP packets there will be no XferNotReady(DATA) generated and we
155 * will be stuck waiting for XferNotReady(DATA) forever.
156 *
157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
158 * it tells us to start Data Phase right away. It also mentions that if
159 * we receive a SETUP phase instead of the DATA phase, core will issue
160 * XferComplete for the DATA phase, before actually initiating it in
161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
162 * can only be used to print some debugging logs, as the core expects
163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
164 * just so it completes right away, without transferring anything and,
165 * only then, we can go back to the SETUP phase.
166 *
167 * Because of this scenario, SNPS decided to change the programming
168 * model of control transfers and support on-demand transfers only for
169 * the STATUS phase. To fix the issue we have now, we will always wait
170 * for gadget driver to queue the DATA phase's struct usb_request, then
171 * start it right away.
172 *
173 * If we're actually in a 2-stage transfer, we will wait for
174 * XferNotReady(STATUS).
175 */
176 if (dwc->three_stage_setup) {
177 unsigned int direction;
178
179 direction = dwc->ep0_expect_in;
180 dwc->ep0state = EP0_DATA_PHASE;
181
182 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
183
184 dep->flags &= ~DWC3_EP0_DIR_IN;
185 }
186
187 return 0;
188}
189
190int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 gfp_t gfp_flags)
192{
193 struct dwc3_request *req = to_dwc3_request(request);
194 struct dwc3_ep *dep = to_dwc3_ep(ep);
195 struct dwc3 *dwc = dep->dwc;
196
197 unsigned long flags;
198
199 int ret;
200
201 spin_lock_irqsave(&dwc->lock, flags);
202 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
204 dep->name);
205 ret = -ESHUTDOWN;
206 goto out;
207 }
208
209 /* we share one TRB for ep0/1 */
210 if (!list_empty(&dep->pending_list)) {
211 ret = -EBUSY;
212 goto out;
213 }
214
215 ret = __dwc3_gadget_ep0_queue(dep, req);
216
217out:
218 spin_unlock_irqrestore(&dwc->lock, flags);
219
220 return ret;
221}
222
223void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
224{
225 struct dwc3_ep *dep;
226
227 /* reinitialize physical ep1 */
228 dep = dwc->eps[1];
229 dep->flags = DWC3_EP_ENABLED;
230
231 /* stall is always issued on EP0 */
232 dep = dwc->eps[0];
233 __dwc3_gadget_ep_set_halt(dep, 1, false);
234 dep->flags = DWC3_EP_ENABLED;
235 dwc->delayed_status = false;
236
237 if (!list_empty(&dep->pending_list)) {
238 struct dwc3_request *req;
239
240 req = next_request(&dep->pending_list);
241 if (!dwc->connected)
242 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
243 else
244 dwc3_gadget_giveback(dep, req, -ECONNRESET);
245 }
246
247 dwc->eps[0]->trb_enqueue = 0;
248 dwc->eps[1]->trb_enqueue = 0;
249 dwc->ep0state = EP0_SETUP_PHASE;
250 dwc3_ep0_out_start(dwc);
251}
252
253int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
254{
255 struct dwc3_ep *dep = to_dwc3_ep(ep);
256 struct dwc3 *dwc = dep->dwc;
257
258 dwc3_ep0_stall_and_restart(dwc);
259
260 return 0;
261}
262
263int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
264{
265 struct dwc3_ep *dep = to_dwc3_ep(ep);
266 struct dwc3 *dwc = dep->dwc;
267 unsigned long flags;
268 int ret;
269
270 spin_lock_irqsave(&dwc->lock, flags);
271 ret = __dwc3_gadget_ep0_set_halt(ep, value);
272 spin_unlock_irqrestore(&dwc->lock, flags);
273
274 return ret;
275}
276
277void dwc3_ep0_out_start(struct dwc3 *dwc)
278{
279 struct dwc3_ep *dep;
280 int ret;
281 int i;
282
283 complete(&dwc->ep0_in_setup);
284
285 dep = dwc->eps[0];
286 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
287 DWC3_TRBCTL_CONTROL_SETUP, false);
288 ret = dwc3_ep0_start_trans(dep);
289 WARN_ON(ret < 0);
290 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
291 struct dwc3_ep *dwc3_ep;
292
293 dwc3_ep = dwc->eps[i];
294 if (!dwc3_ep)
295 continue;
296
297 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
298 continue;
299
300 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
301 if (dwc->connected)
302 dwc3_stop_active_transfer(dwc3_ep, true, true);
303 else
304 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
305 }
306}
307
308static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
309{
310 struct dwc3_ep *dep;
311 u32 windex = le16_to_cpu(wIndex_le);
312 u32 epnum;
313
314 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
315 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
316 epnum |= 1;
317
318 dep = dwc->eps[epnum];
319 if (dep == NULL)
320 return NULL;
321
322 if (dep->flags & DWC3_EP_ENABLED)
323 return dep;
324
325 return NULL;
326}
327
328static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
329{
330}
331/*
332 * ch 9.4.5
333 */
334static int dwc3_ep0_handle_status(struct dwc3 *dwc,
335 struct usb_ctrlrequest *ctrl)
336{
337 struct dwc3_ep *dep;
338 u32 recip;
339 u32 value;
340 u32 reg;
341 u16 usb_status = 0;
342 __le16 *response_pkt;
343
344 /* We don't support PTM_STATUS */
345 value = le16_to_cpu(ctrl->wValue);
346 if (value != 0)
347 return -EINVAL;
348
349 recip = ctrl->bRequestType & USB_RECIP_MASK;
350 switch (recip) {
351 case USB_RECIP_DEVICE:
352 /*
353 * LTM will be set once we know how to set this in HW.
354 */
355 usb_status |= dwc->gadget->is_selfpowered;
356
357 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
358 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
359 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
360 if (reg & DWC3_DCTL_INITU1ENA)
361 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
362 if (reg & DWC3_DCTL_INITU2ENA)
363 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
364 } else {
365 usb_status |= dwc->gadget->wakeup_armed <<
366 USB_DEVICE_REMOTE_WAKEUP;
367 }
368
369 break;
370
371 case USB_RECIP_INTERFACE:
372 /*
373 * Function Remote Wake Capable D0
374 * Function Remote Wakeup D1
375 */
376 return dwc3_ep0_delegate_req(dwc, ctrl);
377
378 case USB_RECIP_ENDPOINT:
379 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
380 if (!dep)
381 return -EINVAL;
382
383 if (dep->flags & DWC3_EP_STALL)
384 usb_status = 1 << USB_ENDPOINT_HALT;
385 break;
386 default:
387 return -EINVAL;
388 }
389
390 response_pkt = (__le16 *) dwc->setup_buf;
391 *response_pkt = cpu_to_le16(usb_status);
392
393 dep = dwc->eps[0];
394 dwc->ep0_usb_req.dep = dep;
395 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
396 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
397 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
398
399 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
400}
401
402static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
403 int set)
404{
405 u32 reg;
406
407 if (state != USB_STATE_CONFIGURED)
408 return -EINVAL;
409 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
410 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
411 return -EINVAL;
412 if (set && dwc->dis_u1_entry_quirk)
413 return -EINVAL;
414
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
416 if (set)
417 reg |= DWC3_DCTL_INITU1ENA;
418 else
419 reg &= ~DWC3_DCTL_INITU1ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
421
422 return 0;
423}
424
425static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
426 int set)
427{
428 u32 reg;
429
430
431 if (state != USB_STATE_CONFIGURED)
432 return -EINVAL;
433 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
434 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
435 return -EINVAL;
436 if (set && dwc->dis_u2_entry_quirk)
437 return -EINVAL;
438
439 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
440 if (set)
441 reg |= DWC3_DCTL_INITU2ENA;
442 else
443 reg &= ~DWC3_DCTL_INITU2ENA;
444 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
445
446 return 0;
447}
448
449static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
450 u32 wIndex, int set)
451{
452 if ((wIndex & 0xff) != 0)
453 return -EINVAL;
454 if (!set)
455 return -EINVAL;
456
457 switch (wIndex >> 8) {
458 case USB_TEST_J:
459 case USB_TEST_K:
460 case USB_TEST_SE0_NAK:
461 case USB_TEST_PACKET:
462 case USB_TEST_FORCE_ENABLE:
463 dwc->test_mode_nr = wIndex >> 8;
464 dwc->test_mode = true;
465 break;
466 default:
467 return -EINVAL;
468 }
469
470 return 0;
471}
472
473static int dwc3_ep0_handle_device(struct dwc3 *dwc,
474 struct usb_ctrlrequest *ctrl, int set)
475{
476 enum usb_device_state state;
477 u32 wValue;
478 u32 wIndex;
479 int ret = 0;
480
481 wValue = le16_to_cpu(ctrl->wValue);
482 wIndex = le16_to_cpu(ctrl->wIndex);
483 state = dwc->gadget->state;
484
485 switch (wValue) {
486 case USB_DEVICE_REMOTE_WAKEUP:
487 if (dwc->wakeup_configured)
488 dwc->gadget->wakeup_armed = set;
489 else
490 ret = -EINVAL;
491 break;
492 /*
493 * 9.4.1 says only for SS, in AddressState only for
494 * default control pipe
495 */
496 case USB_DEVICE_U1_ENABLE:
497 ret = dwc3_ep0_handle_u1(dwc, state, set);
498 break;
499 case USB_DEVICE_U2_ENABLE:
500 ret = dwc3_ep0_handle_u2(dwc, state, set);
501 break;
502 case USB_DEVICE_LTM_ENABLE:
503 ret = -EINVAL;
504 break;
505 case USB_DEVICE_TEST_MODE:
506 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
507 break;
508 default:
509 ret = -EINVAL;
510 }
511
512 return ret;
513}
514
515static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
516 struct usb_ctrlrequest *ctrl, int set)
517{
518 u32 wValue;
519 int ret = 0;
520
521 wValue = le16_to_cpu(ctrl->wValue);
522
523 switch (wValue) {
524 case USB_INTRF_FUNC_SUSPEND:
525 ret = dwc3_ep0_delegate_req(dwc, ctrl);
526 break;
527 default:
528 ret = -EINVAL;
529 }
530
531 return ret;
532}
533
534static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
535 struct usb_ctrlrequest *ctrl, int set)
536{
537 struct dwc3_ep *dep;
538 u32 wValue;
539 int ret;
540
541 wValue = le16_to_cpu(ctrl->wValue);
542
543 switch (wValue) {
544 case USB_ENDPOINT_HALT:
545 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
546 if (!dep)
547 return -EINVAL;
548
549 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
550 break;
551
552 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
553 if (ret)
554 return -EINVAL;
555
556 /* ClearFeature(Halt) may need delayed status */
557 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
558 return USB_GADGET_DELAYED_STATUS;
559
560 break;
561 default:
562 return -EINVAL;
563 }
564
565 return 0;
566}
567
568static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
569 struct usb_ctrlrequest *ctrl, int set)
570{
571 u32 recip;
572 int ret;
573
574 recip = ctrl->bRequestType & USB_RECIP_MASK;
575
576 switch (recip) {
577 case USB_RECIP_DEVICE:
578 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
579 break;
580 case USB_RECIP_INTERFACE:
581 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
582 break;
583 case USB_RECIP_ENDPOINT:
584 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
585 break;
586 default:
587 ret = -EINVAL;
588 }
589
590 return ret;
591}
592
593static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
594{
595 enum usb_device_state state = dwc->gadget->state;
596 u32 addr;
597 u32 reg;
598
599 addr = le16_to_cpu(ctrl->wValue);
600 if (addr > 127) {
601 dev_err(dwc->dev, "invalid device address %d\n", addr);
602 return -EINVAL;
603 }
604
605 if (state == USB_STATE_CONFIGURED) {
606 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
607 return -EINVAL;
608 }
609
610 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
611 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
612 reg |= DWC3_DCFG_DEVADDR(addr);
613 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
614
615 if (addr)
616 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
617 else
618 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
619
620 return 0;
621}
622
623static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
624{
625 int ret = -EINVAL;
626
627 if (dwc->async_callbacks) {
628 spin_unlock(&dwc->lock);
629 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
630 spin_lock(&dwc->lock);
631 }
632 return ret;
633}
634
635static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
636{
637 enum usb_device_state state = dwc->gadget->state;
638 u32 cfg;
639 int ret;
640 u32 reg;
641
642 cfg = le16_to_cpu(ctrl->wValue);
643
644 switch (state) {
645 case USB_STATE_DEFAULT:
646 return -EINVAL;
647
648 case USB_STATE_ADDRESS:
649 dwc3_gadget_clear_tx_fifos(dwc);
650
651 ret = dwc3_ep0_delegate_req(dwc, ctrl);
652 /* if the cfg matches and the cfg is non zero */
653 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
654
655 /*
656 * only change state if set_config has already
657 * been processed. If gadget driver returns
658 * USB_GADGET_DELAYED_STATUS, we will wait
659 * to change the state on the next usb_ep_queue()
660 */
661 if (ret == 0)
662 usb_gadget_set_state(dwc->gadget,
663 USB_STATE_CONFIGURED);
664
665 /*
666 * Enable transition to U1/U2 state when
667 * nothing is pending from application.
668 */
669 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
670 if (!dwc->dis_u1_entry_quirk)
671 reg |= DWC3_DCTL_ACCEPTU1ENA;
672 if (!dwc->dis_u2_entry_quirk)
673 reg |= DWC3_DCTL_ACCEPTU2ENA;
674 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
675 }
676 break;
677
678 case USB_STATE_CONFIGURED:
679 ret = dwc3_ep0_delegate_req(dwc, ctrl);
680 if (!cfg && !ret)
681 usb_gadget_set_state(dwc->gadget,
682 USB_STATE_ADDRESS);
683 break;
684 default:
685 ret = -EINVAL;
686 }
687 return ret;
688}
689
690static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
691{
692 struct dwc3_ep *dep = to_dwc3_ep(ep);
693 struct dwc3 *dwc = dep->dwc;
694
695 u32 param = 0;
696 u32 reg;
697
698 struct timing {
699 u8 u1sel;
700 u8 u1pel;
701 __le16 u2sel;
702 __le16 u2pel;
703 } __packed timing;
704
705 int ret;
706
707 memcpy(&timing, req->buf, sizeof(timing));
708
709 dwc->u1sel = timing.u1sel;
710 dwc->u1pel = timing.u1pel;
711 dwc->u2sel = le16_to_cpu(timing.u2sel);
712 dwc->u2pel = le16_to_cpu(timing.u2pel);
713
714 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
715 if (reg & DWC3_DCTL_INITU2ENA)
716 param = dwc->u2pel;
717 if (reg & DWC3_DCTL_INITU1ENA)
718 param = dwc->u1pel;
719
720 /*
721 * According to Synopsys Databook, if parameter is
722 * greater than 125, a value of zero should be
723 * programmed in the register.
724 */
725 if (param > 125)
726 param = 0;
727
728 /* now that we have the time, issue DGCMD Set Sel */
729 ret = dwc3_send_gadget_generic_command(dwc,
730 DWC3_DGCMD_SET_PERIODIC_PAR, param);
731 WARN_ON(ret < 0);
732}
733
734static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
735{
736 struct dwc3_ep *dep;
737 enum usb_device_state state = dwc->gadget->state;
738 u16 wLength;
739
740 if (state == USB_STATE_DEFAULT)
741 return -EINVAL;
742
743 wLength = le16_to_cpu(ctrl->wLength);
744
745 if (wLength != 6) {
746 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
747 wLength);
748 return -EINVAL;
749 }
750
751 /*
752 * To handle Set SEL we need to receive 6 bytes from Host. So let's
753 * queue a usb_request for 6 bytes.
754 *
755 * Remember, though, this controller can't handle non-wMaxPacketSize
756 * aligned transfers on the OUT direction, so we queue a request for
757 * wMaxPacketSize instead.
758 */
759 dep = dwc->eps[0];
760 dwc->ep0_usb_req.dep = dep;
761 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
762 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
763 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
764
765 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
766}
767
768static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
769{
770 u16 wLength;
771 u16 wValue;
772 u16 wIndex;
773
774 wValue = le16_to_cpu(ctrl->wValue);
775 wLength = le16_to_cpu(ctrl->wLength);
776 wIndex = le16_to_cpu(ctrl->wIndex);
777
778 if (wIndex || wLength)
779 return -EINVAL;
780
781 dwc->gadget->isoch_delay = wValue;
782
783 return 0;
784}
785
786static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
787{
788 int ret;
789
790 switch (ctrl->bRequest) {
791 case USB_REQ_GET_STATUS:
792 ret = dwc3_ep0_handle_status(dwc, ctrl);
793 break;
794 case USB_REQ_CLEAR_FEATURE:
795 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
796 break;
797 case USB_REQ_SET_FEATURE:
798 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
799 break;
800 case USB_REQ_SET_ADDRESS:
801 ret = dwc3_ep0_set_address(dwc, ctrl);
802 break;
803 case USB_REQ_SET_CONFIGURATION:
804 ret = dwc3_ep0_set_config(dwc, ctrl);
805 break;
806 case USB_REQ_SET_SEL:
807 ret = dwc3_ep0_set_sel(dwc, ctrl);
808 break;
809 case USB_REQ_SET_ISOCH_DELAY:
810 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
811 break;
812 default:
813 ret = dwc3_ep0_delegate_req(dwc, ctrl);
814 break;
815 }
816
817 return ret;
818}
819
820static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
821 const struct dwc3_event_depevt *event)
822{
823 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
824 int ret = -EINVAL;
825 u32 len;
826
827 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
828 goto out;
829
830 trace_dwc3_ctrl_req(ctrl);
831
832 len = le16_to_cpu(ctrl->wLength);
833 if (!len) {
834 dwc->three_stage_setup = false;
835 dwc->ep0_expect_in = false;
836 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
837 } else {
838 dwc->three_stage_setup = true;
839 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
840 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
841 }
842
843 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
844 ret = dwc3_ep0_std_request(dwc, ctrl);
845 else
846 ret = dwc3_ep0_delegate_req(dwc, ctrl);
847
848 if (ret == USB_GADGET_DELAYED_STATUS)
849 dwc->delayed_status = true;
850
851out:
852 if (ret < 0)
853 dwc3_ep0_stall_and_restart(dwc);
854}
855
856static void dwc3_ep0_complete_data(struct dwc3 *dwc,
857 const struct dwc3_event_depevt *event)
858{
859 struct dwc3_request *r;
860 struct usb_request *ur;
861 struct dwc3_trb *trb;
862 struct dwc3_ep *ep0;
863 u32 transferred = 0;
864 u32 status;
865 u32 length;
866 u8 epnum;
867
868 epnum = event->endpoint_number;
869 ep0 = dwc->eps[0];
870
871 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
872 trb = dwc->ep0_trb;
873 trace_dwc3_complete_trb(ep0, trb);
874
875 r = next_request(&ep0->pending_list);
876 if (!r)
877 return;
878
879 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
880 if (status == DWC3_TRBSTS_SETUP_PENDING) {
881 dwc->setup_packet_pending = true;
882 if (r)
883 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
884
885 return;
886 }
887
888 ur = &r->request;
889
890 length = trb->size & DWC3_TRB_SIZE_MASK;
891 transferred = ur->length - length;
892 ur->actual += transferred;
893
894 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
895 ur->length && ur->zero) || dwc->ep0_bounced) {
896 trb++;
897 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
898 trace_dwc3_complete_trb(ep0, trb);
899
900 if (r->direction)
901 dwc->eps[1]->trb_enqueue = 0;
902 else
903 dwc->eps[0]->trb_enqueue = 0;
904
905 dwc->ep0_bounced = false;
906 }
907
908 if ((epnum & 1) && ur->actual < ur->length)
909 dwc3_ep0_stall_and_restart(dwc);
910 else
911 dwc3_gadget_giveback(ep0, r, 0);
912}
913
914static void dwc3_ep0_complete_status(struct dwc3 *dwc,
915 const struct dwc3_event_depevt *event)
916{
917 struct dwc3_request *r;
918 struct dwc3_ep *dep;
919 struct dwc3_trb *trb;
920 u32 status;
921
922 dep = dwc->eps[0];
923 trb = dwc->ep0_trb;
924
925 trace_dwc3_complete_trb(dep, trb);
926
927 if (!list_empty(&dep->pending_list)) {
928 r = next_request(&dep->pending_list);
929
930 dwc3_gadget_giveback(dep, r, 0);
931 }
932
933 if (dwc->test_mode) {
934 int ret;
935
936 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
937 if (ret < 0) {
938 dev_err(dwc->dev, "invalid test #%d\n",
939 dwc->test_mode_nr);
940 dwc3_ep0_stall_and_restart(dwc);
941 return;
942 }
943 }
944
945 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
946 if (status == DWC3_TRBSTS_SETUP_PENDING)
947 dwc->setup_packet_pending = true;
948
949 dwc->ep0state = EP0_SETUP_PHASE;
950 dwc3_ep0_out_start(dwc);
951}
952
953static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
954 const struct dwc3_event_depevt *event)
955{
956 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
957
958 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
959 dep->resource_index = 0;
960 dwc->setup_packet_pending = false;
961
962 switch (dwc->ep0state) {
963 case EP0_SETUP_PHASE:
964 dwc3_ep0_inspect_setup(dwc, event);
965 break;
966
967 case EP0_DATA_PHASE:
968 dwc3_ep0_complete_data(dwc, event);
969 break;
970
971 case EP0_STATUS_PHASE:
972 dwc3_ep0_complete_status(dwc, event);
973 break;
974 default:
975 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
976 }
977}
978
979static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
980 struct dwc3_ep *dep, struct dwc3_request *req)
981{
982 unsigned int trb_length = 0;
983 int ret;
984
985 req->direction = !!dep->number;
986
987 if (req->request.length == 0) {
988 if (!req->direction)
989 trb_length = dep->endpoint.maxpacket;
990
991 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
992 DWC3_TRBCTL_CONTROL_DATA, false);
993 ret = dwc3_ep0_start_trans(dep);
994 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
995 && (dep->number == 0)) {
996 u32 maxpacket;
997 u32 rem;
998
999 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1000 &req->request, dep->number);
1001 if (ret)
1002 return;
1003
1004 maxpacket = dep->endpoint.maxpacket;
1005 rem = req->request.length % maxpacket;
1006 dwc->ep0_bounced = true;
1007
1008 /* prepare normal TRB */
1009 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1010 req->request.length,
1011 DWC3_TRBCTL_CONTROL_DATA,
1012 true);
1013
1014 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1015
1016 /* Now prepare one extra TRB to align transfer size */
1017 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1018 maxpacket - rem,
1019 DWC3_TRBCTL_CONTROL_DATA,
1020 false);
1021 ret = dwc3_ep0_start_trans(dep);
1022 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1023 req->request.length && req->request.zero) {
1024
1025 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1026 &req->request, dep->number);
1027 if (ret)
1028 return;
1029
1030 /* prepare normal TRB */
1031 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1032 req->request.length,
1033 DWC3_TRBCTL_CONTROL_DATA,
1034 true);
1035
1036 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1037
1038 if (!req->direction)
1039 trb_length = dep->endpoint.maxpacket;
1040
1041 /* Now prepare one extra TRB to align transfer size */
1042 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1043 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1044 false);
1045 ret = dwc3_ep0_start_trans(dep);
1046 } else {
1047 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1048 &req->request, dep->number);
1049 if (ret)
1050 return;
1051
1052 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1053 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1054 false);
1055
1056 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1057
1058 ret = dwc3_ep0_start_trans(dep);
1059 }
1060
1061 WARN_ON(ret < 0);
1062}
1063
1064static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1065{
1066 struct dwc3 *dwc = dep->dwc;
1067 u32 type;
1068
1069 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1070 : DWC3_TRBCTL_CONTROL_STATUS2;
1071
1072 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1073 return dwc3_ep0_start_trans(dep);
1074}
1075
1076static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1077{
1078 WARN_ON(dwc3_ep0_start_control_status(dep));
1079}
1080
1081static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1082 const struct dwc3_event_depevt *event)
1083{
1084 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1085
1086 __dwc3_ep0_do_control_status(dwc, dep);
1087}
1088
1089void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1090{
1091 unsigned int direction = !dwc->ep0_expect_in;
1092
1093 dwc->delayed_status = false;
1094 dwc->clear_stall_protocol = 0;
1095
1096 if (dwc->ep0state != EP0_STATUS_PHASE)
1097 return;
1098
1099 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1100}
1101
1102void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1103{
1104 struct dwc3_gadget_ep_cmd_params params;
1105 u32 cmd;
1106 int ret;
1107
1108 /*
1109 * For status/DATA OUT stage, TRB will be queued on ep0 out
1110 * endpoint for which resource index is zero. Hence allow
1111 * queuing ENDXFER command for ep0 out endpoint.
1112 */
1113 if (!dep->resource_index && dep->number)
1114 return;
1115
1116 cmd = DWC3_DEPCMD_ENDTRANSFER;
1117 cmd |= DWC3_DEPCMD_CMDIOC;
1118 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1119 memset(¶ms, 0, sizeof(params));
1120 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1121 WARN_ON_ONCE(ret);
1122 dep->resource_index = 0;
1123}
1124
1125static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1126 const struct dwc3_event_depevt *event)
1127{
1128 switch (event->status) {
1129 case DEPEVT_STATUS_CONTROL_DATA:
1130 if (!dwc->softconnect || !dwc->connected)
1131 return;
1132 /*
1133 * We already have a DATA transfer in the controller's cache,
1134 * if we receive a XferNotReady(DATA) we will ignore it, unless
1135 * it's for the wrong direction.
1136 *
1137 * In that case, we must issue END_TRANSFER command to the Data
1138 * Phase we already have started and issue SetStall on the
1139 * control endpoint.
1140 */
1141 if (dwc->ep0_expect_in != event->endpoint_number) {
1142 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1143
1144 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1145 dwc3_ep0_end_control_data(dwc, dep);
1146 dwc3_ep0_stall_and_restart(dwc);
1147 return;
1148 }
1149
1150 break;
1151
1152 case DEPEVT_STATUS_CONTROL_STATUS:
1153 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1154 return;
1155
1156 if (dwc->setup_packet_pending) {
1157 dwc3_ep0_stall_and_restart(dwc);
1158 return;
1159 }
1160
1161 dwc->ep0state = EP0_STATUS_PHASE;
1162
1163 if (dwc->delayed_status) {
1164 struct dwc3_ep *dep = dwc->eps[0];
1165
1166 WARN_ON_ONCE(event->endpoint_number != 1);
1167 /*
1168 * We should handle the delay STATUS phase here if the
1169 * request for handling delay STATUS has been queued
1170 * into the list.
1171 */
1172 if (!list_empty(&dep->pending_list)) {
1173 dwc->delayed_status = false;
1174 usb_gadget_set_state(dwc->gadget,
1175 USB_STATE_CONFIGURED);
1176 dwc3_ep0_do_control_status(dwc, event);
1177 }
1178
1179 return;
1180 }
1181
1182 dwc3_ep0_do_control_status(dwc, event);
1183 }
1184}
1185
1186void dwc3_ep0_interrupt(struct dwc3 *dwc,
1187 const struct dwc3_event_depevt *event)
1188{
1189 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1190 u8 cmd;
1191
1192 switch (event->endpoint_event) {
1193 case DWC3_DEPEVT_XFERCOMPLETE:
1194 dwc3_ep0_xfer_complete(dwc, event);
1195 break;
1196
1197 case DWC3_DEPEVT_XFERNOTREADY:
1198 dwc3_ep0_xfernotready(dwc, event);
1199 break;
1200
1201 case DWC3_DEPEVT_XFERINPROGRESS:
1202 case DWC3_DEPEVT_RXTXFIFOEVT:
1203 case DWC3_DEPEVT_STREAMEVT:
1204 break;
1205 case DWC3_DEPEVT_EPCMDCMPLT:
1206 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1207
1208 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1209 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1210 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1211 }
1212 break;
1213 default:
1214 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
1215 break;
1216 }
1217}
1/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/interrupt.h>
45#include <linux/io.h>
46#include <linux/list.h>
47#include <linux/dma-mapping.h>
48
49#include <linux/usb/ch9.h>
50#include <linux/usb/gadget.h>
51#include <linux/usb/composite.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
58
59static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
60{
61 switch (state) {
62 case EP0_UNCONNECTED:
63 return "Unconnected";
64 case EP0_SETUP_PHASE:
65 return "Setup Phase";
66 case EP0_DATA_PHASE:
67 return "Data Phase";
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
70 default:
71 return "UNKNOWN";
72 }
73}
74
75static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
76 u32 len, u32 type)
77{
78 struct dwc3_gadget_ep_cmd_params params;
79 struct dwc3_trb *trb;
80 struct dwc3_ep *dep;
81
82 int ret;
83
84 dep = dwc->eps[epnum];
85 if (dep->flags & DWC3_EP_BUSY) {
86 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
87 return 0;
88 }
89
90 trb = dwc->ep0_trb;
91
92 trb->bpl = lower_32_bits(buf_dma);
93 trb->bph = upper_32_bits(buf_dma);
94 trb->size = len;
95 trb->ctrl = type;
96
97 trb->ctrl |= (DWC3_TRB_CTRL_HWO
98 | DWC3_TRB_CTRL_LST
99 | DWC3_TRB_CTRL_IOC
100 | DWC3_TRB_CTRL_ISP_IMI);
101
102 memset(¶ms, 0, sizeof(params));
103 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
104 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
105
106 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
107 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
108 if (ret < 0) {
109 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
110 return ret;
111 }
112
113 dep->flags |= DWC3_EP_BUSY;
114 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
115 dep->number);
116
117 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
118
119 return 0;
120}
121
122static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
123 struct dwc3_request *req)
124{
125 struct dwc3 *dwc = dep->dwc;
126 int ret = 0;
127
128 req->request.actual = 0;
129 req->request.status = -EINPROGRESS;
130 req->epnum = dep->number;
131
132 list_add_tail(&req->list, &dep->request_list);
133
134 /*
135 * Gadget driver might not be quick enough to queue a request
136 * before we get a Transfer Not Ready event on this endpoint.
137 *
138 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
139 * flag is set, it's telling us that as soon as Gadget queues the
140 * required request, we should kick the transfer here because the
141 * IRQ we were waiting for is long gone.
142 */
143 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
144 unsigned direction;
145
146 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
147
148 if (dwc->ep0state != EP0_DATA_PHASE) {
149 dev_WARN(dwc->dev, "Unexpected pending request\n");
150 return 0;
151 }
152
153 ret = dwc3_ep0_start_trans(dwc, direction,
154 req->request.dma, req->request.length,
155 DWC3_TRBCTL_CONTROL_DATA);
156 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
157 DWC3_EP0_DIR_IN);
158 } else if (dwc->delayed_status) {
159 dwc->delayed_status = false;
160
161 if (dwc->ep0state == EP0_STATUS_PHASE)
162 dwc3_ep0_do_control_status(dwc, 1);
163 else
164 dev_dbg(dwc->dev, "too early for delayed status\n");
165 }
166
167 return ret;
168}
169
170int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
171 gfp_t gfp_flags)
172{
173 struct dwc3_request *req = to_dwc3_request(request);
174 struct dwc3_ep *dep = to_dwc3_ep(ep);
175 struct dwc3 *dwc = dep->dwc;
176
177 unsigned long flags;
178
179 int ret;
180
181 spin_lock_irqsave(&dwc->lock, flags);
182 if (!dep->endpoint.desc) {
183 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
184 request, dep->name);
185 ret = -ESHUTDOWN;
186 goto out;
187 }
188
189 /* we share one TRB for ep0/1 */
190 if (!list_empty(&dep->request_list)) {
191 ret = -EBUSY;
192 goto out;
193 }
194
195 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
196 request, dep->name, request->length,
197 dwc3_ep0_state_string(dwc->ep0state));
198
199 ret = __dwc3_gadget_ep0_queue(dep, req);
200
201out:
202 spin_unlock_irqrestore(&dwc->lock, flags);
203
204 return ret;
205}
206
207static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
208{
209 struct dwc3_ep *dep = dwc->eps[0];
210
211 /* stall is always issued on EP0 */
212 __dwc3_gadget_ep_set_halt(dep, 1);
213 dep->flags = DWC3_EP_ENABLED;
214 dwc->delayed_status = false;
215
216 if (!list_empty(&dep->request_list)) {
217 struct dwc3_request *req;
218
219 req = next_request(&dep->request_list);
220 dwc3_gadget_giveback(dep, req, -ECONNRESET);
221 }
222
223 dwc->ep0state = EP0_SETUP_PHASE;
224 dwc3_ep0_out_start(dwc);
225}
226
227void dwc3_ep0_out_start(struct dwc3 *dwc)
228{
229 int ret;
230
231 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
232 DWC3_TRBCTL_CONTROL_SETUP);
233 WARN_ON(ret < 0);
234}
235
236static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
237{
238 struct dwc3_ep *dep;
239 u32 windex = le16_to_cpu(wIndex_le);
240 u32 epnum;
241
242 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
243 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
244 epnum |= 1;
245
246 dep = dwc->eps[epnum];
247 if (dep->flags & DWC3_EP_ENABLED)
248 return dep;
249
250 return NULL;
251}
252
253static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
254{
255}
256/*
257 * ch 9.4.5
258 */
259static int dwc3_ep0_handle_status(struct dwc3 *dwc,
260 struct usb_ctrlrequest *ctrl)
261{
262 struct dwc3_ep *dep;
263 u32 recip;
264 u32 reg;
265 u16 usb_status = 0;
266 __le16 *response_pkt;
267
268 recip = ctrl->bRequestType & USB_RECIP_MASK;
269 switch (recip) {
270 case USB_RECIP_DEVICE:
271 /*
272 * LTM will be set once we know how to set this in HW.
273 */
274 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
275
276 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
277 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
278 if (reg & DWC3_DCTL_INITU1ENA)
279 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
280 if (reg & DWC3_DCTL_INITU2ENA)
281 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
282 }
283
284 break;
285
286 case USB_RECIP_INTERFACE:
287 /*
288 * Function Remote Wake Capable D0
289 * Function Remote Wakeup D1
290 */
291 break;
292
293 case USB_RECIP_ENDPOINT:
294 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
295 if (!dep)
296 return -EINVAL;
297
298 if (dep->flags & DWC3_EP_STALL)
299 usb_status = 1 << USB_ENDPOINT_HALT;
300 break;
301 default:
302 return -EINVAL;
303 };
304
305 response_pkt = (__le16 *) dwc->setup_buf;
306 *response_pkt = cpu_to_le16(usb_status);
307
308 dep = dwc->eps[0];
309 dwc->ep0_usb_req.dep = dep;
310 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
311 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
312 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
313
314 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
315}
316
317static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
318 struct usb_ctrlrequest *ctrl, int set)
319{
320 struct dwc3_ep *dep;
321 u32 recip;
322 u32 wValue;
323 u32 wIndex;
324 u32 reg;
325 int ret;
326
327 wValue = le16_to_cpu(ctrl->wValue);
328 wIndex = le16_to_cpu(ctrl->wIndex);
329 recip = ctrl->bRequestType & USB_RECIP_MASK;
330 switch (recip) {
331 case USB_RECIP_DEVICE:
332
333 switch (wValue) {
334 case USB_DEVICE_REMOTE_WAKEUP:
335 break;
336 /*
337 * 9.4.1 says only only for SS, in AddressState only for
338 * default control pipe
339 */
340 case USB_DEVICE_U1_ENABLE:
341 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
342 return -EINVAL;
343 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
344 return -EINVAL;
345
346 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
347 if (set)
348 reg |= DWC3_DCTL_INITU1ENA;
349 else
350 reg &= ~DWC3_DCTL_INITU1ENA;
351 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
352 break;
353
354 case USB_DEVICE_U2_ENABLE:
355 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
356 return -EINVAL;
357 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
358 return -EINVAL;
359
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 if (set)
362 reg |= DWC3_DCTL_INITU2ENA;
363 else
364 reg &= ~DWC3_DCTL_INITU2ENA;
365 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
366 break;
367
368 case USB_DEVICE_LTM_ENABLE:
369 return -EINVAL;
370 break;
371
372 case USB_DEVICE_TEST_MODE:
373 if ((wIndex & 0xff) != 0)
374 return -EINVAL;
375 if (!set)
376 return -EINVAL;
377
378 dwc->test_mode_nr = wIndex >> 8;
379 dwc->test_mode = true;
380 break;
381 default:
382 return -EINVAL;
383 }
384 break;
385
386 case USB_RECIP_INTERFACE:
387 switch (wValue) {
388 case USB_INTRF_FUNC_SUSPEND:
389 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
390 /* XXX enable Low power suspend */
391 ;
392 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
393 /* XXX enable remote wakeup */
394 ;
395 break;
396 default:
397 return -EINVAL;
398 }
399 break;
400
401 case USB_RECIP_ENDPOINT:
402 switch (wValue) {
403 case USB_ENDPOINT_HALT:
404 dep = dwc3_wIndex_to_dep(dwc, wIndex);
405 if (!dep)
406 return -EINVAL;
407 ret = __dwc3_gadget_ep_set_halt(dep, set);
408 if (ret)
409 return -EINVAL;
410 break;
411 default:
412 return -EINVAL;
413 }
414 break;
415
416 default:
417 return -EINVAL;
418 };
419
420 return 0;
421}
422
423static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
424{
425 u32 addr;
426 u32 reg;
427
428 addr = le16_to_cpu(ctrl->wValue);
429 if (addr > 127) {
430 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
431 return -EINVAL;
432 }
433
434 if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
435 dev_dbg(dwc->dev, "trying to set address when configured\n");
436 return -EINVAL;
437 }
438
439 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
440 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
441 reg |= DWC3_DCFG_DEVADDR(addr);
442 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
443
444 if (addr)
445 dwc->dev_state = DWC3_ADDRESS_STATE;
446 else
447 dwc->dev_state = DWC3_DEFAULT_STATE;
448
449 return 0;
450}
451
452static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
453{
454 int ret;
455
456 spin_unlock(&dwc->lock);
457 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
458 spin_lock(&dwc->lock);
459 return ret;
460}
461
462static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
463{
464 u32 cfg;
465 int ret;
466
467 dwc->start_config_issued = false;
468 cfg = le16_to_cpu(ctrl->wValue);
469
470 switch (dwc->dev_state) {
471 case DWC3_DEFAULT_STATE:
472 return -EINVAL;
473 break;
474
475 case DWC3_ADDRESS_STATE:
476 ret = dwc3_ep0_delegate_req(dwc, ctrl);
477 /* if the cfg matches and the cfg is non zero */
478 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
479 dwc->dev_state = DWC3_CONFIGURED_STATE;
480 dwc->resize_fifos = true;
481 dev_dbg(dwc->dev, "resize fifos flag SET\n");
482 }
483 break;
484
485 case DWC3_CONFIGURED_STATE:
486 ret = dwc3_ep0_delegate_req(dwc, ctrl);
487 if (!cfg)
488 dwc->dev_state = DWC3_ADDRESS_STATE;
489 break;
490 default:
491 ret = -EINVAL;
492 }
493 return ret;
494}
495
496static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
497{
498 struct dwc3_ep *dep = to_dwc3_ep(ep);
499 struct dwc3 *dwc = dep->dwc;
500
501 u32 param = 0;
502 u32 reg;
503
504 struct timing {
505 u8 u1sel;
506 u8 u1pel;
507 u16 u2sel;
508 u16 u2pel;
509 } __packed timing;
510
511 int ret;
512
513 memcpy(&timing, req->buf, sizeof(timing));
514
515 dwc->u1sel = timing.u1sel;
516 dwc->u1pel = timing.u1pel;
517 dwc->u2sel = timing.u2sel;
518 dwc->u2pel = timing.u2pel;
519
520 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
521 if (reg & DWC3_DCTL_INITU2ENA)
522 param = dwc->u2pel;
523 if (reg & DWC3_DCTL_INITU1ENA)
524 param = dwc->u1pel;
525
526 /*
527 * According to Synopsys Databook, if parameter is
528 * greater than 125, a value of zero should be
529 * programmed in the register.
530 */
531 if (param > 125)
532 param = 0;
533
534 /* now that we have the time, issue DGCMD Set Sel */
535 ret = dwc3_send_gadget_generic_command(dwc,
536 DWC3_DGCMD_SET_PERIODIC_PAR, param);
537 WARN_ON(ret < 0);
538}
539
540static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
541{
542 struct dwc3_ep *dep;
543 u16 wLength;
544 u16 wValue;
545
546 if (dwc->dev_state == DWC3_DEFAULT_STATE)
547 return -EINVAL;
548
549 wValue = le16_to_cpu(ctrl->wValue);
550 wLength = le16_to_cpu(ctrl->wLength);
551
552 if (wLength != 6) {
553 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
554 wLength);
555 return -EINVAL;
556 }
557
558 /*
559 * To handle Set SEL we need to receive 6 bytes from Host. So let's
560 * queue a usb_request for 6 bytes.
561 *
562 * Remember, though, this controller can't handle non-wMaxPacketSize
563 * aligned transfers on the OUT direction, so we queue a request for
564 * wMaxPacketSize instead.
565 */
566 dep = dwc->eps[0];
567 dwc->ep0_usb_req.dep = dep;
568 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
569 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
570 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
571
572 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
573}
574
575static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
576{
577 u16 wLength;
578 u16 wValue;
579 u16 wIndex;
580
581 wValue = le16_to_cpu(ctrl->wValue);
582 wLength = le16_to_cpu(ctrl->wLength);
583 wIndex = le16_to_cpu(ctrl->wIndex);
584
585 if (wIndex || wLength)
586 return -EINVAL;
587
588 /*
589 * REVISIT It's unclear from Databook what to do with this
590 * value. For now, just cache it.
591 */
592 dwc->isoch_delay = wValue;
593
594 return 0;
595}
596
597static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
598{
599 int ret;
600
601 switch (ctrl->bRequest) {
602 case USB_REQ_GET_STATUS:
603 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
604 ret = dwc3_ep0_handle_status(dwc, ctrl);
605 break;
606 case USB_REQ_CLEAR_FEATURE:
607 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
608 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
609 break;
610 case USB_REQ_SET_FEATURE:
611 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
612 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
613 break;
614 case USB_REQ_SET_ADDRESS:
615 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
616 ret = dwc3_ep0_set_address(dwc, ctrl);
617 break;
618 case USB_REQ_SET_CONFIGURATION:
619 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
620 ret = dwc3_ep0_set_config(dwc, ctrl);
621 break;
622 case USB_REQ_SET_SEL:
623 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
624 ret = dwc3_ep0_set_sel(dwc, ctrl);
625 break;
626 case USB_REQ_SET_ISOCH_DELAY:
627 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
628 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
629 break;
630 default:
631 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
632 ret = dwc3_ep0_delegate_req(dwc, ctrl);
633 break;
634 };
635
636 return ret;
637}
638
639static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
640 const struct dwc3_event_depevt *event)
641{
642 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
643 int ret;
644 u32 len;
645
646 if (!dwc->gadget_driver)
647 goto err;
648
649 len = le16_to_cpu(ctrl->wLength);
650 if (!len) {
651 dwc->three_stage_setup = false;
652 dwc->ep0_expect_in = false;
653 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
654 } else {
655 dwc->three_stage_setup = true;
656 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
657 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
658 }
659
660 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
661 ret = dwc3_ep0_std_request(dwc, ctrl);
662 else
663 ret = dwc3_ep0_delegate_req(dwc, ctrl);
664
665 if (ret == USB_GADGET_DELAYED_STATUS)
666 dwc->delayed_status = true;
667
668 if (ret >= 0)
669 return;
670
671err:
672 dwc3_ep0_stall_and_restart(dwc);
673}
674
675static void dwc3_ep0_complete_data(struct dwc3 *dwc,
676 const struct dwc3_event_depevt *event)
677{
678 struct dwc3_request *r = NULL;
679 struct usb_request *ur;
680 struct dwc3_trb *trb;
681 struct dwc3_ep *ep0;
682 u32 transferred;
683 u32 length;
684 u8 epnum;
685
686 epnum = event->endpoint_number;
687 ep0 = dwc->eps[0];
688
689 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
690
691 r = next_request(&ep0->request_list);
692 ur = &r->request;
693
694 trb = dwc->ep0_trb;
695 length = trb->size & DWC3_TRB_SIZE_MASK;
696
697 if (dwc->ep0_bounced) {
698 unsigned transfer_size = ur->length;
699 unsigned maxp = ep0->endpoint.maxpacket;
700
701 transfer_size += (maxp - (transfer_size % maxp));
702 transferred = min_t(u32, ur->length,
703 transfer_size - length);
704 memcpy(ur->buf, dwc->ep0_bounce, transferred);
705 } else {
706 transferred = ur->length - length;
707 }
708
709 ur->actual += transferred;
710
711 if ((epnum & 1) && ur->actual < ur->length) {
712 /* for some reason we did not get everything out */
713
714 dwc3_ep0_stall_and_restart(dwc);
715 } else {
716 /*
717 * handle the case where we have to send a zero packet. This
718 * seems to be case when req.length > maxpacket. Could it be?
719 */
720 if (r)
721 dwc3_gadget_giveback(ep0, r, 0);
722 }
723}
724
725static void dwc3_ep0_complete_req(struct dwc3 *dwc,
726 const struct dwc3_event_depevt *event)
727{
728 struct dwc3_request *r;
729 struct dwc3_ep *dep;
730
731 dep = dwc->eps[0];
732
733 if (!list_empty(&dep->request_list)) {
734 r = next_request(&dep->request_list);
735
736 dwc3_gadget_giveback(dep, r, 0);
737 }
738
739 if (dwc->test_mode) {
740 int ret;
741
742 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
743 if (ret < 0) {
744 dev_dbg(dwc->dev, "Invalid Test #%d\n",
745 dwc->test_mode_nr);
746 dwc3_ep0_stall_and_restart(dwc);
747 }
748 }
749
750 dwc->ep0state = EP0_SETUP_PHASE;
751 dwc3_ep0_out_start(dwc);
752}
753
754static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
755 const struct dwc3_event_depevt *event)
756{
757 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
758
759 dep->flags &= ~DWC3_EP_BUSY;
760 dep->res_trans_idx = 0;
761 dwc->setup_packet_pending = false;
762
763 switch (dwc->ep0state) {
764 case EP0_SETUP_PHASE:
765 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
766 dwc3_ep0_inspect_setup(dwc, event);
767 break;
768
769 case EP0_DATA_PHASE:
770 dev_vdbg(dwc->dev, "Data Phase\n");
771 dwc3_ep0_complete_data(dwc, event);
772 break;
773
774 case EP0_STATUS_PHASE:
775 dev_vdbg(dwc->dev, "Status Phase\n");
776 dwc3_ep0_complete_req(dwc, event);
777 break;
778 default:
779 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
780 }
781}
782
783static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
784 const struct dwc3_event_depevt *event)
785{
786 dwc3_ep0_out_start(dwc);
787}
788
789static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
790 const struct dwc3_event_depevt *event)
791{
792 struct dwc3_ep *dep;
793 struct dwc3_request *req;
794 int ret;
795
796 dep = dwc->eps[0];
797
798 if (list_empty(&dep->request_list)) {
799 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
800 dep->flags |= DWC3_EP_PENDING_REQUEST;
801
802 if (event->endpoint_number)
803 dep->flags |= DWC3_EP0_DIR_IN;
804 return;
805 }
806
807 req = next_request(&dep->request_list);
808 req->direction = !!event->endpoint_number;
809
810 if (req->request.length == 0) {
811 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
812 dwc->ctrl_req_addr, 0,
813 DWC3_TRBCTL_CONTROL_DATA);
814 } else if ((req->request.length % dep->endpoint.maxpacket)
815 && (event->endpoint_number == 0)) {
816 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
817 event->endpoint_number);
818 if (ret) {
819 dev_dbg(dwc->dev, "failed to map request\n");
820 return;
821 }
822
823 WARN_ON(req->request.length > dep->endpoint.maxpacket);
824
825 dwc->ep0_bounced = true;
826
827 /*
828 * REVISIT in case request length is bigger than EP0
829 * wMaxPacketSize, we will need two chained TRBs to handle
830 * the transfer.
831 */
832 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
833 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
834 DWC3_TRBCTL_CONTROL_DATA);
835 } else {
836 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
837 event->endpoint_number);
838 if (ret) {
839 dev_dbg(dwc->dev, "failed to map request\n");
840 return;
841 }
842
843 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
844 req->request.dma, req->request.length,
845 DWC3_TRBCTL_CONTROL_DATA);
846 }
847
848 WARN_ON(ret < 0);
849}
850
851static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
852{
853 struct dwc3 *dwc = dep->dwc;
854 u32 type;
855
856 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
857 : DWC3_TRBCTL_CONTROL_STATUS2;
858
859 return dwc3_ep0_start_trans(dwc, dep->number,
860 dwc->ctrl_req_addr, 0, type);
861}
862
863static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
864{
865 struct dwc3_ep *dep = dwc->eps[epnum];
866
867 if (dwc->resize_fifos) {
868 dev_dbg(dwc->dev, "starting to resize fifos\n");
869 dwc3_gadget_resize_tx_fifos(dwc);
870 dwc->resize_fifos = 0;
871 }
872
873 WARN_ON(dwc3_ep0_start_control_status(dep));
874}
875
876static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
877 const struct dwc3_event_depevt *event)
878{
879 dwc->setup_packet_pending = true;
880
881 /*
882 * This part is very tricky: If we has just handled
883 * XferNotReady(Setup) and we're now expecting a
884 * XferComplete but, instead, we receive another
885 * XferNotReady(Setup), we should STALL and restart
886 * the state machine.
887 *
888 * In all other cases, we just continue waiting
889 * for the XferComplete event.
890 *
891 * We are a little bit unsafe here because we're
892 * not trying to ensure that last event was, indeed,
893 * XferNotReady(Setup).
894 *
895 * Still, we don't expect any condition where that
896 * should happen and, even if it does, it would be
897 * another error condition.
898 */
899 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
900 switch (event->status) {
901 case DEPEVT_STATUS_CONTROL_SETUP:
902 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
903 dwc3_ep0_stall_and_restart(dwc);
904 break;
905 case DEPEVT_STATUS_CONTROL_DATA:
906 /* FALLTHROUGH */
907 case DEPEVT_STATUS_CONTROL_STATUS:
908 /* FALLTHROUGH */
909 default:
910 dev_vdbg(dwc->dev, "waiting for XferComplete\n");
911 }
912
913 return;
914 }
915
916 switch (event->status) {
917 case DEPEVT_STATUS_CONTROL_SETUP:
918 dev_vdbg(dwc->dev, "Control Setup\n");
919
920 dwc->ep0state = EP0_SETUP_PHASE;
921
922 dwc3_ep0_do_control_setup(dwc, event);
923 break;
924
925 case DEPEVT_STATUS_CONTROL_DATA:
926 dev_vdbg(dwc->dev, "Control Data\n");
927
928 dwc->ep0state = EP0_DATA_PHASE;
929
930 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
931 dev_vdbg(dwc->dev, "Expected %d got %d\n",
932 dwc->ep0_next_event,
933 DWC3_EP0_NRDY_DATA);
934
935 dwc3_ep0_stall_and_restart(dwc);
936 return;
937 }
938
939 /*
940 * One of the possible error cases is when Host _does_
941 * request for Data Phase, but it does so on the wrong
942 * direction.
943 *
944 * Here, we already know ep0_next_event is DATA (see above),
945 * so we only need to check for direction.
946 */
947 if (dwc->ep0_expect_in != event->endpoint_number) {
948 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
949 dwc3_ep0_stall_and_restart(dwc);
950 return;
951 }
952
953 dwc3_ep0_do_control_data(dwc, event);
954 break;
955
956 case DEPEVT_STATUS_CONTROL_STATUS:
957 dev_vdbg(dwc->dev, "Control Status\n");
958
959 dwc->ep0state = EP0_STATUS_PHASE;
960
961 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
962 dev_vdbg(dwc->dev, "Expected %d got %d\n",
963 dwc->ep0_next_event,
964 DWC3_EP0_NRDY_STATUS);
965
966 dwc3_ep0_stall_and_restart(dwc);
967 return;
968 }
969
970 if (dwc->delayed_status) {
971 WARN_ON_ONCE(event->endpoint_number != 1);
972 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
973 return;
974 }
975
976 dwc3_ep0_do_control_status(dwc, event->endpoint_number);
977 }
978}
979
980void dwc3_ep0_interrupt(struct dwc3 *dwc,
981 const struct dwc3_event_depevt *event)
982{
983 u8 epnum = event->endpoint_number;
984
985 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
986 dwc3_ep_event_string(event->endpoint_event),
987 epnum >> 1, (epnum & 1) ? "in" : "out",
988 dwc3_ep0_state_string(dwc->ep0state));
989
990 switch (event->endpoint_event) {
991 case DWC3_DEPEVT_XFERCOMPLETE:
992 dwc3_ep0_xfer_complete(dwc, event);
993 break;
994
995 case DWC3_DEPEVT_XFERNOTREADY:
996 dwc3_ep0_xfernotready(dwc, event);
997 break;
998
999 case DWC3_DEPEVT_XFERINPROGRESS:
1000 case DWC3_DEPEVT_RXTXFIFOEVT:
1001 case DWC3_DEPEVT_STREAMEVT:
1002 case DWC3_DEPEVT_EPCMDCMPLT:
1003 break;
1004 }
1005}