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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/log2.h>
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/slab.h>
18#include <linux/dmi.h>
19#include <linux/dma-mapping.h>
20
21#include "xhci.h"
22#include "xhci-trace.h"
23#include "xhci-debugfs.h"
24#include "xhci-dbgcap.h"
25
26#define DRIVER_AUTHOR "Sarah Sharp"
27#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
28
29#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
30
31/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32static int link_quirk;
33module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
35
36static unsigned long long quirks;
37module_param(quirks, ullong, S_IRUGO);
38MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
39
40static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
41{
42 struct xhci_segment *seg = ring->first_seg;
43
44 if (!td || !td->start_seg)
45 return false;
46 do {
47 if (seg == td->start_seg)
48 return true;
49 seg = seg->next;
50 } while (seg && seg != ring->first_seg);
51
52 return false;
53}
54
55/*
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
61 *
62 * Returns negative errno, or zero on success
63 *
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
67 */
68int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
69{
70 u32 result;
71 int ret;
72
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
75 result == U32_MAX,
76 1, timeout_us);
77 if (result == U32_MAX) /* card removed */
78 return -ENODEV;
79
80 return ret;
81}
82
83/*
84 * Disable interrupts and begin the xHCI halting process.
85 */
86void xhci_quiesce(struct xhci_hcd *xhci)
87{
88 u32 halted;
89 u32 cmd;
90 u32 mask;
91
92 mask = ~(XHCI_IRQS);
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
94 if (!halted)
95 mask &= ~CMD_RUN;
96
97 cmd = readl(&xhci->op_regs->command);
98 cmd &= mask;
99 writel(cmd, &xhci->op_regs->command);
100}
101
102/*
103 * Force HC into halt state.
104 *
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
109 */
110int xhci_halt(struct xhci_hcd *xhci)
111{
112 int ret;
113
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
115 xhci_quiesce(xhci);
116
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 if (ret) {
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
121 return ret;
122 }
123
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
126
127 return ret;
128}
129
130/*
131 * Set the run bit and wait for the host to be running.
132 */
133int xhci_start(struct xhci_hcd *xhci)
134{
135 u32 temp;
136 int ret;
137
138 temp = readl(&xhci->op_regs->command);
139 temp |= (CMD_RUN);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
141 temp);
142 writel(temp, &xhci->op_regs->command);
143
144 /*
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 * running.
147 */
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
153 XHCI_MAX_HALT_USEC);
154 if (!ret) {
155 /* clear state flags. Including dying, halted or removing */
156 xhci->xhc_state = 0;
157 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
158 }
159
160 return ret;
161}
162
163/*
164 * Reset a halted HC.
165 *
166 * This resets pipelines, timers, counters, state machines, etc.
167 * Transactions will be terminated immediately, and operational registers
168 * will be set to their defaults.
169 */
170int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
171{
172 u32 command;
173 u32 state;
174 int ret;
175
176 state = readl(&xhci->op_regs->status);
177
178 if (state == ~(u32)0) {
179 xhci_warn(xhci, "Host not accessible, reset failed.\n");
180 return -ENODEV;
181 }
182
183 if ((state & STS_HALT) == 0) {
184 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
185 return 0;
186 }
187
188 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
189 command = readl(&xhci->op_regs->command);
190 command |= CMD_RESET;
191 writel(command, &xhci->op_regs->command);
192
193 /* Existing Intel xHCI controllers require a delay of 1 mS,
194 * after setting the CMD_RESET bit, and before accessing any
195 * HC registers. This allows the HC to complete the
196 * reset operation and be ready for HC register access.
197 * Without this delay, the subsequent HC register access,
198 * may result in a system hang very rarely.
199 */
200 if (xhci->quirks & XHCI_INTEL_HOST)
201 udelay(1000);
202
203 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
204 if (ret)
205 return ret;
206
207 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
208 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
209
210 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
211 "Wait for controller to be ready for doorbell rings");
212 /*
213 * xHCI cannot write to any doorbells or operational registers other
214 * than status until the "Controller Not Ready" flag is cleared.
215 */
216 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
217
218 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb2_rhub.bus_state.suspended_ports = 0;
220 xhci->usb2_rhub.bus_state.resuming_ports = 0;
221 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
222 xhci->usb3_rhub.bus_state.suspended_ports = 0;
223 xhci->usb3_rhub.bus_state.resuming_ports = 0;
224
225 return ret;
226}
227
228static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
229{
230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
231 int err, i;
232 u64 val;
233 u32 intrs;
234
235 /*
236 * Some Renesas controllers get into a weird state if they are
237 * reset while programmed with 64bit addresses (they will preserve
238 * the top half of the address in internal, non visible
239 * registers). You end up with half the address coming from the
240 * kernel, and the other half coming from the firmware. Also,
241 * changing the programming leads to extra accesses even if the
242 * controller is supposed to be halted. The controller ends up with
243 * a fatal fault, and is then ripe for being properly reset.
244 *
245 * Special care is taken to only apply this if the device is behind
246 * an iommu. Doing anything when there is no iommu is definitely
247 * unsafe...
248 */
249 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
250 return;
251
252 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
253
254 /* Clear HSEIE so that faults do not get signaled */
255 val = readl(&xhci->op_regs->command);
256 val &= ~CMD_HSEIE;
257 writel(val, &xhci->op_regs->command);
258
259 /* Clear HSE (aka FATAL) */
260 val = readl(&xhci->op_regs->status);
261 val |= STS_FATAL;
262 writel(val, &xhci->op_regs->status);
263
264 /* Now zero the registers, and brace for impact */
265 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
268 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
269 if (upper_32_bits(val))
270 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
271
272 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
273 ARRAY_SIZE(xhci->run_regs->ir_set));
274
275 for (i = 0; i < intrs; i++) {
276 struct xhci_intr_reg __iomem *ir;
277
278 ir = &xhci->run_regs->ir_set[i];
279 val = xhci_read_64(xhci, &ir->erst_base);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_base);
282 val= xhci_read_64(xhci, &ir->erst_dequeue);
283 if (upper_32_bits(val))
284 xhci_write_64(xhci, 0, &ir->erst_dequeue);
285 }
286
287 /* Wait for the fault to appear. It will be cleared on reset */
288 err = xhci_handshake(&xhci->op_regs->status,
289 STS_FATAL, STS_FATAL,
290 XHCI_MAX_HALT_USEC);
291 if (!err)
292 xhci_info(xhci, "Fault detected\n");
293}
294
295#ifdef CONFIG_USB_PCI
296/*
297 * Set up MSI
298 */
299static int xhci_setup_msi(struct xhci_hcd *xhci)
300{
301 int ret;
302 /*
303 * TODO:Check with MSI Soc for sysdev
304 */
305 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
306
307 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
308 if (ret < 0) {
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "failed to allocate MSI entry");
311 return ret;
312 }
313
314 ret = request_irq(pdev->irq, xhci_msi_irq,
315 0, "xhci_hcd", xhci_to_hcd(xhci));
316 if (ret) {
317 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
318 "disable MSI interrupt");
319 pci_free_irq_vectors(pdev);
320 }
321
322 return ret;
323}
324
325/*
326 * Set up MSI-X
327 */
328static int xhci_setup_msix(struct xhci_hcd *xhci)
329{
330 int i, ret;
331 struct usb_hcd *hcd = xhci_to_hcd(xhci);
332 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
333
334 /*
335 * calculate number of msi-x vectors supported.
336 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
337 * with max number of interrupters based on the xhci HCSPARAMS1.
338 * - num_online_cpus: maximum msi-x vectors per CPUs core.
339 * Add additional 1 vector to ensure always available interrupt.
340 */
341 xhci->msix_count = min(num_online_cpus() + 1,
342 HCS_MAX_INTRS(xhci->hcs_params1));
343
344 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
345 PCI_IRQ_MSIX);
346 if (ret < 0) {
347 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
348 "Failed to enable MSI-X");
349 return ret;
350 }
351
352 for (i = 0; i < xhci->msix_count; i++) {
353 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
354 "xhci_hcd", xhci_to_hcd(xhci));
355 if (ret)
356 goto disable_msix;
357 }
358
359 hcd->msix_enabled = 1;
360 return ret;
361
362disable_msix:
363 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
364 while (--i >= 0)
365 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
366 pci_free_irq_vectors(pdev);
367 return ret;
368}
369
370/* Free any IRQs and disable MSI-X */
371static void xhci_cleanup_msix(struct xhci_hcd *xhci)
372{
373 struct usb_hcd *hcd = xhci_to_hcd(xhci);
374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
375
376 if (xhci->quirks & XHCI_PLAT)
377 return;
378
379 /* return if using legacy interrupt */
380 if (hcd->irq > 0)
381 return;
382
383 if (hcd->msix_enabled) {
384 int i;
385
386 for (i = 0; i < xhci->msix_count; i++)
387 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
388 } else {
389 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
390 }
391
392 pci_free_irq_vectors(pdev);
393 hcd->msix_enabled = 0;
394}
395
396static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
397{
398 struct usb_hcd *hcd = xhci_to_hcd(xhci);
399
400 if (hcd->msix_enabled) {
401 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
402 int i;
403
404 for (i = 0; i < xhci->msix_count; i++)
405 synchronize_irq(pci_irq_vector(pdev, i));
406 }
407}
408
409static int xhci_try_enable_msi(struct usb_hcd *hcd)
410{
411 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
412 struct pci_dev *pdev;
413 int ret;
414
415 /* The xhci platform device has set up IRQs through usb_add_hcd. */
416 if (xhci->quirks & XHCI_PLAT)
417 return 0;
418
419 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
420 /*
421 * Some Fresco Logic host controllers advertise MSI, but fail to
422 * generate interrupts. Don't even try to enable MSI.
423 */
424 if (xhci->quirks & XHCI_BROKEN_MSI)
425 goto legacy_irq;
426
427 /* unregister the legacy interrupt */
428 if (hcd->irq)
429 free_irq(hcd->irq, hcd);
430 hcd->irq = 0;
431
432 ret = xhci_setup_msix(xhci);
433 if (ret)
434 /* fall back to msi*/
435 ret = xhci_setup_msi(xhci);
436
437 if (!ret) {
438 hcd->msi_enabled = 1;
439 return 0;
440 }
441
442 if (!pdev->irq) {
443 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
444 return -EINVAL;
445 }
446
447 legacy_irq:
448 if (!strlen(hcd->irq_descr))
449 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
450 hcd->driver->description, hcd->self.busnum);
451
452 /* fall back to legacy interrupt*/
453 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
454 hcd->irq_descr, hcd);
455 if (ret) {
456 xhci_err(xhci, "request interrupt %d failed\n",
457 pdev->irq);
458 return ret;
459 }
460 hcd->irq = pdev->irq;
461 return 0;
462}
463
464#else
465
466static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
467{
468 return 0;
469}
470
471static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
472{
473}
474
475static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
476{
477}
478
479#endif
480
481static void compliance_mode_recovery(struct timer_list *t)
482{
483 struct xhci_hcd *xhci;
484 struct usb_hcd *hcd;
485 struct xhci_hub *rhub;
486 u32 temp;
487 int i;
488
489 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
490 rhub = &xhci->usb3_rhub;
491 hcd = rhub->hcd;
492
493 if (!hcd)
494 return;
495
496 for (i = 0; i < rhub->num_ports; i++) {
497 temp = readl(rhub->ports[i]->addr);
498 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
499 /*
500 * Compliance Mode Detected. Letting USB Core
501 * handle the Warm Reset
502 */
503 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
504 "Compliance mode detected->port %d",
505 i + 1);
506 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
507 "Attempting compliance mode recovery");
508
509 if (hcd->state == HC_STATE_SUSPENDED)
510 usb_hcd_resume_root_hub(hcd);
511
512 usb_hcd_poll_rh_status(hcd);
513 }
514 }
515
516 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
517 mod_timer(&xhci->comp_mode_recovery_timer,
518 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
519}
520
521/*
522 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
523 * that causes ports behind that hardware to enter compliance mode sometimes.
524 * The quirk creates a timer that polls every 2 seconds the link state of
525 * each host controller's port and recovers it by issuing a Warm reset
526 * if Compliance mode is detected, otherwise the port will become "dead" (no
527 * device connections or disconnections will be detected anymore). Becasue no
528 * status event is generated when entering compliance mode (per xhci spec),
529 * this quirk is needed on systems that have the failing hardware installed.
530 */
531static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
532{
533 xhci->port_status_u0 = 0;
534 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
535 0);
536 xhci->comp_mode_recovery_timer.expires = jiffies +
537 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
538
539 add_timer(&xhci->comp_mode_recovery_timer);
540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
541 "Compliance mode recovery timer initialized");
542}
543
544/*
545 * This function identifies the systems that have installed the SN65LVPE502CP
546 * USB3.0 re-driver and that need the Compliance Mode Quirk.
547 * Systems:
548 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
549 */
550static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
551{
552 const char *dmi_product_name, *dmi_sys_vendor;
553
554 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
555 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
556 if (!dmi_product_name || !dmi_sys_vendor)
557 return false;
558
559 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
560 return false;
561
562 if (strstr(dmi_product_name, "Z420") ||
563 strstr(dmi_product_name, "Z620") ||
564 strstr(dmi_product_name, "Z820") ||
565 strstr(dmi_product_name, "Z1 Workstation"))
566 return true;
567
568 return false;
569}
570
571static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
572{
573 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
574}
575
576
577/*
578 * Initialize memory for HCD and xHC (one-time init).
579 *
580 * Program the PAGESIZE register, initialize the device context array, create
581 * device contexts (?), set up a command ring segment (or two?), create event
582 * ring (one for now).
583 */
584static int xhci_init(struct usb_hcd *hcd)
585{
586 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
587 int retval;
588
589 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
590 spin_lock_init(&xhci->lock);
591 if (xhci->hci_version == 0x95 && link_quirk) {
592 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
593 "QUIRK: Not clearing Link TRB chain bits.");
594 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
595 } else {
596 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
597 "xHCI doesn't need link TRB QUIRK");
598 }
599 retval = xhci_mem_init(xhci, GFP_KERNEL);
600 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
601
602 /* Initializing Compliance Mode Recovery Data If Needed */
603 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
604 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
605 compliance_mode_recovery_timer_init(xhci);
606 }
607
608 return retval;
609}
610
611/*-------------------------------------------------------------------------*/
612
613
614static int xhci_run_finished(struct xhci_hcd *xhci)
615{
616 unsigned long flags;
617 u32 temp;
618
619 /*
620 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
621 * Protect the short window before host is running with a lock
622 */
623 spin_lock_irqsave(&xhci->lock, flags);
624
625 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
626 temp = readl(&xhci->op_regs->command);
627 temp |= (CMD_EIE);
628 writel(temp, &xhci->op_regs->command);
629
630 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
631 temp = readl(&xhci->ir_set->irq_pending);
632 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
633
634 if (xhci_start(xhci)) {
635 xhci_halt(xhci);
636 spin_unlock_irqrestore(&xhci->lock, flags);
637 return -ENODEV;
638 }
639
640 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
641
642 if (xhci->quirks & XHCI_NEC_HOST)
643 xhci_ring_cmd_db(xhci);
644
645 spin_unlock_irqrestore(&xhci->lock, flags);
646
647 return 0;
648}
649
650/*
651 * Start the HC after it was halted.
652 *
653 * This function is called by the USB core when the HC driver is added.
654 * Its opposite is xhci_stop().
655 *
656 * xhci_init() must be called once before this function can be called.
657 * Reset the HC, enable device slot contexts, program DCBAAP, and
658 * set command ring pointer and event ring pointer.
659 *
660 * Setup MSI-X vectors and enable interrupts.
661 */
662int xhci_run(struct usb_hcd *hcd)
663{
664 u32 temp;
665 u64 temp_64;
666 int ret;
667 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
668
669 /* Start the xHCI host controller running only after the USB 2.0 roothub
670 * is setup.
671 */
672
673 hcd->uses_new_polling = 1;
674 if (!usb_hcd_is_primary_hcd(hcd))
675 return xhci_run_finished(xhci);
676
677 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
678
679 ret = xhci_try_enable_msi(hcd);
680 if (ret)
681 return ret;
682
683 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
684 temp_64 &= ~ERST_PTR_MASK;
685 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
686 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
687
688 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
689 "// Set the interrupt modulation register");
690 temp = readl(&xhci->ir_set->irq_control);
691 temp &= ~ER_IRQ_INTERVAL_MASK;
692 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
693 writel(temp, &xhci->ir_set->irq_control);
694
695 if (xhci->quirks & XHCI_NEC_HOST) {
696 struct xhci_command *command;
697
698 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
699 if (!command)
700 return -ENOMEM;
701
702 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
703 TRB_TYPE(TRB_NEC_GET_FW));
704 if (ret)
705 xhci_free_command(xhci, command);
706 }
707 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
708 "Finished %s for main hcd", __func__);
709
710 xhci_create_dbc_dev(xhci);
711
712 xhci_debugfs_init(xhci);
713
714 if (xhci_has_one_roothub(xhci))
715 return xhci_run_finished(xhci);
716
717 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
718
719 return 0;
720}
721EXPORT_SYMBOL_GPL(xhci_run);
722
723/*
724 * Stop xHCI driver.
725 *
726 * This function is called by the USB core when the HC driver is removed.
727 * Its opposite is xhci_run().
728 *
729 * Disable device contexts, disable IRQs, and quiesce the HC.
730 * Reset the HC, finish any completed transactions, and cleanup memory.
731 */
732static void xhci_stop(struct usb_hcd *hcd)
733{
734 u32 temp;
735 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
736
737 mutex_lock(&xhci->mutex);
738
739 /* Only halt host and free memory after both hcds are removed */
740 if (!usb_hcd_is_primary_hcd(hcd)) {
741 mutex_unlock(&xhci->mutex);
742 return;
743 }
744
745 xhci_remove_dbc_dev(xhci);
746
747 spin_lock_irq(&xhci->lock);
748 xhci->xhc_state |= XHCI_STATE_HALTED;
749 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
750 xhci_halt(xhci);
751 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
752 spin_unlock_irq(&xhci->lock);
753
754 xhci_cleanup_msix(xhci);
755
756 /* Deleting Compliance Mode Recovery Timer */
757 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
758 (!(xhci_all_ports_seen_u0(xhci)))) {
759 del_timer_sync(&xhci->comp_mode_recovery_timer);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
761 "%s: compliance mode recovery timer deleted",
762 __func__);
763 }
764
765 if (xhci->quirks & XHCI_AMD_PLL_FIX)
766 usb_amd_dev_put();
767
768 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
769 "// Disabling event ring interrupts");
770 temp = readl(&xhci->op_regs->status);
771 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
772 temp = readl(&xhci->ir_set->irq_pending);
773 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
774
775 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
776 xhci_mem_cleanup(xhci);
777 xhci_debugfs_exit(xhci);
778 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
779 "xhci_stop completed - status = %x",
780 readl(&xhci->op_regs->status));
781 mutex_unlock(&xhci->mutex);
782}
783
784/*
785 * Shutdown HC (not bus-specific)
786 *
787 * This is called when the machine is rebooting or halting. We assume that the
788 * machine will be powered off, and the HC's internal state will be reset.
789 * Don't bother to free memory.
790 *
791 * This will only ever be called with the main usb_hcd (the USB3 roothub).
792 */
793void xhci_shutdown(struct usb_hcd *hcd)
794{
795 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
796
797 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
798 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
799
800 /* Don't poll the roothubs after shutdown. */
801 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
802 __func__, hcd->self.busnum);
803 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
804 del_timer_sync(&hcd->rh_timer);
805
806 if (xhci->shared_hcd) {
807 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
808 del_timer_sync(&xhci->shared_hcd->rh_timer);
809 }
810
811 spin_lock_irq(&xhci->lock);
812 xhci_halt(xhci);
813
814 /*
815 * Workaround for spurious wakeps at shutdown with HSW, and for boot
816 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
817 */
818 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
819 xhci->quirks & XHCI_RESET_TO_DEFAULT)
820 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
821
822 spin_unlock_irq(&xhci->lock);
823
824 xhci_cleanup_msix(xhci);
825
826 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
827 "xhci_shutdown completed - status = %x",
828 readl(&xhci->op_regs->status));
829}
830EXPORT_SYMBOL_GPL(xhci_shutdown);
831
832#ifdef CONFIG_PM
833static void xhci_save_registers(struct xhci_hcd *xhci)
834{
835 xhci->s3.command = readl(&xhci->op_regs->command);
836 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
837 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
838 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
839 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
840 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
841 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
842 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
843 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
844}
845
846static void xhci_restore_registers(struct xhci_hcd *xhci)
847{
848 writel(xhci->s3.command, &xhci->op_regs->command);
849 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
850 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
851 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
852 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
853 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
854 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
855 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
856 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
857}
858
859static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
860{
861 u64 val_64;
862
863 /* step 2: initialize command ring buffer */
864 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
865 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
866 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
867 xhci->cmd_ring->dequeue) &
868 (u64) ~CMD_RING_RSVD_BITS) |
869 xhci->cmd_ring->cycle_state;
870 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
871 "// Setting command ring address to 0x%llx",
872 (long unsigned long) val_64);
873 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
874}
875
876/*
877 * The whole command ring must be cleared to zero when we suspend the host.
878 *
879 * The host doesn't save the command ring pointer in the suspend well, so we
880 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
881 * aligned, because of the reserved bits in the command ring dequeue pointer
882 * register. Therefore, we can't just set the dequeue pointer back in the
883 * middle of the ring (TRBs are 16-byte aligned).
884 */
885static void xhci_clear_command_ring(struct xhci_hcd *xhci)
886{
887 struct xhci_ring *ring;
888 struct xhci_segment *seg;
889
890 ring = xhci->cmd_ring;
891 seg = ring->deq_seg;
892 do {
893 memset(seg->trbs, 0,
894 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
895 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
896 cpu_to_le32(~TRB_CYCLE);
897 seg = seg->next;
898 } while (seg != ring->deq_seg);
899
900 /* Reset the software enqueue and dequeue pointers */
901 ring->deq_seg = ring->first_seg;
902 ring->dequeue = ring->first_seg->trbs;
903 ring->enq_seg = ring->deq_seg;
904 ring->enqueue = ring->dequeue;
905
906 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
907 /*
908 * Ring is now zeroed, so the HW should look for change of ownership
909 * when the cycle bit is set to 1.
910 */
911 ring->cycle_state = 1;
912
913 /*
914 * Reset the hardware dequeue pointer.
915 * Yes, this will need to be re-written after resume, but we're paranoid
916 * and want to make sure the hardware doesn't access bogus memory
917 * because, say, the BIOS or an SMI started the host without changing
918 * the command ring pointers.
919 */
920 xhci_set_cmd_ring_deq(xhci);
921}
922
923/*
924 * Disable port wake bits if do_wakeup is not set.
925 *
926 * Also clear a possible internal port wake state left hanging for ports that
927 * detected termination but never successfully enumerated (trained to 0U).
928 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
929 * at enumeration clears this wake, force one here as well for unconnected ports
930 */
931
932static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
933 struct xhci_hub *rhub,
934 bool do_wakeup)
935{
936 unsigned long flags;
937 u32 t1, t2, portsc;
938 int i;
939
940 spin_lock_irqsave(&xhci->lock, flags);
941
942 for (i = 0; i < rhub->num_ports; i++) {
943 portsc = readl(rhub->ports[i]->addr);
944 t1 = xhci_port_state_to_neutral(portsc);
945 t2 = t1;
946
947 /* clear wake bits if do_wake is not set */
948 if (!do_wakeup)
949 t2 &= ~PORT_WAKE_BITS;
950
951 /* Don't touch csc bit if connected or connect change is set */
952 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
953 t2 |= PORT_CSC;
954
955 if (t1 != t2) {
956 writel(t2, rhub->ports[i]->addr);
957 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
958 rhub->hcd->self.busnum, i + 1, portsc, t2);
959 }
960 }
961 spin_unlock_irqrestore(&xhci->lock, flags);
962}
963
964static bool xhci_pending_portevent(struct xhci_hcd *xhci)
965{
966 struct xhci_port **ports;
967 int port_index;
968 u32 status;
969 u32 portsc;
970
971 status = readl(&xhci->op_regs->status);
972 if (status & STS_EINT)
973 return true;
974 /*
975 * Checking STS_EINT is not enough as there is a lag between a change
976 * bit being set and the Port Status Change Event that it generated
977 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
978 */
979
980 port_index = xhci->usb2_rhub.num_ports;
981 ports = xhci->usb2_rhub.ports;
982 while (port_index--) {
983 portsc = readl(ports[port_index]->addr);
984 if (portsc & PORT_CHANGE_MASK ||
985 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
986 return true;
987 }
988 port_index = xhci->usb3_rhub.num_ports;
989 ports = xhci->usb3_rhub.ports;
990 while (port_index--) {
991 portsc = readl(ports[port_index]->addr);
992 if (portsc & PORT_CHANGE_MASK ||
993 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
994 return true;
995 }
996 return false;
997}
998
999/*
1000 * Stop HC (not bus-specific)
1001 *
1002 * This is called when the machine transition into S3/S4 mode.
1003 *
1004 */
1005int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
1006{
1007 int rc = 0;
1008 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
1009 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1010 u32 command;
1011 u32 res;
1012
1013 if (!hcd->state)
1014 return 0;
1015
1016 if (hcd->state != HC_STATE_SUSPENDED ||
1017 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
1018 return -EINVAL;
1019
1020 /* Clear root port wake on bits if wakeup not allowed. */
1021 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1022 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1023
1024 if (!HCD_HW_ACCESSIBLE(hcd))
1025 return 0;
1026
1027 xhci_dbc_suspend(xhci);
1028
1029 /* Don't poll the roothubs on bus suspend. */
1030 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1031 __func__, hcd->self.busnum);
1032 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1033 del_timer_sync(&hcd->rh_timer);
1034 if (xhci->shared_hcd) {
1035 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1036 del_timer_sync(&xhci->shared_hcd->rh_timer);
1037 }
1038
1039 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1040 usleep_range(1000, 1500);
1041
1042 spin_lock_irq(&xhci->lock);
1043 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1044 if (xhci->shared_hcd)
1045 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1046 /* step 1: stop endpoint */
1047 /* skipped assuming that port suspend has done */
1048
1049 /* step 2: clear Run/Stop bit */
1050 command = readl(&xhci->op_regs->command);
1051 command &= ~CMD_RUN;
1052 writel(command, &xhci->op_regs->command);
1053
1054 /* Some chips from Fresco Logic need an extraordinary delay */
1055 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1056
1057 if (xhci_handshake(&xhci->op_regs->status,
1058 STS_HALT, STS_HALT, delay)) {
1059 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1060 spin_unlock_irq(&xhci->lock);
1061 return -ETIMEDOUT;
1062 }
1063 xhci_clear_command_ring(xhci);
1064
1065 /* step 3: save registers */
1066 xhci_save_registers(xhci);
1067
1068 /* step 4: set CSS flag */
1069 command = readl(&xhci->op_regs->command);
1070 command |= CMD_CSS;
1071 writel(command, &xhci->op_regs->command);
1072 xhci->broken_suspend = 0;
1073 if (xhci_handshake(&xhci->op_regs->status,
1074 STS_SAVE, 0, 20 * 1000)) {
1075 /*
1076 * AMD SNPS xHC 3.0 occasionally does not clear the
1077 * SSS bit of USBSTS and when driver tries to poll
1078 * to see if the xHC clears BIT(8) which never happens
1079 * and driver assumes that controller is not responding
1080 * and times out. To workaround this, its good to check
1081 * if SRE and HCE bits are not set (as per xhci
1082 * Section 5.4.2) and bypass the timeout.
1083 */
1084 res = readl(&xhci->op_regs->status);
1085 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1086 (((res & STS_SRE) == 0) &&
1087 ((res & STS_HCE) == 0))) {
1088 xhci->broken_suspend = 1;
1089 } else {
1090 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1091 spin_unlock_irq(&xhci->lock);
1092 return -ETIMEDOUT;
1093 }
1094 }
1095 spin_unlock_irq(&xhci->lock);
1096
1097 /*
1098 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1099 * is about to be suspended.
1100 */
1101 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1102 (!(xhci_all_ports_seen_u0(xhci)))) {
1103 del_timer_sync(&xhci->comp_mode_recovery_timer);
1104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1105 "%s: compliance mode recovery timer deleted",
1106 __func__);
1107 }
1108
1109 /* step 5: remove core well power */
1110 /* synchronize irq when using MSI-X */
1111 xhci_msix_sync_irqs(xhci);
1112
1113 return rc;
1114}
1115EXPORT_SYMBOL_GPL(xhci_suspend);
1116
1117/*
1118 * start xHC (not bus-specific)
1119 *
1120 * This is called when the machine transition from S3/S4 mode.
1121 *
1122 */
1123int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1124{
1125 u32 command, temp = 0;
1126 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1127 int retval = 0;
1128 bool comp_timer_running = false;
1129 bool pending_portevent = false;
1130 bool reinit_xhc = false;
1131
1132 if (!hcd->state)
1133 return 0;
1134
1135 /* Wait a bit if either of the roothubs need to settle from the
1136 * transition into bus suspend.
1137 */
1138
1139 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1140 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1141 msleep(100);
1142
1143 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1144 if (xhci->shared_hcd)
1145 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1146
1147 spin_lock_irq(&xhci->lock);
1148
1149 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1150 reinit_xhc = true;
1151
1152 if (!reinit_xhc) {
1153 /*
1154 * Some controllers might lose power during suspend, so wait
1155 * for controller not ready bit to clear, just as in xHC init.
1156 */
1157 retval = xhci_handshake(&xhci->op_regs->status,
1158 STS_CNR, 0, 10 * 1000 * 1000);
1159 if (retval) {
1160 xhci_warn(xhci, "Controller not ready at resume %d\n",
1161 retval);
1162 spin_unlock_irq(&xhci->lock);
1163 return retval;
1164 }
1165 /* step 1: restore register */
1166 xhci_restore_registers(xhci);
1167 /* step 2: initialize command ring buffer */
1168 xhci_set_cmd_ring_deq(xhci);
1169 /* step 3: restore state and start state*/
1170 /* step 3: set CRS flag */
1171 command = readl(&xhci->op_regs->command);
1172 command |= CMD_CRS;
1173 writel(command, &xhci->op_regs->command);
1174 /*
1175 * Some controllers take up to 55+ ms to complete the controller
1176 * restore so setting the timeout to 100ms. Xhci specification
1177 * doesn't mention any timeout value.
1178 */
1179 if (xhci_handshake(&xhci->op_regs->status,
1180 STS_RESTORE, 0, 100 * 1000)) {
1181 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1182 spin_unlock_irq(&xhci->lock);
1183 return -ETIMEDOUT;
1184 }
1185 }
1186
1187 temp = readl(&xhci->op_regs->status);
1188
1189 /* re-initialize the HC on Restore Error, or Host Controller Error */
1190 if (temp & (STS_SRE | STS_HCE)) {
1191 reinit_xhc = true;
1192 if (!xhci->broken_suspend)
1193 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1194 }
1195
1196 if (reinit_xhc) {
1197 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1198 !(xhci_all_ports_seen_u0(xhci))) {
1199 del_timer_sync(&xhci->comp_mode_recovery_timer);
1200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1201 "Compliance Mode Recovery Timer deleted!");
1202 }
1203
1204 /* Let the USB core know _both_ roothubs lost power. */
1205 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1206 if (xhci->shared_hcd)
1207 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1208
1209 xhci_dbg(xhci, "Stop HCD\n");
1210 xhci_halt(xhci);
1211 xhci_zero_64b_regs(xhci);
1212 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1213 spin_unlock_irq(&xhci->lock);
1214 if (retval)
1215 return retval;
1216 xhci_cleanup_msix(xhci);
1217
1218 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1219 temp = readl(&xhci->op_regs->status);
1220 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1221 temp = readl(&xhci->ir_set->irq_pending);
1222 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1223
1224 xhci_dbg(xhci, "cleaning up memory\n");
1225 xhci_mem_cleanup(xhci);
1226 xhci_debugfs_exit(xhci);
1227 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1228 readl(&xhci->op_regs->status));
1229
1230 /* USB core calls the PCI reinit and start functions twice:
1231 * first with the primary HCD, and then with the secondary HCD.
1232 * If we don't do the same, the host will never be started.
1233 */
1234 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1235 retval = xhci_init(hcd);
1236 if (retval)
1237 return retval;
1238 comp_timer_running = true;
1239
1240 xhci_dbg(xhci, "Start the primary HCD\n");
1241 retval = xhci_run(hcd);
1242 if (!retval && xhci->shared_hcd) {
1243 xhci_dbg(xhci, "Start the secondary HCD\n");
1244 retval = xhci_run(xhci->shared_hcd);
1245 }
1246
1247 hcd->state = HC_STATE_SUSPENDED;
1248 if (xhci->shared_hcd)
1249 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1250 goto done;
1251 }
1252
1253 /* step 4: set Run/Stop bit */
1254 command = readl(&xhci->op_regs->command);
1255 command |= CMD_RUN;
1256 writel(command, &xhci->op_regs->command);
1257 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1258 0, 250 * 1000);
1259
1260 /* step 5: walk topology and initialize portsc,
1261 * portpmsc and portli
1262 */
1263 /* this is done in bus_resume */
1264
1265 /* step 6: restart each of the previously
1266 * Running endpoints by ringing their doorbells
1267 */
1268
1269 spin_unlock_irq(&xhci->lock);
1270
1271 xhci_dbc_resume(xhci);
1272
1273 done:
1274 if (retval == 0) {
1275 /*
1276 * Resume roothubs only if there are pending events.
1277 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1278 * the first wake signalling failed, give it that chance.
1279 */
1280 pending_portevent = xhci_pending_portevent(xhci);
1281 if (!pending_portevent) {
1282 msleep(120);
1283 pending_portevent = xhci_pending_portevent(xhci);
1284 }
1285
1286 if (pending_portevent) {
1287 if (xhci->shared_hcd)
1288 usb_hcd_resume_root_hub(xhci->shared_hcd);
1289 usb_hcd_resume_root_hub(hcd);
1290 }
1291 }
1292 /*
1293 * If system is subject to the Quirk, Compliance Mode Timer needs to
1294 * be re-initialized Always after a system resume. Ports are subject
1295 * to suffer the Compliance Mode issue again. It doesn't matter if
1296 * ports have entered previously to U0 before system's suspension.
1297 */
1298 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1299 compliance_mode_recovery_timer_init(xhci);
1300
1301 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1302 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1303
1304 /* Re-enable port polling. */
1305 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1306 __func__, hcd->self.busnum);
1307 if (xhci->shared_hcd) {
1308 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1309 usb_hcd_poll_rh_status(xhci->shared_hcd);
1310 }
1311 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1312 usb_hcd_poll_rh_status(hcd);
1313
1314 return retval;
1315}
1316EXPORT_SYMBOL_GPL(xhci_resume);
1317#endif /* CONFIG_PM */
1318
1319/*-------------------------------------------------------------------------*/
1320
1321static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1322{
1323 void *temp;
1324 int ret = 0;
1325 unsigned int buf_len;
1326 enum dma_data_direction dir;
1327
1328 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1329 buf_len = urb->transfer_buffer_length;
1330
1331 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1332 dev_to_node(hcd->self.sysdev));
1333
1334 if (usb_urb_dir_out(urb))
1335 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1336 temp, buf_len, 0);
1337
1338 urb->transfer_buffer = temp;
1339 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1340 urb->transfer_buffer,
1341 urb->transfer_buffer_length,
1342 dir);
1343
1344 if (dma_mapping_error(hcd->self.sysdev,
1345 urb->transfer_dma)) {
1346 ret = -EAGAIN;
1347 kfree(temp);
1348 } else {
1349 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1350 }
1351
1352 return ret;
1353}
1354
1355static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1356 struct urb *urb)
1357{
1358 bool ret = false;
1359 unsigned int i;
1360 unsigned int len = 0;
1361 unsigned int trb_size;
1362 unsigned int max_pkt;
1363 struct scatterlist *sg;
1364 struct scatterlist *tail_sg;
1365
1366 tail_sg = urb->sg;
1367 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1368
1369 if (!urb->num_sgs)
1370 return ret;
1371
1372 if (urb->dev->speed >= USB_SPEED_SUPER)
1373 trb_size = TRB_CACHE_SIZE_SS;
1374 else
1375 trb_size = TRB_CACHE_SIZE_HS;
1376
1377 if (urb->transfer_buffer_length != 0 &&
1378 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1379 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1380 len = len + sg->length;
1381 if (i > trb_size - 2) {
1382 len = len - tail_sg->length;
1383 if (len < max_pkt) {
1384 ret = true;
1385 break;
1386 }
1387
1388 tail_sg = sg_next(tail_sg);
1389 }
1390 }
1391 }
1392 return ret;
1393}
1394
1395static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1396{
1397 unsigned int len;
1398 unsigned int buf_len;
1399 enum dma_data_direction dir;
1400
1401 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1402
1403 buf_len = urb->transfer_buffer_length;
1404
1405 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1406 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1407 dma_unmap_single(hcd->self.sysdev,
1408 urb->transfer_dma,
1409 urb->transfer_buffer_length,
1410 dir);
1411
1412 if (usb_urb_dir_in(urb)) {
1413 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1414 urb->transfer_buffer,
1415 buf_len,
1416 0);
1417 if (len != buf_len) {
1418 xhci_dbg(hcd_to_xhci(hcd),
1419 "Copy from tmp buf to urb sg list failed\n");
1420 urb->actual_length = len;
1421 }
1422 }
1423 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1424 kfree(urb->transfer_buffer);
1425 urb->transfer_buffer = NULL;
1426}
1427
1428/*
1429 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1430 * we'll copy the actual data into the TRB address register. This is limited to
1431 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1432 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1433 */
1434static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1435 gfp_t mem_flags)
1436{
1437 struct xhci_hcd *xhci;
1438
1439 xhci = hcd_to_xhci(hcd);
1440
1441 if (xhci_urb_suitable_for_idt(urb))
1442 return 0;
1443
1444 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1445 if (xhci_urb_temp_buffer_required(hcd, urb))
1446 return xhci_map_temp_buffer(hcd, urb);
1447 }
1448 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1449}
1450
1451static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1452{
1453 struct xhci_hcd *xhci;
1454 bool unmap_temp_buf = false;
1455
1456 xhci = hcd_to_xhci(hcd);
1457
1458 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1459 unmap_temp_buf = true;
1460
1461 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1462 xhci_unmap_temp_buf(hcd, urb);
1463 else
1464 usb_hcd_unmap_urb_for_dma(hcd, urb);
1465}
1466
1467/**
1468 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1469 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1470 * value to right shift 1 for the bitmask.
1471 *
1472 * Index = (epnum * 2) + direction - 1,
1473 * where direction = 0 for OUT, 1 for IN.
1474 * For control endpoints, the IN index is used (OUT index is unused), so
1475 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1476 */
1477unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1478{
1479 unsigned int index;
1480 if (usb_endpoint_xfer_control(desc))
1481 index = (unsigned int) (usb_endpoint_num(desc)*2);
1482 else
1483 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1484 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1485 return index;
1486}
1487EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1488
1489/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1490 * address from the XHCI endpoint index.
1491 */
1492static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1493{
1494 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1495 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1496 return direction | number;
1497}
1498
1499/* Find the flag for this endpoint (for use in the control context). Use the
1500 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1501 * bit 1, etc.
1502 */
1503static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1504{
1505 return 1 << (xhci_get_endpoint_index(desc) + 1);
1506}
1507
1508/* Compute the last valid endpoint context index. Basically, this is the
1509 * endpoint index plus one. For slot contexts with more than valid endpoint,
1510 * we find the most significant bit set in the added contexts flags.
1511 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1512 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1513 */
1514unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1515{
1516 return fls(added_ctxs) - 1;
1517}
1518
1519/* Returns 1 if the arguments are OK;
1520 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1521 */
1522static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1523 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1524 const char *func) {
1525 struct xhci_hcd *xhci;
1526 struct xhci_virt_device *virt_dev;
1527
1528 if (!hcd || (check_ep && !ep) || !udev) {
1529 pr_debug("xHCI %s called with invalid args\n", func);
1530 return -EINVAL;
1531 }
1532 if (!udev->parent) {
1533 pr_debug("xHCI %s called for root hub\n", func);
1534 return 0;
1535 }
1536
1537 xhci = hcd_to_xhci(hcd);
1538 if (check_virt_dev) {
1539 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1540 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1541 func);
1542 return -EINVAL;
1543 }
1544
1545 virt_dev = xhci->devs[udev->slot_id];
1546 if (virt_dev->udev != udev) {
1547 xhci_dbg(xhci, "xHCI %s called with udev and "
1548 "virt_dev does not match\n", func);
1549 return -EINVAL;
1550 }
1551 }
1552
1553 if (xhci->xhc_state & XHCI_STATE_HALTED)
1554 return -ENODEV;
1555
1556 return 1;
1557}
1558
1559static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1560 struct usb_device *udev, struct xhci_command *command,
1561 bool ctx_change, bool must_succeed);
1562
1563/*
1564 * Full speed devices may have a max packet size greater than 8 bytes, but the
1565 * USB core doesn't know that until it reads the first 8 bytes of the
1566 * descriptor. If the usb_device's max packet size changes after that point,
1567 * we need to issue an evaluate context command and wait on it.
1568 */
1569static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1570 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1571{
1572 struct xhci_container_ctx *out_ctx;
1573 struct xhci_input_control_ctx *ctrl_ctx;
1574 struct xhci_ep_ctx *ep_ctx;
1575 struct xhci_command *command;
1576 int max_packet_size;
1577 int hw_max_packet_size;
1578 int ret = 0;
1579
1580 out_ctx = xhci->devs[slot_id]->out_ctx;
1581 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1582 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1583 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1584 if (hw_max_packet_size != max_packet_size) {
1585 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1586 "Max Packet Size for ep 0 changed.");
1587 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1588 "Max packet size in usb_device = %d",
1589 max_packet_size);
1590 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1591 "Max packet size in xHCI HW = %d",
1592 hw_max_packet_size);
1593 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1594 "Issuing evaluate context command.");
1595
1596 /* Set up the input context flags for the command */
1597 /* FIXME: This won't work if a non-default control endpoint
1598 * changes max packet sizes.
1599 */
1600
1601 command = xhci_alloc_command(xhci, true, mem_flags);
1602 if (!command)
1603 return -ENOMEM;
1604
1605 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1606 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1607 if (!ctrl_ctx) {
1608 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1609 __func__);
1610 ret = -ENOMEM;
1611 goto command_cleanup;
1612 }
1613 /* Set up the modified control endpoint 0 */
1614 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1615 xhci->devs[slot_id]->out_ctx, ep_index);
1616
1617 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1618 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1619 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1620 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1621
1622 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1623 ctrl_ctx->drop_flags = 0;
1624
1625 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1626 true, false);
1627
1628 /* Clean up the input context for later use by bandwidth
1629 * functions.
1630 */
1631 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1632command_cleanup:
1633 kfree(command->completion);
1634 kfree(command);
1635 }
1636 return ret;
1637}
1638
1639/*
1640 * non-error returns are a promise to giveback() the urb later
1641 * we drop ownership so next owner (or urb unlink) can get it
1642 */
1643static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1644{
1645 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1646 unsigned long flags;
1647 int ret = 0;
1648 unsigned int slot_id, ep_index;
1649 unsigned int *ep_state;
1650 struct urb_priv *urb_priv;
1651 int num_tds;
1652
1653 if (!urb)
1654 return -EINVAL;
1655 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1656 true, true, __func__);
1657 if (ret <= 0)
1658 return ret ? ret : -EINVAL;
1659
1660 slot_id = urb->dev->slot_id;
1661 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1662 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1663
1664 if (!HCD_HW_ACCESSIBLE(hcd))
1665 return -ESHUTDOWN;
1666
1667 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1668 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1669 return -ENODEV;
1670 }
1671
1672 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1673 num_tds = urb->number_of_packets;
1674 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1675 urb->transfer_buffer_length > 0 &&
1676 urb->transfer_flags & URB_ZERO_PACKET &&
1677 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1678 num_tds = 2;
1679 else
1680 num_tds = 1;
1681
1682 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1683 if (!urb_priv)
1684 return -ENOMEM;
1685
1686 urb_priv->num_tds = num_tds;
1687 urb_priv->num_tds_done = 0;
1688 urb->hcpriv = urb_priv;
1689
1690 trace_xhci_urb_enqueue(urb);
1691
1692 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1693 /* Check to see if the max packet size for the default control
1694 * endpoint changed during FS device enumeration
1695 */
1696 if (urb->dev->speed == USB_SPEED_FULL) {
1697 ret = xhci_check_maxpacket(xhci, slot_id,
1698 ep_index, urb, mem_flags);
1699 if (ret < 0) {
1700 xhci_urb_free_priv(urb_priv);
1701 urb->hcpriv = NULL;
1702 return ret;
1703 }
1704 }
1705 }
1706
1707 spin_lock_irqsave(&xhci->lock, flags);
1708
1709 if (xhci->xhc_state & XHCI_STATE_DYING) {
1710 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1711 urb->ep->desc.bEndpointAddress, urb);
1712 ret = -ESHUTDOWN;
1713 goto free_priv;
1714 }
1715 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1716 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1717 *ep_state);
1718 ret = -EINVAL;
1719 goto free_priv;
1720 }
1721 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1722 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1723 ret = -EINVAL;
1724 goto free_priv;
1725 }
1726
1727 switch (usb_endpoint_type(&urb->ep->desc)) {
1728
1729 case USB_ENDPOINT_XFER_CONTROL:
1730 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1731 slot_id, ep_index);
1732 break;
1733 case USB_ENDPOINT_XFER_BULK:
1734 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1735 slot_id, ep_index);
1736 break;
1737 case USB_ENDPOINT_XFER_INT:
1738 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1739 slot_id, ep_index);
1740 break;
1741 case USB_ENDPOINT_XFER_ISOC:
1742 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1743 slot_id, ep_index);
1744 }
1745
1746 if (ret) {
1747free_priv:
1748 xhci_urb_free_priv(urb_priv);
1749 urb->hcpriv = NULL;
1750 }
1751 spin_unlock_irqrestore(&xhci->lock, flags);
1752 return ret;
1753}
1754
1755/*
1756 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1757 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1758 * should pick up where it left off in the TD, unless a Set Transfer Ring
1759 * Dequeue Pointer is issued.
1760 *
1761 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1762 * the ring. Since the ring is a contiguous structure, they can't be physically
1763 * removed. Instead, there are two options:
1764 *
1765 * 1) If the HC is in the middle of processing the URB to be canceled, we
1766 * simply move the ring's dequeue pointer past those TRBs using the Set
1767 * Transfer Ring Dequeue Pointer command. This will be the common case,
1768 * when drivers timeout on the last submitted URB and attempt to cancel.
1769 *
1770 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1771 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1772 * HC will need to invalidate the any TRBs it has cached after the stop
1773 * endpoint command, as noted in the xHCI 0.95 errata.
1774 *
1775 * 3) The TD may have completed by the time the Stop Endpoint Command
1776 * completes, so software needs to handle that case too.
1777 *
1778 * This function should protect against the TD enqueueing code ringing the
1779 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1780 * It also needs to account for multiple cancellations on happening at the same
1781 * time for the same endpoint.
1782 *
1783 * Note that this function can be called in any context, or so says
1784 * usb_hcd_unlink_urb()
1785 */
1786static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1787{
1788 unsigned long flags;
1789 int ret, i;
1790 u32 temp;
1791 struct xhci_hcd *xhci;
1792 struct urb_priv *urb_priv;
1793 struct xhci_td *td;
1794 unsigned int ep_index;
1795 struct xhci_ring *ep_ring;
1796 struct xhci_virt_ep *ep;
1797 struct xhci_command *command;
1798 struct xhci_virt_device *vdev;
1799
1800 xhci = hcd_to_xhci(hcd);
1801 spin_lock_irqsave(&xhci->lock, flags);
1802
1803 trace_xhci_urb_dequeue(urb);
1804
1805 /* Make sure the URB hasn't completed or been unlinked already */
1806 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1807 if (ret)
1808 goto done;
1809
1810 /* give back URB now if we can't queue it for cancel */
1811 vdev = xhci->devs[urb->dev->slot_id];
1812 urb_priv = urb->hcpriv;
1813 if (!vdev || !urb_priv)
1814 goto err_giveback;
1815
1816 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1817 ep = &vdev->eps[ep_index];
1818 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1819 if (!ep || !ep_ring)
1820 goto err_giveback;
1821
1822 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1823 temp = readl(&xhci->op_regs->status);
1824 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1825 xhci_hc_died(xhci);
1826 goto done;
1827 }
1828
1829 /*
1830 * check ring is not re-allocated since URB was enqueued. If it is, then
1831 * make sure none of the ring related pointers in this URB private data
1832 * are touched, such as td_list, otherwise we overwrite freed data
1833 */
1834 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1835 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1836 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1837 td = &urb_priv->td[i];
1838 if (!list_empty(&td->cancelled_td_list))
1839 list_del_init(&td->cancelled_td_list);
1840 }
1841 goto err_giveback;
1842 }
1843
1844 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1845 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1846 "HC halted, freeing TD manually.");
1847 for (i = urb_priv->num_tds_done;
1848 i < urb_priv->num_tds;
1849 i++) {
1850 td = &urb_priv->td[i];
1851 if (!list_empty(&td->td_list))
1852 list_del_init(&td->td_list);
1853 if (!list_empty(&td->cancelled_td_list))
1854 list_del_init(&td->cancelled_td_list);
1855 }
1856 goto err_giveback;
1857 }
1858
1859 i = urb_priv->num_tds_done;
1860 if (i < urb_priv->num_tds)
1861 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1862 "Cancel URB %p, dev %s, ep 0x%x, "
1863 "starting at offset 0x%llx",
1864 urb, urb->dev->devpath,
1865 urb->ep->desc.bEndpointAddress,
1866 (unsigned long long) xhci_trb_virt_to_dma(
1867 urb_priv->td[i].start_seg,
1868 urb_priv->td[i].first_trb));
1869
1870 for (; i < urb_priv->num_tds; i++) {
1871 td = &urb_priv->td[i];
1872 /* TD can already be on cancelled list if ep halted on it */
1873 if (list_empty(&td->cancelled_td_list)) {
1874 td->cancel_status = TD_DIRTY;
1875 list_add_tail(&td->cancelled_td_list,
1876 &ep->cancelled_td_list);
1877 }
1878 }
1879
1880 /* Queue a stop endpoint command, but only if this is
1881 * the first cancellation to be handled.
1882 */
1883 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1884 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1885 if (!command) {
1886 ret = -ENOMEM;
1887 goto done;
1888 }
1889 ep->ep_state |= EP_STOP_CMD_PENDING;
1890 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1891 ep_index, 0);
1892 xhci_ring_cmd_db(xhci);
1893 }
1894done:
1895 spin_unlock_irqrestore(&xhci->lock, flags);
1896 return ret;
1897
1898err_giveback:
1899 if (urb_priv)
1900 xhci_urb_free_priv(urb_priv);
1901 usb_hcd_unlink_urb_from_ep(hcd, urb);
1902 spin_unlock_irqrestore(&xhci->lock, flags);
1903 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1904 return ret;
1905}
1906
1907/* Drop an endpoint from a new bandwidth configuration for this device.
1908 * Only one call to this function is allowed per endpoint before
1909 * check_bandwidth() or reset_bandwidth() must be called.
1910 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1911 * add the endpoint to the schedule with possibly new parameters denoted by a
1912 * different endpoint descriptor in usb_host_endpoint.
1913 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1914 * not allowed.
1915 *
1916 * The USB core will not allow URBs to be queued to an endpoint that is being
1917 * disabled, so there's no need for mutual exclusion to protect
1918 * the xhci->devs[slot_id] structure.
1919 */
1920int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1921 struct usb_host_endpoint *ep)
1922{
1923 struct xhci_hcd *xhci;
1924 struct xhci_container_ctx *in_ctx, *out_ctx;
1925 struct xhci_input_control_ctx *ctrl_ctx;
1926 unsigned int ep_index;
1927 struct xhci_ep_ctx *ep_ctx;
1928 u32 drop_flag;
1929 u32 new_add_flags, new_drop_flags;
1930 int ret;
1931
1932 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1933 if (ret <= 0)
1934 return ret;
1935 xhci = hcd_to_xhci(hcd);
1936 if (xhci->xhc_state & XHCI_STATE_DYING)
1937 return -ENODEV;
1938
1939 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1940 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1941 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1942 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1943 __func__, drop_flag);
1944 return 0;
1945 }
1946
1947 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1948 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1949 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1950 if (!ctrl_ctx) {
1951 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1952 __func__);
1953 return 0;
1954 }
1955
1956 ep_index = xhci_get_endpoint_index(&ep->desc);
1957 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1958 /* If the HC already knows the endpoint is disabled,
1959 * or the HCD has noted it is disabled, ignore this request
1960 */
1961 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1962 le32_to_cpu(ctrl_ctx->drop_flags) &
1963 xhci_get_endpoint_flag(&ep->desc)) {
1964 /* Do not warn when called after a usb_device_reset */
1965 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1966 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1967 __func__, ep);
1968 return 0;
1969 }
1970
1971 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1972 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1973
1974 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1975 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1976
1977 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1978
1979 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1980
1981 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1982 (unsigned int) ep->desc.bEndpointAddress,
1983 udev->slot_id,
1984 (unsigned int) new_drop_flags,
1985 (unsigned int) new_add_flags);
1986 return 0;
1987}
1988EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1989
1990/* Add an endpoint to a new possible bandwidth configuration for this device.
1991 * Only one call to this function is allowed per endpoint before
1992 * check_bandwidth() or reset_bandwidth() must be called.
1993 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1994 * add the endpoint to the schedule with possibly new parameters denoted by a
1995 * different endpoint descriptor in usb_host_endpoint.
1996 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1997 * not allowed.
1998 *
1999 * The USB core will not allow URBs to be queued to an endpoint until the
2000 * configuration or alt setting is installed in the device, so there's no need
2001 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
2002 */
2003int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2004 struct usb_host_endpoint *ep)
2005{
2006 struct xhci_hcd *xhci;
2007 struct xhci_container_ctx *in_ctx;
2008 unsigned int ep_index;
2009 struct xhci_input_control_ctx *ctrl_ctx;
2010 struct xhci_ep_ctx *ep_ctx;
2011 u32 added_ctxs;
2012 u32 new_add_flags, new_drop_flags;
2013 struct xhci_virt_device *virt_dev;
2014 int ret = 0;
2015
2016 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2017 if (ret <= 0) {
2018 /* So we won't queue a reset ep command for a root hub */
2019 ep->hcpriv = NULL;
2020 return ret;
2021 }
2022 xhci = hcd_to_xhci(hcd);
2023 if (xhci->xhc_state & XHCI_STATE_DYING)
2024 return -ENODEV;
2025
2026 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2027 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2028 /* FIXME when we have to issue an evaluate endpoint command to
2029 * deal with ep0 max packet size changing once we get the
2030 * descriptors
2031 */
2032 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2033 __func__, added_ctxs);
2034 return 0;
2035 }
2036
2037 virt_dev = xhci->devs[udev->slot_id];
2038 in_ctx = virt_dev->in_ctx;
2039 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2040 if (!ctrl_ctx) {
2041 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2042 __func__);
2043 return 0;
2044 }
2045
2046 ep_index = xhci_get_endpoint_index(&ep->desc);
2047 /* If this endpoint is already in use, and the upper layers are trying
2048 * to add it again without dropping it, reject the addition.
2049 */
2050 if (virt_dev->eps[ep_index].ring &&
2051 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2052 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2053 "without dropping it.\n",
2054 (unsigned int) ep->desc.bEndpointAddress);
2055 return -EINVAL;
2056 }
2057
2058 /* If the HCD has already noted the endpoint is enabled,
2059 * ignore this request.
2060 */
2061 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2062 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2063 __func__, ep);
2064 return 0;
2065 }
2066
2067 /*
2068 * Configuration and alternate setting changes must be done in
2069 * process context, not interrupt context (or so documenation
2070 * for usb_set_interface() and usb_set_configuration() claim).
2071 */
2072 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2073 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2074 __func__, ep->desc.bEndpointAddress);
2075 return -ENOMEM;
2076 }
2077
2078 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2079 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2080
2081 /* If xhci_endpoint_disable() was called for this endpoint, but the
2082 * xHC hasn't been notified yet through the check_bandwidth() call,
2083 * this re-adds a new state for the endpoint from the new endpoint
2084 * descriptors. We must drop and re-add this endpoint, so we leave the
2085 * drop flags alone.
2086 */
2087 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2088
2089 /* Store the usb_device pointer for later use */
2090 ep->hcpriv = udev;
2091
2092 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2093 trace_xhci_add_endpoint(ep_ctx);
2094
2095 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2096 (unsigned int) ep->desc.bEndpointAddress,
2097 udev->slot_id,
2098 (unsigned int) new_drop_flags,
2099 (unsigned int) new_add_flags);
2100 return 0;
2101}
2102EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2103
2104static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2105{
2106 struct xhci_input_control_ctx *ctrl_ctx;
2107 struct xhci_ep_ctx *ep_ctx;
2108 struct xhci_slot_ctx *slot_ctx;
2109 int i;
2110
2111 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2112 if (!ctrl_ctx) {
2113 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2114 __func__);
2115 return;
2116 }
2117
2118 /* When a device's add flag and drop flag are zero, any subsequent
2119 * configure endpoint command will leave that endpoint's state
2120 * untouched. Make sure we don't leave any old state in the input
2121 * endpoint contexts.
2122 */
2123 ctrl_ctx->drop_flags = 0;
2124 ctrl_ctx->add_flags = 0;
2125 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2126 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2127 /* Endpoint 0 is always valid */
2128 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2129 for (i = 1; i < 31; i++) {
2130 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2131 ep_ctx->ep_info = 0;
2132 ep_ctx->ep_info2 = 0;
2133 ep_ctx->deq = 0;
2134 ep_ctx->tx_info = 0;
2135 }
2136}
2137
2138static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2139 struct usb_device *udev, u32 *cmd_status)
2140{
2141 int ret;
2142
2143 switch (*cmd_status) {
2144 case COMP_COMMAND_ABORTED:
2145 case COMP_COMMAND_RING_STOPPED:
2146 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2147 ret = -ETIME;
2148 break;
2149 case COMP_RESOURCE_ERROR:
2150 dev_warn(&udev->dev,
2151 "Not enough host controller resources for new device state.\n");
2152 ret = -ENOMEM;
2153 /* FIXME: can we allocate more resources for the HC? */
2154 break;
2155 case COMP_BANDWIDTH_ERROR:
2156 case COMP_SECONDARY_BANDWIDTH_ERROR:
2157 dev_warn(&udev->dev,
2158 "Not enough bandwidth for new device state.\n");
2159 ret = -ENOSPC;
2160 /* FIXME: can we go back to the old state? */
2161 break;
2162 case COMP_TRB_ERROR:
2163 /* the HCD set up something wrong */
2164 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2165 "add flag = 1, "
2166 "and endpoint is not disabled.\n");
2167 ret = -EINVAL;
2168 break;
2169 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2170 dev_warn(&udev->dev,
2171 "ERROR: Incompatible device for endpoint configure command.\n");
2172 ret = -ENODEV;
2173 break;
2174 case COMP_SUCCESS:
2175 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2176 "Successful Endpoint Configure command");
2177 ret = 0;
2178 break;
2179 default:
2180 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2181 *cmd_status);
2182 ret = -EINVAL;
2183 break;
2184 }
2185 return ret;
2186}
2187
2188static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2189 struct usb_device *udev, u32 *cmd_status)
2190{
2191 int ret;
2192
2193 switch (*cmd_status) {
2194 case COMP_COMMAND_ABORTED:
2195 case COMP_COMMAND_RING_STOPPED:
2196 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2197 ret = -ETIME;
2198 break;
2199 case COMP_PARAMETER_ERROR:
2200 dev_warn(&udev->dev,
2201 "WARN: xHCI driver setup invalid evaluate context command.\n");
2202 ret = -EINVAL;
2203 break;
2204 case COMP_SLOT_NOT_ENABLED_ERROR:
2205 dev_warn(&udev->dev,
2206 "WARN: slot not enabled for evaluate context command.\n");
2207 ret = -EINVAL;
2208 break;
2209 case COMP_CONTEXT_STATE_ERROR:
2210 dev_warn(&udev->dev,
2211 "WARN: invalid context state for evaluate context command.\n");
2212 ret = -EINVAL;
2213 break;
2214 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2215 dev_warn(&udev->dev,
2216 "ERROR: Incompatible device for evaluate context command.\n");
2217 ret = -ENODEV;
2218 break;
2219 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2220 /* Max Exit Latency too large error */
2221 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2222 ret = -EINVAL;
2223 break;
2224 case COMP_SUCCESS:
2225 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2226 "Successful evaluate context command");
2227 ret = 0;
2228 break;
2229 default:
2230 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2231 *cmd_status);
2232 ret = -EINVAL;
2233 break;
2234 }
2235 return ret;
2236}
2237
2238static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2239 struct xhci_input_control_ctx *ctrl_ctx)
2240{
2241 u32 valid_add_flags;
2242 u32 valid_drop_flags;
2243
2244 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2245 * (bit 1). The default control endpoint is added during the Address
2246 * Device command and is never removed until the slot is disabled.
2247 */
2248 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2249 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2250
2251 /* Use hweight32 to count the number of ones in the add flags, or
2252 * number of endpoints added. Don't count endpoints that are changed
2253 * (both added and dropped).
2254 */
2255 return hweight32(valid_add_flags) -
2256 hweight32(valid_add_flags & valid_drop_flags);
2257}
2258
2259static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2260 struct xhci_input_control_ctx *ctrl_ctx)
2261{
2262 u32 valid_add_flags;
2263 u32 valid_drop_flags;
2264
2265 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2266 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2267
2268 return hweight32(valid_drop_flags) -
2269 hweight32(valid_add_flags & valid_drop_flags);
2270}
2271
2272/*
2273 * We need to reserve the new number of endpoints before the configure endpoint
2274 * command completes. We can't subtract the dropped endpoints from the number
2275 * of active endpoints until the command completes because we can oversubscribe
2276 * the host in this case:
2277 *
2278 * - the first configure endpoint command drops more endpoints than it adds
2279 * - a second configure endpoint command that adds more endpoints is queued
2280 * - the first configure endpoint command fails, so the config is unchanged
2281 * - the second command may succeed, even though there isn't enough resources
2282 *
2283 * Must be called with xhci->lock held.
2284 */
2285static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2286 struct xhci_input_control_ctx *ctrl_ctx)
2287{
2288 u32 added_eps;
2289
2290 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2291 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2292 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2293 "Not enough ep ctxs: "
2294 "%u active, need to add %u, limit is %u.",
2295 xhci->num_active_eps, added_eps,
2296 xhci->limit_active_eps);
2297 return -ENOMEM;
2298 }
2299 xhci->num_active_eps += added_eps;
2300 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2301 "Adding %u ep ctxs, %u now active.", added_eps,
2302 xhci->num_active_eps);
2303 return 0;
2304}
2305
2306/*
2307 * The configure endpoint was failed by the xHC for some other reason, so we
2308 * need to revert the resources that failed configuration would have used.
2309 *
2310 * Must be called with xhci->lock held.
2311 */
2312static void xhci_free_host_resources(struct xhci_hcd *xhci,
2313 struct xhci_input_control_ctx *ctrl_ctx)
2314{
2315 u32 num_failed_eps;
2316
2317 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2318 xhci->num_active_eps -= num_failed_eps;
2319 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2320 "Removing %u failed ep ctxs, %u now active.",
2321 num_failed_eps,
2322 xhci->num_active_eps);
2323}
2324
2325/*
2326 * Now that the command has completed, clean up the active endpoint count by
2327 * subtracting out the endpoints that were dropped (but not changed).
2328 *
2329 * Must be called with xhci->lock held.
2330 */
2331static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2332 struct xhci_input_control_ctx *ctrl_ctx)
2333{
2334 u32 num_dropped_eps;
2335
2336 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2337 xhci->num_active_eps -= num_dropped_eps;
2338 if (num_dropped_eps)
2339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2340 "Removing %u dropped ep ctxs, %u now active.",
2341 num_dropped_eps,
2342 xhci->num_active_eps);
2343}
2344
2345static unsigned int xhci_get_block_size(struct usb_device *udev)
2346{
2347 switch (udev->speed) {
2348 case USB_SPEED_LOW:
2349 case USB_SPEED_FULL:
2350 return FS_BLOCK;
2351 case USB_SPEED_HIGH:
2352 return HS_BLOCK;
2353 case USB_SPEED_SUPER:
2354 case USB_SPEED_SUPER_PLUS:
2355 return SS_BLOCK;
2356 case USB_SPEED_UNKNOWN:
2357 case USB_SPEED_WIRELESS:
2358 default:
2359 /* Should never happen */
2360 return 1;
2361 }
2362}
2363
2364static unsigned int
2365xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2366{
2367 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2368 return LS_OVERHEAD;
2369 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2370 return FS_OVERHEAD;
2371 return HS_OVERHEAD;
2372}
2373
2374/* If we are changing a LS/FS device under a HS hub,
2375 * make sure (if we are activating a new TT) that the HS bus has enough
2376 * bandwidth for this new TT.
2377 */
2378static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2379 struct xhci_virt_device *virt_dev,
2380 int old_active_eps)
2381{
2382 struct xhci_interval_bw_table *bw_table;
2383 struct xhci_tt_bw_info *tt_info;
2384
2385 /* Find the bandwidth table for the root port this TT is attached to. */
2386 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2387 tt_info = virt_dev->tt_info;
2388 /* If this TT already had active endpoints, the bandwidth for this TT
2389 * has already been added. Removing all periodic endpoints (and thus
2390 * making the TT enactive) will only decrease the bandwidth used.
2391 */
2392 if (old_active_eps)
2393 return 0;
2394 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2395 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2396 return -ENOMEM;
2397 return 0;
2398 }
2399 /* Not sure why we would have no new active endpoints...
2400 *
2401 * Maybe because of an Evaluate Context change for a hub update or a
2402 * control endpoint 0 max packet size change?
2403 * FIXME: skip the bandwidth calculation in that case.
2404 */
2405 return 0;
2406}
2407
2408static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2409 struct xhci_virt_device *virt_dev)
2410{
2411 unsigned int bw_reserved;
2412
2413 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2414 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2415 return -ENOMEM;
2416
2417 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2418 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2419 return -ENOMEM;
2420
2421 return 0;
2422}
2423
2424/*
2425 * This algorithm is a very conservative estimate of the worst-case scheduling
2426 * scenario for any one interval. The hardware dynamically schedules the
2427 * packets, so we can't tell which microframe could be the limiting factor in
2428 * the bandwidth scheduling. This only takes into account periodic endpoints.
2429 *
2430 * Obviously, we can't solve an NP complete problem to find the minimum worst
2431 * case scenario. Instead, we come up with an estimate that is no less than
2432 * the worst case bandwidth used for any one microframe, but may be an
2433 * over-estimate.
2434 *
2435 * We walk the requirements for each endpoint by interval, starting with the
2436 * smallest interval, and place packets in the schedule where there is only one
2437 * possible way to schedule packets for that interval. In order to simplify
2438 * this algorithm, we record the largest max packet size for each interval, and
2439 * assume all packets will be that size.
2440 *
2441 * For interval 0, we obviously must schedule all packets for each interval.
2442 * The bandwidth for interval 0 is just the amount of data to be transmitted
2443 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2444 * the number of packets).
2445 *
2446 * For interval 1, we have two possible microframes to schedule those packets
2447 * in. For this algorithm, if we can schedule the same number of packets for
2448 * each possible scheduling opportunity (each microframe), we will do so. The
2449 * remaining number of packets will be saved to be transmitted in the gaps in
2450 * the next interval's scheduling sequence.
2451 *
2452 * As we move those remaining packets to be scheduled with interval 2 packets,
2453 * we have to double the number of remaining packets to transmit. This is
2454 * because the intervals are actually powers of 2, and we would be transmitting
2455 * the previous interval's packets twice in this interval. We also have to be
2456 * sure that when we look at the largest max packet size for this interval, we
2457 * also look at the largest max packet size for the remaining packets and take
2458 * the greater of the two.
2459 *
2460 * The algorithm continues to evenly distribute packets in each scheduling
2461 * opportunity, and push the remaining packets out, until we get to the last
2462 * interval. Then those packets and their associated overhead are just added
2463 * to the bandwidth used.
2464 */
2465static int xhci_check_bw_table(struct xhci_hcd *xhci,
2466 struct xhci_virt_device *virt_dev,
2467 int old_active_eps)
2468{
2469 unsigned int bw_reserved;
2470 unsigned int max_bandwidth;
2471 unsigned int bw_used;
2472 unsigned int block_size;
2473 struct xhci_interval_bw_table *bw_table;
2474 unsigned int packet_size = 0;
2475 unsigned int overhead = 0;
2476 unsigned int packets_transmitted = 0;
2477 unsigned int packets_remaining = 0;
2478 unsigned int i;
2479
2480 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2481 return xhci_check_ss_bw(xhci, virt_dev);
2482
2483 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2484 max_bandwidth = HS_BW_LIMIT;
2485 /* Convert percent of bus BW reserved to blocks reserved */
2486 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2487 } else {
2488 max_bandwidth = FS_BW_LIMIT;
2489 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2490 }
2491
2492 bw_table = virt_dev->bw_table;
2493 /* We need to translate the max packet size and max ESIT payloads into
2494 * the units the hardware uses.
2495 */
2496 block_size = xhci_get_block_size(virt_dev->udev);
2497
2498 /* If we are manipulating a LS/FS device under a HS hub, double check
2499 * that the HS bus has enough bandwidth if we are activing a new TT.
2500 */
2501 if (virt_dev->tt_info) {
2502 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2503 "Recalculating BW for rootport %u",
2504 virt_dev->real_port);
2505 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2506 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2507 "newly activated TT.\n");
2508 return -ENOMEM;
2509 }
2510 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2511 "Recalculating BW for TT slot %u port %u",
2512 virt_dev->tt_info->slot_id,
2513 virt_dev->tt_info->ttport);
2514 } else {
2515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2516 "Recalculating BW for rootport %u",
2517 virt_dev->real_port);
2518 }
2519
2520 /* Add in how much bandwidth will be used for interval zero, or the
2521 * rounded max ESIT payload + number of packets * largest overhead.
2522 */
2523 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2524 bw_table->interval_bw[0].num_packets *
2525 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2526
2527 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2528 unsigned int bw_added;
2529 unsigned int largest_mps;
2530 unsigned int interval_overhead;
2531
2532 /*
2533 * How many packets could we transmit in this interval?
2534 * If packets didn't fit in the previous interval, we will need
2535 * to transmit that many packets twice within this interval.
2536 */
2537 packets_remaining = 2 * packets_remaining +
2538 bw_table->interval_bw[i].num_packets;
2539
2540 /* Find the largest max packet size of this or the previous
2541 * interval.
2542 */
2543 if (list_empty(&bw_table->interval_bw[i].endpoints))
2544 largest_mps = 0;
2545 else {
2546 struct xhci_virt_ep *virt_ep;
2547 struct list_head *ep_entry;
2548
2549 ep_entry = bw_table->interval_bw[i].endpoints.next;
2550 virt_ep = list_entry(ep_entry,
2551 struct xhci_virt_ep, bw_endpoint_list);
2552 /* Convert to blocks, rounding up */
2553 largest_mps = DIV_ROUND_UP(
2554 virt_ep->bw_info.max_packet_size,
2555 block_size);
2556 }
2557 if (largest_mps > packet_size)
2558 packet_size = largest_mps;
2559
2560 /* Use the larger overhead of this or the previous interval. */
2561 interval_overhead = xhci_get_largest_overhead(
2562 &bw_table->interval_bw[i]);
2563 if (interval_overhead > overhead)
2564 overhead = interval_overhead;
2565
2566 /* How many packets can we evenly distribute across
2567 * (1 << (i + 1)) possible scheduling opportunities?
2568 */
2569 packets_transmitted = packets_remaining >> (i + 1);
2570
2571 /* Add in the bandwidth used for those scheduled packets */
2572 bw_added = packets_transmitted * (overhead + packet_size);
2573
2574 /* How many packets do we have remaining to transmit? */
2575 packets_remaining = packets_remaining % (1 << (i + 1));
2576
2577 /* What largest max packet size should those packets have? */
2578 /* If we've transmitted all packets, don't carry over the
2579 * largest packet size.
2580 */
2581 if (packets_remaining == 0) {
2582 packet_size = 0;
2583 overhead = 0;
2584 } else if (packets_transmitted > 0) {
2585 /* Otherwise if we do have remaining packets, and we've
2586 * scheduled some packets in this interval, take the
2587 * largest max packet size from endpoints with this
2588 * interval.
2589 */
2590 packet_size = largest_mps;
2591 overhead = interval_overhead;
2592 }
2593 /* Otherwise carry over packet_size and overhead from the last
2594 * time we had a remainder.
2595 */
2596 bw_used += bw_added;
2597 if (bw_used > max_bandwidth) {
2598 xhci_warn(xhci, "Not enough bandwidth. "
2599 "Proposed: %u, Max: %u\n",
2600 bw_used, max_bandwidth);
2601 return -ENOMEM;
2602 }
2603 }
2604 /*
2605 * Ok, we know we have some packets left over after even-handedly
2606 * scheduling interval 15. We don't know which microframes they will
2607 * fit into, so we over-schedule and say they will be scheduled every
2608 * microframe.
2609 */
2610 if (packets_remaining > 0)
2611 bw_used += overhead + packet_size;
2612
2613 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2614 unsigned int port_index = virt_dev->real_port - 1;
2615
2616 /* OK, we're manipulating a HS device attached to a
2617 * root port bandwidth domain. Include the number of active TTs
2618 * in the bandwidth used.
2619 */
2620 bw_used += TT_HS_OVERHEAD *
2621 xhci->rh_bw[port_index].num_active_tts;
2622 }
2623
2624 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2625 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2626 "Available: %u " "percent",
2627 bw_used, max_bandwidth, bw_reserved,
2628 (max_bandwidth - bw_used - bw_reserved) * 100 /
2629 max_bandwidth);
2630
2631 bw_used += bw_reserved;
2632 if (bw_used > max_bandwidth) {
2633 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2634 bw_used, max_bandwidth);
2635 return -ENOMEM;
2636 }
2637
2638 bw_table->bw_used = bw_used;
2639 return 0;
2640}
2641
2642static bool xhci_is_async_ep(unsigned int ep_type)
2643{
2644 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2645 ep_type != ISOC_IN_EP &&
2646 ep_type != INT_IN_EP);
2647}
2648
2649static bool xhci_is_sync_in_ep(unsigned int ep_type)
2650{
2651 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2652}
2653
2654static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2655{
2656 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2657
2658 if (ep_bw->ep_interval == 0)
2659 return SS_OVERHEAD_BURST +
2660 (ep_bw->mult * ep_bw->num_packets *
2661 (SS_OVERHEAD + mps));
2662 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2663 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2664 1 << ep_bw->ep_interval);
2665
2666}
2667
2668static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2669 struct xhci_bw_info *ep_bw,
2670 struct xhci_interval_bw_table *bw_table,
2671 struct usb_device *udev,
2672 struct xhci_virt_ep *virt_ep,
2673 struct xhci_tt_bw_info *tt_info)
2674{
2675 struct xhci_interval_bw *interval_bw;
2676 int normalized_interval;
2677
2678 if (xhci_is_async_ep(ep_bw->type))
2679 return;
2680
2681 if (udev->speed >= USB_SPEED_SUPER) {
2682 if (xhci_is_sync_in_ep(ep_bw->type))
2683 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2684 xhci_get_ss_bw_consumed(ep_bw);
2685 else
2686 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2687 xhci_get_ss_bw_consumed(ep_bw);
2688 return;
2689 }
2690
2691 /* SuperSpeed endpoints never get added to intervals in the table, so
2692 * this check is only valid for HS/FS/LS devices.
2693 */
2694 if (list_empty(&virt_ep->bw_endpoint_list))
2695 return;
2696 /* For LS/FS devices, we need to translate the interval expressed in
2697 * microframes to frames.
2698 */
2699 if (udev->speed == USB_SPEED_HIGH)
2700 normalized_interval = ep_bw->ep_interval;
2701 else
2702 normalized_interval = ep_bw->ep_interval - 3;
2703
2704 if (normalized_interval == 0)
2705 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2706 interval_bw = &bw_table->interval_bw[normalized_interval];
2707 interval_bw->num_packets -= ep_bw->num_packets;
2708 switch (udev->speed) {
2709 case USB_SPEED_LOW:
2710 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2711 break;
2712 case USB_SPEED_FULL:
2713 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2714 break;
2715 case USB_SPEED_HIGH:
2716 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2717 break;
2718 case USB_SPEED_SUPER:
2719 case USB_SPEED_SUPER_PLUS:
2720 case USB_SPEED_UNKNOWN:
2721 case USB_SPEED_WIRELESS:
2722 /* Should never happen because only LS/FS/HS endpoints will get
2723 * added to the endpoint list.
2724 */
2725 return;
2726 }
2727 if (tt_info)
2728 tt_info->active_eps -= 1;
2729 list_del_init(&virt_ep->bw_endpoint_list);
2730}
2731
2732static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2733 struct xhci_bw_info *ep_bw,
2734 struct xhci_interval_bw_table *bw_table,
2735 struct usb_device *udev,
2736 struct xhci_virt_ep *virt_ep,
2737 struct xhci_tt_bw_info *tt_info)
2738{
2739 struct xhci_interval_bw *interval_bw;
2740 struct xhci_virt_ep *smaller_ep;
2741 int normalized_interval;
2742
2743 if (xhci_is_async_ep(ep_bw->type))
2744 return;
2745
2746 if (udev->speed == USB_SPEED_SUPER) {
2747 if (xhci_is_sync_in_ep(ep_bw->type))
2748 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2749 xhci_get_ss_bw_consumed(ep_bw);
2750 else
2751 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2752 xhci_get_ss_bw_consumed(ep_bw);
2753 return;
2754 }
2755
2756 /* For LS/FS devices, we need to translate the interval expressed in
2757 * microframes to frames.
2758 */
2759 if (udev->speed == USB_SPEED_HIGH)
2760 normalized_interval = ep_bw->ep_interval;
2761 else
2762 normalized_interval = ep_bw->ep_interval - 3;
2763
2764 if (normalized_interval == 0)
2765 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2766 interval_bw = &bw_table->interval_bw[normalized_interval];
2767 interval_bw->num_packets += ep_bw->num_packets;
2768 switch (udev->speed) {
2769 case USB_SPEED_LOW:
2770 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2771 break;
2772 case USB_SPEED_FULL:
2773 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2774 break;
2775 case USB_SPEED_HIGH:
2776 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2777 break;
2778 case USB_SPEED_SUPER:
2779 case USB_SPEED_SUPER_PLUS:
2780 case USB_SPEED_UNKNOWN:
2781 case USB_SPEED_WIRELESS:
2782 /* Should never happen because only LS/FS/HS endpoints will get
2783 * added to the endpoint list.
2784 */
2785 return;
2786 }
2787
2788 if (tt_info)
2789 tt_info->active_eps += 1;
2790 /* Insert the endpoint into the list, largest max packet size first. */
2791 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2792 bw_endpoint_list) {
2793 if (ep_bw->max_packet_size >=
2794 smaller_ep->bw_info.max_packet_size) {
2795 /* Add the new ep before the smaller endpoint */
2796 list_add_tail(&virt_ep->bw_endpoint_list,
2797 &smaller_ep->bw_endpoint_list);
2798 return;
2799 }
2800 }
2801 /* Add the new endpoint at the end of the list. */
2802 list_add_tail(&virt_ep->bw_endpoint_list,
2803 &interval_bw->endpoints);
2804}
2805
2806void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2807 struct xhci_virt_device *virt_dev,
2808 int old_active_eps)
2809{
2810 struct xhci_root_port_bw_info *rh_bw_info;
2811 if (!virt_dev->tt_info)
2812 return;
2813
2814 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2815 if (old_active_eps == 0 &&
2816 virt_dev->tt_info->active_eps != 0) {
2817 rh_bw_info->num_active_tts += 1;
2818 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2819 } else if (old_active_eps != 0 &&
2820 virt_dev->tt_info->active_eps == 0) {
2821 rh_bw_info->num_active_tts -= 1;
2822 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2823 }
2824}
2825
2826static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2827 struct xhci_virt_device *virt_dev,
2828 struct xhci_container_ctx *in_ctx)
2829{
2830 struct xhci_bw_info ep_bw_info[31];
2831 int i;
2832 struct xhci_input_control_ctx *ctrl_ctx;
2833 int old_active_eps = 0;
2834
2835 if (virt_dev->tt_info)
2836 old_active_eps = virt_dev->tt_info->active_eps;
2837
2838 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2839 if (!ctrl_ctx) {
2840 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2841 __func__);
2842 return -ENOMEM;
2843 }
2844
2845 for (i = 0; i < 31; i++) {
2846 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2847 continue;
2848
2849 /* Make a copy of the BW info in case we need to revert this */
2850 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2851 sizeof(ep_bw_info[i]));
2852 /* Drop the endpoint from the interval table if the endpoint is
2853 * being dropped or changed.
2854 */
2855 if (EP_IS_DROPPED(ctrl_ctx, i))
2856 xhci_drop_ep_from_interval_table(xhci,
2857 &virt_dev->eps[i].bw_info,
2858 virt_dev->bw_table,
2859 virt_dev->udev,
2860 &virt_dev->eps[i],
2861 virt_dev->tt_info);
2862 }
2863 /* Overwrite the information stored in the endpoints' bw_info */
2864 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2865 for (i = 0; i < 31; i++) {
2866 /* Add any changed or added endpoints to the interval table */
2867 if (EP_IS_ADDED(ctrl_ctx, i))
2868 xhci_add_ep_to_interval_table(xhci,
2869 &virt_dev->eps[i].bw_info,
2870 virt_dev->bw_table,
2871 virt_dev->udev,
2872 &virt_dev->eps[i],
2873 virt_dev->tt_info);
2874 }
2875
2876 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2877 /* Ok, this fits in the bandwidth we have.
2878 * Update the number of active TTs.
2879 */
2880 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2881 return 0;
2882 }
2883
2884 /* We don't have enough bandwidth for this, revert the stored info. */
2885 for (i = 0; i < 31; i++) {
2886 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2887 continue;
2888
2889 /* Drop the new copies of any added or changed endpoints from
2890 * the interval table.
2891 */
2892 if (EP_IS_ADDED(ctrl_ctx, i)) {
2893 xhci_drop_ep_from_interval_table(xhci,
2894 &virt_dev->eps[i].bw_info,
2895 virt_dev->bw_table,
2896 virt_dev->udev,
2897 &virt_dev->eps[i],
2898 virt_dev->tt_info);
2899 }
2900 /* Revert the endpoint back to its old information */
2901 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2902 sizeof(ep_bw_info[i]));
2903 /* Add any changed or dropped endpoints back into the table */
2904 if (EP_IS_DROPPED(ctrl_ctx, i))
2905 xhci_add_ep_to_interval_table(xhci,
2906 &virt_dev->eps[i].bw_info,
2907 virt_dev->bw_table,
2908 virt_dev->udev,
2909 &virt_dev->eps[i],
2910 virt_dev->tt_info);
2911 }
2912 return -ENOMEM;
2913}
2914
2915
2916/* Issue a configure endpoint command or evaluate context command
2917 * and wait for it to finish.
2918 */
2919static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2920 struct usb_device *udev,
2921 struct xhci_command *command,
2922 bool ctx_change, bool must_succeed)
2923{
2924 int ret;
2925 unsigned long flags;
2926 struct xhci_input_control_ctx *ctrl_ctx;
2927 struct xhci_virt_device *virt_dev;
2928 struct xhci_slot_ctx *slot_ctx;
2929
2930 if (!command)
2931 return -EINVAL;
2932
2933 spin_lock_irqsave(&xhci->lock, flags);
2934
2935 if (xhci->xhc_state & XHCI_STATE_DYING) {
2936 spin_unlock_irqrestore(&xhci->lock, flags);
2937 return -ESHUTDOWN;
2938 }
2939
2940 virt_dev = xhci->devs[udev->slot_id];
2941
2942 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2943 if (!ctrl_ctx) {
2944 spin_unlock_irqrestore(&xhci->lock, flags);
2945 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2946 __func__);
2947 return -ENOMEM;
2948 }
2949
2950 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2951 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2952 spin_unlock_irqrestore(&xhci->lock, flags);
2953 xhci_warn(xhci, "Not enough host resources, "
2954 "active endpoint contexts = %u\n",
2955 xhci->num_active_eps);
2956 return -ENOMEM;
2957 }
2958 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2959 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2960 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2961 xhci_free_host_resources(xhci, ctrl_ctx);
2962 spin_unlock_irqrestore(&xhci->lock, flags);
2963 xhci_warn(xhci, "Not enough bandwidth\n");
2964 return -ENOMEM;
2965 }
2966
2967 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2968
2969 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2970 trace_xhci_configure_endpoint(slot_ctx);
2971
2972 if (!ctx_change)
2973 ret = xhci_queue_configure_endpoint(xhci, command,
2974 command->in_ctx->dma,
2975 udev->slot_id, must_succeed);
2976 else
2977 ret = xhci_queue_evaluate_context(xhci, command,
2978 command->in_ctx->dma,
2979 udev->slot_id, must_succeed);
2980 if (ret < 0) {
2981 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2982 xhci_free_host_resources(xhci, ctrl_ctx);
2983 spin_unlock_irqrestore(&xhci->lock, flags);
2984 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2985 "FIXME allocate a new ring segment");
2986 return -ENOMEM;
2987 }
2988 xhci_ring_cmd_db(xhci);
2989 spin_unlock_irqrestore(&xhci->lock, flags);
2990
2991 /* Wait for the configure endpoint command to complete */
2992 wait_for_completion(command->completion);
2993
2994 if (!ctx_change)
2995 ret = xhci_configure_endpoint_result(xhci, udev,
2996 &command->status);
2997 else
2998 ret = xhci_evaluate_context_result(xhci, udev,
2999 &command->status);
3000
3001 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3002 spin_lock_irqsave(&xhci->lock, flags);
3003 /* If the command failed, remove the reserved resources.
3004 * Otherwise, clean up the estimate to include dropped eps.
3005 */
3006 if (ret)
3007 xhci_free_host_resources(xhci, ctrl_ctx);
3008 else
3009 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3010 spin_unlock_irqrestore(&xhci->lock, flags);
3011 }
3012 return ret;
3013}
3014
3015static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3016 struct xhci_virt_device *vdev, int i)
3017{
3018 struct xhci_virt_ep *ep = &vdev->eps[i];
3019
3020 if (ep->ep_state & EP_HAS_STREAMS) {
3021 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3022 xhci_get_endpoint_address(i));
3023 xhci_free_stream_info(xhci, ep->stream_info);
3024 ep->stream_info = NULL;
3025 ep->ep_state &= ~EP_HAS_STREAMS;
3026 }
3027}
3028
3029/* Called after one or more calls to xhci_add_endpoint() or
3030 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3031 * to call xhci_reset_bandwidth().
3032 *
3033 * Since we are in the middle of changing either configuration or
3034 * installing a new alt setting, the USB core won't allow URBs to be
3035 * enqueued for any endpoint on the old config or interface. Nothing
3036 * else should be touching the xhci->devs[slot_id] structure, so we
3037 * don't need to take the xhci->lock for manipulating that.
3038 */
3039int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3040{
3041 int i;
3042 int ret = 0;
3043 struct xhci_hcd *xhci;
3044 struct xhci_virt_device *virt_dev;
3045 struct xhci_input_control_ctx *ctrl_ctx;
3046 struct xhci_slot_ctx *slot_ctx;
3047 struct xhci_command *command;
3048
3049 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3050 if (ret <= 0)
3051 return ret;
3052 xhci = hcd_to_xhci(hcd);
3053 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3054 (xhci->xhc_state & XHCI_STATE_REMOVING))
3055 return -ENODEV;
3056
3057 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3058 virt_dev = xhci->devs[udev->slot_id];
3059
3060 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3061 if (!command)
3062 return -ENOMEM;
3063
3064 command->in_ctx = virt_dev->in_ctx;
3065
3066 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3067 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3068 if (!ctrl_ctx) {
3069 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3070 __func__);
3071 ret = -ENOMEM;
3072 goto command_cleanup;
3073 }
3074 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3075 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3076 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3077
3078 /* Don't issue the command if there's no endpoints to update. */
3079 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3080 ctrl_ctx->drop_flags == 0) {
3081 ret = 0;
3082 goto command_cleanup;
3083 }
3084 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3085 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3086 for (i = 31; i >= 1; i--) {
3087 __le32 le32 = cpu_to_le32(BIT(i));
3088
3089 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3090 || (ctrl_ctx->add_flags & le32) || i == 1) {
3091 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3092 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3093 break;
3094 }
3095 }
3096
3097 ret = xhci_configure_endpoint(xhci, udev, command,
3098 false, false);
3099 if (ret)
3100 /* Callee should call reset_bandwidth() */
3101 goto command_cleanup;
3102
3103 /* Free any rings that were dropped, but not changed. */
3104 for (i = 1; i < 31; i++) {
3105 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3106 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3107 xhci_free_endpoint_ring(xhci, virt_dev, i);
3108 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3109 }
3110 }
3111 xhci_zero_in_ctx(xhci, virt_dev);
3112 /*
3113 * Install any rings for completely new endpoints or changed endpoints,
3114 * and free any old rings from changed endpoints.
3115 */
3116 for (i = 1; i < 31; i++) {
3117 if (!virt_dev->eps[i].new_ring)
3118 continue;
3119 /* Only free the old ring if it exists.
3120 * It may not if this is the first add of an endpoint.
3121 */
3122 if (virt_dev->eps[i].ring) {
3123 xhci_free_endpoint_ring(xhci, virt_dev, i);
3124 }
3125 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3126 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3127 virt_dev->eps[i].new_ring = NULL;
3128 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3129 }
3130command_cleanup:
3131 kfree(command->completion);
3132 kfree(command);
3133
3134 return ret;
3135}
3136EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3137
3138void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3139{
3140 struct xhci_hcd *xhci;
3141 struct xhci_virt_device *virt_dev;
3142 int i, ret;
3143
3144 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3145 if (ret <= 0)
3146 return;
3147 xhci = hcd_to_xhci(hcd);
3148
3149 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3150 virt_dev = xhci->devs[udev->slot_id];
3151 /* Free any rings allocated for added endpoints */
3152 for (i = 0; i < 31; i++) {
3153 if (virt_dev->eps[i].new_ring) {
3154 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3155 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3156 virt_dev->eps[i].new_ring = NULL;
3157 }
3158 }
3159 xhci_zero_in_ctx(xhci, virt_dev);
3160}
3161EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3162
3163static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3164 struct xhci_container_ctx *in_ctx,
3165 struct xhci_container_ctx *out_ctx,
3166 struct xhci_input_control_ctx *ctrl_ctx,
3167 u32 add_flags, u32 drop_flags)
3168{
3169 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3170 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3171 xhci_slot_copy(xhci, in_ctx, out_ctx);
3172 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3173}
3174
3175static void xhci_endpoint_disable(struct usb_hcd *hcd,
3176 struct usb_host_endpoint *host_ep)
3177{
3178 struct xhci_hcd *xhci;
3179 struct xhci_virt_device *vdev;
3180 struct xhci_virt_ep *ep;
3181 struct usb_device *udev;
3182 unsigned long flags;
3183 unsigned int ep_index;
3184
3185 xhci = hcd_to_xhci(hcd);
3186rescan:
3187 spin_lock_irqsave(&xhci->lock, flags);
3188
3189 udev = (struct usb_device *)host_ep->hcpriv;
3190 if (!udev || !udev->slot_id)
3191 goto done;
3192
3193 vdev = xhci->devs[udev->slot_id];
3194 if (!vdev)
3195 goto done;
3196
3197 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3198 ep = &vdev->eps[ep_index];
3199
3200 /* wait for hub_tt_work to finish clearing hub TT */
3201 if (ep->ep_state & EP_CLEARING_TT) {
3202 spin_unlock_irqrestore(&xhci->lock, flags);
3203 schedule_timeout_uninterruptible(1);
3204 goto rescan;
3205 }
3206
3207 if (ep->ep_state)
3208 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3209 ep->ep_state);
3210done:
3211 host_ep->hcpriv = NULL;
3212 spin_unlock_irqrestore(&xhci->lock, flags);
3213}
3214
3215/*
3216 * Called after usb core issues a clear halt control message.
3217 * The host side of the halt should already be cleared by a reset endpoint
3218 * command issued when the STALL event was received.
3219 *
3220 * The reset endpoint command may only be issued to endpoints in the halted
3221 * state. For software that wishes to reset the data toggle or sequence number
3222 * of an endpoint that isn't in the halted state this function will issue a
3223 * configure endpoint command with the Drop and Add bits set for the target
3224 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3225 */
3226
3227static void xhci_endpoint_reset(struct usb_hcd *hcd,
3228 struct usb_host_endpoint *host_ep)
3229{
3230 struct xhci_hcd *xhci;
3231 struct usb_device *udev;
3232 struct xhci_virt_device *vdev;
3233 struct xhci_virt_ep *ep;
3234 struct xhci_input_control_ctx *ctrl_ctx;
3235 struct xhci_command *stop_cmd, *cfg_cmd;
3236 unsigned int ep_index;
3237 unsigned long flags;
3238 u32 ep_flag;
3239 int err;
3240
3241 xhci = hcd_to_xhci(hcd);
3242 if (!host_ep->hcpriv)
3243 return;
3244 udev = (struct usb_device *) host_ep->hcpriv;
3245 vdev = xhci->devs[udev->slot_id];
3246
3247 /*
3248 * vdev may be lost due to xHC restore error and re-initialization
3249 * during S3/S4 resume. A new vdev will be allocated later by
3250 * xhci_discover_or_reset_device()
3251 */
3252 if (!udev->slot_id || !vdev)
3253 return;
3254 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3255 ep = &vdev->eps[ep_index];
3256
3257 /* Bail out if toggle is already being cleared by a endpoint reset */
3258 spin_lock_irqsave(&xhci->lock, flags);
3259 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3260 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3261 spin_unlock_irqrestore(&xhci->lock, flags);
3262 return;
3263 }
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3265 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3266 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3267 usb_endpoint_xfer_isoc(&host_ep->desc))
3268 return;
3269
3270 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3271
3272 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3273 return;
3274
3275 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3276 if (!stop_cmd)
3277 return;
3278
3279 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3280 if (!cfg_cmd)
3281 goto cleanup;
3282
3283 spin_lock_irqsave(&xhci->lock, flags);
3284
3285 /* block queuing new trbs and ringing ep doorbell */
3286 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3287
3288 /*
3289 * Make sure endpoint ring is empty before resetting the toggle/seq.
3290 * Driver is required to synchronously cancel all transfer request.
3291 * Stop the endpoint to force xHC to update the output context
3292 */
3293
3294 if (!list_empty(&ep->ring->td_list)) {
3295 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3296 spin_unlock_irqrestore(&xhci->lock, flags);
3297 xhci_free_command(xhci, cfg_cmd);
3298 goto cleanup;
3299 }
3300
3301 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3302 ep_index, 0);
3303 if (err < 0) {
3304 spin_unlock_irqrestore(&xhci->lock, flags);
3305 xhci_free_command(xhci, cfg_cmd);
3306 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3307 __func__, err);
3308 goto cleanup;
3309 }
3310
3311 xhci_ring_cmd_db(xhci);
3312 spin_unlock_irqrestore(&xhci->lock, flags);
3313
3314 wait_for_completion(stop_cmd->completion);
3315
3316 spin_lock_irqsave(&xhci->lock, flags);
3317
3318 /* config ep command clears toggle if add and drop ep flags are set */
3319 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3320 if (!ctrl_ctx) {
3321 spin_unlock_irqrestore(&xhci->lock, flags);
3322 xhci_free_command(xhci, cfg_cmd);
3323 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3324 __func__);
3325 goto cleanup;
3326 }
3327
3328 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3329 ctrl_ctx, ep_flag, ep_flag);
3330 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3331
3332 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3333 udev->slot_id, false);
3334 if (err < 0) {
3335 spin_unlock_irqrestore(&xhci->lock, flags);
3336 xhci_free_command(xhci, cfg_cmd);
3337 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3338 __func__, err);
3339 goto cleanup;
3340 }
3341
3342 xhci_ring_cmd_db(xhci);
3343 spin_unlock_irqrestore(&xhci->lock, flags);
3344
3345 wait_for_completion(cfg_cmd->completion);
3346
3347 xhci_free_command(xhci, cfg_cmd);
3348cleanup:
3349 xhci_free_command(xhci, stop_cmd);
3350 spin_lock_irqsave(&xhci->lock, flags);
3351 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3352 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3353 spin_unlock_irqrestore(&xhci->lock, flags);
3354}
3355
3356static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3357 struct usb_device *udev, struct usb_host_endpoint *ep,
3358 unsigned int slot_id)
3359{
3360 int ret;
3361 unsigned int ep_index;
3362 unsigned int ep_state;
3363
3364 if (!ep)
3365 return -EINVAL;
3366 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3367 if (ret <= 0)
3368 return ret ? ret : -EINVAL;
3369 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3370 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3371 " descriptor for ep 0x%x does not support streams\n",
3372 ep->desc.bEndpointAddress);
3373 return -EINVAL;
3374 }
3375
3376 ep_index = xhci_get_endpoint_index(&ep->desc);
3377 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3378 if (ep_state & EP_HAS_STREAMS ||
3379 ep_state & EP_GETTING_STREAMS) {
3380 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3381 "already has streams set up.\n",
3382 ep->desc.bEndpointAddress);
3383 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3384 "dynamic stream context array reallocation.\n");
3385 return -EINVAL;
3386 }
3387 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3388 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3389 "endpoint 0x%x; URBs are pending.\n",
3390 ep->desc.bEndpointAddress);
3391 return -EINVAL;
3392 }
3393 return 0;
3394}
3395
3396static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3397 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3398{
3399 unsigned int max_streams;
3400
3401 /* The stream context array size must be a power of two */
3402 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3403 /*
3404 * Find out how many primary stream array entries the host controller
3405 * supports. Later we may use secondary stream arrays (similar to 2nd
3406 * level page entries), but that's an optional feature for xHCI host
3407 * controllers. xHCs must support at least 4 stream IDs.
3408 */
3409 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3410 if (*num_stream_ctxs > max_streams) {
3411 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3412 max_streams);
3413 *num_stream_ctxs = max_streams;
3414 *num_streams = max_streams;
3415 }
3416}
3417
3418/* Returns an error code if one of the endpoint already has streams.
3419 * This does not change any data structures, it only checks and gathers
3420 * information.
3421 */
3422static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3423 struct usb_device *udev,
3424 struct usb_host_endpoint **eps, unsigned int num_eps,
3425 unsigned int *num_streams, u32 *changed_ep_bitmask)
3426{
3427 unsigned int max_streams;
3428 unsigned int endpoint_flag;
3429 int i;
3430 int ret;
3431
3432 for (i = 0; i < num_eps; i++) {
3433 ret = xhci_check_streams_endpoint(xhci, udev,
3434 eps[i], udev->slot_id);
3435 if (ret < 0)
3436 return ret;
3437
3438 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3439 if (max_streams < (*num_streams - 1)) {
3440 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3441 eps[i]->desc.bEndpointAddress,
3442 max_streams);
3443 *num_streams = max_streams+1;
3444 }
3445
3446 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3447 if (*changed_ep_bitmask & endpoint_flag)
3448 return -EINVAL;
3449 *changed_ep_bitmask |= endpoint_flag;
3450 }
3451 return 0;
3452}
3453
3454static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3455 struct usb_device *udev,
3456 struct usb_host_endpoint **eps, unsigned int num_eps)
3457{
3458 u32 changed_ep_bitmask = 0;
3459 unsigned int slot_id;
3460 unsigned int ep_index;
3461 unsigned int ep_state;
3462 int i;
3463
3464 slot_id = udev->slot_id;
3465 if (!xhci->devs[slot_id])
3466 return 0;
3467
3468 for (i = 0; i < num_eps; i++) {
3469 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3470 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3471 /* Are streams already being freed for the endpoint? */
3472 if (ep_state & EP_GETTING_NO_STREAMS) {
3473 xhci_warn(xhci, "WARN Can't disable streams for "
3474 "endpoint 0x%x, "
3475 "streams are being disabled already\n",
3476 eps[i]->desc.bEndpointAddress);
3477 return 0;
3478 }
3479 /* Are there actually any streams to free? */
3480 if (!(ep_state & EP_HAS_STREAMS) &&
3481 !(ep_state & EP_GETTING_STREAMS)) {
3482 xhci_warn(xhci, "WARN Can't disable streams for "
3483 "endpoint 0x%x, "
3484 "streams are already disabled!\n",
3485 eps[i]->desc.bEndpointAddress);
3486 xhci_warn(xhci, "WARN xhci_free_streams() called "
3487 "with non-streams endpoint\n");
3488 return 0;
3489 }
3490 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3491 }
3492 return changed_ep_bitmask;
3493}
3494
3495/*
3496 * The USB device drivers use this function (through the HCD interface in USB
3497 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3498 * coordinate mass storage command queueing across multiple endpoints (basically
3499 * a stream ID == a task ID).
3500 *
3501 * Setting up streams involves allocating the same size stream context array
3502 * for each endpoint and issuing a configure endpoint command for all endpoints.
3503 *
3504 * Don't allow the call to succeed if one endpoint only supports one stream
3505 * (which means it doesn't support streams at all).
3506 *
3507 * Drivers may get less stream IDs than they asked for, if the host controller
3508 * hardware or endpoints claim they can't support the number of requested
3509 * stream IDs.
3510 */
3511static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3512 struct usb_host_endpoint **eps, unsigned int num_eps,
3513 unsigned int num_streams, gfp_t mem_flags)
3514{
3515 int i, ret;
3516 struct xhci_hcd *xhci;
3517 struct xhci_virt_device *vdev;
3518 struct xhci_command *config_cmd;
3519 struct xhci_input_control_ctx *ctrl_ctx;
3520 unsigned int ep_index;
3521 unsigned int num_stream_ctxs;
3522 unsigned int max_packet;
3523 unsigned long flags;
3524 u32 changed_ep_bitmask = 0;
3525
3526 if (!eps)
3527 return -EINVAL;
3528
3529 /* Add one to the number of streams requested to account for
3530 * stream 0 that is reserved for xHCI usage.
3531 */
3532 num_streams += 1;
3533 xhci = hcd_to_xhci(hcd);
3534 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3535 num_streams);
3536
3537 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3538 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3539 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3540 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3541 return -ENOSYS;
3542 }
3543
3544 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3545 if (!config_cmd)
3546 return -ENOMEM;
3547
3548 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3549 if (!ctrl_ctx) {
3550 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3551 __func__);
3552 xhci_free_command(xhci, config_cmd);
3553 return -ENOMEM;
3554 }
3555
3556 /* Check to make sure all endpoints are not already configured for
3557 * streams. While we're at it, find the maximum number of streams that
3558 * all the endpoints will support and check for duplicate endpoints.
3559 */
3560 spin_lock_irqsave(&xhci->lock, flags);
3561 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3562 num_eps, &num_streams, &changed_ep_bitmask);
3563 if (ret < 0) {
3564 xhci_free_command(xhci, config_cmd);
3565 spin_unlock_irqrestore(&xhci->lock, flags);
3566 return ret;
3567 }
3568 if (num_streams <= 1) {
3569 xhci_warn(xhci, "WARN: endpoints can't handle "
3570 "more than one stream.\n");
3571 xhci_free_command(xhci, config_cmd);
3572 spin_unlock_irqrestore(&xhci->lock, flags);
3573 return -EINVAL;
3574 }
3575 vdev = xhci->devs[udev->slot_id];
3576 /* Mark each endpoint as being in transition, so
3577 * xhci_urb_enqueue() will reject all URBs.
3578 */
3579 for (i = 0; i < num_eps; i++) {
3580 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3581 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3582 }
3583 spin_unlock_irqrestore(&xhci->lock, flags);
3584
3585 /* Setup internal data structures and allocate HW data structures for
3586 * streams (but don't install the HW structures in the input context
3587 * until we're sure all memory allocation succeeded).
3588 */
3589 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3590 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3591 num_stream_ctxs, num_streams);
3592
3593 for (i = 0; i < num_eps; i++) {
3594 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3595 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3596 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3597 num_stream_ctxs,
3598 num_streams,
3599 max_packet, mem_flags);
3600 if (!vdev->eps[ep_index].stream_info)
3601 goto cleanup;
3602 /* Set maxPstreams in endpoint context and update deq ptr to
3603 * point to stream context array. FIXME
3604 */
3605 }
3606
3607 /* Set up the input context for a configure endpoint command. */
3608 for (i = 0; i < num_eps; i++) {
3609 struct xhci_ep_ctx *ep_ctx;
3610
3611 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3612 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3613
3614 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3615 vdev->out_ctx, ep_index);
3616 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3617 vdev->eps[ep_index].stream_info);
3618 }
3619 /* Tell the HW to drop its old copy of the endpoint context info
3620 * and add the updated copy from the input context.
3621 */
3622 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3623 vdev->out_ctx, ctrl_ctx,
3624 changed_ep_bitmask, changed_ep_bitmask);
3625
3626 /* Issue and wait for the configure endpoint command */
3627 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3628 false, false);
3629
3630 /* xHC rejected the configure endpoint command for some reason, so we
3631 * leave the old ring intact and free our internal streams data
3632 * structure.
3633 */
3634 if (ret < 0)
3635 goto cleanup;
3636
3637 spin_lock_irqsave(&xhci->lock, flags);
3638 for (i = 0; i < num_eps; i++) {
3639 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3640 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3641 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3642 udev->slot_id, ep_index);
3643 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3644 }
3645 xhci_free_command(xhci, config_cmd);
3646 spin_unlock_irqrestore(&xhci->lock, flags);
3647
3648 for (i = 0; i < num_eps; i++) {
3649 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3650 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3651 }
3652 /* Subtract 1 for stream 0, which drivers can't use */
3653 return num_streams - 1;
3654
3655cleanup:
3656 /* If it didn't work, free the streams! */
3657 for (i = 0; i < num_eps; i++) {
3658 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3659 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3660 vdev->eps[ep_index].stream_info = NULL;
3661 /* FIXME Unset maxPstreams in endpoint context and
3662 * update deq ptr to point to normal string ring.
3663 */
3664 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3665 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3666 xhci_endpoint_zero(xhci, vdev, eps[i]);
3667 }
3668 xhci_free_command(xhci, config_cmd);
3669 return -ENOMEM;
3670}
3671
3672/* Transition the endpoint from using streams to being a "normal" endpoint
3673 * without streams.
3674 *
3675 * Modify the endpoint context state, submit a configure endpoint command,
3676 * and free all endpoint rings for streams if that completes successfully.
3677 */
3678static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3679 struct usb_host_endpoint **eps, unsigned int num_eps,
3680 gfp_t mem_flags)
3681{
3682 int i, ret;
3683 struct xhci_hcd *xhci;
3684 struct xhci_virt_device *vdev;
3685 struct xhci_command *command;
3686 struct xhci_input_control_ctx *ctrl_ctx;
3687 unsigned int ep_index;
3688 unsigned long flags;
3689 u32 changed_ep_bitmask;
3690
3691 xhci = hcd_to_xhci(hcd);
3692 vdev = xhci->devs[udev->slot_id];
3693
3694 /* Set up a configure endpoint command to remove the streams rings */
3695 spin_lock_irqsave(&xhci->lock, flags);
3696 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3697 udev, eps, num_eps);
3698 if (changed_ep_bitmask == 0) {
3699 spin_unlock_irqrestore(&xhci->lock, flags);
3700 return -EINVAL;
3701 }
3702
3703 /* Use the xhci_command structure from the first endpoint. We may have
3704 * allocated too many, but the driver may call xhci_free_streams() for
3705 * each endpoint it grouped into one call to xhci_alloc_streams().
3706 */
3707 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3708 command = vdev->eps[ep_index].stream_info->free_streams_command;
3709 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3710 if (!ctrl_ctx) {
3711 spin_unlock_irqrestore(&xhci->lock, flags);
3712 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3713 __func__);
3714 return -EINVAL;
3715 }
3716
3717 for (i = 0; i < num_eps; i++) {
3718 struct xhci_ep_ctx *ep_ctx;
3719
3720 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3721 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3722 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3723 EP_GETTING_NO_STREAMS;
3724
3725 xhci_endpoint_copy(xhci, command->in_ctx,
3726 vdev->out_ctx, ep_index);
3727 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3728 &vdev->eps[ep_index]);
3729 }
3730 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3731 vdev->out_ctx, ctrl_ctx,
3732 changed_ep_bitmask, changed_ep_bitmask);
3733 spin_unlock_irqrestore(&xhci->lock, flags);
3734
3735 /* Issue and wait for the configure endpoint command,
3736 * which must succeed.
3737 */
3738 ret = xhci_configure_endpoint(xhci, udev, command,
3739 false, true);
3740
3741 /* xHC rejected the configure endpoint command for some reason, so we
3742 * leave the streams rings intact.
3743 */
3744 if (ret < 0)
3745 return ret;
3746
3747 spin_lock_irqsave(&xhci->lock, flags);
3748 for (i = 0; i < num_eps; i++) {
3749 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3750 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3751 vdev->eps[ep_index].stream_info = NULL;
3752 /* FIXME Unset maxPstreams in endpoint context and
3753 * update deq ptr to point to normal string ring.
3754 */
3755 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3756 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3757 }
3758 spin_unlock_irqrestore(&xhci->lock, flags);
3759
3760 return 0;
3761}
3762
3763/*
3764 * Deletes endpoint resources for endpoints that were active before a Reset
3765 * Device command, or a Disable Slot command. The Reset Device command leaves
3766 * the control endpoint intact, whereas the Disable Slot command deletes it.
3767 *
3768 * Must be called with xhci->lock held.
3769 */
3770void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3771 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3772{
3773 int i;
3774 unsigned int num_dropped_eps = 0;
3775 unsigned int drop_flags = 0;
3776
3777 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3778 if (virt_dev->eps[i].ring) {
3779 drop_flags |= 1 << i;
3780 num_dropped_eps++;
3781 }
3782 }
3783 xhci->num_active_eps -= num_dropped_eps;
3784 if (num_dropped_eps)
3785 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3786 "Dropped %u ep ctxs, flags = 0x%x, "
3787 "%u now active.",
3788 num_dropped_eps, drop_flags,
3789 xhci->num_active_eps);
3790}
3791
3792/*
3793 * This submits a Reset Device Command, which will set the device state to 0,
3794 * set the device address to 0, and disable all the endpoints except the default
3795 * control endpoint. The USB core should come back and call
3796 * xhci_address_device(), and then re-set up the configuration. If this is
3797 * called because of a usb_reset_and_verify_device(), then the old alternate
3798 * settings will be re-installed through the normal bandwidth allocation
3799 * functions.
3800 *
3801 * Wait for the Reset Device command to finish. Remove all structures
3802 * associated with the endpoints that were disabled. Clear the input device
3803 * structure? Reset the control endpoint 0 max packet size?
3804 *
3805 * If the virt_dev to be reset does not exist or does not match the udev,
3806 * it means the device is lost, possibly due to the xHC restore error and
3807 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3808 * re-allocate the device.
3809 */
3810static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3811 struct usb_device *udev)
3812{
3813 int ret, i;
3814 unsigned long flags;
3815 struct xhci_hcd *xhci;
3816 unsigned int slot_id;
3817 struct xhci_virt_device *virt_dev;
3818 struct xhci_command *reset_device_cmd;
3819 struct xhci_slot_ctx *slot_ctx;
3820 int old_active_eps = 0;
3821
3822 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3823 if (ret <= 0)
3824 return ret;
3825 xhci = hcd_to_xhci(hcd);
3826 slot_id = udev->slot_id;
3827 virt_dev = xhci->devs[slot_id];
3828 if (!virt_dev) {
3829 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3830 "not exist. Re-allocate the device\n", slot_id);
3831 ret = xhci_alloc_dev(hcd, udev);
3832 if (ret == 1)
3833 return 0;
3834 else
3835 return -EINVAL;
3836 }
3837
3838 if (virt_dev->tt_info)
3839 old_active_eps = virt_dev->tt_info->active_eps;
3840
3841 if (virt_dev->udev != udev) {
3842 /* If the virt_dev and the udev does not match, this virt_dev
3843 * may belong to another udev.
3844 * Re-allocate the device.
3845 */
3846 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3847 "not match the udev. Re-allocate the device\n",
3848 slot_id);
3849 ret = xhci_alloc_dev(hcd, udev);
3850 if (ret == 1)
3851 return 0;
3852 else
3853 return -EINVAL;
3854 }
3855
3856 /* If device is not setup, there is no point in resetting it */
3857 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3858 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3859 SLOT_STATE_DISABLED)
3860 return 0;
3861
3862 trace_xhci_discover_or_reset_device(slot_ctx);
3863
3864 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3865 /* Allocate the command structure that holds the struct completion.
3866 * Assume we're in process context, since the normal device reset
3867 * process has to wait for the device anyway. Storage devices are
3868 * reset as part of error handling, so use GFP_NOIO instead of
3869 * GFP_KERNEL.
3870 */
3871 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3872 if (!reset_device_cmd) {
3873 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3874 return -ENOMEM;
3875 }
3876
3877 /* Attempt to submit the Reset Device command to the command ring */
3878 spin_lock_irqsave(&xhci->lock, flags);
3879
3880 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3881 if (ret) {
3882 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3883 spin_unlock_irqrestore(&xhci->lock, flags);
3884 goto command_cleanup;
3885 }
3886 xhci_ring_cmd_db(xhci);
3887 spin_unlock_irqrestore(&xhci->lock, flags);
3888
3889 /* Wait for the Reset Device command to finish */
3890 wait_for_completion(reset_device_cmd->completion);
3891
3892 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3893 * unless we tried to reset a slot ID that wasn't enabled,
3894 * or the device wasn't in the addressed or configured state.
3895 */
3896 ret = reset_device_cmd->status;
3897 switch (ret) {
3898 case COMP_COMMAND_ABORTED:
3899 case COMP_COMMAND_RING_STOPPED:
3900 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3901 ret = -ETIME;
3902 goto command_cleanup;
3903 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3904 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3905 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3906 slot_id,
3907 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3908 xhci_dbg(xhci, "Not freeing device rings.\n");
3909 /* Don't treat this as an error. May change my mind later. */
3910 ret = 0;
3911 goto command_cleanup;
3912 case COMP_SUCCESS:
3913 xhci_dbg(xhci, "Successful reset device command.\n");
3914 break;
3915 default:
3916 if (xhci_is_vendor_info_code(xhci, ret))
3917 break;
3918 xhci_warn(xhci, "Unknown completion code %u for "
3919 "reset device command.\n", ret);
3920 ret = -EINVAL;
3921 goto command_cleanup;
3922 }
3923
3924 /* Free up host controller endpoint resources */
3925 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3926 spin_lock_irqsave(&xhci->lock, flags);
3927 /* Don't delete the default control endpoint resources */
3928 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3929 spin_unlock_irqrestore(&xhci->lock, flags);
3930 }
3931
3932 /* Everything but endpoint 0 is disabled, so free the rings. */
3933 for (i = 1; i < 31; i++) {
3934 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3935
3936 if (ep->ep_state & EP_HAS_STREAMS) {
3937 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3938 xhci_get_endpoint_address(i));
3939 xhci_free_stream_info(xhci, ep->stream_info);
3940 ep->stream_info = NULL;
3941 ep->ep_state &= ~EP_HAS_STREAMS;
3942 }
3943
3944 if (ep->ring) {
3945 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3946 xhci_free_endpoint_ring(xhci, virt_dev, i);
3947 }
3948 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3949 xhci_drop_ep_from_interval_table(xhci,
3950 &virt_dev->eps[i].bw_info,
3951 virt_dev->bw_table,
3952 udev,
3953 &virt_dev->eps[i],
3954 virt_dev->tt_info);
3955 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3956 }
3957 /* If necessary, update the number of active TTs on this root port */
3958 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3959 virt_dev->flags = 0;
3960 ret = 0;
3961
3962command_cleanup:
3963 xhci_free_command(xhci, reset_device_cmd);
3964 return ret;
3965}
3966
3967/*
3968 * At this point, the struct usb_device is about to go away, the device has
3969 * disconnected, and all traffic has been stopped and the endpoints have been
3970 * disabled. Free any HC data structures associated with that device.
3971 */
3972static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3973{
3974 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3975 struct xhci_virt_device *virt_dev;
3976 struct xhci_slot_ctx *slot_ctx;
3977 unsigned long flags;
3978 int i, ret;
3979
3980 /*
3981 * We called pm_runtime_get_noresume when the device was attached.
3982 * Decrement the counter here to allow controller to runtime suspend
3983 * if no devices remain.
3984 */
3985 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3986 pm_runtime_put_noidle(hcd->self.controller);
3987
3988 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3989 /* If the host is halted due to driver unload, we still need to free the
3990 * device.
3991 */
3992 if (ret <= 0 && ret != -ENODEV)
3993 return;
3994
3995 virt_dev = xhci->devs[udev->slot_id];
3996 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3997 trace_xhci_free_dev(slot_ctx);
3998
3999 /* Stop any wayward timer functions (which may grab the lock) */
4000 for (i = 0; i < 31; i++)
4001 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4002 virt_dev->udev = NULL;
4003 xhci_disable_slot(xhci, udev->slot_id);
4004
4005 spin_lock_irqsave(&xhci->lock, flags);
4006 xhci_free_virt_device(xhci, udev->slot_id);
4007 spin_unlock_irqrestore(&xhci->lock, flags);
4008
4009}
4010
4011int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4012{
4013 struct xhci_command *command;
4014 unsigned long flags;
4015 u32 state;
4016 int ret;
4017
4018 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4019 if (!command)
4020 return -ENOMEM;
4021
4022 xhci_debugfs_remove_slot(xhci, slot_id);
4023
4024 spin_lock_irqsave(&xhci->lock, flags);
4025 /* Don't disable the slot if the host controller is dead. */
4026 state = readl(&xhci->op_regs->status);
4027 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4028 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4029 spin_unlock_irqrestore(&xhci->lock, flags);
4030 kfree(command);
4031 return -ENODEV;
4032 }
4033
4034 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4035 slot_id);
4036 if (ret) {
4037 spin_unlock_irqrestore(&xhci->lock, flags);
4038 kfree(command);
4039 return ret;
4040 }
4041 xhci_ring_cmd_db(xhci);
4042 spin_unlock_irqrestore(&xhci->lock, flags);
4043
4044 wait_for_completion(command->completion);
4045
4046 if (command->status != COMP_SUCCESS)
4047 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4048 slot_id, command->status);
4049
4050 xhci_free_command(xhci, command);
4051
4052 return 0;
4053}
4054
4055/*
4056 * Checks if we have enough host controller resources for the default control
4057 * endpoint.
4058 *
4059 * Must be called with xhci->lock held.
4060 */
4061static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4062{
4063 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4064 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4065 "Not enough ep ctxs: "
4066 "%u active, need to add 1, limit is %u.",
4067 xhci->num_active_eps, xhci->limit_active_eps);
4068 return -ENOMEM;
4069 }
4070 xhci->num_active_eps += 1;
4071 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4072 "Adding 1 ep ctx, %u now active.",
4073 xhci->num_active_eps);
4074 return 0;
4075}
4076
4077
4078/*
4079 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4080 * timed out, or allocating memory failed. Returns 1 on success.
4081 */
4082int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4083{
4084 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4085 struct xhci_virt_device *vdev;
4086 struct xhci_slot_ctx *slot_ctx;
4087 unsigned long flags;
4088 int ret, slot_id;
4089 struct xhci_command *command;
4090
4091 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4092 if (!command)
4093 return 0;
4094
4095 spin_lock_irqsave(&xhci->lock, flags);
4096 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4097 if (ret) {
4098 spin_unlock_irqrestore(&xhci->lock, flags);
4099 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4100 xhci_free_command(xhci, command);
4101 return 0;
4102 }
4103 xhci_ring_cmd_db(xhci);
4104 spin_unlock_irqrestore(&xhci->lock, flags);
4105
4106 wait_for_completion(command->completion);
4107 slot_id = command->slot_id;
4108
4109 if (!slot_id || command->status != COMP_SUCCESS) {
4110 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4111 xhci_trb_comp_code_string(command->status));
4112 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4113 HCS_MAX_SLOTS(
4114 readl(&xhci->cap_regs->hcs_params1)));
4115 xhci_free_command(xhci, command);
4116 return 0;
4117 }
4118
4119 xhci_free_command(xhci, command);
4120
4121 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4122 spin_lock_irqsave(&xhci->lock, flags);
4123 ret = xhci_reserve_host_control_ep_resources(xhci);
4124 if (ret) {
4125 spin_unlock_irqrestore(&xhci->lock, flags);
4126 xhci_warn(xhci, "Not enough host resources, "
4127 "active endpoint contexts = %u\n",
4128 xhci->num_active_eps);
4129 goto disable_slot;
4130 }
4131 spin_unlock_irqrestore(&xhci->lock, flags);
4132 }
4133 /* Use GFP_NOIO, since this function can be called from
4134 * xhci_discover_or_reset_device(), which may be called as part of
4135 * mass storage driver error handling.
4136 */
4137 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4138 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4139 goto disable_slot;
4140 }
4141 vdev = xhci->devs[slot_id];
4142 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4143 trace_xhci_alloc_dev(slot_ctx);
4144
4145 udev->slot_id = slot_id;
4146
4147 xhci_debugfs_create_slot(xhci, slot_id);
4148
4149 /*
4150 * If resetting upon resume, we can't put the controller into runtime
4151 * suspend if there is a device attached.
4152 */
4153 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4154 pm_runtime_get_noresume(hcd->self.controller);
4155
4156 /* Is this a LS or FS device under a HS hub? */
4157 /* Hub or peripherial? */
4158 return 1;
4159
4160disable_slot:
4161 xhci_disable_slot(xhci, udev->slot_id);
4162 xhci_free_virt_device(xhci, udev->slot_id);
4163
4164 return 0;
4165}
4166
4167/*
4168 * Issue an Address Device command and optionally send a corresponding
4169 * SetAddress request to the device.
4170 */
4171static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4172 enum xhci_setup_dev setup)
4173{
4174 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4175 unsigned long flags;
4176 struct xhci_virt_device *virt_dev;
4177 int ret = 0;
4178 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4179 struct xhci_slot_ctx *slot_ctx;
4180 struct xhci_input_control_ctx *ctrl_ctx;
4181 u64 temp_64;
4182 struct xhci_command *command = NULL;
4183
4184 mutex_lock(&xhci->mutex);
4185
4186 if (xhci->xhc_state) { /* dying, removing or halted */
4187 ret = -ESHUTDOWN;
4188 goto out;
4189 }
4190
4191 if (!udev->slot_id) {
4192 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4193 "Bad Slot ID %d", udev->slot_id);
4194 ret = -EINVAL;
4195 goto out;
4196 }
4197
4198 virt_dev = xhci->devs[udev->slot_id];
4199
4200 if (WARN_ON(!virt_dev)) {
4201 /*
4202 * In plug/unplug torture test with an NEC controller,
4203 * a zero-dereference was observed once due to virt_dev = 0.
4204 * Print useful debug rather than crash if it is observed again!
4205 */
4206 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4207 udev->slot_id);
4208 ret = -EINVAL;
4209 goto out;
4210 }
4211 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4212 trace_xhci_setup_device_slot(slot_ctx);
4213
4214 if (setup == SETUP_CONTEXT_ONLY) {
4215 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4216 SLOT_STATE_DEFAULT) {
4217 xhci_dbg(xhci, "Slot already in default state\n");
4218 goto out;
4219 }
4220 }
4221
4222 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4223 if (!command) {
4224 ret = -ENOMEM;
4225 goto out;
4226 }
4227
4228 command->in_ctx = virt_dev->in_ctx;
4229
4230 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4231 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4232 if (!ctrl_ctx) {
4233 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4234 __func__);
4235 ret = -EINVAL;
4236 goto out;
4237 }
4238 /*
4239 * If this is the first Set Address since device plug-in or
4240 * virt_device realloaction after a resume with an xHCI power loss,
4241 * then set up the slot context.
4242 */
4243 if (!slot_ctx->dev_info)
4244 xhci_setup_addressable_virt_dev(xhci, udev);
4245 /* Otherwise, update the control endpoint ring enqueue pointer. */
4246 else
4247 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4248 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4249 ctrl_ctx->drop_flags = 0;
4250
4251 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4252 le32_to_cpu(slot_ctx->dev_info) >> 27);
4253
4254 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4255 spin_lock_irqsave(&xhci->lock, flags);
4256 trace_xhci_setup_device(virt_dev);
4257 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4258 udev->slot_id, setup);
4259 if (ret) {
4260 spin_unlock_irqrestore(&xhci->lock, flags);
4261 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4262 "FIXME: allocate a command ring segment");
4263 goto out;
4264 }
4265 xhci_ring_cmd_db(xhci);
4266 spin_unlock_irqrestore(&xhci->lock, flags);
4267
4268 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4269 wait_for_completion(command->completion);
4270
4271 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4272 * the SetAddress() "recovery interval" required by USB and aborting the
4273 * command on a timeout.
4274 */
4275 switch (command->status) {
4276 case COMP_COMMAND_ABORTED:
4277 case COMP_COMMAND_RING_STOPPED:
4278 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4279 ret = -ETIME;
4280 break;
4281 case COMP_CONTEXT_STATE_ERROR:
4282 case COMP_SLOT_NOT_ENABLED_ERROR:
4283 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4284 act, udev->slot_id);
4285 ret = -EINVAL;
4286 break;
4287 case COMP_USB_TRANSACTION_ERROR:
4288 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4289
4290 mutex_unlock(&xhci->mutex);
4291 ret = xhci_disable_slot(xhci, udev->slot_id);
4292 xhci_free_virt_device(xhci, udev->slot_id);
4293 if (!ret)
4294 xhci_alloc_dev(hcd, udev);
4295 kfree(command->completion);
4296 kfree(command);
4297 return -EPROTO;
4298 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4299 dev_warn(&udev->dev,
4300 "ERROR: Incompatible device for setup %s command\n", act);
4301 ret = -ENODEV;
4302 break;
4303 case COMP_SUCCESS:
4304 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4305 "Successful setup %s command", act);
4306 break;
4307 default:
4308 xhci_err(xhci,
4309 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4310 act, command->status);
4311 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4312 ret = -EINVAL;
4313 break;
4314 }
4315 if (ret)
4316 goto out;
4317 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4318 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4319 "Op regs DCBAA ptr = %#016llx", temp_64);
4320 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4321 "Slot ID %d dcbaa entry @%p = %#016llx",
4322 udev->slot_id,
4323 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4324 (unsigned long long)
4325 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4326 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4327 "Output Context DMA address = %#08llx",
4328 (unsigned long long)virt_dev->out_ctx->dma);
4329 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4330 le32_to_cpu(slot_ctx->dev_info) >> 27);
4331 /*
4332 * USB core uses address 1 for the roothubs, so we add one to the
4333 * address given back to us by the HC.
4334 */
4335 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4336 le32_to_cpu(slot_ctx->dev_info) >> 27);
4337 /* Zero the input context control for later use */
4338 ctrl_ctx->add_flags = 0;
4339 ctrl_ctx->drop_flags = 0;
4340 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4341 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4342
4343 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4344 "Internal device address = %d",
4345 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4346out:
4347 mutex_unlock(&xhci->mutex);
4348 if (command) {
4349 kfree(command->completion);
4350 kfree(command);
4351 }
4352 return ret;
4353}
4354
4355static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4356{
4357 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4358}
4359
4360static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4361{
4362 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4363}
4364
4365/*
4366 * Transfer the port index into real index in the HW port status
4367 * registers. Caculate offset between the port's PORTSC register
4368 * and port status base. Divide the number of per port register
4369 * to get the real index. The raw port number bases 1.
4370 */
4371int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4372{
4373 struct xhci_hub *rhub;
4374
4375 rhub = xhci_get_rhub(hcd);
4376 return rhub->ports[port1 - 1]->hw_portnum + 1;
4377}
4378
4379/*
4380 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4381 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4382 */
4383static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4384 struct usb_device *udev, u16 max_exit_latency)
4385{
4386 struct xhci_virt_device *virt_dev;
4387 struct xhci_command *command;
4388 struct xhci_input_control_ctx *ctrl_ctx;
4389 struct xhci_slot_ctx *slot_ctx;
4390 unsigned long flags;
4391 int ret;
4392
4393 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4394 if (!command)
4395 return -ENOMEM;
4396
4397 spin_lock_irqsave(&xhci->lock, flags);
4398
4399 virt_dev = xhci->devs[udev->slot_id];
4400
4401 /*
4402 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4403 * xHC was re-initialized. Exit latency will be set later after
4404 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4405 */
4406
4407 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4408 spin_unlock_irqrestore(&xhci->lock, flags);
4409 return 0;
4410 }
4411
4412 /* Attempt to issue an Evaluate Context command to change the MEL. */
4413 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4414 if (!ctrl_ctx) {
4415 spin_unlock_irqrestore(&xhci->lock, flags);
4416 xhci_free_command(xhci, command);
4417 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4418 __func__);
4419 return -ENOMEM;
4420 }
4421
4422 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4423 spin_unlock_irqrestore(&xhci->lock, flags);
4424
4425 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4426 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4427 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4428 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4429 slot_ctx->dev_state = 0;
4430
4431 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4432 "Set up evaluate context for LPM MEL change.");
4433
4434 /* Issue and wait for the evaluate context command. */
4435 ret = xhci_configure_endpoint(xhci, udev, command,
4436 true, true);
4437
4438 if (!ret) {
4439 spin_lock_irqsave(&xhci->lock, flags);
4440 virt_dev->current_mel = max_exit_latency;
4441 spin_unlock_irqrestore(&xhci->lock, flags);
4442 }
4443
4444 xhci_free_command(xhci, command);
4445
4446 return ret;
4447}
4448
4449#ifdef CONFIG_PM
4450
4451/* BESL to HIRD Encoding array for USB2 LPM */
4452static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4453 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4454
4455/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4456static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4457 struct usb_device *udev)
4458{
4459 int u2del, besl, besl_host;
4460 int besl_device = 0;
4461 u32 field;
4462
4463 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4464 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4465
4466 if (field & USB_BESL_SUPPORT) {
4467 for (besl_host = 0; besl_host < 16; besl_host++) {
4468 if (xhci_besl_encoding[besl_host] >= u2del)
4469 break;
4470 }
4471 /* Use baseline BESL value as default */
4472 if (field & USB_BESL_BASELINE_VALID)
4473 besl_device = USB_GET_BESL_BASELINE(field);
4474 else if (field & USB_BESL_DEEP_VALID)
4475 besl_device = USB_GET_BESL_DEEP(field);
4476 } else {
4477 if (u2del <= 50)
4478 besl_host = 0;
4479 else
4480 besl_host = (u2del - 51) / 75 + 1;
4481 }
4482
4483 besl = besl_host + besl_device;
4484 if (besl > 15)
4485 besl = 15;
4486
4487 return besl;
4488}
4489
4490/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4491static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4492{
4493 u32 field;
4494 int l1;
4495 int besld = 0;
4496 int hirdm = 0;
4497
4498 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4499
4500 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4501 l1 = udev->l1_params.timeout / 256;
4502
4503 /* device has preferred BESLD */
4504 if (field & USB_BESL_DEEP_VALID) {
4505 besld = USB_GET_BESL_DEEP(field);
4506 hirdm = 1;
4507 }
4508
4509 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4510}
4511
4512static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4513 struct usb_device *udev, int enable)
4514{
4515 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4516 struct xhci_port **ports;
4517 __le32 __iomem *pm_addr, *hlpm_addr;
4518 u32 pm_val, hlpm_val, field;
4519 unsigned int port_num;
4520 unsigned long flags;
4521 int hird, exit_latency;
4522 int ret;
4523
4524 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4525 return -EPERM;
4526
4527 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4528 !udev->lpm_capable)
4529 return -EPERM;
4530
4531 if (!udev->parent || udev->parent->parent ||
4532 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4533 return -EPERM;
4534
4535 if (udev->usb2_hw_lpm_capable != 1)
4536 return -EPERM;
4537
4538 spin_lock_irqsave(&xhci->lock, flags);
4539
4540 ports = xhci->usb2_rhub.ports;
4541 port_num = udev->portnum - 1;
4542 pm_addr = ports[port_num]->addr + PORTPMSC;
4543 pm_val = readl(pm_addr);
4544 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4545
4546 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4547 enable ? "enable" : "disable", port_num + 1);
4548
4549 if (enable) {
4550 /* Host supports BESL timeout instead of HIRD */
4551 if (udev->usb2_hw_lpm_besl_capable) {
4552 /* if device doesn't have a preferred BESL value use a
4553 * default one which works with mixed HIRD and BESL
4554 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4555 */
4556 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4557 if ((field & USB_BESL_SUPPORT) &&
4558 (field & USB_BESL_BASELINE_VALID))
4559 hird = USB_GET_BESL_BASELINE(field);
4560 else
4561 hird = udev->l1_params.besl;
4562
4563 exit_latency = xhci_besl_encoding[hird];
4564 spin_unlock_irqrestore(&xhci->lock, flags);
4565
4566 ret = xhci_change_max_exit_latency(xhci, udev,
4567 exit_latency);
4568 if (ret < 0)
4569 return ret;
4570 spin_lock_irqsave(&xhci->lock, flags);
4571
4572 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4573 writel(hlpm_val, hlpm_addr);
4574 /* flush write */
4575 readl(hlpm_addr);
4576 } else {
4577 hird = xhci_calculate_hird_besl(xhci, udev);
4578 }
4579
4580 pm_val &= ~PORT_HIRD_MASK;
4581 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4582 writel(pm_val, pm_addr);
4583 pm_val = readl(pm_addr);
4584 pm_val |= PORT_HLE;
4585 writel(pm_val, pm_addr);
4586 /* flush write */
4587 readl(pm_addr);
4588 } else {
4589 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4590 writel(pm_val, pm_addr);
4591 /* flush write */
4592 readl(pm_addr);
4593 if (udev->usb2_hw_lpm_besl_capable) {
4594 spin_unlock_irqrestore(&xhci->lock, flags);
4595 xhci_change_max_exit_latency(xhci, udev, 0);
4596 readl_poll_timeout(ports[port_num]->addr, pm_val,
4597 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4598 100, 10000);
4599 return 0;
4600 }
4601 }
4602
4603 spin_unlock_irqrestore(&xhci->lock, flags);
4604 return 0;
4605}
4606
4607/* check if a usb2 port supports a given extened capability protocol
4608 * only USB2 ports extended protocol capability values are cached.
4609 * Return 1 if capability is supported
4610 */
4611static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4612 unsigned capability)
4613{
4614 u32 port_offset, port_count;
4615 int i;
4616
4617 for (i = 0; i < xhci->num_ext_caps; i++) {
4618 if (xhci->ext_caps[i] & capability) {
4619 /* port offsets starts at 1 */
4620 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4621 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4622 if (port >= port_offset &&
4623 port < port_offset + port_count)
4624 return 1;
4625 }
4626 }
4627 return 0;
4628}
4629
4630static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4631{
4632 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4633 int portnum = udev->portnum - 1;
4634
4635 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4636 return 0;
4637
4638 /* we only support lpm for non-hub device connected to root hub yet */
4639 if (!udev->parent || udev->parent->parent ||
4640 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4641 return 0;
4642
4643 if (xhci->hw_lpm_support == 1 &&
4644 xhci_check_usb2_port_capability(
4645 xhci, portnum, XHCI_HLC)) {
4646 udev->usb2_hw_lpm_capable = 1;
4647 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4648 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4649 if (xhci_check_usb2_port_capability(xhci, portnum,
4650 XHCI_BLC))
4651 udev->usb2_hw_lpm_besl_capable = 1;
4652 }
4653
4654 return 0;
4655}
4656
4657/*---------------------- USB 3.0 Link PM functions ------------------------*/
4658
4659/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4660static unsigned long long xhci_service_interval_to_ns(
4661 struct usb_endpoint_descriptor *desc)
4662{
4663 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4664}
4665
4666static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4667 enum usb3_link_state state)
4668{
4669 unsigned long long sel;
4670 unsigned long long pel;
4671 unsigned int max_sel_pel;
4672 char *state_name;
4673
4674 switch (state) {
4675 case USB3_LPM_U1:
4676 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4677 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4678 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4679 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4680 state_name = "U1";
4681 break;
4682 case USB3_LPM_U2:
4683 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4684 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4685 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4686 state_name = "U2";
4687 break;
4688 default:
4689 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4690 __func__);
4691 return USB3_LPM_DISABLED;
4692 }
4693
4694 if (sel <= max_sel_pel && pel <= max_sel_pel)
4695 return USB3_LPM_DEVICE_INITIATED;
4696
4697 if (sel > max_sel_pel)
4698 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4699 "due to long SEL %llu ms\n",
4700 state_name, sel);
4701 else
4702 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4703 "due to long PEL %llu ms\n",
4704 state_name, pel);
4705 return USB3_LPM_DISABLED;
4706}
4707
4708/* The U1 timeout should be the maximum of the following values:
4709 * - For control endpoints, U1 system exit latency (SEL) * 3
4710 * - For bulk endpoints, U1 SEL * 5
4711 * - For interrupt endpoints:
4712 * - Notification EPs, U1 SEL * 3
4713 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4714 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4715 */
4716static unsigned long long xhci_calculate_intel_u1_timeout(
4717 struct usb_device *udev,
4718 struct usb_endpoint_descriptor *desc)
4719{
4720 unsigned long long timeout_ns;
4721 int ep_type;
4722 int intr_type;
4723
4724 ep_type = usb_endpoint_type(desc);
4725 switch (ep_type) {
4726 case USB_ENDPOINT_XFER_CONTROL:
4727 timeout_ns = udev->u1_params.sel * 3;
4728 break;
4729 case USB_ENDPOINT_XFER_BULK:
4730 timeout_ns = udev->u1_params.sel * 5;
4731 break;
4732 case USB_ENDPOINT_XFER_INT:
4733 intr_type = usb_endpoint_interrupt_type(desc);
4734 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4735 timeout_ns = udev->u1_params.sel * 3;
4736 break;
4737 }
4738 /* Otherwise the calculation is the same as isoc eps */
4739 fallthrough;
4740 case USB_ENDPOINT_XFER_ISOC:
4741 timeout_ns = xhci_service_interval_to_ns(desc);
4742 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4743 if (timeout_ns < udev->u1_params.sel * 2)
4744 timeout_ns = udev->u1_params.sel * 2;
4745 break;
4746 default:
4747 return 0;
4748 }
4749
4750 return timeout_ns;
4751}
4752
4753/* Returns the hub-encoded U1 timeout value. */
4754static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4755 struct usb_device *udev,
4756 struct usb_endpoint_descriptor *desc)
4757{
4758 unsigned long long timeout_ns;
4759
4760 /* Prevent U1 if service interval is shorter than U1 exit latency */
4761 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4762 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4763 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4764 return USB3_LPM_DISABLED;
4765 }
4766 }
4767
4768 if (xhci->quirks & XHCI_INTEL_HOST)
4769 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4770 else
4771 timeout_ns = udev->u1_params.sel;
4772
4773 /* The U1 timeout is encoded in 1us intervals.
4774 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4775 */
4776 if (timeout_ns == USB3_LPM_DISABLED)
4777 timeout_ns = 1;
4778 else
4779 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4780
4781 /* If the necessary timeout value is bigger than what we can set in the
4782 * USB 3.0 hub, we have to disable hub-initiated U1.
4783 */
4784 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4785 return timeout_ns;
4786 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4787 "due to long timeout %llu ms\n", timeout_ns);
4788 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4789}
4790
4791/* The U2 timeout should be the maximum of:
4792 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4793 * - largest bInterval of any active periodic endpoint (to avoid going
4794 * into lower power link states between intervals).
4795 * - the U2 Exit Latency of the device
4796 */
4797static unsigned long long xhci_calculate_intel_u2_timeout(
4798 struct usb_device *udev,
4799 struct usb_endpoint_descriptor *desc)
4800{
4801 unsigned long long timeout_ns;
4802 unsigned long long u2_del_ns;
4803
4804 timeout_ns = 10 * 1000 * 1000;
4805
4806 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4807 (xhci_service_interval_to_ns(desc) > timeout_ns))
4808 timeout_ns = xhci_service_interval_to_ns(desc);
4809
4810 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4811 if (u2_del_ns > timeout_ns)
4812 timeout_ns = u2_del_ns;
4813
4814 return timeout_ns;
4815}
4816
4817/* Returns the hub-encoded U2 timeout value. */
4818static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4819 struct usb_device *udev,
4820 struct usb_endpoint_descriptor *desc)
4821{
4822 unsigned long long timeout_ns;
4823
4824 /* Prevent U2 if service interval is shorter than U2 exit latency */
4825 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4826 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4827 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4828 return USB3_LPM_DISABLED;
4829 }
4830 }
4831
4832 if (xhci->quirks & XHCI_INTEL_HOST)
4833 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4834 else
4835 timeout_ns = udev->u2_params.sel;
4836
4837 /* The U2 timeout is encoded in 256us intervals */
4838 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4839 /* If the necessary timeout value is bigger than what we can set in the
4840 * USB 3.0 hub, we have to disable hub-initiated U2.
4841 */
4842 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4843 return timeout_ns;
4844 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4845 "due to long timeout %llu ms\n", timeout_ns);
4846 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4847}
4848
4849static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4850 struct usb_device *udev,
4851 struct usb_endpoint_descriptor *desc,
4852 enum usb3_link_state state,
4853 u16 *timeout)
4854{
4855 if (state == USB3_LPM_U1)
4856 return xhci_calculate_u1_timeout(xhci, udev, desc);
4857 else if (state == USB3_LPM_U2)
4858 return xhci_calculate_u2_timeout(xhci, udev, desc);
4859
4860 return USB3_LPM_DISABLED;
4861}
4862
4863static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4864 struct usb_device *udev,
4865 struct usb_endpoint_descriptor *desc,
4866 enum usb3_link_state state,
4867 u16 *timeout)
4868{
4869 u16 alt_timeout;
4870
4871 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4872 desc, state, timeout);
4873
4874 /* If we found we can't enable hub-initiated LPM, and
4875 * the U1 or U2 exit latency was too high to allow
4876 * device-initiated LPM as well, then we will disable LPM
4877 * for this device, so stop searching any further.
4878 */
4879 if (alt_timeout == USB3_LPM_DISABLED) {
4880 *timeout = alt_timeout;
4881 return -E2BIG;
4882 }
4883 if (alt_timeout > *timeout)
4884 *timeout = alt_timeout;
4885 return 0;
4886}
4887
4888static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4889 struct usb_device *udev,
4890 struct usb_host_interface *alt,
4891 enum usb3_link_state state,
4892 u16 *timeout)
4893{
4894 int j;
4895
4896 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4897 if (xhci_update_timeout_for_endpoint(xhci, udev,
4898 &alt->endpoint[j].desc, state, timeout))
4899 return -E2BIG;
4900 }
4901 return 0;
4902}
4903
4904static int xhci_check_intel_tier_policy(struct usb_device *udev,
4905 enum usb3_link_state state)
4906{
4907 struct usb_device *parent;
4908 unsigned int num_hubs;
4909
4910 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4911 for (parent = udev->parent, num_hubs = 0; parent->parent;
4912 parent = parent->parent)
4913 num_hubs++;
4914
4915 if (num_hubs < 2)
4916 return 0;
4917
4918 dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
4919 " below second-tier hub.\n");
4920 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4921 "to decrease power consumption.\n");
4922 return -E2BIG;
4923}
4924
4925static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4926 struct usb_device *udev,
4927 enum usb3_link_state state)
4928{
4929 if (xhci->quirks & XHCI_INTEL_HOST)
4930 return xhci_check_intel_tier_policy(udev, state);
4931 else
4932 return 0;
4933}
4934
4935/* Returns the U1 or U2 timeout that should be enabled.
4936 * If the tier check or timeout setting functions return with a non-zero exit
4937 * code, that means the timeout value has been finalized and we shouldn't look
4938 * at any more endpoints.
4939 */
4940static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4941 struct usb_device *udev, enum usb3_link_state state)
4942{
4943 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4944 struct usb_host_config *config;
4945 char *state_name;
4946 int i;
4947 u16 timeout = USB3_LPM_DISABLED;
4948
4949 if (state == USB3_LPM_U1)
4950 state_name = "U1";
4951 else if (state == USB3_LPM_U2)
4952 state_name = "U2";
4953 else {
4954 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4955 state);
4956 return timeout;
4957 }
4958
4959 /* Gather some information about the currently installed configuration
4960 * and alternate interface settings.
4961 */
4962 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4963 state, &timeout))
4964 return timeout;
4965
4966 config = udev->actconfig;
4967 if (!config)
4968 return timeout;
4969
4970 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4971 struct usb_driver *driver;
4972 struct usb_interface *intf = config->interface[i];
4973
4974 if (!intf)
4975 continue;
4976
4977 /* Check if any currently bound drivers want hub-initiated LPM
4978 * disabled.
4979 */
4980 if (intf->dev.driver) {
4981 driver = to_usb_driver(intf->dev.driver);
4982 if (driver && driver->disable_hub_initiated_lpm) {
4983 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4984 state_name, driver->name);
4985 timeout = xhci_get_timeout_no_hub_lpm(udev,
4986 state);
4987 if (timeout == USB3_LPM_DISABLED)
4988 return timeout;
4989 }
4990 }
4991
4992 /* Not sure how this could happen... */
4993 if (!intf->cur_altsetting)
4994 continue;
4995
4996 if (xhci_update_timeout_for_interface(xhci, udev,
4997 intf->cur_altsetting,
4998 state, &timeout))
4999 return timeout;
5000 }
5001 return timeout;
5002}
5003
5004static int calculate_max_exit_latency(struct usb_device *udev,
5005 enum usb3_link_state state_changed,
5006 u16 hub_encoded_timeout)
5007{
5008 unsigned long long u1_mel_us = 0;
5009 unsigned long long u2_mel_us = 0;
5010 unsigned long long mel_us = 0;
5011 bool disabling_u1;
5012 bool disabling_u2;
5013 bool enabling_u1;
5014 bool enabling_u2;
5015
5016 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5017 hub_encoded_timeout == USB3_LPM_DISABLED);
5018 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5019 hub_encoded_timeout == USB3_LPM_DISABLED);
5020
5021 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5022 hub_encoded_timeout != USB3_LPM_DISABLED);
5023 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5024 hub_encoded_timeout != USB3_LPM_DISABLED);
5025
5026 /* If U1 was already enabled and we're not disabling it,
5027 * or we're going to enable U1, account for the U1 max exit latency.
5028 */
5029 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5030 enabling_u1)
5031 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5032 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5033 enabling_u2)
5034 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5035
5036 mel_us = max(u1_mel_us, u2_mel_us);
5037
5038 /* xHCI host controller max exit latency field is only 16 bits wide. */
5039 if (mel_us > MAX_EXIT) {
5040 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5041 "is too big.\n", mel_us);
5042 return -E2BIG;
5043 }
5044 return mel_us;
5045}
5046
5047/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5048static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5049 struct usb_device *udev, enum usb3_link_state state)
5050{
5051 struct xhci_hcd *xhci;
5052 struct xhci_port *port;
5053 u16 hub_encoded_timeout;
5054 int mel;
5055 int ret;
5056
5057 xhci = hcd_to_xhci(hcd);
5058 /* The LPM timeout values are pretty host-controller specific, so don't
5059 * enable hub-initiated timeouts unless the vendor has provided
5060 * information about their timeout algorithm.
5061 */
5062 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5063 !xhci->devs[udev->slot_id])
5064 return USB3_LPM_DISABLED;
5065
5066 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5067 return USB3_LPM_DISABLED;
5068
5069 /* If connected to root port then check port can handle lpm */
5070 if (udev->parent && !udev->parent->parent) {
5071 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5072 if (port->lpm_incapable)
5073 return USB3_LPM_DISABLED;
5074 }
5075
5076 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5077 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5078 if (mel < 0) {
5079 /* Max Exit Latency is too big, disable LPM. */
5080 hub_encoded_timeout = USB3_LPM_DISABLED;
5081 mel = 0;
5082 }
5083
5084 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5085 if (ret)
5086 return ret;
5087 return hub_encoded_timeout;
5088}
5089
5090static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5091 struct usb_device *udev, enum usb3_link_state state)
5092{
5093 struct xhci_hcd *xhci;
5094 u16 mel;
5095
5096 xhci = hcd_to_xhci(hcd);
5097 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5098 !xhci->devs[udev->slot_id])
5099 return 0;
5100
5101 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5102 return xhci_change_max_exit_latency(xhci, udev, mel);
5103}
5104#else /* CONFIG_PM */
5105
5106static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5107 struct usb_device *udev, int enable)
5108{
5109 return 0;
5110}
5111
5112static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5113{
5114 return 0;
5115}
5116
5117static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5118 struct usb_device *udev, enum usb3_link_state state)
5119{
5120 return USB3_LPM_DISABLED;
5121}
5122
5123static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5124 struct usb_device *udev, enum usb3_link_state state)
5125{
5126 return 0;
5127}
5128#endif /* CONFIG_PM */
5129
5130/*-------------------------------------------------------------------------*/
5131
5132/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5133 * internal data structures for the device.
5134 */
5135int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5136 struct usb_tt *tt, gfp_t mem_flags)
5137{
5138 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5139 struct xhci_virt_device *vdev;
5140 struct xhci_command *config_cmd;
5141 struct xhci_input_control_ctx *ctrl_ctx;
5142 struct xhci_slot_ctx *slot_ctx;
5143 unsigned long flags;
5144 unsigned think_time;
5145 int ret;
5146
5147 /* Ignore root hubs */
5148 if (!hdev->parent)
5149 return 0;
5150
5151 vdev = xhci->devs[hdev->slot_id];
5152 if (!vdev) {
5153 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5154 return -EINVAL;
5155 }
5156
5157 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5158 if (!config_cmd)
5159 return -ENOMEM;
5160
5161 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5162 if (!ctrl_ctx) {
5163 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5164 __func__);
5165 xhci_free_command(xhci, config_cmd);
5166 return -ENOMEM;
5167 }
5168
5169 spin_lock_irqsave(&xhci->lock, flags);
5170 if (hdev->speed == USB_SPEED_HIGH &&
5171 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5172 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5173 xhci_free_command(xhci, config_cmd);
5174 spin_unlock_irqrestore(&xhci->lock, flags);
5175 return -ENOMEM;
5176 }
5177
5178 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5179 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5180 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5181 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5182 /*
5183 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5184 * but it may be already set to 1 when setup an xHCI virtual
5185 * device, so clear it anyway.
5186 */
5187 if (tt->multi)
5188 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5189 else if (hdev->speed == USB_SPEED_FULL)
5190 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5191
5192 if (xhci->hci_version > 0x95) {
5193 xhci_dbg(xhci, "xHCI version %x needs hub "
5194 "TT think time and number of ports\n",
5195 (unsigned int) xhci->hci_version);
5196 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5197 /* Set TT think time - convert from ns to FS bit times.
5198 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5199 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5200 *
5201 * xHCI 1.0: this field shall be 0 if the device is not a
5202 * High-spped hub.
5203 */
5204 think_time = tt->think_time;
5205 if (think_time != 0)
5206 think_time = (think_time / 666) - 1;
5207 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5208 slot_ctx->tt_info |=
5209 cpu_to_le32(TT_THINK_TIME(think_time));
5210 } else {
5211 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5212 "TT think time or number of ports\n",
5213 (unsigned int) xhci->hci_version);
5214 }
5215 slot_ctx->dev_state = 0;
5216 spin_unlock_irqrestore(&xhci->lock, flags);
5217
5218 xhci_dbg(xhci, "Set up %s for hub device.\n",
5219 (xhci->hci_version > 0x95) ?
5220 "configure endpoint" : "evaluate context");
5221
5222 /* Issue and wait for the configure endpoint or
5223 * evaluate context command.
5224 */
5225 if (xhci->hci_version > 0x95)
5226 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5227 false, false);
5228 else
5229 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5230 true, false);
5231
5232 xhci_free_command(xhci, config_cmd);
5233 return ret;
5234}
5235EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5236
5237static int xhci_get_frame(struct usb_hcd *hcd)
5238{
5239 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5240 /* EHCI mods by the periodic size. Why? */
5241 return readl(&xhci->run_regs->microframe_index) >> 3;
5242}
5243
5244static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5245{
5246 xhci->usb2_rhub.hcd = hcd;
5247 hcd->speed = HCD_USB2;
5248 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5249 /*
5250 * USB 2.0 roothub under xHCI has an integrated TT,
5251 * (rate matching hub) as opposed to having an OHCI/UHCI
5252 * companion controller.
5253 */
5254 hcd->has_tt = 1;
5255}
5256
5257static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5258{
5259 unsigned int minor_rev;
5260
5261 /*
5262 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5263 * should return 0x31 for sbrn, or that the minor revision
5264 * is a two digit BCD containig minor and sub-minor numbers.
5265 * This was later clarified in xHCI 1.2.
5266 *
5267 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5268 * minor revision set to 0x1 instead of 0x10.
5269 */
5270 if (xhci->usb3_rhub.min_rev == 0x1)
5271 minor_rev = 1;
5272 else
5273 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5274
5275 switch (minor_rev) {
5276 case 2:
5277 hcd->speed = HCD_USB32;
5278 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5279 hcd->self.root_hub->rx_lanes = 2;
5280 hcd->self.root_hub->tx_lanes = 2;
5281 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5282 break;
5283 case 1:
5284 hcd->speed = HCD_USB31;
5285 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5286 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5287 break;
5288 }
5289 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5290 minor_rev, minor_rev ? "Enhanced " : "");
5291
5292 xhci->usb3_rhub.hcd = hcd;
5293}
5294
5295int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5296{
5297 struct xhci_hcd *xhci;
5298 /*
5299 * TODO: Check with DWC3 clients for sysdev according to
5300 * quirks
5301 */
5302 struct device *dev = hcd->self.sysdev;
5303 int retval;
5304
5305 /* Accept arbitrarily long scatter-gather lists */
5306 hcd->self.sg_tablesize = ~0;
5307
5308 /* support to build packet from discontinuous buffers */
5309 hcd->self.no_sg_constraint = 1;
5310
5311 /* XHCI controllers don't stop the ep queue on short packets :| */
5312 hcd->self.no_stop_on_short = 1;
5313
5314 xhci = hcd_to_xhci(hcd);
5315
5316 if (!usb_hcd_is_primary_hcd(hcd)) {
5317 xhci_hcd_init_usb3_data(xhci, hcd);
5318 return 0;
5319 }
5320
5321 mutex_init(&xhci->mutex);
5322 xhci->main_hcd = hcd;
5323 xhci->cap_regs = hcd->regs;
5324 xhci->op_regs = hcd->regs +
5325 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5326 xhci->run_regs = hcd->regs +
5327 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5328 /* Cache read-only capability registers */
5329 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5330 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5331 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5332 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5333 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5334 if (xhci->hci_version > 0x100)
5335 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5336
5337 xhci->quirks |= quirks;
5338
5339 get_quirks(dev, xhci);
5340
5341 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5342 * success event after a short transfer. This quirk will ignore such
5343 * spurious event.
5344 */
5345 if (xhci->hci_version > 0x96)
5346 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5347
5348 /* Make sure the HC is halted. */
5349 retval = xhci_halt(xhci);
5350 if (retval)
5351 return retval;
5352
5353 xhci_zero_64b_regs(xhci);
5354
5355 xhci_dbg(xhci, "Resetting HCD\n");
5356 /* Reset the internal HC memory state and registers. */
5357 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5358 if (retval)
5359 return retval;
5360 xhci_dbg(xhci, "Reset complete\n");
5361
5362 /*
5363 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5364 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5365 * address memory pointers actually. So, this driver clears the AC64
5366 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5367 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5368 */
5369 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5370 xhci->hcc_params &= ~BIT(0);
5371
5372 /* Set dma_mask and coherent_dma_mask to 64-bits,
5373 * if xHC supports 64-bit addressing */
5374 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5375 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5376 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5377 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5378 } else {
5379 /*
5380 * This is to avoid error in cases where a 32-bit USB
5381 * controller is used on a 64-bit capable system.
5382 */
5383 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5384 if (retval)
5385 return retval;
5386 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5387 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5388 }
5389
5390 xhci_dbg(xhci, "Calling HCD init\n");
5391 /* Initialize HCD and host controller data structures. */
5392 retval = xhci_init(hcd);
5393 if (retval)
5394 return retval;
5395 xhci_dbg(xhci, "Called HCD init\n");
5396
5397 if (xhci_hcd_is_usb3(hcd))
5398 xhci_hcd_init_usb3_data(xhci, hcd);
5399 else
5400 xhci_hcd_init_usb2_data(xhci, hcd);
5401
5402 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5403 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5404
5405 return 0;
5406}
5407EXPORT_SYMBOL_GPL(xhci_gen_setup);
5408
5409static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5410 struct usb_host_endpoint *ep)
5411{
5412 struct xhci_hcd *xhci;
5413 struct usb_device *udev;
5414 unsigned int slot_id;
5415 unsigned int ep_index;
5416 unsigned long flags;
5417
5418 xhci = hcd_to_xhci(hcd);
5419
5420 spin_lock_irqsave(&xhci->lock, flags);
5421 udev = (struct usb_device *)ep->hcpriv;
5422 slot_id = udev->slot_id;
5423 ep_index = xhci_get_endpoint_index(&ep->desc);
5424
5425 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5426 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5427 spin_unlock_irqrestore(&xhci->lock, flags);
5428}
5429
5430static const struct hc_driver xhci_hc_driver = {
5431 .description = "xhci-hcd",
5432 .product_desc = "xHCI Host Controller",
5433 .hcd_priv_size = sizeof(struct xhci_hcd),
5434
5435 /*
5436 * generic hardware linkage
5437 */
5438 .irq = xhci_irq,
5439 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5440 HCD_BH,
5441
5442 /*
5443 * basic lifecycle operations
5444 */
5445 .reset = NULL, /* set in xhci_init_driver() */
5446 .start = xhci_run,
5447 .stop = xhci_stop,
5448 .shutdown = xhci_shutdown,
5449
5450 /*
5451 * managing i/o requests and associated device resources
5452 */
5453 .map_urb_for_dma = xhci_map_urb_for_dma,
5454 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5455 .urb_enqueue = xhci_urb_enqueue,
5456 .urb_dequeue = xhci_urb_dequeue,
5457 .alloc_dev = xhci_alloc_dev,
5458 .free_dev = xhci_free_dev,
5459 .alloc_streams = xhci_alloc_streams,
5460 .free_streams = xhci_free_streams,
5461 .add_endpoint = xhci_add_endpoint,
5462 .drop_endpoint = xhci_drop_endpoint,
5463 .endpoint_disable = xhci_endpoint_disable,
5464 .endpoint_reset = xhci_endpoint_reset,
5465 .check_bandwidth = xhci_check_bandwidth,
5466 .reset_bandwidth = xhci_reset_bandwidth,
5467 .address_device = xhci_address_device,
5468 .enable_device = xhci_enable_device,
5469 .update_hub_device = xhci_update_hub_device,
5470 .reset_device = xhci_discover_or_reset_device,
5471
5472 /*
5473 * scheduling support
5474 */
5475 .get_frame_number = xhci_get_frame,
5476
5477 /*
5478 * root hub support
5479 */
5480 .hub_control = xhci_hub_control,
5481 .hub_status_data = xhci_hub_status_data,
5482 .bus_suspend = xhci_bus_suspend,
5483 .bus_resume = xhci_bus_resume,
5484 .get_resuming_ports = xhci_get_resuming_ports,
5485
5486 /*
5487 * call back when device connected and addressed
5488 */
5489 .update_device = xhci_update_device,
5490 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5491 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5492 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5493 .find_raw_port_number = xhci_find_raw_port_number,
5494 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5495};
5496
5497void xhci_init_driver(struct hc_driver *drv,
5498 const struct xhci_driver_overrides *over)
5499{
5500 BUG_ON(!over);
5501
5502 /* Copy the generic table to drv then apply the overrides */
5503 *drv = xhci_hc_driver;
5504
5505 if (over) {
5506 drv->hcd_priv_size += over->extra_priv_size;
5507 if (over->reset)
5508 drv->reset = over->reset;
5509 if (over->start)
5510 drv->start = over->start;
5511 if (over->add_endpoint)
5512 drv->add_endpoint = over->add_endpoint;
5513 if (over->drop_endpoint)
5514 drv->drop_endpoint = over->drop_endpoint;
5515 if (over->check_bandwidth)
5516 drv->check_bandwidth = over->check_bandwidth;
5517 if (over->reset_bandwidth)
5518 drv->reset_bandwidth = over->reset_bandwidth;
5519 if (over->update_hub_device)
5520 drv->update_hub_device = over->update_hub_device;
5521 }
5522}
5523EXPORT_SYMBOL_GPL(xhci_init_driver);
5524
5525MODULE_DESCRIPTION(DRIVER_DESC);
5526MODULE_AUTHOR(DRIVER_AUTHOR);
5527MODULE_LICENSE("GPL");
5528
5529static int __init xhci_hcd_init(void)
5530{
5531 /*
5532 * Check the compiler generated sizes of structures that must be laid
5533 * out in specific ways for hardware access.
5534 */
5535 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5536 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5537 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5538 /* xhci_device_control has eight fields, and also
5539 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5540 */
5541 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5542 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5543 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5544 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5545 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5546 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5547 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5548
5549 if (usb_disabled())
5550 return -ENODEV;
5551
5552 xhci_debugfs_create_root();
5553 xhci_dbc_init();
5554
5555 return 0;
5556}
5557
5558/*
5559 * If an init function is provided, an exit function must also be provided
5560 * to allow module unload.
5561 */
5562static void __exit xhci_hcd_fini(void)
5563{
5564 xhci_debugfs_remove_root();
5565 xhci_dbc_exit();
5566}
5567
5568module_init(xhci_hcd_init);
5569module_exit(xhci_hcd_fini);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/iommu.h>
13#include <linux/iopoll.h>
14#include <linux/irq.h>
15#include <linux/log2.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/slab.h>
19#include <linux/dmi.h>
20#include <linux/dma-mapping.h>
21
22#include "xhci.h"
23#include "xhci-trace.h"
24#include "xhci-debugfs.h"
25#include "xhci-dbgcap.h"
26
27#define DRIVER_AUTHOR "Sarah Sharp"
28#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31
32/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33static int link_quirk;
34module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36
37static unsigned long long quirks;
38module_param(quirks, ullong, S_IRUGO);
39MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40
41static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42{
43 struct xhci_segment *seg = ring->first_seg;
44
45 if (!td || !td->start_seg)
46 return false;
47 do {
48 if (seg == td->start_seg)
49 return true;
50 seg = seg->next;
51 } while (seg && seg != ring->first_seg);
52
53 return false;
54}
55
56/*
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
62 *
63 * Returns negative errno, or zero on success
64 *
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 */
69int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
70{
71 u32 result;
72 int ret;
73
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
76 result == U32_MAX,
77 1, timeout_us);
78 if (result == U32_MAX) /* card removed */
79 return -ENODEV;
80
81 return ret;
82}
83
84/*
85 * xhci_handshake_check_state - same as xhci_handshake but takes an additional
86 * exit_state parameter, and bails out with an error immediately when xhc_state
87 * has exit_state flag set.
88 */
89int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
90 u32 mask, u32 done, int usec, unsigned int exit_state)
91{
92 u32 result;
93 int ret;
94
95 ret = readl_poll_timeout_atomic(ptr, result,
96 (result & mask) == done ||
97 result == U32_MAX ||
98 xhci->xhc_state & exit_state,
99 1, usec);
100
101 if (result == U32_MAX || xhci->xhc_state & exit_state)
102 return -ENODEV;
103
104 return ret;
105}
106
107/*
108 * Disable interrupts and begin the xHCI halting process.
109 */
110void xhci_quiesce(struct xhci_hcd *xhci)
111{
112 u32 halted;
113 u32 cmd;
114 u32 mask;
115
116 mask = ~(XHCI_IRQS);
117 halted = readl(&xhci->op_regs->status) & STS_HALT;
118 if (!halted)
119 mask &= ~CMD_RUN;
120
121 cmd = readl(&xhci->op_regs->command);
122 cmd &= mask;
123 writel(cmd, &xhci->op_regs->command);
124}
125
126/*
127 * Force HC into halt state.
128 *
129 * Disable any IRQs and clear the run/stop bit.
130 * HC will complete any current and actively pipelined transactions, and
131 * should halt within 16 ms of the run/stop bit being cleared.
132 * Read HC Halted bit in the status register to see when the HC is finished.
133 */
134int xhci_halt(struct xhci_hcd *xhci)
135{
136 int ret;
137
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
139 xhci_quiesce(xhci);
140
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
143 if (ret) {
144 xhci_warn(xhci, "Host halt failed, %d\n", ret);
145 return ret;
146 }
147
148 xhci->xhc_state |= XHCI_STATE_HALTED;
149 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
150
151 return ret;
152}
153
154/*
155 * Set the run bit and wait for the host to be running.
156 */
157int xhci_start(struct xhci_hcd *xhci)
158{
159 u32 temp;
160 int ret;
161
162 temp = readl(&xhci->op_regs->command);
163 temp |= (CMD_RUN);
164 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
165 temp);
166 writel(temp, &xhci->op_regs->command);
167
168 /*
169 * Wait for the HCHalted Status bit to be 0 to indicate the host is
170 * running.
171 */
172 ret = xhci_handshake(&xhci->op_regs->status,
173 STS_HALT, 0, XHCI_MAX_HALT_USEC);
174 if (ret == -ETIMEDOUT)
175 xhci_err(xhci, "Host took too long to start, "
176 "waited %u microseconds.\n",
177 XHCI_MAX_HALT_USEC);
178 if (!ret) {
179 /* clear state flags. Including dying, halted or removing */
180 xhci->xhc_state = 0;
181 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
182 }
183
184 return ret;
185}
186
187/*
188 * Reset a halted HC.
189 *
190 * This resets pipelines, timers, counters, state machines, etc.
191 * Transactions will be terminated immediately, and operational registers
192 * will be set to their defaults.
193 */
194int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
195{
196 u32 command;
197 u32 state;
198 int ret;
199
200 state = readl(&xhci->op_regs->status);
201
202 if (state == ~(u32)0) {
203 xhci_warn(xhci, "Host not accessible, reset failed.\n");
204 return -ENODEV;
205 }
206
207 if ((state & STS_HALT) == 0) {
208 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
209 return 0;
210 }
211
212 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
213 command = readl(&xhci->op_regs->command);
214 command |= CMD_RESET;
215 writel(command, &xhci->op_regs->command);
216
217 /* Existing Intel xHCI controllers require a delay of 1 mS,
218 * after setting the CMD_RESET bit, and before accessing any
219 * HC registers. This allows the HC to complete the
220 * reset operation and be ready for HC register access.
221 * Without this delay, the subsequent HC register access,
222 * may result in a system hang very rarely.
223 */
224 if (xhci->quirks & XHCI_INTEL_HOST)
225 udelay(1000);
226
227 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->command,
228 CMD_RESET, 0, timeout_us, XHCI_STATE_REMOVING);
229 if (ret)
230 return ret;
231
232 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
233 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
234
235 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
236 "Wait for controller to be ready for doorbell rings");
237 /*
238 * xHCI cannot write to any doorbells or operational registers other
239 * than status until the "Controller Not Ready" flag is cleared.
240 */
241 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
242
243 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
244 xhci->usb2_rhub.bus_state.suspended_ports = 0;
245 xhci->usb2_rhub.bus_state.resuming_ports = 0;
246 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
247 xhci->usb3_rhub.bus_state.suspended_ports = 0;
248 xhci->usb3_rhub.bus_state.resuming_ports = 0;
249
250 return ret;
251}
252
253static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
254{
255 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
256 struct iommu_domain *domain;
257 int err, i;
258 u64 val;
259 u32 intrs;
260
261 /*
262 * Some Renesas controllers get into a weird state if they are
263 * reset while programmed with 64bit addresses (they will preserve
264 * the top half of the address in internal, non visible
265 * registers). You end up with half the address coming from the
266 * kernel, and the other half coming from the firmware. Also,
267 * changing the programming leads to extra accesses even if the
268 * controller is supposed to be halted. The controller ends up with
269 * a fatal fault, and is then ripe for being properly reset.
270 *
271 * Special care is taken to only apply this if the device is behind
272 * an iommu. Doing anything when there is no iommu is definitely
273 * unsafe...
274 */
275 domain = iommu_get_domain_for_dev(dev);
276 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
277 domain->type == IOMMU_DOMAIN_IDENTITY)
278 return;
279
280 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
281
282 /* Clear HSEIE so that faults do not get signaled */
283 val = readl(&xhci->op_regs->command);
284 val &= ~CMD_HSEIE;
285 writel(val, &xhci->op_regs->command);
286
287 /* Clear HSE (aka FATAL) */
288 val = readl(&xhci->op_regs->status);
289 val |= STS_FATAL;
290 writel(val, &xhci->op_regs->status);
291
292 /* Now zero the registers, and brace for impact */
293 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
294 if (upper_32_bits(val))
295 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
296 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
297 if (upper_32_bits(val))
298 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
299
300 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
301 ARRAY_SIZE(xhci->run_regs->ir_set));
302
303 for (i = 0; i < intrs; i++) {
304 struct xhci_intr_reg __iomem *ir;
305
306 ir = &xhci->run_regs->ir_set[i];
307 val = xhci_read_64(xhci, &ir->erst_base);
308 if (upper_32_bits(val))
309 xhci_write_64(xhci, 0, &ir->erst_base);
310 val= xhci_read_64(xhci, &ir->erst_dequeue);
311 if (upper_32_bits(val))
312 xhci_write_64(xhci, 0, &ir->erst_dequeue);
313 }
314
315 /* Wait for the fault to appear. It will be cleared on reset */
316 err = xhci_handshake(&xhci->op_regs->status,
317 STS_FATAL, STS_FATAL,
318 XHCI_MAX_HALT_USEC);
319 if (!err)
320 xhci_info(xhci, "Fault detected\n");
321}
322
323static int xhci_enable_interrupter(struct xhci_interrupter *ir)
324{
325 u32 iman;
326
327 if (!ir || !ir->ir_set)
328 return -EINVAL;
329
330 iman = readl(&ir->ir_set->irq_pending);
331 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
332
333 return 0;
334}
335
336static int xhci_disable_interrupter(struct xhci_interrupter *ir)
337{
338 u32 iman;
339
340 if (!ir || !ir->ir_set)
341 return -EINVAL;
342
343 iman = readl(&ir->ir_set->irq_pending);
344 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
345
346 return 0;
347}
348
349/* interrupt moderation interval imod_interval in nanoseconds */
350static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
351 u32 imod_interval)
352{
353 u32 imod;
354
355 if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250)
356 return -EINVAL;
357
358 imod = readl(&ir->ir_set->irq_control);
359 imod &= ~ER_IRQ_INTERVAL_MASK;
360 imod |= (imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
361 writel(imod, &ir->ir_set->irq_control);
362
363 return 0;
364}
365
366static void compliance_mode_recovery(struct timer_list *t)
367{
368 struct xhci_hcd *xhci;
369 struct usb_hcd *hcd;
370 struct xhci_hub *rhub;
371 u32 temp;
372 int i;
373
374 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
375 rhub = &xhci->usb3_rhub;
376 hcd = rhub->hcd;
377
378 if (!hcd)
379 return;
380
381 for (i = 0; i < rhub->num_ports; i++) {
382 temp = readl(rhub->ports[i]->addr);
383 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
384 /*
385 * Compliance Mode Detected. Letting USB Core
386 * handle the Warm Reset
387 */
388 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
389 "Compliance mode detected->port %d",
390 i + 1);
391 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
392 "Attempting compliance mode recovery");
393
394 if (hcd->state == HC_STATE_SUSPENDED)
395 usb_hcd_resume_root_hub(hcd);
396
397 usb_hcd_poll_rh_status(hcd);
398 }
399 }
400
401 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
402 mod_timer(&xhci->comp_mode_recovery_timer,
403 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
404}
405
406/*
407 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
408 * that causes ports behind that hardware to enter compliance mode sometimes.
409 * The quirk creates a timer that polls every 2 seconds the link state of
410 * each host controller's port and recovers it by issuing a Warm reset
411 * if Compliance mode is detected, otherwise the port will become "dead" (no
412 * device connections or disconnections will be detected anymore). Becasue no
413 * status event is generated when entering compliance mode (per xhci spec),
414 * this quirk is needed on systems that have the failing hardware installed.
415 */
416static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
417{
418 xhci->port_status_u0 = 0;
419 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
420 0);
421 xhci->comp_mode_recovery_timer.expires = jiffies +
422 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
423
424 add_timer(&xhci->comp_mode_recovery_timer);
425 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
426 "Compliance mode recovery timer initialized");
427}
428
429/*
430 * This function identifies the systems that have installed the SN65LVPE502CP
431 * USB3.0 re-driver and that need the Compliance Mode Quirk.
432 * Systems:
433 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
434 */
435static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
436{
437 const char *dmi_product_name, *dmi_sys_vendor;
438
439 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
440 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
441 if (!dmi_product_name || !dmi_sys_vendor)
442 return false;
443
444 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
445 return false;
446
447 if (strstr(dmi_product_name, "Z420") ||
448 strstr(dmi_product_name, "Z620") ||
449 strstr(dmi_product_name, "Z820") ||
450 strstr(dmi_product_name, "Z1 Workstation"))
451 return true;
452
453 return false;
454}
455
456static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
457{
458 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
459}
460
461
462/*
463 * Initialize memory for HCD and xHC (one-time init).
464 *
465 * Program the PAGESIZE register, initialize the device context array, create
466 * device contexts (?), set up a command ring segment (or two?), create event
467 * ring (one for now).
468 */
469static int xhci_init(struct usb_hcd *hcd)
470{
471 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
472 int retval;
473
474 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
475 spin_lock_init(&xhci->lock);
476 if (xhci->hci_version == 0x95 && link_quirk) {
477 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
478 "QUIRK: Not clearing Link TRB chain bits.");
479 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
480 } else {
481 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
482 "xHCI doesn't need link TRB QUIRK");
483 }
484 retval = xhci_mem_init(xhci, GFP_KERNEL);
485 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
486
487 /* Initializing Compliance Mode Recovery Data If Needed */
488 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
489 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
490 compliance_mode_recovery_timer_init(xhci);
491 }
492
493 return retval;
494}
495
496/*-------------------------------------------------------------------------*/
497
498static int xhci_run_finished(struct xhci_hcd *xhci)
499{
500 struct xhci_interrupter *ir = xhci->interrupters[0];
501 unsigned long flags;
502 u32 temp;
503
504 /*
505 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
506 * Protect the short window before host is running with a lock
507 */
508 spin_lock_irqsave(&xhci->lock, flags);
509
510 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
511 temp = readl(&xhci->op_regs->command);
512 temp |= (CMD_EIE);
513 writel(temp, &xhci->op_regs->command);
514
515 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
516 xhci_enable_interrupter(ir);
517
518 if (xhci_start(xhci)) {
519 xhci_halt(xhci);
520 spin_unlock_irqrestore(&xhci->lock, flags);
521 return -ENODEV;
522 }
523
524 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
525
526 if (xhci->quirks & XHCI_NEC_HOST)
527 xhci_ring_cmd_db(xhci);
528
529 spin_unlock_irqrestore(&xhci->lock, flags);
530
531 return 0;
532}
533
534/*
535 * Start the HC after it was halted.
536 *
537 * This function is called by the USB core when the HC driver is added.
538 * Its opposite is xhci_stop().
539 *
540 * xhci_init() must be called once before this function can be called.
541 * Reset the HC, enable device slot contexts, program DCBAAP, and
542 * set command ring pointer and event ring pointer.
543 *
544 * Setup MSI-X vectors and enable interrupts.
545 */
546int xhci_run(struct usb_hcd *hcd)
547{
548 u64 temp_64;
549 int ret;
550 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
551 struct xhci_interrupter *ir = xhci->interrupters[0];
552 /* Start the xHCI host controller running only after the USB 2.0 roothub
553 * is setup.
554 */
555
556 hcd->uses_new_polling = 1;
557 if (hcd->msi_enabled)
558 ir->ip_autoclear = true;
559
560 if (!usb_hcd_is_primary_hcd(hcd))
561 return xhci_run_finished(xhci);
562
563 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
564
565 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
566 temp_64 &= ERST_PTR_MASK;
567 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
568 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
569
570 xhci_set_interrupter_moderation(ir, xhci->imod_interval);
571
572 if (xhci->quirks & XHCI_NEC_HOST) {
573 struct xhci_command *command;
574
575 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
576 if (!command)
577 return -ENOMEM;
578
579 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
580 TRB_TYPE(TRB_NEC_GET_FW));
581 if (ret)
582 xhci_free_command(xhci, command);
583 }
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
585 "Finished %s for main hcd", __func__);
586
587 xhci_create_dbc_dev(xhci);
588
589 xhci_debugfs_init(xhci);
590
591 if (xhci_has_one_roothub(xhci))
592 return xhci_run_finished(xhci);
593
594 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
595
596 return 0;
597}
598EXPORT_SYMBOL_GPL(xhci_run);
599
600/*
601 * Stop xHCI driver.
602 *
603 * This function is called by the USB core when the HC driver is removed.
604 * Its opposite is xhci_run().
605 *
606 * Disable device contexts, disable IRQs, and quiesce the HC.
607 * Reset the HC, finish any completed transactions, and cleanup memory.
608 */
609void xhci_stop(struct usb_hcd *hcd)
610{
611 u32 temp;
612 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
613 struct xhci_interrupter *ir = xhci->interrupters[0];
614
615 mutex_lock(&xhci->mutex);
616
617 /* Only halt host and free memory after both hcds are removed */
618 if (!usb_hcd_is_primary_hcd(hcd)) {
619 mutex_unlock(&xhci->mutex);
620 return;
621 }
622
623 xhci_remove_dbc_dev(xhci);
624
625 spin_lock_irq(&xhci->lock);
626 xhci->xhc_state |= XHCI_STATE_HALTED;
627 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
628 xhci_halt(xhci);
629 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
630 spin_unlock_irq(&xhci->lock);
631
632 /* Deleting Compliance Mode Recovery Timer */
633 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
634 (!(xhci_all_ports_seen_u0(xhci)))) {
635 del_timer_sync(&xhci->comp_mode_recovery_timer);
636 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
637 "%s: compliance mode recovery timer deleted",
638 __func__);
639 }
640
641 if (xhci->quirks & XHCI_AMD_PLL_FIX)
642 usb_amd_dev_put();
643
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
645 "// Disabling event ring interrupts");
646 temp = readl(&xhci->op_regs->status);
647 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
648 xhci_disable_interrupter(ir);
649
650 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
651 xhci_mem_cleanup(xhci);
652 xhci_debugfs_exit(xhci);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
654 "xhci_stop completed - status = %x",
655 readl(&xhci->op_regs->status));
656 mutex_unlock(&xhci->mutex);
657}
658EXPORT_SYMBOL_GPL(xhci_stop);
659
660/*
661 * Shutdown HC (not bus-specific)
662 *
663 * This is called when the machine is rebooting or halting. We assume that the
664 * machine will be powered off, and the HC's internal state will be reset.
665 * Don't bother to free memory.
666 *
667 * This will only ever be called with the main usb_hcd (the USB3 roothub).
668 */
669void xhci_shutdown(struct usb_hcd *hcd)
670{
671 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
672
673 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
674 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
675
676 /* Don't poll the roothubs after shutdown. */
677 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
678 __func__, hcd->self.busnum);
679 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
680 del_timer_sync(&hcd->rh_timer);
681
682 if (xhci->shared_hcd) {
683 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
684 del_timer_sync(&xhci->shared_hcd->rh_timer);
685 }
686
687 spin_lock_irq(&xhci->lock);
688 xhci_halt(xhci);
689
690 /*
691 * Workaround for spurious wakeps at shutdown with HSW, and for boot
692 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
693 */
694 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
695 xhci->quirks & XHCI_RESET_TO_DEFAULT)
696 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
697
698 spin_unlock_irq(&xhci->lock);
699
700 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
701 "xhci_shutdown completed - status = %x",
702 readl(&xhci->op_regs->status));
703}
704EXPORT_SYMBOL_GPL(xhci_shutdown);
705
706#ifdef CONFIG_PM
707static void xhci_save_registers(struct xhci_hcd *xhci)
708{
709 struct xhci_interrupter *ir;
710 unsigned int i;
711
712 xhci->s3.command = readl(&xhci->op_regs->command);
713 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
714 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
715 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
716
717 /* save both primary and all secondary interrupters */
718 /* fixme, shold we lock to prevent race with remove secondary interrupter? */
719 for (i = 0; i < xhci->max_interrupters; i++) {
720 ir = xhci->interrupters[i];
721 if (!ir)
722 continue;
723
724 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
725 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
726 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
727 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
728 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
729 }
730}
731
732static void xhci_restore_registers(struct xhci_hcd *xhci)
733{
734 struct xhci_interrupter *ir;
735 unsigned int i;
736
737 writel(xhci->s3.command, &xhci->op_regs->command);
738 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
739 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
740 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
741
742 /* FIXME should we lock to protect against freeing of interrupters */
743 for (i = 0; i < xhci->max_interrupters; i++) {
744 ir = xhci->interrupters[i];
745 if (!ir)
746 continue;
747
748 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
749 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
750 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
751 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
752 writel(ir->s3_irq_control, &ir->ir_set->irq_control);
753 }
754}
755
756static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
757{
758 u64 val_64;
759
760 /* step 2: initialize command ring buffer */
761 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
762 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
763 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
764 xhci->cmd_ring->dequeue) &
765 (u64) ~CMD_RING_RSVD_BITS) |
766 xhci->cmd_ring->cycle_state;
767 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
768 "// Setting command ring address to 0x%llx",
769 (long unsigned long) val_64);
770 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
771}
772
773/*
774 * The whole command ring must be cleared to zero when we suspend the host.
775 *
776 * The host doesn't save the command ring pointer in the suspend well, so we
777 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
778 * aligned, because of the reserved bits in the command ring dequeue pointer
779 * register. Therefore, we can't just set the dequeue pointer back in the
780 * middle of the ring (TRBs are 16-byte aligned).
781 */
782static void xhci_clear_command_ring(struct xhci_hcd *xhci)
783{
784 struct xhci_ring *ring;
785 struct xhci_segment *seg;
786
787 ring = xhci->cmd_ring;
788 seg = ring->deq_seg;
789 do {
790 memset(seg->trbs, 0,
791 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
792 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
793 cpu_to_le32(~TRB_CYCLE);
794 seg = seg->next;
795 } while (seg != ring->deq_seg);
796
797 xhci_initialize_ring_info(ring, 1);
798 /*
799 * Reset the hardware dequeue pointer.
800 * Yes, this will need to be re-written after resume, but we're paranoid
801 * and want to make sure the hardware doesn't access bogus memory
802 * because, say, the BIOS or an SMI started the host without changing
803 * the command ring pointers.
804 */
805 xhci_set_cmd_ring_deq(xhci);
806}
807
808/*
809 * Disable port wake bits if do_wakeup is not set.
810 *
811 * Also clear a possible internal port wake state left hanging for ports that
812 * detected termination but never successfully enumerated (trained to 0U).
813 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
814 * at enumeration clears this wake, force one here as well for unconnected ports
815 */
816
817static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
818 struct xhci_hub *rhub,
819 bool do_wakeup)
820{
821 unsigned long flags;
822 u32 t1, t2, portsc;
823 int i;
824
825 spin_lock_irqsave(&xhci->lock, flags);
826
827 for (i = 0; i < rhub->num_ports; i++) {
828 portsc = readl(rhub->ports[i]->addr);
829 t1 = xhci_port_state_to_neutral(portsc);
830 t2 = t1;
831
832 /* clear wake bits if do_wake is not set */
833 if (!do_wakeup)
834 t2 &= ~PORT_WAKE_BITS;
835
836 /* Don't touch csc bit if connected or connect change is set */
837 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
838 t2 |= PORT_CSC;
839
840 if (t1 != t2) {
841 writel(t2, rhub->ports[i]->addr);
842 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
843 rhub->hcd->self.busnum, i + 1, portsc, t2);
844 }
845 }
846 spin_unlock_irqrestore(&xhci->lock, flags);
847}
848
849static bool xhci_pending_portevent(struct xhci_hcd *xhci)
850{
851 struct xhci_port **ports;
852 int port_index;
853 u32 status;
854 u32 portsc;
855
856 status = readl(&xhci->op_regs->status);
857 if (status & STS_EINT)
858 return true;
859 /*
860 * Checking STS_EINT is not enough as there is a lag between a change
861 * bit being set and the Port Status Change Event that it generated
862 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
863 */
864
865 port_index = xhci->usb2_rhub.num_ports;
866 ports = xhci->usb2_rhub.ports;
867 while (port_index--) {
868 portsc = readl(ports[port_index]->addr);
869 if (portsc & PORT_CHANGE_MASK ||
870 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
871 return true;
872 }
873 port_index = xhci->usb3_rhub.num_ports;
874 ports = xhci->usb3_rhub.ports;
875 while (port_index--) {
876 portsc = readl(ports[port_index]->addr);
877 if (portsc & (PORT_CHANGE_MASK | PORT_CAS) ||
878 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
879 return true;
880 }
881 return false;
882}
883
884/*
885 * Stop HC (not bus-specific)
886 *
887 * This is called when the machine transition into S3/S4 mode.
888 *
889 */
890int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
891{
892 int rc = 0;
893 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
894 struct usb_hcd *hcd = xhci_to_hcd(xhci);
895 u32 command;
896 u32 res;
897
898 if (!hcd->state)
899 return 0;
900
901 if (hcd->state != HC_STATE_SUSPENDED ||
902 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
903 return -EINVAL;
904
905 /* Clear root port wake on bits if wakeup not allowed. */
906 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
907 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
908
909 if (!HCD_HW_ACCESSIBLE(hcd))
910 return 0;
911
912 xhci_dbc_suspend(xhci);
913
914 /* Don't poll the roothubs on bus suspend. */
915 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
916 __func__, hcd->self.busnum);
917 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
918 del_timer_sync(&hcd->rh_timer);
919 if (xhci->shared_hcd) {
920 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
921 del_timer_sync(&xhci->shared_hcd->rh_timer);
922 }
923
924 if (xhci->quirks & XHCI_SUSPEND_DELAY)
925 usleep_range(1000, 1500);
926
927 spin_lock_irq(&xhci->lock);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
929 if (xhci->shared_hcd)
930 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
931 /* step 1: stop endpoint */
932 /* skipped assuming that port suspend has done */
933
934 /* step 2: clear Run/Stop bit */
935 command = readl(&xhci->op_regs->command);
936 command &= ~CMD_RUN;
937 writel(command, &xhci->op_regs->command);
938
939 /* Some chips from Fresco Logic need an extraordinary delay */
940 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
941
942 if (xhci_handshake(&xhci->op_regs->status,
943 STS_HALT, STS_HALT, delay)) {
944 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
945 spin_unlock_irq(&xhci->lock);
946 return -ETIMEDOUT;
947 }
948 xhci_clear_command_ring(xhci);
949
950 /* step 3: save registers */
951 xhci_save_registers(xhci);
952
953 /* step 4: set CSS flag */
954 command = readl(&xhci->op_regs->command);
955 command |= CMD_CSS;
956 writel(command, &xhci->op_regs->command);
957 xhci->broken_suspend = 0;
958 if (xhci_handshake(&xhci->op_regs->status,
959 STS_SAVE, 0, 20 * 1000)) {
960 /*
961 * AMD SNPS xHC 3.0 occasionally does not clear the
962 * SSS bit of USBSTS and when driver tries to poll
963 * to see if the xHC clears BIT(8) which never happens
964 * and driver assumes that controller is not responding
965 * and times out. To workaround this, its good to check
966 * if SRE and HCE bits are not set (as per xhci
967 * Section 5.4.2) and bypass the timeout.
968 */
969 res = readl(&xhci->op_regs->status);
970 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
971 (((res & STS_SRE) == 0) &&
972 ((res & STS_HCE) == 0))) {
973 xhci->broken_suspend = 1;
974 } else {
975 xhci_warn(xhci, "WARN: xHC save state timeout\n");
976 spin_unlock_irq(&xhci->lock);
977 return -ETIMEDOUT;
978 }
979 }
980 spin_unlock_irq(&xhci->lock);
981
982 /*
983 * Deleting Compliance Mode Recovery Timer because the xHCI Host
984 * is about to be suspended.
985 */
986 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
987 (!(xhci_all_ports_seen_u0(xhci)))) {
988 del_timer_sync(&xhci->comp_mode_recovery_timer);
989 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
990 "%s: compliance mode recovery timer deleted",
991 __func__);
992 }
993
994 return rc;
995}
996EXPORT_SYMBOL_GPL(xhci_suspend);
997
998/*
999 * start xHC (not bus-specific)
1000 *
1001 * This is called when the machine transition from S3/S4 mode.
1002 *
1003 */
1004int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg)
1005{
1006 bool hibernated = (msg.event == PM_EVENT_RESTORE);
1007 u32 command, temp = 0;
1008 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1009 int retval = 0;
1010 bool comp_timer_running = false;
1011 bool pending_portevent = false;
1012 bool suspended_usb3_devs = false;
1013 bool reinit_xhc = false;
1014
1015 if (!hcd->state)
1016 return 0;
1017
1018 /* Wait a bit if either of the roothubs need to settle from the
1019 * transition into bus suspend.
1020 */
1021
1022 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1023 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1024 msleep(100);
1025
1026 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1027 if (xhci->shared_hcd)
1028 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1029
1030 spin_lock_irq(&xhci->lock);
1031
1032 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1033 reinit_xhc = true;
1034
1035 if (!reinit_xhc) {
1036 /*
1037 * Some controllers might lose power during suspend, so wait
1038 * for controller not ready bit to clear, just as in xHC init.
1039 */
1040 retval = xhci_handshake(&xhci->op_regs->status,
1041 STS_CNR, 0, 10 * 1000 * 1000);
1042 if (retval) {
1043 xhci_warn(xhci, "Controller not ready at resume %d\n",
1044 retval);
1045 spin_unlock_irq(&xhci->lock);
1046 return retval;
1047 }
1048 /* step 1: restore register */
1049 xhci_restore_registers(xhci);
1050 /* step 2: initialize command ring buffer */
1051 xhci_set_cmd_ring_deq(xhci);
1052 /* step 3: restore state and start state*/
1053 /* step 3: set CRS flag */
1054 command = readl(&xhci->op_regs->command);
1055 command |= CMD_CRS;
1056 writel(command, &xhci->op_regs->command);
1057 /*
1058 * Some controllers take up to 55+ ms to complete the controller
1059 * restore so setting the timeout to 100ms. Xhci specification
1060 * doesn't mention any timeout value.
1061 */
1062 if (xhci_handshake(&xhci->op_regs->status,
1063 STS_RESTORE, 0, 100 * 1000)) {
1064 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1065 spin_unlock_irq(&xhci->lock);
1066 return -ETIMEDOUT;
1067 }
1068 }
1069
1070 temp = readl(&xhci->op_regs->status);
1071
1072 /* re-initialize the HC on Restore Error, or Host Controller Error */
1073 if ((temp & (STS_SRE | STS_HCE)) &&
1074 !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1075 reinit_xhc = true;
1076 if (!xhci->broken_suspend)
1077 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1078 }
1079
1080 if (reinit_xhc) {
1081 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1082 !(xhci_all_ports_seen_u0(xhci))) {
1083 del_timer_sync(&xhci->comp_mode_recovery_timer);
1084 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1085 "Compliance Mode Recovery Timer deleted!");
1086 }
1087
1088 /* Let the USB core know _both_ roothubs lost power. */
1089 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1090 if (xhci->shared_hcd)
1091 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1092
1093 xhci_dbg(xhci, "Stop HCD\n");
1094 xhci_halt(xhci);
1095 xhci_zero_64b_regs(xhci);
1096 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1097 spin_unlock_irq(&xhci->lock);
1098 if (retval)
1099 return retval;
1100
1101 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1102 temp = readl(&xhci->op_regs->status);
1103 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1104 xhci_disable_interrupter(xhci->interrupters[0]);
1105
1106 xhci_dbg(xhci, "cleaning up memory\n");
1107 xhci_mem_cleanup(xhci);
1108 xhci_debugfs_exit(xhci);
1109 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1110 readl(&xhci->op_regs->status));
1111
1112 /* USB core calls the PCI reinit and start functions twice:
1113 * first with the primary HCD, and then with the secondary HCD.
1114 * If we don't do the same, the host will never be started.
1115 */
1116 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1117 retval = xhci_init(hcd);
1118 if (retval)
1119 return retval;
1120 comp_timer_running = true;
1121
1122 xhci_dbg(xhci, "Start the primary HCD\n");
1123 retval = xhci_run(hcd);
1124 if (!retval && xhci->shared_hcd) {
1125 xhci_dbg(xhci, "Start the secondary HCD\n");
1126 retval = xhci_run(xhci->shared_hcd);
1127 }
1128
1129 hcd->state = HC_STATE_SUSPENDED;
1130 if (xhci->shared_hcd)
1131 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1132 goto done;
1133 }
1134
1135 /* step 4: set Run/Stop bit */
1136 command = readl(&xhci->op_regs->command);
1137 command |= CMD_RUN;
1138 writel(command, &xhci->op_regs->command);
1139 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1140 0, 250 * 1000);
1141
1142 /* step 5: walk topology and initialize portsc,
1143 * portpmsc and portli
1144 */
1145 /* this is done in bus_resume */
1146
1147 /* step 6: restart each of the previously
1148 * Running endpoints by ringing their doorbells
1149 */
1150
1151 spin_unlock_irq(&xhci->lock);
1152
1153 xhci_dbc_resume(xhci);
1154
1155 done:
1156 if (retval == 0) {
1157 /*
1158 * Resume roothubs only if there are pending events.
1159 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1160 * the first wake signalling failed, give it that chance if
1161 * there are suspended USB 3 devices.
1162 */
1163 if (xhci->usb3_rhub.bus_state.suspended_ports ||
1164 xhci->usb3_rhub.bus_state.bus_suspended)
1165 suspended_usb3_devs = true;
1166
1167 pending_portevent = xhci_pending_portevent(xhci);
1168
1169 if (suspended_usb3_devs && !pending_portevent &&
1170 msg.event == PM_EVENT_AUTO_RESUME) {
1171 msleep(120);
1172 pending_portevent = xhci_pending_portevent(xhci);
1173 }
1174
1175 if (pending_portevent) {
1176 if (xhci->shared_hcd)
1177 usb_hcd_resume_root_hub(xhci->shared_hcd);
1178 usb_hcd_resume_root_hub(hcd);
1179 }
1180 }
1181 /*
1182 * If system is subject to the Quirk, Compliance Mode Timer needs to
1183 * be re-initialized Always after a system resume. Ports are subject
1184 * to suffer the Compliance Mode issue again. It doesn't matter if
1185 * ports have entered previously to U0 before system's suspension.
1186 */
1187 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1188 compliance_mode_recovery_timer_init(xhci);
1189
1190 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1191 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1192
1193 /* Re-enable port polling. */
1194 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1195 __func__, hcd->self.busnum);
1196 if (xhci->shared_hcd) {
1197 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1198 usb_hcd_poll_rh_status(xhci->shared_hcd);
1199 }
1200 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1201 usb_hcd_poll_rh_status(hcd);
1202
1203 return retval;
1204}
1205EXPORT_SYMBOL_GPL(xhci_resume);
1206#endif /* CONFIG_PM */
1207
1208/*-------------------------------------------------------------------------*/
1209
1210static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1211{
1212 void *temp;
1213 int ret = 0;
1214 unsigned int buf_len;
1215 enum dma_data_direction dir;
1216
1217 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1218 buf_len = urb->transfer_buffer_length;
1219
1220 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1221 dev_to_node(hcd->self.sysdev));
1222 if (!temp)
1223 return -ENOMEM;
1224
1225 if (usb_urb_dir_out(urb))
1226 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1227 temp, buf_len, 0);
1228
1229 urb->transfer_buffer = temp;
1230 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1231 urb->transfer_buffer,
1232 urb->transfer_buffer_length,
1233 dir);
1234
1235 if (dma_mapping_error(hcd->self.sysdev,
1236 urb->transfer_dma)) {
1237 ret = -EAGAIN;
1238 kfree(temp);
1239 } else {
1240 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1241 }
1242
1243 return ret;
1244}
1245
1246static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1247 struct urb *urb)
1248{
1249 bool ret = false;
1250 unsigned int i;
1251 unsigned int len = 0;
1252 unsigned int trb_size;
1253 unsigned int max_pkt;
1254 struct scatterlist *sg;
1255 struct scatterlist *tail_sg;
1256
1257 tail_sg = urb->sg;
1258 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1259
1260 if (!urb->num_sgs)
1261 return ret;
1262
1263 if (urb->dev->speed >= USB_SPEED_SUPER)
1264 trb_size = TRB_CACHE_SIZE_SS;
1265 else
1266 trb_size = TRB_CACHE_SIZE_HS;
1267
1268 if (urb->transfer_buffer_length != 0 &&
1269 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1270 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1271 len = len + sg->length;
1272 if (i > trb_size - 2) {
1273 len = len - tail_sg->length;
1274 if (len < max_pkt) {
1275 ret = true;
1276 break;
1277 }
1278
1279 tail_sg = sg_next(tail_sg);
1280 }
1281 }
1282 }
1283 return ret;
1284}
1285
1286static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1287{
1288 unsigned int len;
1289 unsigned int buf_len;
1290 enum dma_data_direction dir;
1291
1292 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1293
1294 buf_len = urb->transfer_buffer_length;
1295
1296 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1297 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1298 dma_unmap_single(hcd->self.sysdev,
1299 urb->transfer_dma,
1300 urb->transfer_buffer_length,
1301 dir);
1302
1303 if (usb_urb_dir_in(urb)) {
1304 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1305 urb->transfer_buffer,
1306 buf_len,
1307 0);
1308 if (len != buf_len) {
1309 xhci_dbg(hcd_to_xhci(hcd),
1310 "Copy from tmp buf to urb sg list failed\n");
1311 urb->actual_length = len;
1312 }
1313 }
1314 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1315 kfree(urb->transfer_buffer);
1316 urb->transfer_buffer = NULL;
1317}
1318
1319/*
1320 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1321 * we'll copy the actual data into the TRB address register. This is limited to
1322 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1323 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1324 */
1325static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1326 gfp_t mem_flags)
1327{
1328 struct xhci_hcd *xhci;
1329
1330 xhci = hcd_to_xhci(hcd);
1331
1332 if (xhci_urb_suitable_for_idt(urb))
1333 return 0;
1334
1335 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1336 if (xhci_urb_temp_buffer_required(hcd, urb))
1337 return xhci_map_temp_buffer(hcd, urb);
1338 }
1339 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1340}
1341
1342static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1343{
1344 struct xhci_hcd *xhci;
1345 bool unmap_temp_buf = false;
1346
1347 xhci = hcd_to_xhci(hcd);
1348
1349 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1350 unmap_temp_buf = true;
1351
1352 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1353 xhci_unmap_temp_buf(hcd, urb);
1354 else
1355 usb_hcd_unmap_urb_for_dma(hcd, urb);
1356}
1357
1358/**
1359 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1360 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1361 * value to right shift 1 for the bitmask.
1362 *
1363 * Index = (epnum * 2) + direction - 1,
1364 * where direction = 0 for OUT, 1 for IN.
1365 * For control endpoints, the IN index is used (OUT index is unused), so
1366 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1367 */
1368unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1369{
1370 unsigned int index;
1371 if (usb_endpoint_xfer_control(desc))
1372 index = (unsigned int) (usb_endpoint_num(desc)*2);
1373 else
1374 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1375 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1376 return index;
1377}
1378EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1379
1380/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1381 * address from the XHCI endpoint index.
1382 */
1383static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1384{
1385 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1386 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1387 return direction | number;
1388}
1389
1390/* Find the flag for this endpoint (for use in the control context). Use the
1391 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1392 * bit 1, etc.
1393 */
1394static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1395{
1396 return 1 << (xhci_get_endpoint_index(desc) + 1);
1397}
1398
1399/* Compute the last valid endpoint context index. Basically, this is the
1400 * endpoint index plus one. For slot contexts with more than valid endpoint,
1401 * we find the most significant bit set in the added contexts flags.
1402 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1403 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1404 */
1405unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1406{
1407 return fls(added_ctxs) - 1;
1408}
1409
1410/* Returns 1 if the arguments are OK;
1411 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1412 */
1413static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1414 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1415 const char *func) {
1416 struct xhci_hcd *xhci;
1417 struct xhci_virt_device *virt_dev;
1418
1419 if (!hcd || (check_ep && !ep) || !udev) {
1420 pr_debug("xHCI %s called with invalid args\n", func);
1421 return -EINVAL;
1422 }
1423 if (!udev->parent) {
1424 pr_debug("xHCI %s called for root hub\n", func);
1425 return 0;
1426 }
1427
1428 xhci = hcd_to_xhci(hcd);
1429 if (check_virt_dev) {
1430 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1431 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1432 func);
1433 return -EINVAL;
1434 }
1435
1436 virt_dev = xhci->devs[udev->slot_id];
1437 if (virt_dev->udev != udev) {
1438 xhci_dbg(xhci, "xHCI %s called with udev and "
1439 "virt_dev does not match\n", func);
1440 return -EINVAL;
1441 }
1442 }
1443
1444 if (xhci->xhc_state & XHCI_STATE_HALTED)
1445 return -ENODEV;
1446
1447 return 1;
1448}
1449
1450static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1451 struct usb_device *udev, struct xhci_command *command,
1452 bool ctx_change, bool must_succeed);
1453
1454/*
1455 * Full speed devices may have a max packet size greater than 8 bytes, but the
1456 * USB core doesn't know that until it reads the first 8 bytes of the
1457 * descriptor. If the usb_device's max packet size changes after that point,
1458 * we need to issue an evaluate context command and wait on it.
1459 */
1460static int xhci_check_ep0_maxpacket(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
1461{
1462 struct xhci_input_control_ctx *ctrl_ctx;
1463 struct xhci_ep_ctx *ep_ctx;
1464 struct xhci_command *command;
1465 int max_packet_size;
1466 int hw_max_packet_size;
1467 int ret = 0;
1468
1469 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, 0);
1470 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1471 max_packet_size = usb_endpoint_maxp(&vdev->udev->ep0.desc);
1472
1473 if (hw_max_packet_size == max_packet_size)
1474 return 0;
1475
1476 switch (max_packet_size) {
1477 case 8: case 16: case 32: case 64: case 9:
1478 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1479 "Max Packet Size for ep 0 changed.");
1480 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1481 "Max packet size in usb_device = %d",
1482 max_packet_size);
1483 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1484 "Max packet size in xHCI HW = %d",
1485 hw_max_packet_size);
1486 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1487 "Issuing evaluate context command.");
1488
1489 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1490 if (!command)
1491 return -ENOMEM;
1492
1493 command->in_ctx = vdev->in_ctx;
1494 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1495 if (!ctrl_ctx) {
1496 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1497 __func__);
1498 ret = -ENOMEM;
1499 break;
1500 }
1501 /* Set up the modified control endpoint 0 */
1502 xhci_endpoint_copy(xhci, vdev->in_ctx, vdev->out_ctx, 0);
1503
1504 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, 0);
1505 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1506 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1507 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1508
1509 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1510 ctrl_ctx->drop_flags = 0;
1511
1512 ret = xhci_configure_endpoint(xhci, vdev->udev, command,
1513 true, false);
1514 /* Clean up the input context for later use by bandwidth functions */
1515 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1516 break;
1517 default:
1518 dev_dbg(&vdev->udev->dev, "incorrect max packet size %d for ep0\n",
1519 max_packet_size);
1520 return -EINVAL;
1521 }
1522
1523 kfree(command->completion);
1524 kfree(command);
1525
1526 return ret;
1527}
1528
1529/*
1530 * non-error returns are a promise to giveback() the urb later
1531 * we drop ownership so next owner (or urb unlink) can get it
1532 */
1533static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1534{
1535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1536 unsigned long flags;
1537 int ret = 0;
1538 unsigned int slot_id, ep_index;
1539 unsigned int *ep_state;
1540 struct urb_priv *urb_priv;
1541 int num_tds;
1542
1543 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1544
1545 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1546 num_tds = urb->number_of_packets;
1547 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1548 urb->transfer_buffer_length > 0 &&
1549 urb->transfer_flags & URB_ZERO_PACKET &&
1550 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1551 num_tds = 2;
1552 else
1553 num_tds = 1;
1554
1555 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1556 if (!urb_priv)
1557 return -ENOMEM;
1558
1559 urb_priv->num_tds = num_tds;
1560 urb_priv->num_tds_done = 0;
1561 urb->hcpriv = urb_priv;
1562
1563 trace_xhci_urb_enqueue(urb);
1564
1565 spin_lock_irqsave(&xhci->lock, flags);
1566
1567 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1568 true, true, __func__);
1569 if (ret <= 0) {
1570 ret = ret ? ret : -EINVAL;
1571 goto free_priv;
1572 }
1573
1574 slot_id = urb->dev->slot_id;
1575
1576 if (!HCD_HW_ACCESSIBLE(hcd)) {
1577 ret = -ESHUTDOWN;
1578 goto free_priv;
1579 }
1580
1581 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1582 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1583 ret = -ENODEV;
1584 goto free_priv;
1585 }
1586
1587 if (xhci->xhc_state & XHCI_STATE_DYING) {
1588 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1589 urb->ep->desc.bEndpointAddress, urb);
1590 ret = -ESHUTDOWN;
1591 goto free_priv;
1592 }
1593
1594 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1595
1596 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1597 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1598 *ep_state);
1599 ret = -EINVAL;
1600 goto free_priv;
1601 }
1602 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1603 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1604 ret = -EINVAL;
1605 goto free_priv;
1606 }
1607
1608 switch (usb_endpoint_type(&urb->ep->desc)) {
1609
1610 case USB_ENDPOINT_XFER_CONTROL:
1611 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1612 slot_id, ep_index);
1613 break;
1614 case USB_ENDPOINT_XFER_BULK:
1615 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1616 slot_id, ep_index);
1617 break;
1618 case USB_ENDPOINT_XFER_INT:
1619 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1620 slot_id, ep_index);
1621 break;
1622 case USB_ENDPOINT_XFER_ISOC:
1623 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1624 slot_id, ep_index);
1625 }
1626
1627 if (ret) {
1628free_priv:
1629 xhci_urb_free_priv(urb_priv);
1630 urb->hcpriv = NULL;
1631 }
1632 spin_unlock_irqrestore(&xhci->lock, flags);
1633 return ret;
1634}
1635
1636/*
1637 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1638 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1639 * should pick up where it left off in the TD, unless a Set Transfer Ring
1640 * Dequeue Pointer is issued.
1641 *
1642 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1643 * the ring. Since the ring is a contiguous structure, they can't be physically
1644 * removed. Instead, there are two options:
1645 *
1646 * 1) If the HC is in the middle of processing the URB to be canceled, we
1647 * simply move the ring's dequeue pointer past those TRBs using the Set
1648 * Transfer Ring Dequeue Pointer command. This will be the common case,
1649 * when drivers timeout on the last submitted URB and attempt to cancel.
1650 *
1651 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1652 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1653 * HC will need to invalidate the any TRBs it has cached after the stop
1654 * endpoint command, as noted in the xHCI 0.95 errata.
1655 *
1656 * 3) The TD may have completed by the time the Stop Endpoint Command
1657 * completes, so software needs to handle that case too.
1658 *
1659 * This function should protect against the TD enqueueing code ringing the
1660 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1661 * It also needs to account for multiple cancellations on happening at the same
1662 * time for the same endpoint.
1663 *
1664 * Note that this function can be called in any context, or so says
1665 * usb_hcd_unlink_urb()
1666 */
1667static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1668{
1669 unsigned long flags;
1670 int ret, i;
1671 u32 temp;
1672 struct xhci_hcd *xhci;
1673 struct urb_priv *urb_priv;
1674 struct xhci_td *td;
1675 unsigned int ep_index;
1676 struct xhci_ring *ep_ring;
1677 struct xhci_virt_ep *ep;
1678 struct xhci_command *command;
1679 struct xhci_virt_device *vdev;
1680
1681 xhci = hcd_to_xhci(hcd);
1682 spin_lock_irqsave(&xhci->lock, flags);
1683
1684 trace_xhci_urb_dequeue(urb);
1685
1686 /* Make sure the URB hasn't completed or been unlinked already */
1687 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1688 if (ret)
1689 goto done;
1690
1691 /* give back URB now if we can't queue it for cancel */
1692 vdev = xhci->devs[urb->dev->slot_id];
1693 urb_priv = urb->hcpriv;
1694 if (!vdev || !urb_priv)
1695 goto err_giveback;
1696
1697 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1698 ep = &vdev->eps[ep_index];
1699 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1700 if (!ep || !ep_ring)
1701 goto err_giveback;
1702
1703 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1704 temp = readl(&xhci->op_regs->status);
1705 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1706 xhci_hc_died(xhci);
1707 goto done;
1708 }
1709
1710 /*
1711 * check ring is not re-allocated since URB was enqueued. If it is, then
1712 * make sure none of the ring related pointers in this URB private data
1713 * are touched, such as td_list, otherwise we overwrite freed data
1714 */
1715 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1716 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1717 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1718 td = &urb_priv->td[i];
1719 if (!list_empty(&td->cancelled_td_list))
1720 list_del_init(&td->cancelled_td_list);
1721 }
1722 goto err_giveback;
1723 }
1724
1725 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1726 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1727 "HC halted, freeing TD manually.");
1728 for (i = urb_priv->num_tds_done;
1729 i < urb_priv->num_tds;
1730 i++) {
1731 td = &urb_priv->td[i];
1732 if (!list_empty(&td->td_list))
1733 list_del_init(&td->td_list);
1734 if (!list_empty(&td->cancelled_td_list))
1735 list_del_init(&td->cancelled_td_list);
1736 }
1737 goto err_giveback;
1738 }
1739
1740 i = urb_priv->num_tds_done;
1741 if (i < urb_priv->num_tds)
1742 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1743 "Cancel URB %p, dev %s, ep 0x%x, "
1744 "starting at offset 0x%llx",
1745 urb, urb->dev->devpath,
1746 urb->ep->desc.bEndpointAddress,
1747 (unsigned long long) xhci_trb_virt_to_dma(
1748 urb_priv->td[i].start_seg,
1749 urb_priv->td[i].first_trb));
1750
1751 for (; i < urb_priv->num_tds; i++) {
1752 td = &urb_priv->td[i];
1753 /* TD can already be on cancelled list if ep halted on it */
1754 if (list_empty(&td->cancelled_td_list)) {
1755 td->cancel_status = TD_DIRTY;
1756 list_add_tail(&td->cancelled_td_list,
1757 &ep->cancelled_td_list);
1758 }
1759 }
1760
1761 /* Queue a stop endpoint command, but only if this is
1762 * the first cancellation to be handled.
1763 */
1764 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1765 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1766 if (!command) {
1767 ret = -ENOMEM;
1768 goto done;
1769 }
1770 ep->ep_state |= EP_STOP_CMD_PENDING;
1771 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1772 ep_index, 0);
1773 xhci_ring_cmd_db(xhci);
1774 }
1775done:
1776 spin_unlock_irqrestore(&xhci->lock, flags);
1777 return ret;
1778
1779err_giveback:
1780 if (urb_priv)
1781 xhci_urb_free_priv(urb_priv);
1782 usb_hcd_unlink_urb_from_ep(hcd, urb);
1783 spin_unlock_irqrestore(&xhci->lock, flags);
1784 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1785 return ret;
1786}
1787
1788/* Drop an endpoint from a new bandwidth configuration for this device.
1789 * Only one call to this function is allowed per endpoint before
1790 * check_bandwidth() or reset_bandwidth() must be called.
1791 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1792 * add the endpoint to the schedule with possibly new parameters denoted by a
1793 * different endpoint descriptor in usb_host_endpoint.
1794 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1795 * not allowed.
1796 *
1797 * The USB core will not allow URBs to be queued to an endpoint that is being
1798 * disabled, so there's no need for mutual exclusion to protect
1799 * the xhci->devs[slot_id] structure.
1800 */
1801int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1802 struct usb_host_endpoint *ep)
1803{
1804 struct xhci_hcd *xhci;
1805 struct xhci_container_ctx *in_ctx, *out_ctx;
1806 struct xhci_input_control_ctx *ctrl_ctx;
1807 unsigned int ep_index;
1808 struct xhci_ep_ctx *ep_ctx;
1809 u32 drop_flag;
1810 u32 new_add_flags, new_drop_flags;
1811 int ret;
1812
1813 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1814 if (ret <= 0)
1815 return ret;
1816 xhci = hcd_to_xhci(hcd);
1817 if (xhci->xhc_state & XHCI_STATE_DYING)
1818 return -ENODEV;
1819
1820 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1821 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1822 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1823 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1824 __func__, drop_flag);
1825 return 0;
1826 }
1827
1828 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1829 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1830 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1831 if (!ctrl_ctx) {
1832 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1833 __func__);
1834 return 0;
1835 }
1836
1837 ep_index = xhci_get_endpoint_index(&ep->desc);
1838 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1839 /* If the HC already knows the endpoint is disabled,
1840 * or the HCD has noted it is disabled, ignore this request
1841 */
1842 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1843 le32_to_cpu(ctrl_ctx->drop_flags) &
1844 xhci_get_endpoint_flag(&ep->desc)) {
1845 /* Do not warn when called after a usb_device_reset */
1846 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1847 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1848 __func__, ep);
1849 return 0;
1850 }
1851
1852 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1853 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1854
1855 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1856 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1857
1858 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1859
1860 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1861
1862 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1863 (unsigned int) ep->desc.bEndpointAddress,
1864 udev->slot_id,
1865 (unsigned int) new_drop_flags,
1866 (unsigned int) new_add_flags);
1867 return 0;
1868}
1869EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1870
1871/* Add an endpoint to a new possible bandwidth configuration for this device.
1872 * Only one call to this function is allowed per endpoint before
1873 * check_bandwidth() or reset_bandwidth() must be called.
1874 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1875 * add the endpoint to the schedule with possibly new parameters denoted by a
1876 * different endpoint descriptor in usb_host_endpoint.
1877 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1878 * not allowed.
1879 *
1880 * The USB core will not allow URBs to be queued to an endpoint until the
1881 * configuration or alt setting is installed in the device, so there's no need
1882 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1883 */
1884int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1885 struct usb_host_endpoint *ep)
1886{
1887 struct xhci_hcd *xhci;
1888 struct xhci_container_ctx *in_ctx;
1889 unsigned int ep_index;
1890 struct xhci_input_control_ctx *ctrl_ctx;
1891 struct xhci_ep_ctx *ep_ctx;
1892 u32 added_ctxs;
1893 u32 new_add_flags, new_drop_flags;
1894 struct xhci_virt_device *virt_dev;
1895 int ret = 0;
1896
1897 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1898 if (ret <= 0) {
1899 /* So we won't queue a reset ep command for a root hub */
1900 ep->hcpriv = NULL;
1901 return ret;
1902 }
1903 xhci = hcd_to_xhci(hcd);
1904 if (xhci->xhc_state & XHCI_STATE_DYING)
1905 return -ENODEV;
1906
1907 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1908 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1909 /* FIXME when we have to issue an evaluate endpoint command to
1910 * deal with ep0 max packet size changing once we get the
1911 * descriptors
1912 */
1913 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1914 __func__, added_ctxs);
1915 return 0;
1916 }
1917
1918 virt_dev = xhci->devs[udev->slot_id];
1919 in_ctx = virt_dev->in_ctx;
1920 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1921 if (!ctrl_ctx) {
1922 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1923 __func__);
1924 return 0;
1925 }
1926
1927 ep_index = xhci_get_endpoint_index(&ep->desc);
1928 /* If this endpoint is already in use, and the upper layers are trying
1929 * to add it again without dropping it, reject the addition.
1930 */
1931 if (virt_dev->eps[ep_index].ring &&
1932 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1933 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1934 "without dropping it.\n",
1935 (unsigned int) ep->desc.bEndpointAddress);
1936 return -EINVAL;
1937 }
1938
1939 /* If the HCD has already noted the endpoint is enabled,
1940 * ignore this request.
1941 */
1942 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1943 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1944 __func__, ep);
1945 return 0;
1946 }
1947
1948 /*
1949 * Configuration and alternate setting changes must be done in
1950 * process context, not interrupt context (or so documenation
1951 * for usb_set_interface() and usb_set_configuration() claim).
1952 */
1953 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1954 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1955 __func__, ep->desc.bEndpointAddress);
1956 return -ENOMEM;
1957 }
1958
1959 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1960 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1961
1962 /* If xhci_endpoint_disable() was called for this endpoint, but the
1963 * xHC hasn't been notified yet through the check_bandwidth() call,
1964 * this re-adds a new state for the endpoint from the new endpoint
1965 * descriptors. We must drop and re-add this endpoint, so we leave the
1966 * drop flags alone.
1967 */
1968 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1969
1970 /* Store the usb_device pointer for later use */
1971 ep->hcpriv = udev;
1972
1973 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1974 trace_xhci_add_endpoint(ep_ctx);
1975
1976 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1977 (unsigned int) ep->desc.bEndpointAddress,
1978 udev->slot_id,
1979 (unsigned int) new_drop_flags,
1980 (unsigned int) new_add_flags);
1981 return 0;
1982}
1983EXPORT_SYMBOL_GPL(xhci_add_endpoint);
1984
1985static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1986{
1987 struct xhci_input_control_ctx *ctrl_ctx;
1988 struct xhci_ep_ctx *ep_ctx;
1989 struct xhci_slot_ctx *slot_ctx;
1990 int i;
1991
1992 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1993 if (!ctrl_ctx) {
1994 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1995 __func__);
1996 return;
1997 }
1998
1999 /* When a device's add flag and drop flag are zero, any subsequent
2000 * configure endpoint command will leave that endpoint's state
2001 * untouched. Make sure we don't leave any old state in the input
2002 * endpoint contexts.
2003 */
2004 ctrl_ctx->drop_flags = 0;
2005 ctrl_ctx->add_flags = 0;
2006 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2007 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2008 /* Endpoint 0 is always valid */
2009 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2010 for (i = 1; i < 31; i++) {
2011 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2012 ep_ctx->ep_info = 0;
2013 ep_ctx->ep_info2 = 0;
2014 ep_ctx->deq = 0;
2015 ep_ctx->tx_info = 0;
2016 }
2017}
2018
2019static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2020 struct usb_device *udev, u32 *cmd_status)
2021{
2022 int ret;
2023
2024 switch (*cmd_status) {
2025 case COMP_COMMAND_ABORTED:
2026 case COMP_COMMAND_RING_STOPPED:
2027 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2028 ret = -ETIME;
2029 break;
2030 case COMP_RESOURCE_ERROR:
2031 dev_warn(&udev->dev,
2032 "Not enough host controller resources for new device state.\n");
2033 ret = -ENOMEM;
2034 /* FIXME: can we allocate more resources for the HC? */
2035 break;
2036 case COMP_BANDWIDTH_ERROR:
2037 case COMP_SECONDARY_BANDWIDTH_ERROR:
2038 dev_warn(&udev->dev,
2039 "Not enough bandwidth for new device state.\n");
2040 ret = -ENOSPC;
2041 /* FIXME: can we go back to the old state? */
2042 break;
2043 case COMP_TRB_ERROR:
2044 /* the HCD set up something wrong */
2045 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2046 "add flag = 1, "
2047 "and endpoint is not disabled.\n");
2048 ret = -EINVAL;
2049 break;
2050 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2051 dev_warn(&udev->dev,
2052 "ERROR: Incompatible device for endpoint configure command.\n");
2053 ret = -ENODEV;
2054 break;
2055 case COMP_SUCCESS:
2056 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2057 "Successful Endpoint Configure command");
2058 ret = 0;
2059 break;
2060 default:
2061 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2062 *cmd_status);
2063 ret = -EINVAL;
2064 break;
2065 }
2066 return ret;
2067}
2068
2069static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2070 struct usb_device *udev, u32 *cmd_status)
2071{
2072 int ret;
2073
2074 switch (*cmd_status) {
2075 case COMP_COMMAND_ABORTED:
2076 case COMP_COMMAND_RING_STOPPED:
2077 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2078 ret = -ETIME;
2079 break;
2080 case COMP_PARAMETER_ERROR:
2081 dev_warn(&udev->dev,
2082 "WARN: xHCI driver setup invalid evaluate context command.\n");
2083 ret = -EINVAL;
2084 break;
2085 case COMP_SLOT_NOT_ENABLED_ERROR:
2086 dev_warn(&udev->dev,
2087 "WARN: slot not enabled for evaluate context command.\n");
2088 ret = -EINVAL;
2089 break;
2090 case COMP_CONTEXT_STATE_ERROR:
2091 dev_warn(&udev->dev,
2092 "WARN: invalid context state for evaluate context command.\n");
2093 ret = -EINVAL;
2094 break;
2095 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2096 dev_warn(&udev->dev,
2097 "ERROR: Incompatible device for evaluate context command.\n");
2098 ret = -ENODEV;
2099 break;
2100 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2101 /* Max Exit Latency too large error */
2102 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2103 ret = -EINVAL;
2104 break;
2105 case COMP_SUCCESS:
2106 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2107 "Successful evaluate context command");
2108 ret = 0;
2109 break;
2110 default:
2111 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2112 *cmd_status);
2113 ret = -EINVAL;
2114 break;
2115 }
2116 return ret;
2117}
2118
2119static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2120 struct xhci_input_control_ctx *ctrl_ctx)
2121{
2122 u32 valid_add_flags;
2123 u32 valid_drop_flags;
2124
2125 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2126 * (bit 1). The default control endpoint is added during the Address
2127 * Device command and is never removed until the slot is disabled.
2128 */
2129 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2130 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2131
2132 /* Use hweight32 to count the number of ones in the add flags, or
2133 * number of endpoints added. Don't count endpoints that are changed
2134 * (both added and dropped).
2135 */
2136 return hweight32(valid_add_flags) -
2137 hweight32(valid_add_flags & valid_drop_flags);
2138}
2139
2140static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2141 struct xhci_input_control_ctx *ctrl_ctx)
2142{
2143 u32 valid_add_flags;
2144 u32 valid_drop_flags;
2145
2146 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2147 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2148
2149 return hweight32(valid_drop_flags) -
2150 hweight32(valid_add_flags & valid_drop_flags);
2151}
2152
2153/*
2154 * We need to reserve the new number of endpoints before the configure endpoint
2155 * command completes. We can't subtract the dropped endpoints from the number
2156 * of active endpoints until the command completes because we can oversubscribe
2157 * the host in this case:
2158 *
2159 * - the first configure endpoint command drops more endpoints than it adds
2160 * - a second configure endpoint command that adds more endpoints is queued
2161 * - the first configure endpoint command fails, so the config is unchanged
2162 * - the second command may succeed, even though there isn't enough resources
2163 *
2164 * Must be called with xhci->lock held.
2165 */
2166static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2167 struct xhci_input_control_ctx *ctrl_ctx)
2168{
2169 u32 added_eps;
2170
2171 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2172 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2173 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2174 "Not enough ep ctxs: "
2175 "%u active, need to add %u, limit is %u.",
2176 xhci->num_active_eps, added_eps,
2177 xhci->limit_active_eps);
2178 return -ENOMEM;
2179 }
2180 xhci->num_active_eps += added_eps;
2181 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2182 "Adding %u ep ctxs, %u now active.", added_eps,
2183 xhci->num_active_eps);
2184 return 0;
2185}
2186
2187/*
2188 * The configure endpoint was failed by the xHC for some other reason, so we
2189 * need to revert the resources that failed configuration would have used.
2190 *
2191 * Must be called with xhci->lock held.
2192 */
2193static void xhci_free_host_resources(struct xhci_hcd *xhci,
2194 struct xhci_input_control_ctx *ctrl_ctx)
2195{
2196 u32 num_failed_eps;
2197
2198 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2199 xhci->num_active_eps -= num_failed_eps;
2200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2201 "Removing %u failed ep ctxs, %u now active.",
2202 num_failed_eps,
2203 xhci->num_active_eps);
2204}
2205
2206/*
2207 * Now that the command has completed, clean up the active endpoint count by
2208 * subtracting out the endpoints that were dropped (but not changed).
2209 *
2210 * Must be called with xhci->lock held.
2211 */
2212static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2213 struct xhci_input_control_ctx *ctrl_ctx)
2214{
2215 u32 num_dropped_eps;
2216
2217 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2218 xhci->num_active_eps -= num_dropped_eps;
2219 if (num_dropped_eps)
2220 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2221 "Removing %u dropped ep ctxs, %u now active.",
2222 num_dropped_eps,
2223 xhci->num_active_eps);
2224}
2225
2226static unsigned int xhci_get_block_size(struct usb_device *udev)
2227{
2228 switch (udev->speed) {
2229 case USB_SPEED_LOW:
2230 case USB_SPEED_FULL:
2231 return FS_BLOCK;
2232 case USB_SPEED_HIGH:
2233 return HS_BLOCK;
2234 case USB_SPEED_SUPER:
2235 case USB_SPEED_SUPER_PLUS:
2236 return SS_BLOCK;
2237 case USB_SPEED_UNKNOWN:
2238 default:
2239 /* Should never happen */
2240 return 1;
2241 }
2242}
2243
2244static unsigned int
2245xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2246{
2247 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2248 return LS_OVERHEAD;
2249 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2250 return FS_OVERHEAD;
2251 return HS_OVERHEAD;
2252}
2253
2254/* If we are changing a LS/FS device under a HS hub,
2255 * make sure (if we are activating a new TT) that the HS bus has enough
2256 * bandwidth for this new TT.
2257 */
2258static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2259 struct xhci_virt_device *virt_dev,
2260 int old_active_eps)
2261{
2262 struct xhci_interval_bw_table *bw_table;
2263 struct xhci_tt_bw_info *tt_info;
2264
2265 /* Find the bandwidth table for the root port this TT is attached to. */
2266 bw_table = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum].bw_table;
2267 tt_info = virt_dev->tt_info;
2268 /* If this TT already had active endpoints, the bandwidth for this TT
2269 * has already been added. Removing all periodic endpoints (and thus
2270 * making the TT enactive) will only decrease the bandwidth used.
2271 */
2272 if (old_active_eps)
2273 return 0;
2274 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2275 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2276 return -ENOMEM;
2277 return 0;
2278 }
2279 /* Not sure why we would have no new active endpoints...
2280 *
2281 * Maybe because of an Evaluate Context change for a hub update or a
2282 * control endpoint 0 max packet size change?
2283 * FIXME: skip the bandwidth calculation in that case.
2284 */
2285 return 0;
2286}
2287
2288static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2289 struct xhci_virt_device *virt_dev)
2290{
2291 unsigned int bw_reserved;
2292
2293 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2294 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2295 return -ENOMEM;
2296
2297 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2298 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2299 return -ENOMEM;
2300
2301 return 0;
2302}
2303
2304/*
2305 * This algorithm is a very conservative estimate of the worst-case scheduling
2306 * scenario for any one interval. The hardware dynamically schedules the
2307 * packets, so we can't tell which microframe could be the limiting factor in
2308 * the bandwidth scheduling. This only takes into account periodic endpoints.
2309 *
2310 * Obviously, we can't solve an NP complete problem to find the minimum worst
2311 * case scenario. Instead, we come up with an estimate that is no less than
2312 * the worst case bandwidth used for any one microframe, but may be an
2313 * over-estimate.
2314 *
2315 * We walk the requirements for each endpoint by interval, starting with the
2316 * smallest interval, and place packets in the schedule where there is only one
2317 * possible way to schedule packets for that interval. In order to simplify
2318 * this algorithm, we record the largest max packet size for each interval, and
2319 * assume all packets will be that size.
2320 *
2321 * For interval 0, we obviously must schedule all packets for each interval.
2322 * The bandwidth for interval 0 is just the amount of data to be transmitted
2323 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2324 * the number of packets).
2325 *
2326 * For interval 1, we have two possible microframes to schedule those packets
2327 * in. For this algorithm, if we can schedule the same number of packets for
2328 * each possible scheduling opportunity (each microframe), we will do so. The
2329 * remaining number of packets will be saved to be transmitted in the gaps in
2330 * the next interval's scheduling sequence.
2331 *
2332 * As we move those remaining packets to be scheduled with interval 2 packets,
2333 * we have to double the number of remaining packets to transmit. This is
2334 * because the intervals are actually powers of 2, and we would be transmitting
2335 * the previous interval's packets twice in this interval. We also have to be
2336 * sure that when we look at the largest max packet size for this interval, we
2337 * also look at the largest max packet size for the remaining packets and take
2338 * the greater of the two.
2339 *
2340 * The algorithm continues to evenly distribute packets in each scheduling
2341 * opportunity, and push the remaining packets out, until we get to the last
2342 * interval. Then those packets and their associated overhead are just added
2343 * to the bandwidth used.
2344 */
2345static int xhci_check_bw_table(struct xhci_hcd *xhci,
2346 struct xhci_virt_device *virt_dev,
2347 int old_active_eps)
2348{
2349 unsigned int bw_reserved;
2350 unsigned int max_bandwidth;
2351 unsigned int bw_used;
2352 unsigned int block_size;
2353 struct xhci_interval_bw_table *bw_table;
2354 unsigned int packet_size = 0;
2355 unsigned int overhead = 0;
2356 unsigned int packets_transmitted = 0;
2357 unsigned int packets_remaining = 0;
2358 unsigned int i;
2359
2360 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2361 return xhci_check_ss_bw(xhci, virt_dev);
2362
2363 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2364 max_bandwidth = HS_BW_LIMIT;
2365 /* Convert percent of bus BW reserved to blocks reserved */
2366 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2367 } else {
2368 max_bandwidth = FS_BW_LIMIT;
2369 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2370 }
2371
2372 bw_table = virt_dev->bw_table;
2373 /* We need to translate the max packet size and max ESIT payloads into
2374 * the units the hardware uses.
2375 */
2376 block_size = xhci_get_block_size(virt_dev->udev);
2377
2378 /* If we are manipulating a LS/FS device under a HS hub, double check
2379 * that the HS bus has enough bandwidth if we are activing a new TT.
2380 */
2381 if (virt_dev->tt_info) {
2382 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2383 "Recalculating BW for rootport %u",
2384 virt_dev->rhub_port->hw_portnum + 1);
2385 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2386 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2387 "newly activated TT.\n");
2388 return -ENOMEM;
2389 }
2390 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2391 "Recalculating BW for TT slot %u port %u",
2392 virt_dev->tt_info->slot_id,
2393 virt_dev->tt_info->ttport);
2394 } else {
2395 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2396 "Recalculating BW for rootport %u",
2397 virt_dev->rhub_port->hw_portnum + 1);
2398 }
2399
2400 /* Add in how much bandwidth will be used for interval zero, or the
2401 * rounded max ESIT payload + number of packets * largest overhead.
2402 */
2403 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2404 bw_table->interval_bw[0].num_packets *
2405 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2406
2407 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2408 unsigned int bw_added;
2409 unsigned int largest_mps;
2410 unsigned int interval_overhead;
2411
2412 /*
2413 * How many packets could we transmit in this interval?
2414 * If packets didn't fit in the previous interval, we will need
2415 * to transmit that many packets twice within this interval.
2416 */
2417 packets_remaining = 2 * packets_remaining +
2418 bw_table->interval_bw[i].num_packets;
2419
2420 /* Find the largest max packet size of this or the previous
2421 * interval.
2422 */
2423 if (list_empty(&bw_table->interval_bw[i].endpoints))
2424 largest_mps = 0;
2425 else {
2426 struct xhci_virt_ep *virt_ep;
2427 struct list_head *ep_entry;
2428
2429 ep_entry = bw_table->interval_bw[i].endpoints.next;
2430 virt_ep = list_entry(ep_entry,
2431 struct xhci_virt_ep, bw_endpoint_list);
2432 /* Convert to blocks, rounding up */
2433 largest_mps = DIV_ROUND_UP(
2434 virt_ep->bw_info.max_packet_size,
2435 block_size);
2436 }
2437 if (largest_mps > packet_size)
2438 packet_size = largest_mps;
2439
2440 /* Use the larger overhead of this or the previous interval. */
2441 interval_overhead = xhci_get_largest_overhead(
2442 &bw_table->interval_bw[i]);
2443 if (interval_overhead > overhead)
2444 overhead = interval_overhead;
2445
2446 /* How many packets can we evenly distribute across
2447 * (1 << (i + 1)) possible scheduling opportunities?
2448 */
2449 packets_transmitted = packets_remaining >> (i + 1);
2450
2451 /* Add in the bandwidth used for those scheduled packets */
2452 bw_added = packets_transmitted * (overhead + packet_size);
2453
2454 /* How many packets do we have remaining to transmit? */
2455 packets_remaining = packets_remaining % (1 << (i + 1));
2456
2457 /* What largest max packet size should those packets have? */
2458 /* If we've transmitted all packets, don't carry over the
2459 * largest packet size.
2460 */
2461 if (packets_remaining == 0) {
2462 packet_size = 0;
2463 overhead = 0;
2464 } else if (packets_transmitted > 0) {
2465 /* Otherwise if we do have remaining packets, and we've
2466 * scheduled some packets in this interval, take the
2467 * largest max packet size from endpoints with this
2468 * interval.
2469 */
2470 packet_size = largest_mps;
2471 overhead = interval_overhead;
2472 }
2473 /* Otherwise carry over packet_size and overhead from the last
2474 * time we had a remainder.
2475 */
2476 bw_used += bw_added;
2477 if (bw_used > max_bandwidth) {
2478 xhci_warn(xhci, "Not enough bandwidth. "
2479 "Proposed: %u, Max: %u\n",
2480 bw_used, max_bandwidth);
2481 return -ENOMEM;
2482 }
2483 }
2484 /*
2485 * Ok, we know we have some packets left over after even-handedly
2486 * scheduling interval 15. We don't know which microframes they will
2487 * fit into, so we over-schedule and say they will be scheduled every
2488 * microframe.
2489 */
2490 if (packets_remaining > 0)
2491 bw_used += overhead + packet_size;
2492
2493 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2494 /* OK, we're manipulating a HS device attached to a
2495 * root port bandwidth domain. Include the number of active TTs
2496 * in the bandwidth used.
2497 */
2498 bw_used += TT_HS_OVERHEAD *
2499 xhci->rh_bw[virt_dev->rhub_port->hw_portnum].num_active_tts;
2500 }
2501
2502 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2503 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2504 "Available: %u " "percent",
2505 bw_used, max_bandwidth, bw_reserved,
2506 (max_bandwidth - bw_used - bw_reserved) * 100 /
2507 max_bandwidth);
2508
2509 bw_used += bw_reserved;
2510 if (bw_used > max_bandwidth) {
2511 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2512 bw_used, max_bandwidth);
2513 return -ENOMEM;
2514 }
2515
2516 bw_table->bw_used = bw_used;
2517 return 0;
2518}
2519
2520static bool xhci_is_async_ep(unsigned int ep_type)
2521{
2522 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2523 ep_type != ISOC_IN_EP &&
2524 ep_type != INT_IN_EP);
2525}
2526
2527static bool xhci_is_sync_in_ep(unsigned int ep_type)
2528{
2529 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2530}
2531
2532static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2533{
2534 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2535
2536 if (ep_bw->ep_interval == 0)
2537 return SS_OVERHEAD_BURST +
2538 (ep_bw->mult * ep_bw->num_packets *
2539 (SS_OVERHEAD + mps));
2540 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2541 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2542 1 << ep_bw->ep_interval);
2543
2544}
2545
2546static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2547 struct xhci_bw_info *ep_bw,
2548 struct xhci_interval_bw_table *bw_table,
2549 struct usb_device *udev,
2550 struct xhci_virt_ep *virt_ep,
2551 struct xhci_tt_bw_info *tt_info)
2552{
2553 struct xhci_interval_bw *interval_bw;
2554 int normalized_interval;
2555
2556 if (xhci_is_async_ep(ep_bw->type))
2557 return;
2558
2559 if (udev->speed >= USB_SPEED_SUPER) {
2560 if (xhci_is_sync_in_ep(ep_bw->type))
2561 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2562 xhci_get_ss_bw_consumed(ep_bw);
2563 else
2564 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2565 xhci_get_ss_bw_consumed(ep_bw);
2566 return;
2567 }
2568
2569 /* SuperSpeed endpoints never get added to intervals in the table, so
2570 * this check is only valid for HS/FS/LS devices.
2571 */
2572 if (list_empty(&virt_ep->bw_endpoint_list))
2573 return;
2574 /* For LS/FS devices, we need to translate the interval expressed in
2575 * microframes to frames.
2576 */
2577 if (udev->speed == USB_SPEED_HIGH)
2578 normalized_interval = ep_bw->ep_interval;
2579 else
2580 normalized_interval = ep_bw->ep_interval - 3;
2581
2582 if (normalized_interval == 0)
2583 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2584 interval_bw = &bw_table->interval_bw[normalized_interval];
2585 interval_bw->num_packets -= ep_bw->num_packets;
2586 switch (udev->speed) {
2587 case USB_SPEED_LOW:
2588 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2589 break;
2590 case USB_SPEED_FULL:
2591 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2592 break;
2593 case USB_SPEED_HIGH:
2594 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2595 break;
2596 default:
2597 /* Should never happen because only LS/FS/HS endpoints will get
2598 * added to the endpoint list.
2599 */
2600 return;
2601 }
2602 if (tt_info)
2603 tt_info->active_eps -= 1;
2604 list_del_init(&virt_ep->bw_endpoint_list);
2605}
2606
2607static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2608 struct xhci_bw_info *ep_bw,
2609 struct xhci_interval_bw_table *bw_table,
2610 struct usb_device *udev,
2611 struct xhci_virt_ep *virt_ep,
2612 struct xhci_tt_bw_info *tt_info)
2613{
2614 struct xhci_interval_bw *interval_bw;
2615 struct xhci_virt_ep *smaller_ep;
2616 int normalized_interval;
2617
2618 if (xhci_is_async_ep(ep_bw->type))
2619 return;
2620
2621 if (udev->speed == USB_SPEED_SUPER) {
2622 if (xhci_is_sync_in_ep(ep_bw->type))
2623 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2624 xhci_get_ss_bw_consumed(ep_bw);
2625 else
2626 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2627 xhci_get_ss_bw_consumed(ep_bw);
2628 return;
2629 }
2630
2631 /* For LS/FS devices, we need to translate the interval expressed in
2632 * microframes to frames.
2633 */
2634 if (udev->speed == USB_SPEED_HIGH)
2635 normalized_interval = ep_bw->ep_interval;
2636 else
2637 normalized_interval = ep_bw->ep_interval - 3;
2638
2639 if (normalized_interval == 0)
2640 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2641 interval_bw = &bw_table->interval_bw[normalized_interval];
2642 interval_bw->num_packets += ep_bw->num_packets;
2643 switch (udev->speed) {
2644 case USB_SPEED_LOW:
2645 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2646 break;
2647 case USB_SPEED_FULL:
2648 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2649 break;
2650 case USB_SPEED_HIGH:
2651 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2652 break;
2653 default:
2654 /* Should never happen because only LS/FS/HS endpoints will get
2655 * added to the endpoint list.
2656 */
2657 return;
2658 }
2659
2660 if (tt_info)
2661 tt_info->active_eps += 1;
2662 /* Insert the endpoint into the list, largest max packet size first. */
2663 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2664 bw_endpoint_list) {
2665 if (ep_bw->max_packet_size >=
2666 smaller_ep->bw_info.max_packet_size) {
2667 /* Add the new ep before the smaller endpoint */
2668 list_add_tail(&virt_ep->bw_endpoint_list,
2669 &smaller_ep->bw_endpoint_list);
2670 return;
2671 }
2672 }
2673 /* Add the new endpoint at the end of the list. */
2674 list_add_tail(&virt_ep->bw_endpoint_list,
2675 &interval_bw->endpoints);
2676}
2677
2678void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2679 struct xhci_virt_device *virt_dev,
2680 int old_active_eps)
2681{
2682 struct xhci_root_port_bw_info *rh_bw_info;
2683 if (!virt_dev->tt_info)
2684 return;
2685
2686 rh_bw_info = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum];
2687 if (old_active_eps == 0 &&
2688 virt_dev->tt_info->active_eps != 0) {
2689 rh_bw_info->num_active_tts += 1;
2690 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2691 } else if (old_active_eps != 0 &&
2692 virt_dev->tt_info->active_eps == 0) {
2693 rh_bw_info->num_active_tts -= 1;
2694 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2695 }
2696}
2697
2698static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2699 struct xhci_virt_device *virt_dev,
2700 struct xhci_container_ctx *in_ctx)
2701{
2702 struct xhci_bw_info ep_bw_info[31];
2703 int i;
2704 struct xhci_input_control_ctx *ctrl_ctx;
2705 int old_active_eps = 0;
2706
2707 if (virt_dev->tt_info)
2708 old_active_eps = virt_dev->tt_info->active_eps;
2709
2710 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2711 if (!ctrl_ctx) {
2712 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2713 __func__);
2714 return -ENOMEM;
2715 }
2716
2717 for (i = 0; i < 31; i++) {
2718 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2719 continue;
2720
2721 /* Make a copy of the BW info in case we need to revert this */
2722 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2723 sizeof(ep_bw_info[i]));
2724 /* Drop the endpoint from the interval table if the endpoint is
2725 * being dropped or changed.
2726 */
2727 if (EP_IS_DROPPED(ctrl_ctx, i))
2728 xhci_drop_ep_from_interval_table(xhci,
2729 &virt_dev->eps[i].bw_info,
2730 virt_dev->bw_table,
2731 virt_dev->udev,
2732 &virt_dev->eps[i],
2733 virt_dev->tt_info);
2734 }
2735 /* Overwrite the information stored in the endpoints' bw_info */
2736 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2737 for (i = 0; i < 31; i++) {
2738 /* Add any changed or added endpoints to the interval table */
2739 if (EP_IS_ADDED(ctrl_ctx, i))
2740 xhci_add_ep_to_interval_table(xhci,
2741 &virt_dev->eps[i].bw_info,
2742 virt_dev->bw_table,
2743 virt_dev->udev,
2744 &virt_dev->eps[i],
2745 virt_dev->tt_info);
2746 }
2747
2748 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2749 /* Ok, this fits in the bandwidth we have.
2750 * Update the number of active TTs.
2751 */
2752 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2753 return 0;
2754 }
2755
2756 /* We don't have enough bandwidth for this, revert the stored info. */
2757 for (i = 0; i < 31; i++) {
2758 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2759 continue;
2760
2761 /* Drop the new copies of any added or changed endpoints from
2762 * the interval table.
2763 */
2764 if (EP_IS_ADDED(ctrl_ctx, i)) {
2765 xhci_drop_ep_from_interval_table(xhci,
2766 &virt_dev->eps[i].bw_info,
2767 virt_dev->bw_table,
2768 virt_dev->udev,
2769 &virt_dev->eps[i],
2770 virt_dev->tt_info);
2771 }
2772 /* Revert the endpoint back to its old information */
2773 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2774 sizeof(ep_bw_info[i]));
2775 /* Add any changed or dropped endpoints back into the table */
2776 if (EP_IS_DROPPED(ctrl_ctx, i))
2777 xhci_add_ep_to_interval_table(xhci,
2778 &virt_dev->eps[i].bw_info,
2779 virt_dev->bw_table,
2780 virt_dev->udev,
2781 &virt_dev->eps[i],
2782 virt_dev->tt_info);
2783 }
2784 return -ENOMEM;
2785}
2786
2787
2788/* Issue a configure endpoint command or evaluate context command
2789 * and wait for it to finish.
2790 */
2791static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2792 struct usb_device *udev,
2793 struct xhci_command *command,
2794 bool ctx_change, bool must_succeed)
2795{
2796 int ret;
2797 unsigned long flags;
2798 struct xhci_input_control_ctx *ctrl_ctx;
2799 struct xhci_virt_device *virt_dev;
2800 struct xhci_slot_ctx *slot_ctx;
2801
2802 if (!command)
2803 return -EINVAL;
2804
2805 spin_lock_irqsave(&xhci->lock, flags);
2806
2807 if (xhci->xhc_state & XHCI_STATE_DYING) {
2808 spin_unlock_irqrestore(&xhci->lock, flags);
2809 return -ESHUTDOWN;
2810 }
2811
2812 virt_dev = xhci->devs[udev->slot_id];
2813
2814 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2815 if (!ctrl_ctx) {
2816 spin_unlock_irqrestore(&xhci->lock, flags);
2817 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2818 __func__);
2819 return -ENOMEM;
2820 }
2821
2822 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2823 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2824 spin_unlock_irqrestore(&xhci->lock, flags);
2825 xhci_warn(xhci, "Not enough host resources, "
2826 "active endpoint contexts = %u\n",
2827 xhci->num_active_eps);
2828 return -ENOMEM;
2829 }
2830 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2831 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2832 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2833 xhci_free_host_resources(xhci, ctrl_ctx);
2834 spin_unlock_irqrestore(&xhci->lock, flags);
2835 xhci_warn(xhci, "Not enough bandwidth\n");
2836 return -ENOMEM;
2837 }
2838
2839 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2840
2841 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2842 trace_xhci_configure_endpoint(slot_ctx);
2843
2844 if (!ctx_change)
2845 ret = xhci_queue_configure_endpoint(xhci, command,
2846 command->in_ctx->dma,
2847 udev->slot_id, must_succeed);
2848 else
2849 ret = xhci_queue_evaluate_context(xhci, command,
2850 command->in_ctx->dma,
2851 udev->slot_id, must_succeed);
2852 if (ret < 0) {
2853 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2854 xhci_free_host_resources(xhci, ctrl_ctx);
2855 spin_unlock_irqrestore(&xhci->lock, flags);
2856 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2857 "FIXME allocate a new ring segment");
2858 return -ENOMEM;
2859 }
2860 xhci_ring_cmd_db(xhci);
2861 spin_unlock_irqrestore(&xhci->lock, flags);
2862
2863 /* Wait for the configure endpoint command to complete */
2864 wait_for_completion(command->completion);
2865
2866 if (!ctx_change)
2867 ret = xhci_configure_endpoint_result(xhci, udev,
2868 &command->status);
2869 else
2870 ret = xhci_evaluate_context_result(xhci, udev,
2871 &command->status);
2872
2873 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2874 spin_lock_irqsave(&xhci->lock, flags);
2875 /* If the command failed, remove the reserved resources.
2876 * Otherwise, clean up the estimate to include dropped eps.
2877 */
2878 if (ret)
2879 xhci_free_host_resources(xhci, ctrl_ctx);
2880 else
2881 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2882 spin_unlock_irqrestore(&xhci->lock, flags);
2883 }
2884 return ret;
2885}
2886
2887static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2888 struct xhci_virt_device *vdev, int i)
2889{
2890 struct xhci_virt_ep *ep = &vdev->eps[i];
2891
2892 if (ep->ep_state & EP_HAS_STREAMS) {
2893 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2894 xhci_get_endpoint_address(i));
2895 xhci_free_stream_info(xhci, ep->stream_info);
2896 ep->stream_info = NULL;
2897 ep->ep_state &= ~EP_HAS_STREAMS;
2898 }
2899}
2900
2901/* Called after one or more calls to xhci_add_endpoint() or
2902 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2903 * to call xhci_reset_bandwidth().
2904 *
2905 * Since we are in the middle of changing either configuration or
2906 * installing a new alt setting, the USB core won't allow URBs to be
2907 * enqueued for any endpoint on the old config or interface. Nothing
2908 * else should be touching the xhci->devs[slot_id] structure, so we
2909 * don't need to take the xhci->lock for manipulating that.
2910 */
2911int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2912{
2913 int i;
2914 int ret = 0;
2915 struct xhci_hcd *xhci;
2916 struct xhci_virt_device *virt_dev;
2917 struct xhci_input_control_ctx *ctrl_ctx;
2918 struct xhci_slot_ctx *slot_ctx;
2919 struct xhci_command *command;
2920
2921 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2922 if (ret <= 0)
2923 return ret;
2924 xhci = hcd_to_xhci(hcd);
2925 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2926 (xhci->xhc_state & XHCI_STATE_REMOVING))
2927 return -ENODEV;
2928
2929 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2930 virt_dev = xhci->devs[udev->slot_id];
2931
2932 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2933 if (!command)
2934 return -ENOMEM;
2935
2936 command->in_ctx = virt_dev->in_ctx;
2937
2938 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2939 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2940 if (!ctrl_ctx) {
2941 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2942 __func__);
2943 ret = -ENOMEM;
2944 goto command_cleanup;
2945 }
2946 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2947 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2948 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2949
2950 /* Don't issue the command if there's no endpoints to update. */
2951 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2952 ctrl_ctx->drop_flags == 0) {
2953 ret = 0;
2954 goto command_cleanup;
2955 }
2956 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2957 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2958 for (i = 31; i >= 1; i--) {
2959 __le32 le32 = cpu_to_le32(BIT(i));
2960
2961 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2962 || (ctrl_ctx->add_flags & le32) || i == 1) {
2963 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2964 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2965 break;
2966 }
2967 }
2968
2969 ret = xhci_configure_endpoint(xhci, udev, command,
2970 false, false);
2971 if (ret)
2972 /* Callee should call reset_bandwidth() */
2973 goto command_cleanup;
2974
2975 /* Free any rings that were dropped, but not changed. */
2976 for (i = 1; i < 31; i++) {
2977 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2978 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2979 xhci_free_endpoint_ring(xhci, virt_dev, i);
2980 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2981 }
2982 }
2983 xhci_zero_in_ctx(xhci, virt_dev);
2984 /*
2985 * Install any rings for completely new endpoints or changed endpoints,
2986 * and free any old rings from changed endpoints.
2987 */
2988 for (i = 1; i < 31; i++) {
2989 if (!virt_dev->eps[i].new_ring)
2990 continue;
2991 /* Only free the old ring if it exists.
2992 * It may not if this is the first add of an endpoint.
2993 */
2994 if (virt_dev->eps[i].ring) {
2995 xhci_free_endpoint_ring(xhci, virt_dev, i);
2996 }
2997 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2998 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2999 virt_dev->eps[i].new_ring = NULL;
3000 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3001 }
3002command_cleanup:
3003 kfree(command->completion);
3004 kfree(command);
3005
3006 return ret;
3007}
3008EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3009
3010void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3011{
3012 struct xhci_hcd *xhci;
3013 struct xhci_virt_device *virt_dev;
3014 int i, ret;
3015
3016 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3017 if (ret <= 0)
3018 return;
3019 xhci = hcd_to_xhci(hcd);
3020
3021 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3022 virt_dev = xhci->devs[udev->slot_id];
3023 /* Free any rings allocated for added endpoints */
3024 for (i = 0; i < 31; i++) {
3025 if (virt_dev->eps[i].new_ring) {
3026 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3027 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3028 virt_dev->eps[i].new_ring = NULL;
3029 }
3030 }
3031 xhci_zero_in_ctx(xhci, virt_dev);
3032}
3033EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3034
3035static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3036 struct xhci_container_ctx *in_ctx,
3037 struct xhci_container_ctx *out_ctx,
3038 struct xhci_input_control_ctx *ctrl_ctx,
3039 u32 add_flags, u32 drop_flags)
3040{
3041 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3042 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3043 xhci_slot_copy(xhci, in_ctx, out_ctx);
3044 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3045}
3046
3047static void xhci_endpoint_disable(struct usb_hcd *hcd,
3048 struct usb_host_endpoint *host_ep)
3049{
3050 struct xhci_hcd *xhci;
3051 struct xhci_virt_device *vdev;
3052 struct xhci_virt_ep *ep;
3053 struct usb_device *udev;
3054 unsigned long flags;
3055 unsigned int ep_index;
3056
3057 xhci = hcd_to_xhci(hcd);
3058rescan:
3059 spin_lock_irqsave(&xhci->lock, flags);
3060
3061 udev = (struct usb_device *)host_ep->hcpriv;
3062 if (!udev || !udev->slot_id)
3063 goto done;
3064
3065 vdev = xhci->devs[udev->slot_id];
3066 if (!vdev)
3067 goto done;
3068
3069 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3070 ep = &vdev->eps[ep_index];
3071
3072 /* wait for hub_tt_work to finish clearing hub TT */
3073 if (ep->ep_state & EP_CLEARING_TT) {
3074 spin_unlock_irqrestore(&xhci->lock, flags);
3075 schedule_timeout_uninterruptible(1);
3076 goto rescan;
3077 }
3078
3079 if (ep->ep_state)
3080 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3081 ep->ep_state);
3082done:
3083 host_ep->hcpriv = NULL;
3084 spin_unlock_irqrestore(&xhci->lock, flags);
3085}
3086
3087/*
3088 * Called after usb core issues a clear halt control message.
3089 * The host side of the halt should already be cleared by a reset endpoint
3090 * command issued when the STALL event was received.
3091 *
3092 * The reset endpoint command may only be issued to endpoints in the halted
3093 * state. For software that wishes to reset the data toggle or sequence number
3094 * of an endpoint that isn't in the halted state this function will issue a
3095 * configure endpoint command with the Drop and Add bits set for the target
3096 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3097 *
3098 * vdev may be lost due to xHC restore error and re-initialization during S3/S4
3099 * resume. A new vdev will be allocated later by xhci_discover_or_reset_device()
3100 */
3101
3102static void xhci_endpoint_reset(struct usb_hcd *hcd,
3103 struct usb_host_endpoint *host_ep)
3104{
3105 struct xhci_hcd *xhci;
3106 struct usb_device *udev;
3107 struct xhci_virt_device *vdev;
3108 struct xhci_virt_ep *ep;
3109 struct xhci_input_control_ctx *ctrl_ctx;
3110 struct xhci_command *stop_cmd, *cfg_cmd;
3111 unsigned int ep_index;
3112 unsigned long flags;
3113 u32 ep_flag;
3114 int err;
3115
3116 xhci = hcd_to_xhci(hcd);
3117 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3118
3119 /*
3120 * Usb core assumes a max packet value for ep0 on FS devices until the
3121 * real value is read from the descriptor. Core resets Ep0 if values
3122 * mismatch. Reconfigure the xhci ep0 endpoint context here in that case
3123 */
3124 if (usb_endpoint_xfer_control(&host_ep->desc) && ep_index == 0) {
3125
3126 udev = container_of(host_ep, struct usb_device, ep0);
3127 if (udev->speed != USB_SPEED_FULL || !udev->slot_id)
3128 return;
3129
3130 vdev = xhci->devs[udev->slot_id];
3131 if (!vdev || vdev->udev != udev)
3132 return;
3133
3134 xhci_check_ep0_maxpacket(xhci, vdev);
3135
3136 /* Nothing else should be done here for ep0 during ep reset */
3137 return;
3138 }
3139
3140 if (!host_ep->hcpriv)
3141 return;
3142 udev = (struct usb_device *) host_ep->hcpriv;
3143 vdev = xhci->devs[udev->slot_id];
3144
3145 if (!udev->slot_id || !vdev)
3146 return;
3147
3148 ep = &vdev->eps[ep_index];
3149
3150 /* Bail out if toggle is already being cleared by a endpoint reset */
3151 spin_lock_irqsave(&xhci->lock, flags);
3152 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3153 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3154 spin_unlock_irqrestore(&xhci->lock, flags);
3155 return;
3156 }
3157 spin_unlock_irqrestore(&xhci->lock, flags);
3158 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3159 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3160 usb_endpoint_xfer_isoc(&host_ep->desc))
3161 return;
3162
3163 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3164
3165 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3166 return;
3167
3168 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3169 if (!stop_cmd)
3170 return;
3171
3172 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3173 if (!cfg_cmd)
3174 goto cleanup;
3175
3176 spin_lock_irqsave(&xhci->lock, flags);
3177
3178 /* block queuing new trbs and ringing ep doorbell */
3179 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3180
3181 /*
3182 * Make sure endpoint ring is empty before resetting the toggle/seq.
3183 * Driver is required to synchronously cancel all transfer request.
3184 * Stop the endpoint to force xHC to update the output context
3185 */
3186
3187 if (!list_empty(&ep->ring->td_list)) {
3188 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3189 spin_unlock_irqrestore(&xhci->lock, flags);
3190 xhci_free_command(xhci, cfg_cmd);
3191 goto cleanup;
3192 }
3193
3194 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3195 ep_index, 0);
3196 if (err < 0) {
3197 spin_unlock_irqrestore(&xhci->lock, flags);
3198 xhci_free_command(xhci, cfg_cmd);
3199 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3200 __func__, err);
3201 goto cleanup;
3202 }
3203
3204 xhci_ring_cmd_db(xhci);
3205 spin_unlock_irqrestore(&xhci->lock, flags);
3206
3207 wait_for_completion(stop_cmd->completion);
3208
3209 spin_lock_irqsave(&xhci->lock, flags);
3210
3211 /* config ep command clears toggle if add and drop ep flags are set */
3212 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3213 if (!ctrl_ctx) {
3214 spin_unlock_irqrestore(&xhci->lock, flags);
3215 xhci_free_command(xhci, cfg_cmd);
3216 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3217 __func__);
3218 goto cleanup;
3219 }
3220
3221 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3222 ctrl_ctx, ep_flag, ep_flag);
3223 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3224
3225 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3226 udev->slot_id, false);
3227 if (err < 0) {
3228 spin_unlock_irqrestore(&xhci->lock, flags);
3229 xhci_free_command(xhci, cfg_cmd);
3230 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3231 __func__, err);
3232 goto cleanup;
3233 }
3234
3235 xhci_ring_cmd_db(xhci);
3236 spin_unlock_irqrestore(&xhci->lock, flags);
3237
3238 wait_for_completion(cfg_cmd->completion);
3239
3240 xhci_free_command(xhci, cfg_cmd);
3241cleanup:
3242 xhci_free_command(xhci, stop_cmd);
3243 spin_lock_irqsave(&xhci->lock, flags);
3244 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3245 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3246 spin_unlock_irqrestore(&xhci->lock, flags);
3247}
3248
3249static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3250 struct usb_device *udev, struct usb_host_endpoint *ep,
3251 unsigned int slot_id)
3252{
3253 int ret;
3254 unsigned int ep_index;
3255 unsigned int ep_state;
3256
3257 if (!ep)
3258 return -EINVAL;
3259 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3260 if (ret <= 0)
3261 return ret ? ret : -EINVAL;
3262 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3263 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3264 " descriptor for ep 0x%x does not support streams\n",
3265 ep->desc.bEndpointAddress);
3266 return -EINVAL;
3267 }
3268
3269 ep_index = xhci_get_endpoint_index(&ep->desc);
3270 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3271 if (ep_state & EP_HAS_STREAMS ||
3272 ep_state & EP_GETTING_STREAMS) {
3273 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3274 "already has streams set up.\n",
3275 ep->desc.bEndpointAddress);
3276 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3277 "dynamic stream context array reallocation.\n");
3278 return -EINVAL;
3279 }
3280 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3281 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3282 "endpoint 0x%x; URBs are pending.\n",
3283 ep->desc.bEndpointAddress);
3284 return -EINVAL;
3285 }
3286 return 0;
3287}
3288
3289static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3290 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3291{
3292 unsigned int max_streams;
3293
3294 /* The stream context array size must be a power of two */
3295 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3296 /*
3297 * Find out how many primary stream array entries the host controller
3298 * supports. Later we may use secondary stream arrays (similar to 2nd
3299 * level page entries), but that's an optional feature for xHCI host
3300 * controllers. xHCs must support at least 4 stream IDs.
3301 */
3302 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3303 if (*num_stream_ctxs > max_streams) {
3304 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3305 max_streams);
3306 *num_stream_ctxs = max_streams;
3307 *num_streams = max_streams;
3308 }
3309}
3310
3311/* Returns an error code if one of the endpoint already has streams.
3312 * This does not change any data structures, it only checks and gathers
3313 * information.
3314 */
3315static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3316 struct usb_device *udev,
3317 struct usb_host_endpoint **eps, unsigned int num_eps,
3318 unsigned int *num_streams, u32 *changed_ep_bitmask)
3319{
3320 unsigned int max_streams;
3321 unsigned int endpoint_flag;
3322 int i;
3323 int ret;
3324
3325 for (i = 0; i < num_eps; i++) {
3326 ret = xhci_check_streams_endpoint(xhci, udev,
3327 eps[i], udev->slot_id);
3328 if (ret < 0)
3329 return ret;
3330
3331 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3332 if (max_streams < (*num_streams - 1)) {
3333 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3334 eps[i]->desc.bEndpointAddress,
3335 max_streams);
3336 *num_streams = max_streams+1;
3337 }
3338
3339 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3340 if (*changed_ep_bitmask & endpoint_flag)
3341 return -EINVAL;
3342 *changed_ep_bitmask |= endpoint_flag;
3343 }
3344 return 0;
3345}
3346
3347static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3348 struct usb_device *udev,
3349 struct usb_host_endpoint **eps, unsigned int num_eps)
3350{
3351 u32 changed_ep_bitmask = 0;
3352 unsigned int slot_id;
3353 unsigned int ep_index;
3354 unsigned int ep_state;
3355 int i;
3356
3357 slot_id = udev->slot_id;
3358 if (!xhci->devs[slot_id])
3359 return 0;
3360
3361 for (i = 0; i < num_eps; i++) {
3362 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3363 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3364 /* Are streams already being freed for the endpoint? */
3365 if (ep_state & EP_GETTING_NO_STREAMS) {
3366 xhci_warn(xhci, "WARN Can't disable streams for "
3367 "endpoint 0x%x, "
3368 "streams are being disabled already\n",
3369 eps[i]->desc.bEndpointAddress);
3370 return 0;
3371 }
3372 /* Are there actually any streams to free? */
3373 if (!(ep_state & EP_HAS_STREAMS) &&
3374 !(ep_state & EP_GETTING_STREAMS)) {
3375 xhci_warn(xhci, "WARN Can't disable streams for "
3376 "endpoint 0x%x, "
3377 "streams are already disabled!\n",
3378 eps[i]->desc.bEndpointAddress);
3379 xhci_warn(xhci, "WARN xhci_free_streams() called "
3380 "with non-streams endpoint\n");
3381 return 0;
3382 }
3383 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3384 }
3385 return changed_ep_bitmask;
3386}
3387
3388/*
3389 * The USB device drivers use this function (through the HCD interface in USB
3390 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3391 * coordinate mass storage command queueing across multiple endpoints (basically
3392 * a stream ID == a task ID).
3393 *
3394 * Setting up streams involves allocating the same size stream context array
3395 * for each endpoint and issuing a configure endpoint command for all endpoints.
3396 *
3397 * Don't allow the call to succeed if one endpoint only supports one stream
3398 * (which means it doesn't support streams at all).
3399 *
3400 * Drivers may get less stream IDs than they asked for, if the host controller
3401 * hardware or endpoints claim they can't support the number of requested
3402 * stream IDs.
3403 */
3404static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3405 struct usb_host_endpoint **eps, unsigned int num_eps,
3406 unsigned int num_streams, gfp_t mem_flags)
3407{
3408 int i, ret;
3409 struct xhci_hcd *xhci;
3410 struct xhci_virt_device *vdev;
3411 struct xhci_command *config_cmd;
3412 struct xhci_input_control_ctx *ctrl_ctx;
3413 unsigned int ep_index;
3414 unsigned int num_stream_ctxs;
3415 unsigned int max_packet;
3416 unsigned long flags;
3417 u32 changed_ep_bitmask = 0;
3418
3419 if (!eps)
3420 return -EINVAL;
3421
3422 /* Add one to the number of streams requested to account for
3423 * stream 0 that is reserved for xHCI usage.
3424 */
3425 num_streams += 1;
3426 xhci = hcd_to_xhci(hcd);
3427 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3428 num_streams);
3429
3430 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3431 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3432 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3433 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3434 return -ENOSYS;
3435 }
3436
3437 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3438 if (!config_cmd)
3439 return -ENOMEM;
3440
3441 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3442 if (!ctrl_ctx) {
3443 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3444 __func__);
3445 xhci_free_command(xhci, config_cmd);
3446 return -ENOMEM;
3447 }
3448
3449 /* Check to make sure all endpoints are not already configured for
3450 * streams. While we're at it, find the maximum number of streams that
3451 * all the endpoints will support and check for duplicate endpoints.
3452 */
3453 spin_lock_irqsave(&xhci->lock, flags);
3454 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3455 num_eps, &num_streams, &changed_ep_bitmask);
3456 if (ret < 0) {
3457 xhci_free_command(xhci, config_cmd);
3458 spin_unlock_irqrestore(&xhci->lock, flags);
3459 return ret;
3460 }
3461 if (num_streams <= 1) {
3462 xhci_warn(xhci, "WARN: endpoints can't handle "
3463 "more than one stream.\n");
3464 xhci_free_command(xhci, config_cmd);
3465 spin_unlock_irqrestore(&xhci->lock, flags);
3466 return -EINVAL;
3467 }
3468 vdev = xhci->devs[udev->slot_id];
3469 /* Mark each endpoint as being in transition, so
3470 * xhci_urb_enqueue() will reject all URBs.
3471 */
3472 for (i = 0; i < num_eps; i++) {
3473 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3474 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3475 }
3476 spin_unlock_irqrestore(&xhci->lock, flags);
3477
3478 /* Setup internal data structures and allocate HW data structures for
3479 * streams (but don't install the HW structures in the input context
3480 * until we're sure all memory allocation succeeded).
3481 */
3482 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3483 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3484 num_stream_ctxs, num_streams);
3485
3486 for (i = 0; i < num_eps; i++) {
3487 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3488 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3489 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3490 num_stream_ctxs,
3491 num_streams,
3492 max_packet, mem_flags);
3493 if (!vdev->eps[ep_index].stream_info)
3494 goto cleanup;
3495 /* Set maxPstreams in endpoint context and update deq ptr to
3496 * point to stream context array. FIXME
3497 */
3498 }
3499
3500 /* Set up the input context for a configure endpoint command. */
3501 for (i = 0; i < num_eps; i++) {
3502 struct xhci_ep_ctx *ep_ctx;
3503
3504 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3505 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3506
3507 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3508 vdev->out_ctx, ep_index);
3509 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3510 vdev->eps[ep_index].stream_info);
3511 }
3512 /* Tell the HW to drop its old copy of the endpoint context info
3513 * and add the updated copy from the input context.
3514 */
3515 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3516 vdev->out_ctx, ctrl_ctx,
3517 changed_ep_bitmask, changed_ep_bitmask);
3518
3519 /* Issue and wait for the configure endpoint command */
3520 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3521 false, false);
3522
3523 /* xHC rejected the configure endpoint command for some reason, so we
3524 * leave the old ring intact and free our internal streams data
3525 * structure.
3526 */
3527 if (ret < 0)
3528 goto cleanup;
3529
3530 spin_lock_irqsave(&xhci->lock, flags);
3531 for (i = 0; i < num_eps; i++) {
3532 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3533 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3534 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3535 udev->slot_id, ep_index);
3536 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3537 }
3538 xhci_free_command(xhci, config_cmd);
3539 spin_unlock_irqrestore(&xhci->lock, flags);
3540
3541 for (i = 0; i < num_eps; i++) {
3542 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3543 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3544 }
3545 /* Subtract 1 for stream 0, which drivers can't use */
3546 return num_streams - 1;
3547
3548cleanup:
3549 /* If it didn't work, free the streams! */
3550 for (i = 0; i < num_eps; i++) {
3551 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3552 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3553 vdev->eps[ep_index].stream_info = NULL;
3554 /* FIXME Unset maxPstreams in endpoint context and
3555 * update deq ptr to point to normal string ring.
3556 */
3557 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3558 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3559 xhci_endpoint_zero(xhci, vdev, eps[i]);
3560 }
3561 xhci_free_command(xhci, config_cmd);
3562 return -ENOMEM;
3563}
3564
3565/* Transition the endpoint from using streams to being a "normal" endpoint
3566 * without streams.
3567 *
3568 * Modify the endpoint context state, submit a configure endpoint command,
3569 * and free all endpoint rings for streams if that completes successfully.
3570 */
3571static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3572 struct usb_host_endpoint **eps, unsigned int num_eps,
3573 gfp_t mem_flags)
3574{
3575 int i, ret;
3576 struct xhci_hcd *xhci;
3577 struct xhci_virt_device *vdev;
3578 struct xhci_command *command;
3579 struct xhci_input_control_ctx *ctrl_ctx;
3580 unsigned int ep_index;
3581 unsigned long flags;
3582 u32 changed_ep_bitmask;
3583
3584 xhci = hcd_to_xhci(hcd);
3585 vdev = xhci->devs[udev->slot_id];
3586
3587 /* Set up a configure endpoint command to remove the streams rings */
3588 spin_lock_irqsave(&xhci->lock, flags);
3589 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3590 udev, eps, num_eps);
3591 if (changed_ep_bitmask == 0) {
3592 spin_unlock_irqrestore(&xhci->lock, flags);
3593 return -EINVAL;
3594 }
3595
3596 /* Use the xhci_command structure from the first endpoint. We may have
3597 * allocated too many, but the driver may call xhci_free_streams() for
3598 * each endpoint it grouped into one call to xhci_alloc_streams().
3599 */
3600 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3601 command = vdev->eps[ep_index].stream_info->free_streams_command;
3602 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3603 if (!ctrl_ctx) {
3604 spin_unlock_irqrestore(&xhci->lock, flags);
3605 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3606 __func__);
3607 return -EINVAL;
3608 }
3609
3610 for (i = 0; i < num_eps; i++) {
3611 struct xhci_ep_ctx *ep_ctx;
3612
3613 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3614 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3615 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3616 EP_GETTING_NO_STREAMS;
3617
3618 xhci_endpoint_copy(xhci, command->in_ctx,
3619 vdev->out_ctx, ep_index);
3620 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3621 &vdev->eps[ep_index]);
3622 }
3623 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3624 vdev->out_ctx, ctrl_ctx,
3625 changed_ep_bitmask, changed_ep_bitmask);
3626 spin_unlock_irqrestore(&xhci->lock, flags);
3627
3628 /* Issue and wait for the configure endpoint command,
3629 * which must succeed.
3630 */
3631 ret = xhci_configure_endpoint(xhci, udev, command,
3632 false, true);
3633
3634 /* xHC rejected the configure endpoint command for some reason, so we
3635 * leave the streams rings intact.
3636 */
3637 if (ret < 0)
3638 return ret;
3639
3640 spin_lock_irqsave(&xhci->lock, flags);
3641 for (i = 0; i < num_eps; i++) {
3642 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3643 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3644 vdev->eps[ep_index].stream_info = NULL;
3645 /* FIXME Unset maxPstreams in endpoint context and
3646 * update deq ptr to point to normal string ring.
3647 */
3648 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3649 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3650 }
3651 spin_unlock_irqrestore(&xhci->lock, flags);
3652
3653 return 0;
3654}
3655
3656/*
3657 * Deletes endpoint resources for endpoints that were active before a Reset
3658 * Device command, or a Disable Slot command. The Reset Device command leaves
3659 * the control endpoint intact, whereas the Disable Slot command deletes it.
3660 *
3661 * Must be called with xhci->lock held.
3662 */
3663void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3664 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3665{
3666 int i;
3667 unsigned int num_dropped_eps = 0;
3668 unsigned int drop_flags = 0;
3669
3670 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3671 if (virt_dev->eps[i].ring) {
3672 drop_flags |= 1 << i;
3673 num_dropped_eps++;
3674 }
3675 }
3676 xhci->num_active_eps -= num_dropped_eps;
3677 if (num_dropped_eps)
3678 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3679 "Dropped %u ep ctxs, flags = 0x%x, "
3680 "%u now active.",
3681 num_dropped_eps, drop_flags,
3682 xhci->num_active_eps);
3683}
3684
3685/*
3686 * This submits a Reset Device Command, which will set the device state to 0,
3687 * set the device address to 0, and disable all the endpoints except the default
3688 * control endpoint. The USB core should come back and call
3689 * xhci_address_device(), and then re-set up the configuration. If this is
3690 * called because of a usb_reset_and_verify_device(), then the old alternate
3691 * settings will be re-installed through the normal bandwidth allocation
3692 * functions.
3693 *
3694 * Wait for the Reset Device command to finish. Remove all structures
3695 * associated with the endpoints that were disabled. Clear the input device
3696 * structure? Reset the control endpoint 0 max packet size?
3697 *
3698 * If the virt_dev to be reset does not exist or does not match the udev,
3699 * it means the device is lost, possibly due to the xHC restore error and
3700 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3701 * re-allocate the device.
3702 */
3703static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3704 struct usb_device *udev)
3705{
3706 int ret, i;
3707 unsigned long flags;
3708 struct xhci_hcd *xhci;
3709 unsigned int slot_id;
3710 struct xhci_virt_device *virt_dev;
3711 struct xhci_command *reset_device_cmd;
3712 struct xhci_slot_ctx *slot_ctx;
3713 int old_active_eps = 0;
3714
3715 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3716 if (ret <= 0)
3717 return ret;
3718 xhci = hcd_to_xhci(hcd);
3719 slot_id = udev->slot_id;
3720 virt_dev = xhci->devs[slot_id];
3721 if (!virt_dev) {
3722 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3723 "not exist. Re-allocate the device\n", slot_id);
3724 ret = xhci_alloc_dev(hcd, udev);
3725 if (ret == 1)
3726 return 0;
3727 else
3728 return -EINVAL;
3729 }
3730
3731 if (virt_dev->tt_info)
3732 old_active_eps = virt_dev->tt_info->active_eps;
3733
3734 if (virt_dev->udev != udev) {
3735 /* If the virt_dev and the udev does not match, this virt_dev
3736 * may belong to another udev.
3737 * Re-allocate the device.
3738 */
3739 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3740 "not match the udev. Re-allocate the device\n",
3741 slot_id);
3742 ret = xhci_alloc_dev(hcd, udev);
3743 if (ret == 1)
3744 return 0;
3745 else
3746 return -EINVAL;
3747 }
3748
3749 /* If device is not setup, there is no point in resetting it */
3750 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3751 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3752 SLOT_STATE_DISABLED)
3753 return 0;
3754
3755 trace_xhci_discover_or_reset_device(slot_ctx);
3756
3757 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3758 /* Allocate the command structure that holds the struct completion.
3759 * Assume we're in process context, since the normal device reset
3760 * process has to wait for the device anyway. Storage devices are
3761 * reset as part of error handling, so use GFP_NOIO instead of
3762 * GFP_KERNEL.
3763 */
3764 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3765 if (!reset_device_cmd) {
3766 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3767 return -ENOMEM;
3768 }
3769
3770 /* Attempt to submit the Reset Device command to the command ring */
3771 spin_lock_irqsave(&xhci->lock, flags);
3772
3773 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3774 if (ret) {
3775 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3776 spin_unlock_irqrestore(&xhci->lock, flags);
3777 goto command_cleanup;
3778 }
3779 xhci_ring_cmd_db(xhci);
3780 spin_unlock_irqrestore(&xhci->lock, flags);
3781
3782 /* Wait for the Reset Device command to finish */
3783 wait_for_completion(reset_device_cmd->completion);
3784
3785 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3786 * unless we tried to reset a slot ID that wasn't enabled,
3787 * or the device wasn't in the addressed or configured state.
3788 */
3789 ret = reset_device_cmd->status;
3790 switch (ret) {
3791 case COMP_COMMAND_ABORTED:
3792 case COMP_COMMAND_RING_STOPPED:
3793 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3794 ret = -ETIME;
3795 goto command_cleanup;
3796 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3797 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3798 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3799 slot_id,
3800 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3801 xhci_dbg(xhci, "Not freeing device rings.\n");
3802 /* Don't treat this as an error. May change my mind later. */
3803 ret = 0;
3804 goto command_cleanup;
3805 case COMP_SUCCESS:
3806 xhci_dbg(xhci, "Successful reset device command.\n");
3807 break;
3808 default:
3809 if (xhci_is_vendor_info_code(xhci, ret))
3810 break;
3811 xhci_warn(xhci, "Unknown completion code %u for "
3812 "reset device command.\n", ret);
3813 ret = -EINVAL;
3814 goto command_cleanup;
3815 }
3816
3817 /* Free up host controller endpoint resources */
3818 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3819 spin_lock_irqsave(&xhci->lock, flags);
3820 /* Don't delete the default control endpoint resources */
3821 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3822 spin_unlock_irqrestore(&xhci->lock, flags);
3823 }
3824
3825 /* Everything but endpoint 0 is disabled, so free the rings. */
3826 for (i = 1; i < 31; i++) {
3827 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3828
3829 if (ep->ep_state & EP_HAS_STREAMS) {
3830 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3831 xhci_get_endpoint_address(i));
3832 xhci_free_stream_info(xhci, ep->stream_info);
3833 ep->stream_info = NULL;
3834 ep->ep_state &= ~EP_HAS_STREAMS;
3835 }
3836
3837 if (ep->ring) {
3838 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3839 xhci_free_endpoint_ring(xhci, virt_dev, i);
3840 }
3841 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3842 xhci_drop_ep_from_interval_table(xhci,
3843 &virt_dev->eps[i].bw_info,
3844 virt_dev->bw_table,
3845 udev,
3846 &virt_dev->eps[i],
3847 virt_dev->tt_info);
3848 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3849 }
3850 /* If necessary, update the number of active TTs on this root port */
3851 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3852 virt_dev->flags = 0;
3853 ret = 0;
3854
3855command_cleanup:
3856 xhci_free_command(xhci, reset_device_cmd);
3857 return ret;
3858}
3859
3860/*
3861 * At this point, the struct usb_device is about to go away, the device has
3862 * disconnected, and all traffic has been stopped and the endpoints have been
3863 * disabled. Free any HC data structures associated with that device.
3864 */
3865static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3866{
3867 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3868 struct xhci_virt_device *virt_dev;
3869 struct xhci_slot_ctx *slot_ctx;
3870 unsigned long flags;
3871 int i, ret;
3872
3873 /*
3874 * We called pm_runtime_get_noresume when the device was attached.
3875 * Decrement the counter here to allow controller to runtime suspend
3876 * if no devices remain.
3877 */
3878 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3879 pm_runtime_put_noidle(hcd->self.controller);
3880
3881 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3882 /* If the host is halted due to driver unload, we still need to free the
3883 * device.
3884 */
3885 if (ret <= 0 && ret != -ENODEV)
3886 return;
3887
3888 virt_dev = xhci->devs[udev->slot_id];
3889 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3890 trace_xhci_free_dev(slot_ctx);
3891
3892 /* Stop any wayward timer functions (which may grab the lock) */
3893 for (i = 0; i < 31; i++)
3894 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3895 virt_dev->udev = NULL;
3896 xhci_disable_slot(xhci, udev->slot_id);
3897
3898 spin_lock_irqsave(&xhci->lock, flags);
3899 xhci_free_virt_device(xhci, udev->slot_id);
3900 spin_unlock_irqrestore(&xhci->lock, flags);
3901
3902}
3903
3904int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3905{
3906 struct xhci_command *command;
3907 unsigned long flags;
3908 u32 state;
3909 int ret;
3910
3911 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3912 if (!command)
3913 return -ENOMEM;
3914
3915 xhci_debugfs_remove_slot(xhci, slot_id);
3916
3917 spin_lock_irqsave(&xhci->lock, flags);
3918 /* Don't disable the slot if the host controller is dead. */
3919 state = readl(&xhci->op_regs->status);
3920 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3921 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3922 spin_unlock_irqrestore(&xhci->lock, flags);
3923 kfree(command);
3924 return -ENODEV;
3925 }
3926
3927 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3928 slot_id);
3929 if (ret) {
3930 spin_unlock_irqrestore(&xhci->lock, flags);
3931 kfree(command);
3932 return ret;
3933 }
3934 xhci_ring_cmd_db(xhci);
3935 spin_unlock_irqrestore(&xhci->lock, flags);
3936
3937 wait_for_completion(command->completion);
3938
3939 if (command->status != COMP_SUCCESS)
3940 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
3941 slot_id, command->status);
3942
3943 xhci_free_command(xhci, command);
3944
3945 return 0;
3946}
3947
3948/*
3949 * Checks if we have enough host controller resources for the default control
3950 * endpoint.
3951 *
3952 * Must be called with xhci->lock held.
3953 */
3954static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3955{
3956 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3957 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3958 "Not enough ep ctxs: "
3959 "%u active, need to add 1, limit is %u.",
3960 xhci->num_active_eps, xhci->limit_active_eps);
3961 return -ENOMEM;
3962 }
3963 xhci->num_active_eps += 1;
3964 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3965 "Adding 1 ep ctx, %u now active.",
3966 xhci->num_active_eps);
3967 return 0;
3968}
3969
3970
3971/*
3972 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3973 * timed out, or allocating memory failed. Returns 1 on success.
3974 */
3975int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3976{
3977 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3978 struct xhci_virt_device *vdev;
3979 struct xhci_slot_ctx *slot_ctx;
3980 unsigned long flags;
3981 int ret, slot_id;
3982 struct xhci_command *command;
3983
3984 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3985 if (!command)
3986 return 0;
3987
3988 spin_lock_irqsave(&xhci->lock, flags);
3989 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3990 if (ret) {
3991 spin_unlock_irqrestore(&xhci->lock, flags);
3992 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3993 xhci_free_command(xhci, command);
3994 return 0;
3995 }
3996 xhci_ring_cmd_db(xhci);
3997 spin_unlock_irqrestore(&xhci->lock, flags);
3998
3999 wait_for_completion(command->completion);
4000 slot_id = command->slot_id;
4001
4002 if (!slot_id || command->status != COMP_SUCCESS) {
4003 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4004 xhci_trb_comp_code_string(command->status));
4005 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4006 HCS_MAX_SLOTS(
4007 readl(&xhci->cap_regs->hcs_params1)));
4008 xhci_free_command(xhci, command);
4009 return 0;
4010 }
4011
4012 xhci_free_command(xhci, command);
4013
4014 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4015 spin_lock_irqsave(&xhci->lock, flags);
4016 ret = xhci_reserve_host_control_ep_resources(xhci);
4017 if (ret) {
4018 spin_unlock_irqrestore(&xhci->lock, flags);
4019 xhci_warn(xhci, "Not enough host resources, "
4020 "active endpoint contexts = %u\n",
4021 xhci->num_active_eps);
4022 goto disable_slot;
4023 }
4024 spin_unlock_irqrestore(&xhci->lock, flags);
4025 }
4026 /* Use GFP_NOIO, since this function can be called from
4027 * xhci_discover_or_reset_device(), which may be called as part of
4028 * mass storage driver error handling.
4029 */
4030 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4031 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4032 goto disable_slot;
4033 }
4034 vdev = xhci->devs[slot_id];
4035 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4036 trace_xhci_alloc_dev(slot_ctx);
4037
4038 udev->slot_id = slot_id;
4039
4040 xhci_debugfs_create_slot(xhci, slot_id);
4041
4042 /*
4043 * If resetting upon resume, we can't put the controller into runtime
4044 * suspend if there is a device attached.
4045 */
4046 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4047 pm_runtime_get_noresume(hcd->self.controller);
4048
4049 /* Is this a LS or FS device under a HS hub? */
4050 /* Hub or peripherial? */
4051 return 1;
4052
4053disable_slot:
4054 xhci_disable_slot(xhci, udev->slot_id);
4055 xhci_free_virt_device(xhci, udev->slot_id);
4056
4057 return 0;
4058}
4059
4060/**
4061 * xhci_setup_device - issues an Address Device command to assign a unique
4062 * USB bus address.
4063 * @hcd: USB host controller data structure.
4064 * @udev: USB dev structure representing the connected device.
4065 * @setup: Enum specifying setup mode: address only or with context.
4066 * @timeout_ms: Max wait time (ms) for the command operation to complete.
4067 *
4068 * Return: 0 if successful; otherwise, negative error code.
4069 */
4070static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4071 enum xhci_setup_dev setup, unsigned int timeout_ms)
4072{
4073 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4074 unsigned long flags;
4075 struct xhci_virt_device *virt_dev;
4076 int ret = 0;
4077 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4078 struct xhci_slot_ctx *slot_ctx;
4079 struct xhci_input_control_ctx *ctrl_ctx;
4080 u64 temp_64;
4081 struct xhci_command *command = NULL;
4082
4083 mutex_lock(&xhci->mutex);
4084
4085 if (xhci->xhc_state) { /* dying, removing or halted */
4086 ret = -ESHUTDOWN;
4087 goto out;
4088 }
4089
4090 if (!udev->slot_id) {
4091 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4092 "Bad Slot ID %d", udev->slot_id);
4093 ret = -EINVAL;
4094 goto out;
4095 }
4096
4097 virt_dev = xhci->devs[udev->slot_id];
4098
4099 if (WARN_ON(!virt_dev)) {
4100 /*
4101 * In plug/unplug torture test with an NEC controller,
4102 * a zero-dereference was observed once due to virt_dev = 0.
4103 * Print useful debug rather than crash if it is observed again!
4104 */
4105 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4106 udev->slot_id);
4107 ret = -EINVAL;
4108 goto out;
4109 }
4110 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4111 trace_xhci_setup_device_slot(slot_ctx);
4112
4113 if (setup == SETUP_CONTEXT_ONLY) {
4114 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4115 SLOT_STATE_DEFAULT) {
4116 xhci_dbg(xhci, "Slot already in default state\n");
4117 goto out;
4118 }
4119 }
4120
4121 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4122 if (!command) {
4123 ret = -ENOMEM;
4124 goto out;
4125 }
4126
4127 command->in_ctx = virt_dev->in_ctx;
4128 command->timeout_ms = timeout_ms;
4129
4130 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4131 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4132 if (!ctrl_ctx) {
4133 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4134 __func__);
4135 ret = -EINVAL;
4136 goto out;
4137 }
4138 /*
4139 * If this is the first Set Address since device plug-in or
4140 * virt_device realloaction after a resume with an xHCI power loss,
4141 * then set up the slot context.
4142 */
4143 if (!slot_ctx->dev_info)
4144 xhci_setup_addressable_virt_dev(xhci, udev);
4145 /* Otherwise, update the control endpoint ring enqueue pointer. */
4146 else
4147 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4148 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4149 ctrl_ctx->drop_flags = 0;
4150
4151 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4152 le32_to_cpu(slot_ctx->dev_info) >> 27);
4153
4154 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4155 spin_lock_irqsave(&xhci->lock, flags);
4156 trace_xhci_setup_device(virt_dev);
4157 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4158 udev->slot_id, setup);
4159 if (ret) {
4160 spin_unlock_irqrestore(&xhci->lock, flags);
4161 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4162 "FIXME: allocate a command ring segment");
4163 goto out;
4164 }
4165 xhci_ring_cmd_db(xhci);
4166 spin_unlock_irqrestore(&xhci->lock, flags);
4167
4168 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4169 wait_for_completion(command->completion);
4170
4171 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4172 * the SetAddress() "recovery interval" required by USB and aborting the
4173 * command on a timeout.
4174 */
4175 switch (command->status) {
4176 case COMP_COMMAND_ABORTED:
4177 case COMP_COMMAND_RING_STOPPED:
4178 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4179 ret = -ETIME;
4180 break;
4181 case COMP_CONTEXT_STATE_ERROR:
4182 case COMP_SLOT_NOT_ENABLED_ERROR:
4183 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4184 act, udev->slot_id);
4185 ret = -EINVAL;
4186 break;
4187 case COMP_USB_TRANSACTION_ERROR:
4188 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4189
4190 mutex_unlock(&xhci->mutex);
4191 ret = xhci_disable_slot(xhci, udev->slot_id);
4192 xhci_free_virt_device(xhci, udev->slot_id);
4193 if (!ret)
4194 xhci_alloc_dev(hcd, udev);
4195 kfree(command->completion);
4196 kfree(command);
4197 return -EPROTO;
4198 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4199 dev_warn(&udev->dev,
4200 "ERROR: Incompatible device for setup %s command\n", act);
4201 ret = -ENODEV;
4202 break;
4203 case COMP_SUCCESS:
4204 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4205 "Successful setup %s command", act);
4206 break;
4207 default:
4208 xhci_err(xhci,
4209 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4210 act, command->status);
4211 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4212 ret = -EINVAL;
4213 break;
4214 }
4215 if (ret)
4216 goto out;
4217 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4218 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4219 "Op regs DCBAA ptr = %#016llx", temp_64);
4220 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4221 "Slot ID %d dcbaa entry @%p = %#016llx",
4222 udev->slot_id,
4223 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4224 (unsigned long long)
4225 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4226 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4227 "Output Context DMA address = %#08llx",
4228 (unsigned long long)virt_dev->out_ctx->dma);
4229 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4230 le32_to_cpu(slot_ctx->dev_info) >> 27);
4231 /*
4232 * USB core uses address 1 for the roothubs, so we add one to the
4233 * address given back to us by the HC.
4234 */
4235 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4236 le32_to_cpu(slot_ctx->dev_info) >> 27);
4237 /* Zero the input context control for later use */
4238 ctrl_ctx->add_flags = 0;
4239 ctrl_ctx->drop_flags = 0;
4240 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4241 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4242
4243 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4244 "Internal device address = %d",
4245 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4246out:
4247 mutex_unlock(&xhci->mutex);
4248 if (command) {
4249 kfree(command->completion);
4250 kfree(command);
4251 }
4252 return ret;
4253}
4254
4255static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev,
4256 unsigned int timeout_ms)
4257{
4258 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS, timeout_ms);
4259}
4260
4261static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4262{
4263 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY,
4264 XHCI_CMD_DEFAULT_TIMEOUT);
4265}
4266
4267/*
4268 * Transfer the port index into real index in the HW port status
4269 * registers. Caculate offset between the port's PORTSC register
4270 * and port status base. Divide the number of per port register
4271 * to get the real index. The raw port number bases 1.
4272 */
4273int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4274{
4275 struct xhci_hub *rhub;
4276
4277 rhub = xhci_get_rhub(hcd);
4278 return rhub->ports[port1 - 1]->hw_portnum + 1;
4279}
4280
4281/*
4282 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4283 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4284 */
4285static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4286 struct usb_device *udev, u16 max_exit_latency)
4287{
4288 struct xhci_virt_device *virt_dev;
4289 struct xhci_command *command;
4290 struct xhci_input_control_ctx *ctrl_ctx;
4291 struct xhci_slot_ctx *slot_ctx;
4292 unsigned long flags;
4293 int ret;
4294
4295 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4296 if (!command)
4297 return -ENOMEM;
4298
4299 spin_lock_irqsave(&xhci->lock, flags);
4300
4301 virt_dev = xhci->devs[udev->slot_id];
4302
4303 /*
4304 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4305 * xHC was re-initialized. Exit latency will be set later after
4306 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4307 */
4308
4309 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4310 spin_unlock_irqrestore(&xhci->lock, flags);
4311 xhci_free_command(xhci, command);
4312 return 0;
4313 }
4314
4315 /* Attempt to issue an Evaluate Context command to change the MEL. */
4316 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4317 if (!ctrl_ctx) {
4318 spin_unlock_irqrestore(&xhci->lock, flags);
4319 xhci_free_command(xhci, command);
4320 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4321 __func__);
4322 return -ENOMEM;
4323 }
4324
4325 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4326 spin_unlock_irqrestore(&xhci->lock, flags);
4327
4328 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4329 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4330 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4331 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4332 slot_ctx->dev_state = 0;
4333
4334 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4335 "Set up evaluate context for LPM MEL change.");
4336
4337 /* Issue and wait for the evaluate context command. */
4338 ret = xhci_configure_endpoint(xhci, udev, command,
4339 true, true);
4340
4341 if (!ret) {
4342 spin_lock_irqsave(&xhci->lock, flags);
4343 virt_dev->current_mel = max_exit_latency;
4344 spin_unlock_irqrestore(&xhci->lock, flags);
4345 }
4346
4347 xhci_free_command(xhci, command);
4348
4349 return ret;
4350}
4351
4352#ifdef CONFIG_PM
4353
4354/* BESL to HIRD Encoding array for USB2 LPM */
4355static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4356 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4357
4358/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4359static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4360 struct usb_device *udev)
4361{
4362 int u2del, besl, besl_host;
4363 int besl_device = 0;
4364 u32 field;
4365
4366 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4367 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4368
4369 if (field & USB_BESL_SUPPORT) {
4370 for (besl_host = 0; besl_host < 16; besl_host++) {
4371 if (xhci_besl_encoding[besl_host] >= u2del)
4372 break;
4373 }
4374 /* Use baseline BESL value as default */
4375 if (field & USB_BESL_BASELINE_VALID)
4376 besl_device = USB_GET_BESL_BASELINE(field);
4377 else if (field & USB_BESL_DEEP_VALID)
4378 besl_device = USB_GET_BESL_DEEP(field);
4379 } else {
4380 if (u2del <= 50)
4381 besl_host = 0;
4382 else
4383 besl_host = (u2del - 51) / 75 + 1;
4384 }
4385
4386 besl = besl_host + besl_device;
4387 if (besl > 15)
4388 besl = 15;
4389
4390 return besl;
4391}
4392
4393/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4394static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4395{
4396 u32 field;
4397 int l1;
4398 int besld = 0;
4399 int hirdm = 0;
4400
4401 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4402
4403 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4404 l1 = udev->l1_params.timeout / 256;
4405
4406 /* device has preferred BESLD */
4407 if (field & USB_BESL_DEEP_VALID) {
4408 besld = USB_GET_BESL_DEEP(field);
4409 hirdm = 1;
4410 }
4411
4412 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4413}
4414
4415static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4416 struct usb_device *udev, int enable)
4417{
4418 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4419 struct xhci_port **ports;
4420 __le32 __iomem *pm_addr, *hlpm_addr;
4421 u32 pm_val, hlpm_val, field;
4422 unsigned int port_num;
4423 unsigned long flags;
4424 int hird, exit_latency;
4425 int ret;
4426
4427 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4428 return -EPERM;
4429
4430 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4431 !udev->lpm_capable)
4432 return -EPERM;
4433
4434 if (!udev->parent || udev->parent->parent ||
4435 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4436 return -EPERM;
4437
4438 if (udev->usb2_hw_lpm_capable != 1)
4439 return -EPERM;
4440
4441 spin_lock_irqsave(&xhci->lock, flags);
4442
4443 ports = xhci->usb2_rhub.ports;
4444 port_num = udev->portnum - 1;
4445 pm_addr = ports[port_num]->addr + PORTPMSC;
4446 pm_val = readl(pm_addr);
4447 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4448
4449 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4450 enable ? "enable" : "disable", port_num + 1);
4451
4452 if (enable) {
4453 /* Host supports BESL timeout instead of HIRD */
4454 if (udev->usb2_hw_lpm_besl_capable) {
4455 /* if device doesn't have a preferred BESL value use a
4456 * default one which works with mixed HIRD and BESL
4457 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4458 */
4459 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4460 if ((field & USB_BESL_SUPPORT) &&
4461 (field & USB_BESL_BASELINE_VALID))
4462 hird = USB_GET_BESL_BASELINE(field);
4463 else
4464 hird = udev->l1_params.besl;
4465
4466 exit_latency = xhci_besl_encoding[hird];
4467 spin_unlock_irqrestore(&xhci->lock, flags);
4468
4469 ret = xhci_change_max_exit_latency(xhci, udev,
4470 exit_latency);
4471 if (ret < 0)
4472 return ret;
4473 spin_lock_irqsave(&xhci->lock, flags);
4474
4475 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4476 writel(hlpm_val, hlpm_addr);
4477 /* flush write */
4478 readl(hlpm_addr);
4479 } else {
4480 hird = xhci_calculate_hird_besl(xhci, udev);
4481 }
4482
4483 pm_val &= ~PORT_HIRD_MASK;
4484 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4485 writel(pm_val, pm_addr);
4486 pm_val = readl(pm_addr);
4487 pm_val |= PORT_HLE;
4488 writel(pm_val, pm_addr);
4489 /* flush write */
4490 readl(pm_addr);
4491 } else {
4492 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4493 writel(pm_val, pm_addr);
4494 /* flush write */
4495 readl(pm_addr);
4496 if (udev->usb2_hw_lpm_besl_capable) {
4497 spin_unlock_irqrestore(&xhci->lock, flags);
4498 xhci_change_max_exit_latency(xhci, udev, 0);
4499 readl_poll_timeout(ports[port_num]->addr, pm_val,
4500 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4501 100, 10000);
4502 return 0;
4503 }
4504 }
4505
4506 spin_unlock_irqrestore(&xhci->lock, flags);
4507 return 0;
4508}
4509
4510/* check if a usb2 port supports a given extened capability protocol
4511 * only USB2 ports extended protocol capability values are cached.
4512 * Return 1 if capability is supported
4513 */
4514static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4515 unsigned capability)
4516{
4517 u32 port_offset, port_count;
4518 int i;
4519
4520 for (i = 0; i < xhci->num_ext_caps; i++) {
4521 if (xhci->ext_caps[i] & capability) {
4522 /* port offsets starts at 1 */
4523 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4524 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4525 if (port >= port_offset &&
4526 port < port_offset + port_count)
4527 return 1;
4528 }
4529 }
4530 return 0;
4531}
4532
4533static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4534{
4535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4536 int portnum = udev->portnum - 1;
4537
4538 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4539 return 0;
4540
4541 /* we only support lpm for non-hub device connected to root hub yet */
4542 if (!udev->parent || udev->parent->parent ||
4543 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4544 return 0;
4545
4546 if (xhci->hw_lpm_support == 1 &&
4547 xhci_check_usb2_port_capability(
4548 xhci, portnum, XHCI_HLC)) {
4549 udev->usb2_hw_lpm_capable = 1;
4550 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4551 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4552 if (xhci_check_usb2_port_capability(xhci, portnum,
4553 XHCI_BLC))
4554 udev->usb2_hw_lpm_besl_capable = 1;
4555 }
4556
4557 return 0;
4558}
4559
4560/*---------------------- USB 3.0 Link PM functions ------------------------*/
4561
4562/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4563static unsigned long long xhci_service_interval_to_ns(
4564 struct usb_endpoint_descriptor *desc)
4565{
4566 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4567}
4568
4569static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4570 enum usb3_link_state state)
4571{
4572 unsigned long long sel;
4573 unsigned long long pel;
4574 unsigned int max_sel_pel;
4575 char *state_name;
4576
4577 switch (state) {
4578 case USB3_LPM_U1:
4579 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4580 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4581 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4582 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4583 state_name = "U1";
4584 break;
4585 case USB3_LPM_U2:
4586 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4587 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4588 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4589 state_name = "U2";
4590 break;
4591 default:
4592 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4593 __func__);
4594 return USB3_LPM_DISABLED;
4595 }
4596
4597 if (sel <= max_sel_pel && pel <= max_sel_pel)
4598 return USB3_LPM_DEVICE_INITIATED;
4599
4600 if (sel > max_sel_pel)
4601 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4602 "due to long SEL %llu ms\n",
4603 state_name, sel);
4604 else
4605 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4606 "due to long PEL %llu ms\n",
4607 state_name, pel);
4608 return USB3_LPM_DISABLED;
4609}
4610
4611/* The U1 timeout should be the maximum of the following values:
4612 * - For control endpoints, U1 system exit latency (SEL) * 3
4613 * - For bulk endpoints, U1 SEL * 5
4614 * - For interrupt endpoints:
4615 * - Notification EPs, U1 SEL * 3
4616 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4617 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4618 */
4619static unsigned long long xhci_calculate_intel_u1_timeout(
4620 struct usb_device *udev,
4621 struct usb_endpoint_descriptor *desc)
4622{
4623 unsigned long long timeout_ns;
4624 int ep_type;
4625 int intr_type;
4626
4627 ep_type = usb_endpoint_type(desc);
4628 switch (ep_type) {
4629 case USB_ENDPOINT_XFER_CONTROL:
4630 timeout_ns = udev->u1_params.sel * 3;
4631 break;
4632 case USB_ENDPOINT_XFER_BULK:
4633 timeout_ns = udev->u1_params.sel * 5;
4634 break;
4635 case USB_ENDPOINT_XFER_INT:
4636 intr_type = usb_endpoint_interrupt_type(desc);
4637 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4638 timeout_ns = udev->u1_params.sel * 3;
4639 break;
4640 }
4641 /* Otherwise the calculation is the same as isoc eps */
4642 fallthrough;
4643 case USB_ENDPOINT_XFER_ISOC:
4644 timeout_ns = xhci_service_interval_to_ns(desc);
4645 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4646 if (timeout_ns < udev->u1_params.sel * 2)
4647 timeout_ns = udev->u1_params.sel * 2;
4648 break;
4649 default:
4650 return 0;
4651 }
4652
4653 return timeout_ns;
4654}
4655
4656/* Returns the hub-encoded U1 timeout value. */
4657static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4658 struct usb_device *udev,
4659 struct usb_endpoint_descriptor *desc)
4660{
4661 unsigned long long timeout_ns;
4662
4663 /* Prevent U1 if service interval is shorter than U1 exit latency */
4664 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4665 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4666 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4667 return USB3_LPM_DISABLED;
4668 }
4669 }
4670
4671 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4672 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4673 else
4674 timeout_ns = udev->u1_params.sel;
4675
4676 /* The U1 timeout is encoded in 1us intervals.
4677 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4678 */
4679 if (timeout_ns == USB3_LPM_DISABLED)
4680 timeout_ns = 1;
4681 else
4682 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4683
4684 /* If the necessary timeout value is bigger than what we can set in the
4685 * USB 3.0 hub, we have to disable hub-initiated U1.
4686 */
4687 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4688 return timeout_ns;
4689 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4690 "due to long timeout %llu ms\n", timeout_ns);
4691 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4692}
4693
4694/* The U2 timeout should be the maximum of:
4695 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4696 * - largest bInterval of any active periodic endpoint (to avoid going
4697 * into lower power link states between intervals).
4698 * - the U2 Exit Latency of the device
4699 */
4700static unsigned long long xhci_calculate_intel_u2_timeout(
4701 struct usb_device *udev,
4702 struct usb_endpoint_descriptor *desc)
4703{
4704 unsigned long long timeout_ns;
4705 unsigned long long u2_del_ns;
4706
4707 timeout_ns = 10 * 1000 * 1000;
4708
4709 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4710 (xhci_service_interval_to_ns(desc) > timeout_ns))
4711 timeout_ns = xhci_service_interval_to_ns(desc);
4712
4713 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4714 if (u2_del_ns > timeout_ns)
4715 timeout_ns = u2_del_ns;
4716
4717 return timeout_ns;
4718}
4719
4720/* Returns the hub-encoded U2 timeout value. */
4721static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4722 struct usb_device *udev,
4723 struct usb_endpoint_descriptor *desc)
4724{
4725 unsigned long long timeout_ns;
4726
4727 /* Prevent U2 if service interval is shorter than U2 exit latency */
4728 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4729 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4730 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4731 return USB3_LPM_DISABLED;
4732 }
4733 }
4734
4735 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4736 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4737 else
4738 timeout_ns = udev->u2_params.sel;
4739
4740 /* The U2 timeout is encoded in 256us intervals */
4741 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4742 /* If the necessary timeout value is bigger than what we can set in the
4743 * USB 3.0 hub, we have to disable hub-initiated U2.
4744 */
4745 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4746 return timeout_ns;
4747 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4748 "due to long timeout %llu ms\n", timeout_ns);
4749 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4750}
4751
4752static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4753 struct usb_device *udev,
4754 struct usb_endpoint_descriptor *desc,
4755 enum usb3_link_state state,
4756 u16 *timeout)
4757{
4758 if (state == USB3_LPM_U1)
4759 return xhci_calculate_u1_timeout(xhci, udev, desc);
4760 else if (state == USB3_LPM_U2)
4761 return xhci_calculate_u2_timeout(xhci, udev, desc);
4762
4763 return USB3_LPM_DISABLED;
4764}
4765
4766static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4767 struct usb_device *udev,
4768 struct usb_endpoint_descriptor *desc,
4769 enum usb3_link_state state,
4770 u16 *timeout)
4771{
4772 u16 alt_timeout;
4773
4774 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4775 desc, state, timeout);
4776
4777 /* If we found we can't enable hub-initiated LPM, and
4778 * the U1 or U2 exit latency was too high to allow
4779 * device-initiated LPM as well, then we will disable LPM
4780 * for this device, so stop searching any further.
4781 */
4782 if (alt_timeout == USB3_LPM_DISABLED) {
4783 *timeout = alt_timeout;
4784 return -E2BIG;
4785 }
4786 if (alt_timeout > *timeout)
4787 *timeout = alt_timeout;
4788 return 0;
4789}
4790
4791static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4792 struct usb_device *udev,
4793 struct usb_host_interface *alt,
4794 enum usb3_link_state state,
4795 u16 *timeout)
4796{
4797 int j;
4798
4799 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4800 if (xhci_update_timeout_for_endpoint(xhci, udev,
4801 &alt->endpoint[j].desc, state, timeout))
4802 return -E2BIG;
4803 }
4804 return 0;
4805}
4806
4807static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4808 struct usb_device *udev,
4809 enum usb3_link_state state)
4810{
4811 struct usb_device *parent = udev->parent;
4812 int tier = 1; /* roothub is tier1 */
4813
4814 while (parent) {
4815 parent = parent->parent;
4816 tier++;
4817 }
4818
4819 if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
4820 goto fail;
4821 if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
4822 goto fail;
4823
4824 return 0;
4825fail:
4826 dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
4827 tier);
4828 return -E2BIG;
4829}
4830
4831/* Returns the U1 or U2 timeout that should be enabled.
4832 * If the tier check or timeout setting functions return with a non-zero exit
4833 * code, that means the timeout value has been finalized and we shouldn't look
4834 * at any more endpoints.
4835 */
4836static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4837 struct usb_device *udev, enum usb3_link_state state)
4838{
4839 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4840 struct usb_host_config *config;
4841 char *state_name;
4842 int i;
4843 u16 timeout = USB3_LPM_DISABLED;
4844
4845 if (state == USB3_LPM_U1)
4846 state_name = "U1";
4847 else if (state == USB3_LPM_U2)
4848 state_name = "U2";
4849 else {
4850 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4851 state);
4852 return timeout;
4853 }
4854
4855 /* Gather some information about the currently installed configuration
4856 * and alternate interface settings.
4857 */
4858 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4859 state, &timeout))
4860 return timeout;
4861
4862 config = udev->actconfig;
4863 if (!config)
4864 return timeout;
4865
4866 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4867 struct usb_driver *driver;
4868 struct usb_interface *intf = config->interface[i];
4869
4870 if (!intf)
4871 continue;
4872
4873 /* Check if any currently bound drivers want hub-initiated LPM
4874 * disabled.
4875 */
4876 if (intf->dev.driver) {
4877 driver = to_usb_driver(intf->dev.driver);
4878 if (driver && driver->disable_hub_initiated_lpm) {
4879 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4880 state_name, driver->name);
4881 timeout = xhci_get_timeout_no_hub_lpm(udev,
4882 state);
4883 if (timeout == USB3_LPM_DISABLED)
4884 return timeout;
4885 }
4886 }
4887
4888 /* Not sure how this could happen... */
4889 if (!intf->cur_altsetting)
4890 continue;
4891
4892 if (xhci_update_timeout_for_interface(xhci, udev,
4893 intf->cur_altsetting,
4894 state, &timeout))
4895 return timeout;
4896 }
4897 return timeout;
4898}
4899
4900static int calculate_max_exit_latency(struct usb_device *udev,
4901 enum usb3_link_state state_changed,
4902 u16 hub_encoded_timeout)
4903{
4904 unsigned long long u1_mel_us = 0;
4905 unsigned long long u2_mel_us = 0;
4906 unsigned long long mel_us = 0;
4907 bool disabling_u1;
4908 bool disabling_u2;
4909 bool enabling_u1;
4910 bool enabling_u2;
4911
4912 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4913 hub_encoded_timeout == USB3_LPM_DISABLED);
4914 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4915 hub_encoded_timeout == USB3_LPM_DISABLED);
4916
4917 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4918 hub_encoded_timeout != USB3_LPM_DISABLED);
4919 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4920 hub_encoded_timeout != USB3_LPM_DISABLED);
4921
4922 /* If U1 was already enabled and we're not disabling it,
4923 * or we're going to enable U1, account for the U1 max exit latency.
4924 */
4925 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4926 enabling_u1)
4927 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4928 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4929 enabling_u2)
4930 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4931
4932 mel_us = max(u1_mel_us, u2_mel_us);
4933
4934 /* xHCI host controller max exit latency field is only 16 bits wide. */
4935 if (mel_us > MAX_EXIT) {
4936 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4937 "is too big.\n", mel_us);
4938 return -E2BIG;
4939 }
4940 return mel_us;
4941}
4942
4943/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4944static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4945 struct usb_device *udev, enum usb3_link_state state)
4946{
4947 struct xhci_hcd *xhci;
4948 struct xhci_port *port;
4949 u16 hub_encoded_timeout;
4950 int mel;
4951 int ret;
4952
4953 xhci = hcd_to_xhci(hcd);
4954 /* The LPM timeout values are pretty host-controller specific, so don't
4955 * enable hub-initiated timeouts unless the vendor has provided
4956 * information about their timeout algorithm.
4957 */
4958 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4959 !xhci->devs[udev->slot_id])
4960 return USB3_LPM_DISABLED;
4961
4962 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4963 return USB3_LPM_DISABLED;
4964
4965 /* If connected to root port then check port can handle lpm */
4966 if (udev->parent && !udev->parent->parent) {
4967 port = xhci->usb3_rhub.ports[udev->portnum - 1];
4968 if (port->lpm_incapable)
4969 return USB3_LPM_DISABLED;
4970 }
4971
4972 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4973 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4974 if (mel < 0) {
4975 /* Max Exit Latency is too big, disable LPM. */
4976 hub_encoded_timeout = USB3_LPM_DISABLED;
4977 mel = 0;
4978 }
4979
4980 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4981 if (ret)
4982 return ret;
4983 return hub_encoded_timeout;
4984}
4985
4986static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4987 struct usb_device *udev, enum usb3_link_state state)
4988{
4989 struct xhci_hcd *xhci;
4990 u16 mel;
4991
4992 xhci = hcd_to_xhci(hcd);
4993 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4994 !xhci->devs[udev->slot_id])
4995 return 0;
4996
4997 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4998 return xhci_change_max_exit_latency(xhci, udev, mel);
4999}
5000#else /* CONFIG_PM */
5001
5002static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5003 struct usb_device *udev, int enable)
5004{
5005 return 0;
5006}
5007
5008static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5009{
5010 return 0;
5011}
5012
5013static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5014 struct usb_device *udev, enum usb3_link_state state)
5015{
5016 return USB3_LPM_DISABLED;
5017}
5018
5019static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5020 struct usb_device *udev, enum usb3_link_state state)
5021{
5022 return 0;
5023}
5024#endif /* CONFIG_PM */
5025
5026/*-------------------------------------------------------------------------*/
5027
5028/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5029 * internal data structures for the device.
5030 */
5031int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5032 struct usb_tt *tt, gfp_t mem_flags)
5033{
5034 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5035 struct xhci_virt_device *vdev;
5036 struct xhci_command *config_cmd;
5037 struct xhci_input_control_ctx *ctrl_ctx;
5038 struct xhci_slot_ctx *slot_ctx;
5039 unsigned long flags;
5040 unsigned think_time;
5041 int ret;
5042
5043 /* Ignore root hubs */
5044 if (!hdev->parent)
5045 return 0;
5046
5047 vdev = xhci->devs[hdev->slot_id];
5048 if (!vdev) {
5049 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5050 return -EINVAL;
5051 }
5052
5053 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5054 if (!config_cmd)
5055 return -ENOMEM;
5056
5057 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5058 if (!ctrl_ctx) {
5059 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5060 __func__);
5061 xhci_free_command(xhci, config_cmd);
5062 return -ENOMEM;
5063 }
5064
5065 spin_lock_irqsave(&xhci->lock, flags);
5066 if (hdev->speed == USB_SPEED_HIGH &&
5067 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5068 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5069 xhci_free_command(xhci, config_cmd);
5070 spin_unlock_irqrestore(&xhci->lock, flags);
5071 return -ENOMEM;
5072 }
5073
5074 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5075 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5076 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5077 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5078 /*
5079 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5080 * but it may be already set to 1 when setup an xHCI virtual
5081 * device, so clear it anyway.
5082 */
5083 if (tt->multi)
5084 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5085 else if (hdev->speed == USB_SPEED_FULL)
5086 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5087
5088 if (xhci->hci_version > 0x95) {
5089 xhci_dbg(xhci, "xHCI version %x needs hub "
5090 "TT think time and number of ports\n",
5091 (unsigned int) xhci->hci_version);
5092 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5093 /* Set TT think time - convert from ns to FS bit times.
5094 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5095 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5096 *
5097 * xHCI 1.0: this field shall be 0 if the device is not a
5098 * High-spped hub.
5099 */
5100 think_time = tt->think_time;
5101 if (think_time != 0)
5102 think_time = (think_time / 666) - 1;
5103 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5104 slot_ctx->tt_info |=
5105 cpu_to_le32(TT_THINK_TIME(think_time));
5106 } else {
5107 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5108 "TT think time or number of ports\n",
5109 (unsigned int) xhci->hci_version);
5110 }
5111 slot_ctx->dev_state = 0;
5112 spin_unlock_irqrestore(&xhci->lock, flags);
5113
5114 xhci_dbg(xhci, "Set up %s for hub device.\n",
5115 (xhci->hci_version > 0x95) ?
5116 "configure endpoint" : "evaluate context");
5117
5118 /* Issue and wait for the configure endpoint or
5119 * evaluate context command.
5120 */
5121 if (xhci->hci_version > 0x95)
5122 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5123 false, false);
5124 else
5125 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5126 true, false);
5127
5128 xhci_free_command(xhci, config_cmd);
5129 return ret;
5130}
5131EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5132
5133static int xhci_get_frame(struct usb_hcd *hcd)
5134{
5135 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5136 /* EHCI mods by the periodic size. Why? */
5137 return readl(&xhci->run_regs->microframe_index) >> 3;
5138}
5139
5140static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5141{
5142 xhci->usb2_rhub.hcd = hcd;
5143 hcd->speed = HCD_USB2;
5144 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5145 /*
5146 * USB 2.0 roothub under xHCI has an integrated TT,
5147 * (rate matching hub) as opposed to having an OHCI/UHCI
5148 * companion controller.
5149 */
5150 hcd->has_tt = 1;
5151}
5152
5153static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5154{
5155 unsigned int minor_rev;
5156
5157 /*
5158 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5159 * should return 0x31 for sbrn, or that the minor revision
5160 * is a two digit BCD containig minor and sub-minor numbers.
5161 * This was later clarified in xHCI 1.2.
5162 *
5163 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5164 * minor revision set to 0x1 instead of 0x10.
5165 */
5166 if (xhci->usb3_rhub.min_rev == 0x1)
5167 minor_rev = 1;
5168 else
5169 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5170
5171 switch (minor_rev) {
5172 case 2:
5173 hcd->speed = HCD_USB32;
5174 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5175 hcd->self.root_hub->rx_lanes = 2;
5176 hcd->self.root_hub->tx_lanes = 2;
5177 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5178 break;
5179 case 1:
5180 hcd->speed = HCD_USB31;
5181 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5182 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5183 break;
5184 }
5185 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5186 minor_rev, minor_rev ? "Enhanced " : "");
5187
5188 xhci->usb3_rhub.hcd = hcd;
5189}
5190
5191int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5192{
5193 struct xhci_hcd *xhci;
5194 /*
5195 * TODO: Check with DWC3 clients for sysdev according to
5196 * quirks
5197 */
5198 struct device *dev = hcd->self.sysdev;
5199 int retval;
5200
5201 /* Accept arbitrarily long scatter-gather lists */
5202 hcd->self.sg_tablesize = ~0;
5203
5204 /* support to build packet from discontinuous buffers */
5205 hcd->self.no_sg_constraint = 1;
5206
5207 /* XHCI controllers don't stop the ep queue on short packets :| */
5208 hcd->self.no_stop_on_short = 1;
5209
5210 xhci = hcd_to_xhci(hcd);
5211
5212 if (!usb_hcd_is_primary_hcd(hcd)) {
5213 xhci_hcd_init_usb3_data(xhci, hcd);
5214 return 0;
5215 }
5216
5217 mutex_init(&xhci->mutex);
5218 xhci->main_hcd = hcd;
5219 xhci->cap_regs = hcd->regs;
5220 xhci->op_regs = hcd->regs +
5221 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5222 xhci->run_regs = hcd->regs +
5223 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5224 /* Cache read-only capability registers */
5225 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5226 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5227 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5228 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5229 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5230 if (xhci->hci_version > 0x100)
5231 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5232
5233 /* xhci-plat or xhci-pci might have set max_interrupters already */
5234 if ((!xhci->max_interrupters) ||
5235 xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5236 xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5237
5238 xhci->quirks |= quirks;
5239
5240 if (get_quirks)
5241 get_quirks(dev, xhci);
5242
5243 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5244 * success event after a short transfer. This quirk will ignore such
5245 * spurious event.
5246 */
5247 if (xhci->hci_version > 0x96)
5248 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5249
5250 /* Make sure the HC is halted. */
5251 retval = xhci_halt(xhci);
5252 if (retval)
5253 return retval;
5254
5255 xhci_zero_64b_regs(xhci);
5256
5257 xhci_dbg(xhci, "Resetting HCD\n");
5258 /* Reset the internal HC memory state and registers. */
5259 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5260 if (retval)
5261 return retval;
5262 xhci_dbg(xhci, "Reset complete\n");
5263
5264 /*
5265 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5266 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5267 * address memory pointers actually. So, this driver clears the AC64
5268 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5269 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5270 */
5271 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5272 xhci->hcc_params &= ~BIT(0);
5273
5274 /* Set dma_mask and coherent_dma_mask to 64-bits,
5275 * if xHC supports 64-bit addressing */
5276 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5277 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5278 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5279 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5280 } else {
5281 /*
5282 * This is to avoid error in cases where a 32-bit USB
5283 * controller is used on a 64-bit capable system.
5284 */
5285 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5286 if (retval)
5287 return retval;
5288 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5289 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5290 }
5291
5292 xhci_dbg(xhci, "Calling HCD init\n");
5293 /* Initialize HCD and host controller data structures. */
5294 retval = xhci_init(hcd);
5295 if (retval)
5296 return retval;
5297 xhci_dbg(xhci, "Called HCD init\n");
5298
5299 if (xhci_hcd_is_usb3(hcd))
5300 xhci_hcd_init_usb3_data(xhci, hcd);
5301 else
5302 xhci_hcd_init_usb2_data(xhci, hcd);
5303
5304 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5305 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5306
5307 return 0;
5308}
5309EXPORT_SYMBOL_GPL(xhci_gen_setup);
5310
5311static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5312 struct usb_host_endpoint *ep)
5313{
5314 struct xhci_hcd *xhci;
5315 struct usb_device *udev;
5316 unsigned int slot_id;
5317 unsigned int ep_index;
5318 unsigned long flags;
5319
5320 xhci = hcd_to_xhci(hcd);
5321
5322 spin_lock_irqsave(&xhci->lock, flags);
5323 udev = (struct usb_device *)ep->hcpriv;
5324 slot_id = udev->slot_id;
5325 ep_index = xhci_get_endpoint_index(&ep->desc);
5326
5327 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5328 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5329 spin_unlock_irqrestore(&xhci->lock, flags);
5330}
5331
5332static const struct hc_driver xhci_hc_driver = {
5333 .description = "xhci-hcd",
5334 .product_desc = "xHCI Host Controller",
5335 .hcd_priv_size = sizeof(struct xhci_hcd),
5336
5337 /*
5338 * generic hardware linkage
5339 */
5340 .irq = xhci_irq,
5341 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5342 HCD_BH,
5343
5344 /*
5345 * basic lifecycle operations
5346 */
5347 .reset = NULL, /* set in xhci_init_driver() */
5348 .start = xhci_run,
5349 .stop = xhci_stop,
5350 .shutdown = xhci_shutdown,
5351
5352 /*
5353 * managing i/o requests and associated device resources
5354 */
5355 .map_urb_for_dma = xhci_map_urb_for_dma,
5356 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5357 .urb_enqueue = xhci_urb_enqueue,
5358 .urb_dequeue = xhci_urb_dequeue,
5359 .alloc_dev = xhci_alloc_dev,
5360 .free_dev = xhci_free_dev,
5361 .alloc_streams = xhci_alloc_streams,
5362 .free_streams = xhci_free_streams,
5363 .add_endpoint = xhci_add_endpoint,
5364 .drop_endpoint = xhci_drop_endpoint,
5365 .endpoint_disable = xhci_endpoint_disable,
5366 .endpoint_reset = xhci_endpoint_reset,
5367 .check_bandwidth = xhci_check_bandwidth,
5368 .reset_bandwidth = xhci_reset_bandwidth,
5369 .address_device = xhci_address_device,
5370 .enable_device = xhci_enable_device,
5371 .update_hub_device = xhci_update_hub_device,
5372 .reset_device = xhci_discover_or_reset_device,
5373
5374 /*
5375 * scheduling support
5376 */
5377 .get_frame_number = xhci_get_frame,
5378
5379 /*
5380 * root hub support
5381 */
5382 .hub_control = xhci_hub_control,
5383 .hub_status_data = xhci_hub_status_data,
5384 .bus_suspend = xhci_bus_suspend,
5385 .bus_resume = xhci_bus_resume,
5386 .get_resuming_ports = xhci_get_resuming_ports,
5387
5388 /*
5389 * call back when device connected and addressed
5390 */
5391 .update_device = xhci_update_device,
5392 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5393 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5394 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5395 .find_raw_port_number = xhci_find_raw_port_number,
5396 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5397};
5398
5399void xhci_init_driver(struct hc_driver *drv,
5400 const struct xhci_driver_overrides *over)
5401{
5402 BUG_ON(!over);
5403
5404 /* Copy the generic table to drv then apply the overrides */
5405 *drv = xhci_hc_driver;
5406
5407 if (over) {
5408 drv->hcd_priv_size += over->extra_priv_size;
5409 if (over->reset)
5410 drv->reset = over->reset;
5411 if (over->start)
5412 drv->start = over->start;
5413 if (over->add_endpoint)
5414 drv->add_endpoint = over->add_endpoint;
5415 if (over->drop_endpoint)
5416 drv->drop_endpoint = over->drop_endpoint;
5417 if (over->check_bandwidth)
5418 drv->check_bandwidth = over->check_bandwidth;
5419 if (over->reset_bandwidth)
5420 drv->reset_bandwidth = over->reset_bandwidth;
5421 if (over->update_hub_device)
5422 drv->update_hub_device = over->update_hub_device;
5423 if (over->hub_control)
5424 drv->hub_control = over->hub_control;
5425 }
5426}
5427EXPORT_SYMBOL_GPL(xhci_init_driver);
5428
5429MODULE_DESCRIPTION(DRIVER_DESC);
5430MODULE_AUTHOR(DRIVER_AUTHOR);
5431MODULE_LICENSE("GPL");
5432
5433static int __init xhci_hcd_init(void)
5434{
5435 /*
5436 * Check the compiler generated sizes of structures that must be laid
5437 * out in specific ways for hardware access.
5438 */
5439 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5440 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5441 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5442 /* xhci_device_control has eight fields, and also
5443 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5444 */
5445 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5446 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5447 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5448 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5449 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5450 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5451 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5452
5453 if (usb_disabled())
5454 return -ENODEV;
5455
5456 xhci_debugfs_create_root();
5457 xhci_dbc_init();
5458
5459 return 0;
5460}
5461
5462/*
5463 * If an init function is provided, an exit function must also be provided
5464 * to allow module unload.
5465 */
5466static void __exit xhci_hcd_fini(void)
5467{
5468 xhci_debugfs_remove_root();
5469 xhci_dbc_exit();
5470}
5471
5472module_init(xhci_hcd_init);
5473module_exit(xhci_hcd_fini);