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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/log2.h>
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/slab.h>
18#include <linux/dmi.h>
19#include <linux/dma-mapping.h>
20
21#include "xhci.h"
22#include "xhci-trace.h"
23#include "xhci-debugfs.h"
24#include "xhci-dbgcap.h"
25
26#define DRIVER_AUTHOR "Sarah Sharp"
27#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
28
29#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
30
31/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32static int link_quirk;
33module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
35
36static unsigned long long quirks;
37module_param(quirks, ullong, S_IRUGO);
38MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
39
40static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
41{
42 struct xhci_segment *seg = ring->first_seg;
43
44 if (!td || !td->start_seg)
45 return false;
46 do {
47 if (seg == td->start_seg)
48 return true;
49 seg = seg->next;
50 } while (seg && seg != ring->first_seg);
51
52 return false;
53}
54
55/*
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
61 *
62 * Returns negative errno, or zero on success
63 *
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
67 */
68int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
69{
70 u32 result;
71 int ret;
72
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
75 result == U32_MAX,
76 1, timeout_us);
77 if (result == U32_MAX) /* card removed */
78 return -ENODEV;
79
80 return ret;
81}
82
83/*
84 * Disable interrupts and begin the xHCI halting process.
85 */
86void xhci_quiesce(struct xhci_hcd *xhci)
87{
88 u32 halted;
89 u32 cmd;
90 u32 mask;
91
92 mask = ~(XHCI_IRQS);
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
94 if (!halted)
95 mask &= ~CMD_RUN;
96
97 cmd = readl(&xhci->op_regs->command);
98 cmd &= mask;
99 writel(cmd, &xhci->op_regs->command);
100}
101
102/*
103 * Force HC into halt state.
104 *
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
109 */
110int xhci_halt(struct xhci_hcd *xhci)
111{
112 int ret;
113
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
115 xhci_quiesce(xhci);
116
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 if (ret) {
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
121 return ret;
122 }
123
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
126
127 return ret;
128}
129
130/*
131 * Set the run bit and wait for the host to be running.
132 */
133int xhci_start(struct xhci_hcd *xhci)
134{
135 u32 temp;
136 int ret;
137
138 temp = readl(&xhci->op_regs->command);
139 temp |= (CMD_RUN);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
141 temp);
142 writel(temp, &xhci->op_regs->command);
143
144 /*
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 * running.
147 */
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
153 XHCI_MAX_HALT_USEC);
154 if (!ret) {
155 /* clear state flags. Including dying, halted or removing */
156 xhci->xhc_state = 0;
157 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
158 }
159
160 return ret;
161}
162
163/*
164 * Reset a halted HC.
165 *
166 * This resets pipelines, timers, counters, state machines, etc.
167 * Transactions will be terminated immediately, and operational registers
168 * will be set to their defaults.
169 */
170int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
171{
172 u32 command;
173 u32 state;
174 int ret;
175
176 state = readl(&xhci->op_regs->status);
177
178 if (state == ~(u32)0) {
179 xhci_warn(xhci, "Host not accessible, reset failed.\n");
180 return -ENODEV;
181 }
182
183 if ((state & STS_HALT) == 0) {
184 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
185 return 0;
186 }
187
188 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
189 command = readl(&xhci->op_regs->command);
190 command |= CMD_RESET;
191 writel(command, &xhci->op_regs->command);
192
193 /* Existing Intel xHCI controllers require a delay of 1 mS,
194 * after setting the CMD_RESET bit, and before accessing any
195 * HC registers. This allows the HC to complete the
196 * reset operation and be ready for HC register access.
197 * Without this delay, the subsequent HC register access,
198 * may result in a system hang very rarely.
199 */
200 if (xhci->quirks & XHCI_INTEL_HOST)
201 udelay(1000);
202
203 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
204 if (ret)
205 return ret;
206
207 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
208 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
209
210 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
211 "Wait for controller to be ready for doorbell rings");
212 /*
213 * xHCI cannot write to any doorbells or operational registers other
214 * than status until the "Controller Not Ready" flag is cleared.
215 */
216 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
217
218 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb2_rhub.bus_state.suspended_ports = 0;
220 xhci->usb2_rhub.bus_state.resuming_ports = 0;
221 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
222 xhci->usb3_rhub.bus_state.suspended_ports = 0;
223 xhci->usb3_rhub.bus_state.resuming_ports = 0;
224
225 return ret;
226}
227
228static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
229{
230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
231 int err, i;
232 u64 val;
233 u32 intrs;
234
235 /*
236 * Some Renesas controllers get into a weird state if they are
237 * reset while programmed with 64bit addresses (they will preserve
238 * the top half of the address in internal, non visible
239 * registers). You end up with half the address coming from the
240 * kernel, and the other half coming from the firmware. Also,
241 * changing the programming leads to extra accesses even if the
242 * controller is supposed to be halted. The controller ends up with
243 * a fatal fault, and is then ripe for being properly reset.
244 *
245 * Special care is taken to only apply this if the device is behind
246 * an iommu. Doing anything when there is no iommu is definitely
247 * unsafe...
248 */
249 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
250 return;
251
252 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
253
254 /* Clear HSEIE so that faults do not get signaled */
255 val = readl(&xhci->op_regs->command);
256 val &= ~CMD_HSEIE;
257 writel(val, &xhci->op_regs->command);
258
259 /* Clear HSE (aka FATAL) */
260 val = readl(&xhci->op_regs->status);
261 val |= STS_FATAL;
262 writel(val, &xhci->op_regs->status);
263
264 /* Now zero the registers, and brace for impact */
265 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
268 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
269 if (upper_32_bits(val))
270 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
271
272 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
273 ARRAY_SIZE(xhci->run_regs->ir_set));
274
275 for (i = 0; i < intrs; i++) {
276 struct xhci_intr_reg __iomem *ir;
277
278 ir = &xhci->run_regs->ir_set[i];
279 val = xhci_read_64(xhci, &ir->erst_base);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_base);
282 val= xhci_read_64(xhci, &ir->erst_dequeue);
283 if (upper_32_bits(val))
284 xhci_write_64(xhci, 0, &ir->erst_dequeue);
285 }
286
287 /* Wait for the fault to appear. It will be cleared on reset */
288 err = xhci_handshake(&xhci->op_regs->status,
289 STS_FATAL, STS_FATAL,
290 XHCI_MAX_HALT_USEC);
291 if (!err)
292 xhci_info(xhci, "Fault detected\n");
293}
294
295#ifdef CONFIG_USB_PCI
296/*
297 * Set up MSI
298 */
299static int xhci_setup_msi(struct xhci_hcd *xhci)
300{
301 int ret;
302 /*
303 * TODO:Check with MSI Soc for sysdev
304 */
305 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
306
307 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
308 if (ret < 0) {
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "failed to allocate MSI entry");
311 return ret;
312 }
313
314 ret = request_irq(pdev->irq, xhci_msi_irq,
315 0, "xhci_hcd", xhci_to_hcd(xhci));
316 if (ret) {
317 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
318 "disable MSI interrupt");
319 pci_free_irq_vectors(pdev);
320 }
321
322 return ret;
323}
324
325/*
326 * Set up MSI-X
327 */
328static int xhci_setup_msix(struct xhci_hcd *xhci)
329{
330 int i, ret;
331 struct usb_hcd *hcd = xhci_to_hcd(xhci);
332 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
333
334 /*
335 * calculate number of msi-x vectors supported.
336 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
337 * with max number of interrupters based on the xhci HCSPARAMS1.
338 * - num_online_cpus: maximum msi-x vectors per CPUs core.
339 * Add additional 1 vector to ensure always available interrupt.
340 */
341 xhci->msix_count = min(num_online_cpus() + 1,
342 HCS_MAX_INTRS(xhci->hcs_params1));
343
344 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
345 PCI_IRQ_MSIX);
346 if (ret < 0) {
347 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
348 "Failed to enable MSI-X");
349 return ret;
350 }
351
352 for (i = 0; i < xhci->msix_count; i++) {
353 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
354 "xhci_hcd", xhci_to_hcd(xhci));
355 if (ret)
356 goto disable_msix;
357 }
358
359 hcd->msix_enabled = 1;
360 return ret;
361
362disable_msix:
363 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
364 while (--i >= 0)
365 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
366 pci_free_irq_vectors(pdev);
367 return ret;
368}
369
370/* Free any IRQs and disable MSI-X */
371static void xhci_cleanup_msix(struct xhci_hcd *xhci)
372{
373 struct usb_hcd *hcd = xhci_to_hcd(xhci);
374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
375
376 if (xhci->quirks & XHCI_PLAT)
377 return;
378
379 /* return if using legacy interrupt */
380 if (hcd->irq > 0)
381 return;
382
383 if (hcd->msix_enabled) {
384 int i;
385
386 for (i = 0; i < xhci->msix_count; i++)
387 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
388 } else {
389 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
390 }
391
392 pci_free_irq_vectors(pdev);
393 hcd->msix_enabled = 0;
394}
395
396static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
397{
398 struct usb_hcd *hcd = xhci_to_hcd(xhci);
399
400 if (hcd->msix_enabled) {
401 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
402 int i;
403
404 for (i = 0; i < xhci->msix_count; i++)
405 synchronize_irq(pci_irq_vector(pdev, i));
406 }
407}
408
409static int xhci_try_enable_msi(struct usb_hcd *hcd)
410{
411 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
412 struct pci_dev *pdev;
413 int ret;
414
415 /* The xhci platform device has set up IRQs through usb_add_hcd. */
416 if (xhci->quirks & XHCI_PLAT)
417 return 0;
418
419 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
420 /*
421 * Some Fresco Logic host controllers advertise MSI, but fail to
422 * generate interrupts. Don't even try to enable MSI.
423 */
424 if (xhci->quirks & XHCI_BROKEN_MSI)
425 goto legacy_irq;
426
427 /* unregister the legacy interrupt */
428 if (hcd->irq)
429 free_irq(hcd->irq, hcd);
430 hcd->irq = 0;
431
432 ret = xhci_setup_msix(xhci);
433 if (ret)
434 /* fall back to msi*/
435 ret = xhci_setup_msi(xhci);
436
437 if (!ret) {
438 hcd->msi_enabled = 1;
439 return 0;
440 }
441
442 if (!pdev->irq) {
443 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
444 return -EINVAL;
445 }
446
447 legacy_irq:
448 if (!strlen(hcd->irq_descr))
449 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
450 hcd->driver->description, hcd->self.busnum);
451
452 /* fall back to legacy interrupt*/
453 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
454 hcd->irq_descr, hcd);
455 if (ret) {
456 xhci_err(xhci, "request interrupt %d failed\n",
457 pdev->irq);
458 return ret;
459 }
460 hcd->irq = pdev->irq;
461 return 0;
462}
463
464#else
465
466static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
467{
468 return 0;
469}
470
471static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
472{
473}
474
475static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
476{
477}
478
479#endif
480
481static void compliance_mode_recovery(struct timer_list *t)
482{
483 struct xhci_hcd *xhci;
484 struct usb_hcd *hcd;
485 struct xhci_hub *rhub;
486 u32 temp;
487 int i;
488
489 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
490 rhub = &xhci->usb3_rhub;
491 hcd = rhub->hcd;
492
493 if (!hcd)
494 return;
495
496 for (i = 0; i < rhub->num_ports; i++) {
497 temp = readl(rhub->ports[i]->addr);
498 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
499 /*
500 * Compliance Mode Detected. Letting USB Core
501 * handle the Warm Reset
502 */
503 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
504 "Compliance mode detected->port %d",
505 i + 1);
506 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
507 "Attempting compliance mode recovery");
508
509 if (hcd->state == HC_STATE_SUSPENDED)
510 usb_hcd_resume_root_hub(hcd);
511
512 usb_hcd_poll_rh_status(hcd);
513 }
514 }
515
516 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
517 mod_timer(&xhci->comp_mode_recovery_timer,
518 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
519}
520
521/*
522 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
523 * that causes ports behind that hardware to enter compliance mode sometimes.
524 * The quirk creates a timer that polls every 2 seconds the link state of
525 * each host controller's port and recovers it by issuing a Warm reset
526 * if Compliance mode is detected, otherwise the port will become "dead" (no
527 * device connections or disconnections will be detected anymore). Becasue no
528 * status event is generated when entering compliance mode (per xhci spec),
529 * this quirk is needed on systems that have the failing hardware installed.
530 */
531static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
532{
533 xhci->port_status_u0 = 0;
534 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
535 0);
536 xhci->comp_mode_recovery_timer.expires = jiffies +
537 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
538
539 add_timer(&xhci->comp_mode_recovery_timer);
540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
541 "Compliance mode recovery timer initialized");
542}
543
544/*
545 * This function identifies the systems that have installed the SN65LVPE502CP
546 * USB3.0 re-driver and that need the Compliance Mode Quirk.
547 * Systems:
548 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
549 */
550static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
551{
552 const char *dmi_product_name, *dmi_sys_vendor;
553
554 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
555 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
556 if (!dmi_product_name || !dmi_sys_vendor)
557 return false;
558
559 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
560 return false;
561
562 if (strstr(dmi_product_name, "Z420") ||
563 strstr(dmi_product_name, "Z620") ||
564 strstr(dmi_product_name, "Z820") ||
565 strstr(dmi_product_name, "Z1 Workstation"))
566 return true;
567
568 return false;
569}
570
571static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
572{
573 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
574}
575
576
577/*
578 * Initialize memory for HCD and xHC (one-time init).
579 *
580 * Program the PAGESIZE register, initialize the device context array, create
581 * device contexts (?), set up a command ring segment (or two?), create event
582 * ring (one for now).
583 */
584static int xhci_init(struct usb_hcd *hcd)
585{
586 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
587 int retval;
588
589 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
590 spin_lock_init(&xhci->lock);
591 if (xhci->hci_version == 0x95 && link_quirk) {
592 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
593 "QUIRK: Not clearing Link TRB chain bits.");
594 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
595 } else {
596 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
597 "xHCI doesn't need link TRB QUIRK");
598 }
599 retval = xhci_mem_init(xhci, GFP_KERNEL);
600 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
601
602 /* Initializing Compliance Mode Recovery Data If Needed */
603 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
604 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
605 compliance_mode_recovery_timer_init(xhci);
606 }
607
608 return retval;
609}
610
611/*-------------------------------------------------------------------------*/
612
613
614static int xhci_run_finished(struct xhci_hcd *xhci)
615{
616 unsigned long flags;
617 u32 temp;
618
619 /*
620 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
621 * Protect the short window before host is running with a lock
622 */
623 spin_lock_irqsave(&xhci->lock, flags);
624
625 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
626 temp = readl(&xhci->op_regs->command);
627 temp |= (CMD_EIE);
628 writel(temp, &xhci->op_regs->command);
629
630 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
631 temp = readl(&xhci->ir_set->irq_pending);
632 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
633
634 if (xhci_start(xhci)) {
635 xhci_halt(xhci);
636 spin_unlock_irqrestore(&xhci->lock, flags);
637 return -ENODEV;
638 }
639
640 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
641
642 if (xhci->quirks & XHCI_NEC_HOST)
643 xhci_ring_cmd_db(xhci);
644
645 spin_unlock_irqrestore(&xhci->lock, flags);
646
647 return 0;
648}
649
650/*
651 * Start the HC after it was halted.
652 *
653 * This function is called by the USB core when the HC driver is added.
654 * Its opposite is xhci_stop().
655 *
656 * xhci_init() must be called once before this function can be called.
657 * Reset the HC, enable device slot contexts, program DCBAAP, and
658 * set command ring pointer and event ring pointer.
659 *
660 * Setup MSI-X vectors and enable interrupts.
661 */
662int xhci_run(struct usb_hcd *hcd)
663{
664 u32 temp;
665 u64 temp_64;
666 int ret;
667 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
668
669 /* Start the xHCI host controller running only after the USB 2.0 roothub
670 * is setup.
671 */
672
673 hcd->uses_new_polling = 1;
674 if (!usb_hcd_is_primary_hcd(hcd))
675 return xhci_run_finished(xhci);
676
677 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
678
679 ret = xhci_try_enable_msi(hcd);
680 if (ret)
681 return ret;
682
683 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
684 temp_64 &= ~ERST_PTR_MASK;
685 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
686 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
687
688 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
689 "// Set the interrupt modulation register");
690 temp = readl(&xhci->ir_set->irq_control);
691 temp &= ~ER_IRQ_INTERVAL_MASK;
692 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
693 writel(temp, &xhci->ir_set->irq_control);
694
695 if (xhci->quirks & XHCI_NEC_HOST) {
696 struct xhci_command *command;
697
698 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
699 if (!command)
700 return -ENOMEM;
701
702 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
703 TRB_TYPE(TRB_NEC_GET_FW));
704 if (ret)
705 xhci_free_command(xhci, command);
706 }
707 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
708 "Finished %s for main hcd", __func__);
709
710 xhci_create_dbc_dev(xhci);
711
712 xhci_debugfs_init(xhci);
713
714 if (xhci_has_one_roothub(xhci))
715 return xhci_run_finished(xhci);
716
717 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
718
719 return 0;
720}
721EXPORT_SYMBOL_GPL(xhci_run);
722
723/*
724 * Stop xHCI driver.
725 *
726 * This function is called by the USB core when the HC driver is removed.
727 * Its opposite is xhci_run().
728 *
729 * Disable device contexts, disable IRQs, and quiesce the HC.
730 * Reset the HC, finish any completed transactions, and cleanup memory.
731 */
732static void xhci_stop(struct usb_hcd *hcd)
733{
734 u32 temp;
735 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
736
737 mutex_lock(&xhci->mutex);
738
739 /* Only halt host and free memory after both hcds are removed */
740 if (!usb_hcd_is_primary_hcd(hcd)) {
741 mutex_unlock(&xhci->mutex);
742 return;
743 }
744
745 xhci_remove_dbc_dev(xhci);
746
747 spin_lock_irq(&xhci->lock);
748 xhci->xhc_state |= XHCI_STATE_HALTED;
749 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
750 xhci_halt(xhci);
751 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
752 spin_unlock_irq(&xhci->lock);
753
754 xhci_cleanup_msix(xhci);
755
756 /* Deleting Compliance Mode Recovery Timer */
757 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
758 (!(xhci_all_ports_seen_u0(xhci)))) {
759 del_timer_sync(&xhci->comp_mode_recovery_timer);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
761 "%s: compliance mode recovery timer deleted",
762 __func__);
763 }
764
765 if (xhci->quirks & XHCI_AMD_PLL_FIX)
766 usb_amd_dev_put();
767
768 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
769 "// Disabling event ring interrupts");
770 temp = readl(&xhci->op_regs->status);
771 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
772 temp = readl(&xhci->ir_set->irq_pending);
773 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
774
775 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
776 xhci_mem_cleanup(xhci);
777 xhci_debugfs_exit(xhci);
778 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
779 "xhci_stop completed - status = %x",
780 readl(&xhci->op_regs->status));
781 mutex_unlock(&xhci->mutex);
782}
783
784/*
785 * Shutdown HC (not bus-specific)
786 *
787 * This is called when the machine is rebooting or halting. We assume that the
788 * machine will be powered off, and the HC's internal state will be reset.
789 * Don't bother to free memory.
790 *
791 * This will only ever be called with the main usb_hcd (the USB3 roothub).
792 */
793void xhci_shutdown(struct usb_hcd *hcd)
794{
795 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
796
797 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
798 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
799
800 /* Don't poll the roothubs after shutdown. */
801 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
802 __func__, hcd->self.busnum);
803 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
804 del_timer_sync(&hcd->rh_timer);
805
806 if (xhci->shared_hcd) {
807 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
808 del_timer_sync(&xhci->shared_hcd->rh_timer);
809 }
810
811 spin_lock_irq(&xhci->lock);
812 xhci_halt(xhci);
813
814 /*
815 * Workaround for spurious wakeps at shutdown with HSW, and for boot
816 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
817 */
818 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
819 xhci->quirks & XHCI_RESET_TO_DEFAULT)
820 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
821
822 spin_unlock_irq(&xhci->lock);
823
824 xhci_cleanup_msix(xhci);
825
826 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
827 "xhci_shutdown completed - status = %x",
828 readl(&xhci->op_regs->status));
829}
830EXPORT_SYMBOL_GPL(xhci_shutdown);
831
832#ifdef CONFIG_PM
833static void xhci_save_registers(struct xhci_hcd *xhci)
834{
835 xhci->s3.command = readl(&xhci->op_regs->command);
836 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
837 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
838 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
839 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
840 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
841 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
842 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
843 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
844}
845
846static void xhci_restore_registers(struct xhci_hcd *xhci)
847{
848 writel(xhci->s3.command, &xhci->op_regs->command);
849 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
850 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
851 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
852 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
853 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
854 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
855 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
856 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
857}
858
859static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
860{
861 u64 val_64;
862
863 /* step 2: initialize command ring buffer */
864 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
865 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
866 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
867 xhci->cmd_ring->dequeue) &
868 (u64) ~CMD_RING_RSVD_BITS) |
869 xhci->cmd_ring->cycle_state;
870 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
871 "// Setting command ring address to 0x%llx",
872 (long unsigned long) val_64);
873 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
874}
875
876/*
877 * The whole command ring must be cleared to zero when we suspend the host.
878 *
879 * The host doesn't save the command ring pointer in the suspend well, so we
880 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
881 * aligned, because of the reserved bits in the command ring dequeue pointer
882 * register. Therefore, we can't just set the dequeue pointer back in the
883 * middle of the ring (TRBs are 16-byte aligned).
884 */
885static void xhci_clear_command_ring(struct xhci_hcd *xhci)
886{
887 struct xhci_ring *ring;
888 struct xhci_segment *seg;
889
890 ring = xhci->cmd_ring;
891 seg = ring->deq_seg;
892 do {
893 memset(seg->trbs, 0,
894 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
895 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
896 cpu_to_le32(~TRB_CYCLE);
897 seg = seg->next;
898 } while (seg != ring->deq_seg);
899
900 /* Reset the software enqueue and dequeue pointers */
901 ring->deq_seg = ring->first_seg;
902 ring->dequeue = ring->first_seg->trbs;
903 ring->enq_seg = ring->deq_seg;
904 ring->enqueue = ring->dequeue;
905
906 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
907 /*
908 * Ring is now zeroed, so the HW should look for change of ownership
909 * when the cycle bit is set to 1.
910 */
911 ring->cycle_state = 1;
912
913 /*
914 * Reset the hardware dequeue pointer.
915 * Yes, this will need to be re-written after resume, but we're paranoid
916 * and want to make sure the hardware doesn't access bogus memory
917 * because, say, the BIOS or an SMI started the host without changing
918 * the command ring pointers.
919 */
920 xhci_set_cmd_ring_deq(xhci);
921}
922
923/*
924 * Disable port wake bits if do_wakeup is not set.
925 *
926 * Also clear a possible internal port wake state left hanging for ports that
927 * detected termination but never successfully enumerated (trained to 0U).
928 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
929 * at enumeration clears this wake, force one here as well for unconnected ports
930 */
931
932static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
933 struct xhci_hub *rhub,
934 bool do_wakeup)
935{
936 unsigned long flags;
937 u32 t1, t2, portsc;
938 int i;
939
940 spin_lock_irqsave(&xhci->lock, flags);
941
942 for (i = 0; i < rhub->num_ports; i++) {
943 portsc = readl(rhub->ports[i]->addr);
944 t1 = xhci_port_state_to_neutral(portsc);
945 t2 = t1;
946
947 /* clear wake bits if do_wake is not set */
948 if (!do_wakeup)
949 t2 &= ~PORT_WAKE_BITS;
950
951 /* Don't touch csc bit if connected or connect change is set */
952 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
953 t2 |= PORT_CSC;
954
955 if (t1 != t2) {
956 writel(t2, rhub->ports[i]->addr);
957 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
958 rhub->hcd->self.busnum, i + 1, portsc, t2);
959 }
960 }
961 spin_unlock_irqrestore(&xhci->lock, flags);
962}
963
964static bool xhci_pending_portevent(struct xhci_hcd *xhci)
965{
966 struct xhci_port **ports;
967 int port_index;
968 u32 status;
969 u32 portsc;
970
971 status = readl(&xhci->op_regs->status);
972 if (status & STS_EINT)
973 return true;
974 /*
975 * Checking STS_EINT is not enough as there is a lag between a change
976 * bit being set and the Port Status Change Event that it generated
977 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
978 */
979
980 port_index = xhci->usb2_rhub.num_ports;
981 ports = xhci->usb2_rhub.ports;
982 while (port_index--) {
983 portsc = readl(ports[port_index]->addr);
984 if (portsc & PORT_CHANGE_MASK ||
985 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
986 return true;
987 }
988 port_index = xhci->usb3_rhub.num_ports;
989 ports = xhci->usb3_rhub.ports;
990 while (port_index--) {
991 portsc = readl(ports[port_index]->addr);
992 if (portsc & PORT_CHANGE_MASK ||
993 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
994 return true;
995 }
996 return false;
997}
998
999/*
1000 * Stop HC (not bus-specific)
1001 *
1002 * This is called when the machine transition into S3/S4 mode.
1003 *
1004 */
1005int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
1006{
1007 int rc = 0;
1008 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
1009 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1010 u32 command;
1011 u32 res;
1012
1013 if (!hcd->state)
1014 return 0;
1015
1016 if (hcd->state != HC_STATE_SUSPENDED ||
1017 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
1018 return -EINVAL;
1019
1020 /* Clear root port wake on bits if wakeup not allowed. */
1021 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1022 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1023
1024 if (!HCD_HW_ACCESSIBLE(hcd))
1025 return 0;
1026
1027 xhci_dbc_suspend(xhci);
1028
1029 /* Don't poll the roothubs on bus suspend. */
1030 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1031 __func__, hcd->self.busnum);
1032 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1033 del_timer_sync(&hcd->rh_timer);
1034 if (xhci->shared_hcd) {
1035 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1036 del_timer_sync(&xhci->shared_hcd->rh_timer);
1037 }
1038
1039 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1040 usleep_range(1000, 1500);
1041
1042 spin_lock_irq(&xhci->lock);
1043 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1044 if (xhci->shared_hcd)
1045 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1046 /* step 1: stop endpoint */
1047 /* skipped assuming that port suspend has done */
1048
1049 /* step 2: clear Run/Stop bit */
1050 command = readl(&xhci->op_regs->command);
1051 command &= ~CMD_RUN;
1052 writel(command, &xhci->op_regs->command);
1053
1054 /* Some chips from Fresco Logic need an extraordinary delay */
1055 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1056
1057 if (xhci_handshake(&xhci->op_regs->status,
1058 STS_HALT, STS_HALT, delay)) {
1059 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1060 spin_unlock_irq(&xhci->lock);
1061 return -ETIMEDOUT;
1062 }
1063 xhci_clear_command_ring(xhci);
1064
1065 /* step 3: save registers */
1066 xhci_save_registers(xhci);
1067
1068 /* step 4: set CSS flag */
1069 command = readl(&xhci->op_regs->command);
1070 command |= CMD_CSS;
1071 writel(command, &xhci->op_regs->command);
1072 xhci->broken_suspend = 0;
1073 if (xhci_handshake(&xhci->op_regs->status,
1074 STS_SAVE, 0, 20 * 1000)) {
1075 /*
1076 * AMD SNPS xHC 3.0 occasionally does not clear the
1077 * SSS bit of USBSTS and when driver tries to poll
1078 * to see if the xHC clears BIT(8) which never happens
1079 * and driver assumes that controller is not responding
1080 * and times out. To workaround this, its good to check
1081 * if SRE and HCE bits are not set (as per xhci
1082 * Section 5.4.2) and bypass the timeout.
1083 */
1084 res = readl(&xhci->op_regs->status);
1085 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1086 (((res & STS_SRE) == 0) &&
1087 ((res & STS_HCE) == 0))) {
1088 xhci->broken_suspend = 1;
1089 } else {
1090 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1091 spin_unlock_irq(&xhci->lock);
1092 return -ETIMEDOUT;
1093 }
1094 }
1095 spin_unlock_irq(&xhci->lock);
1096
1097 /*
1098 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1099 * is about to be suspended.
1100 */
1101 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1102 (!(xhci_all_ports_seen_u0(xhci)))) {
1103 del_timer_sync(&xhci->comp_mode_recovery_timer);
1104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1105 "%s: compliance mode recovery timer deleted",
1106 __func__);
1107 }
1108
1109 /* step 5: remove core well power */
1110 /* synchronize irq when using MSI-X */
1111 xhci_msix_sync_irqs(xhci);
1112
1113 return rc;
1114}
1115EXPORT_SYMBOL_GPL(xhci_suspend);
1116
1117/*
1118 * start xHC (not bus-specific)
1119 *
1120 * This is called when the machine transition from S3/S4 mode.
1121 *
1122 */
1123int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1124{
1125 u32 command, temp = 0;
1126 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1127 int retval = 0;
1128 bool comp_timer_running = false;
1129 bool pending_portevent = false;
1130 bool reinit_xhc = false;
1131
1132 if (!hcd->state)
1133 return 0;
1134
1135 /* Wait a bit if either of the roothubs need to settle from the
1136 * transition into bus suspend.
1137 */
1138
1139 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1140 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1141 msleep(100);
1142
1143 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1144 if (xhci->shared_hcd)
1145 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1146
1147 spin_lock_irq(&xhci->lock);
1148
1149 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1150 reinit_xhc = true;
1151
1152 if (!reinit_xhc) {
1153 /*
1154 * Some controllers might lose power during suspend, so wait
1155 * for controller not ready bit to clear, just as in xHC init.
1156 */
1157 retval = xhci_handshake(&xhci->op_regs->status,
1158 STS_CNR, 0, 10 * 1000 * 1000);
1159 if (retval) {
1160 xhci_warn(xhci, "Controller not ready at resume %d\n",
1161 retval);
1162 spin_unlock_irq(&xhci->lock);
1163 return retval;
1164 }
1165 /* step 1: restore register */
1166 xhci_restore_registers(xhci);
1167 /* step 2: initialize command ring buffer */
1168 xhci_set_cmd_ring_deq(xhci);
1169 /* step 3: restore state and start state*/
1170 /* step 3: set CRS flag */
1171 command = readl(&xhci->op_regs->command);
1172 command |= CMD_CRS;
1173 writel(command, &xhci->op_regs->command);
1174 /*
1175 * Some controllers take up to 55+ ms to complete the controller
1176 * restore so setting the timeout to 100ms. Xhci specification
1177 * doesn't mention any timeout value.
1178 */
1179 if (xhci_handshake(&xhci->op_regs->status,
1180 STS_RESTORE, 0, 100 * 1000)) {
1181 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1182 spin_unlock_irq(&xhci->lock);
1183 return -ETIMEDOUT;
1184 }
1185 }
1186
1187 temp = readl(&xhci->op_regs->status);
1188
1189 /* re-initialize the HC on Restore Error, or Host Controller Error */
1190 if (temp & (STS_SRE | STS_HCE)) {
1191 reinit_xhc = true;
1192 if (!xhci->broken_suspend)
1193 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1194 }
1195
1196 if (reinit_xhc) {
1197 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1198 !(xhci_all_ports_seen_u0(xhci))) {
1199 del_timer_sync(&xhci->comp_mode_recovery_timer);
1200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1201 "Compliance Mode Recovery Timer deleted!");
1202 }
1203
1204 /* Let the USB core know _both_ roothubs lost power. */
1205 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1206 if (xhci->shared_hcd)
1207 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1208
1209 xhci_dbg(xhci, "Stop HCD\n");
1210 xhci_halt(xhci);
1211 xhci_zero_64b_regs(xhci);
1212 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1213 spin_unlock_irq(&xhci->lock);
1214 if (retval)
1215 return retval;
1216 xhci_cleanup_msix(xhci);
1217
1218 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1219 temp = readl(&xhci->op_regs->status);
1220 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1221 temp = readl(&xhci->ir_set->irq_pending);
1222 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1223
1224 xhci_dbg(xhci, "cleaning up memory\n");
1225 xhci_mem_cleanup(xhci);
1226 xhci_debugfs_exit(xhci);
1227 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1228 readl(&xhci->op_regs->status));
1229
1230 /* USB core calls the PCI reinit and start functions twice:
1231 * first with the primary HCD, and then with the secondary HCD.
1232 * If we don't do the same, the host will never be started.
1233 */
1234 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1235 retval = xhci_init(hcd);
1236 if (retval)
1237 return retval;
1238 comp_timer_running = true;
1239
1240 xhci_dbg(xhci, "Start the primary HCD\n");
1241 retval = xhci_run(hcd);
1242 if (!retval && xhci->shared_hcd) {
1243 xhci_dbg(xhci, "Start the secondary HCD\n");
1244 retval = xhci_run(xhci->shared_hcd);
1245 }
1246
1247 hcd->state = HC_STATE_SUSPENDED;
1248 if (xhci->shared_hcd)
1249 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1250 goto done;
1251 }
1252
1253 /* step 4: set Run/Stop bit */
1254 command = readl(&xhci->op_regs->command);
1255 command |= CMD_RUN;
1256 writel(command, &xhci->op_regs->command);
1257 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1258 0, 250 * 1000);
1259
1260 /* step 5: walk topology and initialize portsc,
1261 * portpmsc and portli
1262 */
1263 /* this is done in bus_resume */
1264
1265 /* step 6: restart each of the previously
1266 * Running endpoints by ringing their doorbells
1267 */
1268
1269 spin_unlock_irq(&xhci->lock);
1270
1271 xhci_dbc_resume(xhci);
1272
1273 done:
1274 if (retval == 0) {
1275 /*
1276 * Resume roothubs only if there are pending events.
1277 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1278 * the first wake signalling failed, give it that chance.
1279 */
1280 pending_portevent = xhci_pending_portevent(xhci);
1281 if (!pending_portevent) {
1282 msleep(120);
1283 pending_portevent = xhci_pending_portevent(xhci);
1284 }
1285
1286 if (pending_portevent) {
1287 if (xhci->shared_hcd)
1288 usb_hcd_resume_root_hub(xhci->shared_hcd);
1289 usb_hcd_resume_root_hub(hcd);
1290 }
1291 }
1292 /*
1293 * If system is subject to the Quirk, Compliance Mode Timer needs to
1294 * be re-initialized Always after a system resume. Ports are subject
1295 * to suffer the Compliance Mode issue again. It doesn't matter if
1296 * ports have entered previously to U0 before system's suspension.
1297 */
1298 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1299 compliance_mode_recovery_timer_init(xhci);
1300
1301 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1302 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1303
1304 /* Re-enable port polling. */
1305 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1306 __func__, hcd->self.busnum);
1307 if (xhci->shared_hcd) {
1308 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1309 usb_hcd_poll_rh_status(xhci->shared_hcd);
1310 }
1311 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1312 usb_hcd_poll_rh_status(hcd);
1313
1314 return retval;
1315}
1316EXPORT_SYMBOL_GPL(xhci_resume);
1317#endif /* CONFIG_PM */
1318
1319/*-------------------------------------------------------------------------*/
1320
1321static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1322{
1323 void *temp;
1324 int ret = 0;
1325 unsigned int buf_len;
1326 enum dma_data_direction dir;
1327
1328 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1329 buf_len = urb->transfer_buffer_length;
1330
1331 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1332 dev_to_node(hcd->self.sysdev));
1333
1334 if (usb_urb_dir_out(urb))
1335 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1336 temp, buf_len, 0);
1337
1338 urb->transfer_buffer = temp;
1339 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1340 urb->transfer_buffer,
1341 urb->transfer_buffer_length,
1342 dir);
1343
1344 if (dma_mapping_error(hcd->self.sysdev,
1345 urb->transfer_dma)) {
1346 ret = -EAGAIN;
1347 kfree(temp);
1348 } else {
1349 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1350 }
1351
1352 return ret;
1353}
1354
1355static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1356 struct urb *urb)
1357{
1358 bool ret = false;
1359 unsigned int i;
1360 unsigned int len = 0;
1361 unsigned int trb_size;
1362 unsigned int max_pkt;
1363 struct scatterlist *sg;
1364 struct scatterlist *tail_sg;
1365
1366 tail_sg = urb->sg;
1367 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1368
1369 if (!urb->num_sgs)
1370 return ret;
1371
1372 if (urb->dev->speed >= USB_SPEED_SUPER)
1373 trb_size = TRB_CACHE_SIZE_SS;
1374 else
1375 trb_size = TRB_CACHE_SIZE_HS;
1376
1377 if (urb->transfer_buffer_length != 0 &&
1378 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1379 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1380 len = len + sg->length;
1381 if (i > trb_size - 2) {
1382 len = len - tail_sg->length;
1383 if (len < max_pkt) {
1384 ret = true;
1385 break;
1386 }
1387
1388 tail_sg = sg_next(tail_sg);
1389 }
1390 }
1391 }
1392 return ret;
1393}
1394
1395static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1396{
1397 unsigned int len;
1398 unsigned int buf_len;
1399 enum dma_data_direction dir;
1400
1401 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1402
1403 buf_len = urb->transfer_buffer_length;
1404
1405 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1406 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1407 dma_unmap_single(hcd->self.sysdev,
1408 urb->transfer_dma,
1409 urb->transfer_buffer_length,
1410 dir);
1411
1412 if (usb_urb_dir_in(urb)) {
1413 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1414 urb->transfer_buffer,
1415 buf_len,
1416 0);
1417 if (len != buf_len) {
1418 xhci_dbg(hcd_to_xhci(hcd),
1419 "Copy from tmp buf to urb sg list failed\n");
1420 urb->actual_length = len;
1421 }
1422 }
1423 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1424 kfree(urb->transfer_buffer);
1425 urb->transfer_buffer = NULL;
1426}
1427
1428/*
1429 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1430 * we'll copy the actual data into the TRB address register. This is limited to
1431 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1432 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1433 */
1434static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1435 gfp_t mem_flags)
1436{
1437 struct xhci_hcd *xhci;
1438
1439 xhci = hcd_to_xhci(hcd);
1440
1441 if (xhci_urb_suitable_for_idt(urb))
1442 return 0;
1443
1444 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1445 if (xhci_urb_temp_buffer_required(hcd, urb))
1446 return xhci_map_temp_buffer(hcd, urb);
1447 }
1448 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1449}
1450
1451static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1452{
1453 struct xhci_hcd *xhci;
1454 bool unmap_temp_buf = false;
1455
1456 xhci = hcd_to_xhci(hcd);
1457
1458 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1459 unmap_temp_buf = true;
1460
1461 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1462 xhci_unmap_temp_buf(hcd, urb);
1463 else
1464 usb_hcd_unmap_urb_for_dma(hcd, urb);
1465}
1466
1467/**
1468 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1469 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1470 * value to right shift 1 for the bitmask.
1471 *
1472 * Index = (epnum * 2) + direction - 1,
1473 * where direction = 0 for OUT, 1 for IN.
1474 * For control endpoints, the IN index is used (OUT index is unused), so
1475 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1476 */
1477unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1478{
1479 unsigned int index;
1480 if (usb_endpoint_xfer_control(desc))
1481 index = (unsigned int) (usb_endpoint_num(desc)*2);
1482 else
1483 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1484 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1485 return index;
1486}
1487EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1488
1489/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1490 * address from the XHCI endpoint index.
1491 */
1492static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1493{
1494 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1495 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1496 return direction | number;
1497}
1498
1499/* Find the flag for this endpoint (for use in the control context). Use the
1500 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1501 * bit 1, etc.
1502 */
1503static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1504{
1505 return 1 << (xhci_get_endpoint_index(desc) + 1);
1506}
1507
1508/* Compute the last valid endpoint context index. Basically, this is the
1509 * endpoint index plus one. For slot contexts with more than valid endpoint,
1510 * we find the most significant bit set in the added contexts flags.
1511 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1512 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1513 */
1514unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1515{
1516 return fls(added_ctxs) - 1;
1517}
1518
1519/* Returns 1 if the arguments are OK;
1520 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1521 */
1522static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1523 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1524 const char *func) {
1525 struct xhci_hcd *xhci;
1526 struct xhci_virt_device *virt_dev;
1527
1528 if (!hcd || (check_ep && !ep) || !udev) {
1529 pr_debug("xHCI %s called with invalid args\n", func);
1530 return -EINVAL;
1531 }
1532 if (!udev->parent) {
1533 pr_debug("xHCI %s called for root hub\n", func);
1534 return 0;
1535 }
1536
1537 xhci = hcd_to_xhci(hcd);
1538 if (check_virt_dev) {
1539 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1540 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1541 func);
1542 return -EINVAL;
1543 }
1544
1545 virt_dev = xhci->devs[udev->slot_id];
1546 if (virt_dev->udev != udev) {
1547 xhci_dbg(xhci, "xHCI %s called with udev and "
1548 "virt_dev does not match\n", func);
1549 return -EINVAL;
1550 }
1551 }
1552
1553 if (xhci->xhc_state & XHCI_STATE_HALTED)
1554 return -ENODEV;
1555
1556 return 1;
1557}
1558
1559static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1560 struct usb_device *udev, struct xhci_command *command,
1561 bool ctx_change, bool must_succeed);
1562
1563/*
1564 * Full speed devices may have a max packet size greater than 8 bytes, but the
1565 * USB core doesn't know that until it reads the first 8 bytes of the
1566 * descriptor. If the usb_device's max packet size changes after that point,
1567 * we need to issue an evaluate context command and wait on it.
1568 */
1569static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1570 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1571{
1572 struct xhci_container_ctx *out_ctx;
1573 struct xhci_input_control_ctx *ctrl_ctx;
1574 struct xhci_ep_ctx *ep_ctx;
1575 struct xhci_command *command;
1576 int max_packet_size;
1577 int hw_max_packet_size;
1578 int ret = 0;
1579
1580 out_ctx = xhci->devs[slot_id]->out_ctx;
1581 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1582 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1583 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1584 if (hw_max_packet_size != max_packet_size) {
1585 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1586 "Max Packet Size for ep 0 changed.");
1587 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1588 "Max packet size in usb_device = %d",
1589 max_packet_size);
1590 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1591 "Max packet size in xHCI HW = %d",
1592 hw_max_packet_size);
1593 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1594 "Issuing evaluate context command.");
1595
1596 /* Set up the input context flags for the command */
1597 /* FIXME: This won't work if a non-default control endpoint
1598 * changes max packet sizes.
1599 */
1600
1601 command = xhci_alloc_command(xhci, true, mem_flags);
1602 if (!command)
1603 return -ENOMEM;
1604
1605 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1606 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1607 if (!ctrl_ctx) {
1608 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1609 __func__);
1610 ret = -ENOMEM;
1611 goto command_cleanup;
1612 }
1613 /* Set up the modified control endpoint 0 */
1614 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1615 xhci->devs[slot_id]->out_ctx, ep_index);
1616
1617 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1618 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1619 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1620 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1621
1622 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1623 ctrl_ctx->drop_flags = 0;
1624
1625 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1626 true, false);
1627
1628 /* Clean up the input context for later use by bandwidth
1629 * functions.
1630 */
1631 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1632command_cleanup:
1633 kfree(command->completion);
1634 kfree(command);
1635 }
1636 return ret;
1637}
1638
1639/*
1640 * non-error returns are a promise to giveback() the urb later
1641 * we drop ownership so next owner (or urb unlink) can get it
1642 */
1643static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1644{
1645 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1646 unsigned long flags;
1647 int ret = 0;
1648 unsigned int slot_id, ep_index;
1649 unsigned int *ep_state;
1650 struct urb_priv *urb_priv;
1651 int num_tds;
1652
1653 if (!urb)
1654 return -EINVAL;
1655 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1656 true, true, __func__);
1657 if (ret <= 0)
1658 return ret ? ret : -EINVAL;
1659
1660 slot_id = urb->dev->slot_id;
1661 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1662 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1663
1664 if (!HCD_HW_ACCESSIBLE(hcd))
1665 return -ESHUTDOWN;
1666
1667 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1668 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1669 return -ENODEV;
1670 }
1671
1672 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1673 num_tds = urb->number_of_packets;
1674 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1675 urb->transfer_buffer_length > 0 &&
1676 urb->transfer_flags & URB_ZERO_PACKET &&
1677 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1678 num_tds = 2;
1679 else
1680 num_tds = 1;
1681
1682 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1683 if (!urb_priv)
1684 return -ENOMEM;
1685
1686 urb_priv->num_tds = num_tds;
1687 urb_priv->num_tds_done = 0;
1688 urb->hcpriv = urb_priv;
1689
1690 trace_xhci_urb_enqueue(urb);
1691
1692 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1693 /* Check to see if the max packet size for the default control
1694 * endpoint changed during FS device enumeration
1695 */
1696 if (urb->dev->speed == USB_SPEED_FULL) {
1697 ret = xhci_check_maxpacket(xhci, slot_id,
1698 ep_index, urb, mem_flags);
1699 if (ret < 0) {
1700 xhci_urb_free_priv(urb_priv);
1701 urb->hcpriv = NULL;
1702 return ret;
1703 }
1704 }
1705 }
1706
1707 spin_lock_irqsave(&xhci->lock, flags);
1708
1709 if (xhci->xhc_state & XHCI_STATE_DYING) {
1710 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1711 urb->ep->desc.bEndpointAddress, urb);
1712 ret = -ESHUTDOWN;
1713 goto free_priv;
1714 }
1715 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1716 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1717 *ep_state);
1718 ret = -EINVAL;
1719 goto free_priv;
1720 }
1721 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1722 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1723 ret = -EINVAL;
1724 goto free_priv;
1725 }
1726
1727 switch (usb_endpoint_type(&urb->ep->desc)) {
1728
1729 case USB_ENDPOINT_XFER_CONTROL:
1730 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1731 slot_id, ep_index);
1732 break;
1733 case USB_ENDPOINT_XFER_BULK:
1734 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1735 slot_id, ep_index);
1736 break;
1737 case USB_ENDPOINT_XFER_INT:
1738 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1739 slot_id, ep_index);
1740 break;
1741 case USB_ENDPOINT_XFER_ISOC:
1742 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1743 slot_id, ep_index);
1744 }
1745
1746 if (ret) {
1747free_priv:
1748 xhci_urb_free_priv(urb_priv);
1749 urb->hcpriv = NULL;
1750 }
1751 spin_unlock_irqrestore(&xhci->lock, flags);
1752 return ret;
1753}
1754
1755/*
1756 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1757 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1758 * should pick up where it left off in the TD, unless a Set Transfer Ring
1759 * Dequeue Pointer is issued.
1760 *
1761 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1762 * the ring. Since the ring is a contiguous structure, they can't be physically
1763 * removed. Instead, there are two options:
1764 *
1765 * 1) If the HC is in the middle of processing the URB to be canceled, we
1766 * simply move the ring's dequeue pointer past those TRBs using the Set
1767 * Transfer Ring Dequeue Pointer command. This will be the common case,
1768 * when drivers timeout on the last submitted URB and attempt to cancel.
1769 *
1770 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1771 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1772 * HC will need to invalidate the any TRBs it has cached after the stop
1773 * endpoint command, as noted in the xHCI 0.95 errata.
1774 *
1775 * 3) The TD may have completed by the time the Stop Endpoint Command
1776 * completes, so software needs to handle that case too.
1777 *
1778 * This function should protect against the TD enqueueing code ringing the
1779 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1780 * It also needs to account for multiple cancellations on happening at the same
1781 * time for the same endpoint.
1782 *
1783 * Note that this function can be called in any context, or so says
1784 * usb_hcd_unlink_urb()
1785 */
1786static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1787{
1788 unsigned long flags;
1789 int ret, i;
1790 u32 temp;
1791 struct xhci_hcd *xhci;
1792 struct urb_priv *urb_priv;
1793 struct xhci_td *td;
1794 unsigned int ep_index;
1795 struct xhci_ring *ep_ring;
1796 struct xhci_virt_ep *ep;
1797 struct xhci_command *command;
1798 struct xhci_virt_device *vdev;
1799
1800 xhci = hcd_to_xhci(hcd);
1801 spin_lock_irqsave(&xhci->lock, flags);
1802
1803 trace_xhci_urb_dequeue(urb);
1804
1805 /* Make sure the URB hasn't completed or been unlinked already */
1806 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1807 if (ret)
1808 goto done;
1809
1810 /* give back URB now if we can't queue it for cancel */
1811 vdev = xhci->devs[urb->dev->slot_id];
1812 urb_priv = urb->hcpriv;
1813 if (!vdev || !urb_priv)
1814 goto err_giveback;
1815
1816 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1817 ep = &vdev->eps[ep_index];
1818 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1819 if (!ep || !ep_ring)
1820 goto err_giveback;
1821
1822 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1823 temp = readl(&xhci->op_regs->status);
1824 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1825 xhci_hc_died(xhci);
1826 goto done;
1827 }
1828
1829 /*
1830 * check ring is not re-allocated since URB was enqueued. If it is, then
1831 * make sure none of the ring related pointers in this URB private data
1832 * are touched, such as td_list, otherwise we overwrite freed data
1833 */
1834 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1835 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1836 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1837 td = &urb_priv->td[i];
1838 if (!list_empty(&td->cancelled_td_list))
1839 list_del_init(&td->cancelled_td_list);
1840 }
1841 goto err_giveback;
1842 }
1843
1844 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1845 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1846 "HC halted, freeing TD manually.");
1847 for (i = urb_priv->num_tds_done;
1848 i < urb_priv->num_tds;
1849 i++) {
1850 td = &urb_priv->td[i];
1851 if (!list_empty(&td->td_list))
1852 list_del_init(&td->td_list);
1853 if (!list_empty(&td->cancelled_td_list))
1854 list_del_init(&td->cancelled_td_list);
1855 }
1856 goto err_giveback;
1857 }
1858
1859 i = urb_priv->num_tds_done;
1860 if (i < urb_priv->num_tds)
1861 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1862 "Cancel URB %p, dev %s, ep 0x%x, "
1863 "starting at offset 0x%llx",
1864 urb, urb->dev->devpath,
1865 urb->ep->desc.bEndpointAddress,
1866 (unsigned long long) xhci_trb_virt_to_dma(
1867 urb_priv->td[i].start_seg,
1868 urb_priv->td[i].first_trb));
1869
1870 for (; i < urb_priv->num_tds; i++) {
1871 td = &urb_priv->td[i];
1872 /* TD can already be on cancelled list if ep halted on it */
1873 if (list_empty(&td->cancelled_td_list)) {
1874 td->cancel_status = TD_DIRTY;
1875 list_add_tail(&td->cancelled_td_list,
1876 &ep->cancelled_td_list);
1877 }
1878 }
1879
1880 /* Queue a stop endpoint command, but only if this is
1881 * the first cancellation to be handled.
1882 */
1883 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1884 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1885 if (!command) {
1886 ret = -ENOMEM;
1887 goto done;
1888 }
1889 ep->ep_state |= EP_STOP_CMD_PENDING;
1890 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1891 ep_index, 0);
1892 xhci_ring_cmd_db(xhci);
1893 }
1894done:
1895 spin_unlock_irqrestore(&xhci->lock, flags);
1896 return ret;
1897
1898err_giveback:
1899 if (urb_priv)
1900 xhci_urb_free_priv(urb_priv);
1901 usb_hcd_unlink_urb_from_ep(hcd, urb);
1902 spin_unlock_irqrestore(&xhci->lock, flags);
1903 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1904 return ret;
1905}
1906
1907/* Drop an endpoint from a new bandwidth configuration for this device.
1908 * Only one call to this function is allowed per endpoint before
1909 * check_bandwidth() or reset_bandwidth() must be called.
1910 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1911 * add the endpoint to the schedule with possibly new parameters denoted by a
1912 * different endpoint descriptor in usb_host_endpoint.
1913 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1914 * not allowed.
1915 *
1916 * The USB core will not allow URBs to be queued to an endpoint that is being
1917 * disabled, so there's no need for mutual exclusion to protect
1918 * the xhci->devs[slot_id] structure.
1919 */
1920int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1921 struct usb_host_endpoint *ep)
1922{
1923 struct xhci_hcd *xhci;
1924 struct xhci_container_ctx *in_ctx, *out_ctx;
1925 struct xhci_input_control_ctx *ctrl_ctx;
1926 unsigned int ep_index;
1927 struct xhci_ep_ctx *ep_ctx;
1928 u32 drop_flag;
1929 u32 new_add_flags, new_drop_flags;
1930 int ret;
1931
1932 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1933 if (ret <= 0)
1934 return ret;
1935 xhci = hcd_to_xhci(hcd);
1936 if (xhci->xhc_state & XHCI_STATE_DYING)
1937 return -ENODEV;
1938
1939 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1940 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1941 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1942 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1943 __func__, drop_flag);
1944 return 0;
1945 }
1946
1947 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1948 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1949 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1950 if (!ctrl_ctx) {
1951 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1952 __func__);
1953 return 0;
1954 }
1955
1956 ep_index = xhci_get_endpoint_index(&ep->desc);
1957 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1958 /* If the HC already knows the endpoint is disabled,
1959 * or the HCD has noted it is disabled, ignore this request
1960 */
1961 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1962 le32_to_cpu(ctrl_ctx->drop_flags) &
1963 xhci_get_endpoint_flag(&ep->desc)) {
1964 /* Do not warn when called after a usb_device_reset */
1965 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1966 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1967 __func__, ep);
1968 return 0;
1969 }
1970
1971 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1972 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1973
1974 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1975 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1976
1977 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1978
1979 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1980
1981 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1982 (unsigned int) ep->desc.bEndpointAddress,
1983 udev->slot_id,
1984 (unsigned int) new_drop_flags,
1985 (unsigned int) new_add_flags);
1986 return 0;
1987}
1988EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1989
1990/* Add an endpoint to a new possible bandwidth configuration for this device.
1991 * Only one call to this function is allowed per endpoint before
1992 * check_bandwidth() or reset_bandwidth() must be called.
1993 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1994 * add the endpoint to the schedule with possibly new parameters denoted by a
1995 * different endpoint descriptor in usb_host_endpoint.
1996 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1997 * not allowed.
1998 *
1999 * The USB core will not allow URBs to be queued to an endpoint until the
2000 * configuration or alt setting is installed in the device, so there's no need
2001 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
2002 */
2003int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2004 struct usb_host_endpoint *ep)
2005{
2006 struct xhci_hcd *xhci;
2007 struct xhci_container_ctx *in_ctx;
2008 unsigned int ep_index;
2009 struct xhci_input_control_ctx *ctrl_ctx;
2010 struct xhci_ep_ctx *ep_ctx;
2011 u32 added_ctxs;
2012 u32 new_add_flags, new_drop_flags;
2013 struct xhci_virt_device *virt_dev;
2014 int ret = 0;
2015
2016 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2017 if (ret <= 0) {
2018 /* So we won't queue a reset ep command for a root hub */
2019 ep->hcpriv = NULL;
2020 return ret;
2021 }
2022 xhci = hcd_to_xhci(hcd);
2023 if (xhci->xhc_state & XHCI_STATE_DYING)
2024 return -ENODEV;
2025
2026 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2027 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2028 /* FIXME when we have to issue an evaluate endpoint command to
2029 * deal with ep0 max packet size changing once we get the
2030 * descriptors
2031 */
2032 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2033 __func__, added_ctxs);
2034 return 0;
2035 }
2036
2037 virt_dev = xhci->devs[udev->slot_id];
2038 in_ctx = virt_dev->in_ctx;
2039 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2040 if (!ctrl_ctx) {
2041 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2042 __func__);
2043 return 0;
2044 }
2045
2046 ep_index = xhci_get_endpoint_index(&ep->desc);
2047 /* If this endpoint is already in use, and the upper layers are trying
2048 * to add it again without dropping it, reject the addition.
2049 */
2050 if (virt_dev->eps[ep_index].ring &&
2051 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2052 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2053 "without dropping it.\n",
2054 (unsigned int) ep->desc.bEndpointAddress);
2055 return -EINVAL;
2056 }
2057
2058 /* If the HCD has already noted the endpoint is enabled,
2059 * ignore this request.
2060 */
2061 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2062 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2063 __func__, ep);
2064 return 0;
2065 }
2066
2067 /*
2068 * Configuration and alternate setting changes must be done in
2069 * process context, not interrupt context (or so documenation
2070 * for usb_set_interface() and usb_set_configuration() claim).
2071 */
2072 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2073 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2074 __func__, ep->desc.bEndpointAddress);
2075 return -ENOMEM;
2076 }
2077
2078 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2079 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2080
2081 /* If xhci_endpoint_disable() was called for this endpoint, but the
2082 * xHC hasn't been notified yet through the check_bandwidth() call,
2083 * this re-adds a new state for the endpoint from the new endpoint
2084 * descriptors. We must drop and re-add this endpoint, so we leave the
2085 * drop flags alone.
2086 */
2087 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2088
2089 /* Store the usb_device pointer for later use */
2090 ep->hcpriv = udev;
2091
2092 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2093 trace_xhci_add_endpoint(ep_ctx);
2094
2095 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2096 (unsigned int) ep->desc.bEndpointAddress,
2097 udev->slot_id,
2098 (unsigned int) new_drop_flags,
2099 (unsigned int) new_add_flags);
2100 return 0;
2101}
2102EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2103
2104static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2105{
2106 struct xhci_input_control_ctx *ctrl_ctx;
2107 struct xhci_ep_ctx *ep_ctx;
2108 struct xhci_slot_ctx *slot_ctx;
2109 int i;
2110
2111 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2112 if (!ctrl_ctx) {
2113 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2114 __func__);
2115 return;
2116 }
2117
2118 /* When a device's add flag and drop flag are zero, any subsequent
2119 * configure endpoint command will leave that endpoint's state
2120 * untouched. Make sure we don't leave any old state in the input
2121 * endpoint contexts.
2122 */
2123 ctrl_ctx->drop_flags = 0;
2124 ctrl_ctx->add_flags = 0;
2125 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2126 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2127 /* Endpoint 0 is always valid */
2128 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2129 for (i = 1; i < 31; i++) {
2130 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2131 ep_ctx->ep_info = 0;
2132 ep_ctx->ep_info2 = 0;
2133 ep_ctx->deq = 0;
2134 ep_ctx->tx_info = 0;
2135 }
2136}
2137
2138static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2139 struct usb_device *udev, u32 *cmd_status)
2140{
2141 int ret;
2142
2143 switch (*cmd_status) {
2144 case COMP_COMMAND_ABORTED:
2145 case COMP_COMMAND_RING_STOPPED:
2146 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2147 ret = -ETIME;
2148 break;
2149 case COMP_RESOURCE_ERROR:
2150 dev_warn(&udev->dev,
2151 "Not enough host controller resources for new device state.\n");
2152 ret = -ENOMEM;
2153 /* FIXME: can we allocate more resources for the HC? */
2154 break;
2155 case COMP_BANDWIDTH_ERROR:
2156 case COMP_SECONDARY_BANDWIDTH_ERROR:
2157 dev_warn(&udev->dev,
2158 "Not enough bandwidth for new device state.\n");
2159 ret = -ENOSPC;
2160 /* FIXME: can we go back to the old state? */
2161 break;
2162 case COMP_TRB_ERROR:
2163 /* the HCD set up something wrong */
2164 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2165 "add flag = 1, "
2166 "and endpoint is not disabled.\n");
2167 ret = -EINVAL;
2168 break;
2169 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2170 dev_warn(&udev->dev,
2171 "ERROR: Incompatible device for endpoint configure command.\n");
2172 ret = -ENODEV;
2173 break;
2174 case COMP_SUCCESS:
2175 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2176 "Successful Endpoint Configure command");
2177 ret = 0;
2178 break;
2179 default:
2180 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2181 *cmd_status);
2182 ret = -EINVAL;
2183 break;
2184 }
2185 return ret;
2186}
2187
2188static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2189 struct usb_device *udev, u32 *cmd_status)
2190{
2191 int ret;
2192
2193 switch (*cmd_status) {
2194 case COMP_COMMAND_ABORTED:
2195 case COMP_COMMAND_RING_STOPPED:
2196 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2197 ret = -ETIME;
2198 break;
2199 case COMP_PARAMETER_ERROR:
2200 dev_warn(&udev->dev,
2201 "WARN: xHCI driver setup invalid evaluate context command.\n");
2202 ret = -EINVAL;
2203 break;
2204 case COMP_SLOT_NOT_ENABLED_ERROR:
2205 dev_warn(&udev->dev,
2206 "WARN: slot not enabled for evaluate context command.\n");
2207 ret = -EINVAL;
2208 break;
2209 case COMP_CONTEXT_STATE_ERROR:
2210 dev_warn(&udev->dev,
2211 "WARN: invalid context state for evaluate context command.\n");
2212 ret = -EINVAL;
2213 break;
2214 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2215 dev_warn(&udev->dev,
2216 "ERROR: Incompatible device for evaluate context command.\n");
2217 ret = -ENODEV;
2218 break;
2219 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2220 /* Max Exit Latency too large error */
2221 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2222 ret = -EINVAL;
2223 break;
2224 case COMP_SUCCESS:
2225 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2226 "Successful evaluate context command");
2227 ret = 0;
2228 break;
2229 default:
2230 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2231 *cmd_status);
2232 ret = -EINVAL;
2233 break;
2234 }
2235 return ret;
2236}
2237
2238static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2239 struct xhci_input_control_ctx *ctrl_ctx)
2240{
2241 u32 valid_add_flags;
2242 u32 valid_drop_flags;
2243
2244 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2245 * (bit 1). The default control endpoint is added during the Address
2246 * Device command and is never removed until the slot is disabled.
2247 */
2248 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2249 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2250
2251 /* Use hweight32 to count the number of ones in the add flags, or
2252 * number of endpoints added. Don't count endpoints that are changed
2253 * (both added and dropped).
2254 */
2255 return hweight32(valid_add_flags) -
2256 hweight32(valid_add_flags & valid_drop_flags);
2257}
2258
2259static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2260 struct xhci_input_control_ctx *ctrl_ctx)
2261{
2262 u32 valid_add_flags;
2263 u32 valid_drop_flags;
2264
2265 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2266 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2267
2268 return hweight32(valid_drop_flags) -
2269 hweight32(valid_add_flags & valid_drop_flags);
2270}
2271
2272/*
2273 * We need to reserve the new number of endpoints before the configure endpoint
2274 * command completes. We can't subtract the dropped endpoints from the number
2275 * of active endpoints until the command completes because we can oversubscribe
2276 * the host in this case:
2277 *
2278 * - the first configure endpoint command drops more endpoints than it adds
2279 * - a second configure endpoint command that adds more endpoints is queued
2280 * - the first configure endpoint command fails, so the config is unchanged
2281 * - the second command may succeed, even though there isn't enough resources
2282 *
2283 * Must be called with xhci->lock held.
2284 */
2285static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2286 struct xhci_input_control_ctx *ctrl_ctx)
2287{
2288 u32 added_eps;
2289
2290 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2291 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2292 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2293 "Not enough ep ctxs: "
2294 "%u active, need to add %u, limit is %u.",
2295 xhci->num_active_eps, added_eps,
2296 xhci->limit_active_eps);
2297 return -ENOMEM;
2298 }
2299 xhci->num_active_eps += added_eps;
2300 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2301 "Adding %u ep ctxs, %u now active.", added_eps,
2302 xhci->num_active_eps);
2303 return 0;
2304}
2305
2306/*
2307 * The configure endpoint was failed by the xHC for some other reason, so we
2308 * need to revert the resources that failed configuration would have used.
2309 *
2310 * Must be called with xhci->lock held.
2311 */
2312static void xhci_free_host_resources(struct xhci_hcd *xhci,
2313 struct xhci_input_control_ctx *ctrl_ctx)
2314{
2315 u32 num_failed_eps;
2316
2317 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2318 xhci->num_active_eps -= num_failed_eps;
2319 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2320 "Removing %u failed ep ctxs, %u now active.",
2321 num_failed_eps,
2322 xhci->num_active_eps);
2323}
2324
2325/*
2326 * Now that the command has completed, clean up the active endpoint count by
2327 * subtracting out the endpoints that were dropped (but not changed).
2328 *
2329 * Must be called with xhci->lock held.
2330 */
2331static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2332 struct xhci_input_control_ctx *ctrl_ctx)
2333{
2334 u32 num_dropped_eps;
2335
2336 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2337 xhci->num_active_eps -= num_dropped_eps;
2338 if (num_dropped_eps)
2339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2340 "Removing %u dropped ep ctxs, %u now active.",
2341 num_dropped_eps,
2342 xhci->num_active_eps);
2343}
2344
2345static unsigned int xhci_get_block_size(struct usb_device *udev)
2346{
2347 switch (udev->speed) {
2348 case USB_SPEED_LOW:
2349 case USB_SPEED_FULL:
2350 return FS_BLOCK;
2351 case USB_SPEED_HIGH:
2352 return HS_BLOCK;
2353 case USB_SPEED_SUPER:
2354 case USB_SPEED_SUPER_PLUS:
2355 return SS_BLOCK;
2356 case USB_SPEED_UNKNOWN:
2357 case USB_SPEED_WIRELESS:
2358 default:
2359 /* Should never happen */
2360 return 1;
2361 }
2362}
2363
2364static unsigned int
2365xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2366{
2367 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2368 return LS_OVERHEAD;
2369 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2370 return FS_OVERHEAD;
2371 return HS_OVERHEAD;
2372}
2373
2374/* If we are changing a LS/FS device under a HS hub,
2375 * make sure (if we are activating a new TT) that the HS bus has enough
2376 * bandwidth for this new TT.
2377 */
2378static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2379 struct xhci_virt_device *virt_dev,
2380 int old_active_eps)
2381{
2382 struct xhci_interval_bw_table *bw_table;
2383 struct xhci_tt_bw_info *tt_info;
2384
2385 /* Find the bandwidth table for the root port this TT is attached to. */
2386 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2387 tt_info = virt_dev->tt_info;
2388 /* If this TT already had active endpoints, the bandwidth for this TT
2389 * has already been added. Removing all periodic endpoints (and thus
2390 * making the TT enactive) will only decrease the bandwidth used.
2391 */
2392 if (old_active_eps)
2393 return 0;
2394 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2395 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2396 return -ENOMEM;
2397 return 0;
2398 }
2399 /* Not sure why we would have no new active endpoints...
2400 *
2401 * Maybe because of an Evaluate Context change for a hub update or a
2402 * control endpoint 0 max packet size change?
2403 * FIXME: skip the bandwidth calculation in that case.
2404 */
2405 return 0;
2406}
2407
2408static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2409 struct xhci_virt_device *virt_dev)
2410{
2411 unsigned int bw_reserved;
2412
2413 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2414 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2415 return -ENOMEM;
2416
2417 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2418 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2419 return -ENOMEM;
2420
2421 return 0;
2422}
2423
2424/*
2425 * This algorithm is a very conservative estimate of the worst-case scheduling
2426 * scenario for any one interval. The hardware dynamically schedules the
2427 * packets, so we can't tell which microframe could be the limiting factor in
2428 * the bandwidth scheduling. This only takes into account periodic endpoints.
2429 *
2430 * Obviously, we can't solve an NP complete problem to find the minimum worst
2431 * case scenario. Instead, we come up with an estimate that is no less than
2432 * the worst case bandwidth used for any one microframe, but may be an
2433 * over-estimate.
2434 *
2435 * We walk the requirements for each endpoint by interval, starting with the
2436 * smallest interval, and place packets in the schedule where there is only one
2437 * possible way to schedule packets for that interval. In order to simplify
2438 * this algorithm, we record the largest max packet size for each interval, and
2439 * assume all packets will be that size.
2440 *
2441 * For interval 0, we obviously must schedule all packets for each interval.
2442 * The bandwidth for interval 0 is just the amount of data to be transmitted
2443 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2444 * the number of packets).
2445 *
2446 * For interval 1, we have two possible microframes to schedule those packets
2447 * in. For this algorithm, if we can schedule the same number of packets for
2448 * each possible scheduling opportunity (each microframe), we will do so. The
2449 * remaining number of packets will be saved to be transmitted in the gaps in
2450 * the next interval's scheduling sequence.
2451 *
2452 * As we move those remaining packets to be scheduled with interval 2 packets,
2453 * we have to double the number of remaining packets to transmit. This is
2454 * because the intervals are actually powers of 2, and we would be transmitting
2455 * the previous interval's packets twice in this interval. We also have to be
2456 * sure that when we look at the largest max packet size for this interval, we
2457 * also look at the largest max packet size for the remaining packets and take
2458 * the greater of the two.
2459 *
2460 * The algorithm continues to evenly distribute packets in each scheduling
2461 * opportunity, and push the remaining packets out, until we get to the last
2462 * interval. Then those packets and their associated overhead are just added
2463 * to the bandwidth used.
2464 */
2465static int xhci_check_bw_table(struct xhci_hcd *xhci,
2466 struct xhci_virt_device *virt_dev,
2467 int old_active_eps)
2468{
2469 unsigned int bw_reserved;
2470 unsigned int max_bandwidth;
2471 unsigned int bw_used;
2472 unsigned int block_size;
2473 struct xhci_interval_bw_table *bw_table;
2474 unsigned int packet_size = 0;
2475 unsigned int overhead = 0;
2476 unsigned int packets_transmitted = 0;
2477 unsigned int packets_remaining = 0;
2478 unsigned int i;
2479
2480 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2481 return xhci_check_ss_bw(xhci, virt_dev);
2482
2483 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2484 max_bandwidth = HS_BW_LIMIT;
2485 /* Convert percent of bus BW reserved to blocks reserved */
2486 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2487 } else {
2488 max_bandwidth = FS_BW_LIMIT;
2489 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2490 }
2491
2492 bw_table = virt_dev->bw_table;
2493 /* We need to translate the max packet size and max ESIT payloads into
2494 * the units the hardware uses.
2495 */
2496 block_size = xhci_get_block_size(virt_dev->udev);
2497
2498 /* If we are manipulating a LS/FS device under a HS hub, double check
2499 * that the HS bus has enough bandwidth if we are activing a new TT.
2500 */
2501 if (virt_dev->tt_info) {
2502 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2503 "Recalculating BW for rootport %u",
2504 virt_dev->real_port);
2505 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2506 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2507 "newly activated TT.\n");
2508 return -ENOMEM;
2509 }
2510 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2511 "Recalculating BW for TT slot %u port %u",
2512 virt_dev->tt_info->slot_id,
2513 virt_dev->tt_info->ttport);
2514 } else {
2515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2516 "Recalculating BW for rootport %u",
2517 virt_dev->real_port);
2518 }
2519
2520 /* Add in how much bandwidth will be used for interval zero, or the
2521 * rounded max ESIT payload + number of packets * largest overhead.
2522 */
2523 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2524 bw_table->interval_bw[0].num_packets *
2525 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2526
2527 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2528 unsigned int bw_added;
2529 unsigned int largest_mps;
2530 unsigned int interval_overhead;
2531
2532 /*
2533 * How many packets could we transmit in this interval?
2534 * If packets didn't fit in the previous interval, we will need
2535 * to transmit that many packets twice within this interval.
2536 */
2537 packets_remaining = 2 * packets_remaining +
2538 bw_table->interval_bw[i].num_packets;
2539
2540 /* Find the largest max packet size of this or the previous
2541 * interval.
2542 */
2543 if (list_empty(&bw_table->interval_bw[i].endpoints))
2544 largest_mps = 0;
2545 else {
2546 struct xhci_virt_ep *virt_ep;
2547 struct list_head *ep_entry;
2548
2549 ep_entry = bw_table->interval_bw[i].endpoints.next;
2550 virt_ep = list_entry(ep_entry,
2551 struct xhci_virt_ep, bw_endpoint_list);
2552 /* Convert to blocks, rounding up */
2553 largest_mps = DIV_ROUND_UP(
2554 virt_ep->bw_info.max_packet_size,
2555 block_size);
2556 }
2557 if (largest_mps > packet_size)
2558 packet_size = largest_mps;
2559
2560 /* Use the larger overhead of this or the previous interval. */
2561 interval_overhead = xhci_get_largest_overhead(
2562 &bw_table->interval_bw[i]);
2563 if (interval_overhead > overhead)
2564 overhead = interval_overhead;
2565
2566 /* How many packets can we evenly distribute across
2567 * (1 << (i + 1)) possible scheduling opportunities?
2568 */
2569 packets_transmitted = packets_remaining >> (i + 1);
2570
2571 /* Add in the bandwidth used for those scheduled packets */
2572 bw_added = packets_transmitted * (overhead + packet_size);
2573
2574 /* How many packets do we have remaining to transmit? */
2575 packets_remaining = packets_remaining % (1 << (i + 1));
2576
2577 /* What largest max packet size should those packets have? */
2578 /* If we've transmitted all packets, don't carry over the
2579 * largest packet size.
2580 */
2581 if (packets_remaining == 0) {
2582 packet_size = 0;
2583 overhead = 0;
2584 } else if (packets_transmitted > 0) {
2585 /* Otherwise if we do have remaining packets, and we've
2586 * scheduled some packets in this interval, take the
2587 * largest max packet size from endpoints with this
2588 * interval.
2589 */
2590 packet_size = largest_mps;
2591 overhead = interval_overhead;
2592 }
2593 /* Otherwise carry over packet_size and overhead from the last
2594 * time we had a remainder.
2595 */
2596 bw_used += bw_added;
2597 if (bw_used > max_bandwidth) {
2598 xhci_warn(xhci, "Not enough bandwidth. "
2599 "Proposed: %u, Max: %u\n",
2600 bw_used, max_bandwidth);
2601 return -ENOMEM;
2602 }
2603 }
2604 /*
2605 * Ok, we know we have some packets left over after even-handedly
2606 * scheduling interval 15. We don't know which microframes they will
2607 * fit into, so we over-schedule and say they will be scheduled every
2608 * microframe.
2609 */
2610 if (packets_remaining > 0)
2611 bw_used += overhead + packet_size;
2612
2613 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2614 unsigned int port_index = virt_dev->real_port - 1;
2615
2616 /* OK, we're manipulating a HS device attached to a
2617 * root port bandwidth domain. Include the number of active TTs
2618 * in the bandwidth used.
2619 */
2620 bw_used += TT_HS_OVERHEAD *
2621 xhci->rh_bw[port_index].num_active_tts;
2622 }
2623
2624 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2625 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2626 "Available: %u " "percent",
2627 bw_used, max_bandwidth, bw_reserved,
2628 (max_bandwidth - bw_used - bw_reserved) * 100 /
2629 max_bandwidth);
2630
2631 bw_used += bw_reserved;
2632 if (bw_used > max_bandwidth) {
2633 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2634 bw_used, max_bandwidth);
2635 return -ENOMEM;
2636 }
2637
2638 bw_table->bw_used = bw_used;
2639 return 0;
2640}
2641
2642static bool xhci_is_async_ep(unsigned int ep_type)
2643{
2644 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2645 ep_type != ISOC_IN_EP &&
2646 ep_type != INT_IN_EP);
2647}
2648
2649static bool xhci_is_sync_in_ep(unsigned int ep_type)
2650{
2651 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2652}
2653
2654static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2655{
2656 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2657
2658 if (ep_bw->ep_interval == 0)
2659 return SS_OVERHEAD_BURST +
2660 (ep_bw->mult * ep_bw->num_packets *
2661 (SS_OVERHEAD + mps));
2662 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2663 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2664 1 << ep_bw->ep_interval);
2665
2666}
2667
2668static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2669 struct xhci_bw_info *ep_bw,
2670 struct xhci_interval_bw_table *bw_table,
2671 struct usb_device *udev,
2672 struct xhci_virt_ep *virt_ep,
2673 struct xhci_tt_bw_info *tt_info)
2674{
2675 struct xhci_interval_bw *interval_bw;
2676 int normalized_interval;
2677
2678 if (xhci_is_async_ep(ep_bw->type))
2679 return;
2680
2681 if (udev->speed >= USB_SPEED_SUPER) {
2682 if (xhci_is_sync_in_ep(ep_bw->type))
2683 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2684 xhci_get_ss_bw_consumed(ep_bw);
2685 else
2686 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2687 xhci_get_ss_bw_consumed(ep_bw);
2688 return;
2689 }
2690
2691 /* SuperSpeed endpoints never get added to intervals in the table, so
2692 * this check is only valid for HS/FS/LS devices.
2693 */
2694 if (list_empty(&virt_ep->bw_endpoint_list))
2695 return;
2696 /* For LS/FS devices, we need to translate the interval expressed in
2697 * microframes to frames.
2698 */
2699 if (udev->speed == USB_SPEED_HIGH)
2700 normalized_interval = ep_bw->ep_interval;
2701 else
2702 normalized_interval = ep_bw->ep_interval - 3;
2703
2704 if (normalized_interval == 0)
2705 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2706 interval_bw = &bw_table->interval_bw[normalized_interval];
2707 interval_bw->num_packets -= ep_bw->num_packets;
2708 switch (udev->speed) {
2709 case USB_SPEED_LOW:
2710 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2711 break;
2712 case USB_SPEED_FULL:
2713 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2714 break;
2715 case USB_SPEED_HIGH:
2716 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2717 break;
2718 case USB_SPEED_SUPER:
2719 case USB_SPEED_SUPER_PLUS:
2720 case USB_SPEED_UNKNOWN:
2721 case USB_SPEED_WIRELESS:
2722 /* Should never happen because only LS/FS/HS endpoints will get
2723 * added to the endpoint list.
2724 */
2725 return;
2726 }
2727 if (tt_info)
2728 tt_info->active_eps -= 1;
2729 list_del_init(&virt_ep->bw_endpoint_list);
2730}
2731
2732static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2733 struct xhci_bw_info *ep_bw,
2734 struct xhci_interval_bw_table *bw_table,
2735 struct usb_device *udev,
2736 struct xhci_virt_ep *virt_ep,
2737 struct xhci_tt_bw_info *tt_info)
2738{
2739 struct xhci_interval_bw *interval_bw;
2740 struct xhci_virt_ep *smaller_ep;
2741 int normalized_interval;
2742
2743 if (xhci_is_async_ep(ep_bw->type))
2744 return;
2745
2746 if (udev->speed == USB_SPEED_SUPER) {
2747 if (xhci_is_sync_in_ep(ep_bw->type))
2748 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2749 xhci_get_ss_bw_consumed(ep_bw);
2750 else
2751 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2752 xhci_get_ss_bw_consumed(ep_bw);
2753 return;
2754 }
2755
2756 /* For LS/FS devices, we need to translate the interval expressed in
2757 * microframes to frames.
2758 */
2759 if (udev->speed == USB_SPEED_HIGH)
2760 normalized_interval = ep_bw->ep_interval;
2761 else
2762 normalized_interval = ep_bw->ep_interval - 3;
2763
2764 if (normalized_interval == 0)
2765 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2766 interval_bw = &bw_table->interval_bw[normalized_interval];
2767 interval_bw->num_packets += ep_bw->num_packets;
2768 switch (udev->speed) {
2769 case USB_SPEED_LOW:
2770 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2771 break;
2772 case USB_SPEED_FULL:
2773 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2774 break;
2775 case USB_SPEED_HIGH:
2776 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2777 break;
2778 case USB_SPEED_SUPER:
2779 case USB_SPEED_SUPER_PLUS:
2780 case USB_SPEED_UNKNOWN:
2781 case USB_SPEED_WIRELESS:
2782 /* Should never happen because only LS/FS/HS endpoints will get
2783 * added to the endpoint list.
2784 */
2785 return;
2786 }
2787
2788 if (tt_info)
2789 tt_info->active_eps += 1;
2790 /* Insert the endpoint into the list, largest max packet size first. */
2791 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2792 bw_endpoint_list) {
2793 if (ep_bw->max_packet_size >=
2794 smaller_ep->bw_info.max_packet_size) {
2795 /* Add the new ep before the smaller endpoint */
2796 list_add_tail(&virt_ep->bw_endpoint_list,
2797 &smaller_ep->bw_endpoint_list);
2798 return;
2799 }
2800 }
2801 /* Add the new endpoint at the end of the list. */
2802 list_add_tail(&virt_ep->bw_endpoint_list,
2803 &interval_bw->endpoints);
2804}
2805
2806void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2807 struct xhci_virt_device *virt_dev,
2808 int old_active_eps)
2809{
2810 struct xhci_root_port_bw_info *rh_bw_info;
2811 if (!virt_dev->tt_info)
2812 return;
2813
2814 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2815 if (old_active_eps == 0 &&
2816 virt_dev->tt_info->active_eps != 0) {
2817 rh_bw_info->num_active_tts += 1;
2818 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2819 } else if (old_active_eps != 0 &&
2820 virt_dev->tt_info->active_eps == 0) {
2821 rh_bw_info->num_active_tts -= 1;
2822 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2823 }
2824}
2825
2826static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2827 struct xhci_virt_device *virt_dev,
2828 struct xhci_container_ctx *in_ctx)
2829{
2830 struct xhci_bw_info ep_bw_info[31];
2831 int i;
2832 struct xhci_input_control_ctx *ctrl_ctx;
2833 int old_active_eps = 0;
2834
2835 if (virt_dev->tt_info)
2836 old_active_eps = virt_dev->tt_info->active_eps;
2837
2838 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2839 if (!ctrl_ctx) {
2840 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2841 __func__);
2842 return -ENOMEM;
2843 }
2844
2845 for (i = 0; i < 31; i++) {
2846 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2847 continue;
2848
2849 /* Make a copy of the BW info in case we need to revert this */
2850 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2851 sizeof(ep_bw_info[i]));
2852 /* Drop the endpoint from the interval table if the endpoint is
2853 * being dropped or changed.
2854 */
2855 if (EP_IS_DROPPED(ctrl_ctx, i))
2856 xhci_drop_ep_from_interval_table(xhci,
2857 &virt_dev->eps[i].bw_info,
2858 virt_dev->bw_table,
2859 virt_dev->udev,
2860 &virt_dev->eps[i],
2861 virt_dev->tt_info);
2862 }
2863 /* Overwrite the information stored in the endpoints' bw_info */
2864 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2865 for (i = 0; i < 31; i++) {
2866 /* Add any changed or added endpoints to the interval table */
2867 if (EP_IS_ADDED(ctrl_ctx, i))
2868 xhci_add_ep_to_interval_table(xhci,
2869 &virt_dev->eps[i].bw_info,
2870 virt_dev->bw_table,
2871 virt_dev->udev,
2872 &virt_dev->eps[i],
2873 virt_dev->tt_info);
2874 }
2875
2876 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2877 /* Ok, this fits in the bandwidth we have.
2878 * Update the number of active TTs.
2879 */
2880 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2881 return 0;
2882 }
2883
2884 /* We don't have enough bandwidth for this, revert the stored info. */
2885 for (i = 0; i < 31; i++) {
2886 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2887 continue;
2888
2889 /* Drop the new copies of any added or changed endpoints from
2890 * the interval table.
2891 */
2892 if (EP_IS_ADDED(ctrl_ctx, i)) {
2893 xhci_drop_ep_from_interval_table(xhci,
2894 &virt_dev->eps[i].bw_info,
2895 virt_dev->bw_table,
2896 virt_dev->udev,
2897 &virt_dev->eps[i],
2898 virt_dev->tt_info);
2899 }
2900 /* Revert the endpoint back to its old information */
2901 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2902 sizeof(ep_bw_info[i]));
2903 /* Add any changed or dropped endpoints back into the table */
2904 if (EP_IS_DROPPED(ctrl_ctx, i))
2905 xhci_add_ep_to_interval_table(xhci,
2906 &virt_dev->eps[i].bw_info,
2907 virt_dev->bw_table,
2908 virt_dev->udev,
2909 &virt_dev->eps[i],
2910 virt_dev->tt_info);
2911 }
2912 return -ENOMEM;
2913}
2914
2915
2916/* Issue a configure endpoint command or evaluate context command
2917 * and wait for it to finish.
2918 */
2919static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2920 struct usb_device *udev,
2921 struct xhci_command *command,
2922 bool ctx_change, bool must_succeed)
2923{
2924 int ret;
2925 unsigned long flags;
2926 struct xhci_input_control_ctx *ctrl_ctx;
2927 struct xhci_virt_device *virt_dev;
2928 struct xhci_slot_ctx *slot_ctx;
2929
2930 if (!command)
2931 return -EINVAL;
2932
2933 spin_lock_irqsave(&xhci->lock, flags);
2934
2935 if (xhci->xhc_state & XHCI_STATE_DYING) {
2936 spin_unlock_irqrestore(&xhci->lock, flags);
2937 return -ESHUTDOWN;
2938 }
2939
2940 virt_dev = xhci->devs[udev->slot_id];
2941
2942 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2943 if (!ctrl_ctx) {
2944 spin_unlock_irqrestore(&xhci->lock, flags);
2945 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2946 __func__);
2947 return -ENOMEM;
2948 }
2949
2950 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2951 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2952 spin_unlock_irqrestore(&xhci->lock, flags);
2953 xhci_warn(xhci, "Not enough host resources, "
2954 "active endpoint contexts = %u\n",
2955 xhci->num_active_eps);
2956 return -ENOMEM;
2957 }
2958 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2959 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2960 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2961 xhci_free_host_resources(xhci, ctrl_ctx);
2962 spin_unlock_irqrestore(&xhci->lock, flags);
2963 xhci_warn(xhci, "Not enough bandwidth\n");
2964 return -ENOMEM;
2965 }
2966
2967 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2968
2969 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2970 trace_xhci_configure_endpoint(slot_ctx);
2971
2972 if (!ctx_change)
2973 ret = xhci_queue_configure_endpoint(xhci, command,
2974 command->in_ctx->dma,
2975 udev->slot_id, must_succeed);
2976 else
2977 ret = xhci_queue_evaluate_context(xhci, command,
2978 command->in_ctx->dma,
2979 udev->slot_id, must_succeed);
2980 if (ret < 0) {
2981 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2982 xhci_free_host_resources(xhci, ctrl_ctx);
2983 spin_unlock_irqrestore(&xhci->lock, flags);
2984 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2985 "FIXME allocate a new ring segment");
2986 return -ENOMEM;
2987 }
2988 xhci_ring_cmd_db(xhci);
2989 spin_unlock_irqrestore(&xhci->lock, flags);
2990
2991 /* Wait for the configure endpoint command to complete */
2992 wait_for_completion(command->completion);
2993
2994 if (!ctx_change)
2995 ret = xhci_configure_endpoint_result(xhci, udev,
2996 &command->status);
2997 else
2998 ret = xhci_evaluate_context_result(xhci, udev,
2999 &command->status);
3000
3001 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3002 spin_lock_irqsave(&xhci->lock, flags);
3003 /* If the command failed, remove the reserved resources.
3004 * Otherwise, clean up the estimate to include dropped eps.
3005 */
3006 if (ret)
3007 xhci_free_host_resources(xhci, ctrl_ctx);
3008 else
3009 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3010 spin_unlock_irqrestore(&xhci->lock, flags);
3011 }
3012 return ret;
3013}
3014
3015static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3016 struct xhci_virt_device *vdev, int i)
3017{
3018 struct xhci_virt_ep *ep = &vdev->eps[i];
3019
3020 if (ep->ep_state & EP_HAS_STREAMS) {
3021 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3022 xhci_get_endpoint_address(i));
3023 xhci_free_stream_info(xhci, ep->stream_info);
3024 ep->stream_info = NULL;
3025 ep->ep_state &= ~EP_HAS_STREAMS;
3026 }
3027}
3028
3029/* Called after one or more calls to xhci_add_endpoint() or
3030 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3031 * to call xhci_reset_bandwidth().
3032 *
3033 * Since we are in the middle of changing either configuration or
3034 * installing a new alt setting, the USB core won't allow URBs to be
3035 * enqueued for any endpoint on the old config or interface. Nothing
3036 * else should be touching the xhci->devs[slot_id] structure, so we
3037 * don't need to take the xhci->lock for manipulating that.
3038 */
3039int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3040{
3041 int i;
3042 int ret = 0;
3043 struct xhci_hcd *xhci;
3044 struct xhci_virt_device *virt_dev;
3045 struct xhci_input_control_ctx *ctrl_ctx;
3046 struct xhci_slot_ctx *slot_ctx;
3047 struct xhci_command *command;
3048
3049 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3050 if (ret <= 0)
3051 return ret;
3052 xhci = hcd_to_xhci(hcd);
3053 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3054 (xhci->xhc_state & XHCI_STATE_REMOVING))
3055 return -ENODEV;
3056
3057 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3058 virt_dev = xhci->devs[udev->slot_id];
3059
3060 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3061 if (!command)
3062 return -ENOMEM;
3063
3064 command->in_ctx = virt_dev->in_ctx;
3065
3066 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3067 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3068 if (!ctrl_ctx) {
3069 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3070 __func__);
3071 ret = -ENOMEM;
3072 goto command_cleanup;
3073 }
3074 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3075 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3076 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3077
3078 /* Don't issue the command if there's no endpoints to update. */
3079 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3080 ctrl_ctx->drop_flags == 0) {
3081 ret = 0;
3082 goto command_cleanup;
3083 }
3084 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3085 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3086 for (i = 31; i >= 1; i--) {
3087 __le32 le32 = cpu_to_le32(BIT(i));
3088
3089 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3090 || (ctrl_ctx->add_flags & le32) || i == 1) {
3091 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3092 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3093 break;
3094 }
3095 }
3096
3097 ret = xhci_configure_endpoint(xhci, udev, command,
3098 false, false);
3099 if (ret)
3100 /* Callee should call reset_bandwidth() */
3101 goto command_cleanup;
3102
3103 /* Free any rings that were dropped, but not changed. */
3104 for (i = 1; i < 31; i++) {
3105 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3106 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3107 xhci_free_endpoint_ring(xhci, virt_dev, i);
3108 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3109 }
3110 }
3111 xhci_zero_in_ctx(xhci, virt_dev);
3112 /*
3113 * Install any rings for completely new endpoints or changed endpoints,
3114 * and free any old rings from changed endpoints.
3115 */
3116 for (i = 1; i < 31; i++) {
3117 if (!virt_dev->eps[i].new_ring)
3118 continue;
3119 /* Only free the old ring if it exists.
3120 * It may not if this is the first add of an endpoint.
3121 */
3122 if (virt_dev->eps[i].ring) {
3123 xhci_free_endpoint_ring(xhci, virt_dev, i);
3124 }
3125 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3126 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3127 virt_dev->eps[i].new_ring = NULL;
3128 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3129 }
3130command_cleanup:
3131 kfree(command->completion);
3132 kfree(command);
3133
3134 return ret;
3135}
3136EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3137
3138void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3139{
3140 struct xhci_hcd *xhci;
3141 struct xhci_virt_device *virt_dev;
3142 int i, ret;
3143
3144 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3145 if (ret <= 0)
3146 return;
3147 xhci = hcd_to_xhci(hcd);
3148
3149 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3150 virt_dev = xhci->devs[udev->slot_id];
3151 /* Free any rings allocated for added endpoints */
3152 for (i = 0; i < 31; i++) {
3153 if (virt_dev->eps[i].new_ring) {
3154 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3155 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3156 virt_dev->eps[i].new_ring = NULL;
3157 }
3158 }
3159 xhci_zero_in_ctx(xhci, virt_dev);
3160}
3161EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3162
3163static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3164 struct xhci_container_ctx *in_ctx,
3165 struct xhci_container_ctx *out_ctx,
3166 struct xhci_input_control_ctx *ctrl_ctx,
3167 u32 add_flags, u32 drop_flags)
3168{
3169 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3170 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3171 xhci_slot_copy(xhci, in_ctx, out_ctx);
3172 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3173}
3174
3175static void xhci_endpoint_disable(struct usb_hcd *hcd,
3176 struct usb_host_endpoint *host_ep)
3177{
3178 struct xhci_hcd *xhci;
3179 struct xhci_virt_device *vdev;
3180 struct xhci_virt_ep *ep;
3181 struct usb_device *udev;
3182 unsigned long flags;
3183 unsigned int ep_index;
3184
3185 xhci = hcd_to_xhci(hcd);
3186rescan:
3187 spin_lock_irqsave(&xhci->lock, flags);
3188
3189 udev = (struct usb_device *)host_ep->hcpriv;
3190 if (!udev || !udev->slot_id)
3191 goto done;
3192
3193 vdev = xhci->devs[udev->slot_id];
3194 if (!vdev)
3195 goto done;
3196
3197 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3198 ep = &vdev->eps[ep_index];
3199
3200 /* wait for hub_tt_work to finish clearing hub TT */
3201 if (ep->ep_state & EP_CLEARING_TT) {
3202 spin_unlock_irqrestore(&xhci->lock, flags);
3203 schedule_timeout_uninterruptible(1);
3204 goto rescan;
3205 }
3206
3207 if (ep->ep_state)
3208 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3209 ep->ep_state);
3210done:
3211 host_ep->hcpriv = NULL;
3212 spin_unlock_irqrestore(&xhci->lock, flags);
3213}
3214
3215/*
3216 * Called after usb core issues a clear halt control message.
3217 * The host side of the halt should already be cleared by a reset endpoint
3218 * command issued when the STALL event was received.
3219 *
3220 * The reset endpoint command may only be issued to endpoints in the halted
3221 * state. For software that wishes to reset the data toggle or sequence number
3222 * of an endpoint that isn't in the halted state this function will issue a
3223 * configure endpoint command with the Drop and Add bits set for the target
3224 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3225 */
3226
3227static void xhci_endpoint_reset(struct usb_hcd *hcd,
3228 struct usb_host_endpoint *host_ep)
3229{
3230 struct xhci_hcd *xhci;
3231 struct usb_device *udev;
3232 struct xhci_virt_device *vdev;
3233 struct xhci_virt_ep *ep;
3234 struct xhci_input_control_ctx *ctrl_ctx;
3235 struct xhci_command *stop_cmd, *cfg_cmd;
3236 unsigned int ep_index;
3237 unsigned long flags;
3238 u32 ep_flag;
3239 int err;
3240
3241 xhci = hcd_to_xhci(hcd);
3242 if (!host_ep->hcpriv)
3243 return;
3244 udev = (struct usb_device *) host_ep->hcpriv;
3245 vdev = xhci->devs[udev->slot_id];
3246
3247 /*
3248 * vdev may be lost due to xHC restore error and re-initialization
3249 * during S3/S4 resume. A new vdev will be allocated later by
3250 * xhci_discover_or_reset_device()
3251 */
3252 if (!udev->slot_id || !vdev)
3253 return;
3254 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3255 ep = &vdev->eps[ep_index];
3256
3257 /* Bail out if toggle is already being cleared by a endpoint reset */
3258 spin_lock_irqsave(&xhci->lock, flags);
3259 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3260 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3261 spin_unlock_irqrestore(&xhci->lock, flags);
3262 return;
3263 }
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3265 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3266 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3267 usb_endpoint_xfer_isoc(&host_ep->desc))
3268 return;
3269
3270 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3271
3272 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3273 return;
3274
3275 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3276 if (!stop_cmd)
3277 return;
3278
3279 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3280 if (!cfg_cmd)
3281 goto cleanup;
3282
3283 spin_lock_irqsave(&xhci->lock, flags);
3284
3285 /* block queuing new trbs and ringing ep doorbell */
3286 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3287
3288 /*
3289 * Make sure endpoint ring is empty before resetting the toggle/seq.
3290 * Driver is required to synchronously cancel all transfer request.
3291 * Stop the endpoint to force xHC to update the output context
3292 */
3293
3294 if (!list_empty(&ep->ring->td_list)) {
3295 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3296 spin_unlock_irqrestore(&xhci->lock, flags);
3297 xhci_free_command(xhci, cfg_cmd);
3298 goto cleanup;
3299 }
3300
3301 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3302 ep_index, 0);
3303 if (err < 0) {
3304 spin_unlock_irqrestore(&xhci->lock, flags);
3305 xhci_free_command(xhci, cfg_cmd);
3306 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3307 __func__, err);
3308 goto cleanup;
3309 }
3310
3311 xhci_ring_cmd_db(xhci);
3312 spin_unlock_irqrestore(&xhci->lock, flags);
3313
3314 wait_for_completion(stop_cmd->completion);
3315
3316 spin_lock_irqsave(&xhci->lock, flags);
3317
3318 /* config ep command clears toggle if add and drop ep flags are set */
3319 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3320 if (!ctrl_ctx) {
3321 spin_unlock_irqrestore(&xhci->lock, flags);
3322 xhci_free_command(xhci, cfg_cmd);
3323 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3324 __func__);
3325 goto cleanup;
3326 }
3327
3328 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3329 ctrl_ctx, ep_flag, ep_flag);
3330 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3331
3332 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3333 udev->slot_id, false);
3334 if (err < 0) {
3335 spin_unlock_irqrestore(&xhci->lock, flags);
3336 xhci_free_command(xhci, cfg_cmd);
3337 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3338 __func__, err);
3339 goto cleanup;
3340 }
3341
3342 xhci_ring_cmd_db(xhci);
3343 spin_unlock_irqrestore(&xhci->lock, flags);
3344
3345 wait_for_completion(cfg_cmd->completion);
3346
3347 xhci_free_command(xhci, cfg_cmd);
3348cleanup:
3349 xhci_free_command(xhci, stop_cmd);
3350 spin_lock_irqsave(&xhci->lock, flags);
3351 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3352 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3353 spin_unlock_irqrestore(&xhci->lock, flags);
3354}
3355
3356static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3357 struct usb_device *udev, struct usb_host_endpoint *ep,
3358 unsigned int slot_id)
3359{
3360 int ret;
3361 unsigned int ep_index;
3362 unsigned int ep_state;
3363
3364 if (!ep)
3365 return -EINVAL;
3366 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3367 if (ret <= 0)
3368 return ret ? ret : -EINVAL;
3369 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3370 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3371 " descriptor for ep 0x%x does not support streams\n",
3372 ep->desc.bEndpointAddress);
3373 return -EINVAL;
3374 }
3375
3376 ep_index = xhci_get_endpoint_index(&ep->desc);
3377 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3378 if (ep_state & EP_HAS_STREAMS ||
3379 ep_state & EP_GETTING_STREAMS) {
3380 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3381 "already has streams set up.\n",
3382 ep->desc.bEndpointAddress);
3383 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3384 "dynamic stream context array reallocation.\n");
3385 return -EINVAL;
3386 }
3387 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3388 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3389 "endpoint 0x%x; URBs are pending.\n",
3390 ep->desc.bEndpointAddress);
3391 return -EINVAL;
3392 }
3393 return 0;
3394}
3395
3396static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3397 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3398{
3399 unsigned int max_streams;
3400
3401 /* The stream context array size must be a power of two */
3402 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3403 /*
3404 * Find out how many primary stream array entries the host controller
3405 * supports. Later we may use secondary stream arrays (similar to 2nd
3406 * level page entries), but that's an optional feature for xHCI host
3407 * controllers. xHCs must support at least 4 stream IDs.
3408 */
3409 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3410 if (*num_stream_ctxs > max_streams) {
3411 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3412 max_streams);
3413 *num_stream_ctxs = max_streams;
3414 *num_streams = max_streams;
3415 }
3416}
3417
3418/* Returns an error code if one of the endpoint already has streams.
3419 * This does not change any data structures, it only checks and gathers
3420 * information.
3421 */
3422static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3423 struct usb_device *udev,
3424 struct usb_host_endpoint **eps, unsigned int num_eps,
3425 unsigned int *num_streams, u32 *changed_ep_bitmask)
3426{
3427 unsigned int max_streams;
3428 unsigned int endpoint_flag;
3429 int i;
3430 int ret;
3431
3432 for (i = 0; i < num_eps; i++) {
3433 ret = xhci_check_streams_endpoint(xhci, udev,
3434 eps[i], udev->slot_id);
3435 if (ret < 0)
3436 return ret;
3437
3438 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3439 if (max_streams < (*num_streams - 1)) {
3440 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3441 eps[i]->desc.bEndpointAddress,
3442 max_streams);
3443 *num_streams = max_streams+1;
3444 }
3445
3446 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3447 if (*changed_ep_bitmask & endpoint_flag)
3448 return -EINVAL;
3449 *changed_ep_bitmask |= endpoint_flag;
3450 }
3451 return 0;
3452}
3453
3454static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3455 struct usb_device *udev,
3456 struct usb_host_endpoint **eps, unsigned int num_eps)
3457{
3458 u32 changed_ep_bitmask = 0;
3459 unsigned int slot_id;
3460 unsigned int ep_index;
3461 unsigned int ep_state;
3462 int i;
3463
3464 slot_id = udev->slot_id;
3465 if (!xhci->devs[slot_id])
3466 return 0;
3467
3468 for (i = 0; i < num_eps; i++) {
3469 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3470 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3471 /* Are streams already being freed for the endpoint? */
3472 if (ep_state & EP_GETTING_NO_STREAMS) {
3473 xhci_warn(xhci, "WARN Can't disable streams for "
3474 "endpoint 0x%x, "
3475 "streams are being disabled already\n",
3476 eps[i]->desc.bEndpointAddress);
3477 return 0;
3478 }
3479 /* Are there actually any streams to free? */
3480 if (!(ep_state & EP_HAS_STREAMS) &&
3481 !(ep_state & EP_GETTING_STREAMS)) {
3482 xhci_warn(xhci, "WARN Can't disable streams for "
3483 "endpoint 0x%x, "
3484 "streams are already disabled!\n",
3485 eps[i]->desc.bEndpointAddress);
3486 xhci_warn(xhci, "WARN xhci_free_streams() called "
3487 "with non-streams endpoint\n");
3488 return 0;
3489 }
3490 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3491 }
3492 return changed_ep_bitmask;
3493}
3494
3495/*
3496 * The USB device drivers use this function (through the HCD interface in USB
3497 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3498 * coordinate mass storage command queueing across multiple endpoints (basically
3499 * a stream ID == a task ID).
3500 *
3501 * Setting up streams involves allocating the same size stream context array
3502 * for each endpoint and issuing a configure endpoint command for all endpoints.
3503 *
3504 * Don't allow the call to succeed if one endpoint only supports one stream
3505 * (which means it doesn't support streams at all).
3506 *
3507 * Drivers may get less stream IDs than they asked for, if the host controller
3508 * hardware or endpoints claim they can't support the number of requested
3509 * stream IDs.
3510 */
3511static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3512 struct usb_host_endpoint **eps, unsigned int num_eps,
3513 unsigned int num_streams, gfp_t mem_flags)
3514{
3515 int i, ret;
3516 struct xhci_hcd *xhci;
3517 struct xhci_virt_device *vdev;
3518 struct xhci_command *config_cmd;
3519 struct xhci_input_control_ctx *ctrl_ctx;
3520 unsigned int ep_index;
3521 unsigned int num_stream_ctxs;
3522 unsigned int max_packet;
3523 unsigned long flags;
3524 u32 changed_ep_bitmask = 0;
3525
3526 if (!eps)
3527 return -EINVAL;
3528
3529 /* Add one to the number of streams requested to account for
3530 * stream 0 that is reserved for xHCI usage.
3531 */
3532 num_streams += 1;
3533 xhci = hcd_to_xhci(hcd);
3534 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3535 num_streams);
3536
3537 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3538 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3539 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3540 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3541 return -ENOSYS;
3542 }
3543
3544 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3545 if (!config_cmd)
3546 return -ENOMEM;
3547
3548 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3549 if (!ctrl_ctx) {
3550 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3551 __func__);
3552 xhci_free_command(xhci, config_cmd);
3553 return -ENOMEM;
3554 }
3555
3556 /* Check to make sure all endpoints are not already configured for
3557 * streams. While we're at it, find the maximum number of streams that
3558 * all the endpoints will support and check for duplicate endpoints.
3559 */
3560 spin_lock_irqsave(&xhci->lock, flags);
3561 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3562 num_eps, &num_streams, &changed_ep_bitmask);
3563 if (ret < 0) {
3564 xhci_free_command(xhci, config_cmd);
3565 spin_unlock_irqrestore(&xhci->lock, flags);
3566 return ret;
3567 }
3568 if (num_streams <= 1) {
3569 xhci_warn(xhci, "WARN: endpoints can't handle "
3570 "more than one stream.\n");
3571 xhci_free_command(xhci, config_cmd);
3572 spin_unlock_irqrestore(&xhci->lock, flags);
3573 return -EINVAL;
3574 }
3575 vdev = xhci->devs[udev->slot_id];
3576 /* Mark each endpoint as being in transition, so
3577 * xhci_urb_enqueue() will reject all URBs.
3578 */
3579 for (i = 0; i < num_eps; i++) {
3580 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3581 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3582 }
3583 spin_unlock_irqrestore(&xhci->lock, flags);
3584
3585 /* Setup internal data structures and allocate HW data structures for
3586 * streams (but don't install the HW structures in the input context
3587 * until we're sure all memory allocation succeeded).
3588 */
3589 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3590 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3591 num_stream_ctxs, num_streams);
3592
3593 for (i = 0; i < num_eps; i++) {
3594 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3595 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3596 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3597 num_stream_ctxs,
3598 num_streams,
3599 max_packet, mem_flags);
3600 if (!vdev->eps[ep_index].stream_info)
3601 goto cleanup;
3602 /* Set maxPstreams in endpoint context and update deq ptr to
3603 * point to stream context array. FIXME
3604 */
3605 }
3606
3607 /* Set up the input context for a configure endpoint command. */
3608 for (i = 0; i < num_eps; i++) {
3609 struct xhci_ep_ctx *ep_ctx;
3610
3611 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3612 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3613
3614 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3615 vdev->out_ctx, ep_index);
3616 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3617 vdev->eps[ep_index].stream_info);
3618 }
3619 /* Tell the HW to drop its old copy of the endpoint context info
3620 * and add the updated copy from the input context.
3621 */
3622 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3623 vdev->out_ctx, ctrl_ctx,
3624 changed_ep_bitmask, changed_ep_bitmask);
3625
3626 /* Issue and wait for the configure endpoint command */
3627 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3628 false, false);
3629
3630 /* xHC rejected the configure endpoint command for some reason, so we
3631 * leave the old ring intact and free our internal streams data
3632 * structure.
3633 */
3634 if (ret < 0)
3635 goto cleanup;
3636
3637 spin_lock_irqsave(&xhci->lock, flags);
3638 for (i = 0; i < num_eps; i++) {
3639 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3640 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3641 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3642 udev->slot_id, ep_index);
3643 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3644 }
3645 xhci_free_command(xhci, config_cmd);
3646 spin_unlock_irqrestore(&xhci->lock, flags);
3647
3648 for (i = 0; i < num_eps; i++) {
3649 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3650 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3651 }
3652 /* Subtract 1 for stream 0, which drivers can't use */
3653 return num_streams - 1;
3654
3655cleanup:
3656 /* If it didn't work, free the streams! */
3657 for (i = 0; i < num_eps; i++) {
3658 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3659 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3660 vdev->eps[ep_index].stream_info = NULL;
3661 /* FIXME Unset maxPstreams in endpoint context and
3662 * update deq ptr to point to normal string ring.
3663 */
3664 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3665 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3666 xhci_endpoint_zero(xhci, vdev, eps[i]);
3667 }
3668 xhci_free_command(xhci, config_cmd);
3669 return -ENOMEM;
3670}
3671
3672/* Transition the endpoint from using streams to being a "normal" endpoint
3673 * without streams.
3674 *
3675 * Modify the endpoint context state, submit a configure endpoint command,
3676 * and free all endpoint rings for streams if that completes successfully.
3677 */
3678static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3679 struct usb_host_endpoint **eps, unsigned int num_eps,
3680 gfp_t mem_flags)
3681{
3682 int i, ret;
3683 struct xhci_hcd *xhci;
3684 struct xhci_virt_device *vdev;
3685 struct xhci_command *command;
3686 struct xhci_input_control_ctx *ctrl_ctx;
3687 unsigned int ep_index;
3688 unsigned long flags;
3689 u32 changed_ep_bitmask;
3690
3691 xhci = hcd_to_xhci(hcd);
3692 vdev = xhci->devs[udev->slot_id];
3693
3694 /* Set up a configure endpoint command to remove the streams rings */
3695 spin_lock_irqsave(&xhci->lock, flags);
3696 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3697 udev, eps, num_eps);
3698 if (changed_ep_bitmask == 0) {
3699 spin_unlock_irqrestore(&xhci->lock, flags);
3700 return -EINVAL;
3701 }
3702
3703 /* Use the xhci_command structure from the first endpoint. We may have
3704 * allocated too many, but the driver may call xhci_free_streams() for
3705 * each endpoint it grouped into one call to xhci_alloc_streams().
3706 */
3707 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3708 command = vdev->eps[ep_index].stream_info->free_streams_command;
3709 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3710 if (!ctrl_ctx) {
3711 spin_unlock_irqrestore(&xhci->lock, flags);
3712 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3713 __func__);
3714 return -EINVAL;
3715 }
3716
3717 for (i = 0; i < num_eps; i++) {
3718 struct xhci_ep_ctx *ep_ctx;
3719
3720 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3721 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3722 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3723 EP_GETTING_NO_STREAMS;
3724
3725 xhci_endpoint_copy(xhci, command->in_ctx,
3726 vdev->out_ctx, ep_index);
3727 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3728 &vdev->eps[ep_index]);
3729 }
3730 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3731 vdev->out_ctx, ctrl_ctx,
3732 changed_ep_bitmask, changed_ep_bitmask);
3733 spin_unlock_irqrestore(&xhci->lock, flags);
3734
3735 /* Issue and wait for the configure endpoint command,
3736 * which must succeed.
3737 */
3738 ret = xhci_configure_endpoint(xhci, udev, command,
3739 false, true);
3740
3741 /* xHC rejected the configure endpoint command for some reason, so we
3742 * leave the streams rings intact.
3743 */
3744 if (ret < 0)
3745 return ret;
3746
3747 spin_lock_irqsave(&xhci->lock, flags);
3748 for (i = 0; i < num_eps; i++) {
3749 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3750 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3751 vdev->eps[ep_index].stream_info = NULL;
3752 /* FIXME Unset maxPstreams in endpoint context and
3753 * update deq ptr to point to normal string ring.
3754 */
3755 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3756 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3757 }
3758 spin_unlock_irqrestore(&xhci->lock, flags);
3759
3760 return 0;
3761}
3762
3763/*
3764 * Deletes endpoint resources for endpoints that were active before a Reset
3765 * Device command, or a Disable Slot command. The Reset Device command leaves
3766 * the control endpoint intact, whereas the Disable Slot command deletes it.
3767 *
3768 * Must be called with xhci->lock held.
3769 */
3770void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3771 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3772{
3773 int i;
3774 unsigned int num_dropped_eps = 0;
3775 unsigned int drop_flags = 0;
3776
3777 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3778 if (virt_dev->eps[i].ring) {
3779 drop_flags |= 1 << i;
3780 num_dropped_eps++;
3781 }
3782 }
3783 xhci->num_active_eps -= num_dropped_eps;
3784 if (num_dropped_eps)
3785 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3786 "Dropped %u ep ctxs, flags = 0x%x, "
3787 "%u now active.",
3788 num_dropped_eps, drop_flags,
3789 xhci->num_active_eps);
3790}
3791
3792/*
3793 * This submits a Reset Device Command, which will set the device state to 0,
3794 * set the device address to 0, and disable all the endpoints except the default
3795 * control endpoint. The USB core should come back and call
3796 * xhci_address_device(), and then re-set up the configuration. If this is
3797 * called because of a usb_reset_and_verify_device(), then the old alternate
3798 * settings will be re-installed through the normal bandwidth allocation
3799 * functions.
3800 *
3801 * Wait for the Reset Device command to finish. Remove all structures
3802 * associated with the endpoints that were disabled. Clear the input device
3803 * structure? Reset the control endpoint 0 max packet size?
3804 *
3805 * If the virt_dev to be reset does not exist or does not match the udev,
3806 * it means the device is lost, possibly due to the xHC restore error and
3807 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3808 * re-allocate the device.
3809 */
3810static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3811 struct usb_device *udev)
3812{
3813 int ret, i;
3814 unsigned long flags;
3815 struct xhci_hcd *xhci;
3816 unsigned int slot_id;
3817 struct xhci_virt_device *virt_dev;
3818 struct xhci_command *reset_device_cmd;
3819 struct xhci_slot_ctx *slot_ctx;
3820 int old_active_eps = 0;
3821
3822 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3823 if (ret <= 0)
3824 return ret;
3825 xhci = hcd_to_xhci(hcd);
3826 slot_id = udev->slot_id;
3827 virt_dev = xhci->devs[slot_id];
3828 if (!virt_dev) {
3829 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3830 "not exist. Re-allocate the device\n", slot_id);
3831 ret = xhci_alloc_dev(hcd, udev);
3832 if (ret == 1)
3833 return 0;
3834 else
3835 return -EINVAL;
3836 }
3837
3838 if (virt_dev->tt_info)
3839 old_active_eps = virt_dev->tt_info->active_eps;
3840
3841 if (virt_dev->udev != udev) {
3842 /* If the virt_dev and the udev does not match, this virt_dev
3843 * may belong to another udev.
3844 * Re-allocate the device.
3845 */
3846 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3847 "not match the udev. Re-allocate the device\n",
3848 slot_id);
3849 ret = xhci_alloc_dev(hcd, udev);
3850 if (ret == 1)
3851 return 0;
3852 else
3853 return -EINVAL;
3854 }
3855
3856 /* If device is not setup, there is no point in resetting it */
3857 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3858 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3859 SLOT_STATE_DISABLED)
3860 return 0;
3861
3862 trace_xhci_discover_or_reset_device(slot_ctx);
3863
3864 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3865 /* Allocate the command structure that holds the struct completion.
3866 * Assume we're in process context, since the normal device reset
3867 * process has to wait for the device anyway. Storage devices are
3868 * reset as part of error handling, so use GFP_NOIO instead of
3869 * GFP_KERNEL.
3870 */
3871 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3872 if (!reset_device_cmd) {
3873 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3874 return -ENOMEM;
3875 }
3876
3877 /* Attempt to submit the Reset Device command to the command ring */
3878 spin_lock_irqsave(&xhci->lock, flags);
3879
3880 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3881 if (ret) {
3882 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3883 spin_unlock_irqrestore(&xhci->lock, flags);
3884 goto command_cleanup;
3885 }
3886 xhci_ring_cmd_db(xhci);
3887 spin_unlock_irqrestore(&xhci->lock, flags);
3888
3889 /* Wait for the Reset Device command to finish */
3890 wait_for_completion(reset_device_cmd->completion);
3891
3892 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3893 * unless we tried to reset a slot ID that wasn't enabled,
3894 * or the device wasn't in the addressed or configured state.
3895 */
3896 ret = reset_device_cmd->status;
3897 switch (ret) {
3898 case COMP_COMMAND_ABORTED:
3899 case COMP_COMMAND_RING_STOPPED:
3900 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3901 ret = -ETIME;
3902 goto command_cleanup;
3903 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3904 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3905 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3906 slot_id,
3907 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3908 xhci_dbg(xhci, "Not freeing device rings.\n");
3909 /* Don't treat this as an error. May change my mind later. */
3910 ret = 0;
3911 goto command_cleanup;
3912 case COMP_SUCCESS:
3913 xhci_dbg(xhci, "Successful reset device command.\n");
3914 break;
3915 default:
3916 if (xhci_is_vendor_info_code(xhci, ret))
3917 break;
3918 xhci_warn(xhci, "Unknown completion code %u for "
3919 "reset device command.\n", ret);
3920 ret = -EINVAL;
3921 goto command_cleanup;
3922 }
3923
3924 /* Free up host controller endpoint resources */
3925 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3926 spin_lock_irqsave(&xhci->lock, flags);
3927 /* Don't delete the default control endpoint resources */
3928 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3929 spin_unlock_irqrestore(&xhci->lock, flags);
3930 }
3931
3932 /* Everything but endpoint 0 is disabled, so free the rings. */
3933 for (i = 1; i < 31; i++) {
3934 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3935
3936 if (ep->ep_state & EP_HAS_STREAMS) {
3937 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3938 xhci_get_endpoint_address(i));
3939 xhci_free_stream_info(xhci, ep->stream_info);
3940 ep->stream_info = NULL;
3941 ep->ep_state &= ~EP_HAS_STREAMS;
3942 }
3943
3944 if (ep->ring) {
3945 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3946 xhci_free_endpoint_ring(xhci, virt_dev, i);
3947 }
3948 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3949 xhci_drop_ep_from_interval_table(xhci,
3950 &virt_dev->eps[i].bw_info,
3951 virt_dev->bw_table,
3952 udev,
3953 &virt_dev->eps[i],
3954 virt_dev->tt_info);
3955 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3956 }
3957 /* If necessary, update the number of active TTs on this root port */
3958 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3959 virt_dev->flags = 0;
3960 ret = 0;
3961
3962command_cleanup:
3963 xhci_free_command(xhci, reset_device_cmd);
3964 return ret;
3965}
3966
3967/*
3968 * At this point, the struct usb_device is about to go away, the device has
3969 * disconnected, and all traffic has been stopped and the endpoints have been
3970 * disabled. Free any HC data structures associated with that device.
3971 */
3972static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3973{
3974 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3975 struct xhci_virt_device *virt_dev;
3976 struct xhci_slot_ctx *slot_ctx;
3977 unsigned long flags;
3978 int i, ret;
3979
3980 /*
3981 * We called pm_runtime_get_noresume when the device was attached.
3982 * Decrement the counter here to allow controller to runtime suspend
3983 * if no devices remain.
3984 */
3985 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3986 pm_runtime_put_noidle(hcd->self.controller);
3987
3988 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3989 /* If the host is halted due to driver unload, we still need to free the
3990 * device.
3991 */
3992 if (ret <= 0 && ret != -ENODEV)
3993 return;
3994
3995 virt_dev = xhci->devs[udev->slot_id];
3996 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3997 trace_xhci_free_dev(slot_ctx);
3998
3999 /* Stop any wayward timer functions (which may grab the lock) */
4000 for (i = 0; i < 31; i++)
4001 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4002 virt_dev->udev = NULL;
4003 xhci_disable_slot(xhci, udev->slot_id);
4004
4005 spin_lock_irqsave(&xhci->lock, flags);
4006 xhci_free_virt_device(xhci, udev->slot_id);
4007 spin_unlock_irqrestore(&xhci->lock, flags);
4008
4009}
4010
4011int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4012{
4013 struct xhci_command *command;
4014 unsigned long flags;
4015 u32 state;
4016 int ret;
4017
4018 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4019 if (!command)
4020 return -ENOMEM;
4021
4022 xhci_debugfs_remove_slot(xhci, slot_id);
4023
4024 spin_lock_irqsave(&xhci->lock, flags);
4025 /* Don't disable the slot if the host controller is dead. */
4026 state = readl(&xhci->op_regs->status);
4027 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4028 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4029 spin_unlock_irqrestore(&xhci->lock, flags);
4030 kfree(command);
4031 return -ENODEV;
4032 }
4033
4034 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4035 slot_id);
4036 if (ret) {
4037 spin_unlock_irqrestore(&xhci->lock, flags);
4038 kfree(command);
4039 return ret;
4040 }
4041 xhci_ring_cmd_db(xhci);
4042 spin_unlock_irqrestore(&xhci->lock, flags);
4043
4044 wait_for_completion(command->completion);
4045
4046 if (command->status != COMP_SUCCESS)
4047 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4048 slot_id, command->status);
4049
4050 xhci_free_command(xhci, command);
4051
4052 return 0;
4053}
4054
4055/*
4056 * Checks if we have enough host controller resources for the default control
4057 * endpoint.
4058 *
4059 * Must be called with xhci->lock held.
4060 */
4061static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4062{
4063 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4064 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4065 "Not enough ep ctxs: "
4066 "%u active, need to add 1, limit is %u.",
4067 xhci->num_active_eps, xhci->limit_active_eps);
4068 return -ENOMEM;
4069 }
4070 xhci->num_active_eps += 1;
4071 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4072 "Adding 1 ep ctx, %u now active.",
4073 xhci->num_active_eps);
4074 return 0;
4075}
4076
4077
4078/*
4079 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4080 * timed out, or allocating memory failed. Returns 1 on success.
4081 */
4082int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4083{
4084 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4085 struct xhci_virt_device *vdev;
4086 struct xhci_slot_ctx *slot_ctx;
4087 unsigned long flags;
4088 int ret, slot_id;
4089 struct xhci_command *command;
4090
4091 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4092 if (!command)
4093 return 0;
4094
4095 spin_lock_irqsave(&xhci->lock, flags);
4096 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4097 if (ret) {
4098 spin_unlock_irqrestore(&xhci->lock, flags);
4099 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4100 xhci_free_command(xhci, command);
4101 return 0;
4102 }
4103 xhci_ring_cmd_db(xhci);
4104 spin_unlock_irqrestore(&xhci->lock, flags);
4105
4106 wait_for_completion(command->completion);
4107 slot_id = command->slot_id;
4108
4109 if (!slot_id || command->status != COMP_SUCCESS) {
4110 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4111 xhci_trb_comp_code_string(command->status));
4112 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4113 HCS_MAX_SLOTS(
4114 readl(&xhci->cap_regs->hcs_params1)));
4115 xhci_free_command(xhci, command);
4116 return 0;
4117 }
4118
4119 xhci_free_command(xhci, command);
4120
4121 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4122 spin_lock_irqsave(&xhci->lock, flags);
4123 ret = xhci_reserve_host_control_ep_resources(xhci);
4124 if (ret) {
4125 spin_unlock_irqrestore(&xhci->lock, flags);
4126 xhci_warn(xhci, "Not enough host resources, "
4127 "active endpoint contexts = %u\n",
4128 xhci->num_active_eps);
4129 goto disable_slot;
4130 }
4131 spin_unlock_irqrestore(&xhci->lock, flags);
4132 }
4133 /* Use GFP_NOIO, since this function can be called from
4134 * xhci_discover_or_reset_device(), which may be called as part of
4135 * mass storage driver error handling.
4136 */
4137 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4138 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4139 goto disable_slot;
4140 }
4141 vdev = xhci->devs[slot_id];
4142 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4143 trace_xhci_alloc_dev(slot_ctx);
4144
4145 udev->slot_id = slot_id;
4146
4147 xhci_debugfs_create_slot(xhci, slot_id);
4148
4149 /*
4150 * If resetting upon resume, we can't put the controller into runtime
4151 * suspend if there is a device attached.
4152 */
4153 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4154 pm_runtime_get_noresume(hcd->self.controller);
4155
4156 /* Is this a LS or FS device under a HS hub? */
4157 /* Hub or peripherial? */
4158 return 1;
4159
4160disable_slot:
4161 xhci_disable_slot(xhci, udev->slot_id);
4162 xhci_free_virt_device(xhci, udev->slot_id);
4163
4164 return 0;
4165}
4166
4167/*
4168 * Issue an Address Device command and optionally send a corresponding
4169 * SetAddress request to the device.
4170 */
4171static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4172 enum xhci_setup_dev setup)
4173{
4174 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4175 unsigned long flags;
4176 struct xhci_virt_device *virt_dev;
4177 int ret = 0;
4178 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4179 struct xhci_slot_ctx *slot_ctx;
4180 struct xhci_input_control_ctx *ctrl_ctx;
4181 u64 temp_64;
4182 struct xhci_command *command = NULL;
4183
4184 mutex_lock(&xhci->mutex);
4185
4186 if (xhci->xhc_state) { /* dying, removing or halted */
4187 ret = -ESHUTDOWN;
4188 goto out;
4189 }
4190
4191 if (!udev->slot_id) {
4192 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4193 "Bad Slot ID %d", udev->slot_id);
4194 ret = -EINVAL;
4195 goto out;
4196 }
4197
4198 virt_dev = xhci->devs[udev->slot_id];
4199
4200 if (WARN_ON(!virt_dev)) {
4201 /*
4202 * In plug/unplug torture test with an NEC controller,
4203 * a zero-dereference was observed once due to virt_dev = 0.
4204 * Print useful debug rather than crash if it is observed again!
4205 */
4206 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4207 udev->slot_id);
4208 ret = -EINVAL;
4209 goto out;
4210 }
4211 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4212 trace_xhci_setup_device_slot(slot_ctx);
4213
4214 if (setup == SETUP_CONTEXT_ONLY) {
4215 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4216 SLOT_STATE_DEFAULT) {
4217 xhci_dbg(xhci, "Slot already in default state\n");
4218 goto out;
4219 }
4220 }
4221
4222 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4223 if (!command) {
4224 ret = -ENOMEM;
4225 goto out;
4226 }
4227
4228 command->in_ctx = virt_dev->in_ctx;
4229
4230 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4231 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4232 if (!ctrl_ctx) {
4233 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4234 __func__);
4235 ret = -EINVAL;
4236 goto out;
4237 }
4238 /*
4239 * If this is the first Set Address since device plug-in or
4240 * virt_device realloaction after a resume with an xHCI power loss,
4241 * then set up the slot context.
4242 */
4243 if (!slot_ctx->dev_info)
4244 xhci_setup_addressable_virt_dev(xhci, udev);
4245 /* Otherwise, update the control endpoint ring enqueue pointer. */
4246 else
4247 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4248 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4249 ctrl_ctx->drop_flags = 0;
4250
4251 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4252 le32_to_cpu(slot_ctx->dev_info) >> 27);
4253
4254 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4255 spin_lock_irqsave(&xhci->lock, flags);
4256 trace_xhci_setup_device(virt_dev);
4257 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4258 udev->slot_id, setup);
4259 if (ret) {
4260 spin_unlock_irqrestore(&xhci->lock, flags);
4261 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4262 "FIXME: allocate a command ring segment");
4263 goto out;
4264 }
4265 xhci_ring_cmd_db(xhci);
4266 spin_unlock_irqrestore(&xhci->lock, flags);
4267
4268 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4269 wait_for_completion(command->completion);
4270
4271 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4272 * the SetAddress() "recovery interval" required by USB and aborting the
4273 * command on a timeout.
4274 */
4275 switch (command->status) {
4276 case COMP_COMMAND_ABORTED:
4277 case COMP_COMMAND_RING_STOPPED:
4278 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4279 ret = -ETIME;
4280 break;
4281 case COMP_CONTEXT_STATE_ERROR:
4282 case COMP_SLOT_NOT_ENABLED_ERROR:
4283 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4284 act, udev->slot_id);
4285 ret = -EINVAL;
4286 break;
4287 case COMP_USB_TRANSACTION_ERROR:
4288 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4289
4290 mutex_unlock(&xhci->mutex);
4291 ret = xhci_disable_slot(xhci, udev->slot_id);
4292 xhci_free_virt_device(xhci, udev->slot_id);
4293 if (!ret)
4294 xhci_alloc_dev(hcd, udev);
4295 kfree(command->completion);
4296 kfree(command);
4297 return -EPROTO;
4298 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4299 dev_warn(&udev->dev,
4300 "ERROR: Incompatible device for setup %s command\n", act);
4301 ret = -ENODEV;
4302 break;
4303 case COMP_SUCCESS:
4304 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4305 "Successful setup %s command", act);
4306 break;
4307 default:
4308 xhci_err(xhci,
4309 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4310 act, command->status);
4311 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4312 ret = -EINVAL;
4313 break;
4314 }
4315 if (ret)
4316 goto out;
4317 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4318 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4319 "Op regs DCBAA ptr = %#016llx", temp_64);
4320 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4321 "Slot ID %d dcbaa entry @%p = %#016llx",
4322 udev->slot_id,
4323 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4324 (unsigned long long)
4325 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4326 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4327 "Output Context DMA address = %#08llx",
4328 (unsigned long long)virt_dev->out_ctx->dma);
4329 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4330 le32_to_cpu(slot_ctx->dev_info) >> 27);
4331 /*
4332 * USB core uses address 1 for the roothubs, so we add one to the
4333 * address given back to us by the HC.
4334 */
4335 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4336 le32_to_cpu(slot_ctx->dev_info) >> 27);
4337 /* Zero the input context control for later use */
4338 ctrl_ctx->add_flags = 0;
4339 ctrl_ctx->drop_flags = 0;
4340 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4341 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4342
4343 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4344 "Internal device address = %d",
4345 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4346out:
4347 mutex_unlock(&xhci->mutex);
4348 if (command) {
4349 kfree(command->completion);
4350 kfree(command);
4351 }
4352 return ret;
4353}
4354
4355static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4356{
4357 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4358}
4359
4360static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4361{
4362 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4363}
4364
4365/*
4366 * Transfer the port index into real index in the HW port status
4367 * registers. Caculate offset between the port's PORTSC register
4368 * and port status base. Divide the number of per port register
4369 * to get the real index. The raw port number bases 1.
4370 */
4371int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4372{
4373 struct xhci_hub *rhub;
4374
4375 rhub = xhci_get_rhub(hcd);
4376 return rhub->ports[port1 - 1]->hw_portnum + 1;
4377}
4378
4379/*
4380 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4381 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4382 */
4383static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4384 struct usb_device *udev, u16 max_exit_latency)
4385{
4386 struct xhci_virt_device *virt_dev;
4387 struct xhci_command *command;
4388 struct xhci_input_control_ctx *ctrl_ctx;
4389 struct xhci_slot_ctx *slot_ctx;
4390 unsigned long flags;
4391 int ret;
4392
4393 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4394 if (!command)
4395 return -ENOMEM;
4396
4397 spin_lock_irqsave(&xhci->lock, flags);
4398
4399 virt_dev = xhci->devs[udev->slot_id];
4400
4401 /*
4402 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4403 * xHC was re-initialized. Exit latency will be set later after
4404 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4405 */
4406
4407 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4408 spin_unlock_irqrestore(&xhci->lock, flags);
4409 return 0;
4410 }
4411
4412 /* Attempt to issue an Evaluate Context command to change the MEL. */
4413 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4414 if (!ctrl_ctx) {
4415 spin_unlock_irqrestore(&xhci->lock, flags);
4416 xhci_free_command(xhci, command);
4417 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4418 __func__);
4419 return -ENOMEM;
4420 }
4421
4422 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4423 spin_unlock_irqrestore(&xhci->lock, flags);
4424
4425 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4426 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4427 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4428 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4429 slot_ctx->dev_state = 0;
4430
4431 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4432 "Set up evaluate context for LPM MEL change.");
4433
4434 /* Issue and wait for the evaluate context command. */
4435 ret = xhci_configure_endpoint(xhci, udev, command,
4436 true, true);
4437
4438 if (!ret) {
4439 spin_lock_irqsave(&xhci->lock, flags);
4440 virt_dev->current_mel = max_exit_latency;
4441 spin_unlock_irqrestore(&xhci->lock, flags);
4442 }
4443
4444 xhci_free_command(xhci, command);
4445
4446 return ret;
4447}
4448
4449#ifdef CONFIG_PM
4450
4451/* BESL to HIRD Encoding array for USB2 LPM */
4452static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4453 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4454
4455/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4456static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4457 struct usb_device *udev)
4458{
4459 int u2del, besl, besl_host;
4460 int besl_device = 0;
4461 u32 field;
4462
4463 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4464 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4465
4466 if (field & USB_BESL_SUPPORT) {
4467 for (besl_host = 0; besl_host < 16; besl_host++) {
4468 if (xhci_besl_encoding[besl_host] >= u2del)
4469 break;
4470 }
4471 /* Use baseline BESL value as default */
4472 if (field & USB_BESL_BASELINE_VALID)
4473 besl_device = USB_GET_BESL_BASELINE(field);
4474 else if (field & USB_BESL_DEEP_VALID)
4475 besl_device = USB_GET_BESL_DEEP(field);
4476 } else {
4477 if (u2del <= 50)
4478 besl_host = 0;
4479 else
4480 besl_host = (u2del - 51) / 75 + 1;
4481 }
4482
4483 besl = besl_host + besl_device;
4484 if (besl > 15)
4485 besl = 15;
4486
4487 return besl;
4488}
4489
4490/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4491static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4492{
4493 u32 field;
4494 int l1;
4495 int besld = 0;
4496 int hirdm = 0;
4497
4498 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4499
4500 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4501 l1 = udev->l1_params.timeout / 256;
4502
4503 /* device has preferred BESLD */
4504 if (field & USB_BESL_DEEP_VALID) {
4505 besld = USB_GET_BESL_DEEP(field);
4506 hirdm = 1;
4507 }
4508
4509 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4510}
4511
4512static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4513 struct usb_device *udev, int enable)
4514{
4515 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4516 struct xhci_port **ports;
4517 __le32 __iomem *pm_addr, *hlpm_addr;
4518 u32 pm_val, hlpm_val, field;
4519 unsigned int port_num;
4520 unsigned long flags;
4521 int hird, exit_latency;
4522 int ret;
4523
4524 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4525 return -EPERM;
4526
4527 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4528 !udev->lpm_capable)
4529 return -EPERM;
4530
4531 if (!udev->parent || udev->parent->parent ||
4532 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4533 return -EPERM;
4534
4535 if (udev->usb2_hw_lpm_capable != 1)
4536 return -EPERM;
4537
4538 spin_lock_irqsave(&xhci->lock, flags);
4539
4540 ports = xhci->usb2_rhub.ports;
4541 port_num = udev->portnum - 1;
4542 pm_addr = ports[port_num]->addr + PORTPMSC;
4543 pm_val = readl(pm_addr);
4544 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4545
4546 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4547 enable ? "enable" : "disable", port_num + 1);
4548
4549 if (enable) {
4550 /* Host supports BESL timeout instead of HIRD */
4551 if (udev->usb2_hw_lpm_besl_capable) {
4552 /* if device doesn't have a preferred BESL value use a
4553 * default one which works with mixed HIRD and BESL
4554 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4555 */
4556 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4557 if ((field & USB_BESL_SUPPORT) &&
4558 (field & USB_BESL_BASELINE_VALID))
4559 hird = USB_GET_BESL_BASELINE(field);
4560 else
4561 hird = udev->l1_params.besl;
4562
4563 exit_latency = xhci_besl_encoding[hird];
4564 spin_unlock_irqrestore(&xhci->lock, flags);
4565
4566 ret = xhci_change_max_exit_latency(xhci, udev,
4567 exit_latency);
4568 if (ret < 0)
4569 return ret;
4570 spin_lock_irqsave(&xhci->lock, flags);
4571
4572 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4573 writel(hlpm_val, hlpm_addr);
4574 /* flush write */
4575 readl(hlpm_addr);
4576 } else {
4577 hird = xhci_calculate_hird_besl(xhci, udev);
4578 }
4579
4580 pm_val &= ~PORT_HIRD_MASK;
4581 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4582 writel(pm_val, pm_addr);
4583 pm_val = readl(pm_addr);
4584 pm_val |= PORT_HLE;
4585 writel(pm_val, pm_addr);
4586 /* flush write */
4587 readl(pm_addr);
4588 } else {
4589 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4590 writel(pm_val, pm_addr);
4591 /* flush write */
4592 readl(pm_addr);
4593 if (udev->usb2_hw_lpm_besl_capable) {
4594 spin_unlock_irqrestore(&xhci->lock, flags);
4595 xhci_change_max_exit_latency(xhci, udev, 0);
4596 readl_poll_timeout(ports[port_num]->addr, pm_val,
4597 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4598 100, 10000);
4599 return 0;
4600 }
4601 }
4602
4603 spin_unlock_irqrestore(&xhci->lock, flags);
4604 return 0;
4605}
4606
4607/* check if a usb2 port supports a given extened capability protocol
4608 * only USB2 ports extended protocol capability values are cached.
4609 * Return 1 if capability is supported
4610 */
4611static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4612 unsigned capability)
4613{
4614 u32 port_offset, port_count;
4615 int i;
4616
4617 for (i = 0; i < xhci->num_ext_caps; i++) {
4618 if (xhci->ext_caps[i] & capability) {
4619 /* port offsets starts at 1 */
4620 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4621 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4622 if (port >= port_offset &&
4623 port < port_offset + port_count)
4624 return 1;
4625 }
4626 }
4627 return 0;
4628}
4629
4630static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4631{
4632 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4633 int portnum = udev->portnum - 1;
4634
4635 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4636 return 0;
4637
4638 /* we only support lpm for non-hub device connected to root hub yet */
4639 if (!udev->parent || udev->parent->parent ||
4640 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4641 return 0;
4642
4643 if (xhci->hw_lpm_support == 1 &&
4644 xhci_check_usb2_port_capability(
4645 xhci, portnum, XHCI_HLC)) {
4646 udev->usb2_hw_lpm_capable = 1;
4647 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4648 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4649 if (xhci_check_usb2_port_capability(xhci, portnum,
4650 XHCI_BLC))
4651 udev->usb2_hw_lpm_besl_capable = 1;
4652 }
4653
4654 return 0;
4655}
4656
4657/*---------------------- USB 3.0 Link PM functions ------------------------*/
4658
4659/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4660static unsigned long long xhci_service_interval_to_ns(
4661 struct usb_endpoint_descriptor *desc)
4662{
4663 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4664}
4665
4666static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4667 enum usb3_link_state state)
4668{
4669 unsigned long long sel;
4670 unsigned long long pel;
4671 unsigned int max_sel_pel;
4672 char *state_name;
4673
4674 switch (state) {
4675 case USB3_LPM_U1:
4676 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4677 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4678 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4679 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4680 state_name = "U1";
4681 break;
4682 case USB3_LPM_U2:
4683 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4684 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4685 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4686 state_name = "U2";
4687 break;
4688 default:
4689 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4690 __func__);
4691 return USB3_LPM_DISABLED;
4692 }
4693
4694 if (sel <= max_sel_pel && pel <= max_sel_pel)
4695 return USB3_LPM_DEVICE_INITIATED;
4696
4697 if (sel > max_sel_pel)
4698 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4699 "due to long SEL %llu ms\n",
4700 state_name, sel);
4701 else
4702 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4703 "due to long PEL %llu ms\n",
4704 state_name, pel);
4705 return USB3_LPM_DISABLED;
4706}
4707
4708/* The U1 timeout should be the maximum of the following values:
4709 * - For control endpoints, U1 system exit latency (SEL) * 3
4710 * - For bulk endpoints, U1 SEL * 5
4711 * - For interrupt endpoints:
4712 * - Notification EPs, U1 SEL * 3
4713 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4714 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4715 */
4716static unsigned long long xhci_calculate_intel_u1_timeout(
4717 struct usb_device *udev,
4718 struct usb_endpoint_descriptor *desc)
4719{
4720 unsigned long long timeout_ns;
4721 int ep_type;
4722 int intr_type;
4723
4724 ep_type = usb_endpoint_type(desc);
4725 switch (ep_type) {
4726 case USB_ENDPOINT_XFER_CONTROL:
4727 timeout_ns = udev->u1_params.sel * 3;
4728 break;
4729 case USB_ENDPOINT_XFER_BULK:
4730 timeout_ns = udev->u1_params.sel * 5;
4731 break;
4732 case USB_ENDPOINT_XFER_INT:
4733 intr_type = usb_endpoint_interrupt_type(desc);
4734 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4735 timeout_ns = udev->u1_params.sel * 3;
4736 break;
4737 }
4738 /* Otherwise the calculation is the same as isoc eps */
4739 fallthrough;
4740 case USB_ENDPOINT_XFER_ISOC:
4741 timeout_ns = xhci_service_interval_to_ns(desc);
4742 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4743 if (timeout_ns < udev->u1_params.sel * 2)
4744 timeout_ns = udev->u1_params.sel * 2;
4745 break;
4746 default:
4747 return 0;
4748 }
4749
4750 return timeout_ns;
4751}
4752
4753/* Returns the hub-encoded U1 timeout value. */
4754static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4755 struct usb_device *udev,
4756 struct usb_endpoint_descriptor *desc)
4757{
4758 unsigned long long timeout_ns;
4759
4760 /* Prevent U1 if service interval is shorter than U1 exit latency */
4761 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4762 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4763 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4764 return USB3_LPM_DISABLED;
4765 }
4766 }
4767
4768 if (xhci->quirks & XHCI_INTEL_HOST)
4769 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4770 else
4771 timeout_ns = udev->u1_params.sel;
4772
4773 /* The U1 timeout is encoded in 1us intervals.
4774 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4775 */
4776 if (timeout_ns == USB3_LPM_DISABLED)
4777 timeout_ns = 1;
4778 else
4779 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4780
4781 /* If the necessary timeout value is bigger than what we can set in the
4782 * USB 3.0 hub, we have to disable hub-initiated U1.
4783 */
4784 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4785 return timeout_ns;
4786 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4787 "due to long timeout %llu ms\n", timeout_ns);
4788 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4789}
4790
4791/* The U2 timeout should be the maximum of:
4792 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4793 * - largest bInterval of any active periodic endpoint (to avoid going
4794 * into lower power link states between intervals).
4795 * - the U2 Exit Latency of the device
4796 */
4797static unsigned long long xhci_calculate_intel_u2_timeout(
4798 struct usb_device *udev,
4799 struct usb_endpoint_descriptor *desc)
4800{
4801 unsigned long long timeout_ns;
4802 unsigned long long u2_del_ns;
4803
4804 timeout_ns = 10 * 1000 * 1000;
4805
4806 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4807 (xhci_service_interval_to_ns(desc) > timeout_ns))
4808 timeout_ns = xhci_service_interval_to_ns(desc);
4809
4810 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4811 if (u2_del_ns > timeout_ns)
4812 timeout_ns = u2_del_ns;
4813
4814 return timeout_ns;
4815}
4816
4817/* Returns the hub-encoded U2 timeout value. */
4818static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4819 struct usb_device *udev,
4820 struct usb_endpoint_descriptor *desc)
4821{
4822 unsigned long long timeout_ns;
4823
4824 /* Prevent U2 if service interval is shorter than U2 exit latency */
4825 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4826 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4827 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4828 return USB3_LPM_DISABLED;
4829 }
4830 }
4831
4832 if (xhci->quirks & XHCI_INTEL_HOST)
4833 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4834 else
4835 timeout_ns = udev->u2_params.sel;
4836
4837 /* The U2 timeout is encoded in 256us intervals */
4838 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4839 /* If the necessary timeout value is bigger than what we can set in the
4840 * USB 3.0 hub, we have to disable hub-initiated U2.
4841 */
4842 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4843 return timeout_ns;
4844 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4845 "due to long timeout %llu ms\n", timeout_ns);
4846 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4847}
4848
4849static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4850 struct usb_device *udev,
4851 struct usb_endpoint_descriptor *desc,
4852 enum usb3_link_state state,
4853 u16 *timeout)
4854{
4855 if (state == USB3_LPM_U1)
4856 return xhci_calculate_u1_timeout(xhci, udev, desc);
4857 else if (state == USB3_LPM_U2)
4858 return xhci_calculate_u2_timeout(xhci, udev, desc);
4859
4860 return USB3_LPM_DISABLED;
4861}
4862
4863static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4864 struct usb_device *udev,
4865 struct usb_endpoint_descriptor *desc,
4866 enum usb3_link_state state,
4867 u16 *timeout)
4868{
4869 u16 alt_timeout;
4870
4871 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4872 desc, state, timeout);
4873
4874 /* If we found we can't enable hub-initiated LPM, and
4875 * the U1 or U2 exit latency was too high to allow
4876 * device-initiated LPM as well, then we will disable LPM
4877 * for this device, so stop searching any further.
4878 */
4879 if (alt_timeout == USB3_LPM_DISABLED) {
4880 *timeout = alt_timeout;
4881 return -E2BIG;
4882 }
4883 if (alt_timeout > *timeout)
4884 *timeout = alt_timeout;
4885 return 0;
4886}
4887
4888static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4889 struct usb_device *udev,
4890 struct usb_host_interface *alt,
4891 enum usb3_link_state state,
4892 u16 *timeout)
4893{
4894 int j;
4895
4896 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4897 if (xhci_update_timeout_for_endpoint(xhci, udev,
4898 &alt->endpoint[j].desc, state, timeout))
4899 return -E2BIG;
4900 }
4901 return 0;
4902}
4903
4904static int xhci_check_intel_tier_policy(struct usb_device *udev,
4905 enum usb3_link_state state)
4906{
4907 struct usb_device *parent;
4908 unsigned int num_hubs;
4909
4910 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4911 for (parent = udev->parent, num_hubs = 0; parent->parent;
4912 parent = parent->parent)
4913 num_hubs++;
4914
4915 if (num_hubs < 2)
4916 return 0;
4917
4918 dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
4919 " below second-tier hub.\n");
4920 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4921 "to decrease power consumption.\n");
4922 return -E2BIG;
4923}
4924
4925static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4926 struct usb_device *udev,
4927 enum usb3_link_state state)
4928{
4929 if (xhci->quirks & XHCI_INTEL_HOST)
4930 return xhci_check_intel_tier_policy(udev, state);
4931 else
4932 return 0;
4933}
4934
4935/* Returns the U1 or U2 timeout that should be enabled.
4936 * If the tier check or timeout setting functions return with a non-zero exit
4937 * code, that means the timeout value has been finalized and we shouldn't look
4938 * at any more endpoints.
4939 */
4940static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4941 struct usb_device *udev, enum usb3_link_state state)
4942{
4943 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4944 struct usb_host_config *config;
4945 char *state_name;
4946 int i;
4947 u16 timeout = USB3_LPM_DISABLED;
4948
4949 if (state == USB3_LPM_U1)
4950 state_name = "U1";
4951 else if (state == USB3_LPM_U2)
4952 state_name = "U2";
4953 else {
4954 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4955 state);
4956 return timeout;
4957 }
4958
4959 /* Gather some information about the currently installed configuration
4960 * and alternate interface settings.
4961 */
4962 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4963 state, &timeout))
4964 return timeout;
4965
4966 config = udev->actconfig;
4967 if (!config)
4968 return timeout;
4969
4970 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4971 struct usb_driver *driver;
4972 struct usb_interface *intf = config->interface[i];
4973
4974 if (!intf)
4975 continue;
4976
4977 /* Check if any currently bound drivers want hub-initiated LPM
4978 * disabled.
4979 */
4980 if (intf->dev.driver) {
4981 driver = to_usb_driver(intf->dev.driver);
4982 if (driver && driver->disable_hub_initiated_lpm) {
4983 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4984 state_name, driver->name);
4985 timeout = xhci_get_timeout_no_hub_lpm(udev,
4986 state);
4987 if (timeout == USB3_LPM_DISABLED)
4988 return timeout;
4989 }
4990 }
4991
4992 /* Not sure how this could happen... */
4993 if (!intf->cur_altsetting)
4994 continue;
4995
4996 if (xhci_update_timeout_for_interface(xhci, udev,
4997 intf->cur_altsetting,
4998 state, &timeout))
4999 return timeout;
5000 }
5001 return timeout;
5002}
5003
5004static int calculate_max_exit_latency(struct usb_device *udev,
5005 enum usb3_link_state state_changed,
5006 u16 hub_encoded_timeout)
5007{
5008 unsigned long long u1_mel_us = 0;
5009 unsigned long long u2_mel_us = 0;
5010 unsigned long long mel_us = 0;
5011 bool disabling_u1;
5012 bool disabling_u2;
5013 bool enabling_u1;
5014 bool enabling_u2;
5015
5016 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5017 hub_encoded_timeout == USB3_LPM_DISABLED);
5018 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5019 hub_encoded_timeout == USB3_LPM_DISABLED);
5020
5021 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5022 hub_encoded_timeout != USB3_LPM_DISABLED);
5023 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5024 hub_encoded_timeout != USB3_LPM_DISABLED);
5025
5026 /* If U1 was already enabled and we're not disabling it,
5027 * or we're going to enable U1, account for the U1 max exit latency.
5028 */
5029 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5030 enabling_u1)
5031 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5032 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5033 enabling_u2)
5034 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5035
5036 mel_us = max(u1_mel_us, u2_mel_us);
5037
5038 /* xHCI host controller max exit latency field is only 16 bits wide. */
5039 if (mel_us > MAX_EXIT) {
5040 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5041 "is too big.\n", mel_us);
5042 return -E2BIG;
5043 }
5044 return mel_us;
5045}
5046
5047/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5048static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5049 struct usb_device *udev, enum usb3_link_state state)
5050{
5051 struct xhci_hcd *xhci;
5052 struct xhci_port *port;
5053 u16 hub_encoded_timeout;
5054 int mel;
5055 int ret;
5056
5057 xhci = hcd_to_xhci(hcd);
5058 /* The LPM timeout values are pretty host-controller specific, so don't
5059 * enable hub-initiated timeouts unless the vendor has provided
5060 * information about their timeout algorithm.
5061 */
5062 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5063 !xhci->devs[udev->slot_id])
5064 return USB3_LPM_DISABLED;
5065
5066 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5067 return USB3_LPM_DISABLED;
5068
5069 /* If connected to root port then check port can handle lpm */
5070 if (udev->parent && !udev->parent->parent) {
5071 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5072 if (port->lpm_incapable)
5073 return USB3_LPM_DISABLED;
5074 }
5075
5076 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5077 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5078 if (mel < 0) {
5079 /* Max Exit Latency is too big, disable LPM. */
5080 hub_encoded_timeout = USB3_LPM_DISABLED;
5081 mel = 0;
5082 }
5083
5084 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5085 if (ret)
5086 return ret;
5087 return hub_encoded_timeout;
5088}
5089
5090static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5091 struct usb_device *udev, enum usb3_link_state state)
5092{
5093 struct xhci_hcd *xhci;
5094 u16 mel;
5095
5096 xhci = hcd_to_xhci(hcd);
5097 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5098 !xhci->devs[udev->slot_id])
5099 return 0;
5100
5101 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5102 return xhci_change_max_exit_latency(xhci, udev, mel);
5103}
5104#else /* CONFIG_PM */
5105
5106static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5107 struct usb_device *udev, int enable)
5108{
5109 return 0;
5110}
5111
5112static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5113{
5114 return 0;
5115}
5116
5117static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5118 struct usb_device *udev, enum usb3_link_state state)
5119{
5120 return USB3_LPM_DISABLED;
5121}
5122
5123static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5124 struct usb_device *udev, enum usb3_link_state state)
5125{
5126 return 0;
5127}
5128#endif /* CONFIG_PM */
5129
5130/*-------------------------------------------------------------------------*/
5131
5132/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5133 * internal data structures for the device.
5134 */
5135int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5136 struct usb_tt *tt, gfp_t mem_flags)
5137{
5138 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5139 struct xhci_virt_device *vdev;
5140 struct xhci_command *config_cmd;
5141 struct xhci_input_control_ctx *ctrl_ctx;
5142 struct xhci_slot_ctx *slot_ctx;
5143 unsigned long flags;
5144 unsigned think_time;
5145 int ret;
5146
5147 /* Ignore root hubs */
5148 if (!hdev->parent)
5149 return 0;
5150
5151 vdev = xhci->devs[hdev->slot_id];
5152 if (!vdev) {
5153 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5154 return -EINVAL;
5155 }
5156
5157 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5158 if (!config_cmd)
5159 return -ENOMEM;
5160
5161 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5162 if (!ctrl_ctx) {
5163 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5164 __func__);
5165 xhci_free_command(xhci, config_cmd);
5166 return -ENOMEM;
5167 }
5168
5169 spin_lock_irqsave(&xhci->lock, flags);
5170 if (hdev->speed == USB_SPEED_HIGH &&
5171 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5172 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5173 xhci_free_command(xhci, config_cmd);
5174 spin_unlock_irqrestore(&xhci->lock, flags);
5175 return -ENOMEM;
5176 }
5177
5178 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5179 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5180 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5181 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5182 /*
5183 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5184 * but it may be already set to 1 when setup an xHCI virtual
5185 * device, so clear it anyway.
5186 */
5187 if (tt->multi)
5188 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5189 else if (hdev->speed == USB_SPEED_FULL)
5190 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5191
5192 if (xhci->hci_version > 0x95) {
5193 xhci_dbg(xhci, "xHCI version %x needs hub "
5194 "TT think time and number of ports\n",
5195 (unsigned int) xhci->hci_version);
5196 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5197 /* Set TT think time - convert from ns to FS bit times.
5198 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5199 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5200 *
5201 * xHCI 1.0: this field shall be 0 if the device is not a
5202 * High-spped hub.
5203 */
5204 think_time = tt->think_time;
5205 if (think_time != 0)
5206 think_time = (think_time / 666) - 1;
5207 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5208 slot_ctx->tt_info |=
5209 cpu_to_le32(TT_THINK_TIME(think_time));
5210 } else {
5211 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5212 "TT think time or number of ports\n",
5213 (unsigned int) xhci->hci_version);
5214 }
5215 slot_ctx->dev_state = 0;
5216 spin_unlock_irqrestore(&xhci->lock, flags);
5217
5218 xhci_dbg(xhci, "Set up %s for hub device.\n",
5219 (xhci->hci_version > 0x95) ?
5220 "configure endpoint" : "evaluate context");
5221
5222 /* Issue and wait for the configure endpoint or
5223 * evaluate context command.
5224 */
5225 if (xhci->hci_version > 0x95)
5226 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5227 false, false);
5228 else
5229 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5230 true, false);
5231
5232 xhci_free_command(xhci, config_cmd);
5233 return ret;
5234}
5235EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5236
5237static int xhci_get_frame(struct usb_hcd *hcd)
5238{
5239 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5240 /* EHCI mods by the periodic size. Why? */
5241 return readl(&xhci->run_regs->microframe_index) >> 3;
5242}
5243
5244static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5245{
5246 xhci->usb2_rhub.hcd = hcd;
5247 hcd->speed = HCD_USB2;
5248 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5249 /*
5250 * USB 2.0 roothub under xHCI has an integrated TT,
5251 * (rate matching hub) as opposed to having an OHCI/UHCI
5252 * companion controller.
5253 */
5254 hcd->has_tt = 1;
5255}
5256
5257static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5258{
5259 unsigned int minor_rev;
5260
5261 /*
5262 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5263 * should return 0x31 for sbrn, or that the minor revision
5264 * is a two digit BCD containig minor and sub-minor numbers.
5265 * This was later clarified in xHCI 1.2.
5266 *
5267 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5268 * minor revision set to 0x1 instead of 0x10.
5269 */
5270 if (xhci->usb3_rhub.min_rev == 0x1)
5271 minor_rev = 1;
5272 else
5273 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5274
5275 switch (minor_rev) {
5276 case 2:
5277 hcd->speed = HCD_USB32;
5278 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5279 hcd->self.root_hub->rx_lanes = 2;
5280 hcd->self.root_hub->tx_lanes = 2;
5281 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5282 break;
5283 case 1:
5284 hcd->speed = HCD_USB31;
5285 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5286 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5287 break;
5288 }
5289 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5290 minor_rev, minor_rev ? "Enhanced " : "");
5291
5292 xhci->usb3_rhub.hcd = hcd;
5293}
5294
5295int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5296{
5297 struct xhci_hcd *xhci;
5298 /*
5299 * TODO: Check with DWC3 clients for sysdev according to
5300 * quirks
5301 */
5302 struct device *dev = hcd->self.sysdev;
5303 int retval;
5304
5305 /* Accept arbitrarily long scatter-gather lists */
5306 hcd->self.sg_tablesize = ~0;
5307
5308 /* support to build packet from discontinuous buffers */
5309 hcd->self.no_sg_constraint = 1;
5310
5311 /* XHCI controllers don't stop the ep queue on short packets :| */
5312 hcd->self.no_stop_on_short = 1;
5313
5314 xhci = hcd_to_xhci(hcd);
5315
5316 if (!usb_hcd_is_primary_hcd(hcd)) {
5317 xhci_hcd_init_usb3_data(xhci, hcd);
5318 return 0;
5319 }
5320
5321 mutex_init(&xhci->mutex);
5322 xhci->main_hcd = hcd;
5323 xhci->cap_regs = hcd->regs;
5324 xhci->op_regs = hcd->regs +
5325 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5326 xhci->run_regs = hcd->regs +
5327 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5328 /* Cache read-only capability registers */
5329 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5330 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5331 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5332 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5333 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5334 if (xhci->hci_version > 0x100)
5335 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5336
5337 xhci->quirks |= quirks;
5338
5339 get_quirks(dev, xhci);
5340
5341 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5342 * success event after a short transfer. This quirk will ignore such
5343 * spurious event.
5344 */
5345 if (xhci->hci_version > 0x96)
5346 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5347
5348 /* Make sure the HC is halted. */
5349 retval = xhci_halt(xhci);
5350 if (retval)
5351 return retval;
5352
5353 xhci_zero_64b_regs(xhci);
5354
5355 xhci_dbg(xhci, "Resetting HCD\n");
5356 /* Reset the internal HC memory state and registers. */
5357 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5358 if (retval)
5359 return retval;
5360 xhci_dbg(xhci, "Reset complete\n");
5361
5362 /*
5363 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5364 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5365 * address memory pointers actually. So, this driver clears the AC64
5366 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5367 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5368 */
5369 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5370 xhci->hcc_params &= ~BIT(0);
5371
5372 /* Set dma_mask and coherent_dma_mask to 64-bits,
5373 * if xHC supports 64-bit addressing */
5374 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5375 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5376 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5377 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5378 } else {
5379 /*
5380 * This is to avoid error in cases where a 32-bit USB
5381 * controller is used on a 64-bit capable system.
5382 */
5383 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5384 if (retval)
5385 return retval;
5386 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5387 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5388 }
5389
5390 xhci_dbg(xhci, "Calling HCD init\n");
5391 /* Initialize HCD and host controller data structures. */
5392 retval = xhci_init(hcd);
5393 if (retval)
5394 return retval;
5395 xhci_dbg(xhci, "Called HCD init\n");
5396
5397 if (xhci_hcd_is_usb3(hcd))
5398 xhci_hcd_init_usb3_data(xhci, hcd);
5399 else
5400 xhci_hcd_init_usb2_data(xhci, hcd);
5401
5402 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5403 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5404
5405 return 0;
5406}
5407EXPORT_SYMBOL_GPL(xhci_gen_setup);
5408
5409static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5410 struct usb_host_endpoint *ep)
5411{
5412 struct xhci_hcd *xhci;
5413 struct usb_device *udev;
5414 unsigned int slot_id;
5415 unsigned int ep_index;
5416 unsigned long flags;
5417
5418 xhci = hcd_to_xhci(hcd);
5419
5420 spin_lock_irqsave(&xhci->lock, flags);
5421 udev = (struct usb_device *)ep->hcpriv;
5422 slot_id = udev->slot_id;
5423 ep_index = xhci_get_endpoint_index(&ep->desc);
5424
5425 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5426 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5427 spin_unlock_irqrestore(&xhci->lock, flags);
5428}
5429
5430static const struct hc_driver xhci_hc_driver = {
5431 .description = "xhci-hcd",
5432 .product_desc = "xHCI Host Controller",
5433 .hcd_priv_size = sizeof(struct xhci_hcd),
5434
5435 /*
5436 * generic hardware linkage
5437 */
5438 .irq = xhci_irq,
5439 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5440 HCD_BH,
5441
5442 /*
5443 * basic lifecycle operations
5444 */
5445 .reset = NULL, /* set in xhci_init_driver() */
5446 .start = xhci_run,
5447 .stop = xhci_stop,
5448 .shutdown = xhci_shutdown,
5449
5450 /*
5451 * managing i/o requests and associated device resources
5452 */
5453 .map_urb_for_dma = xhci_map_urb_for_dma,
5454 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5455 .urb_enqueue = xhci_urb_enqueue,
5456 .urb_dequeue = xhci_urb_dequeue,
5457 .alloc_dev = xhci_alloc_dev,
5458 .free_dev = xhci_free_dev,
5459 .alloc_streams = xhci_alloc_streams,
5460 .free_streams = xhci_free_streams,
5461 .add_endpoint = xhci_add_endpoint,
5462 .drop_endpoint = xhci_drop_endpoint,
5463 .endpoint_disable = xhci_endpoint_disable,
5464 .endpoint_reset = xhci_endpoint_reset,
5465 .check_bandwidth = xhci_check_bandwidth,
5466 .reset_bandwidth = xhci_reset_bandwidth,
5467 .address_device = xhci_address_device,
5468 .enable_device = xhci_enable_device,
5469 .update_hub_device = xhci_update_hub_device,
5470 .reset_device = xhci_discover_or_reset_device,
5471
5472 /*
5473 * scheduling support
5474 */
5475 .get_frame_number = xhci_get_frame,
5476
5477 /*
5478 * root hub support
5479 */
5480 .hub_control = xhci_hub_control,
5481 .hub_status_data = xhci_hub_status_data,
5482 .bus_suspend = xhci_bus_suspend,
5483 .bus_resume = xhci_bus_resume,
5484 .get_resuming_ports = xhci_get_resuming_ports,
5485
5486 /*
5487 * call back when device connected and addressed
5488 */
5489 .update_device = xhci_update_device,
5490 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5491 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5492 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5493 .find_raw_port_number = xhci_find_raw_port_number,
5494 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5495};
5496
5497void xhci_init_driver(struct hc_driver *drv,
5498 const struct xhci_driver_overrides *over)
5499{
5500 BUG_ON(!over);
5501
5502 /* Copy the generic table to drv then apply the overrides */
5503 *drv = xhci_hc_driver;
5504
5505 if (over) {
5506 drv->hcd_priv_size += over->extra_priv_size;
5507 if (over->reset)
5508 drv->reset = over->reset;
5509 if (over->start)
5510 drv->start = over->start;
5511 if (over->add_endpoint)
5512 drv->add_endpoint = over->add_endpoint;
5513 if (over->drop_endpoint)
5514 drv->drop_endpoint = over->drop_endpoint;
5515 if (over->check_bandwidth)
5516 drv->check_bandwidth = over->check_bandwidth;
5517 if (over->reset_bandwidth)
5518 drv->reset_bandwidth = over->reset_bandwidth;
5519 if (over->update_hub_device)
5520 drv->update_hub_device = over->update_hub_device;
5521 }
5522}
5523EXPORT_SYMBOL_GPL(xhci_init_driver);
5524
5525MODULE_DESCRIPTION(DRIVER_DESC);
5526MODULE_AUTHOR(DRIVER_AUTHOR);
5527MODULE_LICENSE("GPL");
5528
5529static int __init xhci_hcd_init(void)
5530{
5531 /*
5532 * Check the compiler generated sizes of structures that must be laid
5533 * out in specific ways for hardware access.
5534 */
5535 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5536 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5537 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5538 /* xhci_device_control has eight fields, and also
5539 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5540 */
5541 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5542 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5543 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5544 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5545 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5546 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5547 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5548
5549 if (usb_disabled())
5550 return -ENODEV;
5551
5552 xhci_debugfs_create_root();
5553 xhci_dbc_init();
5554
5555 return 0;
5556}
5557
5558/*
5559 * If an init function is provided, an exit function must also be provided
5560 * to allow module unload.
5561 */
5562static void __exit xhci_hcd_fini(void)
5563{
5564 xhci_debugfs_remove_root();
5565 xhci_dbc_exit();
5566}
5567
5568module_init(xhci_hcd_init);
5569module_exit(xhci_hcd_fini);
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29#include <linux/dmi.h>
30#include <linux/dma-mapping.h>
31
32#include "xhci.h"
33#include "xhci-trace.h"
34#include "xhci-mtk.h"
35
36#define DRIVER_AUTHOR "Sarah Sharp"
37#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
38
39#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
40
41/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42static int link_quirk;
43module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
45
46static unsigned int quirks;
47module_param(quirks, uint, S_IRUGO);
48MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
49
50/* TODO: copied from ehci-hcd.c - can this be refactored? */
51/*
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
57 *
58 * Returns negative errno, or zero on success
59 *
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
63 */
64int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
65{
66 u32 result;
67
68 do {
69 result = readl(ptr);
70 if (result == ~(u32)0) /* card removed */
71 return -ENODEV;
72 result &= mask;
73 if (result == done)
74 return 0;
75 udelay(1);
76 usec--;
77 } while (usec > 0);
78 return -ETIMEDOUT;
79}
80
81/*
82 * Disable interrupts and begin the xHCI halting process.
83 */
84void xhci_quiesce(struct xhci_hcd *xhci)
85{
86 u32 halted;
87 u32 cmd;
88 u32 mask;
89
90 mask = ~(XHCI_IRQS);
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
92 if (!halted)
93 mask &= ~CMD_RUN;
94
95 cmd = readl(&xhci->op_regs->command);
96 cmd &= mask;
97 writel(cmd, &xhci->op_regs->command);
98}
99
100/*
101 * Force HC into halt state.
102 *
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
107 */
108int xhci_halt(struct xhci_hcd *xhci)
109{
110 int ret;
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 xhci_quiesce(xhci);
113
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
116 if (!ret) {
117 xhci->xhc_state |= XHCI_STATE_HALTED;
118 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
119 } else
120 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
121 XHCI_MAX_HALT_USEC);
122 return ret;
123}
124
125/*
126 * Set the run bit and wait for the host to be running.
127 */
128static int xhci_start(struct xhci_hcd *xhci)
129{
130 u32 temp;
131 int ret;
132
133 temp = readl(&xhci->op_regs->command);
134 temp |= (CMD_RUN);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
136 temp);
137 writel(temp, &xhci->op_regs->command);
138
139 /*
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 * running.
142 */
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
148 XHCI_MAX_HALT_USEC);
149 if (!ret)
150 /* clear state flags. Including dying, halted or removing */
151 xhci->xhc_state = 0;
152
153 return ret;
154}
155
156/*
157 * Reset a halted HC.
158 *
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
162 */
163int xhci_reset(struct xhci_hcd *xhci)
164{
165 u32 command;
166 u32 state;
167 int ret, i;
168
169 state = readl(&xhci->op_regs->status);
170 if ((state & STS_HALT) == 0) {
171 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
172 return 0;
173 }
174
175 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
176 command = readl(&xhci->op_regs->command);
177 command |= CMD_RESET;
178 writel(command, &xhci->op_regs->command);
179
180 /* Existing Intel xHCI controllers require a delay of 1 mS,
181 * after setting the CMD_RESET bit, and before accessing any
182 * HC registers. This allows the HC to complete the
183 * reset operation and be ready for HC register access.
184 * Without this delay, the subsequent HC register access,
185 * may result in a system hang very rarely.
186 */
187 if (xhci->quirks & XHCI_INTEL_HOST)
188 udelay(1000);
189
190 ret = xhci_handshake(&xhci->op_regs->command,
191 CMD_RESET, 0, 10 * 1000 * 1000);
192 if (ret)
193 return ret;
194
195 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
196 "Wait for controller to be ready for doorbell rings");
197 /*
198 * xHCI cannot write to any doorbells or operational registers other
199 * than status until the "Controller Not Ready" flag is cleared.
200 */
201 ret = xhci_handshake(&xhci->op_regs->status,
202 STS_CNR, 0, 10 * 1000 * 1000);
203
204 for (i = 0; i < 2; ++i) {
205 xhci->bus_state[i].port_c_suspend = 0;
206 xhci->bus_state[i].suspended_ports = 0;
207 xhci->bus_state[i].resuming_ports = 0;
208 }
209
210 return ret;
211}
212
213#ifdef CONFIG_PCI
214static int xhci_free_msi(struct xhci_hcd *xhci)
215{
216 int i;
217
218 if (!xhci->msix_entries)
219 return -EINVAL;
220
221 for (i = 0; i < xhci->msix_count; i++)
222 if (xhci->msix_entries[i].vector)
223 free_irq(xhci->msix_entries[i].vector,
224 xhci_to_hcd(xhci));
225 return 0;
226}
227
228/*
229 * Set up MSI
230 */
231static int xhci_setup_msi(struct xhci_hcd *xhci)
232{
233 int ret;
234 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
235
236 ret = pci_enable_msi(pdev);
237 if (ret) {
238 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
239 "failed to allocate MSI entry");
240 return ret;
241 }
242
243 ret = request_irq(pdev->irq, xhci_msi_irq,
244 0, "xhci_hcd", xhci_to_hcd(xhci));
245 if (ret) {
246 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
247 "disable MSI interrupt");
248 pci_disable_msi(pdev);
249 }
250
251 return ret;
252}
253
254/*
255 * Free IRQs
256 * free all IRQs request
257 */
258static void xhci_free_irq(struct xhci_hcd *xhci)
259{
260 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
261 int ret;
262
263 /* return if using legacy interrupt */
264 if (xhci_to_hcd(xhci)->irq > 0)
265 return;
266
267 ret = xhci_free_msi(xhci);
268 if (!ret)
269 return;
270 if (pdev->irq > 0)
271 free_irq(pdev->irq, xhci_to_hcd(xhci));
272
273 return;
274}
275
276/*
277 * Set up MSI-X
278 */
279static int xhci_setup_msix(struct xhci_hcd *xhci)
280{
281 int i, ret = 0;
282 struct usb_hcd *hcd = xhci_to_hcd(xhci);
283 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
284
285 /*
286 * calculate number of msi-x vectors supported.
287 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
288 * with max number of interrupters based on the xhci HCSPARAMS1.
289 * - num_online_cpus: maximum msi-x vectors per CPUs core.
290 * Add additional 1 vector to ensure always available interrupt.
291 */
292 xhci->msix_count = min(num_online_cpus() + 1,
293 HCS_MAX_INTRS(xhci->hcs_params1));
294
295 xhci->msix_entries =
296 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
297 GFP_KERNEL);
298 if (!xhci->msix_entries) {
299 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
300 return -ENOMEM;
301 }
302
303 for (i = 0; i < xhci->msix_count; i++) {
304 xhci->msix_entries[i].entry = i;
305 xhci->msix_entries[i].vector = 0;
306 }
307
308 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 if (ret) {
310 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
311 "Failed to enable MSI-X");
312 goto free_entries;
313 }
314
315 for (i = 0; i < xhci->msix_count; i++) {
316 ret = request_irq(xhci->msix_entries[i].vector,
317 xhci_msi_irq,
318 0, "xhci_hcd", xhci_to_hcd(xhci));
319 if (ret)
320 goto disable_msix;
321 }
322
323 hcd->msix_enabled = 1;
324 return ret;
325
326disable_msix:
327 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 xhci_free_irq(xhci);
329 pci_disable_msix(pdev);
330free_entries:
331 kfree(xhci->msix_entries);
332 xhci->msix_entries = NULL;
333 return ret;
334}
335
336/* Free any IRQs and disable MSI-X */
337static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338{
339 struct usb_hcd *hcd = xhci_to_hcd(xhci);
340 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341
342 if (xhci->quirks & XHCI_PLAT)
343 return;
344
345 xhci_free_irq(xhci);
346
347 if (xhci->msix_entries) {
348 pci_disable_msix(pdev);
349 kfree(xhci->msix_entries);
350 xhci->msix_entries = NULL;
351 } else {
352 pci_disable_msi(pdev);
353 }
354
355 hcd->msix_enabled = 0;
356 return;
357}
358
359static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
360{
361 int i;
362
363 if (xhci->msix_entries) {
364 for (i = 0; i < xhci->msix_count; i++)
365 synchronize_irq(xhci->msix_entries[i].vector);
366 }
367}
368
369static int xhci_try_enable_msi(struct usb_hcd *hcd)
370{
371 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
372 struct pci_dev *pdev;
373 int ret;
374
375 /* The xhci platform device has set up IRQs through usb_add_hcd. */
376 if (xhci->quirks & XHCI_PLAT)
377 return 0;
378
379 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 /*
381 * Some Fresco Logic host controllers advertise MSI, but fail to
382 * generate interrupts. Don't even try to enable MSI.
383 */
384 if (xhci->quirks & XHCI_BROKEN_MSI)
385 goto legacy_irq;
386
387 /* unregister the legacy interrupt */
388 if (hcd->irq)
389 free_irq(hcd->irq, hcd);
390 hcd->irq = 0;
391
392 ret = xhci_setup_msix(xhci);
393 if (ret)
394 /* fall back to msi*/
395 ret = xhci_setup_msi(xhci);
396
397 if (!ret)
398 /* hcd->irq is 0, we have MSI */
399 return 0;
400
401 if (!pdev->irq) {
402 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
403 return -EINVAL;
404 }
405
406 legacy_irq:
407 if (!strlen(hcd->irq_descr))
408 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
409 hcd->driver->description, hcd->self.busnum);
410
411 /* fall back to legacy interrupt*/
412 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
413 hcd->irq_descr, hcd);
414 if (ret) {
415 xhci_err(xhci, "request interrupt %d failed\n",
416 pdev->irq);
417 return ret;
418 }
419 hcd->irq = pdev->irq;
420 return 0;
421}
422
423#else
424
425static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
426{
427 return 0;
428}
429
430static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
431{
432}
433
434static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
435{
436}
437
438#endif
439
440static void compliance_mode_recovery(unsigned long arg)
441{
442 struct xhci_hcd *xhci;
443 struct usb_hcd *hcd;
444 u32 temp;
445 int i;
446
447 xhci = (struct xhci_hcd *)arg;
448
449 for (i = 0; i < xhci->num_usb3_ports; i++) {
450 temp = readl(xhci->usb3_ports[i]);
451 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 /*
453 * Compliance Mode Detected. Letting USB Core
454 * handle the Warm Reset
455 */
456 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
457 "Compliance mode detected->port %d",
458 i + 1);
459 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
460 "Attempting compliance mode recovery");
461 hcd = xhci->shared_hcd;
462
463 if (hcd->state == HC_STATE_SUSPENDED)
464 usb_hcd_resume_root_hub(hcd);
465
466 usb_hcd_poll_rh_status(hcd);
467 }
468 }
469
470 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
471 mod_timer(&xhci->comp_mode_recovery_timer,
472 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
473}
474
475/*
476 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
477 * that causes ports behind that hardware to enter compliance mode sometimes.
478 * The quirk creates a timer that polls every 2 seconds the link state of
479 * each host controller's port and recovers it by issuing a Warm reset
480 * if Compliance mode is detected, otherwise the port will become "dead" (no
481 * device connections or disconnections will be detected anymore). Becasue no
482 * status event is generated when entering compliance mode (per xhci spec),
483 * this quirk is needed on systems that have the failing hardware installed.
484 */
485static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486{
487 xhci->port_status_u0 = 0;
488 setup_timer(&xhci->comp_mode_recovery_timer,
489 compliance_mode_recovery, (unsigned long)xhci);
490 xhci->comp_mode_recovery_timer.expires = jiffies +
491 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492
493 set_timer_slack(&xhci->comp_mode_recovery_timer,
494 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
495 add_timer(&xhci->comp_mode_recovery_timer);
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Compliance mode recovery timer initialized");
498}
499
500/*
501 * This function identifies the systems that have installed the SN65LVPE502CP
502 * USB3.0 re-driver and that need the Compliance Mode Quirk.
503 * Systems:
504 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
505 */
506static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
507{
508 const char *dmi_product_name, *dmi_sys_vendor;
509
510 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
511 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
512 if (!dmi_product_name || !dmi_sys_vendor)
513 return false;
514
515 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
516 return false;
517
518 if (strstr(dmi_product_name, "Z420") ||
519 strstr(dmi_product_name, "Z620") ||
520 strstr(dmi_product_name, "Z820") ||
521 strstr(dmi_product_name, "Z1 Workstation"))
522 return true;
523
524 return false;
525}
526
527static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
528{
529 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
530}
531
532
533/*
534 * Initialize memory for HCD and xHC (one-time init).
535 *
536 * Program the PAGESIZE register, initialize the device context array, create
537 * device contexts (?), set up a command ring segment (or two?), create event
538 * ring (one for now).
539 */
540int xhci_init(struct usb_hcd *hcd)
541{
542 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
543 int retval = 0;
544
545 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
546 spin_lock_init(&xhci->lock);
547 if (xhci->hci_version == 0x95 && link_quirk) {
548 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
549 "QUIRK: Not clearing Link TRB chain bits.");
550 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
551 } else {
552 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
553 "xHCI doesn't need link TRB QUIRK");
554 }
555 retval = xhci_mem_init(xhci, GFP_KERNEL);
556 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
557
558 /* Initializing Compliance Mode Recovery Data If Needed */
559 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
560 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
561 compliance_mode_recovery_timer_init(xhci);
562 }
563
564 return retval;
565}
566
567/*-------------------------------------------------------------------------*/
568
569
570static int xhci_run_finished(struct xhci_hcd *xhci)
571{
572 if (xhci_start(xhci)) {
573 xhci_halt(xhci);
574 return -ENODEV;
575 }
576 xhci->shared_hcd->state = HC_STATE_RUNNING;
577 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
578
579 if (xhci->quirks & XHCI_NEC_HOST)
580 xhci_ring_cmd_db(xhci);
581
582 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
583 "Finished xhci_run for USB3 roothub");
584 return 0;
585}
586
587/*
588 * Start the HC after it was halted.
589 *
590 * This function is called by the USB core when the HC driver is added.
591 * Its opposite is xhci_stop().
592 *
593 * xhci_init() must be called once before this function can be called.
594 * Reset the HC, enable device slot contexts, program DCBAAP, and
595 * set command ring pointer and event ring pointer.
596 *
597 * Setup MSI-X vectors and enable interrupts.
598 */
599int xhci_run(struct usb_hcd *hcd)
600{
601 u32 temp;
602 u64 temp_64;
603 int ret;
604 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605
606 /* Start the xHCI host controller running only after the USB 2.0 roothub
607 * is setup.
608 */
609
610 hcd->uses_new_polling = 1;
611 if (!usb_hcd_is_primary_hcd(hcd))
612 return xhci_run_finished(xhci);
613
614 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
615
616 ret = xhci_try_enable_msi(hcd);
617 if (ret)
618 return ret;
619
620 xhci_dbg(xhci, "Command ring memory map follows:\n");
621 xhci_debug_ring(xhci, xhci->cmd_ring);
622 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
623 xhci_dbg_cmd_ptrs(xhci);
624
625 xhci_dbg(xhci, "ERST memory map follows:\n");
626 xhci_dbg_erst(xhci, &xhci->erst);
627 xhci_dbg(xhci, "Event ring:\n");
628 xhci_debug_ring(xhci, xhci->event_ring);
629 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
630 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
631 temp_64 &= ~ERST_PTR_MASK;
632 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
633 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
634
635 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
636 "// Set the interrupt modulation register");
637 temp = readl(&xhci->ir_set->irq_control);
638 temp &= ~ER_IRQ_INTERVAL_MASK;
639 /*
640 * the increment interval is 8 times as much as that defined
641 * in xHCI spec on MTK's controller
642 */
643 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
644 writel(temp, &xhci->ir_set->irq_control);
645
646 /* Set the HCD state before we enable the irqs */
647 temp = readl(&xhci->op_regs->command);
648 temp |= (CMD_EIE);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
650 "// Enable interrupts, cmd = 0x%x.", temp);
651 writel(temp, &xhci->op_regs->command);
652
653 temp = readl(&xhci->ir_set->irq_pending);
654 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
655 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
656 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
657 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
658 xhci_print_ir_set(xhci, 0);
659
660 if (xhci->quirks & XHCI_NEC_HOST) {
661 struct xhci_command *command;
662 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
663 if (!command)
664 return -ENOMEM;
665 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
666 TRB_TYPE(TRB_NEC_GET_FW));
667 }
668 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
669 "Finished xhci_run for USB2 roothub");
670 return 0;
671}
672EXPORT_SYMBOL_GPL(xhci_run);
673
674/*
675 * Stop xHCI driver.
676 *
677 * This function is called by the USB core when the HC driver is removed.
678 * Its opposite is xhci_run().
679 *
680 * Disable device contexts, disable IRQs, and quiesce the HC.
681 * Reset the HC, finish any completed transactions, and cleanup memory.
682 */
683void xhci_stop(struct usb_hcd *hcd)
684{
685 u32 temp;
686 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
687
688 if (xhci->xhc_state & XHCI_STATE_HALTED)
689 return;
690
691 mutex_lock(&xhci->mutex);
692 spin_lock_irq(&xhci->lock);
693 xhci->xhc_state |= XHCI_STATE_HALTED;
694 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
695
696 /* Make sure the xHC is halted for a USB3 roothub
697 * (xhci_stop() could be called as part of failed init).
698 */
699 xhci_halt(xhci);
700 xhci_reset(xhci);
701 spin_unlock_irq(&xhci->lock);
702
703 xhci_cleanup_msix(xhci);
704
705 /* Deleting Compliance Mode Recovery Timer */
706 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
707 (!(xhci_all_ports_seen_u0(xhci)))) {
708 del_timer_sync(&xhci->comp_mode_recovery_timer);
709 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
710 "%s: compliance mode recovery timer deleted",
711 __func__);
712 }
713
714 if (xhci->quirks & XHCI_AMD_PLL_FIX)
715 usb_amd_dev_put();
716
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
718 "// Disabling event ring interrupts");
719 temp = readl(&xhci->op_regs->status);
720 writel(temp & ~STS_EINT, &xhci->op_regs->status);
721 temp = readl(&xhci->ir_set->irq_pending);
722 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
723 xhci_print_ir_set(xhci, 0);
724
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
726 xhci_mem_cleanup(xhci);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
728 "xhci_stop completed - status = %x",
729 readl(&xhci->op_regs->status));
730 mutex_unlock(&xhci->mutex);
731}
732
733/*
734 * Shutdown HC (not bus-specific)
735 *
736 * This is called when the machine is rebooting or halting. We assume that the
737 * machine will be powered off, and the HC's internal state will be reset.
738 * Don't bother to free memory.
739 *
740 * This will only ever be called with the main usb_hcd (the USB3 roothub).
741 */
742void xhci_shutdown(struct usb_hcd *hcd)
743{
744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
745
746 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
747 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
748
749 spin_lock_irq(&xhci->lock);
750 xhci_halt(xhci);
751 /* Workaround for spurious wakeups at shutdown with HSW */
752 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
753 xhci_reset(xhci);
754 spin_unlock_irq(&xhci->lock);
755
756 xhci_cleanup_msix(xhci);
757
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_shutdown completed - status = %x",
760 readl(&xhci->op_regs->status));
761
762 /* Yet another workaround for spurious wakeups at shutdown with HSW */
763 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
764 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
765}
766
767#ifdef CONFIG_PM
768static void xhci_save_registers(struct xhci_hcd *xhci)
769{
770 xhci->s3.command = readl(&xhci->op_regs->command);
771 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
772 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
773 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
774 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
775 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
776 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
777 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
778 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
779}
780
781static void xhci_restore_registers(struct xhci_hcd *xhci)
782{
783 writel(xhci->s3.command, &xhci->op_regs->command);
784 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
785 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
786 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
787 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
788 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
789 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
790 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
791 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
792}
793
794static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
795{
796 u64 val_64;
797
798 /* step 2: initialize command ring buffer */
799 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
800 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
801 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
802 xhci->cmd_ring->dequeue) &
803 (u64) ~CMD_RING_RSVD_BITS) |
804 xhci->cmd_ring->cycle_state;
805 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
806 "// Setting command ring address to 0x%llx",
807 (long unsigned long) val_64);
808 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
809}
810
811/*
812 * The whole command ring must be cleared to zero when we suspend the host.
813 *
814 * The host doesn't save the command ring pointer in the suspend well, so we
815 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
816 * aligned, because of the reserved bits in the command ring dequeue pointer
817 * register. Therefore, we can't just set the dequeue pointer back in the
818 * middle of the ring (TRBs are 16-byte aligned).
819 */
820static void xhci_clear_command_ring(struct xhci_hcd *xhci)
821{
822 struct xhci_ring *ring;
823 struct xhci_segment *seg;
824
825 ring = xhci->cmd_ring;
826 seg = ring->deq_seg;
827 do {
828 memset(seg->trbs, 0,
829 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
830 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
831 cpu_to_le32(~TRB_CYCLE);
832 seg = seg->next;
833 } while (seg != ring->deq_seg);
834
835 /* Reset the software enqueue and dequeue pointers */
836 ring->deq_seg = ring->first_seg;
837 ring->dequeue = ring->first_seg->trbs;
838 ring->enq_seg = ring->deq_seg;
839 ring->enqueue = ring->dequeue;
840
841 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
842 /*
843 * Ring is now zeroed, so the HW should look for change of ownership
844 * when the cycle bit is set to 1.
845 */
846 ring->cycle_state = 1;
847
848 /*
849 * Reset the hardware dequeue pointer.
850 * Yes, this will need to be re-written after resume, but we're paranoid
851 * and want to make sure the hardware doesn't access bogus memory
852 * because, say, the BIOS or an SMI started the host without changing
853 * the command ring pointers.
854 */
855 xhci_set_cmd_ring_deq(xhci);
856}
857
858static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
859{
860 int port_index;
861 __le32 __iomem **port_array;
862 unsigned long flags;
863 u32 t1, t2;
864
865 spin_lock_irqsave(&xhci->lock, flags);
866
867 /* disble usb3 ports Wake bits*/
868 port_index = xhci->num_usb3_ports;
869 port_array = xhci->usb3_ports;
870 while (port_index--) {
871 t1 = readl(port_array[port_index]);
872 t1 = xhci_port_state_to_neutral(t1);
873 t2 = t1 & ~PORT_WAKE_BITS;
874 if (t1 != t2)
875 writel(t2, port_array[port_index]);
876 }
877
878 /* disble usb2 ports Wake bits*/
879 port_index = xhci->num_usb2_ports;
880 port_array = xhci->usb2_ports;
881 while (port_index--) {
882 t1 = readl(port_array[port_index]);
883 t1 = xhci_port_state_to_neutral(t1);
884 t2 = t1 & ~PORT_WAKE_BITS;
885 if (t1 != t2)
886 writel(t2, port_array[port_index]);
887 }
888
889 spin_unlock_irqrestore(&xhci->lock, flags);
890}
891
892/*
893 * Stop HC (not bus-specific)
894 *
895 * This is called when the machine transition into S3/S4 mode.
896 *
897 */
898int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
899{
900 int rc = 0;
901 unsigned int delay = XHCI_MAX_HALT_USEC;
902 struct usb_hcd *hcd = xhci_to_hcd(xhci);
903 u32 command;
904
905 if (!hcd->state)
906 return 0;
907
908 if (hcd->state != HC_STATE_SUSPENDED ||
909 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
910 return -EINVAL;
911
912 /* Clear root port wake on bits if wakeup not allowed. */
913 if (!do_wakeup)
914 xhci_disable_port_wake_on_bits(xhci);
915
916 /* Don't poll the roothubs on bus suspend. */
917 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
918 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
919 del_timer_sync(&hcd->rh_timer);
920 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
921 del_timer_sync(&xhci->shared_hcd->rh_timer);
922
923 spin_lock_irq(&xhci->lock);
924 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
925 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
926 /* step 1: stop endpoint */
927 /* skipped assuming that port suspend has done */
928
929 /* step 2: clear Run/Stop bit */
930 command = readl(&xhci->op_regs->command);
931 command &= ~CMD_RUN;
932 writel(command, &xhci->op_regs->command);
933
934 /* Some chips from Fresco Logic need an extraordinary delay */
935 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
936
937 if (xhci_handshake(&xhci->op_regs->status,
938 STS_HALT, STS_HALT, delay)) {
939 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
940 spin_unlock_irq(&xhci->lock);
941 return -ETIMEDOUT;
942 }
943 xhci_clear_command_ring(xhci);
944
945 /* step 3: save registers */
946 xhci_save_registers(xhci);
947
948 /* step 4: set CSS flag */
949 command = readl(&xhci->op_regs->command);
950 command |= CMD_CSS;
951 writel(command, &xhci->op_regs->command);
952 if (xhci_handshake(&xhci->op_regs->status,
953 STS_SAVE, 0, 10 * 1000)) {
954 xhci_warn(xhci, "WARN: xHC save state timeout\n");
955 spin_unlock_irq(&xhci->lock);
956 return -ETIMEDOUT;
957 }
958 spin_unlock_irq(&xhci->lock);
959
960 /*
961 * Deleting Compliance Mode Recovery Timer because the xHCI Host
962 * is about to be suspended.
963 */
964 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
965 (!(xhci_all_ports_seen_u0(xhci)))) {
966 del_timer_sync(&xhci->comp_mode_recovery_timer);
967 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
968 "%s: compliance mode recovery timer deleted",
969 __func__);
970 }
971
972 /* step 5: remove core well power */
973 /* synchronize irq when using MSI-X */
974 xhci_msix_sync_irqs(xhci);
975
976 return rc;
977}
978EXPORT_SYMBOL_GPL(xhci_suspend);
979
980/*
981 * start xHC (not bus-specific)
982 *
983 * This is called when the machine transition from S3/S4 mode.
984 *
985 */
986int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
987{
988 u32 command, temp = 0, status;
989 struct usb_hcd *hcd = xhci_to_hcd(xhci);
990 struct usb_hcd *secondary_hcd;
991 int retval = 0;
992 bool comp_timer_running = false;
993
994 if (!hcd->state)
995 return 0;
996
997 /* Wait a bit if either of the roothubs need to settle from the
998 * transition into bus suspend.
999 */
1000 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1001 time_before(jiffies,
1002 xhci->bus_state[1].next_statechange))
1003 msleep(100);
1004
1005 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1006 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1007
1008 spin_lock_irq(&xhci->lock);
1009 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1010 hibernated = true;
1011
1012 if (!hibernated) {
1013 /* step 1: restore register */
1014 xhci_restore_registers(xhci);
1015 /* step 2: initialize command ring buffer */
1016 xhci_set_cmd_ring_deq(xhci);
1017 /* step 3: restore state and start state*/
1018 /* step 3: set CRS flag */
1019 command = readl(&xhci->op_regs->command);
1020 command |= CMD_CRS;
1021 writel(command, &xhci->op_regs->command);
1022 if (xhci_handshake(&xhci->op_regs->status,
1023 STS_RESTORE, 0, 10 * 1000)) {
1024 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1025 spin_unlock_irq(&xhci->lock);
1026 return -ETIMEDOUT;
1027 }
1028 temp = readl(&xhci->op_regs->status);
1029 }
1030
1031 /* If restore operation fails, re-initialize the HC during resume */
1032 if ((temp & STS_SRE) || hibernated) {
1033
1034 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1035 !(xhci_all_ports_seen_u0(xhci))) {
1036 del_timer_sync(&xhci->comp_mode_recovery_timer);
1037 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1038 "Compliance Mode Recovery Timer deleted!");
1039 }
1040
1041 /* Let the USB core know _both_ roothubs lost power. */
1042 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1043 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1044
1045 xhci_dbg(xhci, "Stop HCD\n");
1046 xhci_halt(xhci);
1047 xhci_reset(xhci);
1048 spin_unlock_irq(&xhci->lock);
1049 xhci_cleanup_msix(xhci);
1050
1051 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1052 temp = readl(&xhci->op_regs->status);
1053 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1054 temp = readl(&xhci->ir_set->irq_pending);
1055 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1056 xhci_print_ir_set(xhci, 0);
1057
1058 xhci_dbg(xhci, "cleaning up memory\n");
1059 xhci_mem_cleanup(xhci);
1060 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1061 readl(&xhci->op_regs->status));
1062
1063 /* USB core calls the PCI reinit and start functions twice:
1064 * first with the primary HCD, and then with the secondary HCD.
1065 * If we don't do the same, the host will never be started.
1066 */
1067 if (!usb_hcd_is_primary_hcd(hcd))
1068 secondary_hcd = hcd;
1069 else
1070 secondary_hcd = xhci->shared_hcd;
1071
1072 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1073 retval = xhci_init(hcd->primary_hcd);
1074 if (retval)
1075 return retval;
1076 comp_timer_running = true;
1077
1078 xhci_dbg(xhci, "Start the primary HCD\n");
1079 retval = xhci_run(hcd->primary_hcd);
1080 if (!retval) {
1081 xhci_dbg(xhci, "Start the secondary HCD\n");
1082 retval = xhci_run(secondary_hcd);
1083 }
1084 hcd->state = HC_STATE_SUSPENDED;
1085 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1086 goto done;
1087 }
1088
1089 /* step 4: set Run/Stop bit */
1090 command = readl(&xhci->op_regs->command);
1091 command |= CMD_RUN;
1092 writel(command, &xhci->op_regs->command);
1093 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1094 0, 250 * 1000);
1095
1096 /* step 5: walk topology and initialize portsc,
1097 * portpmsc and portli
1098 */
1099 /* this is done in bus_resume */
1100
1101 /* step 6: restart each of the previously
1102 * Running endpoints by ringing their doorbells
1103 */
1104
1105 spin_unlock_irq(&xhci->lock);
1106
1107 done:
1108 if (retval == 0) {
1109 /* Resume root hubs only when have pending events. */
1110 status = readl(&xhci->op_regs->status);
1111 if (status & STS_EINT) {
1112 usb_hcd_resume_root_hub(xhci->shared_hcd);
1113 usb_hcd_resume_root_hub(hcd);
1114 }
1115 }
1116
1117 /*
1118 * If system is subject to the Quirk, Compliance Mode Timer needs to
1119 * be re-initialized Always after a system resume. Ports are subject
1120 * to suffer the Compliance Mode issue again. It doesn't matter if
1121 * ports have entered previously to U0 before system's suspension.
1122 */
1123 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1124 compliance_mode_recovery_timer_init(xhci);
1125
1126 /* Re-enable port polling. */
1127 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1128 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1129 usb_hcd_poll_rh_status(xhci->shared_hcd);
1130 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1131 usb_hcd_poll_rh_status(hcd);
1132
1133 return retval;
1134}
1135EXPORT_SYMBOL_GPL(xhci_resume);
1136#endif /* CONFIG_PM */
1137
1138/*-------------------------------------------------------------------------*/
1139
1140/**
1141 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1142 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1143 * value to right shift 1 for the bitmask.
1144 *
1145 * Index = (epnum * 2) + direction - 1,
1146 * where direction = 0 for OUT, 1 for IN.
1147 * For control endpoints, the IN index is used (OUT index is unused), so
1148 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1149 */
1150unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1151{
1152 unsigned int index;
1153 if (usb_endpoint_xfer_control(desc))
1154 index = (unsigned int) (usb_endpoint_num(desc)*2);
1155 else
1156 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1157 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1158 return index;
1159}
1160
1161/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1162 * address from the XHCI endpoint index.
1163 */
1164unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1165{
1166 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1167 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1168 return direction | number;
1169}
1170
1171/* Find the flag for this endpoint (for use in the control context). Use the
1172 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1173 * bit 1, etc.
1174 */
1175unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1176{
1177 return 1 << (xhci_get_endpoint_index(desc) + 1);
1178}
1179
1180/* Find the flag for this endpoint (for use in the control context). Use the
1181 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1182 * bit 1, etc.
1183 */
1184unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1185{
1186 return 1 << (ep_index + 1);
1187}
1188
1189/* Compute the last valid endpoint context index. Basically, this is the
1190 * endpoint index plus one. For slot contexts with more than valid endpoint,
1191 * we find the most significant bit set in the added contexts flags.
1192 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1193 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1194 */
1195unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1196{
1197 return fls(added_ctxs) - 1;
1198}
1199
1200/* Returns 1 if the arguments are OK;
1201 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1202 */
1203static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1204 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1205 const char *func) {
1206 struct xhci_hcd *xhci;
1207 struct xhci_virt_device *virt_dev;
1208
1209 if (!hcd || (check_ep && !ep) || !udev) {
1210 pr_debug("xHCI %s called with invalid args\n", func);
1211 return -EINVAL;
1212 }
1213 if (!udev->parent) {
1214 pr_debug("xHCI %s called for root hub\n", func);
1215 return 0;
1216 }
1217
1218 xhci = hcd_to_xhci(hcd);
1219 if (check_virt_dev) {
1220 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1221 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1222 func);
1223 return -EINVAL;
1224 }
1225
1226 virt_dev = xhci->devs[udev->slot_id];
1227 if (virt_dev->udev != udev) {
1228 xhci_dbg(xhci, "xHCI %s called with udev and "
1229 "virt_dev does not match\n", func);
1230 return -EINVAL;
1231 }
1232 }
1233
1234 if (xhci->xhc_state & XHCI_STATE_HALTED)
1235 return -ENODEV;
1236
1237 return 1;
1238}
1239
1240static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1241 struct usb_device *udev, struct xhci_command *command,
1242 bool ctx_change, bool must_succeed);
1243
1244/*
1245 * Full speed devices may have a max packet size greater than 8 bytes, but the
1246 * USB core doesn't know that until it reads the first 8 bytes of the
1247 * descriptor. If the usb_device's max packet size changes after that point,
1248 * we need to issue an evaluate context command and wait on it.
1249 */
1250static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1251 unsigned int ep_index, struct urb *urb)
1252{
1253 struct xhci_container_ctx *out_ctx;
1254 struct xhci_input_control_ctx *ctrl_ctx;
1255 struct xhci_ep_ctx *ep_ctx;
1256 struct xhci_command *command;
1257 int max_packet_size;
1258 int hw_max_packet_size;
1259 int ret = 0;
1260
1261 out_ctx = xhci->devs[slot_id]->out_ctx;
1262 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1263 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1264 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1265 if (hw_max_packet_size != max_packet_size) {
1266 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1267 "Max Packet Size for ep 0 changed.");
1268 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1269 "Max packet size in usb_device = %d",
1270 max_packet_size);
1271 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1272 "Max packet size in xHCI HW = %d",
1273 hw_max_packet_size);
1274 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1275 "Issuing evaluate context command.");
1276
1277 /* Set up the input context flags for the command */
1278 /* FIXME: This won't work if a non-default control endpoint
1279 * changes max packet sizes.
1280 */
1281
1282 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1283 if (!command)
1284 return -ENOMEM;
1285
1286 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1287 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1288 if (!ctrl_ctx) {
1289 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1290 __func__);
1291 ret = -ENOMEM;
1292 goto command_cleanup;
1293 }
1294 /* Set up the modified control endpoint 0 */
1295 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1296 xhci->devs[slot_id]->out_ctx, ep_index);
1297
1298 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1299 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1300 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1301
1302 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1303 ctrl_ctx->drop_flags = 0;
1304
1305 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1306 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1307 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1308 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1309
1310 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1311 true, false);
1312
1313 /* Clean up the input context for later use by bandwidth
1314 * functions.
1315 */
1316 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1317command_cleanup:
1318 kfree(command->completion);
1319 kfree(command);
1320 }
1321 return ret;
1322}
1323
1324/*
1325 * non-error returns are a promise to giveback() the urb later
1326 * we drop ownership so next owner (or urb unlink) can get it
1327 */
1328int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1329{
1330 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1331 struct xhci_td *buffer;
1332 unsigned long flags;
1333 int ret = 0;
1334 unsigned int slot_id, ep_index;
1335 struct urb_priv *urb_priv;
1336 int size, i;
1337
1338 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1339 true, true, __func__) <= 0)
1340 return -EINVAL;
1341
1342 slot_id = urb->dev->slot_id;
1343 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1344
1345 if (!HCD_HW_ACCESSIBLE(hcd)) {
1346 if (!in_interrupt())
1347 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1348 ret = -ESHUTDOWN;
1349 goto exit;
1350 }
1351
1352 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1353 size = urb->number_of_packets;
1354 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1355 urb->transfer_buffer_length > 0 &&
1356 urb->transfer_flags & URB_ZERO_PACKET &&
1357 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1358 size = 2;
1359 else
1360 size = 1;
1361
1362 urb_priv = kzalloc(sizeof(struct urb_priv) +
1363 size * sizeof(struct xhci_td *), mem_flags);
1364 if (!urb_priv)
1365 return -ENOMEM;
1366
1367 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1368 if (!buffer) {
1369 kfree(urb_priv);
1370 return -ENOMEM;
1371 }
1372
1373 for (i = 0; i < size; i++) {
1374 urb_priv->td[i] = buffer;
1375 buffer++;
1376 }
1377
1378 urb_priv->length = size;
1379 urb_priv->td_cnt = 0;
1380 urb->hcpriv = urb_priv;
1381
1382 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1383 /* Check to see if the max packet size for the default control
1384 * endpoint changed during FS device enumeration
1385 */
1386 if (urb->dev->speed == USB_SPEED_FULL) {
1387 ret = xhci_check_maxpacket(xhci, slot_id,
1388 ep_index, urb);
1389 if (ret < 0) {
1390 xhci_urb_free_priv(urb_priv);
1391 urb->hcpriv = NULL;
1392 return ret;
1393 }
1394 }
1395
1396 /* We have a spinlock and interrupts disabled, so we must pass
1397 * atomic context to this function, which may allocate memory.
1398 */
1399 spin_lock_irqsave(&xhci->lock, flags);
1400 if (xhci->xhc_state & XHCI_STATE_DYING)
1401 goto dying;
1402 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1403 slot_id, ep_index);
1404 if (ret)
1405 goto free_priv;
1406 spin_unlock_irqrestore(&xhci->lock, flags);
1407 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1408 spin_lock_irqsave(&xhci->lock, flags);
1409 if (xhci->xhc_state & XHCI_STATE_DYING)
1410 goto dying;
1411 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1412 EP_GETTING_STREAMS) {
1413 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1414 "is transitioning to using streams.\n");
1415 ret = -EINVAL;
1416 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1417 EP_GETTING_NO_STREAMS) {
1418 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1419 "is transitioning to "
1420 "not having streams.\n");
1421 ret = -EINVAL;
1422 } else {
1423 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1424 slot_id, ep_index);
1425 }
1426 if (ret)
1427 goto free_priv;
1428 spin_unlock_irqrestore(&xhci->lock, flags);
1429 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1430 spin_lock_irqsave(&xhci->lock, flags);
1431 if (xhci->xhc_state & XHCI_STATE_DYING)
1432 goto dying;
1433 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1434 slot_id, ep_index);
1435 if (ret)
1436 goto free_priv;
1437 spin_unlock_irqrestore(&xhci->lock, flags);
1438 } else {
1439 spin_lock_irqsave(&xhci->lock, flags);
1440 if (xhci->xhc_state & XHCI_STATE_DYING)
1441 goto dying;
1442 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1443 slot_id, ep_index);
1444 if (ret)
1445 goto free_priv;
1446 spin_unlock_irqrestore(&xhci->lock, flags);
1447 }
1448exit:
1449 return ret;
1450dying:
1451 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1452 "non-responsive xHCI host.\n",
1453 urb->ep->desc.bEndpointAddress, urb);
1454 ret = -ESHUTDOWN;
1455free_priv:
1456 xhci_urb_free_priv(urb_priv);
1457 urb->hcpriv = NULL;
1458 spin_unlock_irqrestore(&xhci->lock, flags);
1459 return ret;
1460}
1461
1462/* Get the right ring for the given URB.
1463 * If the endpoint supports streams, boundary check the URB's stream ID.
1464 * If the endpoint doesn't support streams, return the singular endpoint ring.
1465 */
1466static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1467 struct urb *urb)
1468{
1469 unsigned int slot_id;
1470 unsigned int ep_index;
1471 unsigned int stream_id;
1472 struct xhci_virt_ep *ep;
1473
1474 slot_id = urb->dev->slot_id;
1475 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1476 stream_id = urb->stream_id;
1477 ep = &xhci->devs[slot_id]->eps[ep_index];
1478 /* Common case: no streams */
1479 if (!(ep->ep_state & EP_HAS_STREAMS))
1480 return ep->ring;
1481
1482 if (stream_id == 0) {
1483 xhci_warn(xhci,
1484 "WARN: Slot ID %u, ep index %u has streams, "
1485 "but URB has no stream ID.\n",
1486 slot_id, ep_index);
1487 return NULL;
1488 }
1489
1490 if (stream_id < ep->stream_info->num_streams)
1491 return ep->stream_info->stream_rings[stream_id];
1492
1493 xhci_warn(xhci,
1494 "WARN: Slot ID %u, ep index %u has "
1495 "stream IDs 1 to %u allocated, "
1496 "but stream ID %u is requested.\n",
1497 slot_id, ep_index,
1498 ep->stream_info->num_streams - 1,
1499 stream_id);
1500 return NULL;
1501}
1502
1503/*
1504 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1505 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1506 * should pick up where it left off in the TD, unless a Set Transfer Ring
1507 * Dequeue Pointer is issued.
1508 *
1509 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1510 * the ring. Since the ring is a contiguous structure, they can't be physically
1511 * removed. Instead, there are two options:
1512 *
1513 * 1) If the HC is in the middle of processing the URB to be canceled, we
1514 * simply move the ring's dequeue pointer past those TRBs using the Set
1515 * Transfer Ring Dequeue Pointer command. This will be the common case,
1516 * when drivers timeout on the last submitted URB and attempt to cancel.
1517 *
1518 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1519 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1520 * HC will need to invalidate the any TRBs it has cached after the stop
1521 * endpoint command, as noted in the xHCI 0.95 errata.
1522 *
1523 * 3) The TD may have completed by the time the Stop Endpoint Command
1524 * completes, so software needs to handle that case too.
1525 *
1526 * This function should protect against the TD enqueueing code ringing the
1527 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1528 * It also needs to account for multiple cancellations on happening at the same
1529 * time for the same endpoint.
1530 *
1531 * Note that this function can be called in any context, or so says
1532 * usb_hcd_unlink_urb()
1533 */
1534int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1535{
1536 unsigned long flags;
1537 int ret, i;
1538 u32 temp;
1539 struct xhci_hcd *xhci;
1540 struct urb_priv *urb_priv;
1541 struct xhci_td *td;
1542 unsigned int ep_index;
1543 struct xhci_ring *ep_ring;
1544 struct xhci_virt_ep *ep;
1545 struct xhci_command *command;
1546
1547 xhci = hcd_to_xhci(hcd);
1548 spin_lock_irqsave(&xhci->lock, flags);
1549 /* Make sure the URB hasn't completed or been unlinked already */
1550 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1551 if (ret || !urb->hcpriv)
1552 goto done;
1553 temp = readl(&xhci->op_regs->status);
1554 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1555 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1556 "HW died, freeing TD.");
1557 urb_priv = urb->hcpriv;
1558 for (i = urb_priv->td_cnt;
1559 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1560 i++) {
1561 td = urb_priv->td[i];
1562 if (!list_empty(&td->td_list))
1563 list_del_init(&td->td_list);
1564 if (!list_empty(&td->cancelled_td_list))
1565 list_del_init(&td->cancelled_td_list);
1566 }
1567
1568 usb_hcd_unlink_urb_from_ep(hcd, urb);
1569 spin_unlock_irqrestore(&xhci->lock, flags);
1570 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1571 xhci_urb_free_priv(urb_priv);
1572 return ret;
1573 }
1574 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1575 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1576 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1577 "Ep 0x%x: URB %p to be canceled on "
1578 "non-responsive xHCI host.",
1579 urb->ep->desc.bEndpointAddress, urb);
1580 /* Let the stop endpoint command watchdog timer (which set this
1581 * state) finish cleaning up the endpoint TD lists. We must
1582 * have caught it in the middle of dropping a lock and giving
1583 * back an URB.
1584 */
1585 goto done;
1586 }
1587
1588 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1589 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1590 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1591 if (!ep_ring) {
1592 ret = -EINVAL;
1593 goto done;
1594 }
1595
1596 urb_priv = urb->hcpriv;
1597 i = urb_priv->td_cnt;
1598 if (i < urb_priv->length)
1599 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1600 "Cancel URB %p, dev %s, ep 0x%x, "
1601 "starting at offset 0x%llx",
1602 urb, urb->dev->devpath,
1603 urb->ep->desc.bEndpointAddress,
1604 (unsigned long long) xhci_trb_virt_to_dma(
1605 urb_priv->td[i]->start_seg,
1606 urb_priv->td[i]->first_trb));
1607
1608 for (; i < urb_priv->length; i++) {
1609 td = urb_priv->td[i];
1610 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1611 }
1612
1613 /* Queue a stop endpoint command, but only if this is
1614 * the first cancellation to be handled.
1615 */
1616 if (!(ep->ep_state & EP_HALT_PENDING)) {
1617 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1618 if (!command) {
1619 ret = -ENOMEM;
1620 goto done;
1621 }
1622 ep->ep_state |= EP_HALT_PENDING;
1623 ep->stop_cmds_pending++;
1624 ep->stop_cmd_timer.expires = jiffies +
1625 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1626 add_timer(&ep->stop_cmd_timer);
1627 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1628 ep_index, 0);
1629 xhci_ring_cmd_db(xhci);
1630 }
1631done:
1632 spin_unlock_irqrestore(&xhci->lock, flags);
1633 return ret;
1634}
1635
1636/* Drop an endpoint from a new bandwidth configuration for this device.
1637 * Only one call to this function is allowed per endpoint before
1638 * check_bandwidth() or reset_bandwidth() must be called.
1639 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1640 * add the endpoint to the schedule with possibly new parameters denoted by a
1641 * different endpoint descriptor in usb_host_endpoint.
1642 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1643 * not allowed.
1644 *
1645 * The USB core will not allow URBs to be queued to an endpoint that is being
1646 * disabled, so there's no need for mutual exclusion to protect
1647 * the xhci->devs[slot_id] structure.
1648 */
1649int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1650 struct usb_host_endpoint *ep)
1651{
1652 struct xhci_hcd *xhci;
1653 struct xhci_container_ctx *in_ctx, *out_ctx;
1654 struct xhci_input_control_ctx *ctrl_ctx;
1655 unsigned int ep_index;
1656 struct xhci_ep_ctx *ep_ctx;
1657 u32 drop_flag;
1658 u32 new_add_flags, new_drop_flags;
1659 int ret;
1660
1661 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1662 if (ret <= 0)
1663 return ret;
1664 xhci = hcd_to_xhci(hcd);
1665 if (xhci->xhc_state & XHCI_STATE_DYING)
1666 return -ENODEV;
1667
1668 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1669 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1670 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1671 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1672 __func__, drop_flag);
1673 return 0;
1674 }
1675
1676 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1677 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1678 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1679 if (!ctrl_ctx) {
1680 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1681 __func__);
1682 return 0;
1683 }
1684
1685 ep_index = xhci_get_endpoint_index(&ep->desc);
1686 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1687 /* If the HC already knows the endpoint is disabled,
1688 * or the HCD has noted it is disabled, ignore this request
1689 */
1690 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1691 cpu_to_le32(EP_STATE_DISABLED)) ||
1692 le32_to_cpu(ctrl_ctx->drop_flags) &
1693 xhci_get_endpoint_flag(&ep->desc)) {
1694 /* Do not warn when called after a usb_device_reset */
1695 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1696 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1697 __func__, ep);
1698 return 0;
1699 }
1700
1701 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1702 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1703
1704 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1705 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1706
1707 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1708
1709 if (xhci->quirks & XHCI_MTK_HOST)
1710 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1711
1712 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1713 (unsigned int) ep->desc.bEndpointAddress,
1714 udev->slot_id,
1715 (unsigned int) new_drop_flags,
1716 (unsigned int) new_add_flags);
1717 return 0;
1718}
1719
1720/* Add an endpoint to a new possible bandwidth configuration for this device.
1721 * Only one call to this function is allowed per endpoint before
1722 * check_bandwidth() or reset_bandwidth() must be called.
1723 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1724 * add the endpoint to the schedule with possibly new parameters denoted by a
1725 * different endpoint descriptor in usb_host_endpoint.
1726 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1727 * not allowed.
1728 *
1729 * The USB core will not allow URBs to be queued to an endpoint until the
1730 * configuration or alt setting is installed in the device, so there's no need
1731 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1732 */
1733int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1734 struct usb_host_endpoint *ep)
1735{
1736 struct xhci_hcd *xhci;
1737 struct xhci_container_ctx *in_ctx;
1738 unsigned int ep_index;
1739 struct xhci_input_control_ctx *ctrl_ctx;
1740 u32 added_ctxs;
1741 u32 new_add_flags, new_drop_flags;
1742 struct xhci_virt_device *virt_dev;
1743 int ret = 0;
1744
1745 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1746 if (ret <= 0) {
1747 /* So we won't queue a reset ep command for a root hub */
1748 ep->hcpriv = NULL;
1749 return ret;
1750 }
1751 xhci = hcd_to_xhci(hcd);
1752 if (xhci->xhc_state & XHCI_STATE_DYING)
1753 return -ENODEV;
1754
1755 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1756 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1757 /* FIXME when we have to issue an evaluate endpoint command to
1758 * deal with ep0 max packet size changing once we get the
1759 * descriptors
1760 */
1761 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1762 __func__, added_ctxs);
1763 return 0;
1764 }
1765
1766 virt_dev = xhci->devs[udev->slot_id];
1767 in_ctx = virt_dev->in_ctx;
1768 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1769 if (!ctrl_ctx) {
1770 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1771 __func__);
1772 return 0;
1773 }
1774
1775 ep_index = xhci_get_endpoint_index(&ep->desc);
1776 /* If this endpoint is already in use, and the upper layers are trying
1777 * to add it again without dropping it, reject the addition.
1778 */
1779 if (virt_dev->eps[ep_index].ring &&
1780 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1781 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1782 "without dropping it.\n",
1783 (unsigned int) ep->desc.bEndpointAddress);
1784 return -EINVAL;
1785 }
1786
1787 /* If the HCD has already noted the endpoint is enabled,
1788 * ignore this request.
1789 */
1790 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1791 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1792 __func__, ep);
1793 return 0;
1794 }
1795
1796 /*
1797 * Configuration and alternate setting changes must be done in
1798 * process context, not interrupt context (or so documenation
1799 * for usb_set_interface() and usb_set_configuration() claim).
1800 */
1801 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1802 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1803 __func__, ep->desc.bEndpointAddress);
1804 return -ENOMEM;
1805 }
1806
1807 if (xhci->quirks & XHCI_MTK_HOST) {
1808 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1809 if (ret < 0) {
1810 xhci_free_or_cache_endpoint_ring(xhci,
1811 virt_dev, ep_index);
1812 return ret;
1813 }
1814 }
1815
1816 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1817 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1818
1819 /* If xhci_endpoint_disable() was called for this endpoint, but the
1820 * xHC hasn't been notified yet through the check_bandwidth() call,
1821 * this re-adds a new state for the endpoint from the new endpoint
1822 * descriptors. We must drop and re-add this endpoint, so we leave the
1823 * drop flags alone.
1824 */
1825 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1826
1827 /* Store the usb_device pointer for later use */
1828 ep->hcpriv = udev;
1829
1830 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1831 (unsigned int) ep->desc.bEndpointAddress,
1832 udev->slot_id,
1833 (unsigned int) new_drop_flags,
1834 (unsigned int) new_add_flags);
1835 return 0;
1836}
1837
1838static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1839{
1840 struct xhci_input_control_ctx *ctrl_ctx;
1841 struct xhci_ep_ctx *ep_ctx;
1842 struct xhci_slot_ctx *slot_ctx;
1843 int i;
1844
1845 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1846 if (!ctrl_ctx) {
1847 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1848 __func__);
1849 return;
1850 }
1851
1852 /* When a device's add flag and drop flag are zero, any subsequent
1853 * configure endpoint command will leave that endpoint's state
1854 * untouched. Make sure we don't leave any old state in the input
1855 * endpoint contexts.
1856 */
1857 ctrl_ctx->drop_flags = 0;
1858 ctrl_ctx->add_flags = 0;
1859 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1860 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1861 /* Endpoint 0 is always valid */
1862 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1863 for (i = 1; i < 31; ++i) {
1864 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1865 ep_ctx->ep_info = 0;
1866 ep_ctx->ep_info2 = 0;
1867 ep_ctx->deq = 0;
1868 ep_ctx->tx_info = 0;
1869 }
1870}
1871
1872static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1873 struct usb_device *udev, u32 *cmd_status)
1874{
1875 int ret;
1876
1877 switch (*cmd_status) {
1878 case COMP_CMD_ABORT:
1879 case COMP_CMD_STOP:
1880 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1881 ret = -ETIME;
1882 break;
1883 case COMP_ENOMEM:
1884 dev_warn(&udev->dev,
1885 "Not enough host controller resources for new device state.\n");
1886 ret = -ENOMEM;
1887 /* FIXME: can we allocate more resources for the HC? */
1888 break;
1889 case COMP_BW_ERR:
1890 case COMP_2ND_BW_ERR:
1891 dev_warn(&udev->dev,
1892 "Not enough bandwidth for new device state.\n");
1893 ret = -ENOSPC;
1894 /* FIXME: can we go back to the old state? */
1895 break;
1896 case COMP_TRB_ERR:
1897 /* the HCD set up something wrong */
1898 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1899 "add flag = 1, "
1900 "and endpoint is not disabled.\n");
1901 ret = -EINVAL;
1902 break;
1903 case COMP_DEV_ERR:
1904 dev_warn(&udev->dev,
1905 "ERROR: Incompatible device for endpoint configure command.\n");
1906 ret = -ENODEV;
1907 break;
1908 case COMP_SUCCESS:
1909 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1910 "Successful Endpoint Configure command");
1911 ret = 0;
1912 break;
1913 default:
1914 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1915 *cmd_status);
1916 ret = -EINVAL;
1917 break;
1918 }
1919 return ret;
1920}
1921
1922static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1923 struct usb_device *udev, u32 *cmd_status)
1924{
1925 int ret;
1926 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1927
1928 switch (*cmd_status) {
1929 case COMP_CMD_ABORT:
1930 case COMP_CMD_STOP:
1931 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1932 ret = -ETIME;
1933 break;
1934 case COMP_EINVAL:
1935 dev_warn(&udev->dev,
1936 "WARN: xHCI driver setup invalid evaluate context command.\n");
1937 ret = -EINVAL;
1938 break;
1939 case COMP_EBADSLT:
1940 dev_warn(&udev->dev,
1941 "WARN: slot not enabled for evaluate context command.\n");
1942 ret = -EINVAL;
1943 break;
1944 case COMP_CTX_STATE:
1945 dev_warn(&udev->dev,
1946 "WARN: invalid context state for evaluate context command.\n");
1947 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1948 ret = -EINVAL;
1949 break;
1950 case COMP_DEV_ERR:
1951 dev_warn(&udev->dev,
1952 "ERROR: Incompatible device for evaluate context command.\n");
1953 ret = -ENODEV;
1954 break;
1955 case COMP_MEL_ERR:
1956 /* Max Exit Latency too large error */
1957 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1958 ret = -EINVAL;
1959 break;
1960 case COMP_SUCCESS:
1961 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1962 "Successful evaluate context command");
1963 ret = 0;
1964 break;
1965 default:
1966 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1967 *cmd_status);
1968 ret = -EINVAL;
1969 break;
1970 }
1971 return ret;
1972}
1973
1974static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1975 struct xhci_input_control_ctx *ctrl_ctx)
1976{
1977 u32 valid_add_flags;
1978 u32 valid_drop_flags;
1979
1980 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1981 * (bit 1). The default control endpoint is added during the Address
1982 * Device command and is never removed until the slot is disabled.
1983 */
1984 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1985 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1986
1987 /* Use hweight32 to count the number of ones in the add flags, or
1988 * number of endpoints added. Don't count endpoints that are changed
1989 * (both added and dropped).
1990 */
1991 return hweight32(valid_add_flags) -
1992 hweight32(valid_add_flags & valid_drop_flags);
1993}
1994
1995static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1996 struct xhci_input_control_ctx *ctrl_ctx)
1997{
1998 u32 valid_add_flags;
1999 u32 valid_drop_flags;
2000
2001 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2002 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2003
2004 return hweight32(valid_drop_flags) -
2005 hweight32(valid_add_flags & valid_drop_flags);
2006}
2007
2008/*
2009 * We need to reserve the new number of endpoints before the configure endpoint
2010 * command completes. We can't subtract the dropped endpoints from the number
2011 * of active endpoints until the command completes because we can oversubscribe
2012 * the host in this case:
2013 *
2014 * - the first configure endpoint command drops more endpoints than it adds
2015 * - a second configure endpoint command that adds more endpoints is queued
2016 * - the first configure endpoint command fails, so the config is unchanged
2017 * - the second command may succeed, even though there isn't enough resources
2018 *
2019 * Must be called with xhci->lock held.
2020 */
2021static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2022 struct xhci_input_control_ctx *ctrl_ctx)
2023{
2024 u32 added_eps;
2025
2026 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2027 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2028 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2029 "Not enough ep ctxs: "
2030 "%u active, need to add %u, limit is %u.",
2031 xhci->num_active_eps, added_eps,
2032 xhci->limit_active_eps);
2033 return -ENOMEM;
2034 }
2035 xhci->num_active_eps += added_eps;
2036 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2037 "Adding %u ep ctxs, %u now active.", added_eps,
2038 xhci->num_active_eps);
2039 return 0;
2040}
2041
2042/*
2043 * The configure endpoint was failed by the xHC for some other reason, so we
2044 * need to revert the resources that failed configuration would have used.
2045 *
2046 * Must be called with xhci->lock held.
2047 */
2048static void xhci_free_host_resources(struct xhci_hcd *xhci,
2049 struct xhci_input_control_ctx *ctrl_ctx)
2050{
2051 u32 num_failed_eps;
2052
2053 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2054 xhci->num_active_eps -= num_failed_eps;
2055 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2056 "Removing %u failed ep ctxs, %u now active.",
2057 num_failed_eps,
2058 xhci->num_active_eps);
2059}
2060
2061/*
2062 * Now that the command has completed, clean up the active endpoint count by
2063 * subtracting out the endpoints that were dropped (but not changed).
2064 *
2065 * Must be called with xhci->lock held.
2066 */
2067static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2068 struct xhci_input_control_ctx *ctrl_ctx)
2069{
2070 u32 num_dropped_eps;
2071
2072 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2073 xhci->num_active_eps -= num_dropped_eps;
2074 if (num_dropped_eps)
2075 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2076 "Removing %u dropped ep ctxs, %u now active.",
2077 num_dropped_eps,
2078 xhci->num_active_eps);
2079}
2080
2081static unsigned int xhci_get_block_size(struct usb_device *udev)
2082{
2083 switch (udev->speed) {
2084 case USB_SPEED_LOW:
2085 case USB_SPEED_FULL:
2086 return FS_BLOCK;
2087 case USB_SPEED_HIGH:
2088 return HS_BLOCK;
2089 case USB_SPEED_SUPER:
2090 case USB_SPEED_SUPER_PLUS:
2091 return SS_BLOCK;
2092 case USB_SPEED_UNKNOWN:
2093 case USB_SPEED_WIRELESS:
2094 default:
2095 /* Should never happen */
2096 return 1;
2097 }
2098}
2099
2100static unsigned int
2101xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2102{
2103 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2104 return LS_OVERHEAD;
2105 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2106 return FS_OVERHEAD;
2107 return HS_OVERHEAD;
2108}
2109
2110/* If we are changing a LS/FS device under a HS hub,
2111 * make sure (if we are activating a new TT) that the HS bus has enough
2112 * bandwidth for this new TT.
2113 */
2114static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2115 struct xhci_virt_device *virt_dev,
2116 int old_active_eps)
2117{
2118 struct xhci_interval_bw_table *bw_table;
2119 struct xhci_tt_bw_info *tt_info;
2120
2121 /* Find the bandwidth table for the root port this TT is attached to. */
2122 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2123 tt_info = virt_dev->tt_info;
2124 /* If this TT already had active endpoints, the bandwidth for this TT
2125 * has already been added. Removing all periodic endpoints (and thus
2126 * making the TT enactive) will only decrease the bandwidth used.
2127 */
2128 if (old_active_eps)
2129 return 0;
2130 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2131 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2132 return -ENOMEM;
2133 return 0;
2134 }
2135 /* Not sure why we would have no new active endpoints...
2136 *
2137 * Maybe because of an Evaluate Context change for a hub update or a
2138 * control endpoint 0 max packet size change?
2139 * FIXME: skip the bandwidth calculation in that case.
2140 */
2141 return 0;
2142}
2143
2144static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2145 struct xhci_virt_device *virt_dev)
2146{
2147 unsigned int bw_reserved;
2148
2149 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2150 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2151 return -ENOMEM;
2152
2153 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2154 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2155 return -ENOMEM;
2156
2157 return 0;
2158}
2159
2160/*
2161 * This algorithm is a very conservative estimate of the worst-case scheduling
2162 * scenario for any one interval. The hardware dynamically schedules the
2163 * packets, so we can't tell which microframe could be the limiting factor in
2164 * the bandwidth scheduling. This only takes into account periodic endpoints.
2165 *
2166 * Obviously, we can't solve an NP complete problem to find the minimum worst
2167 * case scenario. Instead, we come up with an estimate that is no less than
2168 * the worst case bandwidth used for any one microframe, but may be an
2169 * over-estimate.
2170 *
2171 * We walk the requirements for each endpoint by interval, starting with the
2172 * smallest interval, and place packets in the schedule where there is only one
2173 * possible way to schedule packets for that interval. In order to simplify
2174 * this algorithm, we record the largest max packet size for each interval, and
2175 * assume all packets will be that size.
2176 *
2177 * For interval 0, we obviously must schedule all packets for each interval.
2178 * The bandwidth for interval 0 is just the amount of data to be transmitted
2179 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2180 * the number of packets).
2181 *
2182 * For interval 1, we have two possible microframes to schedule those packets
2183 * in. For this algorithm, if we can schedule the same number of packets for
2184 * each possible scheduling opportunity (each microframe), we will do so. The
2185 * remaining number of packets will be saved to be transmitted in the gaps in
2186 * the next interval's scheduling sequence.
2187 *
2188 * As we move those remaining packets to be scheduled with interval 2 packets,
2189 * we have to double the number of remaining packets to transmit. This is
2190 * because the intervals are actually powers of 2, and we would be transmitting
2191 * the previous interval's packets twice in this interval. We also have to be
2192 * sure that when we look at the largest max packet size for this interval, we
2193 * also look at the largest max packet size for the remaining packets and take
2194 * the greater of the two.
2195 *
2196 * The algorithm continues to evenly distribute packets in each scheduling
2197 * opportunity, and push the remaining packets out, until we get to the last
2198 * interval. Then those packets and their associated overhead are just added
2199 * to the bandwidth used.
2200 */
2201static int xhci_check_bw_table(struct xhci_hcd *xhci,
2202 struct xhci_virt_device *virt_dev,
2203 int old_active_eps)
2204{
2205 unsigned int bw_reserved;
2206 unsigned int max_bandwidth;
2207 unsigned int bw_used;
2208 unsigned int block_size;
2209 struct xhci_interval_bw_table *bw_table;
2210 unsigned int packet_size = 0;
2211 unsigned int overhead = 0;
2212 unsigned int packets_transmitted = 0;
2213 unsigned int packets_remaining = 0;
2214 unsigned int i;
2215
2216 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2217 return xhci_check_ss_bw(xhci, virt_dev);
2218
2219 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2220 max_bandwidth = HS_BW_LIMIT;
2221 /* Convert percent of bus BW reserved to blocks reserved */
2222 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2223 } else {
2224 max_bandwidth = FS_BW_LIMIT;
2225 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2226 }
2227
2228 bw_table = virt_dev->bw_table;
2229 /* We need to translate the max packet size and max ESIT payloads into
2230 * the units the hardware uses.
2231 */
2232 block_size = xhci_get_block_size(virt_dev->udev);
2233
2234 /* If we are manipulating a LS/FS device under a HS hub, double check
2235 * that the HS bus has enough bandwidth if we are activing a new TT.
2236 */
2237 if (virt_dev->tt_info) {
2238 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2239 "Recalculating BW for rootport %u",
2240 virt_dev->real_port);
2241 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2242 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2243 "newly activated TT.\n");
2244 return -ENOMEM;
2245 }
2246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2247 "Recalculating BW for TT slot %u port %u",
2248 virt_dev->tt_info->slot_id,
2249 virt_dev->tt_info->ttport);
2250 } else {
2251 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2252 "Recalculating BW for rootport %u",
2253 virt_dev->real_port);
2254 }
2255
2256 /* Add in how much bandwidth will be used for interval zero, or the
2257 * rounded max ESIT payload + number of packets * largest overhead.
2258 */
2259 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2260 bw_table->interval_bw[0].num_packets *
2261 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2262
2263 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2264 unsigned int bw_added;
2265 unsigned int largest_mps;
2266 unsigned int interval_overhead;
2267
2268 /*
2269 * How many packets could we transmit in this interval?
2270 * If packets didn't fit in the previous interval, we will need
2271 * to transmit that many packets twice within this interval.
2272 */
2273 packets_remaining = 2 * packets_remaining +
2274 bw_table->interval_bw[i].num_packets;
2275
2276 /* Find the largest max packet size of this or the previous
2277 * interval.
2278 */
2279 if (list_empty(&bw_table->interval_bw[i].endpoints))
2280 largest_mps = 0;
2281 else {
2282 struct xhci_virt_ep *virt_ep;
2283 struct list_head *ep_entry;
2284
2285 ep_entry = bw_table->interval_bw[i].endpoints.next;
2286 virt_ep = list_entry(ep_entry,
2287 struct xhci_virt_ep, bw_endpoint_list);
2288 /* Convert to blocks, rounding up */
2289 largest_mps = DIV_ROUND_UP(
2290 virt_ep->bw_info.max_packet_size,
2291 block_size);
2292 }
2293 if (largest_mps > packet_size)
2294 packet_size = largest_mps;
2295
2296 /* Use the larger overhead of this or the previous interval. */
2297 interval_overhead = xhci_get_largest_overhead(
2298 &bw_table->interval_bw[i]);
2299 if (interval_overhead > overhead)
2300 overhead = interval_overhead;
2301
2302 /* How many packets can we evenly distribute across
2303 * (1 << (i + 1)) possible scheduling opportunities?
2304 */
2305 packets_transmitted = packets_remaining >> (i + 1);
2306
2307 /* Add in the bandwidth used for those scheduled packets */
2308 bw_added = packets_transmitted * (overhead + packet_size);
2309
2310 /* How many packets do we have remaining to transmit? */
2311 packets_remaining = packets_remaining % (1 << (i + 1));
2312
2313 /* What largest max packet size should those packets have? */
2314 /* If we've transmitted all packets, don't carry over the
2315 * largest packet size.
2316 */
2317 if (packets_remaining == 0) {
2318 packet_size = 0;
2319 overhead = 0;
2320 } else if (packets_transmitted > 0) {
2321 /* Otherwise if we do have remaining packets, and we've
2322 * scheduled some packets in this interval, take the
2323 * largest max packet size from endpoints with this
2324 * interval.
2325 */
2326 packet_size = largest_mps;
2327 overhead = interval_overhead;
2328 }
2329 /* Otherwise carry over packet_size and overhead from the last
2330 * time we had a remainder.
2331 */
2332 bw_used += bw_added;
2333 if (bw_used > max_bandwidth) {
2334 xhci_warn(xhci, "Not enough bandwidth. "
2335 "Proposed: %u, Max: %u\n",
2336 bw_used, max_bandwidth);
2337 return -ENOMEM;
2338 }
2339 }
2340 /*
2341 * Ok, we know we have some packets left over after even-handedly
2342 * scheduling interval 15. We don't know which microframes they will
2343 * fit into, so we over-schedule and say they will be scheduled every
2344 * microframe.
2345 */
2346 if (packets_remaining > 0)
2347 bw_used += overhead + packet_size;
2348
2349 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2350 unsigned int port_index = virt_dev->real_port - 1;
2351
2352 /* OK, we're manipulating a HS device attached to a
2353 * root port bandwidth domain. Include the number of active TTs
2354 * in the bandwidth used.
2355 */
2356 bw_used += TT_HS_OVERHEAD *
2357 xhci->rh_bw[port_index].num_active_tts;
2358 }
2359
2360 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2361 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2362 "Available: %u " "percent",
2363 bw_used, max_bandwidth, bw_reserved,
2364 (max_bandwidth - bw_used - bw_reserved) * 100 /
2365 max_bandwidth);
2366
2367 bw_used += bw_reserved;
2368 if (bw_used > max_bandwidth) {
2369 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2370 bw_used, max_bandwidth);
2371 return -ENOMEM;
2372 }
2373
2374 bw_table->bw_used = bw_used;
2375 return 0;
2376}
2377
2378static bool xhci_is_async_ep(unsigned int ep_type)
2379{
2380 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2381 ep_type != ISOC_IN_EP &&
2382 ep_type != INT_IN_EP);
2383}
2384
2385static bool xhci_is_sync_in_ep(unsigned int ep_type)
2386{
2387 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2388}
2389
2390static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2391{
2392 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2393
2394 if (ep_bw->ep_interval == 0)
2395 return SS_OVERHEAD_BURST +
2396 (ep_bw->mult * ep_bw->num_packets *
2397 (SS_OVERHEAD + mps));
2398 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2399 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2400 1 << ep_bw->ep_interval);
2401
2402}
2403
2404void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2405 struct xhci_bw_info *ep_bw,
2406 struct xhci_interval_bw_table *bw_table,
2407 struct usb_device *udev,
2408 struct xhci_virt_ep *virt_ep,
2409 struct xhci_tt_bw_info *tt_info)
2410{
2411 struct xhci_interval_bw *interval_bw;
2412 int normalized_interval;
2413
2414 if (xhci_is_async_ep(ep_bw->type))
2415 return;
2416
2417 if (udev->speed >= USB_SPEED_SUPER) {
2418 if (xhci_is_sync_in_ep(ep_bw->type))
2419 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2420 xhci_get_ss_bw_consumed(ep_bw);
2421 else
2422 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2423 xhci_get_ss_bw_consumed(ep_bw);
2424 return;
2425 }
2426
2427 /* SuperSpeed endpoints never get added to intervals in the table, so
2428 * this check is only valid for HS/FS/LS devices.
2429 */
2430 if (list_empty(&virt_ep->bw_endpoint_list))
2431 return;
2432 /* For LS/FS devices, we need to translate the interval expressed in
2433 * microframes to frames.
2434 */
2435 if (udev->speed == USB_SPEED_HIGH)
2436 normalized_interval = ep_bw->ep_interval;
2437 else
2438 normalized_interval = ep_bw->ep_interval - 3;
2439
2440 if (normalized_interval == 0)
2441 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2442 interval_bw = &bw_table->interval_bw[normalized_interval];
2443 interval_bw->num_packets -= ep_bw->num_packets;
2444 switch (udev->speed) {
2445 case USB_SPEED_LOW:
2446 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2447 break;
2448 case USB_SPEED_FULL:
2449 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2450 break;
2451 case USB_SPEED_HIGH:
2452 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2453 break;
2454 case USB_SPEED_SUPER:
2455 case USB_SPEED_SUPER_PLUS:
2456 case USB_SPEED_UNKNOWN:
2457 case USB_SPEED_WIRELESS:
2458 /* Should never happen because only LS/FS/HS endpoints will get
2459 * added to the endpoint list.
2460 */
2461 return;
2462 }
2463 if (tt_info)
2464 tt_info->active_eps -= 1;
2465 list_del_init(&virt_ep->bw_endpoint_list);
2466}
2467
2468static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2469 struct xhci_bw_info *ep_bw,
2470 struct xhci_interval_bw_table *bw_table,
2471 struct usb_device *udev,
2472 struct xhci_virt_ep *virt_ep,
2473 struct xhci_tt_bw_info *tt_info)
2474{
2475 struct xhci_interval_bw *interval_bw;
2476 struct xhci_virt_ep *smaller_ep;
2477 int normalized_interval;
2478
2479 if (xhci_is_async_ep(ep_bw->type))
2480 return;
2481
2482 if (udev->speed == USB_SPEED_SUPER) {
2483 if (xhci_is_sync_in_ep(ep_bw->type))
2484 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2485 xhci_get_ss_bw_consumed(ep_bw);
2486 else
2487 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2488 xhci_get_ss_bw_consumed(ep_bw);
2489 return;
2490 }
2491
2492 /* For LS/FS devices, we need to translate the interval expressed in
2493 * microframes to frames.
2494 */
2495 if (udev->speed == USB_SPEED_HIGH)
2496 normalized_interval = ep_bw->ep_interval;
2497 else
2498 normalized_interval = ep_bw->ep_interval - 3;
2499
2500 if (normalized_interval == 0)
2501 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2502 interval_bw = &bw_table->interval_bw[normalized_interval];
2503 interval_bw->num_packets += ep_bw->num_packets;
2504 switch (udev->speed) {
2505 case USB_SPEED_LOW:
2506 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2507 break;
2508 case USB_SPEED_FULL:
2509 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2510 break;
2511 case USB_SPEED_HIGH:
2512 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2513 break;
2514 case USB_SPEED_SUPER:
2515 case USB_SPEED_SUPER_PLUS:
2516 case USB_SPEED_UNKNOWN:
2517 case USB_SPEED_WIRELESS:
2518 /* Should never happen because only LS/FS/HS endpoints will get
2519 * added to the endpoint list.
2520 */
2521 return;
2522 }
2523
2524 if (tt_info)
2525 tt_info->active_eps += 1;
2526 /* Insert the endpoint into the list, largest max packet size first. */
2527 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2528 bw_endpoint_list) {
2529 if (ep_bw->max_packet_size >=
2530 smaller_ep->bw_info.max_packet_size) {
2531 /* Add the new ep before the smaller endpoint */
2532 list_add_tail(&virt_ep->bw_endpoint_list,
2533 &smaller_ep->bw_endpoint_list);
2534 return;
2535 }
2536 }
2537 /* Add the new endpoint at the end of the list. */
2538 list_add_tail(&virt_ep->bw_endpoint_list,
2539 &interval_bw->endpoints);
2540}
2541
2542void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2543 struct xhci_virt_device *virt_dev,
2544 int old_active_eps)
2545{
2546 struct xhci_root_port_bw_info *rh_bw_info;
2547 if (!virt_dev->tt_info)
2548 return;
2549
2550 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2551 if (old_active_eps == 0 &&
2552 virt_dev->tt_info->active_eps != 0) {
2553 rh_bw_info->num_active_tts += 1;
2554 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2555 } else if (old_active_eps != 0 &&
2556 virt_dev->tt_info->active_eps == 0) {
2557 rh_bw_info->num_active_tts -= 1;
2558 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2559 }
2560}
2561
2562static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2563 struct xhci_virt_device *virt_dev,
2564 struct xhci_container_ctx *in_ctx)
2565{
2566 struct xhci_bw_info ep_bw_info[31];
2567 int i;
2568 struct xhci_input_control_ctx *ctrl_ctx;
2569 int old_active_eps = 0;
2570
2571 if (virt_dev->tt_info)
2572 old_active_eps = virt_dev->tt_info->active_eps;
2573
2574 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2575 if (!ctrl_ctx) {
2576 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2577 __func__);
2578 return -ENOMEM;
2579 }
2580
2581 for (i = 0; i < 31; i++) {
2582 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2583 continue;
2584
2585 /* Make a copy of the BW info in case we need to revert this */
2586 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2587 sizeof(ep_bw_info[i]));
2588 /* Drop the endpoint from the interval table if the endpoint is
2589 * being dropped or changed.
2590 */
2591 if (EP_IS_DROPPED(ctrl_ctx, i))
2592 xhci_drop_ep_from_interval_table(xhci,
2593 &virt_dev->eps[i].bw_info,
2594 virt_dev->bw_table,
2595 virt_dev->udev,
2596 &virt_dev->eps[i],
2597 virt_dev->tt_info);
2598 }
2599 /* Overwrite the information stored in the endpoints' bw_info */
2600 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2601 for (i = 0; i < 31; i++) {
2602 /* Add any changed or added endpoints to the interval table */
2603 if (EP_IS_ADDED(ctrl_ctx, i))
2604 xhci_add_ep_to_interval_table(xhci,
2605 &virt_dev->eps[i].bw_info,
2606 virt_dev->bw_table,
2607 virt_dev->udev,
2608 &virt_dev->eps[i],
2609 virt_dev->tt_info);
2610 }
2611
2612 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2613 /* Ok, this fits in the bandwidth we have.
2614 * Update the number of active TTs.
2615 */
2616 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2617 return 0;
2618 }
2619
2620 /* We don't have enough bandwidth for this, revert the stored info. */
2621 for (i = 0; i < 31; i++) {
2622 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2623 continue;
2624
2625 /* Drop the new copies of any added or changed endpoints from
2626 * the interval table.
2627 */
2628 if (EP_IS_ADDED(ctrl_ctx, i)) {
2629 xhci_drop_ep_from_interval_table(xhci,
2630 &virt_dev->eps[i].bw_info,
2631 virt_dev->bw_table,
2632 virt_dev->udev,
2633 &virt_dev->eps[i],
2634 virt_dev->tt_info);
2635 }
2636 /* Revert the endpoint back to its old information */
2637 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2638 sizeof(ep_bw_info[i]));
2639 /* Add any changed or dropped endpoints back into the table */
2640 if (EP_IS_DROPPED(ctrl_ctx, i))
2641 xhci_add_ep_to_interval_table(xhci,
2642 &virt_dev->eps[i].bw_info,
2643 virt_dev->bw_table,
2644 virt_dev->udev,
2645 &virt_dev->eps[i],
2646 virt_dev->tt_info);
2647 }
2648 return -ENOMEM;
2649}
2650
2651
2652/* Issue a configure endpoint command or evaluate context command
2653 * and wait for it to finish.
2654 */
2655static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2656 struct usb_device *udev,
2657 struct xhci_command *command,
2658 bool ctx_change, bool must_succeed)
2659{
2660 int ret;
2661 unsigned long flags;
2662 struct xhci_input_control_ctx *ctrl_ctx;
2663 struct xhci_virt_device *virt_dev;
2664
2665 if (!command)
2666 return -EINVAL;
2667
2668 spin_lock_irqsave(&xhci->lock, flags);
2669 virt_dev = xhci->devs[udev->slot_id];
2670
2671 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2672 if (!ctrl_ctx) {
2673 spin_unlock_irqrestore(&xhci->lock, flags);
2674 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2675 __func__);
2676 return -ENOMEM;
2677 }
2678
2679 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2680 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2681 spin_unlock_irqrestore(&xhci->lock, flags);
2682 xhci_warn(xhci, "Not enough host resources, "
2683 "active endpoint contexts = %u\n",
2684 xhci->num_active_eps);
2685 return -ENOMEM;
2686 }
2687 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2688 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2689 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2690 xhci_free_host_resources(xhci, ctrl_ctx);
2691 spin_unlock_irqrestore(&xhci->lock, flags);
2692 xhci_warn(xhci, "Not enough bandwidth\n");
2693 return -ENOMEM;
2694 }
2695
2696 if (!ctx_change)
2697 ret = xhci_queue_configure_endpoint(xhci, command,
2698 command->in_ctx->dma,
2699 udev->slot_id, must_succeed);
2700 else
2701 ret = xhci_queue_evaluate_context(xhci, command,
2702 command->in_ctx->dma,
2703 udev->slot_id, must_succeed);
2704 if (ret < 0) {
2705 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2706 xhci_free_host_resources(xhci, ctrl_ctx);
2707 spin_unlock_irqrestore(&xhci->lock, flags);
2708 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2709 "FIXME allocate a new ring segment");
2710 return -ENOMEM;
2711 }
2712 xhci_ring_cmd_db(xhci);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714
2715 /* Wait for the configure endpoint command to complete */
2716 wait_for_completion(command->completion);
2717
2718 if (!ctx_change)
2719 ret = xhci_configure_endpoint_result(xhci, udev,
2720 &command->status);
2721 else
2722 ret = xhci_evaluate_context_result(xhci, udev,
2723 &command->status);
2724
2725 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2726 spin_lock_irqsave(&xhci->lock, flags);
2727 /* If the command failed, remove the reserved resources.
2728 * Otherwise, clean up the estimate to include dropped eps.
2729 */
2730 if (ret)
2731 xhci_free_host_resources(xhci, ctrl_ctx);
2732 else
2733 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2734 spin_unlock_irqrestore(&xhci->lock, flags);
2735 }
2736 return ret;
2737}
2738
2739static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2740 struct xhci_virt_device *vdev, int i)
2741{
2742 struct xhci_virt_ep *ep = &vdev->eps[i];
2743
2744 if (ep->ep_state & EP_HAS_STREAMS) {
2745 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2746 xhci_get_endpoint_address(i));
2747 xhci_free_stream_info(xhci, ep->stream_info);
2748 ep->stream_info = NULL;
2749 ep->ep_state &= ~EP_HAS_STREAMS;
2750 }
2751}
2752
2753/* Called after one or more calls to xhci_add_endpoint() or
2754 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2755 * to call xhci_reset_bandwidth().
2756 *
2757 * Since we are in the middle of changing either configuration or
2758 * installing a new alt setting, the USB core won't allow URBs to be
2759 * enqueued for any endpoint on the old config or interface. Nothing
2760 * else should be touching the xhci->devs[slot_id] structure, so we
2761 * don't need to take the xhci->lock for manipulating that.
2762 */
2763int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2764{
2765 int i;
2766 int ret = 0;
2767 struct xhci_hcd *xhci;
2768 struct xhci_virt_device *virt_dev;
2769 struct xhci_input_control_ctx *ctrl_ctx;
2770 struct xhci_slot_ctx *slot_ctx;
2771 struct xhci_command *command;
2772
2773 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2774 if (ret <= 0)
2775 return ret;
2776 xhci = hcd_to_xhci(hcd);
2777 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2778 (xhci->xhc_state & XHCI_STATE_REMOVING))
2779 return -ENODEV;
2780
2781 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2782 virt_dev = xhci->devs[udev->slot_id];
2783
2784 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2785 if (!command)
2786 return -ENOMEM;
2787
2788 command->in_ctx = virt_dev->in_ctx;
2789
2790 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2791 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2792 if (!ctrl_ctx) {
2793 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2794 __func__);
2795 ret = -ENOMEM;
2796 goto command_cleanup;
2797 }
2798 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2799 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2800 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2801
2802 /* Don't issue the command if there's no endpoints to update. */
2803 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2804 ctrl_ctx->drop_flags == 0) {
2805 ret = 0;
2806 goto command_cleanup;
2807 }
2808 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2809 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2810 for (i = 31; i >= 1; i--) {
2811 __le32 le32 = cpu_to_le32(BIT(i));
2812
2813 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2814 || (ctrl_ctx->add_flags & le32) || i == 1) {
2815 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2816 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2817 break;
2818 }
2819 }
2820 xhci_dbg(xhci, "New Input Control Context:\n");
2821 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2822 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2823
2824 ret = xhci_configure_endpoint(xhci, udev, command,
2825 false, false);
2826 if (ret)
2827 /* Callee should call reset_bandwidth() */
2828 goto command_cleanup;
2829
2830 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2831 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2832 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2833
2834 /* Free any rings that were dropped, but not changed. */
2835 for (i = 1; i < 31; ++i) {
2836 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2837 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2838 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2839 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2840 }
2841 }
2842 xhci_zero_in_ctx(xhci, virt_dev);
2843 /*
2844 * Install any rings for completely new endpoints or changed endpoints,
2845 * and free or cache any old rings from changed endpoints.
2846 */
2847 for (i = 1; i < 31; ++i) {
2848 if (!virt_dev->eps[i].new_ring)
2849 continue;
2850 /* Only cache or free the old ring if it exists.
2851 * It may not if this is the first add of an endpoint.
2852 */
2853 if (virt_dev->eps[i].ring) {
2854 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2855 }
2856 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2857 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2858 virt_dev->eps[i].new_ring = NULL;
2859 }
2860command_cleanup:
2861 kfree(command->completion);
2862 kfree(command);
2863
2864 return ret;
2865}
2866
2867void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2868{
2869 struct xhci_hcd *xhci;
2870 struct xhci_virt_device *virt_dev;
2871 int i, ret;
2872
2873 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2874 if (ret <= 0)
2875 return;
2876 xhci = hcd_to_xhci(hcd);
2877
2878 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2879 virt_dev = xhci->devs[udev->slot_id];
2880 /* Free any rings allocated for added endpoints */
2881 for (i = 0; i < 31; ++i) {
2882 if (virt_dev->eps[i].new_ring) {
2883 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2884 virt_dev->eps[i].new_ring = NULL;
2885 }
2886 }
2887 xhci_zero_in_ctx(xhci, virt_dev);
2888}
2889
2890static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2891 struct xhci_container_ctx *in_ctx,
2892 struct xhci_container_ctx *out_ctx,
2893 struct xhci_input_control_ctx *ctrl_ctx,
2894 u32 add_flags, u32 drop_flags)
2895{
2896 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2897 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2898 xhci_slot_copy(xhci, in_ctx, out_ctx);
2899 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2900
2901 xhci_dbg(xhci, "Input Context:\n");
2902 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2903}
2904
2905static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2906 unsigned int slot_id, unsigned int ep_index,
2907 struct xhci_dequeue_state *deq_state)
2908{
2909 struct xhci_input_control_ctx *ctrl_ctx;
2910 struct xhci_container_ctx *in_ctx;
2911 struct xhci_ep_ctx *ep_ctx;
2912 u32 added_ctxs;
2913 dma_addr_t addr;
2914
2915 in_ctx = xhci->devs[slot_id]->in_ctx;
2916 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2917 if (!ctrl_ctx) {
2918 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2919 __func__);
2920 return;
2921 }
2922
2923 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2924 xhci->devs[slot_id]->out_ctx, ep_index);
2925 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2926 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2927 deq_state->new_deq_ptr);
2928 if (addr == 0) {
2929 xhci_warn(xhci, "WARN Cannot submit config ep after "
2930 "reset ep command\n");
2931 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2932 deq_state->new_deq_seg,
2933 deq_state->new_deq_ptr);
2934 return;
2935 }
2936 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2937
2938 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2939 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2940 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2941 added_ctxs, added_ctxs);
2942}
2943
2944void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2945 unsigned int ep_index, struct xhci_td *td)
2946{
2947 struct xhci_dequeue_state deq_state;
2948 struct xhci_virt_ep *ep;
2949 struct usb_device *udev = td->urb->dev;
2950
2951 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2952 "Cleaning up stalled endpoint ring");
2953 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2954 /* We need to move the HW's dequeue pointer past this TD,
2955 * or it will attempt to resend it on the next doorbell ring.
2956 */
2957 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2958 ep_index, ep->stopped_stream, td, &deq_state);
2959
2960 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2961 return;
2962
2963 /* HW with the reset endpoint quirk will use the saved dequeue state to
2964 * issue a configure endpoint command later.
2965 */
2966 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2967 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2968 "Queueing new dequeue state");
2969 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2970 ep_index, ep->stopped_stream, &deq_state);
2971 } else {
2972 /* Better hope no one uses the input context between now and the
2973 * reset endpoint completion!
2974 * XXX: No idea how this hardware will react when stream rings
2975 * are enabled.
2976 */
2977 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2978 "Setting up input context for "
2979 "configure endpoint command");
2980 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2981 ep_index, &deq_state);
2982 }
2983}
2984
2985/* Called when clearing halted device. The core should have sent the control
2986 * message to clear the device halt condition. The host side of the halt should
2987 * already be cleared with a reset endpoint command issued when the STALL tx
2988 * event was received.
2989 *
2990 * Context: in_interrupt
2991 */
2992
2993void xhci_endpoint_reset(struct usb_hcd *hcd,
2994 struct usb_host_endpoint *ep)
2995{
2996 struct xhci_hcd *xhci;
2997
2998 xhci = hcd_to_xhci(hcd);
2999
3000 /*
3001 * We might need to implement the config ep cmd in xhci 4.8.1 note:
3002 * The Reset Endpoint Command may only be issued to endpoints in the
3003 * Halted state. If software wishes reset the Data Toggle or Sequence
3004 * Number of an endpoint that isn't in the Halted state, then software
3005 * may issue a Configure Endpoint Command with the Drop and Add bits set
3006 * for the target endpoint. that is in the Stopped state.
3007 */
3008
3009 /* For now just print debug to follow the situation */
3010 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3011 ep->desc.bEndpointAddress);
3012}
3013
3014static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3015 struct usb_device *udev, struct usb_host_endpoint *ep,
3016 unsigned int slot_id)
3017{
3018 int ret;
3019 unsigned int ep_index;
3020 unsigned int ep_state;
3021
3022 if (!ep)
3023 return -EINVAL;
3024 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3025 if (ret <= 0)
3026 return -EINVAL;
3027 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3028 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3029 " descriptor for ep 0x%x does not support streams\n",
3030 ep->desc.bEndpointAddress);
3031 return -EINVAL;
3032 }
3033
3034 ep_index = xhci_get_endpoint_index(&ep->desc);
3035 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3036 if (ep_state & EP_HAS_STREAMS ||
3037 ep_state & EP_GETTING_STREAMS) {
3038 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3039 "already has streams set up.\n",
3040 ep->desc.bEndpointAddress);
3041 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3042 "dynamic stream context array reallocation.\n");
3043 return -EINVAL;
3044 }
3045 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3046 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3047 "endpoint 0x%x; URBs are pending.\n",
3048 ep->desc.bEndpointAddress);
3049 return -EINVAL;
3050 }
3051 return 0;
3052}
3053
3054static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3055 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3056{
3057 unsigned int max_streams;
3058
3059 /* The stream context array size must be a power of two */
3060 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3061 /*
3062 * Find out how many primary stream array entries the host controller
3063 * supports. Later we may use secondary stream arrays (similar to 2nd
3064 * level page entries), but that's an optional feature for xHCI host
3065 * controllers. xHCs must support at least 4 stream IDs.
3066 */
3067 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3068 if (*num_stream_ctxs > max_streams) {
3069 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3070 max_streams);
3071 *num_stream_ctxs = max_streams;
3072 *num_streams = max_streams;
3073 }
3074}
3075
3076/* Returns an error code if one of the endpoint already has streams.
3077 * This does not change any data structures, it only checks and gathers
3078 * information.
3079 */
3080static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3081 struct usb_device *udev,
3082 struct usb_host_endpoint **eps, unsigned int num_eps,
3083 unsigned int *num_streams, u32 *changed_ep_bitmask)
3084{
3085 unsigned int max_streams;
3086 unsigned int endpoint_flag;
3087 int i;
3088 int ret;
3089
3090 for (i = 0; i < num_eps; i++) {
3091 ret = xhci_check_streams_endpoint(xhci, udev,
3092 eps[i], udev->slot_id);
3093 if (ret < 0)
3094 return ret;
3095
3096 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3097 if (max_streams < (*num_streams - 1)) {
3098 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3099 eps[i]->desc.bEndpointAddress,
3100 max_streams);
3101 *num_streams = max_streams+1;
3102 }
3103
3104 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3105 if (*changed_ep_bitmask & endpoint_flag)
3106 return -EINVAL;
3107 *changed_ep_bitmask |= endpoint_flag;
3108 }
3109 return 0;
3110}
3111
3112static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3113 struct usb_device *udev,
3114 struct usb_host_endpoint **eps, unsigned int num_eps)
3115{
3116 u32 changed_ep_bitmask = 0;
3117 unsigned int slot_id;
3118 unsigned int ep_index;
3119 unsigned int ep_state;
3120 int i;
3121
3122 slot_id = udev->slot_id;
3123 if (!xhci->devs[slot_id])
3124 return 0;
3125
3126 for (i = 0; i < num_eps; i++) {
3127 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3128 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3129 /* Are streams already being freed for the endpoint? */
3130 if (ep_state & EP_GETTING_NO_STREAMS) {
3131 xhci_warn(xhci, "WARN Can't disable streams for "
3132 "endpoint 0x%x, "
3133 "streams are being disabled already\n",
3134 eps[i]->desc.bEndpointAddress);
3135 return 0;
3136 }
3137 /* Are there actually any streams to free? */
3138 if (!(ep_state & EP_HAS_STREAMS) &&
3139 !(ep_state & EP_GETTING_STREAMS)) {
3140 xhci_warn(xhci, "WARN Can't disable streams for "
3141 "endpoint 0x%x, "
3142 "streams are already disabled!\n",
3143 eps[i]->desc.bEndpointAddress);
3144 xhci_warn(xhci, "WARN xhci_free_streams() called "
3145 "with non-streams endpoint\n");
3146 return 0;
3147 }
3148 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3149 }
3150 return changed_ep_bitmask;
3151}
3152
3153/*
3154 * The USB device drivers use this function (through the HCD interface in USB
3155 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3156 * coordinate mass storage command queueing across multiple endpoints (basically
3157 * a stream ID == a task ID).
3158 *
3159 * Setting up streams involves allocating the same size stream context array
3160 * for each endpoint and issuing a configure endpoint command for all endpoints.
3161 *
3162 * Don't allow the call to succeed if one endpoint only supports one stream
3163 * (which means it doesn't support streams at all).
3164 *
3165 * Drivers may get less stream IDs than they asked for, if the host controller
3166 * hardware or endpoints claim they can't support the number of requested
3167 * stream IDs.
3168 */
3169int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3170 struct usb_host_endpoint **eps, unsigned int num_eps,
3171 unsigned int num_streams, gfp_t mem_flags)
3172{
3173 int i, ret;
3174 struct xhci_hcd *xhci;
3175 struct xhci_virt_device *vdev;
3176 struct xhci_command *config_cmd;
3177 struct xhci_input_control_ctx *ctrl_ctx;
3178 unsigned int ep_index;
3179 unsigned int num_stream_ctxs;
3180 unsigned long flags;
3181 u32 changed_ep_bitmask = 0;
3182
3183 if (!eps)
3184 return -EINVAL;
3185
3186 /* Add one to the number of streams requested to account for
3187 * stream 0 that is reserved for xHCI usage.
3188 */
3189 num_streams += 1;
3190 xhci = hcd_to_xhci(hcd);
3191 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3192 num_streams);
3193
3194 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3195 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3196 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3197 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3198 return -ENOSYS;
3199 }
3200
3201 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3202 if (!config_cmd) {
3203 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3204 return -ENOMEM;
3205 }
3206 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3207 if (!ctrl_ctx) {
3208 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3209 __func__);
3210 xhci_free_command(xhci, config_cmd);
3211 return -ENOMEM;
3212 }
3213
3214 /* Check to make sure all endpoints are not already configured for
3215 * streams. While we're at it, find the maximum number of streams that
3216 * all the endpoints will support and check for duplicate endpoints.
3217 */
3218 spin_lock_irqsave(&xhci->lock, flags);
3219 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3220 num_eps, &num_streams, &changed_ep_bitmask);
3221 if (ret < 0) {
3222 xhci_free_command(xhci, config_cmd);
3223 spin_unlock_irqrestore(&xhci->lock, flags);
3224 return ret;
3225 }
3226 if (num_streams <= 1) {
3227 xhci_warn(xhci, "WARN: endpoints can't handle "
3228 "more than one stream.\n");
3229 xhci_free_command(xhci, config_cmd);
3230 spin_unlock_irqrestore(&xhci->lock, flags);
3231 return -EINVAL;
3232 }
3233 vdev = xhci->devs[udev->slot_id];
3234 /* Mark each endpoint as being in transition, so
3235 * xhci_urb_enqueue() will reject all URBs.
3236 */
3237 for (i = 0; i < num_eps; i++) {
3238 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3239 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3240 }
3241 spin_unlock_irqrestore(&xhci->lock, flags);
3242
3243 /* Setup internal data structures and allocate HW data structures for
3244 * streams (but don't install the HW structures in the input context
3245 * until we're sure all memory allocation succeeded).
3246 */
3247 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3248 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3249 num_stream_ctxs, num_streams);
3250
3251 for (i = 0; i < num_eps; i++) {
3252 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3253 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3254 num_stream_ctxs,
3255 num_streams, mem_flags);
3256 if (!vdev->eps[ep_index].stream_info)
3257 goto cleanup;
3258 /* Set maxPstreams in endpoint context and update deq ptr to
3259 * point to stream context array. FIXME
3260 */
3261 }
3262
3263 /* Set up the input context for a configure endpoint command. */
3264 for (i = 0; i < num_eps; i++) {
3265 struct xhci_ep_ctx *ep_ctx;
3266
3267 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3268 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3269
3270 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3271 vdev->out_ctx, ep_index);
3272 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3273 vdev->eps[ep_index].stream_info);
3274 }
3275 /* Tell the HW to drop its old copy of the endpoint context info
3276 * and add the updated copy from the input context.
3277 */
3278 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3279 vdev->out_ctx, ctrl_ctx,
3280 changed_ep_bitmask, changed_ep_bitmask);
3281
3282 /* Issue and wait for the configure endpoint command */
3283 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3284 false, false);
3285
3286 /* xHC rejected the configure endpoint command for some reason, so we
3287 * leave the old ring intact and free our internal streams data
3288 * structure.
3289 */
3290 if (ret < 0)
3291 goto cleanup;
3292
3293 spin_lock_irqsave(&xhci->lock, flags);
3294 for (i = 0; i < num_eps; i++) {
3295 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3296 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3297 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3298 udev->slot_id, ep_index);
3299 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3300 }
3301 xhci_free_command(xhci, config_cmd);
3302 spin_unlock_irqrestore(&xhci->lock, flags);
3303
3304 /* Subtract 1 for stream 0, which drivers can't use */
3305 return num_streams - 1;
3306
3307cleanup:
3308 /* If it didn't work, free the streams! */
3309 for (i = 0; i < num_eps; i++) {
3310 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3311 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3312 vdev->eps[ep_index].stream_info = NULL;
3313 /* FIXME Unset maxPstreams in endpoint context and
3314 * update deq ptr to point to normal string ring.
3315 */
3316 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3317 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3318 xhci_endpoint_zero(xhci, vdev, eps[i]);
3319 }
3320 xhci_free_command(xhci, config_cmd);
3321 return -ENOMEM;
3322}
3323
3324/* Transition the endpoint from using streams to being a "normal" endpoint
3325 * without streams.
3326 *
3327 * Modify the endpoint context state, submit a configure endpoint command,
3328 * and free all endpoint rings for streams if that completes successfully.
3329 */
3330int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3331 struct usb_host_endpoint **eps, unsigned int num_eps,
3332 gfp_t mem_flags)
3333{
3334 int i, ret;
3335 struct xhci_hcd *xhci;
3336 struct xhci_virt_device *vdev;
3337 struct xhci_command *command;
3338 struct xhci_input_control_ctx *ctrl_ctx;
3339 unsigned int ep_index;
3340 unsigned long flags;
3341 u32 changed_ep_bitmask;
3342
3343 xhci = hcd_to_xhci(hcd);
3344 vdev = xhci->devs[udev->slot_id];
3345
3346 /* Set up a configure endpoint command to remove the streams rings */
3347 spin_lock_irqsave(&xhci->lock, flags);
3348 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3349 udev, eps, num_eps);
3350 if (changed_ep_bitmask == 0) {
3351 spin_unlock_irqrestore(&xhci->lock, flags);
3352 return -EINVAL;
3353 }
3354
3355 /* Use the xhci_command structure from the first endpoint. We may have
3356 * allocated too many, but the driver may call xhci_free_streams() for
3357 * each endpoint it grouped into one call to xhci_alloc_streams().
3358 */
3359 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3360 command = vdev->eps[ep_index].stream_info->free_streams_command;
3361 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3362 if (!ctrl_ctx) {
3363 spin_unlock_irqrestore(&xhci->lock, flags);
3364 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3365 __func__);
3366 return -EINVAL;
3367 }
3368
3369 for (i = 0; i < num_eps; i++) {
3370 struct xhci_ep_ctx *ep_ctx;
3371
3372 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3373 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3374 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3375 EP_GETTING_NO_STREAMS;
3376
3377 xhci_endpoint_copy(xhci, command->in_ctx,
3378 vdev->out_ctx, ep_index);
3379 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3380 &vdev->eps[ep_index]);
3381 }
3382 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3383 vdev->out_ctx, ctrl_ctx,
3384 changed_ep_bitmask, changed_ep_bitmask);
3385 spin_unlock_irqrestore(&xhci->lock, flags);
3386
3387 /* Issue and wait for the configure endpoint command,
3388 * which must succeed.
3389 */
3390 ret = xhci_configure_endpoint(xhci, udev, command,
3391 false, true);
3392
3393 /* xHC rejected the configure endpoint command for some reason, so we
3394 * leave the streams rings intact.
3395 */
3396 if (ret < 0)
3397 return ret;
3398
3399 spin_lock_irqsave(&xhci->lock, flags);
3400 for (i = 0; i < num_eps; i++) {
3401 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3402 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3403 vdev->eps[ep_index].stream_info = NULL;
3404 /* FIXME Unset maxPstreams in endpoint context and
3405 * update deq ptr to point to normal string ring.
3406 */
3407 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3408 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3409 }
3410 spin_unlock_irqrestore(&xhci->lock, flags);
3411
3412 return 0;
3413}
3414
3415/*
3416 * Deletes endpoint resources for endpoints that were active before a Reset
3417 * Device command, or a Disable Slot command. The Reset Device command leaves
3418 * the control endpoint intact, whereas the Disable Slot command deletes it.
3419 *
3420 * Must be called with xhci->lock held.
3421 */
3422void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3423 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3424{
3425 int i;
3426 unsigned int num_dropped_eps = 0;
3427 unsigned int drop_flags = 0;
3428
3429 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3430 if (virt_dev->eps[i].ring) {
3431 drop_flags |= 1 << i;
3432 num_dropped_eps++;
3433 }
3434 }
3435 xhci->num_active_eps -= num_dropped_eps;
3436 if (num_dropped_eps)
3437 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3438 "Dropped %u ep ctxs, flags = 0x%x, "
3439 "%u now active.",
3440 num_dropped_eps, drop_flags,
3441 xhci->num_active_eps);
3442}
3443
3444/*
3445 * This submits a Reset Device Command, which will set the device state to 0,
3446 * set the device address to 0, and disable all the endpoints except the default
3447 * control endpoint. The USB core should come back and call
3448 * xhci_address_device(), and then re-set up the configuration. If this is
3449 * called because of a usb_reset_and_verify_device(), then the old alternate
3450 * settings will be re-installed through the normal bandwidth allocation
3451 * functions.
3452 *
3453 * Wait for the Reset Device command to finish. Remove all structures
3454 * associated with the endpoints that were disabled. Clear the input device
3455 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3456 *
3457 * If the virt_dev to be reset does not exist or does not match the udev,
3458 * it means the device is lost, possibly due to the xHC restore error and
3459 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3460 * re-allocate the device.
3461 */
3462int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3463{
3464 int ret, i;
3465 unsigned long flags;
3466 struct xhci_hcd *xhci;
3467 unsigned int slot_id;
3468 struct xhci_virt_device *virt_dev;
3469 struct xhci_command *reset_device_cmd;
3470 int last_freed_endpoint;
3471 struct xhci_slot_ctx *slot_ctx;
3472 int old_active_eps = 0;
3473
3474 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3475 if (ret <= 0)
3476 return ret;
3477 xhci = hcd_to_xhci(hcd);
3478 slot_id = udev->slot_id;
3479 virt_dev = xhci->devs[slot_id];
3480 if (!virt_dev) {
3481 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3482 "not exist. Re-allocate the device\n", slot_id);
3483 ret = xhci_alloc_dev(hcd, udev);
3484 if (ret == 1)
3485 return 0;
3486 else
3487 return -EINVAL;
3488 }
3489
3490 if (virt_dev->tt_info)
3491 old_active_eps = virt_dev->tt_info->active_eps;
3492
3493 if (virt_dev->udev != udev) {
3494 /* If the virt_dev and the udev does not match, this virt_dev
3495 * may belong to another udev.
3496 * Re-allocate the device.
3497 */
3498 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3499 "not match the udev. Re-allocate the device\n",
3500 slot_id);
3501 ret = xhci_alloc_dev(hcd, udev);
3502 if (ret == 1)
3503 return 0;
3504 else
3505 return -EINVAL;
3506 }
3507
3508 /* If device is not setup, there is no point in resetting it */
3509 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3510 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3511 SLOT_STATE_DISABLED)
3512 return 0;
3513
3514 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3515 /* Allocate the command structure that holds the struct completion.
3516 * Assume we're in process context, since the normal device reset
3517 * process has to wait for the device anyway. Storage devices are
3518 * reset as part of error handling, so use GFP_NOIO instead of
3519 * GFP_KERNEL.
3520 */
3521 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3522 if (!reset_device_cmd) {
3523 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3524 return -ENOMEM;
3525 }
3526
3527 /* Attempt to submit the Reset Device command to the command ring */
3528 spin_lock_irqsave(&xhci->lock, flags);
3529
3530 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3531 if (ret) {
3532 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3533 spin_unlock_irqrestore(&xhci->lock, flags);
3534 goto command_cleanup;
3535 }
3536 xhci_ring_cmd_db(xhci);
3537 spin_unlock_irqrestore(&xhci->lock, flags);
3538
3539 /* Wait for the Reset Device command to finish */
3540 wait_for_completion(reset_device_cmd->completion);
3541
3542 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3543 * unless we tried to reset a slot ID that wasn't enabled,
3544 * or the device wasn't in the addressed or configured state.
3545 */
3546 ret = reset_device_cmd->status;
3547 switch (ret) {
3548 case COMP_CMD_ABORT:
3549 case COMP_CMD_STOP:
3550 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3551 ret = -ETIME;
3552 goto command_cleanup;
3553 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3554 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3555 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3556 slot_id,
3557 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3558 xhci_dbg(xhci, "Not freeing device rings.\n");
3559 /* Don't treat this as an error. May change my mind later. */
3560 ret = 0;
3561 goto command_cleanup;
3562 case COMP_SUCCESS:
3563 xhci_dbg(xhci, "Successful reset device command.\n");
3564 break;
3565 default:
3566 if (xhci_is_vendor_info_code(xhci, ret))
3567 break;
3568 xhci_warn(xhci, "Unknown completion code %u for "
3569 "reset device command.\n", ret);
3570 ret = -EINVAL;
3571 goto command_cleanup;
3572 }
3573
3574 /* Free up host controller endpoint resources */
3575 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3576 spin_lock_irqsave(&xhci->lock, flags);
3577 /* Don't delete the default control endpoint resources */
3578 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3579 spin_unlock_irqrestore(&xhci->lock, flags);
3580 }
3581
3582 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3583 last_freed_endpoint = 1;
3584 for (i = 1; i < 31; ++i) {
3585 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3586
3587 if (ep->ep_state & EP_HAS_STREAMS) {
3588 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3589 xhci_get_endpoint_address(i));
3590 xhci_free_stream_info(xhci, ep->stream_info);
3591 ep->stream_info = NULL;
3592 ep->ep_state &= ~EP_HAS_STREAMS;
3593 }
3594
3595 if (ep->ring) {
3596 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3597 last_freed_endpoint = i;
3598 }
3599 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3600 xhci_drop_ep_from_interval_table(xhci,
3601 &virt_dev->eps[i].bw_info,
3602 virt_dev->bw_table,
3603 udev,
3604 &virt_dev->eps[i],
3605 virt_dev->tt_info);
3606 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3607 }
3608 /* If necessary, update the number of active TTs on this root port */
3609 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3610
3611 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3612 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3613 ret = 0;
3614
3615command_cleanup:
3616 xhci_free_command(xhci, reset_device_cmd);
3617 return ret;
3618}
3619
3620/*
3621 * At this point, the struct usb_device is about to go away, the device has
3622 * disconnected, and all traffic has been stopped and the endpoints have been
3623 * disabled. Free any HC data structures associated with that device.
3624 */
3625void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3626{
3627 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3628 struct xhci_virt_device *virt_dev;
3629 unsigned long flags;
3630 u32 state;
3631 int i, ret;
3632 struct xhci_command *command;
3633
3634 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3635 if (!command)
3636 return;
3637
3638#ifndef CONFIG_USB_DEFAULT_PERSIST
3639 /*
3640 * We called pm_runtime_get_noresume when the device was attached.
3641 * Decrement the counter here to allow controller to runtime suspend
3642 * if no devices remain.
3643 */
3644 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3645 pm_runtime_put_noidle(hcd->self.controller);
3646#endif
3647
3648 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3649 /* If the host is halted due to driver unload, we still need to free the
3650 * device.
3651 */
3652 if (ret <= 0 && ret != -ENODEV) {
3653 kfree(command);
3654 return;
3655 }
3656
3657 virt_dev = xhci->devs[udev->slot_id];
3658
3659 /* Stop any wayward timer functions (which may grab the lock) */
3660 for (i = 0; i < 31; ++i) {
3661 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3662 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3663 }
3664
3665 spin_lock_irqsave(&xhci->lock, flags);
3666 /* Don't disable the slot if the host controller is dead. */
3667 state = readl(&xhci->op_regs->status);
3668 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3669 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3670 xhci_free_virt_device(xhci, udev->slot_id);
3671 spin_unlock_irqrestore(&xhci->lock, flags);
3672 kfree(command);
3673 return;
3674 }
3675
3676 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3677 udev->slot_id)) {
3678 spin_unlock_irqrestore(&xhci->lock, flags);
3679 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3680 return;
3681 }
3682 xhci_ring_cmd_db(xhci);
3683 spin_unlock_irqrestore(&xhci->lock, flags);
3684
3685 /*
3686 * Event command completion handler will free any data structures
3687 * associated with the slot. XXX Can free sleep?
3688 */
3689}
3690
3691/*
3692 * Checks if we have enough host controller resources for the default control
3693 * endpoint.
3694 *
3695 * Must be called with xhci->lock held.
3696 */
3697static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3698{
3699 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3700 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3701 "Not enough ep ctxs: "
3702 "%u active, need to add 1, limit is %u.",
3703 xhci->num_active_eps, xhci->limit_active_eps);
3704 return -ENOMEM;
3705 }
3706 xhci->num_active_eps += 1;
3707 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3708 "Adding 1 ep ctx, %u now active.",
3709 xhci->num_active_eps);
3710 return 0;
3711}
3712
3713
3714/*
3715 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3716 * timed out, or allocating memory failed. Returns 1 on success.
3717 */
3718int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3719{
3720 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3721 unsigned long flags;
3722 int ret, slot_id;
3723 struct xhci_command *command;
3724
3725 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3726 if (!command)
3727 return 0;
3728
3729 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3730 mutex_lock(&xhci->mutex);
3731 spin_lock_irqsave(&xhci->lock, flags);
3732 command->completion = &xhci->addr_dev;
3733 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3734 if (ret) {
3735 spin_unlock_irqrestore(&xhci->lock, flags);
3736 mutex_unlock(&xhci->mutex);
3737 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3738 kfree(command);
3739 return 0;
3740 }
3741 xhci_ring_cmd_db(xhci);
3742 spin_unlock_irqrestore(&xhci->lock, flags);
3743
3744 wait_for_completion(command->completion);
3745 slot_id = xhci->slot_id;
3746 mutex_unlock(&xhci->mutex);
3747
3748 if (!slot_id || command->status != COMP_SUCCESS) {
3749 xhci_err(xhci, "Error while assigning device slot ID\n");
3750 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3751 HCS_MAX_SLOTS(
3752 readl(&xhci->cap_regs->hcs_params1)));
3753 kfree(command);
3754 return 0;
3755 }
3756
3757 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3758 spin_lock_irqsave(&xhci->lock, flags);
3759 ret = xhci_reserve_host_control_ep_resources(xhci);
3760 if (ret) {
3761 spin_unlock_irqrestore(&xhci->lock, flags);
3762 xhci_warn(xhci, "Not enough host resources, "
3763 "active endpoint contexts = %u\n",
3764 xhci->num_active_eps);
3765 goto disable_slot;
3766 }
3767 spin_unlock_irqrestore(&xhci->lock, flags);
3768 }
3769 /* Use GFP_NOIO, since this function can be called from
3770 * xhci_discover_or_reset_device(), which may be called as part of
3771 * mass storage driver error handling.
3772 */
3773 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3774 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3775 goto disable_slot;
3776 }
3777 udev->slot_id = slot_id;
3778
3779#ifndef CONFIG_USB_DEFAULT_PERSIST
3780 /*
3781 * If resetting upon resume, we can't put the controller into runtime
3782 * suspend if there is a device attached.
3783 */
3784 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3785 pm_runtime_get_noresume(hcd->self.controller);
3786#endif
3787
3788
3789 kfree(command);
3790 /* Is this a LS or FS device under a HS hub? */
3791 /* Hub or peripherial? */
3792 return 1;
3793
3794disable_slot:
3795 /* Disable slot, if we can do it without mem alloc */
3796 spin_lock_irqsave(&xhci->lock, flags);
3797 command->completion = NULL;
3798 command->status = 0;
3799 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3800 udev->slot_id))
3801 xhci_ring_cmd_db(xhci);
3802 spin_unlock_irqrestore(&xhci->lock, flags);
3803 return 0;
3804}
3805
3806/*
3807 * Issue an Address Device command and optionally send a corresponding
3808 * SetAddress request to the device.
3809 */
3810static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3811 enum xhci_setup_dev setup)
3812{
3813 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3814 unsigned long flags;
3815 struct xhci_virt_device *virt_dev;
3816 int ret = 0;
3817 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3818 struct xhci_slot_ctx *slot_ctx;
3819 struct xhci_input_control_ctx *ctrl_ctx;
3820 u64 temp_64;
3821 struct xhci_command *command = NULL;
3822
3823 mutex_lock(&xhci->mutex);
3824
3825 if (xhci->xhc_state) /* dying, removing or halted */
3826 goto out;
3827
3828 if (!udev->slot_id) {
3829 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3830 "Bad Slot ID %d", udev->slot_id);
3831 ret = -EINVAL;
3832 goto out;
3833 }
3834
3835 virt_dev = xhci->devs[udev->slot_id];
3836
3837 if (WARN_ON(!virt_dev)) {
3838 /*
3839 * In plug/unplug torture test with an NEC controller,
3840 * a zero-dereference was observed once due to virt_dev = 0.
3841 * Print useful debug rather than crash if it is observed again!
3842 */
3843 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3844 udev->slot_id);
3845 ret = -EINVAL;
3846 goto out;
3847 }
3848
3849 if (setup == SETUP_CONTEXT_ONLY) {
3850 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3851 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3852 SLOT_STATE_DEFAULT) {
3853 xhci_dbg(xhci, "Slot already in default state\n");
3854 goto out;
3855 }
3856 }
3857
3858 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3859 if (!command) {
3860 ret = -ENOMEM;
3861 goto out;
3862 }
3863
3864 command->in_ctx = virt_dev->in_ctx;
3865 command->completion = &xhci->addr_dev;
3866
3867 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3868 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3869 if (!ctrl_ctx) {
3870 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3871 __func__);
3872 ret = -EINVAL;
3873 goto out;
3874 }
3875 /*
3876 * If this is the first Set Address since device plug-in or
3877 * virt_device realloaction after a resume with an xHCI power loss,
3878 * then set up the slot context.
3879 */
3880 if (!slot_ctx->dev_info)
3881 xhci_setup_addressable_virt_dev(xhci, udev);
3882 /* Otherwise, update the control endpoint ring enqueue pointer. */
3883 else
3884 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3885 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3886 ctrl_ctx->drop_flags = 0;
3887
3888 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3889 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3890 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3891 le32_to_cpu(slot_ctx->dev_info) >> 27);
3892
3893 spin_lock_irqsave(&xhci->lock, flags);
3894 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3895 udev->slot_id, setup);
3896 if (ret) {
3897 spin_unlock_irqrestore(&xhci->lock, flags);
3898 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3899 "FIXME: allocate a command ring segment");
3900 goto out;
3901 }
3902 xhci_ring_cmd_db(xhci);
3903 spin_unlock_irqrestore(&xhci->lock, flags);
3904
3905 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3906 wait_for_completion(command->completion);
3907
3908 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3909 * the SetAddress() "recovery interval" required by USB and aborting the
3910 * command on a timeout.
3911 */
3912 switch (command->status) {
3913 case COMP_CMD_ABORT:
3914 case COMP_CMD_STOP:
3915 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3916 ret = -ETIME;
3917 break;
3918 case COMP_CTX_STATE:
3919 case COMP_EBADSLT:
3920 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3921 act, udev->slot_id);
3922 ret = -EINVAL;
3923 break;
3924 case COMP_TX_ERR:
3925 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3926 ret = -EPROTO;
3927 break;
3928 case COMP_DEV_ERR:
3929 dev_warn(&udev->dev,
3930 "ERROR: Incompatible device for setup %s command\n", act);
3931 ret = -ENODEV;
3932 break;
3933 case COMP_SUCCESS:
3934 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3935 "Successful setup %s command", act);
3936 break;
3937 default:
3938 xhci_err(xhci,
3939 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3940 act, command->status);
3941 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3942 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3943 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3944 ret = -EINVAL;
3945 break;
3946 }
3947 if (ret)
3948 goto out;
3949 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3950 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3951 "Op regs DCBAA ptr = %#016llx", temp_64);
3952 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3953 "Slot ID %d dcbaa entry @%p = %#016llx",
3954 udev->slot_id,
3955 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3956 (unsigned long long)
3957 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3958 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3959 "Output Context DMA address = %#08llx",
3960 (unsigned long long)virt_dev->out_ctx->dma);
3961 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3962 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3963 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3964 le32_to_cpu(slot_ctx->dev_info) >> 27);
3965 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3966 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3967 /*
3968 * USB core uses address 1 for the roothubs, so we add one to the
3969 * address given back to us by the HC.
3970 */
3971 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3972 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3973 le32_to_cpu(slot_ctx->dev_info) >> 27);
3974 /* Zero the input context control for later use */
3975 ctrl_ctx->add_flags = 0;
3976 ctrl_ctx->drop_flags = 0;
3977
3978 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3979 "Internal device address = %d",
3980 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3981out:
3982 mutex_unlock(&xhci->mutex);
3983 kfree(command);
3984 return ret;
3985}
3986
3987int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3988{
3989 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3990}
3991
3992int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3993{
3994 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3995}
3996
3997/*
3998 * Transfer the port index into real index in the HW port status
3999 * registers. Caculate offset between the port's PORTSC register
4000 * and port status base. Divide the number of per port register
4001 * to get the real index. The raw port number bases 1.
4002 */
4003int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4004{
4005 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4006 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4007 __le32 __iomem *addr;
4008 int raw_port;
4009
4010 if (hcd->speed < HCD_USB3)
4011 addr = xhci->usb2_ports[port1 - 1];
4012 else
4013 addr = xhci->usb3_ports[port1 - 1];
4014
4015 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4016 return raw_port;
4017}
4018
4019/*
4020 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4021 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4022 */
4023static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4024 struct usb_device *udev, u16 max_exit_latency)
4025{
4026 struct xhci_virt_device *virt_dev;
4027 struct xhci_command *command;
4028 struct xhci_input_control_ctx *ctrl_ctx;
4029 struct xhci_slot_ctx *slot_ctx;
4030 unsigned long flags;
4031 int ret;
4032
4033 spin_lock_irqsave(&xhci->lock, flags);
4034
4035 virt_dev = xhci->devs[udev->slot_id];
4036
4037 /*
4038 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4039 * xHC was re-initialized. Exit latency will be set later after
4040 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4041 */
4042
4043 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4044 spin_unlock_irqrestore(&xhci->lock, flags);
4045 return 0;
4046 }
4047
4048 /* Attempt to issue an Evaluate Context command to change the MEL. */
4049 command = xhci->lpm_command;
4050 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4051 if (!ctrl_ctx) {
4052 spin_unlock_irqrestore(&xhci->lock, flags);
4053 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4054 __func__);
4055 return -ENOMEM;
4056 }
4057
4058 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4059 spin_unlock_irqrestore(&xhci->lock, flags);
4060
4061 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4062 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4063 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4064 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4065 slot_ctx->dev_state = 0;
4066
4067 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4068 "Set up evaluate context for LPM MEL change.");
4069 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4070 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4071
4072 /* Issue and wait for the evaluate context command. */
4073 ret = xhci_configure_endpoint(xhci, udev, command,
4074 true, true);
4075 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4076 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4077
4078 if (!ret) {
4079 spin_lock_irqsave(&xhci->lock, flags);
4080 virt_dev->current_mel = max_exit_latency;
4081 spin_unlock_irqrestore(&xhci->lock, flags);
4082 }
4083 return ret;
4084}
4085
4086#ifdef CONFIG_PM
4087
4088/* BESL to HIRD Encoding array for USB2 LPM */
4089static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4090 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4091
4092/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4093static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4094 struct usb_device *udev)
4095{
4096 int u2del, besl, besl_host;
4097 int besl_device = 0;
4098 u32 field;
4099
4100 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4101 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4102
4103 if (field & USB_BESL_SUPPORT) {
4104 for (besl_host = 0; besl_host < 16; besl_host++) {
4105 if (xhci_besl_encoding[besl_host] >= u2del)
4106 break;
4107 }
4108 /* Use baseline BESL value as default */
4109 if (field & USB_BESL_BASELINE_VALID)
4110 besl_device = USB_GET_BESL_BASELINE(field);
4111 else if (field & USB_BESL_DEEP_VALID)
4112 besl_device = USB_GET_BESL_DEEP(field);
4113 } else {
4114 if (u2del <= 50)
4115 besl_host = 0;
4116 else
4117 besl_host = (u2del - 51) / 75 + 1;
4118 }
4119
4120 besl = besl_host + besl_device;
4121 if (besl > 15)
4122 besl = 15;
4123
4124 return besl;
4125}
4126
4127/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4128static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4129{
4130 u32 field;
4131 int l1;
4132 int besld = 0;
4133 int hirdm = 0;
4134
4135 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4136
4137 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4138 l1 = udev->l1_params.timeout / 256;
4139
4140 /* device has preferred BESLD */
4141 if (field & USB_BESL_DEEP_VALID) {
4142 besld = USB_GET_BESL_DEEP(field);
4143 hirdm = 1;
4144 }
4145
4146 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4147}
4148
4149int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4150 struct usb_device *udev, int enable)
4151{
4152 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4153 __le32 __iomem **port_array;
4154 __le32 __iomem *pm_addr, *hlpm_addr;
4155 u32 pm_val, hlpm_val, field;
4156 unsigned int port_num;
4157 unsigned long flags;
4158 int hird, exit_latency;
4159 int ret;
4160
4161 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4162 !udev->lpm_capable)
4163 return -EPERM;
4164
4165 if (!udev->parent || udev->parent->parent ||
4166 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4167 return -EPERM;
4168
4169 if (udev->usb2_hw_lpm_capable != 1)
4170 return -EPERM;
4171
4172 spin_lock_irqsave(&xhci->lock, flags);
4173
4174 port_array = xhci->usb2_ports;
4175 port_num = udev->portnum - 1;
4176 pm_addr = port_array[port_num] + PORTPMSC;
4177 pm_val = readl(pm_addr);
4178 hlpm_addr = port_array[port_num] + PORTHLPMC;
4179 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4180
4181 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4182 enable ? "enable" : "disable", port_num + 1);
4183
4184 if (enable) {
4185 /* Host supports BESL timeout instead of HIRD */
4186 if (udev->usb2_hw_lpm_besl_capable) {
4187 /* if device doesn't have a preferred BESL value use a
4188 * default one which works with mixed HIRD and BESL
4189 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4190 */
4191 if ((field & USB_BESL_SUPPORT) &&
4192 (field & USB_BESL_BASELINE_VALID))
4193 hird = USB_GET_BESL_BASELINE(field);
4194 else
4195 hird = udev->l1_params.besl;
4196
4197 exit_latency = xhci_besl_encoding[hird];
4198 spin_unlock_irqrestore(&xhci->lock, flags);
4199
4200 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4201 * input context for link powermanagement evaluate
4202 * context commands. It is protected by hcd->bandwidth
4203 * mutex and is shared by all devices. We need to set
4204 * the max ext latency in USB 2 BESL LPM as well, so
4205 * use the same mutex and xhci_change_max_exit_latency()
4206 */
4207 mutex_lock(hcd->bandwidth_mutex);
4208 ret = xhci_change_max_exit_latency(xhci, udev,
4209 exit_latency);
4210 mutex_unlock(hcd->bandwidth_mutex);
4211
4212 if (ret < 0)
4213 return ret;
4214 spin_lock_irqsave(&xhci->lock, flags);
4215
4216 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4217 writel(hlpm_val, hlpm_addr);
4218 /* flush write */
4219 readl(hlpm_addr);
4220 } else {
4221 hird = xhci_calculate_hird_besl(xhci, udev);
4222 }
4223
4224 pm_val &= ~PORT_HIRD_MASK;
4225 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4226 writel(pm_val, pm_addr);
4227 pm_val = readl(pm_addr);
4228 pm_val |= PORT_HLE;
4229 writel(pm_val, pm_addr);
4230 /* flush write */
4231 readl(pm_addr);
4232 } else {
4233 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4234 writel(pm_val, pm_addr);
4235 /* flush write */
4236 readl(pm_addr);
4237 if (udev->usb2_hw_lpm_besl_capable) {
4238 spin_unlock_irqrestore(&xhci->lock, flags);
4239 mutex_lock(hcd->bandwidth_mutex);
4240 xhci_change_max_exit_latency(xhci, udev, 0);
4241 mutex_unlock(hcd->bandwidth_mutex);
4242 return 0;
4243 }
4244 }
4245
4246 spin_unlock_irqrestore(&xhci->lock, flags);
4247 return 0;
4248}
4249
4250/* check if a usb2 port supports a given extened capability protocol
4251 * only USB2 ports extended protocol capability values are cached.
4252 * Return 1 if capability is supported
4253 */
4254static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4255 unsigned capability)
4256{
4257 u32 port_offset, port_count;
4258 int i;
4259
4260 for (i = 0; i < xhci->num_ext_caps; i++) {
4261 if (xhci->ext_caps[i] & capability) {
4262 /* port offsets starts at 1 */
4263 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4264 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4265 if (port >= port_offset &&
4266 port < port_offset + port_count)
4267 return 1;
4268 }
4269 }
4270 return 0;
4271}
4272
4273int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4274{
4275 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4276 int portnum = udev->portnum - 1;
4277
4278 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4279 !udev->lpm_capable)
4280 return 0;
4281
4282 /* we only support lpm for non-hub device connected to root hub yet */
4283 if (!udev->parent || udev->parent->parent ||
4284 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4285 return 0;
4286
4287 if (xhci->hw_lpm_support == 1 &&
4288 xhci_check_usb2_port_capability(
4289 xhci, portnum, XHCI_HLC)) {
4290 udev->usb2_hw_lpm_capable = 1;
4291 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4292 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4293 if (xhci_check_usb2_port_capability(xhci, portnum,
4294 XHCI_BLC))
4295 udev->usb2_hw_lpm_besl_capable = 1;
4296 }
4297
4298 return 0;
4299}
4300
4301/*---------------------- USB 3.0 Link PM functions ------------------------*/
4302
4303/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4304static unsigned long long xhci_service_interval_to_ns(
4305 struct usb_endpoint_descriptor *desc)
4306{
4307 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4308}
4309
4310static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4311 enum usb3_link_state state)
4312{
4313 unsigned long long sel;
4314 unsigned long long pel;
4315 unsigned int max_sel_pel;
4316 char *state_name;
4317
4318 switch (state) {
4319 case USB3_LPM_U1:
4320 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4321 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4322 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4323 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4324 state_name = "U1";
4325 break;
4326 case USB3_LPM_U2:
4327 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4328 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4329 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4330 state_name = "U2";
4331 break;
4332 default:
4333 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4334 __func__);
4335 return USB3_LPM_DISABLED;
4336 }
4337
4338 if (sel <= max_sel_pel && pel <= max_sel_pel)
4339 return USB3_LPM_DEVICE_INITIATED;
4340
4341 if (sel > max_sel_pel)
4342 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4343 "due to long SEL %llu ms\n",
4344 state_name, sel);
4345 else
4346 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4347 "due to long PEL %llu ms\n",
4348 state_name, pel);
4349 return USB3_LPM_DISABLED;
4350}
4351
4352/* The U1 timeout should be the maximum of the following values:
4353 * - For control endpoints, U1 system exit latency (SEL) * 3
4354 * - For bulk endpoints, U1 SEL * 5
4355 * - For interrupt endpoints:
4356 * - Notification EPs, U1 SEL * 3
4357 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4358 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4359 */
4360static unsigned long long xhci_calculate_intel_u1_timeout(
4361 struct usb_device *udev,
4362 struct usb_endpoint_descriptor *desc)
4363{
4364 unsigned long long timeout_ns;
4365 int ep_type;
4366 int intr_type;
4367
4368 ep_type = usb_endpoint_type(desc);
4369 switch (ep_type) {
4370 case USB_ENDPOINT_XFER_CONTROL:
4371 timeout_ns = udev->u1_params.sel * 3;
4372 break;
4373 case USB_ENDPOINT_XFER_BULK:
4374 timeout_ns = udev->u1_params.sel * 5;
4375 break;
4376 case USB_ENDPOINT_XFER_INT:
4377 intr_type = usb_endpoint_interrupt_type(desc);
4378 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4379 timeout_ns = udev->u1_params.sel * 3;
4380 break;
4381 }
4382 /* Otherwise the calculation is the same as isoc eps */
4383 case USB_ENDPOINT_XFER_ISOC:
4384 timeout_ns = xhci_service_interval_to_ns(desc);
4385 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4386 if (timeout_ns < udev->u1_params.sel * 2)
4387 timeout_ns = udev->u1_params.sel * 2;
4388 break;
4389 default:
4390 return 0;
4391 }
4392
4393 return timeout_ns;
4394}
4395
4396/* Returns the hub-encoded U1 timeout value. */
4397static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4398 struct usb_device *udev,
4399 struct usb_endpoint_descriptor *desc)
4400{
4401 unsigned long long timeout_ns;
4402
4403 if (xhci->quirks & XHCI_INTEL_HOST)
4404 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4405 else
4406 timeout_ns = udev->u1_params.sel;
4407
4408 /* The U1 timeout is encoded in 1us intervals.
4409 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4410 */
4411 if (timeout_ns == USB3_LPM_DISABLED)
4412 timeout_ns = 1;
4413 else
4414 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4415
4416 /* If the necessary timeout value is bigger than what we can set in the
4417 * USB 3.0 hub, we have to disable hub-initiated U1.
4418 */
4419 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4420 return timeout_ns;
4421 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4422 "due to long timeout %llu ms\n", timeout_ns);
4423 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4424}
4425
4426/* The U2 timeout should be the maximum of:
4427 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4428 * - largest bInterval of any active periodic endpoint (to avoid going
4429 * into lower power link states between intervals).
4430 * - the U2 Exit Latency of the device
4431 */
4432static unsigned long long xhci_calculate_intel_u2_timeout(
4433 struct usb_device *udev,
4434 struct usb_endpoint_descriptor *desc)
4435{
4436 unsigned long long timeout_ns;
4437 unsigned long long u2_del_ns;
4438
4439 timeout_ns = 10 * 1000 * 1000;
4440
4441 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4442 (xhci_service_interval_to_ns(desc) > timeout_ns))
4443 timeout_ns = xhci_service_interval_to_ns(desc);
4444
4445 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4446 if (u2_del_ns > timeout_ns)
4447 timeout_ns = u2_del_ns;
4448
4449 return timeout_ns;
4450}
4451
4452/* Returns the hub-encoded U2 timeout value. */
4453static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4454 struct usb_device *udev,
4455 struct usb_endpoint_descriptor *desc)
4456{
4457 unsigned long long timeout_ns;
4458
4459 if (xhci->quirks & XHCI_INTEL_HOST)
4460 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4461 else
4462 timeout_ns = udev->u2_params.sel;
4463
4464 /* The U2 timeout is encoded in 256us intervals */
4465 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4466 /* If the necessary timeout value is bigger than what we can set in the
4467 * USB 3.0 hub, we have to disable hub-initiated U2.
4468 */
4469 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4470 return timeout_ns;
4471 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4472 "due to long timeout %llu ms\n", timeout_ns);
4473 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4474}
4475
4476static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4477 struct usb_device *udev,
4478 struct usb_endpoint_descriptor *desc,
4479 enum usb3_link_state state,
4480 u16 *timeout)
4481{
4482 if (state == USB3_LPM_U1)
4483 return xhci_calculate_u1_timeout(xhci, udev, desc);
4484 else if (state == USB3_LPM_U2)
4485 return xhci_calculate_u2_timeout(xhci, udev, desc);
4486
4487 return USB3_LPM_DISABLED;
4488}
4489
4490static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4491 struct usb_device *udev,
4492 struct usb_endpoint_descriptor *desc,
4493 enum usb3_link_state state,
4494 u16 *timeout)
4495{
4496 u16 alt_timeout;
4497
4498 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4499 desc, state, timeout);
4500
4501 /* If we found we can't enable hub-initiated LPM, or
4502 * the U1 or U2 exit latency was too high to allow
4503 * device-initiated LPM as well, just stop searching.
4504 */
4505 if (alt_timeout == USB3_LPM_DISABLED ||
4506 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4507 *timeout = alt_timeout;
4508 return -E2BIG;
4509 }
4510 if (alt_timeout > *timeout)
4511 *timeout = alt_timeout;
4512 return 0;
4513}
4514
4515static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4516 struct usb_device *udev,
4517 struct usb_host_interface *alt,
4518 enum usb3_link_state state,
4519 u16 *timeout)
4520{
4521 int j;
4522
4523 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4524 if (xhci_update_timeout_for_endpoint(xhci, udev,
4525 &alt->endpoint[j].desc, state, timeout))
4526 return -E2BIG;
4527 continue;
4528 }
4529 return 0;
4530}
4531
4532static int xhci_check_intel_tier_policy(struct usb_device *udev,
4533 enum usb3_link_state state)
4534{
4535 struct usb_device *parent;
4536 unsigned int num_hubs;
4537
4538 if (state == USB3_LPM_U2)
4539 return 0;
4540
4541 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4542 for (parent = udev->parent, num_hubs = 0; parent->parent;
4543 parent = parent->parent)
4544 num_hubs++;
4545
4546 if (num_hubs < 2)
4547 return 0;
4548
4549 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4550 " below second-tier hub.\n");
4551 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4552 "to decrease power consumption.\n");
4553 return -E2BIG;
4554}
4555
4556static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4557 struct usb_device *udev,
4558 enum usb3_link_state state)
4559{
4560 if (xhci->quirks & XHCI_INTEL_HOST)
4561 return xhci_check_intel_tier_policy(udev, state);
4562 else
4563 return 0;
4564}
4565
4566/* Returns the U1 or U2 timeout that should be enabled.
4567 * If the tier check or timeout setting functions return with a non-zero exit
4568 * code, that means the timeout value has been finalized and we shouldn't look
4569 * at any more endpoints.
4570 */
4571static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4572 struct usb_device *udev, enum usb3_link_state state)
4573{
4574 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4575 struct usb_host_config *config;
4576 char *state_name;
4577 int i;
4578 u16 timeout = USB3_LPM_DISABLED;
4579
4580 if (state == USB3_LPM_U1)
4581 state_name = "U1";
4582 else if (state == USB3_LPM_U2)
4583 state_name = "U2";
4584 else {
4585 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4586 state);
4587 return timeout;
4588 }
4589
4590 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4591 return timeout;
4592
4593 /* Gather some information about the currently installed configuration
4594 * and alternate interface settings.
4595 */
4596 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4597 state, &timeout))
4598 return timeout;
4599
4600 config = udev->actconfig;
4601 if (!config)
4602 return timeout;
4603
4604 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4605 struct usb_driver *driver;
4606 struct usb_interface *intf = config->interface[i];
4607
4608 if (!intf)
4609 continue;
4610
4611 /* Check if any currently bound drivers want hub-initiated LPM
4612 * disabled.
4613 */
4614 if (intf->dev.driver) {
4615 driver = to_usb_driver(intf->dev.driver);
4616 if (driver && driver->disable_hub_initiated_lpm) {
4617 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4618 "at request of driver %s\n",
4619 state_name, driver->name);
4620 return xhci_get_timeout_no_hub_lpm(udev, state);
4621 }
4622 }
4623
4624 /* Not sure how this could happen... */
4625 if (!intf->cur_altsetting)
4626 continue;
4627
4628 if (xhci_update_timeout_for_interface(xhci, udev,
4629 intf->cur_altsetting,
4630 state, &timeout))
4631 return timeout;
4632 }
4633 return timeout;
4634}
4635
4636static int calculate_max_exit_latency(struct usb_device *udev,
4637 enum usb3_link_state state_changed,
4638 u16 hub_encoded_timeout)
4639{
4640 unsigned long long u1_mel_us = 0;
4641 unsigned long long u2_mel_us = 0;
4642 unsigned long long mel_us = 0;
4643 bool disabling_u1;
4644 bool disabling_u2;
4645 bool enabling_u1;
4646 bool enabling_u2;
4647
4648 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4649 hub_encoded_timeout == USB3_LPM_DISABLED);
4650 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4651 hub_encoded_timeout == USB3_LPM_DISABLED);
4652
4653 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4654 hub_encoded_timeout != USB3_LPM_DISABLED);
4655 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4656 hub_encoded_timeout != USB3_LPM_DISABLED);
4657
4658 /* If U1 was already enabled and we're not disabling it,
4659 * or we're going to enable U1, account for the U1 max exit latency.
4660 */
4661 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4662 enabling_u1)
4663 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4664 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4665 enabling_u2)
4666 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4667
4668 if (u1_mel_us > u2_mel_us)
4669 mel_us = u1_mel_us;
4670 else
4671 mel_us = u2_mel_us;
4672 /* xHCI host controller max exit latency field is only 16 bits wide. */
4673 if (mel_us > MAX_EXIT) {
4674 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4675 "is too big.\n", mel_us);
4676 return -E2BIG;
4677 }
4678 return mel_us;
4679}
4680
4681/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4682int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4683 struct usb_device *udev, enum usb3_link_state state)
4684{
4685 struct xhci_hcd *xhci;
4686 u16 hub_encoded_timeout;
4687 int mel;
4688 int ret;
4689
4690 xhci = hcd_to_xhci(hcd);
4691 /* The LPM timeout values are pretty host-controller specific, so don't
4692 * enable hub-initiated timeouts unless the vendor has provided
4693 * information about their timeout algorithm.
4694 */
4695 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4696 !xhci->devs[udev->slot_id])
4697 return USB3_LPM_DISABLED;
4698
4699 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4700 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4701 if (mel < 0) {
4702 /* Max Exit Latency is too big, disable LPM. */
4703 hub_encoded_timeout = USB3_LPM_DISABLED;
4704 mel = 0;
4705 }
4706
4707 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4708 if (ret)
4709 return ret;
4710 return hub_encoded_timeout;
4711}
4712
4713int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4714 struct usb_device *udev, enum usb3_link_state state)
4715{
4716 struct xhci_hcd *xhci;
4717 u16 mel;
4718
4719 xhci = hcd_to_xhci(hcd);
4720 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4721 !xhci->devs[udev->slot_id])
4722 return 0;
4723
4724 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4725 return xhci_change_max_exit_latency(xhci, udev, mel);
4726}
4727#else /* CONFIG_PM */
4728
4729int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4730 struct usb_device *udev, int enable)
4731{
4732 return 0;
4733}
4734
4735int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4736{
4737 return 0;
4738}
4739
4740int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4741 struct usb_device *udev, enum usb3_link_state state)
4742{
4743 return USB3_LPM_DISABLED;
4744}
4745
4746int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4747 struct usb_device *udev, enum usb3_link_state state)
4748{
4749 return 0;
4750}
4751#endif /* CONFIG_PM */
4752
4753/*-------------------------------------------------------------------------*/
4754
4755/* Once a hub descriptor is fetched for a device, we need to update the xHC's
4756 * internal data structures for the device.
4757 */
4758int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4759 struct usb_tt *tt, gfp_t mem_flags)
4760{
4761 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4762 struct xhci_virt_device *vdev;
4763 struct xhci_command *config_cmd;
4764 struct xhci_input_control_ctx *ctrl_ctx;
4765 struct xhci_slot_ctx *slot_ctx;
4766 unsigned long flags;
4767 unsigned think_time;
4768 int ret;
4769
4770 /* Ignore root hubs */
4771 if (!hdev->parent)
4772 return 0;
4773
4774 vdev = xhci->devs[hdev->slot_id];
4775 if (!vdev) {
4776 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4777 return -EINVAL;
4778 }
4779 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4780 if (!config_cmd) {
4781 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4782 return -ENOMEM;
4783 }
4784 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4785 if (!ctrl_ctx) {
4786 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4787 __func__);
4788 xhci_free_command(xhci, config_cmd);
4789 return -ENOMEM;
4790 }
4791
4792 spin_lock_irqsave(&xhci->lock, flags);
4793 if (hdev->speed == USB_SPEED_HIGH &&
4794 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4795 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4796 xhci_free_command(xhci, config_cmd);
4797 spin_unlock_irqrestore(&xhci->lock, flags);
4798 return -ENOMEM;
4799 }
4800
4801 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4802 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4803 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4804 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4805 /*
4806 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4807 * but it may be already set to 1 when setup an xHCI virtual
4808 * device, so clear it anyway.
4809 */
4810 if (tt->multi)
4811 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4812 else if (hdev->speed == USB_SPEED_FULL)
4813 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4814
4815 if (xhci->hci_version > 0x95) {
4816 xhci_dbg(xhci, "xHCI version %x needs hub "
4817 "TT think time and number of ports\n",
4818 (unsigned int) xhci->hci_version);
4819 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4820 /* Set TT think time - convert from ns to FS bit times.
4821 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4822 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4823 *
4824 * xHCI 1.0: this field shall be 0 if the device is not a
4825 * High-spped hub.
4826 */
4827 think_time = tt->think_time;
4828 if (think_time != 0)
4829 think_time = (think_time / 666) - 1;
4830 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4831 slot_ctx->tt_info |=
4832 cpu_to_le32(TT_THINK_TIME(think_time));
4833 } else {
4834 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4835 "TT think time or number of ports\n",
4836 (unsigned int) xhci->hci_version);
4837 }
4838 slot_ctx->dev_state = 0;
4839 spin_unlock_irqrestore(&xhci->lock, flags);
4840
4841 xhci_dbg(xhci, "Set up %s for hub device.\n",
4842 (xhci->hci_version > 0x95) ?
4843 "configure endpoint" : "evaluate context");
4844 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4845 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4846
4847 /* Issue and wait for the configure endpoint or
4848 * evaluate context command.
4849 */
4850 if (xhci->hci_version > 0x95)
4851 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4852 false, false);
4853 else
4854 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4855 true, false);
4856
4857 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4858 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4859
4860 xhci_free_command(xhci, config_cmd);
4861 return ret;
4862}
4863
4864int xhci_get_frame(struct usb_hcd *hcd)
4865{
4866 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4867 /* EHCI mods by the periodic size. Why? */
4868 return readl(&xhci->run_regs->microframe_index) >> 3;
4869}
4870
4871int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4872{
4873 struct xhci_hcd *xhci;
4874 struct device *dev = hcd->self.controller;
4875 int retval;
4876
4877 /* Accept arbitrarily long scatter-gather lists */
4878 hcd->self.sg_tablesize = ~0;
4879
4880 /* support to build packet from discontinuous buffers */
4881 hcd->self.no_sg_constraint = 1;
4882
4883 /* XHCI controllers don't stop the ep queue on short packets :| */
4884 hcd->self.no_stop_on_short = 1;
4885
4886 xhci = hcd_to_xhci(hcd);
4887
4888 if (usb_hcd_is_primary_hcd(hcd)) {
4889 xhci->main_hcd = hcd;
4890 /* Mark the first roothub as being USB 2.0.
4891 * The xHCI driver will register the USB 3.0 roothub.
4892 */
4893 hcd->speed = HCD_USB2;
4894 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4895 /*
4896 * USB 2.0 roothub under xHCI has an integrated TT,
4897 * (rate matching hub) as opposed to having an OHCI/UHCI
4898 * companion controller.
4899 */
4900 hcd->has_tt = 1;
4901 } else {
4902 if (xhci->sbrn == 0x31) {
4903 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4904 hcd->speed = HCD_USB31;
4905 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4906 }
4907 /* xHCI private pointer was set in xhci_pci_probe for the second
4908 * registered roothub.
4909 */
4910 return 0;
4911 }
4912
4913 mutex_init(&xhci->mutex);
4914 xhci->cap_regs = hcd->regs;
4915 xhci->op_regs = hcd->regs +
4916 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4917 xhci->run_regs = hcd->regs +
4918 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4919 /* Cache read-only capability registers */
4920 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4921 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4922 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4923 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4924 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4925 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4926 if (xhci->hci_version > 0x100)
4927 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4928 xhci_print_registers(xhci);
4929
4930 xhci->quirks = quirks;
4931
4932 get_quirks(dev, xhci);
4933
4934 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4935 * success event after a short transfer. This quirk will ignore such
4936 * spurious event.
4937 */
4938 if (xhci->hci_version > 0x96)
4939 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4940
4941 /* Make sure the HC is halted. */
4942 retval = xhci_halt(xhci);
4943 if (retval)
4944 return retval;
4945
4946 xhci_dbg(xhci, "Resetting HCD\n");
4947 /* Reset the internal HC memory state and registers. */
4948 retval = xhci_reset(xhci);
4949 if (retval)
4950 return retval;
4951 xhci_dbg(xhci, "Reset complete\n");
4952
4953 /*
4954 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4955 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4956 * address memory pointers actually. So, this driver clears the AC64
4957 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4958 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4959 */
4960 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4961 xhci->hcc_params &= ~BIT(0);
4962
4963 /* Set dma_mask and coherent_dma_mask to 64-bits,
4964 * if xHC supports 64-bit addressing */
4965 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4966 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4967 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4968 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4969 } else {
4970 /*
4971 * This is to avoid error in cases where a 32-bit USB
4972 * controller is used on a 64-bit capable system.
4973 */
4974 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4975 if (retval)
4976 return retval;
4977 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4978 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4979 }
4980
4981 xhci_dbg(xhci, "Calling HCD init\n");
4982 /* Initialize HCD and host controller data structures. */
4983 retval = xhci_init(hcd);
4984 if (retval)
4985 return retval;
4986 xhci_dbg(xhci, "Called HCD init\n");
4987
4988 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4989 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4990
4991 return 0;
4992}
4993EXPORT_SYMBOL_GPL(xhci_gen_setup);
4994
4995static const struct hc_driver xhci_hc_driver = {
4996 .description = "xhci-hcd",
4997 .product_desc = "xHCI Host Controller",
4998 .hcd_priv_size = sizeof(struct xhci_hcd),
4999
5000 /*
5001 * generic hardware linkage
5002 */
5003 .irq = xhci_irq,
5004 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5005
5006 /*
5007 * basic lifecycle operations
5008 */
5009 .reset = NULL, /* set in xhci_init_driver() */
5010 .start = xhci_run,
5011 .stop = xhci_stop,
5012 .shutdown = xhci_shutdown,
5013
5014 /*
5015 * managing i/o requests and associated device resources
5016 */
5017 .urb_enqueue = xhci_urb_enqueue,
5018 .urb_dequeue = xhci_urb_dequeue,
5019 .alloc_dev = xhci_alloc_dev,
5020 .free_dev = xhci_free_dev,
5021 .alloc_streams = xhci_alloc_streams,
5022 .free_streams = xhci_free_streams,
5023 .add_endpoint = xhci_add_endpoint,
5024 .drop_endpoint = xhci_drop_endpoint,
5025 .endpoint_reset = xhci_endpoint_reset,
5026 .check_bandwidth = xhci_check_bandwidth,
5027 .reset_bandwidth = xhci_reset_bandwidth,
5028 .address_device = xhci_address_device,
5029 .enable_device = xhci_enable_device,
5030 .update_hub_device = xhci_update_hub_device,
5031 .reset_device = xhci_discover_or_reset_device,
5032
5033 /*
5034 * scheduling support
5035 */
5036 .get_frame_number = xhci_get_frame,
5037
5038 /*
5039 * root hub support
5040 */
5041 .hub_control = xhci_hub_control,
5042 .hub_status_data = xhci_hub_status_data,
5043 .bus_suspend = xhci_bus_suspend,
5044 .bus_resume = xhci_bus_resume,
5045
5046 /*
5047 * call back when device connected and addressed
5048 */
5049 .update_device = xhci_update_device,
5050 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5051 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5052 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5053 .find_raw_port_number = xhci_find_raw_port_number,
5054};
5055
5056void xhci_init_driver(struct hc_driver *drv,
5057 const struct xhci_driver_overrides *over)
5058{
5059 BUG_ON(!over);
5060
5061 /* Copy the generic table to drv then apply the overrides */
5062 *drv = xhci_hc_driver;
5063
5064 if (over) {
5065 drv->hcd_priv_size += over->extra_priv_size;
5066 if (over->reset)
5067 drv->reset = over->reset;
5068 if (over->start)
5069 drv->start = over->start;
5070 }
5071}
5072EXPORT_SYMBOL_GPL(xhci_init_driver);
5073
5074MODULE_DESCRIPTION(DRIVER_DESC);
5075MODULE_AUTHOR(DRIVER_AUTHOR);
5076MODULE_LICENSE("GPL");
5077
5078static int __init xhci_hcd_init(void)
5079{
5080 /*
5081 * Check the compiler generated sizes of structures that must be laid
5082 * out in specific ways for hardware access.
5083 */
5084 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5085 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5086 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5087 /* xhci_device_control has eight fields, and also
5088 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5089 */
5090 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5091 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5092 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5093 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5094 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5095 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5096 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5097
5098 if (usb_disabled())
5099 return -ENODEV;
5100
5101 return 0;
5102}
5103
5104/*
5105 * If an init function is provided, an exit function must also be provided
5106 * to allow module unload.
5107 */
5108static void __exit xhci_hcd_fini(void) { }
5109
5110module_init(xhci_hcd_init);
5111module_exit(xhci_hcd_fini);