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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
4 */
5#include <linux/sched/task_stack.h>
6#include <linux/vmalloc.h>
7
8#include <asm/fpu/api.h>
9#include <asm/fpu/signal.h>
10#include <asm/fpu/regset.h>
11
12#include "context.h"
13#include "internal.h"
14#include "legacy.h"
15#include "xstate.h"
16
17/*
18 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
19 * as the "regset->n" for the xstate regset will be updated based on the feature
20 * capabilities supported by the xsave.
21 */
22int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
23{
24 return regset->n;
25}
26
27int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
28{
29 if (boot_cpu_has(X86_FEATURE_FXSR))
30 return regset->n;
31 else
32 return 0;
33}
34
35/*
36 * The regset get() functions are invoked from:
37 *
38 * - coredump to dump the current task's fpstate. If the current task
39 * owns the FPU then the memory state has to be synchronized and the
40 * FPU register state preserved. Otherwise fpstate is already in sync.
41 *
42 * - ptrace to dump fpstate of a stopped task, in which case the registers
43 * have already been saved to fpstate on context switch.
44 */
45static void sync_fpstate(struct fpu *fpu)
46{
47 if (fpu == ¤t->thread.fpu)
48 fpu_sync_fpstate(fpu);
49}
50
51/*
52 * Invalidate cached FPU registers before modifying the stopped target
53 * task's fpstate.
54 *
55 * This forces the target task on resume to restore the FPU registers from
56 * modified fpstate. Otherwise the task might skip the restore and operate
57 * with the cached FPU registers which discards the modifications.
58 */
59static void fpu_force_restore(struct fpu *fpu)
60{
61 /*
62 * Only stopped child tasks can be used to modify the FPU
63 * state in the fpstate buffer:
64 */
65 WARN_ON_FPU(fpu == ¤t->thread.fpu);
66
67 __fpu_invalidate_fpregs_state(fpu);
68}
69
70int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
71 struct membuf to)
72{
73 struct fpu *fpu = &target->thread.fpu;
74
75 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
76 return -ENODEV;
77
78 sync_fpstate(fpu);
79
80 if (!use_xsave()) {
81 return membuf_write(&to, &fpu->fpstate->regs.fxsave,
82 sizeof(fpu->fpstate->regs.fxsave));
83 }
84
85 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
86 return 0;
87}
88
89int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
90 unsigned int pos, unsigned int count,
91 const void *kbuf, const void __user *ubuf)
92{
93 struct fpu *fpu = &target->thread.fpu;
94 struct fxregs_state newstate;
95 int ret;
96
97 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
98 return -ENODEV;
99
100 /* No funny business with partial or oversized writes is permitted. */
101 if (pos != 0 || count != sizeof(newstate))
102 return -EINVAL;
103
104 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
105 if (ret)
106 return ret;
107
108 /* Do not allow an invalid MXCSR value. */
109 if (newstate.mxcsr & ~mxcsr_feature_mask)
110 return -EINVAL;
111
112 fpu_force_restore(fpu);
113
114 /* Copy the state */
115 memcpy(&fpu->fpstate->regs.fxsave, &newstate, sizeof(newstate));
116
117 /* Clear xmm8..15 for 32-bit callers */
118 BUILD_BUG_ON(sizeof(fpu->__fpstate.regs.fxsave.xmm_space) != 16 * 16);
119 if (in_ia32_syscall())
120 memset(&fpu->fpstate->regs.fxsave.xmm_space[8*4], 0, 8 * 16);
121
122 /* Mark FP and SSE as in use when XSAVE is enabled */
123 if (use_xsave())
124 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
125
126 return 0;
127}
128
129int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
130 struct membuf to)
131{
132 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
133 return -ENODEV;
134
135 sync_fpstate(&target->thread.fpu);
136
137 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
138 return 0;
139}
140
141int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
142 unsigned int pos, unsigned int count,
143 const void *kbuf, const void __user *ubuf)
144{
145 struct fpu *fpu = &target->thread.fpu;
146 struct xregs_state *tmpbuf = NULL;
147 int ret;
148
149 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
150 return -ENODEV;
151
152 /*
153 * A whole standard-format XSAVE buffer is needed:
154 */
155 if (pos != 0 || count != fpu_user_cfg.max_size)
156 return -EFAULT;
157
158 if (!kbuf) {
159 tmpbuf = vmalloc(count);
160 if (!tmpbuf)
161 return -ENOMEM;
162
163 if (copy_from_user(tmpbuf, ubuf, count)) {
164 ret = -EFAULT;
165 goto out;
166 }
167 }
168
169 fpu_force_restore(fpu);
170 ret = copy_uabi_from_kernel_to_xstate(fpu->fpstate, kbuf ?: tmpbuf, &target->thread.pkru);
171
172out:
173 vfree(tmpbuf);
174 return ret;
175}
176
177#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
178
179/*
180 * FPU tag word conversions.
181 */
182
183static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
184{
185 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
186
187 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
188 tmp = ~twd;
189 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
190 /* and move the valid bits to the lower byte. */
191 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
192 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
193 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
194
195 return tmp;
196}
197
198#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
199#define FP_EXP_TAG_VALID 0
200#define FP_EXP_TAG_ZERO 1
201#define FP_EXP_TAG_SPECIAL 2
202#define FP_EXP_TAG_EMPTY 3
203
204static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
205{
206 struct _fpxreg *st;
207 u32 tos = (fxsave->swd >> 11) & 7;
208 u32 twd = (unsigned long) fxsave->twd;
209 u32 tag;
210 u32 ret = 0xffff0000u;
211 int i;
212
213 for (i = 0; i < 8; i++, twd >>= 1) {
214 if (twd & 0x1) {
215 st = FPREG_ADDR(fxsave, (i - tos) & 7);
216
217 switch (st->exponent & 0x7fff) {
218 case 0x7fff:
219 tag = FP_EXP_TAG_SPECIAL;
220 break;
221 case 0x0000:
222 if (!st->significand[0] &&
223 !st->significand[1] &&
224 !st->significand[2] &&
225 !st->significand[3])
226 tag = FP_EXP_TAG_ZERO;
227 else
228 tag = FP_EXP_TAG_SPECIAL;
229 break;
230 default:
231 if (st->significand[3] & 0x8000)
232 tag = FP_EXP_TAG_VALID;
233 else
234 tag = FP_EXP_TAG_SPECIAL;
235 break;
236 }
237 } else {
238 tag = FP_EXP_TAG_EMPTY;
239 }
240 ret |= tag << (2 * i);
241 }
242 return ret;
243}
244
245/*
246 * FXSR floating point environment conversions.
247 */
248
249static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
250 struct task_struct *tsk,
251 struct fxregs_state *fxsave)
252{
253 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
254 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
255 int i;
256
257 env->cwd = fxsave->cwd | 0xffff0000u;
258 env->swd = fxsave->swd | 0xffff0000u;
259 env->twd = twd_fxsr_to_i387(fxsave);
260
261#ifdef CONFIG_X86_64
262 env->fip = fxsave->rip;
263 env->foo = fxsave->rdp;
264 /*
265 * should be actually ds/cs at fpu exception time, but
266 * that information is not available in 64bit mode.
267 */
268 env->fcs = task_pt_regs(tsk)->cs;
269 if (tsk == current) {
270 savesegment(ds, env->fos);
271 } else {
272 env->fos = tsk->thread.ds;
273 }
274 env->fos |= 0xffff0000;
275#else
276 env->fip = fxsave->fip;
277 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
278 env->foo = fxsave->foo;
279 env->fos = fxsave->fos;
280#endif
281
282 for (i = 0; i < 8; ++i)
283 memcpy(&to[i], &from[i], sizeof(to[0]));
284}
285
286void
287convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
288{
289 __convert_from_fxsr(env, tsk, &tsk->thread.fpu.fpstate->regs.fxsave);
290}
291
292void convert_to_fxsr(struct fxregs_state *fxsave,
293 const struct user_i387_ia32_struct *env)
294
295{
296 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
297 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
298 int i;
299
300 fxsave->cwd = env->cwd;
301 fxsave->swd = env->swd;
302 fxsave->twd = twd_i387_to_fxsr(env->twd);
303 fxsave->fop = (u16) ((u32) env->fcs >> 16);
304#ifdef CONFIG_X86_64
305 fxsave->rip = env->fip;
306 fxsave->rdp = env->foo;
307 /* cs and ds ignored */
308#else
309 fxsave->fip = env->fip;
310 fxsave->fcs = (env->fcs & 0xffff);
311 fxsave->foo = env->foo;
312 fxsave->fos = env->fos;
313#endif
314
315 for (i = 0; i < 8; ++i)
316 memcpy(&to[i], &from[i], sizeof(from[0]));
317}
318
319int fpregs_get(struct task_struct *target, const struct user_regset *regset,
320 struct membuf to)
321{
322 struct fpu *fpu = &target->thread.fpu;
323 struct user_i387_ia32_struct env;
324 struct fxregs_state fxsave, *fx;
325
326 sync_fpstate(fpu);
327
328 if (!cpu_feature_enabled(X86_FEATURE_FPU))
329 return fpregs_soft_get(target, regset, to);
330
331 if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
332 return membuf_write(&to, &fpu->fpstate->regs.fsave,
333 sizeof(struct fregs_state));
334 }
335
336 if (use_xsave()) {
337 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
338
339 /* Handle init state optimized xstate correctly */
340 copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
341 fx = &fxsave;
342 } else {
343 fx = &fpu->fpstate->regs.fxsave;
344 }
345
346 __convert_from_fxsr(&env, target, fx);
347 return membuf_write(&to, &env, sizeof(env));
348}
349
350int fpregs_set(struct task_struct *target, const struct user_regset *regset,
351 unsigned int pos, unsigned int count,
352 const void *kbuf, const void __user *ubuf)
353{
354 struct fpu *fpu = &target->thread.fpu;
355 struct user_i387_ia32_struct env;
356 int ret;
357
358 /* No funny business with partial or oversized writes is permitted. */
359 if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
360 return -EINVAL;
361
362 if (!cpu_feature_enabled(X86_FEATURE_FPU))
363 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
364
365 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
366 if (ret)
367 return ret;
368
369 fpu_force_restore(fpu);
370
371 if (cpu_feature_enabled(X86_FEATURE_FXSR))
372 convert_to_fxsr(&fpu->fpstate->regs.fxsave, &env);
373 else
374 memcpy(&fpu->fpstate->regs.fsave, &env, sizeof(env));
375
376 /*
377 * Update the header bit in the xsave header, indicating the
378 * presence of FP.
379 */
380 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
381 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FP;
382
383 return 0;
384}
385
386#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
4 */
5#include <linux/sched/task_stack.h>
6#include <linux/vmalloc.h>
7
8#include <asm/fpu/api.h>
9#include <asm/fpu/signal.h>
10#include <asm/fpu/regset.h>
11#include <asm/prctl.h>
12
13#include "context.h"
14#include "internal.h"
15#include "legacy.h"
16#include "xstate.h"
17
18/*
19 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
20 * as the "regset->n" for the xstate regset will be updated based on the feature
21 * capabilities supported by the xsave.
22 */
23int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
24{
25 return regset->n;
26}
27
28int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
29{
30 if (boot_cpu_has(X86_FEATURE_FXSR))
31 return regset->n;
32 else
33 return 0;
34}
35
36/*
37 * The regset get() functions are invoked from:
38 *
39 * - coredump to dump the current task's fpstate. If the current task
40 * owns the FPU then the memory state has to be synchronized and the
41 * FPU register state preserved. Otherwise fpstate is already in sync.
42 *
43 * - ptrace to dump fpstate of a stopped task, in which case the registers
44 * have already been saved to fpstate on context switch.
45 */
46static void sync_fpstate(struct fpu *fpu)
47{
48 if (fpu == ¤t->thread.fpu)
49 fpu_sync_fpstate(fpu);
50}
51
52/*
53 * Invalidate cached FPU registers before modifying the stopped target
54 * task's fpstate.
55 *
56 * This forces the target task on resume to restore the FPU registers from
57 * modified fpstate. Otherwise the task might skip the restore and operate
58 * with the cached FPU registers which discards the modifications.
59 */
60static void fpu_force_restore(struct fpu *fpu)
61{
62 /*
63 * Only stopped child tasks can be used to modify the FPU
64 * state in the fpstate buffer:
65 */
66 WARN_ON_FPU(fpu == ¤t->thread.fpu);
67
68 __fpu_invalidate_fpregs_state(fpu);
69}
70
71int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
72 struct membuf to)
73{
74 struct fpu *fpu = &target->thread.fpu;
75
76 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
77 return -ENODEV;
78
79 sync_fpstate(fpu);
80
81 if (!use_xsave()) {
82 return membuf_write(&to, &fpu->fpstate->regs.fxsave,
83 sizeof(fpu->fpstate->regs.fxsave));
84 }
85
86 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
87 return 0;
88}
89
90int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
91 unsigned int pos, unsigned int count,
92 const void *kbuf, const void __user *ubuf)
93{
94 struct fpu *fpu = &target->thread.fpu;
95 struct fxregs_state newstate;
96 int ret;
97
98 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
99 return -ENODEV;
100
101 /* No funny business with partial or oversized writes is permitted. */
102 if (pos != 0 || count != sizeof(newstate))
103 return -EINVAL;
104
105 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
106 if (ret)
107 return ret;
108
109 /* Do not allow an invalid MXCSR value. */
110 if (newstate.mxcsr & ~mxcsr_feature_mask)
111 return -EINVAL;
112
113 fpu_force_restore(fpu);
114
115 /* Copy the state */
116 memcpy(&fpu->fpstate->regs.fxsave, &newstate, sizeof(newstate));
117
118 /* Clear xmm8..15 for 32-bit callers */
119 BUILD_BUG_ON(sizeof(fpu->__fpstate.regs.fxsave.xmm_space) != 16 * 16);
120 if (in_ia32_syscall())
121 memset(&fpu->fpstate->regs.fxsave.xmm_space[8*4], 0, 8 * 16);
122
123 /* Mark FP and SSE as in use when XSAVE is enabled */
124 if (use_xsave())
125 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
126
127 return 0;
128}
129
130int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
131 struct membuf to)
132{
133 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
134 return -ENODEV;
135
136 sync_fpstate(&target->thread.fpu);
137
138 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
139 return 0;
140}
141
142int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
143 unsigned int pos, unsigned int count,
144 const void *kbuf, const void __user *ubuf)
145{
146 struct fpu *fpu = &target->thread.fpu;
147 struct xregs_state *tmpbuf = NULL;
148 int ret;
149
150 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
151 return -ENODEV;
152
153 /*
154 * A whole standard-format XSAVE buffer is needed:
155 */
156 if (pos != 0 || count != fpu_user_cfg.max_size)
157 return -EFAULT;
158
159 if (!kbuf) {
160 tmpbuf = vmalloc(count);
161 if (!tmpbuf)
162 return -ENOMEM;
163
164 if (copy_from_user(tmpbuf, ubuf, count)) {
165 ret = -EFAULT;
166 goto out;
167 }
168 }
169
170 fpu_force_restore(fpu);
171 ret = copy_uabi_from_kernel_to_xstate(fpu->fpstate, kbuf ?: tmpbuf, &target->thread.pkru);
172
173out:
174 vfree(tmpbuf);
175 return ret;
176}
177
178#ifdef CONFIG_X86_USER_SHADOW_STACK
179int ssp_active(struct task_struct *target, const struct user_regset *regset)
180{
181 if (target->thread.features & ARCH_SHSTK_SHSTK)
182 return regset->n;
183
184 return 0;
185}
186
187int ssp_get(struct task_struct *target, const struct user_regset *regset,
188 struct membuf to)
189{
190 struct fpu *fpu = &target->thread.fpu;
191 struct cet_user_state *cetregs;
192
193 if (!cpu_feature_enabled(X86_FEATURE_USER_SHSTK) ||
194 !ssp_active(target, regset))
195 return -ENODEV;
196
197 sync_fpstate(fpu);
198 cetregs = get_xsave_addr(&fpu->fpstate->regs.xsave, XFEATURE_CET_USER);
199 if (WARN_ON(!cetregs)) {
200 /*
201 * This shouldn't ever be NULL because shadow stack was
202 * verified to be enabled above. This means
203 * MSR_IA32_U_CET.CET_SHSTK_EN should be 1 and so
204 * XFEATURE_CET_USER should not be in the init state.
205 */
206 return -ENODEV;
207 }
208
209 return membuf_write(&to, (unsigned long *)&cetregs->user_ssp,
210 sizeof(cetregs->user_ssp));
211}
212
213int ssp_set(struct task_struct *target, const struct user_regset *regset,
214 unsigned int pos, unsigned int count,
215 const void *kbuf, const void __user *ubuf)
216{
217 struct fpu *fpu = &target->thread.fpu;
218 struct xregs_state *xsave = &fpu->fpstate->regs.xsave;
219 struct cet_user_state *cetregs;
220 unsigned long user_ssp;
221 int r;
222
223 if (!cpu_feature_enabled(X86_FEATURE_USER_SHSTK) ||
224 !ssp_active(target, regset))
225 return -ENODEV;
226
227 if (pos != 0 || count != sizeof(user_ssp))
228 return -EINVAL;
229
230 r = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_ssp, 0, -1);
231 if (r)
232 return r;
233
234 /*
235 * Some kernel instructions (IRET, etc) can cause exceptions in the case
236 * of disallowed CET register values. Just prevent invalid values.
237 */
238 if (user_ssp >= TASK_SIZE_MAX || !IS_ALIGNED(user_ssp, 8))
239 return -EINVAL;
240
241 fpu_force_restore(fpu);
242
243 cetregs = get_xsave_addr(xsave, XFEATURE_CET_USER);
244 if (WARN_ON(!cetregs)) {
245 /*
246 * This shouldn't ever be NULL because shadow stack was
247 * verified to be enabled above. This means
248 * MSR_IA32_U_CET.CET_SHSTK_EN should be 1 and so
249 * XFEATURE_CET_USER should not be in the init state.
250 */
251 return -ENODEV;
252 }
253
254 cetregs->user_ssp = user_ssp;
255 return 0;
256}
257#endif /* CONFIG_X86_USER_SHADOW_STACK */
258
259#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
260
261/*
262 * FPU tag word conversions.
263 */
264
265static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
266{
267 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
268
269 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
270 tmp = ~twd;
271 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
272 /* and move the valid bits to the lower byte. */
273 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
274 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
275 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
276
277 return tmp;
278}
279
280#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
281#define FP_EXP_TAG_VALID 0
282#define FP_EXP_TAG_ZERO 1
283#define FP_EXP_TAG_SPECIAL 2
284#define FP_EXP_TAG_EMPTY 3
285
286static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
287{
288 struct _fpxreg *st;
289 u32 tos = (fxsave->swd >> 11) & 7;
290 u32 twd = (unsigned long) fxsave->twd;
291 u32 tag;
292 u32 ret = 0xffff0000u;
293 int i;
294
295 for (i = 0; i < 8; i++, twd >>= 1) {
296 if (twd & 0x1) {
297 st = FPREG_ADDR(fxsave, (i - tos) & 7);
298
299 switch (st->exponent & 0x7fff) {
300 case 0x7fff:
301 tag = FP_EXP_TAG_SPECIAL;
302 break;
303 case 0x0000:
304 if (!st->significand[0] &&
305 !st->significand[1] &&
306 !st->significand[2] &&
307 !st->significand[3])
308 tag = FP_EXP_TAG_ZERO;
309 else
310 tag = FP_EXP_TAG_SPECIAL;
311 break;
312 default:
313 if (st->significand[3] & 0x8000)
314 tag = FP_EXP_TAG_VALID;
315 else
316 tag = FP_EXP_TAG_SPECIAL;
317 break;
318 }
319 } else {
320 tag = FP_EXP_TAG_EMPTY;
321 }
322 ret |= tag << (2 * i);
323 }
324 return ret;
325}
326
327/*
328 * FXSR floating point environment conversions.
329 */
330
331static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
332 struct task_struct *tsk,
333 struct fxregs_state *fxsave)
334{
335 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
336 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
337 int i;
338
339 env->cwd = fxsave->cwd | 0xffff0000u;
340 env->swd = fxsave->swd | 0xffff0000u;
341 env->twd = twd_fxsr_to_i387(fxsave);
342
343#ifdef CONFIG_X86_64
344 env->fip = fxsave->rip;
345 env->foo = fxsave->rdp;
346 /*
347 * should be actually ds/cs at fpu exception time, but
348 * that information is not available in 64bit mode.
349 */
350 env->fcs = task_pt_regs(tsk)->cs;
351 if (tsk == current) {
352 savesegment(ds, env->fos);
353 } else {
354 env->fos = tsk->thread.ds;
355 }
356 env->fos |= 0xffff0000;
357#else
358 env->fip = fxsave->fip;
359 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
360 env->foo = fxsave->foo;
361 env->fos = fxsave->fos;
362#endif
363
364 for (i = 0; i < 8; ++i)
365 memcpy(&to[i], &from[i], sizeof(to[0]));
366}
367
368void
369convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
370{
371 __convert_from_fxsr(env, tsk, &tsk->thread.fpu.fpstate->regs.fxsave);
372}
373
374void convert_to_fxsr(struct fxregs_state *fxsave,
375 const struct user_i387_ia32_struct *env)
376
377{
378 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
379 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
380 int i;
381
382 fxsave->cwd = env->cwd;
383 fxsave->swd = env->swd;
384 fxsave->twd = twd_i387_to_fxsr(env->twd);
385 fxsave->fop = (u16) ((u32) env->fcs >> 16);
386#ifdef CONFIG_X86_64
387 fxsave->rip = env->fip;
388 fxsave->rdp = env->foo;
389 /* cs and ds ignored */
390#else
391 fxsave->fip = env->fip;
392 fxsave->fcs = (env->fcs & 0xffff);
393 fxsave->foo = env->foo;
394 fxsave->fos = env->fos;
395#endif
396
397 for (i = 0; i < 8; ++i)
398 memcpy(&to[i], &from[i], sizeof(from[0]));
399}
400
401int fpregs_get(struct task_struct *target, const struct user_regset *regset,
402 struct membuf to)
403{
404 struct fpu *fpu = &target->thread.fpu;
405 struct user_i387_ia32_struct env;
406 struct fxregs_state fxsave, *fx;
407
408 sync_fpstate(fpu);
409
410 if (!cpu_feature_enabled(X86_FEATURE_FPU))
411 return fpregs_soft_get(target, regset, to);
412
413 if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
414 return membuf_write(&to, &fpu->fpstate->regs.fsave,
415 sizeof(struct fregs_state));
416 }
417
418 if (use_xsave()) {
419 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
420
421 /* Handle init state optimized xstate correctly */
422 copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
423 fx = &fxsave;
424 } else {
425 fx = &fpu->fpstate->regs.fxsave;
426 }
427
428 __convert_from_fxsr(&env, target, fx);
429 return membuf_write(&to, &env, sizeof(env));
430}
431
432int fpregs_set(struct task_struct *target, const struct user_regset *regset,
433 unsigned int pos, unsigned int count,
434 const void *kbuf, const void __user *ubuf)
435{
436 struct fpu *fpu = &target->thread.fpu;
437 struct user_i387_ia32_struct env;
438 int ret;
439
440 /* No funny business with partial or oversized writes is permitted. */
441 if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
442 return -EINVAL;
443
444 if (!cpu_feature_enabled(X86_FEATURE_FPU))
445 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
446
447 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
448 if (ret)
449 return ret;
450
451 fpu_force_restore(fpu);
452
453 if (cpu_feature_enabled(X86_FEATURE_FXSR))
454 convert_to_fxsr(&fpu->fpstate->regs.fxsave, &env);
455 else
456 memcpy(&fpu->fpstate->regs.fsave, &env, sizeof(env));
457
458 /*
459 * Update the header bit in the xsave header, indicating the
460 * presence of FP.
461 */
462 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
463 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FP;
464
465 return 0;
466}
467
468#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */