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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
4 */
5#include <linux/sched/task_stack.h>
6#include <linux/vmalloc.h>
7
8#include <asm/fpu/api.h>
9#include <asm/fpu/signal.h>
10#include <asm/fpu/regset.h>
11
12#include "context.h"
13#include "internal.h"
14#include "legacy.h"
15#include "xstate.h"
16
17/*
18 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
19 * as the "regset->n" for the xstate regset will be updated based on the feature
20 * capabilities supported by the xsave.
21 */
22int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
23{
24 return regset->n;
25}
26
27int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
28{
29 if (boot_cpu_has(X86_FEATURE_FXSR))
30 return regset->n;
31 else
32 return 0;
33}
34
35/*
36 * The regset get() functions are invoked from:
37 *
38 * - coredump to dump the current task's fpstate. If the current task
39 * owns the FPU then the memory state has to be synchronized and the
40 * FPU register state preserved. Otherwise fpstate is already in sync.
41 *
42 * - ptrace to dump fpstate of a stopped task, in which case the registers
43 * have already been saved to fpstate on context switch.
44 */
45static void sync_fpstate(struct fpu *fpu)
46{
47 if (fpu == ¤t->thread.fpu)
48 fpu_sync_fpstate(fpu);
49}
50
51/*
52 * Invalidate cached FPU registers before modifying the stopped target
53 * task's fpstate.
54 *
55 * This forces the target task on resume to restore the FPU registers from
56 * modified fpstate. Otherwise the task might skip the restore and operate
57 * with the cached FPU registers which discards the modifications.
58 */
59static void fpu_force_restore(struct fpu *fpu)
60{
61 /*
62 * Only stopped child tasks can be used to modify the FPU
63 * state in the fpstate buffer:
64 */
65 WARN_ON_FPU(fpu == ¤t->thread.fpu);
66
67 __fpu_invalidate_fpregs_state(fpu);
68}
69
70int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
71 struct membuf to)
72{
73 struct fpu *fpu = &target->thread.fpu;
74
75 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
76 return -ENODEV;
77
78 sync_fpstate(fpu);
79
80 if (!use_xsave()) {
81 return membuf_write(&to, &fpu->fpstate->regs.fxsave,
82 sizeof(fpu->fpstate->regs.fxsave));
83 }
84
85 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
86 return 0;
87}
88
89int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
90 unsigned int pos, unsigned int count,
91 const void *kbuf, const void __user *ubuf)
92{
93 struct fpu *fpu = &target->thread.fpu;
94 struct fxregs_state newstate;
95 int ret;
96
97 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
98 return -ENODEV;
99
100 /* No funny business with partial or oversized writes is permitted. */
101 if (pos != 0 || count != sizeof(newstate))
102 return -EINVAL;
103
104 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
105 if (ret)
106 return ret;
107
108 /* Do not allow an invalid MXCSR value. */
109 if (newstate.mxcsr & ~mxcsr_feature_mask)
110 return -EINVAL;
111
112 fpu_force_restore(fpu);
113
114 /* Copy the state */
115 memcpy(&fpu->fpstate->regs.fxsave, &newstate, sizeof(newstate));
116
117 /* Clear xmm8..15 for 32-bit callers */
118 BUILD_BUG_ON(sizeof(fpu->__fpstate.regs.fxsave.xmm_space) != 16 * 16);
119 if (in_ia32_syscall())
120 memset(&fpu->fpstate->regs.fxsave.xmm_space[8*4], 0, 8 * 16);
121
122 /* Mark FP and SSE as in use when XSAVE is enabled */
123 if (use_xsave())
124 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
125
126 return 0;
127}
128
129int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
130 struct membuf to)
131{
132 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
133 return -ENODEV;
134
135 sync_fpstate(&target->thread.fpu);
136
137 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
138 return 0;
139}
140
141int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
142 unsigned int pos, unsigned int count,
143 const void *kbuf, const void __user *ubuf)
144{
145 struct fpu *fpu = &target->thread.fpu;
146 struct xregs_state *tmpbuf = NULL;
147 int ret;
148
149 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
150 return -ENODEV;
151
152 /*
153 * A whole standard-format XSAVE buffer is needed:
154 */
155 if (pos != 0 || count != fpu_user_cfg.max_size)
156 return -EFAULT;
157
158 if (!kbuf) {
159 tmpbuf = vmalloc(count);
160 if (!tmpbuf)
161 return -ENOMEM;
162
163 if (copy_from_user(tmpbuf, ubuf, count)) {
164 ret = -EFAULT;
165 goto out;
166 }
167 }
168
169 fpu_force_restore(fpu);
170 ret = copy_uabi_from_kernel_to_xstate(fpu->fpstate, kbuf ?: tmpbuf, &target->thread.pkru);
171
172out:
173 vfree(tmpbuf);
174 return ret;
175}
176
177#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
178
179/*
180 * FPU tag word conversions.
181 */
182
183static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
184{
185 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
186
187 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
188 tmp = ~twd;
189 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
190 /* and move the valid bits to the lower byte. */
191 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
192 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
193 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
194
195 return tmp;
196}
197
198#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
199#define FP_EXP_TAG_VALID 0
200#define FP_EXP_TAG_ZERO 1
201#define FP_EXP_TAG_SPECIAL 2
202#define FP_EXP_TAG_EMPTY 3
203
204static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
205{
206 struct _fpxreg *st;
207 u32 tos = (fxsave->swd >> 11) & 7;
208 u32 twd = (unsigned long) fxsave->twd;
209 u32 tag;
210 u32 ret = 0xffff0000u;
211 int i;
212
213 for (i = 0; i < 8; i++, twd >>= 1) {
214 if (twd & 0x1) {
215 st = FPREG_ADDR(fxsave, (i - tos) & 7);
216
217 switch (st->exponent & 0x7fff) {
218 case 0x7fff:
219 tag = FP_EXP_TAG_SPECIAL;
220 break;
221 case 0x0000:
222 if (!st->significand[0] &&
223 !st->significand[1] &&
224 !st->significand[2] &&
225 !st->significand[3])
226 tag = FP_EXP_TAG_ZERO;
227 else
228 tag = FP_EXP_TAG_SPECIAL;
229 break;
230 default:
231 if (st->significand[3] & 0x8000)
232 tag = FP_EXP_TAG_VALID;
233 else
234 tag = FP_EXP_TAG_SPECIAL;
235 break;
236 }
237 } else {
238 tag = FP_EXP_TAG_EMPTY;
239 }
240 ret |= tag << (2 * i);
241 }
242 return ret;
243}
244
245/*
246 * FXSR floating point environment conversions.
247 */
248
249static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
250 struct task_struct *tsk,
251 struct fxregs_state *fxsave)
252{
253 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
254 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
255 int i;
256
257 env->cwd = fxsave->cwd | 0xffff0000u;
258 env->swd = fxsave->swd | 0xffff0000u;
259 env->twd = twd_fxsr_to_i387(fxsave);
260
261#ifdef CONFIG_X86_64
262 env->fip = fxsave->rip;
263 env->foo = fxsave->rdp;
264 /*
265 * should be actually ds/cs at fpu exception time, but
266 * that information is not available in 64bit mode.
267 */
268 env->fcs = task_pt_regs(tsk)->cs;
269 if (tsk == current) {
270 savesegment(ds, env->fos);
271 } else {
272 env->fos = tsk->thread.ds;
273 }
274 env->fos |= 0xffff0000;
275#else
276 env->fip = fxsave->fip;
277 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
278 env->foo = fxsave->foo;
279 env->fos = fxsave->fos;
280#endif
281
282 for (i = 0; i < 8; ++i)
283 memcpy(&to[i], &from[i], sizeof(to[0]));
284}
285
286void
287convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
288{
289 __convert_from_fxsr(env, tsk, &tsk->thread.fpu.fpstate->regs.fxsave);
290}
291
292void convert_to_fxsr(struct fxregs_state *fxsave,
293 const struct user_i387_ia32_struct *env)
294
295{
296 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
297 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
298 int i;
299
300 fxsave->cwd = env->cwd;
301 fxsave->swd = env->swd;
302 fxsave->twd = twd_i387_to_fxsr(env->twd);
303 fxsave->fop = (u16) ((u32) env->fcs >> 16);
304#ifdef CONFIG_X86_64
305 fxsave->rip = env->fip;
306 fxsave->rdp = env->foo;
307 /* cs and ds ignored */
308#else
309 fxsave->fip = env->fip;
310 fxsave->fcs = (env->fcs & 0xffff);
311 fxsave->foo = env->foo;
312 fxsave->fos = env->fos;
313#endif
314
315 for (i = 0; i < 8; ++i)
316 memcpy(&to[i], &from[i], sizeof(from[0]));
317}
318
319int fpregs_get(struct task_struct *target, const struct user_regset *regset,
320 struct membuf to)
321{
322 struct fpu *fpu = &target->thread.fpu;
323 struct user_i387_ia32_struct env;
324 struct fxregs_state fxsave, *fx;
325
326 sync_fpstate(fpu);
327
328 if (!cpu_feature_enabled(X86_FEATURE_FPU))
329 return fpregs_soft_get(target, regset, to);
330
331 if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
332 return membuf_write(&to, &fpu->fpstate->regs.fsave,
333 sizeof(struct fregs_state));
334 }
335
336 if (use_xsave()) {
337 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
338
339 /* Handle init state optimized xstate correctly */
340 copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
341 fx = &fxsave;
342 } else {
343 fx = &fpu->fpstate->regs.fxsave;
344 }
345
346 __convert_from_fxsr(&env, target, fx);
347 return membuf_write(&to, &env, sizeof(env));
348}
349
350int fpregs_set(struct task_struct *target, const struct user_regset *regset,
351 unsigned int pos, unsigned int count,
352 const void *kbuf, const void __user *ubuf)
353{
354 struct fpu *fpu = &target->thread.fpu;
355 struct user_i387_ia32_struct env;
356 int ret;
357
358 /* No funny business with partial or oversized writes is permitted. */
359 if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
360 return -EINVAL;
361
362 if (!cpu_feature_enabled(X86_FEATURE_FPU))
363 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
364
365 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
366 if (ret)
367 return ret;
368
369 fpu_force_restore(fpu);
370
371 if (cpu_feature_enabled(X86_FEATURE_FXSR))
372 convert_to_fxsr(&fpu->fpstate->regs.fxsave, &env);
373 else
374 memcpy(&fpu->fpstate->regs.fsave, &env, sizeof(env));
375
376 /*
377 * Update the header bit in the xsave header, indicating the
378 * presence of FP.
379 */
380 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
381 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FP;
382
383 return 0;
384}
385
386#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
4 */
5#include <asm/fpu/internal.h>
6#include <asm/fpu/signal.h>
7#include <asm/fpu/regset.h>
8#include <asm/fpu/xstate.h>
9#include <linux/sched/task_stack.h>
10
11/*
12 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
13 * as the "regset->n" for the xstate regset will be updated based on the feature
14 * capabilities supported by the xsave.
15 */
16int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
17{
18 return regset->n;
19}
20
21int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
22{
23 if (boot_cpu_has(X86_FEATURE_FXSR))
24 return regset->n;
25 else
26 return 0;
27}
28
29int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
30 struct membuf to)
31{
32 struct fpu *fpu = &target->thread.fpu;
33
34 if (!boot_cpu_has(X86_FEATURE_FXSR))
35 return -ENODEV;
36
37 fpu__prepare_read(fpu);
38 fpstate_sanitize_xstate(fpu);
39
40 return membuf_write(&to, &fpu->state.fxsave, sizeof(struct fxregs_state));
41}
42
43int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
44 unsigned int pos, unsigned int count,
45 const void *kbuf, const void __user *ubuf)
46{
47 struct fpu *fpu = &target->thread.fpu;
48 int ret;
49
50 if (!boot_cpu_has(X86_FEATURE_FXSR))
51 return -ENODEV;
52
53 fpu__prepare_write(fpu);
54 fpstate_sanitize_xstate(fpu);
55
56 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
57 &fpu->state.fxsave, 0, -1);
58
59 /*
60 * mxcsr reserved bits must be masked to zero for security reasons.
61 */
62 fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
63
64 /*
65 * update the header bits in the xsave header, indicating the
66 * presence of FP and SSE state.
67 */
68 if (boot_cpu_has(X86_FEATURE_XSAVE))
69 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
70
71 return ret;
72}
73
74int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
75 struct membuf to)
76{
77 struct fpu *fpu = &target->thread.fpu;
78 struct xregs_state *xsave;
79
80 if (!boot_cpu_has(X86_FEATURE_XSAVE))
81 return -ENODEV;
82
83 xsave = &fpu->state.xsave;
84
85 fpu__prepare_read(fpu);
86
87 if (using_compacted_format()) {
88 copy_xstate_to_kernel(to, xsave);
89 return 0;
90 } else {
91 fpstate_sanitize_xstate(fpu);
92 /*
93 * Copy the 48 bytes defined by the software into the xsave
94 * area in the thread struct, so that we can copy the whole
95 * area to user using one user_regset_copyout().
96 */
97 memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
98
99 /*
100 * Copy the xstate memory layout.
101 */
102 return membuf_write(&to, xsave, fpu_user_xstate_size);
103 }
104}
105
106int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
107 unsigned int pos, unsigned int count,
108 const void *kbuf, const void __user *ubuf)
109{
110 struct fpu *fpu = &target->thread.fpu;
111 struct xregs_state *xsave;
112 int ret;
113
114 if (!boot_cpu_has(X86_FEATURE_XSAVE))
115 return -ENODEV;
116
117 /*
118 * A whole standard-format XSAVE buffer is needed:
119 */
120 if ((pos != 0) || (count < fpu_user_xstate_size))
121 return -EFAULT;
122
123 xsave = &fpu->state.xsave;
124
125 fpu__prepare_write(fpu);
126
127 if (using_compacted_format()) {
128 if (kbuf)
129 ret = copy_kernel_to_xstate(xsave, kbuf);
130 else
131 ret = copy_user_to_xstate(xsave, ubuf);
132 } else {
133 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
134 if (!ret)
135 ret = validate_user_xstate_header(&xsave->header);
136 }
137
138 /*
139 * mxcsr reserved bits must be masked to zero for security reasons.
140 */
141 xsave->i387.mxcsr &= mxcsr_feature_mask;
142
143 /*
144 * In case of failure, mark all states as init:
145 */
146 if (ret)
147 fpstate_init(&fpu->state);
148
149 return ret;
150}
151
152#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
153
154/*
155 * FPU tag word conversions.
156 */
157
158static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
159{
160 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
161
162 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
163 tmp = ~twd;
164 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
165 /* and move the valid bits to the lower byte. */
166 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
167 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
168 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
169
170 return tmp;
171}
172
173#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
174#define FP_EXP_TAG_VALID 0
175#define FP_EXP_TAG_ZERO 1
176#define FP_EXP_TAG_SPECIAL 2
177#define FP_EXP_TAG_EMPTY 3
178
179static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
180{
181 struct _fpxreg *st;
182 u32 tos = (fxsave->swd >> 11) & 7;
183 u32 twd = (unsigned long) fxsave->twd;
184 u32 tag;
185 u32 ret = 0xffff0000u;
186 int i;
187
188 for (i = 0; i < 8; i++, twd >>= 1) {
189 if (twd & 0x1) {
190 st = FPREG_ADDR(fxsave, (i - tos) & 7);
191
192 switch (st->exponent & 0x7fff) {
193 case 0x7fff:
194 tag = FP_EXP_TAG_SPECIAL;
195 break;
196 case 0x0000:
197 if (!st->significand[0] &&
198 !st->significand[1] &&
199 !st->significand[2] &&
200 !st->significand[3])
201 tag = FP_EXP_TAG_ZERO;
202 else
203 tag = FP_EXP_TAG_SPECIAL;
204 break;
205 default:
206 if (st->significand[3] & 0x8000)
207 tag = FP_EXP_TAG_VALID;
208 else
209 tag = FP_EXP_TAG_SPECIAL;
210 break;
211 }
212 } else {
213 tag = FP_EXP_TAG_EMPTY;
214 }
215 ret |= tag << (2 * i);
216 }
217 return ret;
218}
219
220/*
221 * FXSR floating point environment conversions.
222 */
223
224void
225convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
226{
227 struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
228 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
229 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
230 int i;
231
232 env->cwd = fxsave->cwd | 0xffff0000u;
233 env->swd = fxsave->swd | 0xffff0000u;
234 env->twd = twd_fxsr_to_i387(fxsave);
235
236#ifdef CONFIG_X86_64
237 env->fip = fxsave->rip;
238 env->foo = fxsave->rdp;
239 /*
240 * should be actually ds/cs at fpu exception time, but
241 * that information is not available in 64bit mode.
242 */
243 env->fcs = task_pt_regs(tsk)->cs;
244 if (tsk == current) {
245 savesegment(ds, env->fos);
246 } else {
247 env->fos = tsk->thread.ds;
248 }
249 env->fos |= 0xffff0000;
250#else
251 env->fip = fxsave->fip;
252 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
253 env->foo = fxsave->foo;
254 env->fos = fxsave->fos;
255#endif
256
257 for (i = 0; i < 8; ++i)
258 memcpy(&to[i], &from[i], sizeof(to[0]));
259}
260
261void convert_to_fxsr(struct fxregs_state *fxsave,
262 const struct user_i387_ia32_struct *env)
263
264{
265 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
266 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
267 int i;
268
269 fxsave->cwd = env->cwd;
270 fxsave->swd = env->swd;
271 fxsave->twd = twd_i387_to_fxsr(env->twd);
272 fxsave->fop = (u16) ((u32) env->fcs >> 16);
273#ifdef CONFIG_X86_64
274 fxsave->rip = env->fip;
275 fxsave->rdp = env->foo;
276 /* cs and ds ignored */
277#else
278 fxsave->fip = env->fip;
279 fxsave->fcs = (env->fcs & 0xffff);
280 fxsave->foo = env->foo;
281 fxsave->fos = env->fos;
282#endif
283
284 for (i = 0; i < 8; ++i)
285 memcpy(&to[i], &from[i], sizeof(from[0]));
286}
287
288int fpregs_get(struct task_struct *target, const struct user_regset *regset,
289 struct membuf to)
290{
291 struct fpu *fpu = &target->thread.fpu;
292 struct user_i387_ia32_struct env;
293
294 fpu__prepare_read(fpu);
295
296 if (!boot_cpu_has(X86_FEATURE_FPU))
297 return fpregs_soft_get(target, regset, to);
298
299 if (!boot_cpu_has(X86_FEATURE_FXSR)) {
300 return membuf_write(&to, &fpu->state.fsave,
301 sizeof(struct fregs_state));
302 }
303
304 fpstate_sanitize_xstate(fpu);
305
306 if (to.left == sizeof(env)) {
307 convert_from_fxsr(to.p, target);
308 return 0;
309 }
310
311 convert_from_fxsr(&env, target);
312 return membuf_write(&to, &env, sizeof(env));
313}
314
315int fpregs_set(struct task_struct *target, const struct user_regset *regset,
316 unsigned int pos, unsigned int count,
317 const void *kbuf, const void __user *ubuf)
318{
319 struct fpu *fpu = &target->thread.fpu;
320 struct user_i387_ia32_struct env;
321 int ret;
322
323 fpu__prepare_write(fpu);
324 fpstate_sanitize_xstate(fpu);
325
326 if (!boot_cpu_has(X86_FEATURE_FPU))
327 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
328
329 if (!boot_cpu_has(X86_FEATURE_FXSR))
330 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
331 &fpu->state.fsave, 0,
332 -1);
333
334 if (pos > 0 || count < sizeof(env))
335 convert_from_fxsr(&env, target);
336
337 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
338 if (!ret)
339 convert_to_fxsr(&target->thread.fpu.state.fxsave, &env);
340
341 /*
342 * update the header bit in the xsave header, indicating the
343 * presence of FP.
344 */
345 if (boot_cpu_has(X86_FEATURE_XSAVE))
346 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
347 return ret;
348}
349
350#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */