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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
4 */
5#include <linux/sched/task_stack.h>
6#include <linux/vmalloc.h>
7
8#include <asm/fpu/api.h>
9#include <asm/fpu/signal.h>
10#include <asm/fpu/regset.h>
11
12#include "context.h"
13#include "internal.h"
14#include "legacy.h"
15#include "xstate.h"
16
17/*
18 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
19 * as the "regset->n" for the xstate regset will be updated based on the feature
20 * capabilities supported by the xsave.
21 */
22int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
23{
24 return regset->n;
25}
26
27int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
28{
29 if (boot_cpu_has(X86_FEATURE_FXSR))
30 return regset->n;
31 else
32 return 0;
33}
34
35/*
36 * The regset get() functions are invoked from:
37 *
38 * - coredump to dump the current task's fpstate. If the current task
39 * owns the FPU then the memory state has to be synchronized and the
40 * FPU register state preserved. Otherwise fpstate is already in sync.
41 *
42 * - ptrace to dump fpstate of a stopped task, in which case the registers
43 * have already been saved to fpstate on context switch.
44 */
45static void sync_fpstate(struct fpu *fpu)
46{
47 if (fpu == ¤t->thread.fpu)
48 fpu_sync_fpstate(fpu);
49}
50
51/*
52 * Invalidate cached FPU registers before modifying the stopped target
53 * task's fpstate.
54 *
55 * This forces the target task on resume to restore the FPU registers from
56 * modified fpstate. Otherwise the task might skip the restore and operate
57 * with the cached FPU registers which discards the modifications.
58 */
59static void fpu_force_restore(struct fpu *fpu)
60{
61 /*
62 * Only stopped child tasks can be used to modify the FPU
63 * state in the fpstate buffer:
64 */
65 WARN_ON_FPU(fpu == ¤t->thread.fpu);
66
67 __fpu_invalidate_fpregs_state(fpu);
68}
69
70int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
71 struct membuf to)
72{
73 struct fpu *fpu = &target->thread.fpu;
74
75 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
76 return -ENODEV;
77
78 sync_fpstate(fpu);
79
80 if (!use_xsave()) {
81 return membuf_write(&to, &fpu->fpstate->regs.fxsave,
82 sizeof(fpu->fpstate->regs.fxsave));
83 }
84
85 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
86 return 0;
87}
88
89int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
90 unsigned int pos, unsigned int count,
91 const void *kbuf, const void __user *ubuf)
92{
93 struct fpu *fpu = &target->thread.fpu;
94 struct fxregs_state newstate;
95 int ret;
96
97 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
98 return -ENODEV;
99
100 /* No funny business with partial or oversized writes is permitted. */
101 if (pos != 0 || count != sizeof(newstate))
102 return -EINVAL;
103
104 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
105 if (ret)
106 return ret;
107
108 /* Do not allow an invalid MXCSR value. */
109 if (newstate.mxcsr & ~mxcsr_feature_mask)
110 return -EINVAL;
111
112 fpu_force_restore(fpu);
113
114 /* Copy the state */
115 memcpy(&fpu->fpstate->regs.fxsave, &newstate, sizeof(newstate));
116
117 /* Clear xmm8..15 for 32-bit callers */
118 BUILD_BUG_ON(sizeof(fpu->__fpstate.regs.fxsave.xmm_space) != 16 * 16);
119 if (in_ia32_syscall())
120 memset(&fpu->fpstate->regs.fxsave.xmm_space[8*4], 0, 8 * 16);
121
122 /* Mark FP and SSE as in use when XSAVE is enabled */
123 if (use_xsave())
124 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
125
126 return 0;
127}
128
129int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
130 struct membuf to)
131{
132 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
133 return -ENODEV;
134
135 sync_fpstate(&target->thread.fpu);
136
137 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
138 return 0;
139}
140
141int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
142 unsigned int pos, unsigned int count,
143 const void *kbuf, const void __user *ubuf)
144{
145 struct fpu *fpu = &target->thread.fpu;
146 struct xregs_state *tmpbuf = NULL;
147 int ret;
148
149 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
150 return -ENODEV;
151
152 /*
153 * A whole standard-format XSAVE buffer is needed:
154 */
155 if (pos != 0 || count != fpu_user_cfg.max_size)
156 return -EFAULT;
157
158 if (!kbuf) {
159 tmpbuf = vmalloc(count);
160 if (!tmpbuf)
161 return -ENOMEM;
162
163 if (copy_from_user(tmpbuf, ubuf, count)) {
164 ret = -EFAULT;
165 goto out;
166 }
167 }
168
169 fpu_force_restore(fpu);
170 ret = copy_uabi_from_kernel_to_xstate(fpu->fpstate, kbuf ?: tmpbuf, &target->thread.pkru);
171
172out:
173 vfree(tmpbuf);
174 return ret;
175}
176
177#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
178
179/*
180 * FPU tag word conversions.
181 */
182
183static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
184{
185 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
186
187 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
188 tmp = ~twd;
189 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
190 /* and move the valid bits to the lower byte. */
191 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
192 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
193 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
194
195 return tmp;
196}
197
198#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
199#define FP_EXP_TAG_VALID 0
200#define FP_EXP_TAG_ZERO 1
201#define FP_EXP_TAG_SPECIAL 2
202#define FP_EXP_TAG_EMPTY 3
203
204static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
205{
206 struct _fpxreg *st;
207 u32 tos = (fxsave->swd >> 11) & 7;
208 u32 twd = (unsigned long) fxsave->twd;
209 u32 tag;
210 u32 ret = 0xffff0000u;
211 int i;
212
213 for (i = 0; i < 8; i++, twd >>= 1) {
214 if (twd & 0x1) {
215 st = FPREG_ADDR(fxsave, (i - tos) & 7);
216
217 switch (st->exponent & 0x7fff) {
218 case 0x7fff:
219 tag = FP_EXP_TAG_SPECIAL;
220 break;
221 case 0x0000:
222 if (!st->significand[0] &&
223 !st->significand[1] &&
224 !st->significand[2] &&
225 !st->significand[3])
226 tag = FP_EXP_TAG_ZERO;
227 else
228 tag = FP_EXP_TAG_SPECIAL;
229 break;
230 default:
231 if (st->significand[3] & 0x8000)
232 tag = FP_EXP_TAG_VALID;
233 else
234 tag = FP_EXP_TAG_SPECIAL;
235 break;
236 }
237 } else {
238 tag = FP_EXP_TAG_EMPTY;
239 }
240 ret |= tag << (2 * i);
241 }
242 return ret;
243}
244
245/*
246 * FXSR floating point environment conversions.
247 */
248
249static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
250 struct task_struct *tsk,
251 struct fxregs_state *fxsave)
252{
253 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
254 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
255 int i;
256
257 env->cwd = fxsave->cwd | 0xffff0000u;
258 env->swd = fxsave->swd | 0xffff0000u;
259 env->twd = twd_fxsr_to_i387(fxsave);
260
261#ifdef CONFIG_X86_64
262 env->fip = fxsave->rip;
263 env->foo = fxsave->rdp;
264 /*
265 * should be actually ds/cs at fpu exception time, but
266 * that information is not available in 64bit mode.
267 */
268 env->fcs = task_pt_regs(tsk)->cs;
269 if (tsk == current) {
270 savesegment(ds, env->fos);
271 } else {
272 env->fos = tsk->thread.ds;
273 }
274 env->fos |= 0xffff0000;
275#else
276 env->fip = fxsave->fip;
277 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
278 env->foo = fxsave->foo;
279 env->fos = fxsave->fos;
280#endif
281
282 for (i = 0; i < 8; ++i)
283 memcpy(&to[i], &from[i], sizeof(to[0]));
284}
285
286void
287convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
288{
289 __convert_from_fxsr(env, tsk, &tsk->thread.fpu.fpstate->regs.fxsave);
290}
291
292void convert_to_fxsr(struct fxregs_state *fxsave,
293 const struct user_i387_ia32_struct *env)
294
295{
296 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
297 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
298 int i;
299
300 fxsave->cwd = env->cwd;
301 fxsave->swd = env->swd;
302 fxsave->twd = twd_i387_to_fxsr(env->twd);
303 fxsave->fop = (u16) ((u32) env->fcs >> 16);
304#ifdef CONFIG_X86_64
305 fxsave->rip = env->fip;
306 fxsave->rdp = env->foo;
307 /* cs and ds ignored */
308#else
309 fxsave->fip = env->fip;
310 fxsave->fcs = (env->fcs & 0xffff);
311 fxsave->foo = env->foo;
312 fxsave->fos = env->fos;
313#endif
314
315 for (i = 0; i < 8; ++i)
316 memcpy(&to[i], &from[i], sizeof(from[0]));
317}
318
319int fpregs_get(struct task_struct *target, const struct user_regset *regset,
320 struct membuf to)
321{
322 struct fpu *fpu = &target->thread.fpu;
323 struct user_i387_ia32_struct env;
324 struct fxregs_state fxsave, *fx;
325
326 sync_fpstate(fpu);
327
328 if (!cpu_feature_enabled(X86_FEATURE_FPU))
329 return fpregs_soft_get(target, regset, to);
330
331 if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
332 return membuf_write(&to, &fpu->fpstate->regs.fsave,
333 sizeof(struct fregs_state));
334 }
335
336 if (use_xsave()) {
337 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
338
339 /* Handle init state optimized xstate correctly */
340 copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
341 fx = &fxsave;
342 } else {
343 fx = &fpu->fpstate->regs.fxsave;
344 }
345
346 __convert_from_fxsr(&env, target, fx);
347 return membuf_write(&to, &env, sizeof(env));
348}
349
350int fpregs_set(struct task_struct *target, const struct user_regset *regset,
351 unsigned int pos, unsigned int count,
352 const void *kbuf, const void __user *ubuf)
353{
354 struct fpu *fpu = &target->thread.fpu;
355 struct user_i387_ia32_struct env;
356 int ret;
357
358 /* No funny business with partial or oversized writes is permitted. */
359 if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
360 return -EINVAL;
361
362 if (!cpu_feature_enabled(X86_FEATURE_FPU))
363 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
364
365 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
366 if (ret)
367 return ret;
368
369 fpu_force_restore(fpu);
370
371 if (cpu_feature_enabled(X86_FEATURE_FXSR))
372 convert_to_fxsr(&fpu->fpstate->regs.fxsave, &env);
373 else
374 memcpy(&fpu->fpstate->regs.fsave, &env, sizeof(env));
375
376 /*
377 * Update the header bit in the xsave header, indicating the
378 * presence of FP.
379 */
380 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
381 fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FP;
382
383 return 0;
384}
385
386#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
4 */
5#include <linux/sched/task_stack.h>
6#include <linux/vmalloc.h>
7
8#include <asm/fpu/internal.h>
9#include <asm/fpu/signal.h>
10#include <asm/fpu/regset.h>
11#include <asm/fpu/xstate.h>
12
13/*
14 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
15 * as the "regset->n" for the xstate regset will be updated based on the feature
16 * capabilities supported by the xsave.
17 */
18int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
19{
20 return regset->n;
21}
22
23int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
24{
25 if (boot_cpu_has(X86_FEATURE_FXSR))
26 return regset->n;
27 else
28 return 0;
29}
30
31/*
32 * The regset get() functions are invoked from:
33 *
34 * - coredump to dump the current task's fpstate. If the current task
35 * owns the FPU then the memory state has to be synchronized and the
36 * FPU register state preserved. Otherwise fpstate is already in sync.
37 *
38 * - ptrace to dump fpstate of a stopped task, in which case the registers
39 * have already been saved to fpstate on context switch.
40 */
41static void sync_fpstate(struct fpu *fpu)
42{
43 if (fpu == ¤t->thread.fpu)
44 fpu_sync_fpstate(fpu);
45}
46
47/*
48 * Invalidate cached FPU registers before modifying the stopped target
49 * task's fpstate.
50 *
51 * This forces the target task on resume to restore the FPU registers from
52 * modified fpstate. Otherwise the task might skip the restore and operate
53 * with the cached FPU registers which discards the modifications.
54 */
55static void fpu_force_restore(struct fpu *fpu)
56{
57 /*
58 * Only stopped child tasks can be used to modify the FPU
59 * state in the fpstate buffer:
60 */
61 WARN_ON_FPU(fpu == ¤t->thread.fpu);
62
63 __fpu_invalidate_fpregs_state(fpu);
64}
65
66int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
67 struct membuf to)
68{
69 struct fpu *fpu = &target->thread.fpu;
70
71 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
72 return -ENODEV;
73
74 sync_fpstate(fpu);
75
76 if (!use_xsave()) {
77 return membuf_write(&to, &fpu->state.fxsave,
78 sizeof(fpu->state.fxsave));
79 }
80
81 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
82 return 0;
83}
84
85int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
86 unsigned int pos, unsigned int count,
87 const void *kbuf, const void __user *ubuf)
88{
89 struct fpu *fpu = &target->thread.fpu;
90 struct user32_fxsr_struct newstate;
91 int ret;
92
93 BUILD_BUG_ON(sizeof(newstate) != sizeof(struct fxregs_state));
94
95 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
96 return -ENODEV;
97
98 /* No funny business with partial or oversized writes is permitted. */
99 if (pos != 0 || count != sizeof(newstate))
100 return -EINVAL;
101
102 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
103 if (ret)
104 return ret;
105
106 /* Do not allow an invalid MXCSR value. */
107 if (newstate.mxcsr & ~mxcsr_feature_mask)
108 return -EINVAL;
109
110 fpu_force_restore(fpu);
111
112 /* Copy the state */
113 memcpy(&fpu->state.fxsave, &newstate, sizeof(newstate));
114
115 /* Clear xmm8..15 */
116 BUILD_BUG_ON(sizeof(fpu->state.fxsave.xmm_space) != 16 * 16);
117 memset(&fpu->state.fxsave.xmm_space[8], 0, 8 * 16);
118
119 /* Mark FP and SSE as in use when XSAVE is enabled */
120 if (use_xsave())
121 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
122
123 return 0;
124}
125
126int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
127 struct membuf to)
128{
129 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
130 return -ENODEV;
131
132 sync_fpstate(&target->thread.fpu);
133
134 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
135 return 0;
136}
137
138int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
139 unsigned int pos, unsigned int count,
140 const void *kbuf, const void __user *ubuf)
141{
142 struct fpu *fpu = &target->thread.fpu;
143 struct xregs_state *tmpbuf = NULL;
144 int ret;
145
146 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
147 return -ENODEV;
148
149 /*
150 * A whole standard-format XSAVE buffer is needed:
151 */
152 if (pos != 0 || count != fpu_user_xstate_size)
153 return -EFAULT;
154
155 if (!kbuf) {
156 tmpbuf = vmalloc(count);
157 if (!tmpbuf)
158 return -ENOMEM;
159
160 if (copy_from_user(tmpbuf, ubuf, count)) {
161 ret = -EFAULT;
162 goto out;
163 }
164 }
165
166 fpu_force_restore(fpu);
167 ret = copy_uabi_from_kernel_to_xstate(&fpu->state.xsave, kbuf ?: tmpbuf);
168
169out:
170 vfree(tmpbuf);
171 return ret;
172}
173
174#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
175
176/*
177 * FPU tag word conversions.
178 */
179
180static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
181{
182 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
183
184 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
185 tmp = ~twd;
186 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
187 /* and move the valid bits to the lower byte. */
188 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
189 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
190 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
191
192 return tmp;
193}
194
195#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
196#define FP_EXP_TAG_VALID 0
197#define FP_EXP_TAG_ZERO 1
198#define FP_EXP_TAG_SPECIAL 2
199#define FP_EXP_TAG_EMPTY 3
200
201static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
202{
203 struct _fpxreg *st;
204 u32 tos = (fxsave->swd >> 11) & 7;
205 u32 twd = (unsigned long) fxsave->twd;
206 u32 tag;
207 u32 ret = 0xffff0000u;
208 int i;
209
210 for (i = 0; i < 8; i++, twd >>= 1) {
211 if (twd & 0x1) {
212 st = FPREG_ADDR(fxsave, (i - tos) & 7);
213
214 switch (st->exponent & 0x7fff) {
215 case 0x7fff:
216 tag = FP_EXP_TAG_SPECIAL;
217 break;
218 case 0x0000:
219 if (!st->significand[0] &&
220 !st->significand[1] &&
221 !st->significand[2] &&
222 !st->significand[3])
223 tag = FP_EXP_TAG_ZERO;
224 else
225 tag = FP_EXP_TAG_SPECIAL;
226 break;
227 default:
228 if (st->significand[3] & 0x8000)
229 tag = FP_EXP_TAG_VALID;
230 else
231 tag = FP_EXP_TAG_SPECIAL;
232 break;
233 }
234 } else {
235 tag = FP_EXP_TAG_EMPTY;
236 }
237 ret |= tag << (2 * i);
238 }
239 return ret;
240}
241
242/*
243 * FXSR floating point environment conversions.
244 */
245
246static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
247 struct task_struct *tsk,
248 struct fxregs_state *fxsave)
249{
250 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
251 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
252 int i;
253
254 env->cwd = fxsave->cwd | 0xffff0000u;
255 env->swd = fxsave->swd | 0xffff0000u;
256 env->twd = twd_fxsr_to_i387(fxsave);
257
258#ifdef CONFIG_X86_64
259 env->fip = fxsave->rip;
260 env->foo = fxsave->rdp;
261 /*
262 * should be actually ds/cs at fpu exception time, but
263 * that information is not available in 64bit mode.
264 */
265 env->fcs = task_pt_regs(tsk)->cs;
266 if (tsk == current) {
267 savesegment(ds, env->fos);
268 } else {
269 env->fos = tsk->thread.ds;
270 }
271 env->fos |= 0xffff0000;
272#else
273 env->fip = fxsave->fip;
274 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
275 env->foo = fxsave->foo;
276 env->fos = fxsave->fos;
277#endif
278
279 for (i = 0; i < 8; ++i)
280 memcpy(&to[i], &from[i], sizeof(to[0]));
281}
282
283void
284convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
285{
286 __convert_from_fxsr(env, tsk, &tsk->thread.fpu.state.fxsave);
287}
288
289void convert_to_fxsr(struct fxregs_state *fxsave,
290 const struct user_i387_ia32_struct *env)
291
292{
293 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
294 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
295 int i;
296
297 fxsave->cwd = env->cwd;
298 fxsave->swd = env->swd;
299 fxsave->twd = twd_i387_to_fxsr(env->twd);
300 fxsave->fop = (u16) ((u32) env->fcs >> 16);
301#ifdef CONFIG_X86_64
302 fxsave->rip = env->fip;
303 fxsave->rdp = env->foo;
304 /* cs and ds ignored */
305#else
306 fxsave->fip = env->fip;
307 fxsave->fcs = (env->fcs & 0xffff);
308 fxsave->foo = env->foo;
309 fxsave->fos = env->fos;
310#endif
311
312 for (i = 0; i < 8; ++i)
313 memcpy(&to[i], &from[i], sizeof(from[0]));
314}
315
316int fpregs_get(struct task_struct *target, const struct user_regset *regset,
317 struct membuf to)
318{
319 struct fpu *fpu = &target->thread.fpu;
320 struct user_i387_ia32_struct env;
321 struct fxregs_state fxsave, *fx;
322
323 sync_fpstate(fpu);
324
325 if (!cpu_feature_enabled(X86_FEATURE_FPU))
326 return fpregs_soft_get(target, regset, to);
327
328 if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
329 return membuf_write(&to, &fpu->state.fsave,
330 sizeof(struct fregs_state));
331 }
332
333 if (use_xsave()) {
334 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
335
336 /* Handle init state optimized xstate correctly */
337 copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
338 fx = &fxsave;
339 } else {
340 fx = &fpu->state.fxsave;
341 }
342
343 __convert_from_fxsr(&env, target, fx);
344 return membuf_write(&to, &env, sizeof(env));
345}
346
347int fpregs_set(struct task_struct *target, const struct user_regset *regset,
348 unsigned int pos, unsigned int count,
349 const void *kbuf, const void __user *ubuf)
350{
351 struct fpu *fpu = &target->thread.fpu;
352 struct user_i387_ia32_struct env;
353 int ret;
354
355 /* No funny business with partial or oversized writes is permitted. */
356 if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
357 return -EINVAL;
358
359 if (!cpu_feature_enabled(X86_FEATURE_FPU))
360 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
361
362 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
363 if (ret)
364 return ret;
365
366 fpu_force_restore(fpu);
367
368 if (cpu_feature_enabled(X86_FEATURE_FXSR))
369 convert_to_fxsr(&fpu->state.fxsave, &env);
370 else
371 memcpy(&fpu->state.fsave, &env, sizeof(env));
372
373 /*
374 * Update the header bit in the xsave header, indicating the
375 * presence of FP.
376 */
377 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
378 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
379
380 return 0;
381}
382
383#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */