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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_MMU_H
3#define __KVM_X86_MMU_H
4
5#include <linux/kvm_host.h>
6#include "kvm_cache_regs.h"
7#include "x86.h"
8#include "cpuid.h"
9
10extern bool __read_mostly enable_mmio_caching;
11
12#define PT_WRITABLE_SHIFT 1
13#define PT_USER_SHIFT 2
14
15#define PT_PRESENT_MASK (1ULL << 0)
16#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
17#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
18#define PT_PWT_MASK (1ULL << 3)
19#define PT_PCD_MASK (1ULL << 4)
20#define PT_ACCESSED_SHIFT 5
21#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
22#define PT_DIRTY_SHIFT 6
23#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
24#define PT_PAGE_SIZE_SHIFT 7
25#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
26#define PT_PAT_MASK (1ULL << 7)
27#define PT_GLOBAL_MASK (1ULL << 8)
28#define PT64_NX_SHIFT 63
29#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
30
31#define PT_PAT_SHIFT 7
32#define PT_DIR_PAT_SHIFT 12
33#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
34
35#define PT64_ROOT_5LEVEL 5
36#define PT64_ROOT_4LEVEL 4
37#define PT32_ROOT_LEVEL 2
38#define PT32E_ROOT_LEVEL 3
39
40#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
41 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
42
43#define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
44#define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
45
46static __always_inline u64 rsvd_bits(int s, int e)
47{
48 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
49
50 if (__builtin_constant_p(e))
51 BUILD_BUG_ON(e > 63);
52 else
53 e &= 63;
54
55 if (e < s)
56 return 0;
57
58 return ((2ULL << (e - s)) - 1) << s;
59}
60
61static inline gfn_t kvm_mmu_max_gfn(void)
62{
63 /*
64 * Note that this uses the host MAXPHYADDR, not the guest's.
65 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
66 * assuming KVM is running on bare metal, guest accesses beyond
67 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
68 * (either EPT Violation/Misconfig or #NPF), and so KVM will never
69 * install a SPTE for such addresses. If KVM is running as a VM
70 * itself, on the other hand, it might see a MAXPHYADDR that is less
71 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
72 * disallows such SPTEs entirely and simplifies the TDP MMU.
73 */
74 int max_gpa_bits = likely(tdp_enabled) ? kvm_host.maxphyaddr : 52;
75
76 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
77}
78
79u8 kvm_mmu_get_max_tdp_level(void);
80
81void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
82void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
83void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
84
85void kvm_init_mmu(struct kvm_vcpu *vcpu);
86void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
87 unsigned long cr4, u64 efer, gpa_t nested_cr3);
88void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
89 int huge_page_level, bool accessed_dirty,
90 gpa_t new_eptp);
91bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
92int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
93 u64 fault_address, char *insn, int insn_len);
94void __kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu,
95 struct kvm_mmu *mmu);
96
97int kvm_mmu_load(struct kvm_vcpu *vcpu);
98void kvm_mmu_unload(struct kvm_vcpu *vcpu);
99void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
100void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
101void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
102void kvm_mmu_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
103 int bytes);
104
105static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
106{
107 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
108 return 0;
109
110 return kvm_mmu_load(vcpu);
111}
112
113static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
114{
115 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
116
117 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)
118 ? cr3 & X86_CR3_PCID_MASK
119 : 0;
120}
121
122static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
123{
124 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
125}
126
127static inline unsigned long kvm_get_active_cr3_lam_bits(struct kvm_vcpu *vcpu)
128{
129 if (!guest_can_use(vcpu, X86_FEATURE_LAM))
130 return 0;
131
132 return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57);
133}
134
135static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
136{
137 u64 root_hpa = vcpu->arch.mmu->root.hpa;
138
139 if (!VALID_PAGE(root_hpa))
140 return;
141
142 kvm_x86_call(load_mmu_pgd)(vcpu, root_hpa,
143 vcpu->arch.mmu->root_role.level);
144}
145
146static inline void kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu,
147 struct kvm_mmu *mmu)
148{
149 /*
150 * When EPT is enabled, KVM may passthrough CR0.WP to the guest, i.e.
151 * @mmu's snapshot of CR0.WP and thus all related paging metadata may
152 * be stale. Refresh CR0.WP and the metadata on-demand when checking
153 * for permission faults. Exempt nested MMUs, i.e. MMUs for shadowing
154 * nEPT and nNPT, as CR0.WP is ignored in both cases. Note, KVM does
155 * need to refresh nested_mmu, a.k.a. the walker used to translate L2
156 * GVAs to GPAs, as that "MMU" needs to honor L2's CR0.WP.
157 */
158 if (!tdp_enabled || mmu == &vcpu->arch.guest_mmu)
159 return;
160
161 __kvm_mmu_refresh_passthrough_bits(vcpu, mmu);
162}
163
164/*
165 * Check if a given access (described through the I/D, W/R and U/S bits of a
166 * page fault error code pfec) causes a permission fault with the given PTE
167 * access rights (in ACC_* format).
168 *
169 * Return zero if the access does not fault; return the page fault error code
170 * if the access faults.
171 */
172static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
173 unsigned pte_access, unsigned pte_pkey,
174 u64 access)
175{
176 /* strip nested paging fault error codes */
177 unsigned int pfec = access;
178 unsigned long rflags = kvm_x86_call(get_rflags)(vcpu);
179
180 /*
181 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
182 * For implicit supervisor accesses, SMAP cannot be overridden.
183 *
184 * SMAP works on supervisor accesses only, and not_smap can
185 * be set or not set when user access with neither has any bearing
186 * on the result.
187 *
188 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
189 * this bit will always be zero in pfec, but it will be one in index
190 * if SMAP checks are being disabled.
191 */
192 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
193 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
194 int index = (pfec | (not_smap ? PFERR_RSVD_MASK : 0)) >> 1;
195 u32 errcode = PFERR_PRESENT_MASK;
196 bool fault;
197
198 kvm_mmu_refresh_passthrough_bits(vcpu, mmu);
199
200 fault = (mmu->permissions[index] >> pte_access) & 1;
201
202 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
203 if (unlikely(mmu->pkru_mask)) {
204 u32 pkru_bits, offset;
205
206 /*
207 * PKRU defines 32 bits, there are 16 domains and 2
208 * attribute bits per domain in pkru. pte_pkey is the
209 * index of the protection domain, so pte_pkey * 2 is
210 * is the index of the first bit for the domain.
211 */
212 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
213
214 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
215 offset = (pfec & ~1) | ((pte_access & PT_USER_MASK) ? PFERR_RSVD_MASK : 0);
216
217 pkru_bits &= mmu->pkru_mask >> offset;
218 errcode |= -pkru_bits & PFERR_PK_MASK;
219 fault |= (pkru_bits != 0);
220 }
221
222 return -(u32)fault & errcode;
223}
224
225bool kvm_mmu_may_ignore_guest_pat(void);
226
227int kvm_mmu_post_init_vm(struct kvm *kvm);
228void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
229
230static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
231{
232 /*
233 * Read shadow_root_allocated before related pointers. Hence, threads
234 * reading shadow_root_allocated in any lock context are guaranteed to
235 * see the pointers. Pairs with smp_store_release in
236 * mmu_first_shadow_root_alloc.
237 */
238 return smp_load_acquire(&kvm->arch.shadow_root_allocated);
239}
240
241#ifdef CONFIG_X86_64
242extern bool tdp_mmu_enabled;
243#else
244#define tdp_mmu_enabled false
245#endif
246
247static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
248{
249 return !tdp_mmu_enabled || kvm_shadow_root_allocated(kvm);
250}
251
252static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
253{
254 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
255 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
256 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
257}
258
259static inline unsigned long
260__kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
261 int level)
262{
263 return gfn_to_index(slot->base_gfn + npages - 1,
264 slot->base_gfn, level) + 1;
265}
266
267static inline unsigned long
268kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
269{
270 return __kvm_mmu_slot_lpages(slot, slot->npages, level);
271}
272
273static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
274{
275 atomic64_add(count, &kvm->stat.pages[level - 1]);
276}
277
278gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
279 struct x86_exception *exception);
280
281static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
282 struct kvm_mmu *mmu,
283 gpa_t gpa, u64 access,
284 struct x86_exception *exception)
285{
286 if (mmu != &vcpu->arch.nested_mmu)
287 return gpa;
288 return translate_nested_gpa(vcpu, gpa, access, exception);
289}
290#endif
1#ifndef __KVM_X86_MMU_H
2#define __KVM_X86_MMU_H
3
4#include <linux/kvm_host.h>
5#include "kvm_cache_regs.h"
6
7#define PT64_PT_BITS 9
8#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
9#define PT32_PT_BITS 10
10#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
11
12#define PT_WRITABLE_SHIFT 1
13
14#define PT_PRESENT_MASK (1ULL << 0)
15#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
16#define PT_USER_MASK (1ULL << 2)
17#define PT_PWT_MASK (1ULL << 3)
18#define PT_PCD_MASK (1ULL << 4)
19#define PT_ACCESSED_SHIFT 5
20#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
21#define PT_DIRTY_MASK (1ULL << 6)
22#define PT_PAGE_SIZE_MASK (1ULL << 7)
23#define PT_PAT_MASK (1ULL << 7)
24#define PT_GLOBAL_MASK (1ULL << 8)
25#define PT64_NX_SHIFT 63
26#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
27
28#define PT_PAT_SHIFT 7
29#define PT_DIR_PAT_SHIFT 12
30#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
31
32#define PT32_DIR_PSE36_SIZE 4
33#define PT32_DIR_PSE36_SHIFT 13
34#define PT32_DIR_PSE36_MASK \
35 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
36
37#define PT64_ROOT_LEVEL 4
38#define PT32_ROOT_LEVEL 2
39#define PT32E_ROOT_LEVEL 3
40
41#define PT_PDPE_LEVEL 3
42#define PT_DIRECTORY_LEVEL 2
43#define PT_PAGE_TABLE_LEVEL 1
44
45#define PFERR_PRESENT_MASK (1U << 0)
46#define PFERR_WRITE_MASK (1U << 1)
47#define PFERR_USER_MASK (1U << 2)
48#define PFERR_RSVD_MASK (1U << 3)
49#define PFERR_FETCH_MASK (1U << 4)
50
51int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
52void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
53int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct);
54int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
55
56static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
57{
58 return kvm->arch.n_max_mmu_pages -
59 kvm->arch.n_used_mmu_pages;
60}
61
62static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
63{
64 if (unlikely(kvm_mmu_available_pages(vcpu->kvm)< KVM_MIN_FREE_MMU_PAGES))
65 __kvm_mmu_free_some_pages(vcpu);
66}
67
68static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
69{
70 if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
71 return 0;
72
73 return kvm_mmu_load(vcpu);
74}
75
76static inline int is_present_gpte(unsigned long pte)
77{
78 return pte & PT_PRESENT_MASK;
79}
80
81static inline int is_writable_pte(unsigned long pte)
82{
83 return pte & PT_WRITABLE_MASK;
84}
85
86static inline bool is_write_protection(struct kvm_vcpu *vcpu)
87{
88 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
89}
90
91static inline bool check_write_user_access(struct kvm_vcpu *vcpu,
92 bool write_fault, bool user_fault,
93 unsigned long pte)
94{
95 if (unlikely(write_fault && !is_writable_pte(pte)
96 && (user_fault || is_write_protection(vcpu))))
97 return false;
98
99 if (unlikely(user_fault && !(pte & PT_USER_MASK)))
100 return false;
101
102 return true;
103}
104#endif