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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17#include <linux/kvm_host.h>
18
19#include "irq.h"
20#include "mmu.h"
21#include "kvm_cache_regs.h"
22#include "x86.h"
23#include "cpuid.h"
24
25#include <linux/module.h>
26#include <linux/mod_devicetable.h>
27#include <linux/kernel.h>
28#include <linux/vmalloc.h>
29#include <linux/highmem.h>
30#include <linux/sched.h>
31#include <linux/ftrace_event.h>
32#include <linux/slab.h>
33
34#include <asm/perf_event.h>
35#include <asm/tlbflush.h>
36#include <asm/desc.h>
37#include <asm/debugreg.h>
38#include <asm/kvm_para.h>
39
40#include <asm/virtext.h>
41#include "trace.h"
42
43#define __ex(x) __kvm_handle_fault_on_reboot(x)
44
45MODULE_AUTHOR("Qumranet");
46MODULE_LICENSE("GPL");
47
48static const struct x86_cpu_id svm_cpu_id[] = {
49 X86_FEATURE_MATCH(X86_FEATURE_SVM),
50 {}
51};
52MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
53
54#define IOPM_ALLOC_ORDER 2
55#define MSRPM_ALLOC_ORDER 1
56
57#define SEG_TYPE_LDT 2
58#define SEG_TYPE_BUSY_TSS16 3
59
60#define SVM_FEATURE_NPT (1 << 0)
61#define SVM_FEATURE_LBRV (1 << 1)
62#define SVM_FEATURE_SVML (1 << 2)
63#define SVM_FEATURE_NRIP (1 << 3)
64#define SVM_FEATURE_TSC_RATE (1 << 4)
65#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
66#define SVM_FEATURE_FLUSH_ASID (1 << 6)
67#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
68#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
69
70#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
71#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
72#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
73
74#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
75
76#define TSC_RATIO_RSVD 0xffffff0000000000ULL
77#define TSC_RATIO_MIN 0x0000000000000001ULL
78#define TSC_RATIO_MAX 0x000000ffffffffffULL
79
80static bool erratum_383_found __read_mostly;
81
82static const u32 host_save_user_msrs[] = {
83#ifdef CONFIG_X86_64
84 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
85 MSR_FS_BASE,
86#endif
87 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
88};
89
90#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
91
92struct kvm_vcpu;
93
94struct nested_state {
95 struct vmcb *hsave;
96 u64 hsave_msr;
97 u64 vm_cr_msr;
98 u64 vmcb;
99
100 /* These are the merged vectors */
101 u32 *msrpm;
102
103 /* gpa pointers to the real vectors */
104 u64 vmcb_msrpm;
105 u64 vmcb_iopm;
106
107 /* A VMEXIT is required but not yet emulated */
108 bool exit_required;
109
110 /* cache for intercepts of the guest */
111 u32 intercept_cr;
112 u32 intercept_dr;
113 u32 intercept_exceptions;
114 u64 intercept;
115
116 /* Nested Paging related state */
117 u64 nested_cr3;
118};
119
120#define MSRPM_OFFSETS 16
121static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
122
123/*
124 * Set osvw_len to higher value when updated Revision Guides
125 * are published and we know what the new status bits are
126 */
127static uint64_t osvw_len = 4, osvw_status;
128
129struct vcpu_svm {
130 struct kvm_vcpu vcpu;
131 struct vmcb *vmcb;
132 unsigned long vmcb_pa;
133 struct svm_cpu_data *svm_data;
134 uint64_t asid_generation;
135 uint64_t sysenter_esp;
136 uint64_t sysenter_eip;
137
138 u64 next_rip;
139
140 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
141 struct {
142 u16 fs;
143 u16 gs;
144 u16 ldt;
145 u64 gs_base;
146 } host;
147
148 u32 *msrpm;
149
150 ulong nmi_iret_rip;
151
152 struct nested_state nested;
153
154 bool nmi_singlestep;
155
156 unsigned int3_injected;
157 unsigned long int3_rip;
158 u32 apf_reason;
159
160 u64 tsc_ratio;
161};
162
163static DEFINE_PER_CPU(u64, current_tsc_ratio);
164#define TSC_RATIO_DEFAULT 0x0100000000ULL
165
166#define MSR_INVALID 0xffffffffU
167
168static const struct svm_direct_access_msrs {
169 u32 index; /* Index of the MSR */
170 bool always; /* True if intercept is always on */
171} direct_access_msrs[] = {
172 { .index = MSR_STAR, .always = true },
173 { .index = MSR_IA32_SYSENTER_CS, .always = true },
174#ifdef CONFIG_X86_64
175 { .index = MSR_GS_BASE, .always = true },
176 { .index = MSR_FS_BASE, .always = true },
177 { .index = MSR_KERNEL_GS_BASE, .always = true },
178 { .index = MSR_LSTAR, .always = true },
179 { .index = MSR_CSTAR, .always = true },
180 { .index = MSR_SYSCALL_MASK, .always = true },
181#endif
182 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
183 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
184 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
185 { .index = MSR_IA32_LASTINTTOIP, .always = false },
186 { .index = MSR_INVALID, .always = false },
187};
188
189/* enable NPT for AMD64 and X86 with PAE */
190#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
191static bool npt_enabled = true;
192#else
193static bool npt_enabled;
194#endif
195
196/* allow nested paging (virtualized MMU) for all guests */
197static int npt = true;
198module_param(npt, int, S_IRUGO);
199
200/* allow nested virtualization in KVM/SVM */
201static int nested = true;
202module_param(nested, int, S_IRUGO);
203
204static void svm_flush_tlb(struct kvm_vcpu *vcpu);
205static void svm_complete_interrupts(struct vcpu_svm *svm);
206
207static int nested_svm_exit_handled(struct vcpu_svm *svm);
208static int nested_svm_intercept(struct vcpu_svm *svm);
209static int nested_svm_vmexit(struct vcpu_svm *svm);
210static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
211 bool has_error_code, u32 error_code);
212static u64 __scale_tsc(u64 ratio, u64 tsc);
213
214enum {
215 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
216 pause filter count */
217 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
218 VMCB_ASID, /* ASID */
219 VMCB_INTR, /* int_ctl, int_vector */
220 VMCB_NPT, /* npt_en, nCR3, gPAT */
221 VMCB_CR, /* CR0, CR3, CR4, EFER */
222 VMCB_DR, /* DR6, DR7 */
223 VMCB_DT, /* GDT, IDT */
224 VMCB_SEG, /* CS, DS, SS, ES, CPL */
225 VMCB_CR2, /* CR2 only */
226 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
227 VMCB_DIRTY_MAX,
228};
229
230/* TPR and CR2 are always written before VMRUN */
231#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
232
233static inline void mark_all_dirty(struct vmcb *vmcb)
234{
235 vmcb->control.clean = 0;
236}
237
238static inline void mark_all_clean(struct vmcb *vmcb)
239{
240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
241 & ~VMCB_ALWAYS_DIRTY_MASK;
242}
243
244static inline void mark_dirty(struct vmcb *vmcb, int bit)
245{
246 vmcb->control.clean &= ~(1 << bit);
247}
248
249static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
250{
251 return container_of(vcpu, struct vcpu_svm, vcpu);
252}
253
254static void recalc_intercepts(struct vcpu_svm *svm)
255{
256 struct vmcb_control_area *c, *h;
257 struct nested_state *g;
258
259 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
260
261 if (!is_guest_mode(&svm->vcpu))
262 return;
263
264 c = &svm->vmcb->control;
265 h = &svm->nested.hsave->control;
266 g = &svm->nested;
267
268 c->intercept_cr = h->intercept_cr | g->intercept_cr;
269 c->intercept_dr = h->intercept_dr | g->intercept_dr;
270 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
271 c->intercept = h->intercept | g->intercept;
272}
273
274static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
275{
276 if (is_guest_mode(&svm->vcpu))
277 return svm->nested.hsave;
278 else
279 return svm->vmcb;
280}
281
282static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
283{
284 struct vmcb *vmcb = get_host_vmcb(svm);
285
286 vmcb->control.intercept_cr |= (1U << bit);
287
288 recalc_intercepts(svm);
289}
290
291static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
292{
293 struct vmcb *vmcb = get_host_vmcb(svm);
294
295 vmcb->control.intercept_cr &= ~(1U << bit);
296
297 recalc_intercepts(svm);
298}
299
300static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
301{
302 struct vmcb *vmcb = get_host_vmcb(svm);
303
304 return vmcb->control.intercept_cr & (1U << bit);
305}
306
307static inline void set_dr_intercepts(struct vcpu_svm *svm)
308{
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
312 | (1 << INTERCEPT_DR1_READ)
313 | (1 << INTERCEPT_DR2_READ)
314 | (1 << INTERCEPT_DR3_READ)
315 | (1 << INTERCEPT_DR4_READ)
316 | (1 << INTERCEPT_DR5_READ)
317 | (1 << INTERCEPT_DR6_READ)
318 | (1 << INTERCEPT_DR7_READ)
319 | (1 << INTERCEPT_DR0_WRITE)
320 | (1 << INTERCEPT_DR1_WRITE)
321 | (1 << INTERCEPT_DR2_WRITE)
322 | (1 << INTERCEPT_DR3_WRITE)
323 | (1 << INTERCEPT_DR4_WRITE)
324 | (1 << INTERCEPT_DR5_WRITE)
325 | (1 << INTERCEPT_DR6_WRITE)
326 | (1 << INTERCEPT_DR7_WRITE);
327
328 recalc_intercepts(svm);
329}
330
331static inline void clr_dr_intercepts(struct vcpu_svm *svm)
332{
333 struct vmcb *vmcb = get_host_vmcb(svm);
334
335 vmcb->control.intercept_dr = 0;
336
337 recalc_intercepts(svm);
338}
339
340static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
341{
342 struct vmcb *vmcb = get_host_vmcb(svm);
343
344 vmcb->control.intercept_exceptions |= (1U << bit);
345
346 recalc_intercepts(svm);
347}
348
349static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
350{
351 struct vmcb *vmcb = get_host_vmcb(svm);
352
353 vmcb->control.intercept_exceptions &= ~(1U << bit);
354
355 recalc_intercepts(svm);
356}
357
358static inline void set_intercept(struct vcpu_svm *svm, int bit)
359{
360 struct vmcb *vmcb = get_host_vmcb(svm);
361
362 vmcb->control.intercept |= (1ULL << bit);
363
364 recalc_intercepts(svm);
365}
366
367static inline void clr_intercept(struct vcpu_svm *svm, int bit)
368{
369 struct vmcb *vmcb = get_host_vmcb(svm);
370
371 vmcb->control.intercept &= ~(1ULL << bit);
372
373 recalc_intercepts(svm);
374}
375
376static inline void enable_gif(struct vcpu_svm *svm)
377{
378 svm->vcpu.arch.hflags |= HF_GIF_MASK;
379}
380
381static inline void disable_gif(struct vcpu_svm *svm)
382{
383 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
384}
385
386static inline bool gif_set(struct vcpu_svm *svm)
387{
388 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
389}
390
391static unsigned long iopm_base;
392
393struct kvm_ldttss_desc {
394 u16 limit0;
395 u16 base0;
396 unsigned base1:8, type:5, dpl:2, p:1;
397 unsigned limit1:4, zero0:3, g:1, base2:8;
398 u32 base3;
399 u32 zero1;
400} __attribute__((packed));
401
402struct svm_cpu_data {
403 int cpu;
404
405 u64 asid_generation;
406 u32 max_asid;
407 u32 next_asid;
408 struct kvm_ldttss_desc *tss_desc;
409
410 struct page *save_area;
411};
412
413static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
414
415struct svm_init_data {
416 int cpu;
417 int r;
418};
419
420static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
421
422#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
423#define MSRS_RANGE_SIZE 2048
424#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
425
426static u32 svm_msrpm_offset(u32 msr)
427{
428 u32 offset;
429 int i;
430
431 for (i = 0; i < NUM_MSR_MAPS; i++) {
432 if (msr < msrpm_ranges[i] ||
433 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
434 continue;
435
436 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
437 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
438
439 /* Now we have the u8 offset - but need the u32 offset */
440 return offset / 4;
441 }
442
443 /* MSR not in any range */
444 return MSR_INVALID;
445}
446
447#define MAX_INST_SIZE 15
448
449static inline void clgi(void)
450{
451 asm volatile (__ex(SVM_CLGI));
452}
453
454static inline void stgi(void)
455{
456 asm volatile (__ex(SVM_STGI));
457}
458
459static inline void invlpga(unsigned long addr, u32 asid)
460{
461 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
462}
463
464static int get_npt_level(void)
465{
466#ifdef CONFIG_X86_64
467 return PT64_ROOT_LEVEL;
468#else
469 return PT32E_ROOT_LEVEL;
470#endif
471}
472
473static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
474{
475 vcpu->arch.efer = efer;
476 if (!npt_enabled && !(efer & EFER_LMA))
477 efer &= ~EFER_LME;
478
479 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
480 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
481}
482
483static int is_external_interrupt(u32 info)
484{
485 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
486 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
487}
488
489static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
490{
491 struct vcpu_svm *svm = to_svm(vcpu);
492 u32 ret = 0;
493
494 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
495 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
496 return ret & mask;
497}
498
499static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
500{
501 struct vcpu_svm *svm = to_svm(vcpu);
502
503 if (mask == 0)
504 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
505 else
506 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
507
508}
509
510static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
511{
512 struct vcpu_svm *svm = to_svm(vcpu);
513
514 if (svm->vmcb->control.next_rip != 0)
515 svm->next_rip = svm->vmcb->control.next_rip;
516
517 if (!svm->next_rip) {
518 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
519 EMULATE_DONE)
520 printk(KERN_DEBUG "%s: NOP\n", __func__);
521 return;
522 }
523 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
524 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
525 __func__, kvm_rip_read(vcpu), svm->next_rip);
526
527 kvm_rip_write(vcpu, svm->next_rip);
528 svm_set_interrupt_shadow(vcpu, 0);
529}
530
531static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
532 bool has_error_code, u32 error_code,
533 bool reinject)
534{
535 struct vcpu_svm *svm = to_svm(vcpu);
536
537 /*
538 * If we are within a nested VM we'd better #VMEXIT and let the guest
539 * handle the exception
540 */
541 if (!reinject &&
542 nested_svm_check_exception(svm, nr, has_error_code, error_code))
543 return;
544
545 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
546 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
547
548 /*
549 * For guest debugging where we have to reinject #BP if some
550 * INT3 is guest-owned:
551 * Emulate nRIP by moving RIP forward. Will fail if injection
552 * raises a fault that is not intercepted. Still better than
553 * failing in all cases.
554 */
555 skip_emulated_instruction(&svm->vcpu);
556 rip = kvm_rip_read(&svm->vcpu);
557 svm->int3_rip = rip + svm->vmcb->save.cs.base;
558 svm->int3_injected = rip - old_rip;
559 }
560
561 svm->vmcb->control.event_inj = nr
562 | SVM_EVTINJ_VALID
563 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
564 | SVM_EVTINJ_TYPE_EXEPT;
565 svm->vmcb->control.event_inj_err = error_code;
566}
567
568static void svm_init_erratum_383(void)
569{
570 u32 low, high;
571 int err;
572 u64 val;
573
574 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
575 return;
576
577 /* Use _safe variants to not break nested virtualization */
578 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
579 if (err)
580 return;
581
582 val |= (1ULL << 47);
583
584 low = lower_32_bits(val);
585 high = upper_32_bits(val);
586
587 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
588
589 erratum_383_found = true;
590}
591
592static void svm_init_osvw(struct kvm_vcpu *vcpu)
593{
594 /*
595 * Guests should see errata 400 and 415 as fixed (assuming that
596 * HLT and IO instructions are intercepted).
597 */
598 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
599 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
600
601 /*
602 * By increasing VCPU's osvw.length to 3 we are telling the guest that
603 * all osvw.status bits inside that length, including bit 0 (which is
604 * reserved for erratum 298), are valid. However, if host processor's
605 * osvw_len is 0 then osvw_status[0] carries no information. We need to
606 * be conservative here and therefore we tell the guest that erratum 298
607 * is present (because we really don't know).
608 */
609 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
610 vcpu->arch.osvw.status |= 1;
611}
612
613static int has_svm(void)
614{
615 const char *msg;
616
617 if (!cpu_has_svm(&msg)) {
618 printk(KERN_INFO "has_svm: %s\n", msg);
619 return 0;
620 }
621
622 return 1;
623}
624
625static void svm_hardware_disable(void *garbage)
626{
627 /* Make sure we clean up behind us */
628 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
629 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
630
631 cpu_svm_disable();
632
633 amd_pmu_disable_virt();
634}
635
636static int svm_hardware_enable(void *garbage)
637{
638
639 struct svm_cpu_data *sd;
640 uint64_t efer;
641 struct desc_ptr gdt_descr;
642 struct desc_struct *gdt;
643 int me = raw_smp_processor_id();
644
645 rdmsrl(MSR_EFER, efer);
646 if (efer & EFER_SVME)
647 return -EBUSY;
648
649 if (!has_svm()) {
650 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
651 return -EINVAL;
652 }
653 sd = per_cpu(svm_data, me);
654 if (!sd) {
655 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
656 return -EINVAL;
657 }
658
659 sd->asid_generation = 1;
660 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
661 sd->next_asid = sd->max_asid + 1;
662
663 native_store_gdt(&gdt_descr);
664 gdt = (struct desc_struct *)gdt_descr.address;
665 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
666
667 wrmsrl(MSR_EFER, efer | EFER_SVME);
668
669 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
670
671 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
672 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
673 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
674 }
675
676
677 /*
678 * Get OSVW bits.
679 *
680 * Note that it is possible to have a system with mixed processor
681 * revisions and therefore different OSVW bits. If bits are not the same
682 * on different processors then choose the worst case (i.e. if erratum
683 * is present on one processor and not on another then assume that the
684 * erratum is present everywhere).
685 */
686 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
687 uint64_t len, status = 0;
688 int err;
689
690 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
691 if (!err)
692 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
693 &err);
694
695 if (err)
696 osvw_status = osvw_len = 0;
697 else {
698 if (len < osvw_len)
699 osvw_len = len;
700 osvw_status |= status;
701 osvw_status &= (1ULL << osvw_len) - 1;
702 }
703 } else
704 osvw_status = osvw_len = 0;
705
706 svm_init_erratum_383();
707
708 amd_pmu_enable_virt();
709
710 return 0;
711}
712
713static void svm_cpu_uninit(int cpu)
714{
715 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
716
717 if (!sd)
718 return;
719
720 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
721 __free_page(sd->save_area);
722 kfree(sd);
723}
724
725static int svm_cpu_init(int cpu)
726{
727 struct svm_cpu_data *sd;
728 int r;
729
730 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
731 if (!sd)
732 return -ENOMEM;
733 sd->cpu = cpu;
734 sd->save_area = alloc_page(GFP_KERNEL);
735 r = -ENOMEM;
736 if (!sd->save_area)
737 goto err_1;
738
739 per_cpu(svm_data, cpu) = sd;
740
741 return 0;
742
743err_1:
744 kfree(sd);
745 return r;
746
747}
748
749static bool valid_msr_intercept(u32 index)
750{
751 int i;
752
753 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
754 if (direct_access_msrs[i].index == index)
755 return true;
756
757 return false;
758}
759
760static void set_msr_interception(u32 *msrpm, unsigned msr,
761 int read, int write)
762{
763 u8 bit_read, bit_write;
764 unsigned long tmp;
765 u32 offset;
766
767 /*
768 * If this warning triggers extend the direct_access_msrs list at the
769 * beginning of the file
770 */
771 WARN_ON(!valid_msr_intercept(msr));
772
773 offset = svm_msrpm_offset(msr);
774 bit_read = 2 * (msr & 0x0f);
775 bit_write = 2 * (msr & 0x0f) + 1;
776 tmp = msrpm[offset];
777
778 BUG_ON(offset == MSR_INVALID);
779
780 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
781 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
782
783 msrpm[offset] = tmp;
784}
785
786static void svm_vcpu_init_msrpm(u32 *msrpm)
787{
788 int i;
789
790 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
791
792 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
793 if (!direct_access_msrs[i].always)
794 continue;
795
796 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
797 }
798}
799
800static void add_msr_offset(u32 offset)
801{
802 int i;
803
804 for (i = 0; i < MSRPM_OFFSETS; ++i) {
805
806 /* Offset already in list? */
807 if (msrpm_offsets[i] == offset)
808 return;
809
810 /* Slot used by another offset? */
811 if (msrpm_offsets[i] != MSR_INVALID)
812 continue;
813
814 /* Add offset to list */
815 msrpm_offsets[i] = offset;
816
817 return;
818 }
819
820 /*
821 * If this BUG triggers the msrpm_offsets table has an overflow. Just
822 * increase MSRPM_OFFSETS in this case.
823 */
824 BUG();
825}
826
827static void init_msrpm_offsets(void)
828{
829 int i;
830
831 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
832
833 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
834 u32 offset;
835
836 offset = svm_msrpm_offset(direct_access_msrs[i].index);
837 BUG_ON(offset == MSR_INVALID);
838
839 add_msr_offset(offset);
840 }
841}
842
843static void svm_enable_lbrv(struct vcpu_svm *svm)
844{
845 u32 *msrpm = svm->msrpm;
846
847 svm->vmcb->control.lbr_ctl = 1;
848 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
849 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
850 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
851 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
852}
853
854static void svm_disable_lbrv(struct vcpu_svm *svm)
855{
856 u32 *msrpm = svm->msrpm;
857
858 svm->vmcb->control.lbr_ctl = 0;
859 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
860 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
861 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
862 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
863}
864
865static __init int svm_hardware_setup(void)
866{
867 int cpu;
868 struct page *iopm_pages;
869 void *iopm_va;
870 int r;
871
872 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
873
874 if (!iopm_pages)
875 return -ENOMEM;
876
877 iopm_va = page_address(iopm_pages);
878 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
879 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
880
881 init_msrpm_offsets();
882
883 if (boot_cpu_has(X86_FEATURE_NX))
884 kvm_enable_efer_bits(EFER_NX);
885
886 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
887 kvm_enable_efer_bits(EFER_FFXSR);
888
889 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
890 u64 max;
891
892 kvm_has_tsc_control = true;
893
894 /*
895 * Make sure the user can only configure tsc_khz values that
896 * fit into a signed integer.
897 * A min value is not calculated needed because it will always
898 * be 1 on all machines and a value of 0 is used to disable
899 * tsc-scaling for the vcpu.
900 */
901 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
902
903 kvm_max_guest_tsc_khz = max;
904 }
905
906 if (nested) {
907 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
908 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
909 }
910
911 for_each_possible_cpu(cpu) {
912 r = svm_cpu_init(cpu);
913 if (r)
914 goto err;
915 }
916
917 if (!boot_cpu_has(X86_FEATURE_NPT))
918 npt_enabled = false;
919
920 if (npt_enabled && !npt) {
921 printk(KERN_INFO "kvm: Nested Paging disabled\n");
922 npt_enabled = false;
923 }
924
925 if (npt_enabled) {
926 printk(KERN_INFO "kvm: Nested Paging enabled\n");
927 kvm_enable_tdp();
928 } else
929 kvm_disable_tdp();
930
931 return 0;
932
933err:
934 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
935 iopm_base = 0;
936 return r;
937}
938
939static __exit void svm_hardware_unsetup(void)
940{
941 int cpu;
942
943 for_each_possible_cpu(cpu)
944 svm_cpu_uninit(cpu);
945
946 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
947 iopm_base = 0;
948}
949
950static void init_seg(struct vmcb_seg *seg)
951{
952 seg->selector = 0;
953 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
954 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
955 seg->limit = 0xffff;
956 seg->base = 0;
957}
958
959static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
960{
961 seg->selector = 0;
962 seg->attrib = SVM_SELECTOR_P_MASK | type;
963 seg->limit = 0xffff;
964 seg->base = 0;
965}
966
967static u64 __scale_tsc(u64 ratio, u64 tsc)
968{
969 u64 mult, frac, _tsc;
970
971 mult = ratio >> 32;
972 frac = ratio & ((1ULL << 32) - 1);
973
974 _tsc = tsc;
975 _tsc *= mult;
976 _tsc += (tsc >> 32) * frac;
977 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
978
979 return _tsc;
980}
981
982static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
983{
984 struct vcpu_svm *svm = to_svm(vcpu);
985 u64 _tsc = tsc;
986
987 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
988 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
989
990 return _tsc;
991}
992
993static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
994{
995 struct vcpu_svm *svm = to_svm(vcpu);
996 u64 ratio;
997 u64 khz;
998
999 /* Guest TSC same frequency as host TSC? */
1000 if (!scale) {
1001 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1002 return;
1003 }
1004
1005 /* TSC scaling supported? */
1006 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007 if (user_tsc_khz > tsc_khz) {
1008 vcpu->arch.tsc_catchup = 1;
1009 vcpu->arch.tsc_always_catchup = 1;
1010 } else
1011 WARN(1, "user requested TSC rate below hardware speed\n");
1012 return;
1013 }
1014
1015 khz = user_tsc_khz;
1016
1017 /* TSC scaling required - calculate ratio */
1018 ratio = khz << 32;
1019 do_div(ratio, tsc_khz);
1020
1021 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1023 user_tsc_khz);
1024 return;
1025 }
1026 svm->tsc_ratio = ratio;
1027}
1028
1029static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1030{
1031 struct vcpu_svm *svm = to_svm(vcpu);
1032
1033 return svm->vmcb->control.tsc_offset;
1034}
1035
1036static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1037{
1038 struct vcpu_svm *svm = to_svm(vcpu);
1039 u64 g_tsc_offset = 0;
1040
1041 if (is_guest_mode(vcpu)) {
1042 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043 svm->nested.hsave->control.tsc_offset;
1044 svm->nested.hsave->control.tsc_offset = offset;
1045 } else
1046 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047 svm->vmcb->control.tsc_offset,
1048 offset);
1049
1050 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1051
1052 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1053}
1054
1055static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1056{
1057 struct vcpu_svm *svm = to_svm(vcpu);
1058
1059 WARN_ON(adjustment < 0);
1060 if (host)
1061 adjustment = svm_scale_tsc(vcpu, adjustment);
1062
1063 svm->vmcb->control.tsc_offset += adjustment;
1064 if (is_guest_mode(vcpu))
1065 svm->nested.hsave->control.tsc_offset += adjustment;
1066 else
1067 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1068 svm->vmcb->control.tsc_offset - adjustment,
1069 svm->vmcb->control.tsc_offset);
1070
1071 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1072}
1073
1074static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1075{
1076 u64 tsc;
1077
1078 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1079
1080 return target_tsc - tsc;
1081}
1082
1083static void init_vmcb(struct vcpu_svm *svm)
1084{
1085 struct vmcb_control_area *control = &svm->vmcb->control;
1086 struct vmcb_save_area *save = &svm->vmcb->save;
1087
1088 svm->vcpu.fpu_active = 1;
1089 svm->vcpu.arch.hflags = 0;
1090
1091 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1092 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1093 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1094 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1095 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1096 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1097 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1098
1099 set_dr_intercepts(svm);
1100
1101 set_exception_intercept(svm, PF_VECTOR);
1102 set_exception_intercept(svm, UD_VECTOR);
1103 set_exception_intercept(svm, MC_VECTOR);
1104
1105 set_intercept(svm, INTERCEPT_INTR);
1106 set_intercept(svm, INTERCEPT_NMI);
1107 set_intercept(svm, INTERCEPT_SMI);
1108 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1109 set_intercept(svm, INTERCEPT_RDPMC);
1110 set_intercept(svm, INTERCEPT_CPUID);
1111 set_intercept(svm, INTERCEPT_INVD);
1112 set_intercept(svm, INTERCEPT_HLT);
1113 set_intercept(svm, INTERCEPT_INVLPG);
1114 set_intercept(svm, INTERCEPT_INVLPGA);
1115 set_intercept(svm, INTERCEPT_IOIO_PROT);
1116 set_intercept(svm, INTERCEPT_MSR_PROT);
1117 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1118 set_intercept(svm, INTERCEPT_SHUTDOWN);
1119 set_intercept(svm, INTERCEPT_VMRUN);
1120 set_intercept(svm, INTERCEPT_VMMCALL);
1121 set_intercept(svm, INTERCEPT_VMLOAD);
1122 set_intercept(svm, INTERCEPT_VMSAVE);
1123 set_intercept(svm, INTERCEPT_STGI);
1124 set_intercept(svm, INTERCEPT_CLGI);
1125 set_intercept(svm, INTERCEPT_SKINIT);
1126 set_intercept(svm, INTERCEPT_WBINVD);
1127 set_intercept(svm, INTERCEPT_MONITOR);
1128 set_intercept(svm, INTERCEPT_MWAIT);
1129 set_intercept(svm, INTERCEPT_XSETBV);
1130
1131 control->iopm_base_pa = iopm_base;
1132 control->msrpm_base_pa = __pa(svm->msrpm);
1133 control->int_ctl = V_INTR_MASKING_MASK;
1134
1135 init_seg(&save->es);
1136 init_seg(&save->ss);
1137 init_seg(&save->ds);
1138 init_seg(&save->fs);
1139 init_seg(&save->gs);
1140
1141 save->cs.selector = 0xf000;
1142 save->cs.base = 0xffff0000;
1143 /* Executable/Readable Code Segment */
1144 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1145 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1146 save->cs.limit = 0xffff;
1147
1148 save->gdtr.limit = 0xffff;
1149 save->idtr.limit = 0xffff;
1150
1151 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1152 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1153
1154 svm_set_efer(&svm->vcpu, 0);
1155 save->dr6 = 0xffff0ff0;
1156 kvm_set_rflags(&svm->vcpu, 2);
1157 save->rip = 0x0000fff0;
1158 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1159
1160 /*
1161 * This is the guest-visible cr0 value.
1162 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1163 */
1164 svm->vcpu.arch.cr0 = 0;
1165 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1166
1167 save->cr4 = X86_CR4_PAE;
1168 /* rdx = ?? */
1169
1170 if (npt_enabled) {
1171 /* Setup VMCB for Nested Paging */
1172 control->nested_ctl = 1;
1173 clr_intercept(svm, INTERCEPT_INVLPG);
1174 clr_exception_intercept(svm, PF_VECTOR);
1175 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1176 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1177 save->g_pat = 0x0007040600070406ULL;
1178 save->cr3 = 0;
1179 save->cr4 = 0;
1180 }
1181 svm->asid_generation = 0;
1182
1183 svm->nested.vmcb = 0;
1184 svm->vcpu.arch.hflags = 0;
1185
1186 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1187 control->pause_filter_count = 3000;
1188 set_intercept(svm, INTERCEPT_PAUSE);
1189 }
1190
1191 mark_all_dirty(svm->vmcb);
1192
1193 enable_gif(svm);
1194}
1195
1196static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1197{
1198 struct vcpu_svm *svm = to_svm(vcpu);
1199 u32 dummy;
1200 u32 eax = 1;
1201
1202 init_vmcb(svm);
1203
1204 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1205 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1206}
1207
1208static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1209{
1210 struct vcpu_svm *svm;
1211 struct page *page;
1212 struct page *msrpm_pages;
1213 struct page *hsave_page;
1214 struct page *nested_msrpm_pages;
1215 int err;
1216
1217 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1218 if (!svm) {
1219 err = -ENOMEM;
1220 goto out;
1221 }
1222
1223 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1224
1225 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1226 if (err)
1227 goto free_svm;
1228
1229 err = -ENOMEM;
1230 page = alloc_page(GFP_KERNEL);
1231 if (!page)
1232 goto uninit;
1233
1234 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1235 if (!msrpm_pages)
1236 goto free_page1;
1237
1238 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1239 if (!nested_msrpm_pages)
1240 goto free_page2;
1241
1242 hsave_page = alloc_page(GFP_KERNEL);
1243 if (!hsave_page)
1244 goto free_page3;
1245
1246 svm->nested.hsave = page_address(hsave_page);
1247
1248 svm->msrpm = page_address(msrpm_pages);
1249 svm_vcpu_init_msrpm(svm->msrpm);
1250
1251 svm->nested.msrpm = page_address(nested_msrpm_pages);
1252 svm_vcpu_init_msrpm(svm->nested.msrpm);
1253
1254 svm->vmcb = page_address(page);
1255 clear_page(svm->vmcb);
1256 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1257 svm->asid_generation = 0;
1258 init_vmcb(svm);
1259
1260 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1261 if (kvm_vcpu_is_bsp(&svm->vcpu))
1262 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1263
1264 svm_init_osvw(&svm->vcpu);
1265
1266 return &svm->vcpu;
1267
1268free_page3:
1269 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1270free_page2:
1271 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1272free_page1:
1273 __free_page(page);
1274uninit:
1275 kvm_vcpu_uninit(&svm->vcpu);
1276free_svm:
1277 kmem_cache_free(kvm_vcpu_cache, svm);
1278out:
1279 return ERR_PTR(err);
1280}
1281
1282static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1283{
1284 struct vcpu_svm *svm = to_svm(vcpu);
1285
1286 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1287 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1288 __free_page(virt_to_page(svm->nested.hsave));
1289 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1290 kvm_vcpu_uninit(vcpu);
1291 kmem_cache_free(kvm_vcpu_cache, svm);
1292}
1293
1294static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1295{
1296 struct vcpu_svm *svm = to_svm(vcpu);
1297 int i;
1298
1299 if (unlikely(cpu != vcpu->cpu)) {
1300 svm->asid_generation = 0;
1301 mark_all_dirty(svm->vmcb);
1302 }
1303
1304#ifdef CONFIG_X86_64
1305 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1306#endif
1307 savesegment(fs, svm->host.fs);
1308 savesegment(gs, svm->host.gs);
1309 svm->host.ldt = kvm_read_ldt();
1310
1311 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1312 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1313
1314 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1315 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1316 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1317 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1318 }
1319}
1320
1321static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1322{
1323 struct vcpu_svm *svm = to_svm(vcpu);
1324 int i;
1325
1326 ++vcpu->stat.host_state_reload;
1327 kvm_load_ldt(svm->host.ldt);
1328#ifdef CONFIG_X86_64
1329 loadsegment(fs, svm->host.fs);
1330 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1331 load_gs_index(svm->host.gs);
1332#else
1333#ifdef CONFIG_X86_32_LAZY_GS
1334 loadsegment(gs, svm->host.gs);
1335#endif
1336#endif
1337 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1338 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1339}
1340
1341static void svm_update_cpl(struct kvm_vcpu *vcpu)
1342{
1343 struct vcpu_svm *svm = to_svm(vcpu);
1344 int cpl;
1345
1346 if (!is_protmode(vcpu))
1347 cpl = 0;
1348 else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1349 cpl = 3;
1350 else
1351 cpl = svm->vmcb->save.cs.selector & 0x3;
1352
1353 svm->vmcb->save.cpl = cpl;
1354}
1355
1356static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1357{
1358 return to_svm(vcpu)->vmcb->save.rflags;
1359}
1360
1361static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1362{
1363 unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1364
1365 to_svm(vcpu)->vmcb->save.rflags = rflags;
1366 if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1367 svm_update_cpl(vcpu);
1368}
1369
1370static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1371{
1372 switch (reg) {
1373 case VCPU_EXREG_PDPTR:
1374 BUG_ON(!npt_enabled);
1375 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1376 break;
1377 default:
1378 BUG();
1379 }
1380}
1381
1382static void svm_set_vintr(struct vcpu_svm *svm)
1383{
1384 set_intercept(svm, INTERCEPT_VINTR);
1385}
1386
1387static void svm_clear_vintr(struct vcpu_svm *svm)
1388{
1389 clr_intercept(svm, INTERCEPT_VINTR);
1390}
1391
1392static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1393{
1394 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1395
1396 switch (seg) {
1397 case VCPU_SREG_CS: return &save->cs;
1398 case VCPU_SREG_DS: return &save->ds;
1399 case VCPU_SREG_ES: return &save->es;
1400 case VCPU_SREG_FS: return &save->fs;
1401 case VCPU_SREG_GS: return &save->gs;
1402 case VCPU_SREG_SS: return &save->ss;
1403 case VCPU_SREG_TR: return &save->tr;
1404 case VCPU_SREG_LDTR: return &save->ldtr;
1405 }
1406 BUG();
1407 return NULL;
1408}
1409
1410static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1411{
1412 struct vmcb_seg *s = svm_seg(vcpu, seg);
1413
1414 return s->base;
1415}
1416
1417static void svm_get_segment(struct kvm_vcpu *vcpu,
1418 struct kvm_segment *var, int seg)
1419{
1420 struct vmcb_seg *s = svm_seg(vcpu, seg);
1421
1422 var->base = s->base;
1423 var->limit = s->limit;
1424 var->selector = s->selector;
1425 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1426 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1427 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1428 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1429 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1430 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1431 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1432 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1433
1434 /*
1435 * AMD's VMCB does not have an explicit unusable field, so emulate it
1436 * for cross vendor migration purposes by "not present"
1437 */
1438 var->unusable = !var->present || (var->type == 0);
1439
1440 switch (seg) {
1441 case VCPU_SREG_CS:
1442 /*
1443 * SVM always stores 0 for the 'G' bit in the CS selector in
1444 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1445 * Intel's VMENTRY has a check on the 'G' bit.
1446 */
1447 var->g = s->limit > 0xfffff;
1448 break;
1449 case VCPU_SREG_TR:
1450 /*
1451 * Work around a bug where the busy flag in the tr selector
1452 * isn't exposed
1453 */
1454 var->type |= 0x2;
1455 break;
1456 case VCPU_SREG_DS:
1457 case VCPU_SREG_ES:
1458 case VCPU_SREG_FS:
1459 case VCPU_SREG_GS:
1460 /*
1461 * The accessed bit must always be set in the segment
1462 * descriptor cache, although it can be cleared in the
1463 * descriptor, the cached bit always remains at 1. Since
1464 * Intel has a check on this, set it here to support
1465 * cross-vendor migration.
1466 */
1467 if (!var->unusable)
1468 var->type |= 0x1;
1469 break;
1470 case VCPU_SREG_SS:
1471 /*
1472 * On AMD CPUs sometimes the DB bit in the segment
1473 * descriptor is left as 1, although the whole segment has
1474 * been made unusable. Clear it here to pass an Intel VMX
1475 * entry check when cross vendor migrating.
1476 */
1477 if (var->unusable)
1478 var->db = 0;
1479 break;
1480 }
1481}
1482
1483static int svm_get_cpl(struct kvm_vcpu *vcpu)
1484{
1485 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1486
1487 return save->cpl;
1488}
1489
1490static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1491{
1492 struct vcpu_svm *svm = to_svm(vcpu);
1493
1494 dt->size = svm->vmcb->save.idtr.limit;
1495 dt->address = svm->vmcb->save.idtr.base;
1496}
1497
1498static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1499{
1500 struct vcpu_svm *svm = to_svm(vcpu);
1501
1502 svm->vmcb->save.idtr.limit = dt->size;
1503 svm->vmcb->save.idtr.base = dt->address ;
1504 mark_dirty(svm->vmcb, VMCB_DT);
1505}
1506
1507static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1508{
1509 struct vcpu_svm *svm = to_svm(vcpu);
1510
1511 dt->size = svm->vmcb->save.gdtr.limit;
1512 dt->address = svm->vmcb->save.gdtr.base;
1513}
1514
1515static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1516{
1517 struct vcpu_svm *svm = to_svm(vcpu);
1518
1519 svm->vmcb->save.gdtr.limit = dt->size;
1520 svm->vmcb->save.gdtr.base = dt->address ;
1521 mark_dirty(svm->vmcb, VMCB_DT);
1522}
1523
1524static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1525{
1526}
1527
1528static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1529{
1530}
1531
1532static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1533{
1534}
1535
1536static void update_cr0_intercept(struct vcpu_svm *svm)
1537{
1538 ulong gcr0 = svm->vcpu.arch.cr0;
1539 u64 *hcr0 = &svm->vmcb->save.cr0;
1540
1541 if (!svm->vcpu.fpu_active)
1542 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1543 else
1544 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1545 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1546
1547 mark_dirty(svm->vmcb, VMCB_CR);
1548
1549 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1550 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1551 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1552 } else {
1553 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1554 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1555 }
1556}
1557
1558static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1559{
1560 struct vcpu_svm *svm = to_svm(vcpu);
1561
1562#ifdef CONFIG_X86_64
1563 if (vcpu->arch.efer & EFER_LME) {
1564 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1565 vcpu->arch.efer |= EFER_LMA;
1566 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1567 }
1568
1569 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1570 vcpu->arch.efer &= ~EFER_LMA;
1571 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1572 }
1573 }
1574#endif
1575 vcpu->arch.cr0 = cr0;
1576
1577 if (!npt_enabled)
1578 cr0 |= X86_CR0_PG | X86_CR0_WP;
1579
1580 if (!vcpu->fpu_active)
1581 cr0 |= X86_CR0_TS;
1582 /*
1583 * re-enable caching here because the QEMU bios
1584 * does not do it - this results in some delay at
1585 * reboot
1586 */
1587 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1588 svm->vmcb->save.cr0 = cr0;
1589 mark_dirty(svm->vmcb, VMCB_CR);
1590 update_cr0_intercept(svm);
1591}
1592
1593static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1594{
1595 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1596 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1597
1598 if (cr4 & X86_CR4_VMXE)
1599 return 1;
1600
1601 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1602 svm_flush_tlb(vcpu);
1603
1604 vcpu->arch.cr4 = cr4;
1605 if (!npt_enabled)
1606 cr4 |= X86_CR4_PAE;
1607 cr4 |= host_cr4_mce;
1608 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1609 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1610 return 0;
1611}
1612
1613static void svm_set_segment(struct kvm_vcpu *vcpu,
1614 struct kvm_segment *var, int seg)
1615{
1616 struct vcpu_svm *svm = to_svm(vcpu);
1617 struct vmcb_seg *s = svm_seg(vcpu, seg);
1618
1619 s->base = var->base;
1620 s->limit = var->limit;
1621 s->selector = var->selector;
1622 if (var->unusable)
1623 s->attrib = 0;
1624 else {
1625 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1626 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1627 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1628 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1629 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1630 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1631 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1632 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1633 }
1634 if (seg == VCPU_SREG_CS)
1635 svm_update_cpl(vcpu);
1636
1637 mark_dirty(svm->vmcb, VMCB_SEG);
1638}
1639
1640static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1641{
1642 struct vcpu_svm *svm = to_svm(vcpu);
1643
1644 clr_exception_intercept(svm, DB_VECTOR);
1645 clr_exception_intercept(svm, BP_VECTOR);
1646
1647 if (svm->nmi_singlestep)
1648 set_exception_intercept(svm, DB_VECTOR);
1649
1650 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1651 if (vcpu->guest_debug &
1652 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1653 set_exception_intercept(svm, DB_VECTOR);
1654 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1655 set_exception_intercept(svm, BP_VECTOR);
1656 } else
1657 vcpu->guest_debug = 0;
1658}
1659
1660static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1661{
1662 if (sd->next_asid > sd->max_asid) {
1663 ++sd->asid_generation;
1664 sd->next_asid = 1;
1665 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1666 }
1667
1668 svm->asid_generation = sd->asid_generation;
1669 svm->vmcb->control.asid = sd->next_asid++;
1670
1671 mark_dirty(svm->vmcb, VMCB_ASID);
1672}
1673
1674static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1675{
1676 return to_svm(vcpu)->vmcb->save.dr6;
1677}
1678
1679static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1680{
1681 struct vcpu_svm *svm = to_svm(vcpu);
1682
1683 svm->vmcb->save.dr6 = value;
1684 mark_dirty(svm->vmcb, VMCB_DR);
1685}
1686
1687static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1688{
1689 struct vcpu_svm *svm = to_svm(vcpu);
1690
1691 get_debugreg(vcpu->arch.db[0], 0);
1692 get_debugreg(vcpu->arch.db[1], 1);
1693 get_debugreg(vcpu->arch.db[2], 2);
1694 get_debugreg(vcpu->arch.db[3], 3);
1695 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1696 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1697
1698 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1699 set_dr_intercepts(svm);
1700}
1701
1702static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1703{
1704 struct vcpu_svm *svm = to_svm(vcpu);
1705
1706 svm->vmcb->save.dr7 = value;
1707 mark_dirty(svm->vmcb, VMCB_DR);
1708}
1709
1710static int pf_interception(struct vcpu_svm *svm)
1711{
1712 u64 fault_address = svm->vmcb->control.exit_info_2;
1713 u32 error_code;
1714 int r = 1;
1715
1716 switch (svm->apf_reason) {
1717 default:
1718 error_code = svm->vmcb->control.exit_info_1;
1719
1720 trace_kvm_page_fault(fault_address, error_code);
1721 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1722 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1723 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1724 svm->vmcb->control.insn_bytes,
1725 svm->vmcb->control.insn_len);
1726 break;
1727 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1728 svm->apf_reason = 0;
1729 local_irq_disable();
1730 kvm_async_pf_task_wait(fault_address);
1731 local_irq_enable();
1732 break;
1733 case KVM_PV_REASON_PAGE_READY:
1734 svm->apf_reason = 0;
1735 local_irq_disable();
1736 kvm_async_pf_task_wake(fault_address);
1737 local_irq_enable();
1738 break;
1739 }
1740 return r;
1741}
1742
1743static int db_interception(struct vcpu_svm *svm)
1744{
1745 struct kvm_run *kvm_run = svm->vcpu.run;
1746
1747 if (!(svm->vcpu.guest_debug &
1748 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1749 !svm->nmi_singlestep) {
1750 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1751 return 1;
1752 }
1753
1754 if (svm->nmi_singlestep) {
1755 svm->nmi_singlestep = false;
1756 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1757 svm->vmcb->save.rflags &=
1758 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1759 update_db_bp_intercept(&svm->vcpu);
1760 }
1761
1762 if (svm->vcpu.guest_debug &
1763 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1764 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1765 kvm_run->debug.arch.pc =
1766 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1767 kvm_run->debug.arch.exception = DB_VECTOR;
1768 return 0;
1769 }
1770
1771 return 1;
1772}
1773
1774static int bp_interception(struct vcpu_svm *svm)
1775{
1776 struct kvm_run *kvm_run = svm->vcpu.run;
1777
1778 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1779 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1780 kvm_run->debug.arch.exception = BP_VECTOR;
1781 return 0;
1782}
1783
1784static int ud_interception(struct vcpu_svm *svm)
1785{
1786 int er;
1787
1788 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1789 if (er != EMULATE_DONE)
1790 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1791 return 1;
1792}
1793
1794static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1795{
1796 struct vcpu_svm *svm = to_svm(vcpu);
1797
1798 clr_exception_intercept(svm, NM_VECTOR);
1799
1800 svm->vcpu.fpu_active = 1;
1801 update_cr0_intercept(svm);
1802}
1803
1804static int nm_interception(struct vcpu_svm *svm)
1805{
1806 svm_fpu_activate(&svm->vcpu);
1807 return 1;
1808}
1809
1810static bool is_erratum_383(void)
1811{
1812 int err, i;
1813 u64 value;
1814
1815 if (!erratum_383_found)
1816 return false;
1817
1818 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1819 if (err)
1820 return false;
1821
1822 /* Bit 62 may or may not be set for this mce */
1823 value &= ~(1ULL << 62);
1824
1825 if (value != 0xb600000000010015ULL)
1826 return false;
1827
1828 /* Clear MCi_STATUS registers */
1829 for (i = 0; i < 6; ++i)
1830 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1831
1832 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1833 if (!err) {
1834 u32 low, high;
1835
1836 value &= ~(1ULL << 2);
1837 low = lower_32_bits(value);
1838 high = upper_32_bits(value);
1839
1840 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1841 }
1842
1843 /* Flush tlb to evict multi-match entries */
1844 __flush_tlb_all();
1845
1846 return true;
1847}
1848
1849static void svm_handle_mce(struct vcpu_svm *svm)
1850{
1851 if (is_erratum_383()) {
1852 /*
1853 * Erratum 383 triggered. Guest state is corrupt so kill the
1854 * guest.
1855 */
1856 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1857
1858 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1859
1860 return;
1861 }
1862
1863 /*
1864 * On an #MC intercept the MCE handler is not called automatically in
1865 * the host. So do it by hand here.
1866 */
1867 asm volatile (
1868 "int $0x12\n");
1869 /* not sure if we ever come back to this point */
1870
1871 return;
1872}
1873
1874static int mc_interception(struct vcpu_svm *svm)
1875{
1876 return 1;
1877}
1878
1879static int shutdown_interception(struct vcpu_svm *svm)
1880{
1881 struct kvm_run *kvm_run = svm->vcpu.run;
1882
1883 /*
1884 * VMCB is undefined after a SHUTDOWN intercept
1885 * so reinitialize it.
1886 */
1887 clear_page(svm->vmcb);
1888 init_vmcb(svm);
1889
1890 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1891 return 0;
1892}
1893
1894static int io_interception(struct vcpu_svm *svm)
1895{
1896 struct kvm_vcpu *vcpu = &svm->vcpu;
1897 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1898 int size, in, string;
1899 unsigned port;
1900
1901 ++svm->vcpu.stat.io_exits;
1902 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1903 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1904 if (string || in)
1905 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1906
1907 port = io_info >> 16;
1908 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1909 svm->next_rip = svm->vmcb->control.exit_info_2;
1910 skip_emulated_instruction(&svm->vcpu);
1911
1912 return kvm_fast_pio_out(vcpu, size, port);
1913}
1914
1915static int nmi_interception(struct vcpu_svm *svm)
1916{
1917 return 1;
1918}
1919
1920static int intr_interception(struct vcpu_svm *svm)
1921{
1922 ++svm->vcpu.stat.irq_exits;
1923 return 1;
1924}
1925
1926static int nop_on_interception(struct vcpu_svm *svm)
1927{
1928 return 1;
1929}
1930
1931static int halt_interception(struct vcpu_svm *svm)
1932{
1933 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1934 skip_emulated_instruction(&svm->vcpu);
1935 return kvm_emulate_halt(&svm->vcpu);
1936}
1937
1938static int vmmcall_interception(struct vcpu_svm *svm)
1939{
1940 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1941 skip_emulated_instruction(&svm->vcpu);
1942 kvm_emulate_hypercall(&svm->vcpu);
1943 return 1;
1944}
1945
1946static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1947{
1948 struct vcpu_svm *svm = to_svm(vcpu);
1949
1950 return svm->nested.nested_cr3;
1951}
1952
1953static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1954{
1955 struct vcpu_svm *svm = to_svm(vcpu);
1956 u64 cr3 = svm->nested.nested_cr3;
1957 u64 pdpte;
1958 int ret;
1959
1960 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1961 offset_in_page(cr3) + index * 8, 8);
1962 if (ret)
1963 return 0;
1964 return pdpte;
1965}
1966
1967static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1968 unsigned long root)
1969{
1970 struct vcpu_svm *svm = to_svm(vcpu);
1971
1972 svm->vmcb->control.nested_cr3 = root;
1973 mark_dirty(svm->vmcb, VMCB_NPT);
1974 svm_flush_tlb(vcpu);
1975}
1976
1977static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1978 struct x86_exception *fault)
1979{
1980 struct vcpu_svm *svm = to_svm(vcpu);
1981
1982 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1983 svm->vmcb->control.exit_code_hi = 0;
1984 svm->vmcb->control.exit_info_1 = fault->error_code;
1985 svm->vmcb->control.exit_info_2 = fault->address;
1986
1987 nested_svm_vmexit(svm);
1988}
1989
1990static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1991{
1992 kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1993
1994 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1995 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1996 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1997 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1998 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1999 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2000}
2001
2002static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2003{
2004 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2005}
2006
2007static int nested_svm_check_permissions(struct vcpu_svm *svm)
2008{
2009 if (!(svm->vcpu.arch.efer & EFER_SVME)
2010 || !is_paging(&svm->vcpu)) {
2011 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2012 return 1;
2013 }
2014
2015 if (svm->vmcb->save.cpl) {
2016 kvm_inject_gp(&svm->vcpu, 0);
2017 return 1;
2018 }
2019
2020 return 0;
2021}
2022
2023static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2024 bool has_error_code, u32 error_code)
2025{
2026 int vmexit;
2027
2028 if (!is_guest_mode(&svm->vcpu))
2029 return 0;
2030
2031 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2032 svm->vmcb->control.exit_code_hi = 0;
2033 svm->vmcb->control.exit_info_1 = error_code;
2034 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2035
2036 vmexit = nested_svm_intercept(svm);
2037 if (vmexit == NESTED_EXIT_DONE)
2038 svm->nested.exit_required = true;
2039
2040 return vmexit;
2041}
2042
2043/* This function returns true if it is save to enable the irq window */
2044static inline bool nested_svm_intr(struct vcpu_svm *svm)
2045{
2046 if (!is_guest_mode(&svm->vcpu))
2047 return true;
2048
2049 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2050 return true;
2051
2052 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2053 return false;
2054
2055 /*
2056 * if vmexit was already requested (by intercepted exception
2057 * for instance) do not overwrite it with "external interrupt"
2058 * vmexit.
2059 */
2060 if (svm->nested.exit_required)
2061 return false;
2062
2063 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2064 svm->vmcb->control.exit_info_1 = 0;
2065 svm->vmcb->control.exit_info_2 = 0;
2066
2067 if (svm->nested.intercept & 1ULL) {
2068 /*
2069 * The #vmexit can't be emulated here directly because this
2070 * code path runs with irqs and preemption disabled. A
2071 * #vmexit emulation might sleep. Only signal request for
2072 * the #vmexit here.
2073 */
2074 svm->nested.exit_required = true;
2075 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2076 return false;
2077 }
2078
2079 return true;
2080}
2081
2082/* This function returns true if it is save to enable the nmi window */
2083static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2084{
2085 if (!is_guest_mode(&svm->vcpu))
2086 return true;
2087
2088 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2089 return true;
2090
2091 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2092 svm->nested.exit_required = true;
2093
2094 return false;
2095}
2096
2097static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2098{
2099 struct page *page;
2100
2101 might_sleep();
2102
2103 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2104 if (is_error_page(page))
2105 goto error;
2106
2107 *_page = page;
2108
2109 return kmap(page);
2110
2111error:
2112 kvm_inject_gp(&svm->vcpu, 0);
2113
2114 return NULL;
2115}
2116
2117static void nested_svm_unmap(struct page *page)
2118{
2119 kunmap(page);
2120 kvm_release_page_dirty(page);
2121}
2122
2123static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2124{
2125 unsigned port;
2126 u8 val, bit;
2127 u64 gpa;
2128
2129 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2130 return NESTED_EXIT_HOST;
2131
2132 port = svm->vmcb->control.exit_info_1 >> 16;
2133 gpa = svm->nested.vmcb_iopm + (port / 8);
2134 bit = port % 8;
2135 val = 0;
2136
2137 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2138 val &= (1 << bit);
2139
2140 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2141}
2142
2143static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2144{
2145 u32 offset, msr, value;
2146 int write, mask;
2147
2148 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2149 return NESTED_EXIT_HOST;
2150
2151 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2152 offset = svm_msrpm_offset(msr);
2153 write = svm->vmcb->control.exit_info_1 & 1;
2154 mask = 1 << ((2 * (msr & 0xf)) + write);
2155
2156 if (offset == MSR_INVALID)
2157 return NESTED_EXIT_DONE;
2158
2159 /* Offset is in 32 bit units but need in 8 bit units */
2160 offset *= 4;
2161
2162 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2163 return NESTED_EXIT_DONE;
2164
2165 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2166}
2167
2168static int nested_svm_exit_special(struct vcpu_svm *svm)
2169{
2170 u32 exit_code = svm->vmcb->control.exit_code;
2171
2172 switch (exit_code) {
2173 case SVM_EXIT_INTR:
2174 case SVM_EXIT_NMI:
2175 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2176 return NESTED_EXIT_HOST;
2177 case SVM_EXIT_NPF:
2178 /* For now we are always handling NPFs when using them */
2179 if (npt_enabled)
2180 return NESTED_EXIT_HOST;
2181 break;
2182 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2183 /* When we're shadowing, trap PFs, but not async PF */
2184 if (!npt_enabled && svm->apf_reason == 0)
2185 return NESTED_EXIT_HOST;
2186 break;
2187 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2188 nm_interception(svm);
2189 break;
2190 default:
2191 break;
2192 }
2193
2194 return NESTED_EXIT_CONTINUE;
2195}
2196
2197/*
2198 * If this function returns true, this #vmexit was already handled
2199 */
2200static int nested_svm_intercept(struct vcpu_svm *svm)
2201{
2202 u32 exit_code = svm->vmcb->control.exit_code;
2203 int vmexit = NESTED_EXIT_HOST;
2204
2205 switch (exit_code) {
2206 case SVM_EXIT_MSR:
2207 vmexit = nested_svm_exit_handled_msr(svm);
2208 break;
2209 case SVM_EXIT_IOIO:
2210 vmexit = nested_svm_intercept_ioio(svm);
2211 break;
2212 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2213 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2214 if (svm->nested.intercept_cr & bit)
2215 vmexit = NESTED_EXIT_DONE;
2216 break;
2217 }
2218 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2219 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2220 if (svm->nested.intercept_dr & bit)
2221 vmexit = NESTED_EXIT_DONE;
2222 break;
2223 }
2224 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2225 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2226 if (svm->nested.intercept_exceptions & excp_bits)
2227 vmexit = NESTED_EXIT_DONE;
2228 /* async page fault always cause vmexit */
2229 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2230 svm->apf_reason != 0)
2231 vmexit = NESTED_EXIT_DONE;
2232 break;
2233 }
2234 case SVM_EXIT_ERR: {
2235 vmexit = NESTED_EXIT_DONE;
2236 break;
2237 }
2238 default: {
2239 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2240 if (svm->nested.intercept & exit_bits)
2241 vmexit = NESTED_EXIT_DONE;
2242 }
2243 }
2244
2245 return vmexit;
2246}
2247
2248static int nested_svm_exit_handled(struct vcpu_svm *svm)
2249{
2250 int vmexit;
2251
2252 vmexit = nested_svm_intercept(svm);
2253
2254 if (vmexit == NESTED_EXIT_DONE)
2255 nested_svm_vmexit(svm);
2256
2257 return vmexit;
2258}
2259
2260static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2261{
2262 struct vmcb_control_area *dst = &dst_vmcb->control;
2263 struct vmcb_control_area *from = &from_vmcb->control;
2264
2265 dst->intercept_cr = from->intercept_cr;
2266 dst->intercept_dr = from->intercept_dr;
2267 dst->intercept_exceptions = from->intercept_exceptions;
2268 dst->intercept = from->intercept;
2269 dst->iopm_base_pa = from->iopm_base_pa;
2270 dst->msrpm_base_pa = from->msrpm_base_pa;
2271 dst->tsc_offset = from->tsc_offset;
2272 dst->asid = from->asid;
2273 dst->tlb_ctl = from->tlb_ctl;
2274 dst->int_ctl = from->int_ctl;
2275 dst->int_vector = from->int_vector;
2276 dst->int_state = from->int_state;
2277 dst->exit_code = from->exit_code;
2278 dst->exit_code_hi = from->exit_code_hi;
2279 dst->exit_info_1 = from->exit_info_1;
2280 dst->exit_info_2 = from->exit_info_2;
2281 dst->exit_int_info = from->exit_int_info;
2282 dst->exit_int_info_err = from->exit_int_info_err;
2283 dst->nested_ctl = from->nested_ctl;
2284 dst->event_inj = from->event_inj;
2285 dst->event_inj_err = from->event_inj_err;
2286 dst->nested_cr3 = from->nested_cr3;
2287 dst->lbr_ctl = from->lbr_ctl;
2288}
2289
2290static int nested_svm_vmexit(struct vcpu_svm *svm)
2291{
2292 struct vmcb *nested_vmcb;
2293 struct vmcb *hsave = svm->nested.hsave;
2294 struct vmcb *vmcb = svm->vmcb;
2295 struct page *page;
2296
2297 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2298 vmcb->control.exit_info_1,
2299 vmcb->control.exit_info_2,
2300 vmcb->control.exit_int_info,
2301 vmcb->control.exit_int_info_err,
2302 KVM_ISA_SVM);
2303
2304 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2305 if (!nested_vmcb)
2306 return 1;
2307
2308 /* Exit Guest-Mode */
2309 leave_guest_mode(&svm->vcpu);
2310 svm->nested.vmcb = 0;
2311
2312 /* Give the current vmcb to the guest */
2313 disable_gif(svm);
2314
2315 nested_vmcb->save.es = vmcb->save.es;
2316 nested_vmcb->save.cs = vmcb->save.cs;
2317 nested_vmcb->save.ss = vmcb->save.ss;
2318 nested_vmcb->save.ds = vmcb->save.ds;
2319 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2320 nested_vmcb->save.idtr = vmcb->save.idtr;
2321 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2322 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2323 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2324 nested_vmcb->save.cr2 = vmcb->save.cr2;
2325 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2326 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2327 nested_vmcb->save.rip = vmcb->save.rip;
2328 nested_vmcb->save.rsp = vmcb->save.rsp;
2329 nested_vmcb->save.rax = vmcb->save.rax;
2330 nested_vmcb->save.dr7 = vmcb->save.dr7;
2331 nested_vmcb->save.dr6 = vmcb->save.dr6;
2332 nested_vmcb->save.cpl = vmcb->save.cpl;
2333
2334 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2335 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2336 nested_vmcb->control.int_state = vmcb->control.int_state;
2337 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2338 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2339 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2340 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2341 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2342 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2343 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2344
2345 /*
2346 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2347 * to make sure that we do not lose injected events. So check event_inj
2348 * here and copy it to exit_int_info if it is valid.
2349 * Exit_int_info and event_inj can't be both valid because the case
2350 * below only happens on a VMRUN instruction intercept which has
2351 * no valid exit_int_info set.
2352 */
2353 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2354 struct vmcb_control_area *nc = &nested_vmcb->control;
2355
2356 nc->exit_int_info = vmcb->control.event_inj;
2357 nc->exit_int_info_err = vmcb->control.event_inj_err;
2358 }
2359
2360 nested_vmcb->control.tlb_ctl = 0;
2361 nested_vmcb->control.event_inj = 0;
2362 nested_vmcb->control.event_inj_err = 0;
2363
2364 /* We always set V_INTR_MASKING and remember the old value in hflags */
2365 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2366 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2367
2368 /* Restore the original control entries */
2369 copy_vmcb_control_area(vmcb, hsave);
2370
2371 kvm_clear_exception_queue(&svm->vcpu);
2372 kvm_clear_interrupt_queue(&svm->vcpu);
2373
2374 svm->nested.nested_cr3 = 0;
2375
2376 /* Restore selected save entries */
2377 svm->vmcb->save.es = hsave->save.es;
2378 svm->vmcb->save.cs = hsave->save.cs;
2379 svm->vmcb->save.ss = hsave->save.ss;
2380 svm->vmcb->save.ds = hsave->save.ds;
2381 svm->vmcb->save.gdtr = hsave->save.gdtr;
2382 svm->vmcb->save.idtr = hsave->save.idtr;
2383 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2384 svm_set_efer(&svm->vcpu, hsave->save.efer);
2385 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2386 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2387 if (npt_enabled) {
2388 svm->vmcb->save.cr3 = hsave->save.cr3;
2389 svm->vcpu.arch.cr3 = hsave->save.cr3;
2390 } else {
2391 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2392 }
2393 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2394 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2395 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2396 svm->vmcb->save.dr7 = 0;
2397 svm->vmcb->save.cpl = 0;
2398 svm->vmcb->control.exit_int_info = 0;
2399
2400 mark_all_dirty(svm->vmcb);
2401
2402 nested_svm_unmap(page);
2403
2404 nested_svm_uninit_mmu_context(&svm->vcpu);
2405 kvm_mmu_reset_context(&svm->vcpu);
2406 kvm_mmu_load(&svm->vcpu);
2407
2408 return 0;
2409}
2410
2411static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2412{
2413 /*
2414 * This function merges the msr permission bitmaps of kvm and the
2415 * nested vmcb. It is optimized in that it only merges the parts where
2416 * the kvm msr permission bitmap may contain zero bits
2417 */
2418 int i;
2419
2420 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2421 return true;
2422
2423 for (i = 0; i < MSRPM_OFFSETS; i++) {
2424 u32 value, p;
2425 u64 offset;
2426
2427 if (msrpm_offsets[i] == 0xffffffff)
2428 break;
2429
2430 p = msrpm_offsets[i];
2431 offset = svm->nested.vmcb_msrpm + (p * 4);
2432
2433 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2434 return false;
2435
2436 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2437 }
2438
2439 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2440
2441 return true;
2442}
2443
2444static bool nested_vmcb_checks(struct vmcb *vmcb)
2445{
2446 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2447 return false;
2448
2449 if (vmcb->control.asid == 0)
2450 return false;
2451
2452 if (vmcb->control.nested_ctl && !npt_enabled)
2453 return false;
2454
2455 return true;
2456}
2457
2458static bool nested_svm_vmrun(struct vcpu_svm *svm)
2459{
2460 struct vmcb *nested_vmcb;
2461 struct vmcb *hsave = svm->nested.hsave;
2462 struct vmcb *vmcb = svm->vmcb;
2463 struct page *page;
2464 u64 vmcb_gpa;
2465
2466 vmcb_gpa = svm->vmcb->save.rax;
2467
2468 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2469 if (!nested_vmcb)
2470 return false;
2471
2472 if (!nested_vmcb_checks(nested_vmcb)) {
2473 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2474 nested_vmcb->control.exit_code_hi = 0;
2475 nested_vmcb->control.exit_info_1 = 0;
2476 nested_vmcb->control.exit_info_2 = 0;
2477
2478 nested_svm_unmap(page);
2479
2480 return false;
2481 }
2482
2483 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2484 nested_vmcb->save.rip,
2485 nested_vmcb->control.int_ctl,
2486 nested_vmcb->control.event_inj,
2487 nested_vmcb->control.nested_ctl);
2488
2489 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2490 nested_vmcb->control.intercept_cr >> 16,
2491 nested_vmcb->control.intercept_exceptions,
2492 nested_vmcb->control.intercept);
2493
2494 /* Clear internal status */
2495 kvm_clear_exception_queue(&svm->vcpu);
2496 kvm_clear_interrupt_queue(&svm->vcpu);
2497
2498 /*
2499 * Save the old vmcb, so we don't need to pick what we save, but can
2500 * restore everything when a VMEXIT occurs
2501 */
2502 hsave->save.es = vmcb->save.es;
2503 hsave->save.cs = vmcb->save.cs;
2504 hsave->save.ss = vmcb->save.ss;
2505 hsave->save.ds = vmcb->save.ds;
2506 hsave->save.gdtr = vmcb->save.gdtr;
2507 hsave->save.idtr = vmcb->save.idtr;
2508 hsave->save.efer = svm->vcpu.arch.efer;
2509 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2510 hsave->save.cr4 = svm->vcpu.arch.cr4;
2511 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2512 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2513 hsave->save.rsp = vmcb->save.rsp;
2514 hsave->save.rax = vmcb->save.rax;
2515 if (npt_enabled)
2516 hsave->save.cr3 = vmcb->save.cr3;
2517 else
2518 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2519
2520 copy_vmcb_control_area(hsave, vmcb);
2521
2522 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2523 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2524 else
2525 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2526
2527 if (nested_vmcb->control.nested_ctl) {
2528 kvm_mmu_unload(&svm->vcpu);
2529 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2530 nested_svm_init_mmu_context(&svm->vcpu);
2531 }
2532
2533 /* Load the nested guest state */
2534 svm->vmcb->save.es = nested_vmcb->save.es;
2535 svm->vmcb->save.cs = nested_vmcb->save.cs;
2536 svm->vmcb->save.ss = nested_vmcb->save.ss;
2537 svm->vmcb->save.ds = nested_vmcb->save.ds;
2538 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2539 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2540 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2541 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2542 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2543 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2544 if (npt_enabled) {
2545 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2546 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2547 } else
2548 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2549
2550 /* Guest paging mode is active - reset mmu */
2551 kvm_mmu_reset_context(&svm->vcpu);
2552
2553 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2554 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2555 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2556 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2557
2558 /* In case we don't even reach vcpu_run, the fields are not updated */
2559 svm->vmcb->save.rax = nested_vmcb->save.rax;
2560 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2561 svm->vmcb->save.rip = nested_vmcb->save.rip;
2562 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2563 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2564 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2565
2566 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2567 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2568
2569 /* cache intercepts */
2570 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2571 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2572 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2573 svm->nested.intercept = nested_vmcb->control.intercept;
2574
2575 svm_flush_tlb(&svm->vcpu);
2576 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2577 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2578 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2579 else
2580 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2581
2582 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2583 /* We only want the cr8 intercept bits of the guest */
2584 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2585 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2586 }
2587
2588 /* We don't want to see VMMCALLs from a nested guest */
2589 clr_intercept(svm, INTERCEPT_VMMCALL);
2590
2591 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2592 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2593 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2594 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2595 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2596 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2597
2598 nested_svm_unmap(page);
2599
2600 /* Enter Guest-Mode */
2601 enter_guest_mode(&svm->vcpu);
2602
2603 /*
2604 * Merge guest and host intercepts - must be called with vcpu in
2605 * guest-mode to take affect here
2606 */
2607 recalc_intercepts(svm);
2608
2609 svm->nested.vmcb = vmcb_gpa;
2610
2611 enable_gif(svm);
2612
2613 mark_all_dirty(svm->vmcb);
2614
2615 return true;
2616}
2617
2618static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2619{
2620 to_vmcb->save.fs = from_vmcb->save.fs;
2621 to_vmcb->save.gs = from_vmcb->save.gs;
2622 to_vmcb->save.tr = from_vmcb->save.tr;
2623 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2624 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2625 to_vmcb->save.star = from_vmcb->save.star;
2626 to_vmcb->save.lstar = from_vmcb->save.lstar;
2627 to_vmcb->save.cstar = from_vmcb->save.cstar;
2628 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2629 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2630 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2631 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2632}
2633
2634static int vmload_interception(struct vcpu_svm *svm)
2635{
2636 struct vmcb *nested_vmcb;
2637 struct page *page;
2638
2639 if (nested_svm_check_permissions(svm))
2640 return 1;
2641
2642 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2643 if (!nested_vmcb)
2644 return 1;
2645
2646 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2647 skip_emulated_instruction(&svm->vcpu);
2648
2649 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2650 nested_svm_unmap(page);
2651
2652 return 1;
2653}
2654
2655static int vmsave_interception(struct vcpu_svm *svm)
2656{
2657 struct vmcb *nested_vmcb;
2658 struct page *page;
2659
2660 if (nested_svm_check_permissions(svm))
2661 return 1;
2662
2663 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2664 if (!nested_vmcb)
2665 return 1;
2666
2667 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2668 skip_emulated_instruction(&svm->vcpu);
2669
2670 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2671 nested_svm_unmap(page);
2672
2673 return 1;
2674}
2675
2676static int vmrun_interception(struct vcpu_svm *svm)
2677{
2678 if (nested_svm_check_permissions(svm))
2679 return 1;
2680
2681 /* Save rip after vmrun instruction */
2682 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2683
2684 if (!nested_svm_vmrun(svm))
2685 return 1;
2686
2687 if (!nested_svm_vmrun_msrpm(svm))
2688 goto failed;
2689
2690 return 1;
2691
2692failed:
2693
2694 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2695 svm->vmcb->control.exit_code_hi = 0;
2696 svm->vmcb->control.exit_info_1 = 0;
2697 svm->vmcb->control.exit_info_2 = 0;
2698
2699 nested_svm_vmexit(svm);
2700
2701 return 1;
2702}
2703
2704static int stgi_interception(struct vcpu_svm *svm)
2705{
2706 if (nested_svm_check_permissions(svm))
2707 return 1;
2708
2709 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2710 skip_emulated_instruction(&svm->vcpu);
2711 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2712
2713 enable_gif(svm);
2714
2715 return 1;
2716}
2717
2718static int clgi_interception(struct vcpu_svm *svm)
2719{
2720 if (nested_svm_check_permissions(svm))
2721 return 1;
2722
2723 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2724 skip_emulated_instruction(&svm->vcpu);
2725
2726 disable_gif(svm);
2727
2728 /* After a CLGI no interrupts should come */
2729 svm_clear_vintr(svm);
2730 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2731
2732 mark_dirty(svm->vmcb, VMCB_INTR);
2733
2734 return 1;
2735}
2736
2737static int invlpga_interception(struct vcpu_svm *svm)
2738{
2739 struct kvm_vcpu *vcpu = &svm->vcpu;
2740
2741 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2742 vcpu->arch.regs[VCPU_REGS_RAX]);
2743
2744 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2745 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2746
2747 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2748 skip_emulated_instruction(&svm->vcpu);
2749 return 1;
2750}
2751
2752static int skinit_interception(struct vcpu_svm *svm)
2753{
2754 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2755
2756 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2757 return 1;
2758}
2759
2760static int xsetbv_interception(struct vcpu_svm *svm)
2761{
2762 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2763 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2764
2765 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2766 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2767 skip_emulated_instruction(&svm->vcpu);
2768 }
2769
2770 return 1;
2771}
2772
2773static int invalid_op_interception(struct vcpu_svm *svm)
2774{
2775 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2776 return 1;
2777}
2778
2779static int task_switch_interception(struct vcpu_svm *svm)
2780{
2781 u16 tss_selector;
2782 int reason;
2783 int int_type = svm->vmcb->control.exit_int_info &
2784 SVM_EXITINTINFO_TYPE_MASK;
2785 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2786 uint32_t type =
2787 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2788 uint32_t idt_v =
2789 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2790 bool has_error_code = false;
2791 u32 error_code = 0;
2792
2793 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2794
2795 if (svm->vmcb->control.exit_info_2 &
2796 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2797 reason = TASK_SWITCH_IRET;
2798 else if (svm->vmcb->control.exit_info_2 &
2799 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2800 reason = TASK_SWITCH_JMP;
2801 else if (idt_v)
2802 reason = TASK_SWITCH_GATE;
2803 else
2804 reason = TASK_SWITCH_CALL;
2805
2806 if (reason == TASK_SWITCH_GATE) {
2807 switch (type) {
2808 case SVM_EXITINTINFO_TYPE_NMI:
2809 svm->vcpu.arch.nmi_injected = false;
2810 break;
2811 case SVM_EXITINTINFO_TYPE_EXEPT:
2812 if (svm->vmcb->control.exit_info_2 &
2813 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2814 has_error_code = true;
2815 error_code =
2816 (u32)svm->vmcb->control.exit_info_2;
2817 }
2818 kvm_clear_exception_queue(&svm->vcpu);
2819 break;
2820 case SVM_EXITINTINFO_TYPE_INTR:
2821 kvm_clear_interrupt_queue(&svm->vcpu);
2822 break;
2823 default:
2824 break;
2825 }
2826 }
2827
2828 if (reason != TASK_SWITCH_GATE ||
2829 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2830 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2831 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2832 skip_emulated_instruction(&svm->vcpu);
2833
2834 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2835 int_vec = -1;
2836
2837 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2838 has_error_code, error_code) == EMULATE_FAIL) {
2839 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2840 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2841 svm->vcpu.run->internal.ndata = 0;
2842 return 0;
2843 }
2844 return 1;
2845}
2846
2847static int cpuid_interception(struct vcpu_svm *svm)
2848{
2849 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2850 kvm_emulate_cpuid(&svm->vcpu);
2851 return 1;
2852}
2853
2854static int iret_interception(struct vcpu_svm *svm)
2855{
2856 ++svm->vcpu.stat.nmi_window_exits;
2857 clr_intercept(svm, INTERCEPT_IRET);
2858 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2859 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2860 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2861 return 1;
2862}
2863
2864static int invlpg_interception(struct vcpu_svm *svm)
2865{
2866 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2867 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2868
2869 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2870 skip_emulated_instruction(&svm->vcpu);
2871 return 1;
2872}
2873
2874static int emulate_on_interception(struct vcpu_svm *svm)
2875{
2876 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2877}
2878
2879static int rdpmc_interception(struct vcpu_svm *svm)
2880{
2881 int err;
2882
2883 if (!static_cpu_has(X86_FEATURE_NRIPS))
2884 return emulate_on_interception(svm);
2885
2886 err = kvm_rdpmc(&svm->vcpu);
2887 kvm_complete_insn_gp(&svm->vcpu, err);
2888
2889 return 1;
2890}
2891
2892bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2893{
2894 unsigned long cr0 = svm->vcpu.arch.cr0;
2895 bool ret = false;
2896 u64 intercept;
2897
2898 intercept = svm->nested.intercept;
2899
2900 if (!is_guest_mode(&svm->vcpu) ||
2901 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2902 return false;
2903
2904 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2905 val &= ~SVM_CR0_SELECTIVE_MASK;
2906
2907 if (cr0 ^ val) {
2908 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2909 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2910 }
2911
2912 return ret;
2913}
2914
2915#define CR_VALID (1ULL << 63)
2916
2917static int cr_interception(struct vcpu_svm *svm)
2918{
2919 int reg, cr;
2920 unsigned long val;
2921 int err;
2922
2923 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2924 return emulate_on_interception(svm);
2925
2926 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2927 return emulate_on_interception(svm);
2928
2929 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2930 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2931
2932 err = 0;
2933 if (cr >= 16) { /* mov to cr */
2934 cr -= 16;
2935 val = kvm_register_read(&svm->vcpu, reg);
2936 switch (cr) {
2937 case 0:
2938 if (!check_selective_cr0_intercepted(svm, val))
2939 err = kvm_set_cr0(&svm->vcpu, val);
2940 else
2941 return 1;
2942
2943 break;
2944 case 3:
2945 err = kvm_set_cr3(&svm->vcpu, val);
2946 break;
2947 case 4:
2948 err = kvm_set_cr4(&svm->vcpu, val);
2949 break;
2950 case 8:
2951 err = kvm_set_cr8(&svm->vcpu, val);
2952 break;
2953 default:
2954 WARN(1, "unhandled write to CR%d", cr);
2955 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2956 return 1;
2957 }
2958 } else { /* mov from cr */
2959 switch (cr) {
2960 case 0:
2961 val = kvm_read_cr0(&svm->vcpu);
2962 break;
2963 case 2:
2964 val = svm->vcpu.arch.cr2;
2965 break;
2966 case 3:
2967 val = kvm_read_cr3(&svm->vcpu);
2968 break;
2969 case 4:
2970 val = kvm_read_cr4(&svm->vcpu);
2971 break;
2972 case 8:
2973 val = kvm_get_cr8(&svm->vcpu);
2974 break;
2975 default:
2976 WARN(1, "unhandled read from CR%d", cr);
2977 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2978 return 1;
2979 }
2980 kvm_register_write(&svm->vcpu, reg, val);
2981 }
2982 kvm_complete_insn_gp(&svm->vcpu, err);
2983
2984 return 1;
2985}
2986
2987static int dr_interception(struct vcpu_svm *svm)
2988{
2989 int reg, dr;
2990 unsigned long val;
2991 int err;
2992
2993 if (svm->vcpu.guest_debug == 0) {
2994 /*
2995 * No more DR vmexits; force a reload of the debug registers
2996 * and reenter on this instruction. The next vmexit will
2997 * retrieve the full state of the debug registers.
2998 */
2999 clr_dr_intercepts(svm);
3000 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3001 return 1;
3002 }
3003
3004 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3005 return emulate_on_interception(svm);
3006
3007 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3008 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3009
3010 if (dr >= 16) { /* mov to DRn */
3011 val = kvm_register_read(&svm->vcpu, reg);
3012 kvm_set_dr(&svm->vcpu, dr - 16, val);
3013 } else {
3014 err = kvm_get_dr(&svm->vcpu, dr, &val);
3015 if (!err)
3016 kvm_register_write(&svm->vcpu, reg, val);
3017 }
3018
3019 skip_emulated_instruction(&svm->vcpu);
3020
3021 return 1;
3022}
3023
3024static int cr8_write_interception(struct vcpu_svm *svm)
3025{
3026 struct kvm_run *kvm_run = svm->vcpu.run;
3027 int r;
3028
3029 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3030 /* instruction emulation calls kvm_set_cr8() */
3031 r = cr_interception(svm);
3032 if (irqchip_in_kernel(svm->vcpu.kvm))
3033 return r;
3034 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3035 return r;
3036 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3037 return 0;
3038}
3039
3040u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3041{
3042 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3043 return vmcb->control.tsc_offset +
3044 svm_scale_tsc(vcpu, host_tsc);
3045}
3046
3047static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3048{
3049 struct vcpu_svm *svm = to_svm(vcpu);
3050
3051 switch (ecx) {
3052 case MSR_IA32_TSC: {
3053 *data = svm->vmcb->control.tsc_offset +
3054 svm_scale_tsc(vcpu, native_read_tsc());
3055
3056 break;
3057 }
3058 case MSR_STAR:
3059 *data = svm->vmcb->save.star;
3060 break;
3061#ifdef CONFIG_X86_64
3062 case MSR_LSTAR:
3063 *data = svm->vmcb->save.lstar;
3064 break;
3065 case MSR_CSTAR:
3066 *data = svm->vmcb->save.cstar;
3067 break;
3068 case MSR_KERNEL_GS_BASE:
3069 *data = svm->vmcb->save.kernel_gs_base;
3070 break;
3071 case MSR_SYSCALL_MASK:
3072 *data = svm->vmcb->save.sfmask;
3073 break;
3074#endif
3075 case MSR_IA32_SYSENTER_CS:
3076 *data = svm->vmcb->save.sysenter_cs;
3077 break;
3078 case MSR_IA32_SYSENTER_EIP:
3079 *data = svm->sysenter_eip;
3080 break;
3081 case MSR_IA32_SYSENTER_ESP:
3082 *data = svm->sysenter_esp;
3083 break;
3084 /*
3085 * Nobody will change the following 5 values in the VMCB so we can
3086 * safely return them on rdmsr. They will always be 0 until LBRV is
3087 * implemented.
3088 */
3089 case MSR_IA32_DEBUGCTLMSR:
3090 *data = svm->vmcb->save.dbgctl;
3091 break;
3092 case MSR_IA32_LASTBRANCHFROMIP:
3093 *data = svm->vmcb->save.br_from;
3094 break;
3095 case MSR_IA32_LASTBRANCHTOIP:
3096 *data = svm->vmcb->save.br_to;
3097 break;
3098 case MSR_IA32_LASTINTFROMIP:
3099 *data = svm->vmcb->save.last_excp_from;
3100 break;
3101 case MSR_IA32_LASTINTTOIP:
3102 *data = svm->vmcb->save.last_excp_to;
3103 break;
3104 case MSR_VM_HSAVE_PA:
3105 *data = svm->nested.hsave_msr;
3106 break;
3107 case MSR_VM_CR:
3108 *data = svm->nested.vm_cr_msr;
3109 break;
3110 case MSR_IA32_UCODE_REV:
3111 *data = 0x01000065;
3112 break;
3113 default:
3114 return kvm_get_msr_common(vcpu, ecx, data);
3115 }
3116 return 0;
3117}
3118
3119static int rdmsr_interception(struct vcpu_svm *svm)
3120{
3121 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3122 u64 data;
3123
3124 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3125 trace_kvm_msr_read_ex(ecx);
3126 kvm_inject_gp(&svm->vcpu, 0);
3127 } else {
3128 trace_kvm_msr_read(ecx, data);
3129
3130 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3131 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3132 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3133 skip_emulated_instruction(&svm->vcpu);
3134 }
3135 return 1;
3136}
3137
3138static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3139{
3140 struct vcpu_svm *svm = to_svm(vcpu);
3141 int svm_dis, chg_mask;
3142
3143 if (data & ~SVM_VM_CR_VALID_MASK)
3144 return 1;
3145
3146 chg_mask = SVM_VM_CR_VALID_MASK;
3147
3148 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3149 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3150
3151 svm->nested.vm_cr_msr &= ~chg_mask;
3152 svm->nested.vm_cr_msr |= (data & chg_mask);
3153
3154 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3155
3156 /* check for svm_disable while efer.svme is set */
3157 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3158 return 1;
3159
3160 return 0;
3161}
3162
3163static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3164{
3165 struct vcpu_svm *svm = to_svm(vcpu);
3166
3167 u32 ecx = msr->index;
3168 u64 data = msr->data;
3169 switch (ecx) {
3170 case MSR_IA32_TSC:
3171 kvm_write_tsc(vcpu, msr);
3172 break;
3173 case MSR_STAR:
3174 svm->vmcb->save.star = data;
3175 break;
3176#ifdef CONFIG_X86_64
3177 case MSR_LSTAR:
3178 svm->vmcb->save.lstar = data;
3179 break;
3180 case MSR_CSTAR:
3181 svm->vmcb->save.cstar = data;
3182 break;
3183 case MSR_KERNEL_GS_BASE:
3184 svm->vmcb->save.kernel_gs_base = data;
3185 break;
3186 case MSR_SYSCALL_MASK:
3187 svm->vmcb->save.sfmask = data;
3188 break;
3189#endif
3190 case MSR_IA32_SYSENTER_CS:
3191 svm->vmcb->save.sysenter_cs = data;
3192 break;
3193 case MSR_IA32_SYSENTER_EIP:
3194 svm->sysenter_eip = data;
3195 svm->vmcb->save.sysenter_eip = data;
3196 break;
3197 case MSR_IA32_SYSENTER_ESP:
3198 svm->sysenter_esp = data;
3199 svm->vmcb->save.sysenter_esp = data;
3200 break;
3201 case MSR_IA32_DEBUGCTLMSR:
3202 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3203 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3204 __func__, data);
3205 break;
3206 }
3207 if (data & DEBUGCTL_RESERVED_BITS)
3208 return 1;
3209
3210 svm->vmcb->save.dbgctl = data;
3211 mark_dirty(svm->vmcb, VMCB_LBR);
3212 if (data & (1ULL<<0))
3213 svm_enable_lbrv(svm);
3214 else
3215 svm_disable_lbrv(svm);
3216 break;
3217 case MSR_VM_HSAVE_PA:
3218 svm->nested.hsave_msr = data;
3219 break;
3220 case MSR_VM_CR:
3221 return svm_set_vm_cr(vcpu, data);
3222 case MSR_VM_IGNNE:
3223 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3224 break;
3225 default:
3226 return kvm_set_msr_common(vcpu, msr);
3227 }
3228 return 0;
3229}
3230
3231static int wrmsr_interception(struct vcpu_svm *svm)
3232{
3233 struct msr_data msr;
3234 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3235 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3236 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3237
3238 msr.data = data;
3239 msr.index = ecx;
3240 msr.host_initiated = false;
3241
3242 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3243 if (svm_set_msr(&svm->vcpu, &msr)) {
3244 trace_kvm_msr_write_ex(ecx, data);
3245 kvm_inject_gp(&svm->vcpu, 0);
3246 } else {
3247 trace_kvm_msr_write(ecx, data);
3248 skip_emulated_instruction(&svm->vcpu);
3249 }
3250 return 1;
3251}
3252
3253static int msr_interception(struct vcpu_svm *svm)
3254{
3255 if (svm->vmcb->control.exit_info_1)
3256 return wrmsr_interception(svm);
3257 else
3258 return rdmsr_interception(svm);
3259}
3260
3261static int interrupt_window_interception(struct vcpu_svm *svm)
3262{
3263 struct kvm_run *kvm_run = svm->vcpu.run;
3264
3265 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3266 svm_clear_vintr(svm);
3267 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3268 mark_dirty(svm->vmcb, VMCB_INTR);
3269 ++svm->vcpu.stat.irq_window_exits;
3270 /*
3271 * If the user space waits to inject interrupts, exit as soon as
3272 * possible
3273 */
3274 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3275 kvm_run->request_interrupt_window &&
3276 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3277 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3278 return 0;
3279 }
3280
3281 return 1;
3282}
3283
3284static int pause_interception(struct vcpu_svm *svm)
3285{
3286 kvm_vcpu_on_spin(&(svm->vcpu));
3287 return 1;
3288}
3289
3290static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3291 [SVM_EXIT_READ_CR0] = cr_interception,
3292 [SVM_EXIT_READ_CR3] = cr_interception,
3293 [SVM_EXIT_READ_CR4] = cr_interception,
3294 [SVM_EXIT_READ_CR8] = cr_interception,
3295 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3296 [SVM_EXIT_WRITE_CR0] = cr_interception,
3297 [SVM_EXIT_WRITE_CR3] = cr_interception,
3298 [SVM_EXIT_WRITE_CR4] = cr_interception,
3299 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3300 [SVM_EXIT_READ_DR0] = dr_interception,
3301 [SVM_EXIT_READ_DR1] = dr_interception,
3302 [SVM_EXIT_READ_DR2] = dr_interception,
3303 [SVM_EXIT_READ_DR3] = dr_interception,
3304 [SVM_EXIT_READ_DR4] = dr_interception,
3305 [SVM_EXIT_READ_DR5] = dr_interception,
3306 [SVM_EXIT_READ_DR6] = dr_interception,
3307 [SVM_EXIT_READ_DR7] = dr_interception,
3308 [SVM_EXIT_WRITE_DR0] = dr_interception,
3309 [SVM_EXIT_WRITE_DR1] = dr_interception,
3310 [SVM_EXIT_WRITE_DR2] = dr_interception,
3311 [SVM_EXIT_WRITE_DR3] = dr_interception,
3312 [SVM_EXIT_WRITE_DR4] = dr_interception,
3313 [SVM_EXIT_WRITE_DR5] = dr_interception,
3314 [SVM_EXIT_WRITE_DR6] = dr_interception,
3315 [SVM_EXIT_WRITE_DR7] = dr_interception,
3316 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3317 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3318 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3319 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3320 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3321 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3322 [SVM_EXIT_INTR] = intr_interception,
3323 [SVM_EXIT_NMI] = nmi_interception,
3324 [SVM_EXIT_SMI] = nop_on_interception,
3325 [SVM_EXIT_INIT] = nop_on_interception,
3326 [SVM_EXIT_VINTR] = interrupt_window_interception,
3327 [SVM_EXIT_RDPMC] = rdpmc_interception,
3328 [SVM_EXIT_CPUID] = cpuid_interception,
3329 [SVM_EXIT_IRET] = iret_interception,
3330 [SVM_EXIT_INVD] = emulate_on_interception,
3331 [SVM_EXIT_PAUSE] = pause_interception,
3332 [SVM_EXIT_HLT] = halt_interception,
3333 [SVM_EXIT_INVLPG] = invlpg_interception,
3334 [SVM_EXIT_INVLPGA] = invlpga_interception,
3335 [SVM_EXIT_IOIO] = io_interception,
3336 [SVM_EXIT_MSR] = msr_interception,
3337 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3338 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3339 [SVM_EXIT_VMRUN] = vmrun_interception,
3340 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3341 [SVM_EXIT_VMLOAD] = vmload_interception,
3342 [SVM_EXIT_VMSAVE] = vmsave_interception,
3343 [SVM_EXIT_STGI] = stgi_interception,
3344 [SVM_EXIT_CLGI] = clgi_interception,
3345 [SVM_EXIT_SKINIT] = skinit_interception,
3346 [SVM_EXIT_WBINVD] = emulate_on_interception,
3347 [SVM_EXIT_MONITOR] = invalid_op_interception,
3348 [SVM_EXIT_MWAIT] = invalid_op_interception,
3349 [SVM_EXIT_XSETBV] = xsetbv_interception,
3350 [SVM_EXIT_NPF] = pf_interception,
3351};
3352
3353static void dump_vmcb(struct kvm_vcpu *vcpu)
3354{
3355 struct vcpu_svm *svm = to_svm(vcpu);
3356 struct vmcb_control_area *control = &svm->vmcb->control;
3357 struct vmcb_save_area *save = &svm->vmcb->save;
3358
3359 pr_err("VMCB Control Area:\n");
3360 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3361 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3362 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3363 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3364 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3365 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3366 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3367 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3368 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3369 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3370 pr_err("%-20s%d\n", "asid:", control->asid);
3371 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3372 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3373 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3374 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3375 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3376 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3377 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3378 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3379 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3380 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3381 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3382 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3383 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3384 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3385 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3386 pr_err("VMCB State Save Area:\n");
3387 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3388 "es:",
3389 save->es.selector, save->es.attrib,
3390 save->es.limit, save->es.base);
3391 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3392 "cs:",
3393 save->cs.selector, save->cs.attrib,
3394 save->cs.limit, save->cs.base);
3395 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3396 "ss:",
3397 save->ss.selector, save->ss.attrib,
3398 save->ss.limit, save->ss.base);
3399 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3400 "ds:",
3401 save->ds.selector, save->ds.attrib,
3402 save->ds.limit, save->ds.base);
3403 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3404 "fs:",
3405 save->fs.selector, save->fs.attrib,
3406 save->fs.limit, save->fs.base);
3407 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3408 "gs:",
3409 save->gs.selector, save->gs.attrib,
3410 save->gs.limit, save->gs.base);
3411 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3412 "gdtr:",
3413 save->gdtr.selector, save->gdtr.attrib,
3414 save->gdtr.limit, save->gdtr.base);
3415 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3416 "ldtr:",
3417 save->ldtr.selector, save->ldtr.attrib,
3418 save->ldtr.limit, save->ldtr.base);
3419 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3420 "idtr:",
3421 save->idtr.selector, save->idtr.attrib,
3422 save->idtr.limit, save->idtr.base);
3423 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3424 "tr:",
3425 save->tr.selector, save->tr.attrib,
3426 save->tr.limit, save->tr.base);
3427 pr_err("cpl: %d efer: %016llx\n",
3428 save->cpl, save->efer);
3429 pr_err("%-15s %016llx %-13s %016llx\n",
3430 "cr0:", save->cr0, "cr2:", save->cr2);
3431 pr_err("%-15s %016llx %-13s %016llx\n",
3432 "cr3:", save->cr3, "cr4:", save->cr4);
3433 pr_err("%-15s %016llx %-13s %016llx\n",
3434 "dr6:", save->dr6, "dr7:", save->dr7);
3435 pr_err("%-15s %016llx %-13s %016llx\n",
3436 "rip:", save->rip, "rflags:", save->rflags);
3437 pr_err("%-15s %016llx %-13s %016llx\n",
3438 "rsp:", save->rsp, "rax:", save->rax);
3439 pr_err("%-15s %016llx %-13s %016llx\n",
3440 "star:", save->star, "lstar:", save->lstar);
3441 pr_err("%-15s %016llx %-13s %016llx\n",
3442 "cstar:", save->cstar, "sfmask:", save->sfmask);
3443 pr_err("%-15s %016llx %-13s %016llx\n",
3444 "kernel_gs_base:", save->kernel_gs_base,
3445 "sysenter_cs:", save->sysenter_cs);
3446 pr_err("%-15s %016llx %-13s %016llx\n",
3447 "sysenter_esp:", save->sysenter_esp,
3448 "sysenter_eip:", save->sysenter_eip);
3449 pr_err("%-15s %016llx %-13s %016llx\n",
3450 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3451 pr_err("%-15s %016llx %-13s %016llx\n",
3452 "br_from:", save->br_from, "br_to:", save->br_to);
3453 pr_err("%-15s %016llx %-13s %016llx\n",
3454 "excp_from:", save->last_excp_from,
3455 "excp_to:", save->last_excp_to);
3456}
3457
3458static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3459{
3460 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3461
3462 *info1 = control->exit_info_1;
3463 *info2 = control->exit_info_2;
3464}
3465
3466static int handle_exit(struct kvm_vcpu *vcpu)
3467{
3468 struct vcpu_svm *svm = to_svm(vcpu);
3469 struct kvm_run *kvm_run = vcpu->run;
3470 u32 exit_code = svm->vmcb->control.exit_code;
3471
3472 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3473 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3474 if (npt_enabled)
3475 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3476
3477 if (unlikely(svm->nested.exit_required)) {
3478 nested_svm_vmexit(svm);
3479 svm->nested.exit_required = false;
3480
3481 return 1;
3482 }
3483
3484 if (is_guest_mode(vcpu)) {
3485 int vmexit;
3486
3487 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3488 svm->vmcb->control.exit_info_1,
3489 svm->vmcb->control.exit_info_2,
3490 svm->vmcb->control.exit_int_info,
3491 svm->vmcb->control.exit_int_info_err,
3492 KVM_ISA_SVM);
3493
3494 vmexit = nested_svm_exit_special(svm);
3495
3496 if (vmexit == NESTED_EXIT_CONTINUE)
3497 vmexit = nested_svm_exit_handled(svm);
3498
3499 if (vmexit == NESTED_EXIT_DONE)
3500 return 1;
3501 }
3502
3503 svm_complete_interrupts(svm);
3504
3505 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3506 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3507 kvm_run->fail_entry.hardware_entry_failure_reason
3508 = svm->vmcb->control.exit_code;
3509 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3510 dump_vmcb(vcpu);
3511 return 0;
3512 }
3513
3514 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3515 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3516 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3517 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3518 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3519 "exit_code 0x%x\n",
3520 __func__, svm->vmcb->control.exit_int_info,
3521 exit_code);
3522
3523 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3524 || !svm_exit_handlers[exit_code]) {
3525 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3526 kvm_run->hw.hardware_exit_reason = exit_code;
3527 return 0;
3528 }
3529
3530 return svm_exit_handlers[exit_code](svm);
3531}
3532
3533static void reload_tss(struct kvm_vcpu *vcpu)
3534{
3535 int cpu = raw_smp_processor_id();
3536
3537 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3538 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3539 load_TR_desc();
3540}
3541
3542static void pre_svm_run(struct vcpu_svm *svm)
3543{
3544 int cpu = raw_smp_processor_id();
3545
3546 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3547
3548 /* FIXME: handle wraparound of asid_generation */
3549 if (svm->asid_generation != sd->asid_generation)
3550 new_asid(svm, sd);
3551}
3552
3553static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3554{
3555 struct vcpu_svm *svm = to_svm(vcpu);
3556
3557 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3558 vcpu->arch.hflags |= HF_NMI_MASK;
3559 set_intercept(svm, INTERCEPT_IRET);
3560 ++vcpu->stat.nmi_injections;
3561}
3562
3563static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3564{
3565 struct vmcb_control_area *control;
3566
3567 control = &svm->vmcb->control;
3568 control->int_vector = irq;
3569 control->int_ctl &= ~V_INTR_PRIO_MASK;
3570 control->int_ctl |= V_IRQ_MASK |
3571 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3572 mark_dirty(svm->vmcb, VMCB_INTR);
3573}
3574
3575static void svm_set_irq(struct kvm_vcpu *vcpu)
3576{
3577 struct vcpu_svm *svm = to_svm(vcpu);
3578
3579 BUG_ON(!(gif_set(svm)));
3580
3581 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3582 ++vcpu->stat.irq_injections;
3583
3584 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3585 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3586}
3587
3588static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3589{
3590 struct vcpu_svm *svm = to_svm(vcpu);
3591
3592 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3593 return;
3594
3595 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3596
3597 if (irr == -1)
3598 return;
3599
3600 if (tpr >= irr)
3601 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3602}
3603
3604static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3605{
3606 return;
3607}
3608
3609static int svm_vm_has_apicv(struct kvm *kvm)
3610{
3611 return 0;
3612}
3613
3614static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3615{
3616 return;
3617}
3618
3619static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3620{
3621 return;
3622}
3623
3624static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3625{
3626 return;
3627}
3628
3629static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3630{
3631 struct vcpu_svm *svm = to_svm(vcpu);
3632 struct vmcb *vmcb = svm->vmcb;
3633 int ret;
3634 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3635 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3636 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3637
3638 return ret;
3639}
3640
3641static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3642{
3643 struct vcpu_svm *svm = to_svm(vcpu);
3644
3645 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3646}
3647
3648static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3649{
3650 struct vcpu_svm *svm = to_svm(vcpu);
3651
3652 if (masked) {
3653 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3654 set_intercept(svm, INTERCEPT_IRET);
3655 } else {
3656 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3657 clr_intercept(svm, INTERCEPT_IRET);
3658 }
3659}
3660
3661static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3662{
3663 struct vcpu_svm *svm = to_svm(vcpu);
3664 struct vmcb *vmcb = svm->vmcb;
3665 int ret;
3666
3667 if (!gif_set(svm) ||
3668 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3669 return 0;
3670
3671 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3672
3673 if (is_guest_mode(vcpu))
3674 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3675
3676 return ret;
3677}
3678
3679static void enable_irq_window(struct kvm_vcpu *vcpu)
3680{
3681 struct vcpu_svm *svm = to_svm(vcpu);
3682
3683 /*
3684 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3685 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3686 * get that intercept, this function will be called again though and
3687 * we'll get the vintr intercept.
3688 */
3689 if (gif_set(svm) && nested_svm_intr(svm)) {
3690 svm_set_vintr(svm);
3691 svm_inject_irq(svm, 0x0);
3692 }
3693}
3694
3695static void enable_nmi_window(struct kvm_vcpu *vcpu)
3696{
3697 struct vcpu_svm *svm = to_svm(vcpu);
3698
3699 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3700 == HF_NMI_MASK)
3701 return; /* IRET will cause a vm exit */
3702
3703 /*
3704 * Something prevents NMI from been injected. Single step over possible
3705 * problem (IRET or exception injection or interrupt shadow)
3706 */
3707 svm->nmi_singlestep = true;
3708 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3709 update_db_bp_intercept(vcpu);
3710}
3711
3712static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3713{
3714 return 0;
3715}
3716
3717static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3718{
3719 struct vcpu_svm *svm = to_svm(vcpu);
3720
3721 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3722 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3723 else
3724 svm->asid_generation--;
3725}
3726
3727static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3728{
3729}
3730
3731static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3732{
3733 struct vcpu_svm *svm = to_svm(vcpu);
3734
3735 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3736 return;
3737
3738 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3739 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3740 kvm_set_cr8(vcpu, cr8);
3741 }
3742}
3743
3744static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3745{
3746 struct vcpu_svm *svm = to_svm(vcpu);
3747 u64 cr8;
3748
3749 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3750 return;
3751
3752 cr8 = kvm_get_cr8(vcpu);
3753 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3754 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3755}
3756
3757static void svm_complete_interrupts(struct vcpu_svm *svm)
3758{
3759 u8 vector;
3760 int type;
3761 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3762 unsigned int3_injected = svm->int3_injected;
3763
3764 svm->int3_injected = 0;
3765
3766 /*
3767 * If we've made progress since setting HF_IRET_MASK, we've
3768 * executed an IRET and can allow NMI injection.
3769 */
3770 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3771 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3772 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3773 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3774 }
3775
3776 svm->vcpu.arch.nmi_injected = false;
3777 kvm_clear_exception_queue(&svm->vcpu);
3778 kvm_clear_interrupt_queue(&svm->vcpu);
3779
3780 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3781 return;
3782
3783 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3784
3785 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3786 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3787
3788 switch (type) {
3789 case SVM_EXITINTINFO_TYPE_NMI:
3790 svm->vcpu.arch.nmi_injected = true;
3791 break;
3792 case SVM_EXITINTINFO_TYPE_EXEPT:
3793 /*
3794 * In case of software exceptions, do not reinject the vector,
3795 * but re-execute the instruction instead. Rewind RIP first
3796 * if we emulated INT3 before.
3797 */
3798 if (kvm_exception_is_soft(vector)) {
3799 if (vector == BP_VECTOR && int3_injected &&
3800 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3801 kvm_rip_write(&svm->vcpu,
3802 kvm_rip_read(&svm->vcpu) -
3803 int3_injected);
3804 break;
3805 }
3806 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3807 u32 err = svm->vmcb->control.exit_int_info_err;
3808 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3809
3810 } else
3811 kvm_requeue_exception(&svm->vcpu, vector);
3812 break;
3813 case SVM_EXITINTINFO_TYPE_INTR:
3814 kvm_queue_interrupt(&svm->vcpu, vector, false);
3815 break;
3816 default:
3817 break;
3818 }
3819}
3820
3821static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3822{
3823 struct vcpu_svm *svm = to_svm(vcpu);
3824 struct vmcb_control_area *control = &svm->vmcb->control;
3825
3826 control->exit_int_info = control->event_inj;
3827 control->exit_int_info_err = control->event_inj_err;
3828 control->event_inj = 0;
3829 svm_complete_interrupts(svm);
3830}
3831
3832static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3833{
3834 struct vcpu_svm *svm = to_svm(vcpu);
3835
3836 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3837 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3838 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3839
3840 /*
3841 * A vmexit emulation is required before the vcpu can be executed
3842 * again.
3843 */
3844 if (unlikely(svm->nested.exit_required))
3845 return;
3846
3847 pre_svm_run(svm);
3848
3849 sync_lapic_to_cr8(vcpu);
3850
3851 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3852
3853 clgi();
3854
3855 local_irq_enable();
3856
3857 asm volatile (
3858 "push %%" _ASM_BP "; \n\t"
3859 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3860 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3861 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3862 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3863 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3864 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3865#ifdef CONFIG_X86_64
3866 "mov %c[r8](%[svm]), %%r8 \n\t"
3867 "mov %c[r9](%[svm]), %%r9 \n\t"
3868 "mov %c[r10](%[svm]), %%r10 \n\t"
3869 "mov %c[r11](%[svm]), %%r11 \n\t"
3870 "mov %c[r12](%[svm]), %%r12 \n\t"
3871 "mov %c[r13](%[svm]), %%r13 \n\t"
3872 "mov %c[r14](%[svm]), %%r14 \n\t"
3873 "mov %c[r15](%[svm]), %%r15 \n\t"
3874#endif
3875
3876 /* Enter guest mode */
3877 "push %%" _ASM_AX " \n\t"
3878 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3879 __ex(SVM_VMLOAD) "\n\t"
3880 __ex(SVM_VMRUN) "\n\t"
3881 __ex(SVM_VMSAVE) "\n\t"
3882 "pop %%" _ASM_AX " \n\t"
3883
3884 /* Save guest registers, load host registers */
3885 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3886 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3887 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3888 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3889 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3890 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3891#ifdef CONFIG_X86_64
3892 "mov %%r8, %c[r8](%[svm]) \n\t"
3893 "mov %%r9, %c[r9](%[svm]) \n\t"
3894 "mov %%r10, %c[r10](%[svm]) \n\t"
3895 "mov %%r11, %c[r11](%[svm]) \n\t"
3896 "mov %%r12, %c[r12](%[svm]) \n\t"
3897 "mov %%r13, %c[r13](%[svm]) \n\t"
3898 "mov %%r14, %c[r14](%[svm]) \n\t"
3899 "mov %%r15, %c[r15](%[svm]) \n\t"
3900#endif
3901 "pop %%" _ASM_BP
3902 :
3903 : [svm]"a"(svm),
3904 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3905 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3906 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3907 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3908 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3909 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3910 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3911#ifdef CONFIG_X86_64
3912 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3913 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3914 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3915 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3916 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3917 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3918 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3919 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3920#endif
3921 : "cc", "memory"
3922#ifdef CONFIG_X86_64
3923 , "rbx", "rcx", "rdx", "rsi", "rdi"
3924 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3925#else
3926 , "ebx", "ecx", "edx", "esi", "edi"
3927#endif
3928 );
3929
3930#ifdef CONFIG_X86_64
3931 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3932#else
3933 loadsegment(fs, svm->host.fs);
3934#ifndef CONFIG_X86_32_LAZY_GS
3935 loadsegment(gs, svm->host.gs);
3936#endif
3937#endif
3938
3939 reload_tss(vcpu);
3940
3941 local_irq_disable();
3942
3943 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3944 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3945 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3946 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3947
3948 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3949
3950 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3951 kvm_before_handle_nmi(&svm->vcpu);
3952
3953 stgi();
3954
3955 /* Any pending NMI will happen here */
3956
3957 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3958 kvm_after_handle_nmi(&svm->vcpu);
3959
3960 sync_cr8_to_lapic(vcpu);
3961
3962 svm->next_rip = 0;
3963
3964 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3965
3966 /* if exit due to PF check for async PF */
3967 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3968 svm->apf_reason = kvm_read_and_reset_pf_reason();
3969
3970 if (npt_enabled) {
3971 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3972 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3973 }
3974
3975 /*
3976 * We need to handle MC intercepts here before the vcpu has a chance to
3977 * change the physical cpu
3978 */
3979 if (unlikely(svm->vmcb->control.exit_code ==
3980 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3981 svm_handle_mce(svm);
3982
3983 mark_all_clean(svm->vmcb);
3984}
3985
3986static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3987{
3988 struct vcpu_svm *svm = to_svm(vcpu);
3989
3990 svm->vmcb->save.cr3 = root;
3991 mark_dirty(svm->vmcb, VMCB_CR);
3992 svm_flush_tlb(vcpu);
3993}
3994
3995static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3996{
3997 struct vcpu_svm *svm = to_svm(vcpu);
3998
3999 svm->vmcb->control.nested_cr3 = root;
4000 mark_dirty(svm->vmcb, VMCB_NPT);
4001
4002 /* Also sync guest cr3 here in case we live migrate */
4003 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4004 mark_dirty(svm->vmcb, VMCB_CR);
4005
4006 svm_flush_tlb(vcpu);
4007}
4008
4009static int is_disabled(void)
4010{
4011 u64 vm_cr;
4012
4013 rdmsrl(MSR_VM_CR, vm_cr);
4014 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4015 return 1;
4016
4017 return 0;
4018}
4019
4020static void
4021svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4022{
4023 /*
4024 * Patch in the VMMCALL instruction:
4025 */
4026 hypercall[0] = 0x0f;
4027 hypercall[1] = 0x01;
4028 hypercall[2] = 0xd9;
4029}
4030
4031static void svm_check_processor_compat(void *rtn)
4032{
4033 *(int *)rtn = 0;
4034}
4035
4036static bool svm_cpu_has_accelerated_tpr(void)
4037{
4038 return false;
4039}
4040
4041static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4042{
4043 return 0;
4044}
4045
4046static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4047{
4048}
4049
4050static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4051{
4052 switch (func) {
4053 case 0x80000001:
4054 if (nested)
4055 entry->ecx |= (1 << 2); /* Set SVM bit */
4056 break;
4057 case 0x8000000A:
4058 entry->eax = 1; /* SVM revision 1 */
4059 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4060 ASID emulation to nested SVM */
4061 entry->ecx = 0; /* Reserved */
4062 entry->edx = 0; /* Per default do not support any
4063 additional features */
4064
4065 /* Support next_rip if host supports it */
4066 if (boot_cpu_has(X86_FEATURE_NRIPS))
4067 entry->edx |= SVM_FEATURE_NRIP;
4068
4069 /* Support NPT for the guest if enabled */
4070 if (npt_enabled)
4071 entry->edx |= SVM_FEATURE_NPT;
4072
4073 break;
4074 }
4075}
4076
4077static int svm_get_lpage_level(void)
4078{
4079 return PT_PDPE_LEVEL;
4080}
4081
4082static bool svm_rdtscp_supported(void)
4083{
4084 return false;
4085}
4086
4087static bool svm_invpcid_supported(void)
4088{
4089 return false;
4090}
4091
4092static bool svm_mpx_supported(void)
4093{
4094 return false;
4095}
4096
4097static bool svm_has_wbinvd_exit(void)
4098{
4099 return true;
4100}
4101
4102static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4103{
4104 struct vcpu_svm *svm = to_svm(vcpu);
4105
4106 set_exception_intercept(svm, NM_VECTOR);
4107 update_cr0_intercept(svm);
4108}
4109
4110#define PRE_EX(exit) { .exit_code = (exit), \
4111 .stage = X86_ICPT_PRE_EXCEPT, }
4112#define POST_EX(exit) { .exit_code = (exit), \
4113 .stage = X86_ICPT_POST_EXCEPT, }
4114#define POST_MEM(exit) { .exit_code = (exit), \
4115 .stage = X86_ICPT_POST_MEMACCESS, }
4116
4117static const struct __x86_intercept {
4118 u32 exit_code;
4119 enum x86_intercept_stage stage;
4120} x86_intercept_map[] = {
4121 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4122 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4123 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4124 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4125 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4126 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4127 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4128 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4129 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4130 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4131 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4132 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4133 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4134 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4135 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4136 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4137 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4138 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4139 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4140 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4141 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4142 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4143 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4144 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4145 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4146 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4147 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4148 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4149 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4150 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4151 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4152 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4153 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4154 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4155 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4156 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4157 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4158 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4159 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4160 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4161 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4162 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4163 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4164 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4165 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4166 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4167};
4168
4169#undef PRE_EX
4170#undef POST_EX
4171#undef POST_MEM
4172
4173static int svm_check_intercept(struct kvm_vcpu *vcpu,
4174 struct x86_instruction_info *info,
4175 enum x86_intercept_stage stage)
4176{
4177 struct vcpu_svm *svm = to_svm(vcpu);
4178 int vmexit, ret = X86EMUL_CONTINUE;
4179 struct __x86_intercept icpt_info;
4180 struct vmcb *vmcb = svm->vmcb;
4181
4182 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4183 goto out;
4184
4185 icpt_info = x86_intercept_map[info->intercept];
4186
4187 if (stage != icpt_info.stage)
4188 goto out;
4189
4190 switch (icpt_info.exit_code) {
4191 case SVM_EXIT_READ_CR0:
4192 if (info->intercept == x86_intercept_cr_read)
4193 icpt_info.exit_code += info->modrm_reg;
4194 break;
4195 case SVM_EXIT_WRITE_CR0: {
4196 unsigned long cr0, val;
4197 u64 intercept;
4198
4199 if (info->intercept == x86_intercept_cr_write)
4200 icpt_info.exit_code += info->modrm_reg;
4201
4202 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4203 break;
4204
4205 intercept = svm->nested.intercept;
4206
4207 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4208 break;
4209
4210 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4211 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4212
4213 if (info->intercept == x86_intercept_lmsw) {
4214 cr0 &= 0xfUL;
4215 val &= 0xfUL;
4216 /* lmsw can't clear PE - catch this here */
4217 if (cr0 & X86_CR0_PE)
4218 val |= X86_CR0_PE;
4219 }
4220
4221 if (cr0 ^ val)
4222 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4223
4224 break;
4225 }
4226 case SVM_EXIT_READ_DR0:
4227 case SVM_EXIT_WRITE_DR0:
4228 icpt_info.exit_code += info->modrm_reg;
4229 break;
4230 case SVM_EXIT_MSR:
4231 if (info->intercept == x86_intercept_wrmsr)
4232 vmcb->control.exit_info_1 = 1;
4233 else
4234 vmcb->control.exit_info_1 = 0;
4235 break;
4236 case SVM_EXIT_PAUSE:
4237 /*
4238 * We get this for NOP only, but pause
4239 * is rep not, check this here
4240 */
4241 if (info->rep_prefix != REPE_PREFIX)
4242 goto out;
4243 case SVM_EXIT_IOIO: {
4244 u64 exit_info;
4245 u32 bytes;
4246
4247 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4248
4249 if (info->intercept == x86_intercept_in ||
4250 info->intercept == x86_intercept_ins) {
4251 exit_info |= SVM_IOIO_TYPE_MASK;
4252 bytes = info->src_bytes;
4253 } else {
4254 bytes = info->dst_bytes;
4255 }
4256
4257 if (info->intercept == x86_intercept_outs ||
4258 info->intercept == x86_intercept_ins)
4259 exit_info |= SVM_IOIO_STR_MASK;
4260
4261 if (info->rep_prefix)
4262 exit_info |= SVM_IOIO_REP_MASK;
4263
4264 bytes = min(bytes, 4u);
4265
4266 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4267
4268 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4269
4270 vmcb->control.exit_info_1 = exit_info;
4271 vmcb->control.exit_info_2 = info->next_rip;
4272
4273 break;
4274 }
4275 default:
4276 break;
4277 }
4278
4279 vmcb->control.next_rip = info->next_rip;
4280 vmcb->control.exit_code = icpt_info.exit_code;
4281 vmexit = nested_svm_exit_handled(svm);
4282
4283 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4284 : X86EMUL_CONTINUE;
4285
4286out:
4287 return ret;
4288}
4289
4290static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4291{
4292 local_irq_enable();
4293}
4294
4295static struct kvm_x86_ops svm_x86_ops = {
4296 .cpu_has_kvm_support = has_svm,
4297 .disabled_by_bios = is_disabled,
4298 .hardware_setup = svm_hardware_setup,
4299 .hardware_unsetup = svm_hardware_unsetup,
4300 .check_processor_compatibility = svm_check_processor_compat,
4301 .hardware_enable = svm_hardware_enable,
4302 .hardware_disable = svm_hardware_disable,
4303 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4304
4305 .vcpu_create = svm_create_vcpu,
4306 .vcpu_free = svm_free_vcpu,
4307 .vcpu_reset = svm_vcpu_reset,
4308
4309 .prepare_guest_switch = svm_prepare_guest_switch,
4310 .vcpu_load = svm_vcpu_load,
4311 .vcpu_put = svm_vcpu_put,
4312
4313 .update_db_bp_intercept = update_db_bp_intercept,
4314 .get_msr = svm_get_msr,
4315 .set_msr = svm_set_msr,
4316 .get_segment_base = svm_get_segment_base,
4317 .get_segment = svm_get_segment,
4318 .set_segment = svm_set_segment,
4319 .get_cpl = svm_get_cpl,
4320 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4321 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4322 .decache_cr3 = svm_decache_cr3,
4323 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4324 .set_cr0 = svm_set_cr0,
4325 .set_cr3 = svm_set_cr3,
4326 .set_cr4 = svm_set_cr4,
4327 .set_efer = svm_set_efer,
4328 .get_idt = svm_get_idt,
4329 .set_idt = svm_set_idt,
4330 .get_gdt = svm_get_gdt,
4331 .set_gdt = svm_set_gdt,
4332 .get_dr6 = svm_get_dr6,
4333 .set_dr6 = svm_set_dr6,
4334 .set_dr7 = svm_set_dr7,
4335 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4336 .cache_reg = svm_cache_reg,
4337 .get_rflags = svm_get_rflags,
4338 .set_rflags = svm_set_rflags,
4339 .fpu_activate = svm_fpu_activate,
4340 .fpu_deactivate = svm_fpu_deactivate,
4341
4342 .tlb_flush = svm_flush_tlb,
4343
4344 .run = svm_vcpu_run,
4345 .handle_exit = handle_exit,
4346 .skip_emulated_instruction = skip_emulated_instruction,
4347 .set_interrupt_shadow = svm_set_interrupt_shadow,
4348 .get_interrupt_shadow = svm_get_interrupt_shadow,
4349 .patch_hypercall = svm_patch_hypercall,
4350 .set_irq = svm_set_irq,
4351 .set_nmi = svm_inject_nmi,
4352 .queue_exception = svm_queue_exception,
4353 .cancel_injection = svm_cancel_injection,
4354 .interrupt_allowed = svm_interrupt_allowed,
4355 .nmi_allowed = svm_nmi_allowed,
4356 .get_nmi_mask = svm_get_nmi_mask,
4357 .set_nmi_mask = svm_set_nmi_mask,
4358 .enable_nmi_window = enable_nmi_window,
4359 .enable_irq_window = enable_irq_window,
4360 .update_cr8_intercept = update_cr8_intercept,
4361 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4362 .vm_has_apicv = svm_vm_has_apicv,
4363 .load_eoi_exitmap = svm_load_eoi_exitmap,
4364 .hwapic_isr_update = svm_hwapic_isr_update,
4365 .sync_pir_to_irr = svm_sync_pir_to_irr,
4366
4367 .set_tss_addr = svm_set_tss_addr,
4368 .get_tdp_level = get_npt_level,
4369 .get_mt_mask = svm_get_mt_mask,
4370
4371 .get_exit_info = svm_get_exit_info,
4372
4373 .get_lpage_level = svm_get_lpage_level,
4374
4375 .cpuid_update = svm_cpuid_update,
4376
4377 .rdtscp_supported = svm_rdtscp_supported,
4378 .invpcid_supported = svm_invpcid_supported,
4379 .mpx_supported = svm_mpx_supported,
4380
4381 .set_supported_cpuid = svm_set_supported_cpuid,
4382
4383 .has_wbinvd_exit = svm_has_wbinvd_exit,
4384
4385 .set_tsc_khz = svm_set_tsc_khz,
4386 .read_tsc_offset = svm_read_tsc_offset,
4387 .write_tsc_offset = svm_write_tsc_offset,
4388 .adjust_tsc_offset = svm_adjust_tsc_offset,
4389 .compute_tsc_offset = svm_compute_tsc_offset,
4390 .read_l1_tsc = svm_read_l1_tsc,
4391
4392 .set_tdp_cr3 = set_tdp_cr3,
4393
4394 .check_intercept = svm_check_intercept,
4395 .handle_external_intr = svm_handle_external_intr,
4396};
4397
4398static int __init svm_init(void)
4399{
4400 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4401 __alignof__(struct vcpu_svm), THIS_MODULE);
4402}
4403
4404static void __exit svm_exit(void)
4405{
4406 kvm_exit();
4407}
4408
4409module_init(svm_init)
4410module_exit(svm_exit)