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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * RocketPort device driver for Linux
4 *
5 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 *
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 */
9
10/*
11 * Kernel Synchronization:
12 *
13 * This driver has 2 kernel control paths - exception handlers (calls into the driver
14 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
15 * are not used.
16 *
17 * Critical data:
18 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
19 * serial port state information and the xmit_buf circular buffer. Protected by
20 * a per port spinlock.
21 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
22 * is data to be transmitted. Protected by atomic bit operations.
23 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
24 *
25 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
26 * simultaneous access to the same port by more than one process.
27 */
28
29/****** Defines ******/
30#define ROCKET_PARANOIA_CHECK
31#define ROCKET_DISABLE_SIMUSAGE
32
33#undef ROCKET_SOFT_FLOW
34#undef ROCKET_DEBUG_OPEN
35#undef ROCKET_DEBUG_INTR
36#undef ROCKET_DEBUG_WRITE
37#undef ROCKET_DEBUG_FLOW
38#undef ROCKET_DEBUG_THROTTLE
39#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
40#undef ROCKET_DEBUG_RECEIVE
41#undef ROCKET_DEBUG_HANGUP
42#undef REV_PCI_ORDER
43#undef ROCKET_DEBUG_IO
44
45#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
46
47/****** Kernel includes ******/
48
49#include <linux/module.h>
50#include <linux/errno.h>
51#include <linux/major.h>
52#include <linux/kernel.h>
53#include <linux/signal.h>
54#include <linux/slab.h>
55#include <linux/mm.h>
56#include <linux/sched.h>
57#include <linux/timer.h>
58#include <linux/interrupt.h>
59#include <linux/tty.h>
60#include <linux/tty_driver.h>
61#include <linux/tty_flip.h>
62#include <linux/serial.h>
63#include <linux/string.h>
64#include <linux/fcntl.h>
65#include <linux/ptrace.h>
66#include <linux/mutex.h>
67#include <linux/ioport.h>
68#include <linux/delay.h>
69#include <linux/completion.h>
70#include <linux/wait.h>
71#include <linux/pci.h>
72#include <linux/uaccess.h>
73#include <linux/atomic.h>
74#include <asm/unaligned.h>
75#include <linux/bitops.h>
76#include <linux/spinlock.h>
77#include <linux/init.h>
78
79/****** RocketPort includes ******/
80
81#include "rocket_int.h"
82#include "rocket.h"
83
84#define ROCKET_VERSION "2.09"
85#define ROCKET_DATE "12-June-2003"
86
87/****** RocketPort Local Variables ******/
88
89static void rp_do_poll(struct timer_list *unused);
90
91static struct tty_driver *rocket_driver;
92
93static struct rocket_version driver_version = {
94 ROCKET_VERSION, ROCKET_DATE
95};
96
97static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
98static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
99 /* eg. Bit 0 indicates port 0 has xmit data, ... */
100static atomic_t rp_num_ports_open; /* Number of serial ports open */
101static DEFINE_TIMER(rocket_timer, rp_do_poll);
102
103static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
104static unsigned long board2;
105static unsigned long board3;
106static unsigned long board4;
107static unsigned long controller;
108static bool support_low_speed;
109static unsigned long modem1;
110static unsigned long modem2;
111static unsigned long modem3;
112static unsigned long modem4;
113static unsigned long pc104_1[8];
114static unsigned long pc104_2[8];
115static unsigned long pc104_3[8];
116static unsigned long pc104_4[8];
117static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
118
119static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
120static unsigned long rcktpt_io_addr[NUM_BOARDS];
121static int rcktpt_type[NUM_BOARDS];
122static int is_PCI[NUM_BOARDS];
123static rocketModel_t rocketModel[NUM_BOARDS];
124static int max_board;
125static const struct tty_port_operations rocket_port_ops;
126
127/*
128 * The following arrays define the interrupt bits corresponding to each AIOP.
129 * These bits are different between the ISA and regular PCI boards and the
130 * Universal PCI boards.
131 */
132
133static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
134 AIOP_INTR_BIT_0,
135 AIOP_INTR_BIT_1,
136 AIOP_INTR_BIT_2,
137 AIOP_INTR_BIT_3
138};
139
140#ifdef CONFIG_PCI
141static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
142 UPCI_AIOP_INTR_BIT_0,
143 UPCI_AIOP_INTR_BIT_1,
144 UPCI_AIOP_INTR_BIT_2,
145 UPCI_AIOP_INTR_BIT_3
146};
147#endif
148
149static Byte_t RData[RDATASIZE] = {
150 0x00, 0x09, 0xf6, 0x82,
151 0x02, 0x09, 0x86, 0xfb,
152 0x04, 0x09, 0x00, 0x0a,
153 0x06, 0x09, 0x01, 0x0a,
154 0x08, 0x09, 0x8a, 0x13,
155 0x0a, 0x09, 0xc5, 0x11,
156 0x0c, 0x09, 0x86, 0x85,
157 0x0e, 0x09, 0x20, 0x0a,
158 0x10, 0x09, 0x21, 0x0a,
159 0x12, 0x09, 0x41, 0xff,
160 0x14, 0x09, 0x82, 0x00,
161 0x16, 0x09, 0x82, 0x7b,
162 0x18, 0x09, 0x8a, 0x7d,
163 0x1a, 0x09, 0x88, 0x81,
164 0x1c, 0x09, 0x86, 0x7a,
165 0x1e, 0x09, 0x84, 0x81,
166 0x20, 0x09, 0x82, 0x7c,
167 0x22, 0x09, 0x0a, 0x0a
168};
169
170static Byte_t RRegData[RREGDATASIZE] = {
171 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
172 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
173 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
174 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
175 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
176 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
177 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
178 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
179 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
180 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
181 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
182 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
183 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
184};
185
186static CONTROLLER_T sController[CTL_SIZE] = {
187 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
188 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
189 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
190 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
191 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
192 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
193 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
194 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
195};
196
197static Byte_t sBitMapClrTbl[8] = {
198 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
199};
200
201static Byte_t sBitMapSetTbl[8] = {
202 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
203};
204
205static int sClockPrescale = 0x14;
206
207/*
208 * Line number is the ttySIx number (x), the Minor number. We
209 * assign them sequentially, starting at zero. The following
210 * array keeps track of the line number assigned to a given board/aiop/channel.
211 */
212static unsigned char lineNumbers[MAX_RP_PORTS];
213static unsigned long nextLineNumber;
214
215/***** RocketPort Static Prototypes *********/
216static int __init init_ISA(int i);
217static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
218static void rp_flush_buffer(struct tty_struct *tty);
219static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
220static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
221static void rp_start(struct tty_struct *tty);
222static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
223 int ChanNum);
224static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
225static void sFlushRxFIFO(CHANNEL_T * ChP);
226static void sFlushTxFIFO(CHANNEL_T * ChP);
227static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
228static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
229static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
230static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
231static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
232static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
233 ByteIO_t * AiopIOList, int AiopIOListSize,
234 int IRQNum, Byte_t Frequency, int PeriodicOnly);
235static int sReadAiopID(ByteIO_t io);
236static int sReadAiopNumChan(WordIO_t io);
237
238MODULE_AUTHOR("Theodore Ts'o");
239MODULE_DESCRIPTION("Comtrol RocketPort driver");
240module_param_hw(board1, ulong, ioport, 0);
241MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
242module_param_hw(board2, ulong, ioport, 0);
243MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
244module_param_hw(board3, ulong, ioport, 0);
245MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
246module_param_hw(board4, ulong, ioport, 0);
247MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
248module_param_hw(controller, ulong, ioport, 0);
249MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
250module_param(support_low_speed, bool, 0);
251MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
252module_param(modem1, ulong, 0);
253MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
254module_param(modem2, ulong, 0);
255MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
256module_param(modem3, ulong, 0);
257MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
258module_param(modem4, ulong, 0);
259MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
260module_param_array(pc104_1, ulong, NULL, 0);
261MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
262module_param_array(pc104_2, ulong, NULL, 0);
263MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
264module_param_array(pc104_3, ulong, NULL, 0);
265MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
266module_param_array(pc104_4, ulong, NULL, 0);
267MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
268
269static int __init rp_init(void);
270static void rp_cleanup_module(void);
271
272module_init(rp_init);
273module_exit(rp_cleanup_module);
274
275
276MODULE_LICENSE("Dual BSD/GPL");
277
278/*************************************************************************/
279/* Module code starts here */
280
281static inline int rocket_paranoia_check(struct r_port *info,
282 const char *routine)
283{
284#ifdef ROCKET_PARANOIA_CHECK
285 if (!info)
286 return 1;
287 if (info->magic != RPORT_MAGIC) {
288 printk(KERN_WARNING "Warning: bad magic number for rocketport "
289 "struct in %s\n", routine);
290 return 1;
291 }
292#endif
293 return 0;
294}
295
296
297/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
298 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
299 * tty layer.
300 */
301static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
302 unsigned int ChanStatus)
303{
304 unsigned int CharNStat;
305 int ToRecv, wRecv, space;
306 unsigned char *cbuf;
307
308 ToRecv = sGetRxCnt(cp);
309#ifdef ROCKET_DEBUG_INTR
310 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
311#endif
312 if (ToRecv == 0)
313 return;
314
315 /*
316 * if status indicates there are errored characters in the
317 * FIFO, then enter status mode (a word in FIFO holds
318 * character and status).
319 */
320 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
321 if (!(ChanStatus & STATMODE)) {
322#ifdef ROCKET_DEBUG_RECEIVE
323 printk(KERN_INFO "Entering STATMODE...\n");
324#endif
325 ChanStatus |= STATMODE;
326 sEnRxStatusMode(cp);
327 }
328 }
329
330 /*
331 * if we previously entered status mode, then read down the
332 * FIFO one word at a time, pulling apart the character and
333 * the status. Update error counters depending on status
334 */
335 if (ChanStatus & STATMODE) {
336#ifdef ROCKET_DEBUG_RECEIVE
337 printk(KERN_INFO "Ignore %x, read %x...\n",
338 info->ignore_status_mask, info->read_status_mask);
339#endif
340 while (ToRecv) {
341 char flag;
342
343 CharNStat = sInW(sGetTxRxDataIO(cp));
344#ifdef ROCKET_DEBUG_RECEIVE
345 printk(KERN_INFO "%x...\n", CharNStat);
346#endif
347 if (CharNStat & STMBREAKH)
348 CharNStat &= ~(STMFRAMEH | STMPARITYH);
349 if (CharNStat & info->ignore_status_mask) {
350 ToRecv--;
351 continue;
352 }
353 CharNStat &= info->read_status_mask;
354 if (CharNStat & STMBREAKH)
355 flag = TTY_BREAK;
356 else if (CharNStat & STMPARITYH)
357 flag = TTY_PARITY;
358 else if (CharNStat & STMFRAMEH)
359 flag = TTY_FRAME;
360 else if (CharNStat & STMRCVROVRH)
361 flag = TTY_OVERRUN;
362 else
363 flag = TTY_NORMAL;
364 tty_insert_flip_char(&info->port, CharNStat & 0xff,
365 flag);
366 ToRecv--;
367 }
368
369 /*
370 * after we've emptied the FIFO in status mode, turn
371 * status mode back off
372 */
373 if (sGetRxCnt(cp) == 0) {
374#ifdef ROCKET_DEBUG_RECEIVE
375 printk(KERN_INFO "Status mode off.\n");
376#endif
377 sDisRxStatusMode(cp);
378 }
379 } else {
380 /*
381 * we aren't in status mode, so read down the FIFO two
382 * characters at time by doing repeated word IO
383 * transfer.
384 */
385 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
386 if (space < ToRecv) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
389#endif
390 if (space <= 0)
391 return;
392 ToRecv = space;
393 }
394 wRecv = ToRecv >> 1;
395 if (wRecv)
396 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
397 if (ToRecv & 1)
398 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
399 }
400 /* Push the data up to the tty layer */
401 tty_flip_buffer_push(&info->port);
402}
403
404/*
405 * Serial port transmit data function. Called from the timer polling loop as a
406 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
407 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
408 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
409 */
410static void rp_do_transmit(struct r_port *info)
411{
412 int c;
413 CHANNEL_t *cp = &info->channel;
414 struct tty_struct *tty;
415 unsigned long flags;
416
417#ifdef ROCKET_DEBUG_INTR
418 printk(KERN_DEBUG "%s\n", __func__);
419#endif
420 if (!info)
421 return;
422 tty = tty_port_tty_get(&info->port);
423
424 if (tty == NULL) {
425 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
426 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
427 return;
428 }
429
430 spin_lock_irqsave(&info->slock, flags);
431 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
432
433 /* Loop sending data to FIFO until done or FIFO full */
434 while (1) {
435 if (tty->stopped)
436 break;
437 c = min(info->xmit_fifo_room, info->xmit_cnt);
438 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
439 if (c <= 0 || info->xmit_fifo_room <= 0)
440 break;
441 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
442 if (c & 1)
443 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
444 info->xmit_tail += c;
445 info->xmit_tail &= XMIT_BUF_SIZE - 1;
446 info->xmit_cnt -= c;
447 info->xmit_fifo_room -= c;
448#ifdef ROCKET_DEBUG_INTR
449 printk(KERN_INFO "tx %d chars...\n", c);
450#endif
451 }
452
453 if (info->xmit_cnt == 0)
454 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
455
456 if (info->xmit_cnt < WAKEUP_CHARS) {
457 tty_wakeup(tty);
458#ifdef ROCKETPORT_HAVE_POLL_WAIT
459 wake_up_interruptible(&tty->poll_wait);
460#endif
461 }
462
463 spin_unlock_irqrestore(&info->slock, flags);
464 tty_kref_put(tty);
465
466#ifdef ROCKET_DEBUG_INTR
467 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
468 info->xmit_tail, info->xmit_fifo_room);
469#endif
470}
471
472/*
473 * Called when a serial port signals it has read data in it's RX FIFO.
474 * It checks what interrupts are pending and services them, including
475 * receiving serial data.
476 */
477static void rp_handle_port(struct r_port *info)
478{
479 CHANNEL_t *cp;
480 unsigned int IntMask, ChanStatus;
481
482 if (!info)
483 return;
484
485 if (!tty_port_initialized(&info->port)) {
486 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
487 "info->flags & NOT_INIT\n");
488 return;
489 }
490
491 cp = &info->channel;
492
493 IntMask = sGetChanIntID(cp) & info->intmask;
494#ifdef ROCKET_DEBUG_INTR
495 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
496#endif
497 ChanStatus = sGetChanStatus(cp);
498 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
499 rp_do_receive(info, cp, ChanStatus);
500 }
501 if (IntMask & DELTA_CD) { /* CD change */
502#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
503 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
504 (ChanStatus & CD_ACT) ? "on" : "off");
505#endif
506 if (!(ChanStatus & CD_ACT) && info->cd_status) {
507#ifdef ROCKET_DEBUG_HANGUP
508 printk(KERN_INFO "CD drop, calling hangup.\n");
509#endif
510 tty_port_tty_hangup(&info->port, false);
511 }
512 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
513 wake_up_interruptible(&info->port.open_wait);
514 }
515#ifdef ROCKET_DEBUG_INTR
516 if (IntMask & DELTA_CTS) { /* CTS change */
517 printk(KERN_INFO "CTS change...\n");
518 }
519 if (IntMask & DELTA_DSR) { /* DSR change */
520 printk(KERN_INFO "DSR change...\n");
521 }
522#endif
523}
524
525/*
526 * The top level polling routine. Repeats every 1/100 HZ (10ms).
527 */
528static void rp_do_poll(struct timer_list *unused)
529{
530 CONTROLLER_t *ctlp;
531 int ctrl, aiop, ch, line;
532 unsigned int xmitmask, i;
533 unsigned int CtlMask;
534 unsigned char AiopMask;
535 Word_t bit;
536
537 /* Walk through all the boards (ctrl's) */
538 for (ctrl = 0; ctrl < max_board; ctrl++) {
539 if (rcktpt_io_addr[ctrl] <= 0)
540 continue;
541
542 /* Get a ptr to the board's control struct */
543 ctlp = sCtlNumToCtlPtr(ctrl);
544
545 /* Get the interrupt status from the board */
546#ifdef CONFIG_PCI
547 if (ctlp->BusType == isPCI)
548 CtlMask = sPCIGetControllerIntStatus(ctlp);
549 else
550#endif
551 CtlMask = sGetControllerIntStatus(ctlp);
552
553 /* Check if any AIOP read bits are set */
554 for (aiop = 0; CtlMask; aiop++) {
555 bit = ctlp->AiopIntrBits[aiop];
556 if (CtlMask & bit) {
557 CtlMask &= ~bit;
558 AiopMask = sGetAiopIntStatus(ctlp, aiop);
559
560 /* Check if any port read bits are set */
561 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
562 if (AiopMask & 1) {
563
564 /* Get the line number (/dev/ttyRx number). */
565 /* Read the data from the port. */
566 line = GetLineNumber(ctrl, aiop, ch);
567 rp_handle_port(rp_table[line]);
568 }
569 }
570 }
571 }
572
573 xmitmask = xmit_flags[ctrl];
574
575 /*
576 * xmit_flags contains bit-significant flags, indicating there is data
577 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
578 * 1, ... (32 total possible). The variable i has the aiop and ch
579 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
580 */
581 if (xmitmask) {
582 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
583 if (xmitmask & (1 << i)) {
584 aiop = (i & 0x18) >> 3;
585 ch = i & 0x07;
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_do_transmit(rp_table[line]);
588 }
589 }
590 }
591 }
592
593 /*
594 * Reset the timer so we get called at the next clock tick (10ms).
595 */
596 if (atomic_read(&rp_num_ports_open))
597 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
598}
599
600/*
601 * Initializes the r_port structure for a port, as well as enabling the port on
602 * the board.
603 * Inputs: board, aiop, chan numbers
604 */
605static void __init
606init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
607{
608 unsigned rocketMode;
609 struct r_port *info;
610 int line;
611 CONTROLLER_T *ctlp;
612
613 /* Get the next available line number */
614 line = SetLineNumber(board, aiop, chan);
615
616 ctlp = sCtlNumToCtlPtr(board);
617
618 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
619 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
620 if (!info) {
621 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
622 line);
623 return;
624 }
625
626 info->magic = RPORT_MAGIC;
627 info->line = line;
628 info->ctlp = ctlp;
629 info->board = board;
630 info->aiop = aiop;
631 info->chan = chan;
632 tty_port_init(&info->port);
633 info->port.ops = &rocket_port_ops;
634 info->flags &= ~ROCKET_MODE_MASK;
635 if (board < ARRAY_SIZE(pc104) && line < ARRAY_SIZE(pc104_1))
636 switch (pc104[board][line]) {
637 case 422:
638 info->flags |= ROCKET_MODE_RS422;
639 break;
640 case 485:
641 info->flags |= ROCKET_MODE_RS485;
642 break;
643 case 232:
644 default:
645 info->flags |= ROCKET_MODE_RS232;
646 break;
647 }
648 else
649 info->flags |= ROCKET_MODE_RS232;
650
651 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
652 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
653 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
654 board, aiop, chan);
655 tty_port_destroy(&info->port);
656 kfree(info);
657 return;
658 }
659
660 rocketMode = info->flags & ROCKET_MODE_MASK;
661
662 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
663 sEnRTSToggle(&info->channel);
664 else
665 sDisRTSToggle(&info->channel);
666
667 if (ctlp->boardType == ROCKET_TYPE_PC104) {
668 switch (rocketMode) {
669 case ROCKET_MODE_RS485:
670 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
671 break;
672 case ROCKET_MODE_RS422:
673 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
674 break;
675 case ROCKET_MODE_RS232:
676 default:
677 if (info->flags & ROCKET_RTS_TOGGLE)
678 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
679 else
680 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
681 break;
682 }
683 }
684 spin_lock_init(&info->slock);
685 mutex_init(&info->write_mtx);
686 rp_table[line] = info;
687 tty_port_register_device(&info->port, rocket_driver, line,
688 pci_dev ? &pci_dev->dev : NULL);
689}
690
691/*
692 * Configures a rocketport port according to its termio settings. Called from
693 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
694 */
695static void configure_r_port(struct tty_struct *tty, struct r_port *info,
696 struct ktermios *old_termios)
697{
698 unsigned cflag;
699 unsigned long flags;
700 unsigned rocketMode;
701 int bits, baud, divisor;
702 CHANNEL_t *cp;
703 struct ktermios *t = &tty->termios;
704
705 cp = &info->channel;
706 cflag = t->c_cflag;
707
708 /* Byte size and parity */
709 if ((cflag & CSIZE) == CS8) {
710 sSetData8(cp);
711 bits = 10;
712 } else {
713 sSetData7(cp);
714 bits = 9;
715 }
716 if (cflag & CSTOPB) {
717 sSetStop2(cp);
718 bits++;
719 } else {
720 sSetStop1(cp);
721 }
722
723 if (cflag & PARENB) {
724 sEnParity(cp);
725 bits++;
726 if (cflag & PARODD) {
727 sSetOddParity(cp);
728 } else {
729 sSetEvenParity(cp);
730 }
731 } else {
732 sDisParity(cp);
733 }
734
735 /* baud rate */
736 baud = tty_get_baud_rate(tty);
737 if (!baud)
738 baud = 9600;
739 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
740 if ((divisor >= 8192 || divisor < 0) && old_termios) {
741 baud = tty_termios_baud_rate(old_termios);
742 if (!baud)
743 baud = 9600;
744 divisor = (rp_baud_base[info->board] / baud) - 1;
745 }
746 if (divisor >= 8192 || divisor < 0) {
747 baud = 9600;
748 divisor = (rp_baud_base[info->board] / baud) - 1;
749 }
750 info->cps = baud / bits;
751 sSetBaud(cp, divisor);
752
753 /* FIXME: Should really back compute a baud rate from the divisor */
754 tty_encode_baud_rate(tty, baud, baud);
755
756 if (cflag & CRTSCTS) {
757 info->intmask |= DELTA_CTS;
758 sEnCTSFlowCtl(cp);
759 } else {
760 info->intmask &= ~DELTA_CTS;
761 sDisCTSFlowCtl(cp);
762 }
763 if (cflag & CLOCAL) {
764 info->intmask &= ~DELTA_CD;
765 } else {
766 spin_lock_irqsave(&info->slock, flags);
767 if (sGetChanStatus(cp) & CD_ACT)
768 info->cd_status = 1;
769 else
770 info->cd_status = 0;
771 info->intmask |= DELTA_CD;
772 spin_unlock_irqrestore(&info->slock, flags);
773 }
774
775 /*
776 * Handle software flow control in the board
777 */
778#ifdef ROCKET_SOFT_FLOW
779 if (I_IXON(tty)) {
780 sEnTxSoftFlowCtl(cp);
781 if (I_IXANY(tty)) {
782 sEnIXANY(cp);
783 } else {
784 sDisIXANY(cp);
785 }
786 sSetTxXONChar(cp, START_CHAR(tty));
787 sSetTxXOFFChar(cp, STOP_CHAR(tty));
788 } else {
789 sDisTxSoftFlowCtl(cp);
790 sDisIXANY(cp);
791 sClrTxXOFF(cp);
792 }
793#endif
794
795 /*
796 * Set up ignore/read mask words
797 */
798 info->read_status_mask = STMRCVROVRH | 0xFF;
799 if (I_INPCK(tty))
800 info->read_status_mask |= STMFRAMEH | STMPARITYH;
801 if (I_BRKINT(tty) || I_PARMRK(tty))
802 info->read_status_mask |= STMBREAKH;
803
804 /*
805 * Characters to ignore
806 */
807 info->ignore_status_mask = 0;
808 if (I_IGNPAR(tty))
809 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
810 if (I_IGNBRK(tty)) {
811 info->ignore_status_mask |= STMBREAKH;
812 /*
813 * If we're ignoring parity and break indicators,
814 * ignore overruns too. (For real raw support).
815 */
816 if (I_IGNPAR(tty))
817 info->ignore_status_mask |= STMRCVROVRH;
818 }
819
820 rocketMode = info->flags & ROCKET_MODE_MASK;
821
822 if ((info->flags & ROCKET_RTS_TOGGLE)
823 || (rocketMode == ROCKET_MODE_RS485))
824 sEnRTSToggle(cp);
825 else
826 sDisRTSToggle(cp);
827
828 sSetRTS(&info->channel);
829
830 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
831 switch (rocketMode) {
832 case ROCKET_MODE_RS485:
833 sSetInterfaceMode(cp, InterfaceModeRS485);
834 break;
835 case ROCKET_MODE_RS422:
836 sSetInterfaceMode(cp, InterfaceModeRS422);
837 break;
838 case ROCKET_MODE_RS232:
839 default:
840 if (info->flags & ROCKET_RTS_TOGGLE)
841 sSetInterfaceMode(cp, InterfaceModeRS232T);
842 else
843 sSetInterfaceMode(cp, InterfaceModeRS232);
844 break;
845 }
846 }
847}
848
849static int carrier_raised(struct tty_port *port)
850{
851 struct r_port *info = container_of(port, struct r_port, port);
852 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
853}
854
855static void dtr_rts(struct tty_port *port, int on)
856{
857 struct r_port *info = container_of(port, struct r_port, port);
858 if (on) {
859 sSetDTR(&info->channel);
860 sSetRTS(&info->channel);
861 } else {
862 sClrDTR(&info->channel);
863 sClrRTS(&info->channel);
864 }
865}
866
867/*
868 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
869 * port's r_port struct. Initializes the port hardware.
870 */
871static int rp_open(struct tty_struct *tty, struct file *filp)
872{
873 struct r_port *info;
874 struct tty_port *port;
875 int retval;
876 CHANNEL_t *cp;
877 unsigned long page;
878
879 info = rp_table[tty->index];
880 if (info == NULL)
881 return -ENXIO;
882 port = &info->port;
883
884 page = __get_free_page(GFP_KERNEL);
885 if (!page)
886 return -ENOMEM;
887
888 /*
889 * We must not sleep from here until the port is marked fully in use.
890 */
891 if (info->xmit_buf)
892 free_page(page);
893 else
894 info->xmit_buf = (unsigned char *) page;
895
896 tty->driver_data = info;
897 tty_port_tty_set(port, tty);
898
899 if (port->count++ == 0) {
900 atomic_inc(&rp_num_ports_open);
901
902#ifdef ROCKET_DEBUG_OPEN
903 printk(KERN_INFO "rocket mod++ = %d...\n",
904 atomic_read(&rp_num_ports_open));
905#endif
906 }
907#ifdef ROCKET_DEBUG_OPEN
908 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
909#endif
910
911 /*
912 * Info->count is now 1; so it's safe to sleep now.
913 */
914 if (!tty_port_initialized(port)) {
915 cp = &info->channel;
916 sSetRxTrigger(cp, TRIG_1);
917 if (sGetChanStatus(cp) & CD_ACT)
918 info->cd_status = 1;
919 else
920 info->cd_status = 0;
921 sDisRxStatusMode(cp);
922 sFlushRxFIFO(cp);
923 sFlushTxFIFO(cp);
924
925 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
926 sSetRxTrigger(cp, TRIG_1);
927
928 sGetChanStatus(cp);
929 sDisRxStatusMode(cp);
930 sClrTxXOFF(cp);
931
932 sDisCTSFlowCtl(cp);
933 sDisTxSoftFlowCtl(cp);
934
935 sEnRxFIFO(cp);
936 sEnTransmit(cp);
937
938 tty_port_set_initialized(&info->port, 1);
939
940 configure_r_port(tty, info, NULL);
941 if (C_BAUD(tty)) {
942 sSetDTR(cp);
943 sSetRTS(cp);
944 }
945 }
946 /* Starts (or resets) the maint polling loop */
947 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
948
949 retval = tty_port_block_til_ready(port, tty, filp);
950 if (retval) {
951#ifdef ROCKET_DEBUG_OPEN
952 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
953#endif
954 return retval;
955 }
956 return 0;
957}
958
959/*
960 * Exception handler that closes a serial port. info->port.count is considered critical.
961 */
962static void rp_close(struct tty_struct *tty, struct file *filp)
963{
964 struct r_port *info = tty->driver_data;
965 struct tty_port *port = &info->port;
966 int timeout;
967 CHANNEL_t *cp;
968
969 if (rocket_paranoia_check(info, "rp_close"))
970 return;
971
972#ifdef ROCKET_DEBUG_OPEN
973 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
974#endif
975
976 if (tty_port_close_start(port, tty, filp) == 0)
977 return;
978
979 mutex_lock(&port->mutex);
980 cp = &info->channel;
981 /*
982 * Before we drop DTR, make sure the UART transmitter
983 * has completely drained; this is especially
984 * important if there is a transmit FIFO!
985 */
986 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
987 if (timeout == 0)
988 timeout = 1;
989 rp_wait_until_sent(tty, timeout);
990 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
991
992 sDisTransmit(cp);
993 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
994 sDisCTSFlowCtl(cp);
995 sDisTxSoftFlowCtl(cp);
996 sClrTxXOFF(cp);
997 sFlushRxFIFO(cp);
998 sFlushTxFIFO(cp);
999 sClrRTS(cp);
1000 if (C_HUPCL(tty))
1001 sClrDTR(cp);
1002
1003 rp_flush_buffer(tty);
1004
1005 tty_ldisc_flush(tty);
1006
1007 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1008
1009 /* We can't yet use tty_port_close_end as the buffer handling in this
1010 driver is a bit different to the usual */
1011
1012 if (port->blocked_open) {
1013 if (port->close_delay) {
1014 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1015 }
1016 wake_up_interruptible(&port->open_wait);
1017 } else {
1018 if (info->xmit_buf) {
1019 free_page((unsigned long) info->xmit_buf);
1020 info->xmit_buf = NULL;
1021 }
1022 }
1023 spin_lock_irq(&port->lock);
1024 tty->closing = 0;
1025 spin_unlock_irq(&port->lock);
1026 tty_port_set_initialized(port, 0);
1027 tty_port_set_active(port, 0);
1028 mutex_unlock(&port->mutex);
1029 tty_port_tty_set(port, NULL);
1030
1031 atomic_dec(&rp_num_ports_open);
1032
1033#ifdef ROCKET_DEBUG_OPEN
1034 printk(KERN_INFO "rocket mod-- = %d...\n",
1035 atomic_read(&rp_num_ports_open));
1036 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1037#endif
1038
1039}
1040
1041static void rp_set_termios(struct tty_struct *tty,
1042 struct ktermios *old_termios)
1043{
1044 struct r_port *info = tty->driver_data;
1045 CHANNEL_t *cp;
1046 unsigned cflag;
1047
1048 if (rocket_paranoia_check(info, "rp_set_termios"))
1049 return;
1050
1051 cflag = tty->termios.c_cflag;
1052
1053 /*
1054 * This driver doesn't support CS5 or CS6
1055 */
1056 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1057 tty->termios.c_cflag =
1058 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1059 /* Or CMSPAR */
1060 tty->termios.c_cflag &= ~CMSPAR;
1061
1062 configure_r_port(tty, info, old_termios);
1063
1064 cp = &info->channel;
1065
1066 /* Handle transition to B0 status */
1067 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1068 sClrDTR(cp);
1069 sClrRTS(cp);
1070 }
1071
1072 /* Handle transition away from B0 status */
1073 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1074 sSetRTS(cp);
1075 sSetDTR(cp);
1076 }
1077
1078 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1079 rp_start(tty);
1080}
1081
1082static int rp_break(struct tty_struct *tty, int break_state)
1083{
1084 struct r_port *info = tty->driver_data;
1085 unsigned long flags;
1086
1087 if (rocket_paranoia_check(info, "rp_break"))
1088 return -EINVAL;
1089
1090 spin_lock_irqsave(&info->slock, flags);
1091 if (break_state == -1)
1092 sSendBreak(&info->channel);
1093 else
1094 sClrBreak(&info->channel);
1095 spin_unlock_irqrestore(&info->slock, flags);
1096 return 0;
1097}
1098
1099/*
1100 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1101 * the UPCI boards was added, it was decided to make this a function because
1102 * the macro was getting too complicated. All cases except the first one
1103 * (UPCIRingInd) are taken directly from the original macro.
1104 */
1105static int sGetChanRI(CHANNEL_T * ChP)
1106{
1107 CONTROLLER_t *CtlP = ChP->CtlP;
1108 int ChanNum = ChP->ChanNum;
1109 int RingInd = 0;
1110
1111 if (CtlP->UPCIRingInd)
1112 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1113 else if (CtlP->AltChanRingIndicator)
1114 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1115 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1116 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1117
1118 return RingInd;
1119}
1120
1121/********************************************************************************************/
1122/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1123
1124/*
1125 * Returns the state of the serial modem control lines. These next 2 functions
1126 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1127 */
1128static int rp_tiocmget(struct tty_struct *tty)
1129{
1130 struct r_port *info = tty->driver_data;
1131 unsigned int control, result, ChanStatus;
1132
1133 ChanStatus = sGetChanStatusLo(&info->channel);
1134 control = info->channel.TxControl[3];
1135 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1136 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1137 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1138 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1139 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1140 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1141
1142 return result;
1143}
1144
1145/*
1146 * Sets the modem control lines
1147 */
1148static int rp_tiocmset(struct tty_struct *tty,
1149 unsigned int set, unsigned int clear)
1150{
1151 struct r_port *info = tty->driver_data;
1152
1153 if (set & TIOCM_RTS)
1154 info->channel.TxControl[3] |= SET_RTS;
1155 if (set & TIOCM_DTR)
1156 info->channel.TxControl[3] |= SET_DTR;
1157 if (clear & TIOCM_RTS)
1158 info->channel.TxControl[3] &= ~SET_RTS;
1159 if (clear & TIOCM_DTR)
1160 info->channel.TxControl[3] &= ~SET_DTR;
1161
1162 out32(info->channel.IndexAddr, info->channel.TxControl);
1163 return 0;
1164}
1165
1166static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1167{
1168 struct rocket_config tmp;
1169
1170 memset(&tmp, 0, sizeof (tmp));
1171 mutex_lock(&info->port.mutex);
1172 tmp.line = info->line;
1173 tmp.flags = info->flags;
1174 tmp.close_delay = info->port.close_delay;
1175 tmp.closing_wait = info->port.closing_wait;
1176 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1177 mutex_unlock(&info->port.mutex);
1178
1179 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1180 return -EFAULT;
1181 return 0;
1182}
1183
1184static int set_config(struct tty_struct *tty, struct r_port *info,
1185 struct rocket_config __user *new_info)
1186{
1187 struct rocket_config new_serial;
1188
1189 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1190 return -EFAULT;
1191
1192 mutex_lock(&info->port.mutex);
1193 if (!capable(CAP_SYS_ADMIN))
1194 {
1195 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1196 mutex_unlock(&info->port.mutex);
1197 return -EPERM;
1198 }
1199 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1200 mutex_unlock(&info->port.mutex);
1201 return 0;
1202 }
1203
1204 if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
1205 /* warn about deprecation, unless clearing */
1206 if (new_serial.flags & ROCKET_SPD_MASK)
1207 dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
1208 }
1209
1210 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1211 info->port.close_delay = new_serial.close_delay;
1212 info->port.closing_wait = new_serial.closing_wait;
1213
1214 mutex_unlock(&info->port.mutex);
1215
1216 configure_r_port(tty, info, NULL);
1217 return 0;
1218}
1219
1220/*
1221 * This function fills in a rocket_ports struct with information
1222 * about what boards/ports are in the system. This info is passed
1223 * to user space. See setrocket.c where the info is used to create
1224 * the /dev/ttyRx ports.
1225 */
1226static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1227{
1228 struct rocket_ports *tmp;
1229 int board, ret = 0;
1230
1231 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1232 if (!tmp)
1233 return -ENOMEM;
1234
1235 tmp->tty_major = rocket_driver->major;
1236
1237 for (board = 0; board < 4; board++) {
1238 tmp->rocketModel[board].model = rocketModel[board].model;
1239 strcpy(tmp->rocketModel[board].modelString,
1240 rocketModel[board].modelString);
1241 tmp->rocketModel[board].numPorts = rocketModel[board].numPorts;
1242 tmp->rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1243 tmp->rocketModel[board].startingPortNumber =
1244 rocketModel[board].startingPortNumber;
1245 }
1246 if (copy_to_user(retports, tmp, sizeof(*retports)))
1247 ret = -EFAULT;
1248 kfree(tmp);
1249 return ret;
1250}
1251
1252static int reset_rm2(struct r_port *info, void __user *arg)
1253{
1254 int reset;
1255
1256 if (!capable(CAP_SYS_ADMIN))
1257 return -EPERM;
1258
1259 if (copy_from_user(&reset, arg, sizeof (int)))
1260 return -EFAULT;
1261 if (reset)
1262 reset = 1;
1263
1264 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1265 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1266 return -EINVAL;
1267
1268 if (info->ctlp->BusType == isISA)
1269 sModemReset(info->ctlp, info->chan, reset);
1270 else
1271 sPCIModemReset(info->ctlp, info->chan, reset);
1272
1273 return 0;
1274}
1275
1276static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1277{
1278 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1279 return -EFAULT;
1280 return 0;
1281}
1282
1283/* IOCTL call handler into the driver */
1284static int rp_ioctl(struct tty_struct *tty,
1285 unsigned int cmd, unsigned long arg)
1286{
1287 struct r_port *info = tty->driver_data;
1288 void __user *argp = (void __user *)arg;
1289 int ret = 0;
1290
1291 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1292 return -ENXIO;
1293
1294 switch (cmd) {
1295 case RCKP_GET_CONFIG:
1296 dev_warn_ratelimited(tty->dev,
1297 "RCKP_GET_CONFIG option is deprecated\n");
1298 ret = get_config(info, argp);
1299 break;
1300 case RCKP_SET_CONFIG:
1301 dev_warn_ratelimited(tty->dev,
1302 "RCKP_SET_CONFIG option is deprecated\n");
1303 ret = set_config(tty, info, argp);
1304 break;
1305 case RCKP_GET_PORTS:
1306 dev_warn_ratelimited(tty->dev,
1307 "RCKP_GET_PORTS option is deprecated\n");
1308 ret = get_ports(info, argp);
1309 break;
1310 case RCKP_RESET_RM2:
1311 dev_warn_ratelimited(tty->dev,
1312 "RCKP_RESET_RM2 option is deprecated\n");
1313 ret = reset_rm2(info, argp);
1314 break;
1315 case RCKP_GET_VERSION:
1316 dev_warn_ratelimited(tty->dev,
1317 "RCKP_GET_VERSION option is deprecated\n");
1318 ret = get_version(info, argp);
1319 break;
1320 default:
1321 ret = -ENOIOCTLCMD;
1322 }
1323 return ret;
1324}
1325
1326static void rp_send_xchar(struct tty_struct *tty, char ch)
1327{
1328 struct r_port *info = tty->driver_data;
1329 CHANNEL_t *cp;
1330
1331 if (rocket_paranoia_check(info, "rp_send_xchar"))
1332 return;
1333
1334 cp = &info->channel;
1335 if (sGetTxCnt(cp))
1336 sWriteTxPrioByte(cp, ch);
1337 else
1338 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1339}
1340
1341static void rp_throttle(struct tty_struct *tty)
1342{
1343 struct r_port *info = tty->driver_data;
1344
1345#ifdef ROCKET_DEBUG_THROTTLE
1346 printk(KERN_INFO "throttle %s ....\n", tty->name);
1347#endif
1348
1349 if (rocket_paranoia_check(info, "rp_throttle"))
1350 return;
1351
1352 if (I_IXOFF(tty))
1353 rp_send_xchar(tty, STOP_CHAR(tty));
1354
1355 sClrRTS(&info->channel);
1356}
1357
1358static void rp_unthrottle(struct tty_struct *tty)
1359{
1360 struct r_port *info = tty->driver_data;
1361#ifdef ROCKET_DEBUG_THROTTLE
1362 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1363#endif
1364
1365 if (rocket_paranoia_check(info, "rp_unthrottle"))
1366 return;
1367
1368 if (I_IXOFF(tty))
1369 rp_send_xchar(tty, START_CHAR(tty));
1370
1371 sSetRTS(&info->channel);
1372}
1373
1374/*
1375 * ------------------------------------------------------------
1376 * rp_stop() and rp_start()
1377 *
1378 * This routines are called before setting or resetting tty->stopped.
1379 * They enable or disable transmitter interrupts, as necessary.
1380 * ------------------------------------------------------------
1381 */
1382static void rp_stop(struct tty_struct *tty)
1383{
1384 struct r_port *info = tty->driver_data;
1385
1386#ifdef ROCKET_DEBUG_FLOW
1387 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1388 info->xmit_cnt, info->xmit_fifo_room);
1389#endif
1390
1391 if (rocket_paranoia_check(info, "rp_stop"))
1392 return;
1393
1394 if (sGetTxCnt(&info->channel))
1395 sDisTransmit(&info->channel);
1396}
1397
1398static void rp_start(struct tty_struct *tty)
1399{
1400 struct r_port *info = tty->driver_data;
1401
1402#ifdef ROCKET_DEBUG_FLOW
1403 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1404 info->xmit_cnt, info->xmit_fifo_room);
1405#endif
1406
1407 if (rocket_paranoia_check(info, "rp_stop"))
1408 return;
1409
1410 sEnTransmit(&info->channel);
1411 set_bit((info->aiop * 8) + info->chan,
1412 (void *) &xmit_flags[info->board]);
1413}
1414
1415/*
1416 * rp_wait_until_sent() --- wait until the transmitter is empty
1417 */
1418static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1419{
1420 struct r_port *info = tty->driver_data;
1421 CHANNEL_t *cp;
1422 unsigned long orig_jiffies;
1423 int check_time, exit_time;
1424 int txcnt;
1425
1426 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1427 return;
1428
1429 cp = &info->channel;
1430
1431 orig_jiffies = jiffies;
1432#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1433 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1434 jiffies);
1435 printk(KERN_INFO "cps=%d...\n", info->cps);
1436#endif
1437 while (1) {
1438 txcnt = sGetTxCnt(cp);
1439 if (!txcnt) {
1440 if (sGetChanStatusLo(cp) & TXSHRMT)
1441 break;
1442 check_time = (HZ / info->cps) / 5;
1443 } else {
1444 check_time = HZ * txcnt / info->cps;
1445 }
1446 if (timeout) {
1447 exit_time = orig_jiffies + timeout - jiffies;
1448 if (exit_time <= 0)
1449 break;
1450 if (exit_time < check_time)
1451 check_time = exit_time;
1452 }
1453 if (check_time == 0)
1454 check_time = 1;
1455#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1456 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1457 jiffies, check_time);
1458#endif
1459 msleep_interruptible(jiffies_to_msecs(check_time));
1460 if (signal_pending(current))
1461 break;
1462 }
1463 __set_current_state(TASK_RUNNING);
1464#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1465 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1466#endif
1467}
1468
1469/*
1470 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1471 */
1472static void rp_hangup(struct tty_struct *tty)
1473{
1474 CHANNEL_t *cp;
1475 struct r_port *info = tty->driver_data;
1476 unsigned long flags;
1477
1478 if (rocket_paranoia_check(info, "rp_hangup"))
1479 return;
1480
1481#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1482 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1483#endif
1484 rp_flush_buffer(tty);
1485 spin_lock_irqsave(&info->port.lock, flags);
1486 if (info->port.count)
1487 atomic_dec(&rp_num_ports_open);
1488 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1489 spin_unlock_irqrestore(&info->port.lock, flags);
1490
1491 tty_port_hangup(&info->port);
1492
1493 cp = &info->channel;
1494 sDisRxFIFO(cp);
1495 sDisTransmit(cp);
1496 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1497 sDisCTSFlowCtl(cp);
1498 sDisTxSoftFlowCtl(cp);
1499 sClrTxXOFF(cp);
1500 tty_port_set_initialized(&info->port, 0);
1501
1502 wake_up_interruptible(&info->port.open_wait);
1503}
1504
1505/*
1506 * Exception handler - write char routine. The RocketPort driver uses a
1507 * double-buffering strategy, with the twist that if the in-memory CPU
1508 * buffer is empty, and there's space in the transmit FIFO, the
1509 * writing routines will write directly to transmit FIFO.
1510 * Write buffer and counters protected by spinlocks
1511 */
1512static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1513{
1514 struct r_port *info = tty->driver_data;
1515 CHANNEL_t *cp;
1516 unsigned long flags;
1517
1518 if (rocket_paranoia_check(info, "rp_put_char"))
1519 return 0;
1520
1521 /*
1522 * Grab the port write mutex, locking out other processes that try to
1523 * write to this port
1524 */
1525 mutex_lock(&info->write_mtx);
1526
1527#ifdef ROCKET_DEBUG_WRITE
1528 printk(KERN_INFO "rp_put_char %c...\n", ch);
1529#endif
1530
1531 spin_lock_irqsave(&info->slock, flags);
1532 cp = &info->channel;
1533
1534 if (!tty->stopped && info->xmit_fifo_room == 0)
1535 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1536
1537 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1538 info->xmit_buf[info->xmit_head++] = ch;
1539 info->xmit_head &= XMIT_BUF_SIZE - 1;
1540 info->xmit_cnt++;
1541 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1542 } else {
1543 sOutB(sGetTxRxDataIO(cp), ch);
1544 info->xmit_fifo_room--;
1545 }
1546 spin_unlock_irqrestore(&info->slock, flags);
1547 mutex_unlock(&info->write_mtx);
1548 return 1;
1549}
1550
1551/*
1552 * Exception handler - write routine, called when user app writes to the device.
1553 * A per port write mutex is used to protect from another process writing to
1554 * this port at the same time. This other process could be running on the other CPU
1555 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1556 * Spinlocks protect the info xmit members.
1557 */
1558static int rp_write(struct tty_struct *tty,
1559 const unsigned char *buf, int count)
1560{
1561 struct r_port *info = tty->driver_data;
1562 CHANNEL_t *cp;
1563 const unsigned char *b;
1564 int c, retval = 0;
1565 unsigned long flags;
1566
1567 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1568 return 0;
1569
1570 if (mutex_lock_interruptible(&info->write_mtx))
1571 return -ERESTARTSYS;
1572
1573#ifdef ROCKET_DEBUG_WRITE
1574 printk(KERN_INFO "rp_write %d chars...\n", count);
1575#endif
1576 cp = &info->channel;
1577
1578 if (!tty->stopped && info->xmit_fifo_room < count)
1579 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1580
1581 /*
1582 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1583 * into FIFO. Use the write queue for temp storage.
1584 */
1585 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1586 c = min(count, info->xmit_fifo_room);
1587 b = buf;
1588
1589 /* Push data into FIFO, 2 bytes at a time */
1590 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1591
1592 /* If there is a byte remaining, write it */
1593 if (c & 1)
1594 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1595
1596 retval += c;
1597 buf += c;
1598 count -= c;
1599
1600 spin_lock_irqsave(&info->slock, flags);
1601 info->xmit_fifo_room -= c;
1602 spin_unlock_irqrestore(&info->slock, flags);
1603 }
1604
1605 /* If count is zero, we wrote it all and are done */
1606 if (!count)
1607 goto end;
1608
1609 /* Write remaining data into the port's xmit_buf */
1610 while (1) {
1611 /* Hung up ? */
1612 if (!tty_port_active(&info->port))
1613 goto end;
1614 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1615 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1616 if (c <= 0)
1617 break;
1618
1619 b = buf;
1620 memcpy(info->xmit_buf + info->xmit_head, b, c);
1621
1622 spin_lock_irqsave(&info->slock, flags);
1623 info->xmit_head =
1624 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1625 info->xmit_cnt += c;
1626 spin_unlock_irqrestore(&info->slock, flags);
1627
1628 buf += c;
1629 count -= c;
1630 retval += c;
1631 }
1632
1633 if ((retval > 0) && !tty->stopped)
1634 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1635
1636end:
1637 if (info->xmit_cnt < WAKEUP_CHARS) {
1638 tty_wakeup(tty);
1639#ifdef ROCKETPORT_HAVE_POLL_WAIT
1640 wake_up_interruptible(&tty->poll_wait);
1641#endif
1642 }
1643 mutex_unlock(&info->write_mtx);
1644 return retval;
1645}
1646
1647/*
1648 * Return the number of characters that can be sent. We estimate
1649 * only using the in-memory transmit buffer only, and ignore the
1650 * potential space in the transmit FIFO.
1651 */
1652static int rp_write_room(struct tty_struct *tty)
1653{
1654 struct r_port *info = tty->driver_data;
1655 int ret;
1656
1657 if (rocket_paranoia_check(info, "rp_write_room"))
1658 return 0;
1659
1660 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1661 if (ret < 0)
1662 ret = 0;
1663#ifdef ROCKET_DEBUG_WRITE
1664 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1665#endif
1666 return ret;
1667}
1668
1669/*
1670 * Return the number of characters in the buffer. Again, this only
1671 * counts those characters in the in-memory transmit buffer.
1672 */
1673static int rp_chars_in_buffer(struct tty_struct *tty)
1674{
1675 struct r_port *info = tty->driver_data;
1676
1677 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1678 return 0;
1679
1680#ifdef ROCKET_DEBUG_WRITE
1681 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1682#endif
1683 return info->xmit_cnt;
1684}
1685
1686/*
1687 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1688 * r_port struct for the port. Note that spinlock are used to protect info members,
1689 * do not call this function if the spinlock is already held.
1690 */
1691static void rp_flush_buffer(struct tty_struct *tty)
1692{
1693 struct r_port *info = tty->driver_data;
1694 CHANNEL_t *cp;
1695 unsigned long flags;
1696
1697 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1698 return;
1699
1700 spin_lock_irqsave(&info->slock, flags);
1701 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1702 spin_unlock_irqrestore(&info->slock, flags);
1703
1704#ifdef ROCKETPORT_HAVE_POLL_WAIT
1705 wake_up_interruptible(&tty->poll_wait);
1706#endif
1707 tty_wakeup(tty);
1708
1709 cp = &info->channel;
1710 sFlushTxFIFO(cp);
1711}
1712
1713#ifdef CONFIG_PCI
1714
1715static const struct pci_device_id rocket_pci_ids[] = {
1716 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1717 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1718 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1719 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1720 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1721 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1722 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1723 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1724 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1725 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1726 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1727 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1728 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1729 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1730 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1731 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1732 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1733 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1736 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1738 { }
1739};
1740MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1741
1742/* Resets the speaker controller on RocketModem II and III devices */
1743static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1744{
1745 ByteIO_t addr;
1746
1747 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1748 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1749 addr = CtlP->AiopIO[0] + 0x4F;
1750 sOutB(addr, 0);
1751 }
1752
1753 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1754 if ((model == MODEL_UPCI_RM3_8PORT)
1755 || (model == MODEL_UPCI_RM3_4PORT)) {
1756 addr = CtlP->AiopIO[0] + 0x88;
1757 sOutB(addr, 0);
1758 }
1759}
1760
1761/***************************************************************************
1762Function: sPCIInitController
1763Purpose: Initialization of controller global registers and controller
1764 structure.
1765Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1766 IRQNum,Frequency,PeriodicOnly)
1767 CONTROLLER_T *CtlP; Ptr to controller structure
1768 int CtlNum; Controller number
1769 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1770 This list must be in the order the AIOPs will be found on the
1771 controller. Once an AIOP in the list is not found, it is
1772 assumed that there are no more AIOPs on the controller.
1773 int AiopIOListSize; Number of addresses in AiopIOList
1774 int IRQNum; Interrupt Request number. Can be any of the following:
1775 0: Disable global interrupts
1776 3: IRQ 3
1777 4: IRQ 4
1778 5: IRQ 5
1779 9: IRQ 9
1780 10: IRQ 10
1781 11: IRQ 11
1782 12: IRQ 12
1783 15: IRQ 15
1784 Byte_t Frequency: A flag identifying the frequency
1785 of the periodic interrupt, can be any one of the following:
1786 FREQ_DIS - periodic interrupt disabled
1787 FREQ_137HZ - 137 Hertz
1788 FREQ_69HZ - 69 Hertz
1789 FREQ_34HZ - 34 Hertz
1790 FREQ_17HZ - 17 Hertz
1791 FREQ_9HZ - 9 Hertz
1792 FREQ_4HZ - 4 Hertz
1793 If IRQNum is set to 0 the Frequency parameter is
1794 overidden, it is forced to a value of FREQ_DIS.
1795 int PeriodicOnly: 1 if all interrupts except the periodic
1796 interrupt are to be blocked.
1797 0 is both the periodic interrupt and
1798 other channel interrupts are allowed.
1799 If IRQNum is set to 0 the PeriodicOnly parameter is
1800 overidden, it is forced to a value of 0.
1801Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1802 initialization failed.
1803
1804Comments:
1805 If periodic interrupts are to be disabled but AIOP interrupts
1806 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1807
1808 If interrupts are to be completely disabled set IRQNum to 0.
1809
1810 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1811 invalid combination.
1812
1813 This function performs initialization of global interrupt modes,
1814 but it does not actually enable global interrupts. To enable
1815 and disable global interrupts use functions sEnGlobalInt() and
1816 sDisGlobalInt(). Enabling of global interrupts is normally not
1817 done until all other initializations are complete.
1818
1819 Even if interrupts are globally enabled, they must also be
1820 individually enabled for each channel that is to generate
1821 interrupts.
1822
1823Warnings: No range checking on any of the parameters is done.
1824
1825 No context switches are allowed while executing this function.
1826
1827 After this function all AIOPs on the controller are disabled,
1828 they can be enabled with sEnAiop().
1829*/
1830static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1831 ByteIO_t * AiopIOList, int AiopIOListSize,
1832 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1833 int PeriodicOnly, int altChanRingIndicator,
1834 int UPCIRingInd)
1835{
1836 int i;
1837 ByteIO_t io;
1838
1839 CtlP->AltChanRingIndicator = altChanRingIndicator;
1840 CtlP->UPCIRingInd = UPCIRingInd;
1841 CtlP->CtlNum = CtlNum;
1842 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1843 CtlP->BusType = isPCI; /* controller release 1 */
1844
1845 if (ConfigIO) {
1846 CtlP->isUPCI = 1;
1847 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1848 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1849 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1850 } else {
1851 CtlP->isUPCI = 0;
1852 CtlP->PCIIO =
1853 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1854 CtlP->AiopIntrBits = aiop_intr_bits;
1855 }
1856
1857 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1858 /* Init AIOPs */
1859 CtlP->NumAiop = 0;
1860 for (i = 0; i < AiopIOListSize; i++) {
1861 io = AiopIOList[i];
1862 CtlP->AiopIO[i] = (WordIO_t) io;
1863 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1864
1865 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1866 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1867 break; /* done looking for AIOPs */
1868
1869 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1870 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1871 sOutB(io + _INDX_DATA, sClockPrescale);
1872 CtlP->NumAiop++; /* bump count of AIOPs */
1873 }
1874
1875 if (CtlP->NumAiop == 0)
1876 return (-1);
1877 else
1878 return (CtlP->NumAiop);
1879}
1880
1881/*
1882 * Called when a PCI card is found. Retrieves and stores model information,
1883 * init's aiopic and serial port hardware.
1884 * Inputs: i is the board number (0-n)
1885 */
1886static __init int register_PCI(int i, struct pci_dev *dev)
1887{
1888 int num_aiops, aiop, max_num_aiops, chan;
1889 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1890 CONTROLLER_t *ctlp;
1891
1892 int fast_clock = 0;
1893 int altChanRingIndicator = 0;
1894 int ports_per_aiop = 8;
1895 WordIO_t ConfigIO = 0;
1896 ByteIO_t UPCIRingInd = 0;
1897
1898 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1899 pci_enable_device(dev) || i >= NUM_BOARDS)
1900 return 0;
1901
1902 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1903
1904 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1905 rocketModel[i].loadrm2 = 0;
1906 rocketModel[i].startingPortNumber = nextLineNumber;
1907
1908 /* Depending on the model, set up some config variables */
1909 switch (dev->device) {
1910 case PCI_DEVICE_ID_RP4QUAD:
1911 max_num_aiops = 1;
1912 ports_per_aiop = 4;
1913 rocketModel[i].model = MODEL_RP4QUAD;
1914 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1915 rocketModel[i].numPorts = 4;
1916 break;
1917 case PCI_DEVICE_ID_RP8OCTA:
1918 max_num_aiops = 1;
1919 rocketModel[i].model = MODEL_RP8OCTA;
1920 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1921 rocketModel[i].numPorts = 8;
1922 break;
1923 case PCI_DEVICE_ID_URP8OCTA:
1924 max_num_aiops = 1;
1925 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1926 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1927 rocketModel[i].numPorts = 8;
1928 break;
1929 case PCI_DEVICE_ID_RP8INTF:
1930 max_num_aiops = 1;
1931 rocketModel[i].model = MODEL_RP8INTF;
1932 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1933 rocketModel[i].numPorts = 8;
1934 break;
1935 case PCI_DEVICE_ID_URP8INTF:
1936 max_num_aiops = 1;
1937 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1938 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1939 rocketModel[i].numPorts = 8;
1940 break;
1941 case PCI_DEVICE_ID_RP8J:
1942 max_num_aiops = 1;
1943 rocketModel[i].model = MODEL_RP8J;
1944 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1945 rocketModel[i].numPorts = 8;
1946 break;
1947 case PCI_DEVICE_ID_RP4J:
1948 max_num_aiops = 1;
1949 ports_per_aiop = 4;
1950 rocketModel[i].model = MODEL_RP4J;
1951 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1952 rocketModel[i].numPorts = 4;
1953 break;
1954 case PCI_DEVICE_ID_RP8SNI:
1955 max_num_aiops = 1;
1956 rocketModel[i].model = MODEL_RP8SNI;
1957 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1958 rocketModel[i].numPorts = 8;
1959 break;
1960 case PCI_DEVICE_ID_RP16SNI:
1961 max_num_aiops = 2;
1962 rocketModel[i].model = MODEL_RP16SNI;
1963 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1964 rocketModel[i].numPorts = 16;
1965 break;
1966 case PCI_DEVICE_ID_RP16INTF:
1967 max_num_aiops = 2;
1968 rocketModel[i].model = MODEL_RP16INTF;
1969 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1970 rocketModel[i].numPorts = 16;
1971 break;
1972 case PCI_DEVICE_ID_URP16INTF:
1973 max_num_aiops = 2;
1974 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1975 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1976 rocketModel[i].numPorts = 16;
1977 break;
1978 case PCI_DEVICE_ID_CRP16INTF:
1979 max_num_aiops = 2;
1980 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1981 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1982 rocketModel[i].numPorts = 16;
1983 break;
1984 case PCI_DEVICE_ID_RP32INTF:
1985 max_num_aiops = 4;
1986 rocketModel[i].model = MODEL_RP32INTF;
1987 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1988 rocketModel[i].numPorts = 32;
1989 break;
1990 case PCI_DEVICE_ID_URP32INTF:
1991 max_num_aiops = 4;
1992 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1993 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1994 rocketModel[i].numPorts = 32;
1995 break;
1996 case PCI_DEVICE_ID_RPP4:
1997 max_num_aiops = 1;
1998 ports_per_aiop = 4;
1999 altChanRingIndicator++;
2000 fast_clock++;
2001 rocketModel[i].model = MODEL_RPP4;
2002 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2003 rocketModel[i].numPorts = 4;
2004 break;
2005 case PCI_DEVICE_ID_RPP8:
2006 max_num_aiops = 2;
2007 ports_per_aiop = 4;
2008 altChanRingIndicator++;
2009 fast_clock++;
2010 rocketModel[i].model = MODEL_RPP8;
2011 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2012 rocketModel[i].numPorts = 8;
2013 break;
2014 case PCI_DEVICE_ID_RP2_232:
2015 max_num_aiops = 1;
2016 ports_per_aiop = 2;
2017 altChanRingIndicator++;
2018 fast_clock++;
2019 rocketModel[i].model = MODEL_RP2_232;
2020 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2021 rocketModel[i].numPorts = 2;
2022 break;
2023 case PCI_DEVICE_ID_RP2_422:
2024 max_num_aiops = 1;
2025 ports_per_aiop = 2;
2026 altChanRingIndicator++;
2027 fast_clock++;
2028 rocketModel[i].model = MODEL_RP2_422;
2029 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2030 rocketModel[i].numPorts = 2;
2031 break;
2032 case PCI_DEVICE_ID_RP6M:
2033
2034 max_num_aiops = 1;
2035 ports_per_aiop = 6;
2036
2037 /* If revision is 1, the rocketmodem flash must be loaded.
2038 * If it is 2 it is a "socketed" version. */
2039 if (dev->revision == 1) {
2040 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2041 rocketModel[i].loadrm2 = 1;
2042 } else {
2043 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2044 }
2045
2046 rocketModel[i].model = MODEL_RP6M;
2047 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2048 rocketModel[i].numPorts = 6;
2049 break;
2050 case PCI_DEVICE_ID_RP4M:
2051 max_num_aiops = 1;
2052 ports_per_aiop = 4;
2053 if (dev->revision == 1) {
2054 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2055 rocketModel[i].loadrm2 = 1;
2056 } else {
2057 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2058 }
2059
2060 rocketModel[i].model = MODEL_RP4M;
2061 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2062 rocketModel[i].numPorts = 4;
2063 break;
2064 default:
2065 max_num_aiops = 0;
2066 break;
2067 }
2068
2069 /*
2070 * Check for UPCI boards.
2071 */
2072
2073 switch (dev->device) {
2074 case PCI_DEVICE_ID_URP32INTF:
2075 case PCI_DEVICE_ID_URP8INTF:
2076 case PCI_DEVICE_ID_URP16INTF:
2077 case PCI_DEVICE_ID_CRP16INTF:
2078 case PCI_DEVICE_ID_URP8OCTA:
2079 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2080 ConfigIO = pci_resource_start(dev, 1);
2081 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2082 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2083
2084 /*
2085 * Check for octa or quad cable.
2086 */
2087 if (!
2088 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2089 PCI_GPIO_CTRL_8PORT)) {
2090 ports_per_aiop = 4;
2091 rocketModel[i].numPorts = 4;
2092 }
2093 }
2094 break;
2095 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2096 max_num_aiops = 1;
2097 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2098 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2099 rocketModel[i].numPorts = 8;
2100 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2101 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2102 ConfigIO = pci_resource_start(dev, 1);
2103 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2104 break;
2105 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2106 max_num_aiops = 1;
2107 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2108 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2109 rocketModel[i].numPorts = 4;
2110 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2111 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2112 ConfigIO = pci_resource_start(dev, 1);
2113 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2114 break;
2115 default:
2116 break;
2117 }
2118
2119 if (fast_clock) {
2120 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2121 rp_baud_base[i] = 921600;
2122 } else {
2123 /*
2124 * If support_low_speed is set, use the slow clock
2125 * prescale, which supports 50 bps
2126 */
2127 if (support_low_speed) {
2128 /* mod 9 (divide by 10) prescale */
2129 sClockPrescale = 0x19;
2130 rp_baud_base[i] = 230400;
2131 } else {
2132 /* mod 4 (divide by 5) prescale */
2133 sClockPrescale = 0x14;
2134 rp_baud_base[i] = 460800;
2135 }
2136 }
2137
2138 for (aiop = 0; aiop < max_num_aiops; aiop++)
2139 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2140 ctlp = sCtlNumToCtlPtr(i);
2141 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2142 for (aiop = 0; aiop < max_num_aiops; aiop++)
2143 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2144
2145 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2146 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2147 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2148 rocketModel[i].startingPortNumber,
2149 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2150
2151 if (num_aiops <= 0) {
2152 rcktpt_io_addr[i] = 0;
2153 return (0);
2154 }
2155 is_PCI[i] = 1;
2156
2157 /* Reset the AIOPIC, init the serial ports */
2158 for (aiop = 0; aiop < num_aiops; aiop++) {
2159 sResetAiopByNum(ctlp, aiop);
2160 for (chan = 0; chan < ports_per_aiop; chan++)
2161 init_r_port(i, aiop, chan, dev);
2162 }
2163
2164 /* Rocket modems must be reset */
2165 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2166 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2167 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2168 for (chan = 0; chan < ports_per_aiop; chan++)
2169 sPCIModemReset(ctlp, chan, 1);
2170 msleep(500);
2171 for (chan = 0; chan < ports_per_aiop; chan++)
2172 sPCIModemReset(ctlp, chan, 0);
2173 msleep(500);
2174 rmSpeakerReset(ctlp, rocketModel[i].model);
2175 }
2176 return (1);
2177}
2178
2179/*
2180 * Probes for PCI cards, inits them if found
2181 * Input: board_found = number of ISA boards already found, or the
2182 * starting board number
2183 * Returns: Number of PCI boards found
2184 */
2185static int __init init_PCI(int boards_found)
2186{
2187 struct pci_dev *dev = NULL;
2188 int count = 0;
2189
2190 /* Work through the PCI device list, pulling out ours */
2191 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2192 if (register_PCI(count + boards_found, dev))
2193 count++;
2194 }
2195 return (count);
2196}
2197
2198#endif /* CONFIG_PCI */
2199
2200/*
2201 * Probes for ISA cards
2202 * Input: i = the board number to look for
2203 * Returns: 1 if board found, 0 else
2204 */
2205static int __init init_ISA(int i)
2206{
2207 int num_aiops, num_chan = 0, total_num_chan = 0;
2208 int aiop, chan;
2209 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2210 CONTROLLER_t *ctlp;
2211 char *type_string;
2212
2213 /* If io_addr is zero, no board configured */
2214 if (rcktpt_io_addr[i] == 0)
2215 return (0);
2216
2217 /* Reserve the IO region */
2218 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2219 printk(KERN_ERR "Unable to reserve IO region for configured "
2220 "ISA RocketPort at address 0x%lx, board not "
2221 "installed...\n", rcktpt_io_addr[i]);
2222 rcktpt_io_addr[i] = 0;
2223 return (0);
2224 }
2225
2226 ctlp = sCtlNumToCtlPtr(i);
2227
2228 ctlp->boardType = rcktpt_type[i];
2229
2230 switch (rcktpt_type[i]) {
2231 case ROCKET_TYPE_PC104:
2232 type_string = "(PC104)";
2233 break;
2234 case ROCKET_TYPE_MODEM:
2235 type_string = "(RocketModem)";
2236 break;
2237 case ROCKET_TYPE_MODEMII:
2238 type_string = "(RocketModem II)";
2239 break;
2240 default:
2241 type_string = "";
2242 break;
2243 }
2244
2245 /*
2246 * If support_low_speed is set, use the slow clock prescale,
2247 * which supports 50 bps
2248 */
2249 if (support_low_speed) {
2250 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2251 rp_baud_base[i] = 230400;
2252 } else {
2253 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2254 rp_baud_base[i] = 460800;
2255 }
2256
2257 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2258 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2259
2260 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2261
2262 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2263 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2264 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2265 }
2266
2267 /* If something went wrong initing the AIOP's release the ISA IO memory */
2268 if (num_aiops <= 0) {
2269 release_region(rcktpt_io_addr[i], 64);
2270 rcktpt_io_addr[i] = 0;
2271 return (0);
2272 }
2273
2274 rocketModel[i].startingPortNumber = nextLineNumber;
2275
2276 for (aiop = 0; aiop < num_aiops; aiop++) {
2277 sResetAiopByNum(ctlp, aiop);
2278 sEnAiop(ctlp, aiop);
2279 num_chan = sGetAiopNumChan(ctlp, aiop);
2280 total_num_chan += num_chan;
2281 for (chan = 0; chan < num_chan; chan++)
2282 init_r_port(i, aiop, chan, NULL);
2283 }
2284 is_PCI[i] = 0;
2285 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2286 num_chan = sGetAiopNumChan(ctlp, 0);
2287 total_num_chan = num_chan;
2288 for (chan = 0; chan < num_chan; chan++)
2289 sModemReset(ctlp, chan, 1);
2290 msleep(500);
2291 for (chan = 0; chan < num_chan; chan++)
2292 sModemReset(ctlp, chan, 0);
2293 msleep(500);
2294 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2295 } else {
2296 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2297 }
2298 rocketModel[i].numPorts = total_num_chan;
2299 rocketModel[i].model = MODEL_ISA;
2300
2301 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2302 i, rcktpt_io_addr[i], num_aiops, type_string);
2303
2304 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2305 rocketModel[i].modelString,
2306 rocketModel[i].startingPortNumber,
2307 rocketModel[i].startingPortNumber +
2308 rocketModel[i].numPorts - 1);
2309
2310 return (1);
2311}
2312
2313static const struct tty_operations rocket_ops = {
2314 .open = rp_open,
2315 .close = rp_close,
2316 .write = rp_write,
2317 .put_char = rp_put_char,
2318 .write_room = rp_write_room,
2319 .chars_in_buffer = rp_chars_in_buffer,
2320 .flush_buffer = rp_flush_buffer,
2321 .ioctl = rp_ioctl,
2322 .throttle = rp_throttle,
2323 .unthrottle = rp_unthrottle,
2324 .set_termios = rp_set_termios,
2325 .stop = rp_stop,
2326 .start = rp_start,
2327 .hangup = rp_hangup,
2328 .break_ctl = rp_break,
2329 .send_xchar = rp_send_xchar,
2330 .wait_until_sent = rp_wait_until_sent,
2331 .tiocmget = rp_tiocmget,
2332 .tiocmset = rp_tiocmset,
2333};
2334
2335static const struct tty_port_operations rocket_port_ops = {
2336 .carrier_raised = carrier_raised,
2337 .dtr_rts = dtr_rts,
2338};
2339
2340/*
2341 * The module "startup" routine; it's run when the module is loaded.
2342 */
2343static int __init rp_init(void)
2344{
2345 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2346
2347 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2348 ROCKET_VERSION, ROCKET_DATE);
2349
2350 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2351 if (!rocket_driver)
2352 goto err;
2353
2354 /*
2355 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2356 * zero, use the default controller IO address of board1 + 0x40.
2357 */
2358 if (board1) {
2359 if (controller == 0)
2360 controller = board1 + 0x40;
2361 } else {
2362 controller = 0; /* Used as a flag, meaning no ISA boards */
2363 }
2364
2365 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2366 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2367 printk(KERN_ERR "Unable to reserve IO region for first "
2368 "configured ISA RocketPort controller 0x%lx. "
2369 "Driver exiting\n", controller);
2370 ret = -EBUSY;
2371 goto err_tty;
2372 }
2373
2374 /* Store ISA variable retrieved from command line or .conf file. */
2375 rcktpt_io_addr[0] = board1;
2376 rcktpt_io_addr[1] = board2;
2377 rcktpt_io_addr[2] = board3;
2378 rcktpt_io_addr[3] = board4;
2379
2380 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2381 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2382 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2383 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2384 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2385 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2386 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2387 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2388
2389 /*
2390 * Set up the tty driver structure and then register this
2391 * driver with the tty layer.
2392 */
2393
2394 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2395 rocket_driver->name = "ttyR";
2396 rocket_driver->driver_name = "Comtrol RocketPort";
2397 rocket_driver->major = TTY_ROCKET_MAJOR;
2398 rocket_driver->minor_start = 0;
2399 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2400 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2401 rocket_driver->init_termios = tty_std_termios;
2402 rocket_driver->init_termios.c_cflag =
2403 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2404 rocket_driver->init_termios.c_ispeed = 9600;
2405 rocket_driver->init_termios.c_ospeed = 9600;
2406#ifdef ROCKET_SOFT_FLOW
2407 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2408#endif
2409 tty_set_operations(rocket_driver, &rocket_ops);
2410
2411 ret = tty_register_driver(rocket_driver);
2412 if (ret < 0) {
2413 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2414 goto err_controller;
2415 }
2416
2417#ifdef ROCKET_DEBUG_OPEN
2418 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2419#endif
2420
2421 /*
2422 * OK, let's probe each of the controllers looking for boards. Any boards found
2423 * will be initialized here.
2424 */
2425 isa_boards_found = 0;
2426 pci_boards_found = 0;
2427
2428 for (i = 0; i < NUM_BOARDS; i++) {
2429 if (init_ISA(i))
2430 isa_boards_found++;
2431 }
2432
2433#ifdef CONFIG_PCI
2434 if (isa_boards_found < NUM_BOARDS)
2435 pci_boards_found = init_PCI(isa_boards_found);
2436#endif
2437
2438 max_board = pci_boards_found + isa_boards_found;
2439
2440 if (max_board == 0) {
2441 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2442 ret = -ENXIO;
2443 goto err_ttyu;
2444 }
2445
2446 return 0;
2447err_ttyu:
2448 tty_unregister_driver(rocket_driver);
2449err_controller:
2450 if (controller)
2451 release_region(controller, 4);
2452err_tty:
2453 put_tty_driver(rocket_driver);
2454err:
2455 return ret;
2456}
2457
2458
2459static void rp_cleanup_module(void)
2460{
2461 int retval;
2462 int i;
2463
2464 del_timer_sync(&rocket_timer);
2465
2466 retval = tty_unregister_driver(rocket_driver);
2467 if (retval)
2468 printk(KERN_ERR "Error %d while trying to unregister "
2469 "rocketport driver\n", -retval);
2470
2471 for (i = 0; i < MAX_RP_PORTS; i++)
2472 if (rp_table[i]) {
2473 tty_unregister_device(rocket_driver, i);
2474 tty_port_destroy(&rp_table[i]->port);
2475 kfree(rp_table[i]);
2476 }
2477
2478 put_tty_driver(rocket_driver);
2479
2480 for (i = 0; i < NUM_BOARDS; i++) {
2481 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2482 continue;
2483 release_region(rcktpt_io_addr[i], 64);
2484 }
2485 if (controller)
2486 release_region(controller, 4);
2487}
2488
2489/***************************************************************************
2490Function: sInitController
2491Purpose: Initialization of controller global registers and controller
2492 structure.
2493Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2494 IRQNum,Frequency,PeriodicOnly)
2495 CONTROLLER_T *CtlP; Ptr to controller structure
2496 int CtlNum; Controller number
2497 ByteIO_t MudbacIO; Mudbac base I/O address.
2498 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2499 This list must be in the order the AIOPs will be found on the
2500 controller. Once an AIOP in the list is not found, it is
2501 assumed that there are no more AIOPs on the controller.
2502 int AiopIOListSize; Number of addresses in AiopIOList
2503 int IRQNum; Interrupt Request number. Can be any of the following:
2504 0: Disable global interrupts
2505 3: IRQ 3
2506 4: IRQ 4
2507 5: IRQ 5
2508 9: IRQ 9
2509 10: IRQ 10
2510 11: IRQ 11
2511 12: IRQ 12
2512 15: IRQ 15
2513 Byte_t Frequency: A flag identifying the frequency
2514 of the periodic interrupt, can be any one of the following:
2515 FREQ_DIS - periodic interrupt disabled
2516 FREQ_137HZ - 137 Hertz
2517 FREQ_69HZ - 69 Hertz
2518 FREQ_34HZ - 34 Hertz
2519 FREQ_17HZ - 17 Hertz
2520 FREQ_9HZ - 9 Hertz
2521 FREQ_4HZ - 4 Hertz
2522 If IRQNum is set to 0 the Frequency parameter is
2523 overidden, it is forced to a value of FREQ_DIS.
2524 int PeriodicOnly: 1 if all interrupts except the periodic
2525 interrupt are to be blocked.
2526 0 is both the periodic interrupt and
2527 other channel interrupts are allowed.
2528 If IRQNum is set to 0 the PeriodicOnly parameter is
2529 overidden, it is forced to a value of 0.
2530Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2531 initialization failed.
2532
2533Comments:
2534 If periodic interrupts are to be disabled but AIOP interrupts
2535 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2536
2537 If interrupts are to be completely disabled set IRQNum to 0.
2538
2539 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2540 invalid combination.
2541
2542 This function performs initialization of global interrupt modes,
2543 but it does not actually enable global interrupts. To enable
2544 and disable global interrupts use functions sEnGlobalInt() and
2545 sDisGlobalInt(). Enabling of global interrupts is normally not
2546 done until all other initializations are complete.
2547
2548 Even if interrupts are globally enabled, they must also be
2549 individually enabled for each channel that is to generate
2550 interrupts.
2551
2552Warnings: No range checking on any of the parameters is done.
2553
2554 No context switches are allowed while executing this function.
2555
2556 After this function all AIOPs on the controller are disabled,
2557 they can be enabled with sEnAiop().
2558*/
2559static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2560 ByteIO_t * AiopIOList, int AiopIOListSize,
2561 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2562{
2563 int i;
2564 ByteIO_t io;
2565 int done;
2566
2567 CtlP->AiopIntrBits = aiop_intr_bits;
2568 CtlP->AltChanRingIndicator = 0;
2569 CtlP->CtlNum = CtlNum;
2570 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2571 CtlP->BusType = isISA;
2572 CtlP->MBaseIO = MudbacIO;
2573 CtlP->MReg1IO = MudbacIO + 1;
2574 CtlP->MReg2IO = MudbacIO + 2;
2575 CtlP->MReg3IO = MudbacIO + 3;
2576#if 1
2577 CtlP->MReg2 = 0; /* interrupt disable */
2578 CtlP->MReg3 = 0; /* no periodic interrupts */
2579#else
2580 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2581 CtlP->MReg2 = 0; /* interrupt disable */
2582 CtlP->MReg3 = 0; /* no periodic interrupts */
2583 } else {
2584 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2585 CtlP->MReg3 = Frequency; /* set frequency */
2586 if (PeriodicOnly) { /* periodic interrupt only */
2587 CtlP->MReg3 |= PERIODIC_ONLY;
2588 }
2589 }
2590#endif
2591 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2592 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2593 sControllerEOI(CtlP); /* clear EOI if warm init */
2594 /* Init AIOPs */
2595 CtlP->NumAiop = 0;
2596 for (i = done = 0; i < AiopIOListSize; i++) {
2597 io = AiopIOList[i];
2598 CtlP->AiopIO[i] = (WordIO_t) io;
2599 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2600 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2601 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2602 if (done)
2603 continue;
2604 sEnAiop(CtlP, i); /* enable the AIOP */
2605 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2606 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2607 done = 1; /* done looking for AIOPs */
2608 else {
2609 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2610 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2611 sOutB(io + _INDX_DATA, sClockPrescale);
2612 CtlP->NumAiop++; /* bump count of AIOPs */
2613 }
2614 sDisAiop(CtlP, i); /* disable AIOP */
2615 }
2616
2617 if (CtlP->NumAiop == 0)
2618 return (-1);
2619 else
2620 return (CtlP->NumAiop);
2621}
2622
2623/***************************************************************************
2624Function: sReadAiopID
2625Purpose: Read the AIOP idenfication number directly from an AIOP.
2626Call: sReadAiopID(io)
2627 ByteIO_t io: AIOP base I/O address
2628Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2629 is replace by an identifying number.
2630 Flag AIOPID_NULL if no valid AIOP is found
2631Warnings: No context switches are allowed while executing this function.
2632
2633*/
2634static int sReadAiopID(ByteIO_t io)
2635{
2636 Byte_t AiopID; /* ID byte from AIOP */
2637
2638 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2639 sOutB(io + _CMD_REG, 0x0);
2640 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2641 if (AiopID == 0x06)
2642 return (1);
2643 else /* AIOP does not exist */
2644 return (-1);
2645}
2646
2647/***************************************************************************
2648Function: sReadAiopNumChan
2649Purpose: Read the number of channels available in an AIOP directly from
2650 an AIOP.
2651Call: sReadAiopNumChan(io)
2652 WordIO_t io: AIOP base I/O address
2653Return: int: The number of channels available
2654Comments: The number of channels is determined by write/reads from identical
2655 offsets within the SRAM address spaces for channels 0 and 4.
2656 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2657 AIOP, otherwise it is an 8 channel.
2658Warnings: No context switches are allowed while executing this function.
2659*/
2660static int sReadAiopNumChan(WordIO_t io)
2661{
2662 Word_t x;
2663 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2664
2665 /* write to chan 0 SRAM */
2666 out32((DWordIO_t) io + _INDX_ADDR, R);
2667 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2668 x = sInW(io + _INDX_DATA);
2669 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2670 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2671 return (8);
2672 else
2673 return (4);
2674}
2675
2676/***************************************************************************
2677Function: sInitChan
2678Purpose: Initialization of a channel and channel structure
2679Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2680 CONTROLLER_T *CtlP; Ptr to controller structure
2681 CHANNEL_T *ChP; Ptr to channel structure
2682 int AiopNum; AIOP number within controller
2683 int ChanNum; Channel number within AIOP
2684Return: int: 1 if initialization succeeded, 0 if it fails because channel
2685 number exceeds number of channels available in AIOP.
2686Comments: This function must be called before a channel can be used.
2687Warnings: No range checking on any of the parameters is done.
2688
2689 No context switches are allowed while executing this function.
2690*/
2691static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2692 int ChanNum)
2693{
2694 int i;
2695 WordIO_t AiopIO;
2696 WordIO_t ChIOOff;
2697 Byte_t *ChR;
2698 Word_t ChOff;
2699 static Byte_t R[4];
2700 int brd9600;
2701
2702 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2703 return 0; /* exceeds num chans in AIOP */
2704
2705 /* Channel, AIOP, and controller identifiers */
2706 ChP->CtlP = CtlP;
2707 ChP->ChanID = CtlP->AiopID[AiopNum];
2708 ChP->AiopNum = AiopNum;
2709 ChP->ChanNum = ChanNum;
2710
2711 /* Global direct addresses */
2712 AiopIO = CtlP->AiopIO[AiopNum];
2713 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2714 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2715 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2716 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2717 ChP->IndexData = AiopIO + _INDX_DATA;
2718
2719 /* Channel direct addresses */
2720 ChIOOff = AiopIO + ChP->ChanNum * 2;
2721 ChP->TxRxData = ChIOOff + _TD0;
2722 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2723 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2724 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2725
2726 /* Initialize the channel from the RData array */
2727 for (i = 0; i < RDATASIZE; i += 4) {
2728 R[0] = RData[i];
2729 R[1] = RData[i + 1] + 0x10 * ChanNum;
2730 R[2] = RData[i + 2];
2731 R[3] = RData[i + 3];
2732 out32(ChP->IndexAddr, R);
2733 }
2734
2735 ChR = ChP->R;
2736 for (i = 0; i < RREGDATASIZE; i += 4) {
2737 ChR[i] = RRegData[i];
2738 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2739 ChR[i + 2] = RRegData[i + 2];
2740 ChR[i + 3] = RRegData[i + 3];
2741 }
2742
2743 /* Indexed registers */
2744 ChOff = (Word_t) ChanNum *0x1000;
2745
2746 if (sClockPrescale == 0x14)
2747 brd9600 = 47;
2748 else
2749 brd9600 = 23;
2750
2751 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2752 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2753 ChP->BaudDiv[2] = (Byte_t) brd9600;
2754 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2755 out32(ChP->IndexAddr, ChP->BaudDiv);
2756
2757 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2758 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2759 ChP->TxControl[2] = 0;
2760 ChP->TxControl[3] = 0;
2761 out32(ChP->IndexAddr, ChP->TxControl);
2762
2763 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2764 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2765 ChP->RxControl[2] = 0;
2766 ChP->RxControl[3] = 0;
2767 out32(ChP->IndexAddr, ChP->RxControl);
2768
2769 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2770 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2771 ChP->TxEnables[2] = 0;
2772 ChP->TxEnables[3] = 0;
2773 out32(ChP->IndexAddr, ChP->TxEnables);
2774
2775 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2776 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2777 ChP->TxCompare[2] = 0;
2778 ChP->TxCompare[3] = 0;
2779 out32(ChP->IndexAddr, ChP->TxCompare);
2780
2781 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2782 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2783 ChP->TxReplace1[2] = 0;
2784 ChP->TxReplace1[3] = 0;
2785 out32(ChP->IndexAddr, ChP->TxReplace1);
2786
2787 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2788 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2789 ChP->TxReplace2[2] = 0;
2790 ChP->TxReplace2[3] = 0;
2791 out32(ChP->IndexAddr, ChP->TxReplace2);
2792
2793 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2794 ChP->TxFIFO = ChOff + _TX_FIFO;
2795
2796 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2797 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2798 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2799 sOutW(ChP->IndexData, 0);
2800 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2801 ChP->RxFIFO = ChOff + _RX_FIFO;
2802
2803 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2804 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2805 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2806 sOutW(ChP->IndexData, 0);
2807 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2808 sOutW(ChP->IndexData, 0);
2809 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2811 sOutB(ChP->IndexData, 0);
2812 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2814 sOutB(ChP->IndexData, 0);
2815 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2816 sEnRxProcessor(ChP); /* start the Rx processor */
2817
2818 return 1;
2819}
2820
2821/***************************************************************************
2822Function: sStopRxProcessor
2823Purpose: Stop the receive processor from processing a channel.
2824Call: sStopRxProcessor(ChP)
2825 CHANNEL_T *ChP; Ptr to channel structure
2826
2827Comments: The receive processor can be started again with sStartRxProcessor().
2828 This function causes the receive processor to skip over the
2829 stopped channel. It does not stop it from processing other channels.
2830
2831Warnings: No context switches are allowed while executing this function.
2832
2833 Do not leave the receive processor stopped for more than one
2834 character time.
2835
2836 After calling this function a delay of 4 uS is required to ensure
2837 that the receive processor is no longer processing this channel.
2838*/
2839static void sStopRxProcessor(CHANNEL_T * ChP)
2840{
2841 Byte_t R[4];
2842
2843 R[0] = ChP->R[0];
2844 R[1] = ChP->R[1];
2845 R[2] = 0x0a;
2846 R[3] = ChP->R[3];
2847 out32(ChP->IndexAddr, R);
2848}
2849
2850/***************************************************************************
2851Function: sFlushRxFIFO
2852Purpose: Flush the Rx FIFO
2853Call: sFlushRxFIFO(ChP)
2854 CHANNEL_T *ChP; Ptr to channel structure
2855Return: void
2856Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2857 while it is being flushed the receive processor is stopped
2858 and the transmitter is disabled. After these operations a
2859 4 uS delay is done before clearing the pointers to allow
2860 the receive processor to stop. These items are handled inside
2861 this function.
2862Warnings: No context switches are allowed while executing this function.
2863*/
2864static void sFlushRxFIFO(CHANNEL_T * ChP)
2865{
2866 int i;
2867 Byte_t Ch; /* channel number within AIOP */
2868 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2869
2870 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2871 return; /* don't need to flush */
2872
2873 RxFIFOEnabled = 0;
2874 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2875 RxFIFOEnabled = 1;
2876 sDisRxFIFO(ChP); /* disable it */
2877 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2878 sInB(ChP->IntChan); /* depends on bus i/o timing */
2879 }
2880 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2881 Ch = (Byte_t) sGetChanNum(ChP);
2882 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2883 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2884 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2885 sOutW(ChP->IndexData, 0);
2886 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2887 sOutW(ChP->IndexData, 0);
2888 if (RxFIFOEnabled)
2889 sEnRxFIFO(ChP); /* enable Rx FIFO */
2890}
2891
2892/***************************************************************************
2893Function: sFlushTxFIFO
2894Purpose: Flush the Tx FIFO
2895Call: sFlushTxFIFO(ChP)
2896 CHANNEL_T *ChP; Ptr to channel structure
2897Return: void
2898Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2899 while it is being flushed the receive processor is stopped
2900 and the transmitter is disabled. After these operations a
2901 4 uS delay is done before clearing the pointers to allow
2902 the receive processor to stop. These items are handled inside
2903 this function.
2904Warnings: No context switches are allowed while executing this function.
2905*/
2906static void sFlushTxFIFO(CHANNEL_T * ChP)
2907{
2908 int i;
2909 Byte_t Ch; /* channel number within AIOP */
2910 int TxEnabled; /* 1 if transmitter enabled */
2911
2912 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2913 return; /* don't need to flush */
2914
2915 TxEnabled = 0;
2916 if (ChP->TxControl[3] & TX_ENABLE) {
2917 TxEnabled = 1;
2918 sDisTransmit(ChP); /* disable transmitter */
2919 }
2920 sStopRxProcessor(ChP); /* stop Rx processor */
2921 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2922 sInB(ChP->IntChan); /* depends on bus i/o timing */
2923 Ch = (Byte_t) sGetChanNum(ChP);
2924 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2925 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2926 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2927 sOutW(ChP->IndexData, 0);
2928 if (TxEnabled)
2929 sEnTransmit(ChP); /* enable transmitter */
2930 sStartRxProcessor(ChP); /* restart Rx processor */
2931}
2932
2933/***************************************************************************
2934Function: sWriteTxPrioByte
2935Purpose: Write a byte of priority transmit data to a channel
2936Call: sWriteTxPrioByte(ChP,Data)
2937 CHANNEL_T *ChP; Ptr to channel structure
2938 Byte_t Data; The transmit data byte
2939
2940Return: int: 1 if the bytes is successfully written, otherwise 0.
2941
2942Comments: The priority byte is transmitted before any data in the Tx FIFO.
2943
2944Warnings: No context switches are allowed while executing this function.
2945*/
2946static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2947{
2948 Byte_t DWBuf[4]; /* buffer for double word writes */
2949 Word_t *WordPtr; /* must be far because Win SS != DS */
2950 register DWordIO_t IndexAddr;
2951
2952 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2953 IndexAddr = ChP->IndexAddr;
2954 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2955 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2956 return (0); /* nothing sent */
2957
2958 WordPtr = (Word_t *) (&DWBuf[0]);
2959 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2960
2961 DWBuf[2] = Data; /* data byte value */
2962 out32(IndexAddr, DWBuf); /* write it out */
2963
2964 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2965
2966 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2967 DWBuf[3] = 0; /* priority buffer pointer */
2968 out32(IndexAddr, DWBuf); /* write it out */
2969 } else { /* write it to Tx FIFO */
2970
2971 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2972 }
2973 return (1); /* 1 byte sent */
2974}
2975
2976/***************************************************************************
2977Function: sEnInterrupts
2978Purpose: Enable one or more interrupts for a channel
2979Call: sEnInterrupts(ChP,Flags)
2980 CHANNEL_T *ChP; Ptr to channel structure
2981 Word_t Flags: Interrupt enable flags, can be any combination
2982 of the following flags:
2983 TXINT_EN: Interrupt on Tx FIFO empty
2984 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2985 sSetRxTrigger())
2986 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2987 MCINT_EN: Interrupt on modem input change
2988 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2989 Interrupt Channel Register.
2990Return: void
2991Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2992 enabled. If an interrupt enable flag is not set in Flags, that
2993 interrupt will not be changed. Interrupts can be disabled with
2994 function sDisInterrupts().
2995
2996 This function sets the appropriate bit for the channel in the AIOP's
2997 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
2998 this channel's bit to be set in the AIOP's Interrupt Channel Register.
2999
3000 Interrupts must also be globally enabled before channel interrupts
3001 will be passed on to the host. This is done with function
3002 sEnGlobalInt().
3003
3004 In some cases it may be desirable to disable interrupts globally but
3005 enable channel interrupts. This would allow the global interrupt
3006 status register to be used to determine which AIOPs need service.
3007*/
3008static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3009{
3010 Byte_t Mask; /* Interrupt Mask Register */
3011
3012 ChP->RxControl[2] |=
3013 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3014
3015 out32(ChP->IndexAddr, ChP->RxControl);
3016
3017 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3018
3019 out32(ChP->IndexAddr, ChP->TxControl);
3020
3021 if (Flags & CHANINT_EN) {
3022 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3023 sOutB(ChP->IntMask, Mask);
3024 }
3025}
3026
3027/***************************************************************************
3028Function: sDisInterrupts
3029Purpose: Disable one or more interrupts for a channel
3030Call: sDisInterrupts(ChP,Flags)
3031 CHANNEL_T *ChP; Ptr to channel structure
3032 Word_t Flags: Interrupt flags, can be any combination
3033 of the following flags:
3034 TXINT_EN: Interrupt on Tx FIFO empty
3035 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3036 sSetRxTrigger())
3037 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3038 MCINT_EN: Interrupt on modem input change
3039 CHANINT_EN: Disable channel interrupt signal to the
3040 AIOP's Interrupt Channel Register.
3041Return: void
3042Comments: If an interrupt flag is set in Flags, that interrupt will be
3043 disabled. If an interrupt flag is not set in Flags, that
3044 interrupt will not be changed. Interrupts can be enabled with
3045 function sEnInterrupts().
3046
3047 This function clears the appropriate bit for the channel in the AIOP's
3048 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3049 this channel's bit from being set in the AIOP's Interrupt Channel
3050 Register.
3051*/
3052static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3053{
3054 Byte_t Mask; /* Interrupt Mask Register */
3055
3056 ChP->RxControl[2] &=
3057 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3058 out32(ChP->IndexAddr, ChP->RxControl);
3059 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3060 out32(ChP->IndexAddr, ChP->TxControl);
3061
3062 if (Flags & CHANINT_EN) {
3063 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3064 sOutB(ChP->IntMask, Mask);
3065 }
3066}
3067
3068static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3069{
3070 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3071}
3072
3073/*
3074 * Not an official SSCI function, but how to reset RocketModems.
3075 * ISA bus version
3076 */
3077static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3078{
3079 ByteIO_t addr;
3080 Byte_t val;
3081
3082 addr = CtlP->AiopIO[0] + 0x400;
3083 val = sInB(CtlP->MReg3IO);
3084 /* if AIOP[1] is not enabled, enable it */
3085 if ((val & 2) == 0) {
3086 val = sInB(CtlP->MReg2IO);
3087 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3088 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3089 }
3090
3091 sEnAiop(CtlP, 1);
3092 if (!on)
3093 addr += 8;
3094 sOutB(addr + chan, 0); /* apply or remove reset */
3095 sDisAiop(CtlP, 1);
3096}
3097
3098/*
3099 * Not an official SSCI function, but how to reset RocketModems.
3100 * PCI bus version
3101 */
3102static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3103{
3104 ByteIO_t addr;
3105
3106 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3107 if (!on)
3108 addr += 8;
3109 sOutB(addr + chan, 0); /* apply or remove reset */
3110}
3111
3112/* Returns the line number given the controller (board), aiop and channel number */
3113static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3114{
3115 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3116}
3117
3118/*
3119 * Stores the line number associated with a given controller (board), aiop
3120 * and channel number.
3121 * Returns: The line number assigned
3122 */
3123static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3124{
3125 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3126 return (nextLineNumber - 1);
3127}
1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
75#include <linux/serial.h>
76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
79#include <linux/mutex.h>
80#include <linux/ioport.h>
81#include <linux/delay.h>
82#include <linux/completion.h>
83#include <linux/wait.h>
84#include <linux/pci.h>
85#include <linux/uaccess.h>
86#include <linux/atomic.h>
87#include <asm/unaligned.h>
88#include <linux/bitops.h>
89#include <linux/spinlock.h>
90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
102static void rp_do_poll(unsigned long dummy);
103
104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
121static bool support_low_speed;
122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
138static const struct tty_port_operations rocket_port_ops;
139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
153#ifdef CONFIG_PCI
154static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
158 UPCI_AIOP_INTR_BIT_3
159};
160#endif
161
162static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
181};
182
183static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197};
198
199static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208};
209
210static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212};
213
214static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216};
217
218static int sClockPrescale = 0x14;
219
220/*
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
224 */
225static unsigned char lineNumbers[MAX_RP_PORTS];
226static unsigned long nextLineNumber;
227
228/***** RocketPort Static Prototypes *********/
229static int __init init_ISA(int i);
230static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231static void rp_flush_buffer(struct tty_struct *tty);
232static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234static void rp_start(struct tty_struct *tty);
235static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 int ChanNum);
237static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238static void sFlushRxFIFO(CHANNEL_T * ChP);
239static void sFlushTxFIFO(CHANNEL_T * ChP);
240static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248static int sReadAiopID(ByteIO_t io);
249static int sReadAiopNumChan(WordIO_t io);
250
251MODULE_AUTHOR("Theodore Ts'o");
252MODULE_DESCRIPTION("Comtrol RocketPort driver");
253module_param(board1, ulong, 0);
254MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255module_param(board2, ulong, 0);
256MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257module_param(board3, ulong, 0);
258MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259module_param(board4, ulong, 0);
260MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261module_param(controller, ulong, 0);
262MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263module_param(support_low_speed, bool, 0);
264MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265module_param(modem1, ulong, 0);
266MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267module_param(modem2, ulong, 0);
268MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269module_param(modem3, ulong, 0);
270MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271module_param(modem4, ulong, 0);
272MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273module_param_array(pc104_1, ulong, NULL, 0);
274MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275module_param_array(pc104_2, ulong, NULL, 0);
276MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277module_param_array(pc104_3, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279module_param_array(pc104_4, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281
282static int rp_init(void);
283static void rp_cleanup_module(void);
284
285module_init(rp_init);
286module_exit(rp_cleanup_module);
287
288
289MODULE_LICENSE("Dual BSD/GPL");
290
291/*************************************************************************/
292/* Module code starts here */
293
294static inline int rocket_paranoia_check(struct r_port *info,
295 const char *routine)
296{
297#ifdef ROCKET_PARANOIA_CHECK
298 if (!info)
299 return 1;
300 if (info->magic != RPORT_MAGIC) {
301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
303 return 1;
304 }
305#endif
306 return 0;
307}
308
309
310/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
312 * tty layer.
313 */
314static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
316{
317 unsigned int CharNStat;
318 int ToRecv, wRecv, space;
319 unsigned char *cbuf;
320
321 ToRecv = sGetRxCnt(cp);
322#ifdef ROCKET_DEBUG_INTR
323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
324#endif
325 if (ToRecv == 0)
326 return;
327
328 /*
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
332 */
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335#ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Entering STATMODE...\n");
337#endif
338 ChanStatus |= STATMODE;
339 sEnRxStatusMode(cp);
340 }
341 }
342
343 /*
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
347 */
348 if (ChanStatus & STATMODE) {
349#ifdef ROCKET_DEBUG_RECEIVE
350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
352#endif
353 while (ToRecv) {
354 char flag;
355
356 CharNStat = sInW(sGetTxRxDataIO(cp));
357#ifdef ROCKET_DEBUG_RECEIVE
358 printk(KERN_INFO "%x...\n", CharNStat);
359#endif
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
363 ToRecv--;
364 continue;
365 }
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
368 flag = TTY_BREAK;
369 else if (CharNStat & STMPARITYH)
370 flag = TTY_PARITY;
371 else if (CharNStat & STMFRAMEH)
372 flag = TTY_FRAME;
373 else if (CharNStat & STMRCVROVRH)
374 flag = TTY_OVERRUN;
375 else
376 flag = TTY_NORMAL;
377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
378 flag);
379 ToRecv--;
380 }
381
382 /*
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
385 */
386 if (sGetRxCnt(cp) == 0) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
389#endif
390 sDisRxStatusMode(cp);
391 }
392 } else {
393 /*
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
396 * transfer.
397 */
398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399 if (space < ToRecv) {
400#ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402#endif
403 if (space <= 0)
404 return;
405 ToRecv = space;
406 }
407 wRecv = ToRecv >> 1;
408 if (wRecv)
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410 if (ToRecv & 1)
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
412 }
413 /* Push the data up to the tty layer */
414 tty_flip_buffer_push(&info->port);
415}
416
417/*
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
422 */
423static void rp_do_transmit(struct r_port *info)
424{
425 int c;
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
428 unsigned long flags;
429
430#ifdef ROCKET_DEBUG_INTR
431 printk(KERN_DEBUG "%s\n", __func__);
432#endif
433 if (!info)
434 return;
435 tty = tty_port_tty_get(&info->port);
436
437 if (tty == NULL) {
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440 return;
441 }
442
443 spin_lock_irqsave(&info->slock, flags);
444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445
446 /* Loop sending data to FIFO until done or FIFO full */
447 while (1) {
448 if (tty->stopped)
449 break;
450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452 if (c <= 0 || info->xmit_fifo_room <= 0)
453 break;
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455 if (c & 1)
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459 info->xmit_cnt -= c;
460 info->xmit_fifo_room -= c;
461#ifdef ROCKET_DEBUG_INTR
462 printk(KERN_INFO "tx %d chars...\n", c);
463#endif
464 }
465
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468
469 if (info->xmit_cnt < WAKEUP_CHARS) {
470 tty_wakeup(tty);
471#ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
473#endif
474 }
475
476 spin_unlock_irqrestore(&info->slock, flags);
477 tty_kref_put(tty);
478
479#ifdef ROCKET_DEBUG_INTR
480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481 info->xmit_tail, info->xmit_fifo_room);
482#endif
483}
484
485/*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
490static void rp_handle_port(struct r_port *info)
491{
492 CHANNEL_t *cp;
493 unsigned int IntMask, ChanStatus;
494
495 if (!info)
496 return;
497
498 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
501 return;
502 }
503
504 cp = &info->channel;
505
506 IntMask = sGetChanIntID(cp) & info->intmask;
507#ifdef ROCKET_DEBUG_INTR
508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
509#endif
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
512 rp_do_receive(info, cp, ChanStatus);
513 }
514 if (IntMask & DELTA_CD) { /* CD change */
515#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517 (ChanStatus & CD_ACT) ? "on" : "off");
518#endif
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520#ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
522#endif
523 tty_port_tty_hangup(&info->port, false);
524 }
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526 wake_up_interruptible(&info->port.open_wait);
527 }
528#ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
531 }
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
534 }
535#endif
536}
537
538/*
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
540 */
541static void rp_do_poll(unsigned long dummy)
542{
543 CONTROLLER_t *ctlp;
544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
546 unsigned int CtlMask;
547 unsigned char AiopMask;
548 Word_t bit;
549
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
553 continue;
554
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
557
558 /* Get the interrupt status from the board */
559#ifdef CONFIG_PCI
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
562 else
563#endif
564 CtlMask = sGetControllerIntStatus(ctlp);
565
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
569 if (CtlMask & bit) {
570 CtlMask &= ~bit;
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
575 if (AiopMask & 1) {
576
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
581 }
582 }
583 }
584 }
585
586 xmitmask = xmit_flags[ctrl];
587
588 /*
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593 */
594 if (xmitmask) {
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
598 ch = i & 0x07;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
601 }
602 }
603 }
604 }
605
606 /*
607 * Reset the timer so we get called at the next clock tick (10ms).
608 */
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611}
612
613/*
614 * Initializes the r_port structure for a port, as well as enabling the port on
615 * the board.
616 * Inputs: board, aiop, chan numbers
617 */
618static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
619{
620 unsigned rocketMode;
621 struct r_port *info;
622 int line;
623 CONTROLLER_T *ctlp;
624
625 /* Get the next available line number */
626 line = SetLineNumber(board, aiop, chan);
627
628 ctlp = sCtlNumToCtlPtr(board);
629
630 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
631 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
632 if (!info) {
633 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
634 line);
635 return;
636 }
637
638 info->magic = RPORT_MAGIC;
639 info->line = line;
640 info->ctlp = ctlp;
641 info->board = board;
642 info->aiop = aiop;
643 info->chan = chan;
644 tty_port_init(&info->port);
645 info->port.ops = &rocket_port_ops;
646 init_completion(&info->close_wait);
647 info->flags &= ~ROCKET_MODE_MASK;
648 switch (pc104[board][line]) {
649 case 422:
650 info->flags |= ROCKET_MODE_RS422;
651 break;
652 case 485:
653 info->flags |= ROCKET_MODE_RS485;
654 break;
655 case 232:
656 default:
657 info->flags |= ROCKET_MODE_RS232;
658 break;
659 }
660
661 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
663 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664 board, aiop, chan);
665 tty_port_destroy(&info->port);
666 kfree(info);
667 return;
668 }
669
670 rocketMode = info->flags & ROCKET_MODE_MASK;
671
672 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673 sEnRTSToggle(&info->channel);
674 else
675 sDisRTSToggle(&info->channel);
676
677 if (ctlp->boardType == ROCKET_TYPE_PC104) {
678 switch (rocketMode) {
679 case ROCKET_MODE_RS485:
680 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681 break;
682 case ROCKET_MODE_RS422:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684 break;
685 case ROCKET_MODE_RS232:
686 default:
687 if (info->flags & ROCKET_RTS_TOGGLE)
688 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689 else
690 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691 break;
692 }
693 }
694 spin_lock_init(&info->slock);
695 mutex_init(&info->write_mtx);
696 rp_table[line] = info;
697 tty_port_register_device(&info->port, rocket_driver, line,
698 pci_dev ? &pci_dev->dev : NULL);
699}
700
701/*
702 * Configures a rocketport port according to its termio settings. Called from
703 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
704 */
705static void configure_r_port(struct tty_struct *tty, struct r_port *info,
706 struct ktermios *old_termios)
707{
708 unsigned cflag;
709 unsigned long flags;
710 unsigned rocketMode;
711 int bits, baud, divisor;
712 CHANNEL_t *cp;
713 struct ktermios *t = &tty->termios;
714
715 cp = &info->channel;
716 cflag = t->c_cflag;
717
718 /* Byte size and parity */
719 if ((cflag & CSIZE) == CS8) {
720 sSetData8(cp);
721 bits = 10;
722 } else {
723 sSetData7(cp);
724 bits = 9;
725 }
726 if (cflag & CSTOPB) {
727 sSetStop2(cp);
728 bits++;
729 } else {
730 sSetStop1(cp);
731 }
732
733 if (cflag & PARENB) {
734 sEnParity(cp);
735 bits++;
736 if (cflag & PARODD) {
737 sSetOddParity(cp);
738 } else {
739 sSetEvenParity(cp);
740 }
741 } else {
742 sDisParity(cp);
743 }
744
745 /* baud rate */
746 baud = tty_get_baud_rate(tty);
747 if (!baud)
748 baud = 9600;
749 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750 if ((divisor >= 8192 || divisor < 0) && old_termios) {
751 baud = tty_termios_baud_rate(old_termios);
752 if (!baud)
753 baud = 9600;
754 divisor = (rp_baud_base[info->board] / baud) - 1;
755 }
756 if (divisor >= 8192 || divisor < 0) {
757 baud = 9600;
758 divisor = (rp_baud_base[info->board] / baud) - 1;
759 }
760 info->cps = baud / bits;
761 sSetBaud(cp, divisor);
762
763 /* FIXME: Should really back compute a baud rate from the divisor */
764 tty_encode_baud_rate(tty, baud, baud);
765
766 if (cflag & CRTSCTS) {
767 info->intmask |= DELTA_CTS;
768 sEnCTSFlowCtl(cp);
769 } else {
770 info->intmask &= ~DELTA_CTS;
771 sDisCTSFlowCtl(cp);
772 }
773 if (cflag & CLOCAL) {
774 info->intmask &= ~DELTA_CD;
775 } else {
776 spin_lock_irqsave(&info->slock, flags);
777 if (sGetChanStatus(cp) & CD_ACT)
778 info->cd_status = 1;
779 else
780 info->cd_status = 0;
781 info->intmask |= DELTA_CD;
782 spin_unlock_irqrestore(&info->slock, flags);
783 }
784
785 /*
786 * Handle software flow control in the board
787 */
788#ifdef ROCKET_SOFT_FLOW
789 if (I_IXON(tty)) {
790 sEnTxSoftFlowCtl(cp);
791 if (I_IXANY(tty)) {
792 sEnIXANY(cp);
793 } else {
794 sDisIXANY(cp);
795 }
796 sSetTxXONChar(cp, START_CHAR(tty));
797 sSetTxXOFFChar(cp, STOP_CHAR(tty));
798 } else {
799 sDisTxSoftFlowCtl(cp);
800 sDisIXANY(cp);
801 sClrTxXOFF(cp);
802 }
803#endif
804
805 /*
806 * Set up ignore/read mask words
807 */
808 info->read_status_mask = STMRCVROVRH | 0xFF;
809 if (I_INPCK(tty))
810 info->read_status_mask |= STMFRAMEH | STMPARITYH;
811 if (I_BRKINT(tty) || I_PARMRK(tty))
812 info->read_status_mask |= STMBREAKH;
813
814 /*
815 * Characters to ignore
816 */
817 info->ignore_status_mask = 0;
818 if (I_IGNPAR(tty))
819 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
820 if (I_IGNBRK(tty)) {
821 info->ignore_status_mask |= STMBREAKH;
822 /*
823 * If we're ignoring parity and break indicators,
824 * ignore overruns too. (For real raw support).
825 */
826 if (I_IGNPAR(tty))
827 info->ignore_status_mask |= STMRCVROVRH;
828 }
829
830 rocketMode = info->flags & ROCKET_MODE_MASK;
831
832 if ((info->flags & ROCKET_RTS_TOGGLE)
833 || (rocketMode == ROCKET_MODE_RS485))
834 sEnRTSToggle(cp);
835 else
836 sDisRTSToggle(cp);
837
838 sSetRTS(&info->channel);
839
840 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841 switch (rocketMode) {
842 case ROCKET_MODE_RS485:
843 sSetInterfaceMode(cp, InterfaceModeRS485);
844 break;
845 case ROCKET_MODE_RS422:
846 sSetInterfaceMode(cp, InterfaceModeRS422);
847 break;
848 case ROCKET_MODE_RS232:
849 default:
850 if (info->flags & ROCKET_RTS_TOGGLE)
851 sSetInterfaceMode(cp, InterfaceModeRS232T);
852 else
853 sSetInterfaceMode(cp, InterfaceModeRS232);
854 break;
855 }
856 }
857}
858
859static int carrier_raised(struct tty_port *port)
860{
861 struct r_port *info = container_of(port, struct r_port, port);
862 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863}
864
865static void dtr_rts(struct tty_port *port, int on)
866{
867 struct r_port *info = container_of(port, struct r_port, port);
868 if (on) {
869 sSetDTR(&info->channel);
870 sSetRTS(&info->channel);
871 } else {
872 sClrDTR(&info->channel);
873 sClrRTS(&info->channel);
874 }
875}
876
877/*
878 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
879 * port's r_port struct. Initializes the port hardware.
880 */
881static int rp_open(struct tty_struct *tty, struct file *filp)
882{
883 struct r_port *info;
884 struct tty_port *port;
885 int retval;
886 CHANNEL_t *cp;
887 unsigned long page;
888
889 info = rp_table[tty->index];
890 if (info == NULL)
891 return -ENXIO;
892 port = &info->port;
893
894 page = __get_free_page(GFP_KERNEL);
895 if (!page)
896 return -ENOMEM;
897
898 if (port->flags & ASYNC_CLOSING) {
899 retval = wait_for_completion_interruptible(&info->close_wait);
900 free_page(page);
901 if (retval)
902 return retval;
903 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
904 }
905
906 /*
907 * We must not sleep from here until the port is marked fully in use.
908 */
909 if (info->xmit_buf)
910 free_page(page);
911 else
912 info->xmit_buf = (unsigned char *) page;
913
914 tty->driver_data = info;
915 tty_port_tty_set(port, tty);
916
917 if (port->count++ == 0) {
918 atomic_inc(&rp_num_ports_open);
919
920#ifdef ROCKET_DEBUG_OPEN
921 printk(KERN_INFO "rocket mod++ = %d...\n",
922 atomic_read(&rp_num_ports_open));
923#endif
924 }
925#ifdef ROCKET_DEBUG_OPEN
926 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
927#endif
928
929 /*
930 * Info->count is now 1; so it's safe to sleep now.
931 */
932 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
933 cp = &info->channel;
934 sSetRxTrigger(cp, TRIG_1);
935 if (sGetChanStatus(cp) & CD_ACT)
936 info->cd_status = 1;
937 else
938 info->cd_status = 0;
939 sDisRxStatusMode(cp);
940 sFlushRxFIFO(cp);
941 sFlushTxFIFO(cp);
942
943 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
944 sSetRxTrigger(cp, TRIG_1);
945
946 sGetChanStatus(cp);
947 sDisRxStatusMode(cp);
948 sClrTxXOFF(cp);
949
950 sDisCTSFlowCtl(cp);
951 sDisTxSoftFlowCtl(cp);
952
953 sEnRxFIFO(cp);
954 sEnTransmit(cp);
955
956 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
957
958 /*
959 * Set up the tty->alt_speed kludge
960 */
961 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
962 tty->alt_speed = 57600;
963 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
964 tty->alt_speed = 115200;
965 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
966 tty->alt_speed = 230400;
967 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
968 tty->alt_speed = 460800;
969
970 configure_r_port(tty, info, NULL);
971 if (tty->termios.c_cflag & CBAUD) {
972 sSetDTR(cp);
973 sSetRTS(cp);
974 }
975 }
976 /* Starts (or resets) the maint polling loop */
977 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
978
979 retval = tty_port_block_til_ready(port, tty, filp);
980 if (retval) {
981#ifdef ROCKET_DEBUG_OPEN
982 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
983#endif
984 return retval;
985 }
986 return 0;
987}
988
989/*
990 * Exception handler that closes a serial port. info->port.count is considered critical.
991 */
992static void rp_close(struct tty_struct *tty, struct file *filp)
993{
994 struct r_port *info = tty->driver_data;
995 struct tty_port *port = &info->port;
996 int timeout;
997 CHANNEL_t *cp;
998
999 if (rocket_paranoia_check(info, "rp_close"))
1000 return;
1001
1002#ifdef ROCKET_DEBUG_OPEN
1003 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1004#endif
1005
1006 if (tty_port_close_start(port, tty, filp) == 0)
1007 return;
1008
1009 mutex_lock(&port->mutex);
1010 cp = &info->channel;
1011 /*
1012 * Before we drop DTR, make sure the UART transmitter
1013 * has completely drained; this is especially
1014 * important if there is a transmit FIFO!
1015 */
1016 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1017 if (timeout == 0)
1018 timeout = 1;
1019 rp_wait_until_sent(tty, timeout);
1020 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1021
1022 sDisTransmit(cp);
1023 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1024 sDisCTSFlowCtl(cp);
1025 sDisTxSoftFlowCtl(cp);
1026 sClrTxXOFF(cp);
1027 sFlushRxFIFO(cp);
1028 sFlushTxFIFO(cp);
1029 sClrRTS(cp);
1030 if (C_HUPCL(tty))
1031 sClrDTR(cp);
1032
1033 rp_flush_buffer(tty);
1034
1035 tty_ldisc_flush(tty);
1036
1037 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1038
1039 /* We can't yet use tty_port_close_end as the buffer handling in this
1040 driver is a bit different to the usual */
1041
1042 if (port->blocked_open) {
1043 if (port->close_delay) {
1044 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1045 }
1046 wake_up_interruptible(&port->open_wait);
1047 } else {
1048 if (info->xmit_buf) {
1049 free_page((unsigned long) info->xmit_buf);
1050 info->xmit_buf = NULL;
1051 }
1052 }
1053 spin_lock_irq(&port->lock);
1054 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1055 tty->closing = 0;
1056 spin_unlock_irq(&port->lock);
1057 mutex_unlock(&port->mutex);
1058 tty_port_tty_set(port, NULL);
1059
1060 wake_up_interruptible(&port->close_wait);
1061 complete_all(&info->close_wait);
1062 atomic_dec(&rp_num_ports_open);
1063
1064#ifdef ROCKET_DEBUG_OPEN
1065 printk(KERN_INFO "rocket mod-- = %d...\n",
1066 atomic_read(&rp_num_ports_open));
1067 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1068#endif
1069
1070}
1071
1072static void rp_set_termios(struct tty_struct *tty,
1073 struct ktermios *old_termios)
1074{
1075 struct r_port *info = tty->driver_data;
1076 CHANNEL_t *cp;
1077 unsigned cflag;
1078
1079 if (rocket_paranoia_check(info, "rp_set_termios"))
1080 return;
1081
1082 cflag = tty->termios.c_cflag;
1083
1084 /*
1085 * This driver doesn't support CS5 or CS6
1086 */
1087 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1088 tty->termios.c_cflag =
1089 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1090 /* Or CMSPAR */
1091 tty->termios.c_cflag &= ~CMSPAR;
1092
1093 configure_r_port(tty, info, old_termios);
1094
1095 cp = &info->channel;
1096
1097 /* Handle transition to B0 status */
1098 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1099 sClrDTR(cp);
1100 sClrRTS(cp);
1101 }
1102
1103 /* Handle transition away from B0 status */
1104 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1105 sSetRTS(cp);
1106 sSetDTR(cp);
1107 }
1108
1109 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1110 rp_start(tty);
1111}
1112
1113static int rp_break(struct tty_struct *tty, int break_state)
1114{
1115 struct r_port *info = tty->driver_data;
1116 unsigned long flags;
1117
1118 if (rocket_paranoia_check(info, "rp_break"))
1119 return -EINVAL;
1120
1121 spin_lock_irqsave(&info->slock, flags);
1122 if (break_state == -1)
1123 sSendBreak(&info->channel);
1124 else
1125 sClrBreak(&info->channel);
1126 spin_unlock_irqrestore(&info->slock, flags);
1127 return 0;
1128}
1129
1130/*
1131 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1132 * the UPCI boards was added, it was decided to make this a function because
1133 * the macro was getting too complicated. All cases except the first one
1134 * (UPCIRingInd) are taken directly from the original macro.
1135 */
1136static int sGetChanRI(CHANNEL_T * ChP)
1137{
1138 CONTROLLER_t *CtlP = ChP->CtlP;
1139 int ChanNum = ChP->ChanNum;
1140 int RingInd = 0;
1141
1142 if (CtlP->UPCIRingInd)
1143 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1144 else if (CtlP->AltChanRingIndicator)
1145 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1146 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1147 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1148
1149 return RingInd;
1150}
1151
1152/********************************************************************************************/
1153/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1154
1155/*
1156 * Returns the state of the serial modem control lines. These next 2 functions
1157 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1158 */
1159static int rp_tiocmget(struct tty_struct *tty)
1160{
1161 struct r_port *info = tty->driver_data;
1162 unsigned int control, result, ChanStatus;
1163
1164 ChanStatus = sGetChanStatusLo(&info->channel);
1165 control = info->channel.TxControl[3];
1166 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1167 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1168 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1169 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1170 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1171 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1172
1173 return result;
1174}
1175
1176/*
1177 * Sets the modem control lines
1178 */
1179static int rp_tiocmset(struct tty_struct *tty,
1180 unsigned int set, unsigned int clear)
1181{
1182 struct r_port *info = tty->driver_data;
1183
1184 if (set & TIOCM_RTS)
1185 info->channel.TxControl[3] |= SET_RTS;
1186 if (set & TIOCM_DTR)
1187 info->channel.TxControl[3] |= SET_DTR;
1188 if (clear & TIOCM_RTS)
1189 info->channel.TxControl[3] &= ~SET_RTS;
1190 if (clear & TIOCM_DTR)
1191 info->channel.TxControl[3] &= ~SET_DTR;
1192
1193 out32(info->channel.IndexAddr, info->channel.TxControl);
1194 return 0;
1195}
1196
1197static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1198{
1199 struct rocket_config tmp;
1200
1201 if (!retinfo)
1202 return -EFAULT;
1203 memset(&tmp, 0, sizeof (tmp));
1204 mutex_lock(&info->port.mutex);
1205 tmp.line = info->line;
1206 tmp.flags = info->flags;
1207 tmp.close_delay = info->port.close_delay;
1208 tmp.closing_wait = info->port.closing_wait;
1209 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1210 mutex_unlock(&info->port.mutex);
1211
1212 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1213 return -EFAULT;
1214 return 0;
1215}
1216
1217static int set_config(struct tty_struct *tty, struct r_port *info,
1218 struct rocket_config __user *new_info)
1219{
1220 struct rocket_config new_serial;
1221
1222 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1223 return -EFAULT;
1224
1225 mutex_lock(&info->port.mutex);
1226 if (!capable(CAP_SYS_ADMIN))
1227 {
1228 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1229 mutex_unlock(&info->port.mutex);
1230 return -EPERM;
1231 }
1232 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1233 configure_r_port(tty, info, NULL);
1234 mutex_unlock(&info->port.mutex);
1235 return 0;
1236 }
1237
1238 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1239 info->port.close_delay = new_serial.close_delay;
1240 info->port.closing_wait = new_serial.closing_wait;
1241
1242 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1243 tty->alt_speed = 57600;
1244 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1245 tty->alt_speed = 115200;
1246 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1247 tty->alt_speed = 230400;
1248 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1249 tty->alt_speed = 460800;
1250 mutex_unlock(&info->port.mutex);
1251
1252 configure_r_port(tty, info, NULL);
1253 return 0;
1254}
1255
1256/*
1257 * This function fills in a rocket_ports struct with information
1258 * about what boards/ports are in the system. This info is passed
1259 * to user space. See setrocket.c where the info is used to create
1260 * the /dev/ttyRx ports.
1261 */
1262static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1263{
1264 struct rocket_ports tmp;
1265 int board;
1266
1267 if (!retports)
1268 return -EFAULT;
1269 memset(&tmp, 0, sizeof (tmp));
1270 tmp.tty_major = rocket_driver->major;
1271
1272 for (board = 0; board < 4; board++) {
1273 tmp.rocketModel[board].model = rocketModel[board].model;
1274 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1275 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1276 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1277 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1278 }
1279 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1280 return -EFAULT;
1281 return 0;
1282}
1283
1284static int reset_rm2(struct r_port *info, void __user *arg)
1285{
1286 int reset;
1287
1288 if (!capable(CAP_SYS_ADMIN))
1289 return -EPERM;
1290
1291 if (copy_from_user(&reset, arg, sizeof (int)))
1292 return -EFAULT;
1293 if (reset)
1294 reset = 1;
1295
1296 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1297 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1298 return -EINVAL;
1299
1300 if (info->ctlp->BusType == isISA)
1301 sModemReset(info->ctlp, info->chan, reset);
1302 else
1303 sPCIModemReset(info->ctlp, info->chan, reset);
1304
1305 return 0;
1306}
1307
1308static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1309{
1310 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1311 return -EFAULT;
1312 return 0;
1313}
1314
1315/* IOCTL call handler into the driver */
1316static int rp_ioctl(struct tty_struct *tty,
1317 unsigned int cmd, unsigned long arg)
1318{
1319 struct r_port *info = tty->driver_data;
1320 void __user *argp = (void __user *)arg;
1321 int ret = 0;
1322
1323 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1324 return -ENXIO;
1325
1326 switch (cmd) {
1327 case RCKP_GET_STRUCT:
1328 if (copy_to_user(argp, info, sizeof (struct r_port)))
1329 ret = -EFAULT;
1330 break;
1331 case RCKP_GET_CONFIG:
1332 ret = get_config(info, argp);
1333 break;
1334 case RCKP_SET_CONFIG:
1335 ret = set_config(tty, info, argp);
1336 break;
1337 case RCKP_GET_PORTS:
1338 ret = get_ports(info, argp);
1339 break;
1340 case RCKP_RESET_RM2:
1341 ret = reset_rm2(info, argp);
1342 break;
1343 case RCKP_GET_VERSION:
1344 ret = get_version(info, argp);
1345 break;
1346 default:
1347 ret = -ENOIOCTLCMD;
1348 }
1349 return ret;
1350}
1351
1352static void rp_send_xchar(struct tty_struct *tty, char ch)
1353{
1354 struct r_port *info = tty->driver_data;
1355 CHANNEL_t *cp;
1356
1357 if (rocket_paranoia_check(info, "rp_send_xchar"))
1358 return;
1359
1360 cp = &info->channel;
1361 if (sGetTxCnt(cp))
1362 sWriteTxPrioByte(cp, ch);
1363 else
1364 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1365}
1366
1367static void rp_throttle(struct tty_struct *tty)
1368{
1369 struct r_port *info = tty->driver_data;
1370
1371#ifdef ROCKET_DEBUG_THROTTLE
1372 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1373 tty->ldisc.chars_in_buffer(tty));
1374#endif
1375
1376 if (rocket_paranoia_check(info, "rp_throttle"))
1377 return;
1378
1379 if (I_IXOFF(tty))
1380 rp_send_xchar(tty, STOP_CHAR(tty));
1381
1382 sClrRTS(&info->channel);
1383}
1384
1385static void rp_unthrottle(struct tty_struct *tty)
1386{
1387 struct r_port *info = tty->driver_data;
1388#ifdef ROCKET_DEBUG_THROTTLE
1389 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1390 tty->ldisc.chars_in_buffer(tty));
1391#endif
1392
1393 if (rocket_paranoia_check(info, "rp_throttle"))
1394 return;
1395
1396 if (I_IXOFF(tty))
1397 rp_send_xchar(tty, START_CHAR(tty));
1398
1399 sSetRTS(&info->channel);
1400}
1401
1402/*
1403 * ------------------------------------------------------------
1404 * rp_stop() and rp_start()
1405 *
1406 * This routines are called before setting or resetting tty->stopped.
1407 * They enable or disable transmitter interrupts, as necessary.
1408 * ------------------------------------------------------------
1409 */
1410static void rp_stop(struct tty_struct *tty)
1411{
1412 struct r_port *info = tty->driver_data;
1413
1414#ifdef ROCKET_DEBUG_FLOW
1415 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1416 info->xmit_cnt, info->xmit_fifo_room);
1417#endif
1418
1419 if (rocket_paranoia_check(info, "rp_stop"))
1420 return;
1421
1422 if (sGetTxCnt(&info->channel))
1423 sDisTransmit(&info->channel);
1424}
1425
1426static void rp_start(struct tty_struct *tty)
1427{
1428 struct r_port *info = tty->driver_data;
1429
1430#ifdef ROCKET_DEBUG_FLOW
1431 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1432 info->xmit_cnt, info->xmit_fifo_room);
1433#endif
1434
1435 if (rocket_paranoia_check(info, "rp_stop"))
1436 return;
1437
1438 sEnTransmit(&info->channel);
1439 set_bit((info->aiop * 8) + info->chan,
1440 (void *) &xmit_flags[info->board]);
1441}
1442
1443/*
1444 * rp_wait_until_sent() --- wait until the transmitter is empty
1445 */
1446static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1447{
1448 struct r_port *info = tty->driver_data;
1449 CHANNEL_t *cp;
1450 unsigned long orig_jiffies;
1451 int check_time, exit_time;
1452 int txcnt;
1453
1454 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1455 return;
1456
1457 cp = &info->channel;
1458
1459 orig_jiffies = jiffies;
1460#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1461 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1462 jiffies);
1463 printk(KERN_INFO "cps=%d...\n", info->cps);
1464#endif
1465 while (1) {
1466 txcnt = sGetTxCnt(cp);
1467 if (!txcnt) {
1468 if (sGetChanStatusLo(cp) & TXSHRMT)
1469 break;
1470 check_time = (HZ / info->cps) / 5;
1471 } else {
1472 check_time = HZ * txcnt / info->cps;
1473 }
1474 if (timeout) {
1475 exit_time = orig_jiffies + timeout - jiffies;
1476 if (exit_time <= 0)
1477 break;
1478 if (exit_time < check_time)
1479 check_time = exit_time;
1480 }
1481 if (check_time == 0)
1482 check_time = 1;
1483#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1484 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1485 jiffies, check_time);
1486#endif
1487 msleep_interruptible(jiffies_to_msecs(check_time));
1488 if (signal_pending(current))
1489 break;
1490 }
1491 __set_current_state(TASK_RUNNING);
1492#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1493 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1494#endif
1495}
1496
1497/*
1498 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1499 */
1500static void rp_hangup(struct tty_struct *tty)
1501{
1502 CHANNEL_t *cp;
1503 struct r_port *info = tty->driver_data;
1504 unsigned long flags;
1505
1506 if (rocket_paranoia_check(info, "rp_hangup"))
1507 return;
1508
1509#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1510 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1511#endif
1512 rp_flush_buffer(tty);
1513 spin_lock_irqsave(&info->port.lock, flags);
1514 if (info->port.flags & ASYNC_CLOSING) {
1515 spin_unlock_irqrestore(&info->port.lock, flags);
1516 return;
1517 }
1518 if (info->port.count)
1519 atomic_dec(&rp_num_ports_open);
1520 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1521 spin_unlock_irqrestore(&info->port.lock, flags);
1522
1523 tty_port_hangup(&info->port);
1524
1525 cp = &info->channel;
1526 sDisRxFIFO(cp);
1527 sDisTransmit(cp);
1528 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1529 sDisCTSFlowCtl(cp);
1530 sDisTxSoftFlowCtl(cp);
1531 sClrTxXOFF(cp);
1532 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1533
1534 wake_up_interruptible(&info->port.open_wait);
1535}
1536
1537/*
1538 * Exception handler - write char routine. The RocketPort driver uses a
1539 * double-buffering strategy, with the twist that if the in-memory CPU
1540 * buffer is empty, and there's space in the transmit FIFO, the
1541 * writing routines will write directly to transmit FIFO.
1542 * Write buffer and counters protected by spinlocks
1543 */
1544static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1545{
1546 struct r_port *info = tty->driver_data;
1547 CHANNEL_t *cp;
1548 unsigned long flags;
1549
1550 if (rocket_paranoia_check(info, "rp_put_char"))
1551 return 0;
1552
1553 /*
1554 * Grab the port write mutex, locking out other processes that try to
1555 * write to this port
1556 */
1557 mutex_lock(&info->write_mtx);
1558
1559#ifdef ROCKET_DEBUG_WRITE
1560 printk(KERN_INFO "rp_put_char %c...\n", ch);
1561#endif
1562
1563 spin_lock_irqsave(&info->slock, flags);
1564 cp = &info->channel;
1565
1566 if (!tty->stopped && info->xmit_fifo_room == 0)
1567 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1568
1569 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1570 info->xmit_buf[info->xmit_head++] = ch;
1571 info->xmit_head &= XMIT_BUF_SIZE - 1;
1572 info->xmit_cnt++;
1573 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1574 } else {
1575 sOutB(sGetTxRxDataIO(cp), ch);
1576 info->xmit_fifo_room--;
1577 }
1578 spin_unlock_irqrestore(&info->slock, flags);
1579 mutex_unlock(&info->write_mtx);
1580 return 1;
1581}
1582
1583/*
1584 * Exception handler - write routine, called when user app writes to the device.
1585 * A per port write mutex is used to protect from another process writing to
1586 * this port at the same time. This other process could be running on the other CPU
1587 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1588 * Spinlocks protect the info xmit members.
1589 */
1590static int rp_write(struct tty_struct *tty,
1591 const unsigned char *buf, int count)
1592{
1593 struct r_port *info = tty->driver_data;
1594 CHANNEL_t *cp;
1595 const unsigned char *b;
1596 int c, retval = 0;
1597 unsigned long flags;
1598
1599 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1600 return 0;
1601
1602 if (mutex_lock_interruptible(&info->write_mtx))
1603 return -ERESTARTSYS;
1604
1605#ifdef ROCKET_DEBUG_WRITE
1606 printk(KERN_INFO "rp_write %d chars...\n", count);
1607#endif
1608 cp = &info->channel;
1609
1610 if (!tty->stopped && info->xmit_fifo_room < count)
1611 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1612
1613 /*
1614 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1615 * into FIFO. Use the write queue for temp storage.
1616 */
1617 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1618 c = min(count, info->xmit_fifo_room);
1619 b = buf;
1620
1621 /* Push data into FIFO, 2 bytes at a time */
1622 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1623
1624 /* If there is a byte remaining, write it */
1625 if (c & 1)
1626 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1627
1628 retval += c;
1629 buf += c;
1630 count -= c;
1631
1632 spin_lock_irqsave(&info->slock, flags);
1633 info->xmit_fifo_room -= c;
1634 spin_unlock_irqrestore(&info->slock, flags);
1635 }
1636
1637 /* If count is zero, we wrote it all and are done */
1638 if (!count)
1639 goto end;
1640
1641 /* Write remaining data into the port's xmit_buf */
1642 while (1) {
1643 /* Hung up ? */
1644 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1645 goto end;
1646 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1647 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1648 if (c <= 0)
1649 break;
1650
1651 b = buf;
1652 memcpy(info->xmit_buf + info->xmit_head, b, c);
1653
1654 spin_lock_irqsave(&info->slock, flags);
1655 info->xmit_head =
1656 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1657 info->xmit_cnt += c;
1658 spin_unlock_irqrestore(&info->slock, flags);
1659
1660 buf += c;
1661 count -= c;
1662 retval += c;
1663 }
1664
1665 if ((retval > 0) && !tty->stopped)
1666 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1667
1668end:
1669 if (info->xmit_cnt < WAKEUP_CHARS) {
1670 tty_wakeup(tty);
1671#ifdef ROCKETPORT_HAVE_POLL_WAIT
1672 wake_up_interruptible(&tty->poll_wait);
1673#endif
1674 }
1675 mutex_unlock(&info->write_mtx);
1676 return retval;
1677}
1678
1679/*
1680 * Return the number of characters that can be sent. We estimate
1681 * only using the in-memory transmit buffer only, and ignore the
1682 * potential space in the transmit FIFO.
1683 */
1684static int rp_write_room(struct tty_struct *tty)
1685{
1686 struct r_port *info = tty->driver_data;
1687 int ret;
1688
1689 if (rocket_paranoia_check(info, "rp_write_room"))
1690 return 0;
1691
1692 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1693 if (ret < 0)
1694 ret = 0;
1695#ifdef ROCKET_DEBUG_WRITE
1696 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1697#endif
1698 return ret;
1699}
1700
1701/*
1702 * Return the number of characters in the buffer. Again, this only
1703 * counts those characters in the in-memory transmit buffer.
1704 */
1705static int rp_chars_in_buffer(struct tty_struct *tty)
1706{
1707 struct r_port *info = tty->driver_data;
1708
1709 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1710 return 0;
1711
1712#ifdef ROCKET_DEBUG_WRITE
1713 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1714#endif
1715 return info->xmit_cnt;
1716}
1717
1718/*
1719 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1720 * r_port struct for the port. Note that spinlock are used to protect info members,
1721 * do not call this function if the spinlock is already held.
1722 */
1723static void rp_flush_buffer(struct tty_struct *tty)
1724{
1725 struct r_port *info = tty->driver_data;
1726 CHANNEL_t *cp;
1727 unsigned long flags;
1728
1729 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1730 return;
1731
1732 spin_lock_irqsave(&info->slock, flags);
1733 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1734 spin_unlock_irqrestore(&info->slock, flags);
1735
1736#ifdef ROCKETPORT_HAVE_POLL_WAIT
1737 wake_up_interruptible(&tty->poll_wait);
1738#endif
1739 tty_wakeup(tty);
1740
1741 cp = &info->channel;
1742 sFlushTxFIFO(cp);
1743}
1744
1745#ifdef CONFIG_PCI
1746
1747static const struct pci_device_id rocket_pci_ids[] = {
1748 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1749 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1750 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1751 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1752 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1753 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1754 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1755 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1756 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1757 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1758 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1759 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1760 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1761 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1762 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1763 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1764 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1765 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1766 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1767 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1768 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1769 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1770 { }
1771};
1772MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1773
1774/* Resets the speaker controller on RocketModem II and III devices */
1775static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1776{
1777 ByteIO_t addr;
1778
1779 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1780 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1781 addr = CtlP->AiopIO[0] + 0x4F;
1782 sOutB(addr, 0);
1783 }
1784
1785 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1786 if ((model == MODEL_UPCI_RM3_8PORT)
1787 || (model == MODEL_UPCI_RM3_4PORT)) {
1788 addr = CtlP->AiopIO[0] + 0x88;
1789 sOutB(addr, 0);
1790 }
1791}
1792
1793/***************************************************************************
1794Function: sPCIInitController
1795Purpose: Initialization of controller global registers and controller
1796 structure.
1797Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1798 IRQNum,Frequency,PeriodicOnly)
1799 CONTROLLER_T *CtlP; Ptr to controller structure
1800 int CtlNum; Controller number
1801 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1802 This list must be in the order the AIOPs will be found on the
1803 controller. Once an AIOP in the list is not found, it is
1804 assumed that there are no more AIOPs on the controller.
1805 int AiopIOListSize; Number of addresses in AiopIOList
1806 int IRQNum; Interrupt Request number. Can be any of the following:
1807 0: Disable global interrupts
1808 3: IRQ 3
1809 4: IRQ 4
1810 5: IRQ 5
1811 9: IRQ 9
1812 10: IRQ 10
1813 11: IRQ 11
1814 12: IRQ 12
1815 15: IRQ 15
1816 Byte_t Frequency: A flag identifying the frequency
1817 of the periodic interrupt, can be any one of the following:
1818 FREQ_DIS - periodic interrupt disabled
1819 FREQ_137HZ - 137 Hertz
1820 FREQ_69HZ - 69 Hertz
1821 FREQ_34HZ - 34 Hertz
1822 FREQ_17HZ - 17 Hertz
1823 FREQ_9HZ - 9 Hertz
1824 FREQ_4HZ - 4 Hertz
1825 If IRQNum is set to 0 the Frequency parameter is
1826 overidden, it is forced to a value of FREQ_DIS.
1827 int PeriodicOnly: 1 if all interrupts except the periodic
1828 interrupt are to be blocked.
1829 0 is both the periodic interrupt and
1830 other channel interrupts are allowed.
1831 If IRQNum is set to 0 the PeriodicOnly parameter is
1832 overidden, it is forced to a value of 0.
1833Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1834 initialization failed.
1835
1836Comments:
1837 If periodic interrupts are to be disabled but AIOP interrupts
1838 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1839
1840 If interrupts are to be completely disabled set IRQNum to 0.
1841
1842 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1843 invalid combination.
1844
1845 This function performs initialization of global interrupt modes,
1846 but it does not actually enable global interrupts. To enable
1847 and disable global interrupts use functions sEnGlobalInt() and
1848 sDisGlobalInt(). Enabling of global interrupts is normally not
1849 done until all other initializations are complete.
1850
1851 Even if interrupts are globally enabled, they must also be
1852 individually enabled for each channel that is to generate
1853 interrupts.
1854
1855Warnings: No range checking on any of the parameters is done.
1856
1857 No context switches are allowed while executing this function.
1858
1859 After this function all AIOPs on the controller are disabled,
1860 they can be enabled with sEnAiop().
1861*/
1862static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1863 ByteIO_t * AiopIOList, int AiopIOListSize,
1864 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1865 int PeriodicOnly, int altChanRingIndicator,
1866 int UPCIRingInd)
1867{
1868 int i;
1869 ByteIO_t io;
1870
1871 CtlP->AltChanRingIndicator = altChanRingIndicator;
1872 CtlP->UPCIRingInd = UPCIRingInd;
1873 CtlP->CtlNum = CtlNum;
1874 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1875 CtlP->BusType = isPCI; /* controller release 1 */
1876
1877 if (ConfigIO) {
1878 CtlP->isUPCI = 1;
1879 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1880 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1881 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1882 } else {
1883 CtlP->isUPCI = 0;
1884 CtlP->PCIIO =
1885 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1886 CtlP->AiopIntrBits = aiop_intr_bits;
1887 }
1888
1889 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1890 /* Init AIOPs */
1891 CtlP->NumAiop = 0;
1892 for (i = 0; i < AiopIOListSize; i++) {
1893 io = AiopIOList[i];
1894 CtlP->AiopIO[i] = (WordIO_t) io;
1895 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1896
1897 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1898 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1899 break; /* done looking for AIOPs */
1900
1901 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1902 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1903 sOutB(io + _INDX_DATA, sClockPrescale);
1904 CtlP->NumAiop++; /* bump count of AIOPs */
1905 }
1906
1907 if (CtlP->NumAiop == 0)
1908 return (-1);
1909 else
1910 return (CtlP->NumAiop);
1911}
1912
1913/*
1914 * Called when a PCI card is found. Retrieves and stores model information,
1915 * init's aiopic and serial port hardware.
1916 * Inputs: i is the board number (0-n)
1917 */
1918static __init int register_PCI(int i, struct pci_dev *dev)
1919{
1920 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1921 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1922 CONTROLLER_t *ctlp;
1923
1924 int fast_clock = 0;
1925 int altChanRingIndicator = 0;
1926 int ports_per_aiop = 8;
1927 WordIO_t ConfigIO = 0;
1928 ByteIO_t UPCIRingInd = 0;
1929
1930 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1931 pci_enable_device(dev))
1932 return 0;
1933
1934 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1935
1936 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1937 rocketModel[i].loadrm2 = 0;
1938 rocketModel[i].startingPortNumber = nextLineNumber;
1939
1940 /* Depending on the model, set up some config variables */
1941 switch (dev->device) {
1942 case PCI_DEVICE_ID_RP4QUAD:
1943 max_num_aiops = 1;
1944 ports_per_aiop = 4;
1945 rocketModel[i].model = MODEL_RP4QUAD;
1946 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1947 rocketModel[i].numPorts = 4;
1948 break;
1949 case PCI_DEVICE_ID_RP8OCTA:
1950 max_num_aiops = 1;
1951 rocketModel[i].model = MODEL_RP8OCTA;
1952 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1953 rocketModel[i].numPorts = 8;
1954 break;
1955 case PCI_DEVICE_ID_URP8OCTA:
1956 max_num_aiops = 1;
1957 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1958 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1959 rocketModel[i].numPorts = 8;
1960 break;
1961 case PCI_DEVICE_ID_RP8INTF:
1962 max_num_aiops = 1;
1963 rocketModel[i].model = MODEL_RP8INTF;
1964 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1965 rocketModel[i].numPorts = 8;
1966 break;
1967 case PCI_DEVICE_ID_URP8INTF:
1968 max_num_aiops = 1;
1969 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1970 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1971 rocketModel[i].numPorts = 8;
1972 break;
1973 case PCI_DEVICE_ID_RP8J:
1974 max_num_aiops = 1;
1975 rocketModel[i].model = MODEL_RP8J;
1976 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1977 rocketModel[i].numPorts = 8;
1978 break;
1979 case PCI_DEVICE_ID_RP4J:
1980 max_num_aiops = 1;
1981 ports_per_aiop = 4;
1982 rocketModel[i].model = MODEL_RP4J;
1983 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1984 rocketModel[i].numPorts = 4;
1985 break;
1986 case PCI_DEVICE_ID_RP8SNI:
1987 max_num_aiops = 1;
1988 rocketModel[i].model = MODEL_RP8SNI;
1989 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1990 rocketModel[i].numPorts = 8;
1991 break;
1992 case PCI_DEVICE_ID_RP16SNI:
1993 max_num_aiops = 2;
1994 rocketModel[i].model = MODEL_RP16SNI;
1995 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1996 rocketModel[i].numPorts = 16;
1997 break;
1998 case PCI_DEVICE_ID_RP16INTF:
1999 max_num_aiops = 2;
2000 rocketModel[i].model = MODEL_RP16INTF;
2001 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
2002 rocketModel[i].numPorts = 16;
2003 break;
2004 case PCI_DEVICE_ID_URP16INTF:
2005 max_num_aiops = 2;
2006 rocketModel[i].model = MODEL_UPCI_RP16INTF;
2007 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
2008 rocketModel[i].numPorts = 16;
2009 break;
2010 case PCI_DEVICE_ID_CRP16INTF:
2011 max_num_aiops = 2;
2012 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2013 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2014 rocketModel[i].numPorts = 16;
2015 break;
2016 case PCI_DEVICE_ID_RP32INTF:
2017 max_num_aiops = 4;
2018 rocketModel[i].model = MODEL_RP32INTF;
2019 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2020 rocketModel[i].numPorts = 32;
2021 break;
2022 case PCI_DEVICE_ID_URP32INTF:
2023 max_num_aiops = 4;
2024 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2025 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2026 rocketModel[i].numPorts = 32;
2027 break;
2028 case PCI_DEVICE_ID_RPP4:
2029 max_num_aiops = 1;
2030 ports_per_aiop = 4;
2031 altChanRingIndicator++;
2032 fast_clock++;
2033 rocketModel[i].model = MODEL_RPP4;
2034 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2035 rocketModel[i].numPorts = 4;
2036 break;
2037 case PCI_DEVICE_ID_RPP8:
2038 max_num_aiops = 2;
2039 ports_per_aiop = 4;
2040 altChanRingIndicator++;
2041 fast_clock++;
2042 rocketModel[i].model = MODEL_RPP8;
2043 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2044 rocketModel[i].numPorts = 8;
2045 break;
2046 case PCI_DEVICE_ID_RP2_232:
2047 max_num_aiops = 1;
2048 ports_per_aiop = 2;
2049 altChanRingIndicator++;
2050 fast_clock++;
2051 rocketModel[i].model = MODEL_RP2_232;
2052 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2053 rocketModel[i].numPorts = 2;
2054 break;
2055 case PCI_DEVICE_ID_RP2_422:
2056 max_num_aiops = 1;
2057 ports_per_aiop = 2;
2058 altChanRingIndicator++;
2059 fast_clock++;
2060 rocketModel[i].model = MODEL_RP2_422;
2061 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2062 rocketModel[i].numPorts = 2;
2063 break;
2064 case PCI_DEVICE_ID_RP6M:
2065
2066 max_num_aiops = 1;
2067 ports_per_aiop = 6;
2068
2069 /* If revision is 1, the rocketmodem flash must be loaded.
2070 * If it is 2 it is a "socketed" version. */
2071 if (dev->revision == 1) {
2072 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2073 rocketModel[i].loadrm2 = 1;
2074 } else {
2075 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2076 }
2077
2078 rocketModel[i].model = MODEL_RP6M;
2079 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2080 rocketModel[i].numPorts = 6;
2081 break;
2082 case PCI_DEVICE_ID_RP4M:
2083 max_num_aiops = 1;
2084 ports_per_aiop = 4;
2085 if (dev->revision == 1) {
2086 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2087 rocketModel[i].loadrm2 = 1;
2088 } else {
2089 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2090 }
2091
2092 rocketModel[i].model = MODEL_RP4M;
2093 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2094 rocketModel[i].numPorts = 4;
2095 break;
2096 default:
2097 max_num_aiops = 0;
2098 break;
2099 }
2100
2101 /*
2102 * Check for UPCI boards.
2103 */
2104
2105 switch (dev->device) {
2106 case PCI_DEVICE_ID_URP32INTF:
2107 case PCI_DEVICE_ID_URP8INTF:
2108 case PCI_DEVICE_ID_URP16INTF:
2109 case PCI_DEVICE_ID_CRP16INTF:
2110 case PCI_DEVICE_ID_URP8OCTA:
2111 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2112 ConfigIO = pci_resource_start(dev, 1);
2113 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2114 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2115
2116 /*
2117 * Check for octa or quad cable.
2118 */
2119 if (!
2120 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2121 PCI_GPIO_CTRL_8PORT)) {
2122 ports_per_aiop = 4;
2123 rocketModel[i].numPorts = 4;
2124 }
2125 }
2126 break;
2127 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2128 max_num_aiops = 1;
2129 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2130 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2131 rocketModel[i].numPorts = 8;
2132 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2133 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2134 ConfigIO = pci_resource_start(dev, 1);
2135 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2136 break;
2137 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2138 max_num_aiops = 1;
2139 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2140 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2141 rocketModel[i].numPorts = 4;
2142 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2143 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2144 ConfigIO = pci_resource_start(dev, 1);
2145 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2146 break;
2147 default:
2148 break;
2149 }
2150
2151 if (fast_clock) {
2152 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2153 rp_baud_base[i] = 921600;
2154 } else {
2155 /*
2156 * If support_low_speed is set, use the slow clock
2157 * prescale, which supports 50 bps
2158 */
2159 if (support_low_speed) {
2160 /* mod 9 (divide by 10) prescale */
2161 sClockPrescale = 0x19;
2162 rp_baud_base[i] = 230400;
2163 } else {
2164 /* mod 4 (divide by 5) prescale */
2165 sClockPrescale = 0x14;
2166 rp_baud_base[i] = 460800;
2167 }
2168 }
2169
2170 for (aiop = 0; aiop < max_num_aiops; aiop++)
2171 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2172 ctlp = sCtlNumToCtlPtr(i);
2173 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2174 for (aiop = 0; aiop < max_num_aiops; aiop++)
2175 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2176
2177 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2178 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2179 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2180 rocketModel[i].startingPortNumber,
2181 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2182
2183 if (num_aiops <= 0) {
2184 rcktpt_io_addr[i] = 0;
2185 return (0);
2186 }
2187 is_PCI[i] = 1;
2188
2189 /* Reset the AIOPIC, init the serial ports */
2190 for (aiop = 0; aiop < num_aiops; aiop++) {
2191 sResetAiopByNum(ctlp, aiop);
2192 num_chan = ports_per_aiop;
2193 for (chan = 0; chan < num_chan; chan++)
2194 init_r_port(i, aiop, chan, dev);
2195 }
2196
2197 /* Rocket modems must be reset */
2198 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2199 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2200 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2201 num_chan = ports_per_aiop;
2202 for (chan = 0; chan < num_chan; chan++)
2203 sPCIModemReset(ctlp, chan, 1);
2204 msleep(500);
2205 for (chan = 0; chan < num_chan; chan++)
2206 sPCIModemReset(ctlp, chan, 0);
2207 msleep(500);
2208 rmSpeakerReset(ctlp, rocketModel[i].model);
2209 }
2210 return (1);
2211}
2212
2213/*
2214 * Probes for PCI cards, inits them if found
2215 * Input: board_found = number of ISA boards already found, or the
2216 * starting board number
2217 * Returns: Number of PCI boards found
2218 */
2219static int __init init_PCI(int boards_found)
2220{
2221 struct pci_dev *dev = NULL;
2222 int count = 0;
2223
2224 /* Work through the PCI device list, pulling out ours */
2225 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2226 if (register_PCI(count + boards_found, dev))
2227 count++;
2228 }
2229 return (count);
2230}
2231
2232#endif /* CONFIG_PCI */
2233
2234/*
2235 * Probes for ISA cards
2236 * Input: i = the board number to look for
2237 * Returns: 1 if board found, 0 else
2238 */
2239static int __init init_ISA(int i)
2240{
2241 int num_aiops, num_chan = 0, total_num_chan = 0;
2242 int aiop, chan;
2243 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2244 CONTROLLER_t *ctlp;
2245 char *type_string;
2246
2247 /* If io_addr is zero, no board configured */
2248 if (rcktpt_io_addr[i] == 0)
2249 return (0);
2250
2251 /* Reserve the IO region */
2252 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2253 printk(KERN_ERR "Unable to reserve IO region for configured "
2254 "ISA RocketPort at address 0x%lx, board not "
2255 "installed...\n", rcktpt_io_addr[i]);
2256 rcktpt_io_addr[i] = 0;
2257 return (0);
2258 }
2259
2260 ctlp = sCtlNumToCtlPtr(i);
2261
2262 ctlp->boardType = rcktpt_type[i];
2263
2264 switch (rcktpt_type[i]) {
2265 case ROCKET_TYPE_PC104:
2266 type_string = "(PC104)";
2267 break;
2268 case ROCKET_TYPE_MODEM:
2269 type_string = "(RocketModem)";
2270 break;
2271 case ROCKET_TYPE_MODEMII:
2272 type_string = "(RocketModem II)";
2273 break;
2274 default:
2275 type_string = "";
2276 break;
2277 }
2278
2279 /*
2280 * If support_low_speed is set, use the slow clock prescale,
2281 * which supports 50 bps
2282 */
2283 if (support_low_speed) {
2284 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2285 rp_baud_base[i] = 230400;
2286 } else {
2287 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2288 rp_baud_base[i] = 460800;
2289 }
2290
2291 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2292 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2293
2294 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2295
2296 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2297 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2298 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2299 }
2300
2301 /* If something went wrong initing the AIOP's release the ISA IO memory */
2302 if (num_aiops <= 0) {
2303 release_region(rcktpt_io_addr[i], 64);
2304 rcktpt_io_addr[i] = 0;
2305 return (0);
2306 }
2307
2308 rocketModel[i].startingPortNumber = nextLineNumber;
2309
2310 for (aiop = 0; aiop < num_aiops; aiop++) {
2311 sResetAiopByNum(ctlp, aiop);
2312 sEnAiop(ctlp, aiop);
2313 num_chan = sGetAiopNumChan(ctlp, aiop);
2314 total_num_chan += num_chan;
2315 for (chan = 0; chan < num_chan; chan++)
2316 init_r_port(i, aiop, chan, NULL);
2317 }
2318 is_PCI[i] = 0;
2319 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2320 num_chan = sGetAiopNumChan(ctlp, 0);
2321 total_num_chan = num_chan;
2322 for (chan = 0; chan < num_chan; chan++)
2323 sModemReset(ctlp, chan, 1);
2324 msleep(500);
2325 for (chan = 0; chan < num_chan; chan++)
2326 sModemReset(ctlp, chan, 0);
2327 msleep(500);
2328 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2329 } else {
2330 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2331 }
2332 rocketModel[i].numPorts = total_num_chan;
2333 rocketModel[i].model = MODEL_ISA;
2334
2335 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2336 i, rcktpt_io_addr[i], num_aiops, type_string);
2337
2338 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2339 rocketModel[i].modelString,
2340 rocketModel[i].startingPortNumber,
2341 rocketModel[i].startingPortNumber +
2342 rocketModel[i].numPorts - 1);
2343
2344 return (1);
2345}
2346
2347static const struct tty_operations rocket_ops = {
2348 .open = rp_open,
2349 .close = rp_close,
2350 .write = rp_write,
2351 .put_char = rp_put_char,
2352 .write_room = rp_write_room,
2353 .chars_in_buffer = rp_chars_in_buffer,
2354 .flush_buffer = rp_flush_buffer,
2355 .ioctl = rp_ioctl,
2356 .throttle = rp_throttle,
2357 .unthrottle = rp_unthrottle,
2358 .set_termios = rp_set_termios,
2359 .stop = rp_stop,
2360 .start = rp_start,
2361 .hangup = rp_hangup,
2362 .break_ctl = rp_break,
2363 .send_xchar = rp_send_xchar,
2364 .wait_until_sent = rp_wait_until_sent,
2365 .tiocmget = rp_tiocmget,
2366 .tiocmset = rp_tiocmset,
2367};
2368
2369static const struct tty_port_operations rocket_port_ops = {
2370 .carrier_raised = carrier_raised,
2371 .dtr_rts = dtr_rts,
2372};
2373
2374/*
2375 * The module "startup" routine; it's run when the module is loaded.
2376 */
2377static int __init rp_init(void)
2378{
2379 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2380
2381 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2382 ROCKET_VERSION, ROCKET_DATE);
2383
2384 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2385 if (!rocket_driver)
2386 goto err;
2387
2388 /*
2389 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2390 * zero, use the default controller IO address of board1 + 0x40.
2391 */
2392 if (board1) {
2393 if (controller == 0)
2394 controller = board1 + 0x40;
2395 } else {
2396 controller = 0; /* Used as a flag, meaning no ISA boards */
2397 }
2398
2399 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2400 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2401 printk(KERN_ERR "Unable to reserve IO region for first "
2402 "configured ISA RocketPort controller 0x%lx. "
2403 "Driver exiting\n", controller);
2404 ret = -EBUSY;
2405 goto err_tty;
2406 }
2407
2408 /* Store ISA variable retrieved from command line or .conf file. */
2409 rcktpt_io_addr[0] = board1;
2410 rcktpt_io_addr[1] = board2;
2411 rcktpt_io_addr[2] = board3;
2412 rcktpt_io_addr[3] = board4;
2413
2414 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2415 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2416 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2417 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2418 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2419 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2420 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2421 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2422
2423 /*
2424 * Set up the tty driver structure and then register this
2425 * driver with the tty layer.
2426 */
2427
2428 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2429 rocket_driver->name = "ttyR";
2430 rocket_driver->driver_name = "Comtrol RocketPort";
2431 rocket_driver->major = TTY_ROCKET_MAJOR;
2432 rocket_driver->minor_start = 0;
2433 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2434 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2435 rocket_driver->init_termios = tty_std_termios;
2436 rocket_driver->init_termios.c_cflag =
2437 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2438 rocket_driver->init_termios.c_ispeed = 9600;
2439 rocket_driver->init_termios.c_ospeed = 9600;
2440#ifdef ROCKET_SOFT_FLOW
2441 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2442#endif
2443 tty_set_operations(rocket_driver, &rocket_ops);
2444
2445 ret = tty_register_driver(rocket_driver);
2446 if (ret < 0) {
2447 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2448 goto err_controller;
2449 }
2450
2451#ifdef ROCKET_DEBUG_OPEN
2452 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2453#endif
2454
2455 /*
2456 * OK, let's probe each of the controllers looking for boards. Any boards found
2457 * will be initialized here.
2458 */
2459 isa_boards_found = 0;
2460 pci_boards_found = 0;
2461
2462 for (i = 0; i < NUM_BOARDS; i++) {
2463 if (init_ISA(i))
2464 isa_boards_found++;
2465 }
2466
2467#ifdef CONFIG_PCI
2468 if (isa_boards_found < NUM_BOARDS)
2469 pci_boards_found = init_PCI(isa_boards_found);
2470#endif
2471
2472 max_board = pci_boards_found + isa_boards_found;
2473
2474 if (max_board == 0) {
2475 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2476 ret = -ENXIO;
2477 goto err_ttyu;
2478 }
2479
2480 return 0;
2481err_ttyu:
2482 tty_unregister_driver(rocket_driver);
2483err_controller:
2484 if (controller)
2485 release_region(controller, 4);
2486err_tty:
2487 put_tty_driver(rocket_driver);
2488err:
2489 return ret;
2490}
2491
2492
2493static void rp_cleanup_module(void)
2494{
2495 int retval;
2496 int i;
2497
2498 del_timer_sync(&rocket_timer);
2499
2500 retval = tty_unregister_driver(rocket_driver);
2501 if (retval)
2502 printk(KERN_ERR "Error %d while trying to unregister "
2503 "rocketport driver\n", -retval);
2504
2505 for (i = 0; i < MAX_RP_PORTS; i++)
2506 if (rp_table[i]) {
2507 tty_unregister_device(rocket_driver, i);
2508 tty_port_destroy(&rp_table[i]->port);
2509 kfree(rp_table[i]);
2510 }
2511
2512 put_tty_driver(rocket_driver);
2513
2514 for (i = 0; i < NUM_BOARDS; i++) {
2515 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2516 continue;
2517 release_region(rcktpt_io_addr[i], 64);
2518 }
2519 if (controller)
2520 release_region(controller, 4);
2521}
2522
2523/***************************************************************************
2524Function: sInitController
2525Purpose: Initialization of controller global registers and controller
2526 structure.
2527Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2528 IRQNum,Frequency,PeriodicOnly)
2529 CONTROLLER_T *CtlP; Ptr to controller structure
2530 int CtlNum; Controller number
2531 ByteIO_t MudbacIO; Mudbac base I/O address.
2532 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2533 This list must be in the order the AIOPs will be found on the
2534 controller. Once an AIOP in the list is not found, it is
2535 assumed that there are no more AIOPs on the controller.
2536 int AiopIOListSize; Number of addresses in AiopIOList
2537 int IRQNum; Interrupt Request number. Can be any of the following:
2538 0: Disable global interrupts
2539 3: IRQ 3
2540 4: IRQ 4
2541 5: IRQ 5
2542 9: IRQ 9
2543 10: IRQ 10
2544 11: IRQ 11
2545 12: IRQ 12
2546 15: IRQ 15
2547 Byte_t Frequency: A flag identifying the frequency
2548 of the periodic interrupt, can be any one of the following:
2549 FREQ_DIS - periodic interrupt disabled
2550 FREQ_137HZ - 137 Hertz
2551 FREQ_69HZ - 69 Hertz
2552 FREQ_34HZ - 34 Hertz
2553 FREQ_17HZ - 17 Hertz
2554 FREQ_9HZ - 9 Hertz
2555 FREQ_4HZ - 4 Hertz
2556 If IRQNum is set to 0 the Frequency parameter is
2557 overidden, it is forced to a value of FREQ_DIS.
2558 int PeriodicOnly: 1 if all interrupts except the periodic
2559 interrupt are to be blocked.
2560 0 is both the periodic interrupt and
2561 other channel interrupts are allowed.
2562 If IRQNum is set to 0 the PeriodicOnly parameter is
2563 overidden, it is forced to a value of 0.
2564Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2565 initialization failed.
2566
2567Comments:
2568 If periodic interrupts are to be disabled but AIOP interrupts
2569 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2570
2571 If interrupts are to be completely disabled set IRQNum to 0.
2572
2573 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2574 invalid combination.
2575
2576 This function performs initialization of global interrupt modes,
2577 but it does not actually enable global interrupts. To enable
2578 and disable global interrupts use functions sEnGlobalInt() and
2579 sDisGlobalInt(). Enabling of global interrupts is normally not
2580 done until all other initializations are complete.
2581
2582 Even if interrupts are globally enabled, they must also be
2583 individually enabled for each channel that is to generate
2584 interrupts.
2585
2586Warnings: No range checking on any of the parameters is done.
2587
2588 No context switches are allowed while executing this function.
2589
2590 After this function all AIOPs on the controller are disabled,
2591 they can be enabled with sEnAiop().
2592*/
2593static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2594 ByteIO_t * AiopIOList, int AiopIOListSize,
2595 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2596{
2597 int i;
2598 ByteIO_t io;
2599 int done;
2600
2601 CtlP->AiopIntrBits = aiop_intr_bits;
2602 CtlP->AltChanRingIndicator = 0;
2603 CtlP->CtlNum = CtlNum;
2604 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2605 CtlP->BusType = isISA;
2606 CtlP->MBaseIO = MudbacIO;
2607 CtlP->MReg1IO = MudbacIO + 1;
2608 CtlP->MReg2IO = MudbacIO + 2;
2609 CtlP->MReg3IO = MudbacIO + 3;
2610#if 1
2611 CtlP->MReg2 = 0; /* interrupt disable */
2612 CtlP->MReg3 = 0; /* no periodic interrupts */
2613#else
2614 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2615 CtlP->MReg2 = 0; /* interrupt disable */
2616 CtlP->MReg3 = 0; /* no periodic interrupts */
2617 } else {
2618 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2619 CtlP->MReg3 = Frequency; /* set frequency */
2620 if (PeriodicOnly) { /* periodic interrupt only */
2621 CtlP->MReg3 |= PERIODIC_ONLY;
2622 }
2623 }
2624#endif
2625 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2626 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2627 sControllerEOI(CtlP); /* clear EOI if warm init */
2628 /* Init AIOPs */
2629 CtlP->NumAiop = 0;
2630 for (i = done = 0; i < AiopIOListSize; i++) {
2631 io = AiopIOList[i];
2632 CtlP->AiopIO[i] = (WordIO_t) io;
2633 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2634 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2635 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2636 if (done)
2637 continue;
2638 sEnAiop(CtlP, i); /* enable the AIOP */
2639 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2640 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2641 done = 1; /* done looking for AIOPs */
2642 else {
2643 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2644 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2645 sOutB(io + _INDX_DATA, sClockPrescale);
2646 CtlP->NumAiop++; /* bump count of AIOPs */
2647 }
2648 sDisAiop(CtlP, i); /* disable AIOP */
2649 }
2650
2651 if (CtlP->NumAiop == 0)
2652 return (-1);
2653 else
2654 return (CtlP->NumAiop);
2655}
2656
2657/***************************************************************************
2658Function: sReadAiopID
2659Purpose: Read the AIOP idenfication number directly from an AIOP.
2660Call: sReadAiopID(io)
2661 ByteIO_t io: AIOP base I/O address
2662Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2663 is replace by an identifying number.
2664 Flag AIOPID_NULL if no valid AIOP is found
2665Warnings: No context switches are allowed while executing this function.
2666
2667*/
2668static int sReadAiopID(ByteIO_t io)
2669{
2670 Byte_t AiopID; /* ID byte from AIOP */
2671
2672 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2673 sOutB(io + _CMD_REG, 0x0);
2674 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2675 if (AiopID == 0x06)
2676 return (1);
2677 else /* AIOP does not exist */
2678 return (-1);
2679}
2680
2681/***************************************************************************
2682Function: sReadAiopNumChan
2683Purpose: Read the number of channels available in an AIOP directly from
2684 an AIOP.
2685Call: sReadAiopNumChan(io)
2686 WordIO_t io: AIOP base I/O address
2687Return: int: The number of channels available
2688Comments: The number of channels is determined by write/reads from identical
2689 offsets within the SRAM address spaces for channels 0 and 4.
2690 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2691 AIOP, otherwise it is an 8 channel.
2692Warnings: No context switches are allowed while executing this function.
2693*/
2694static int sReadAiopNumChan(WordIO_t io)
2695{
2696 Word_t x;
2697 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2698
2699 /* write to chan 0 SRAM */
2700 out32((DWordIO_t) io + _INDX_ADDR, R);
2701 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2702 x = sInW(io + _INDX_DATA);
2703 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2704 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2705 return (8);
2706 else
2707 return (4);
2708}
2709
2710/***************************************************************************
2711Function: sInitChan
2712Purpose: Initialization of a channel and channel structure
2713Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2714 CONTROLLER_T *CtlP; Ptr to controller structure
2715 CHANNEL_T *ChP; Ptr to channel structure
2716 int AiopNum; AIOP number within controller
2717 int ChanNum; Channel number within AIOP
2718Return: int: 1 if initialization succeeded, 0 if it fails because channel
2719 number exceeds number of channels available in AIOP.
2720Comments: This function must be called before a channel can be used.
2721Warnings: No range checking on any of the parameters is done.
2722
2723 No context switches are allowed while executing this function.
2724*/
2725static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2726 int ChanNum)
2727{
2728 int i;
2729 WordIO_t AiopIO;
2730 WordIO_t ChIOOff;
2731 Byte_t *ChR;
2732 Word_t ChOff;
2733 static Byte_t R[4];
2734 int brd9600;
2735
2736 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2737 return 0; /* exceeds num chans in AIOP */
2738
2739 /* Channel, AIOP, and controller identifiers */
2740 ChP->CtlP = CtlP;
2741 ChP->ChanID = CtlP->AiopID[AiopNum];
2742 ChP->AiopNum = AiopNum;
2743 ChP->ChanNum = ChanNum;
2744
2745 /* Global direct addresses */
2746 AiopIO = CtlP->AiopIO[AiopNum];
2747 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2748 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2749 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2750 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2751 ChP->IndexData = AiopIO + _INDX_DATA;
2752
2753 /* Channel direct addresses */
2754 ChIOOff = AiopIO + ChP->ChanNum * 2;
2755 ChP->TxRxData = ChIOOff + _TD0;
2756 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2757 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2758 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2759
2760 /* Initialize the channel from the RData array */
2761 for (i = 0; i < RDATASIZE; i += 4) {
2762 R[0] = RData[i];
2763 R[1] = RData[i + 1] + 0x10 * ChanNum;
2764 R[2] = RData[i + 2];
2765 R[3] = RData[i + 3];
2766 out32(ChP->IndexAddr, R);
2767 }
2768
2769 ChR = ChP->R;
2770 for (i = 0; i < RREGDATASIZE; i += 4) {
2771 ChR[i] = RRegData[i];
2772 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2773 ChR[i + 2] = RRegData[i + 2];
2774 ChR[i + 3] = RRegData[i + 3];
2775 }
2776
2777 /* Indexed registers */
2778 ChOff = (Word_t) ChanNum *0x1000;
2779
2780 if (sClockPrescale == 0x14)
2781 brd9600 = 47;
2782 else
2783 brd9600 = 23;
2784
2785 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2786 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2787 ChP->BaudDiv[2] = (Byte_t) brd9600;
2788 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2789 out32(ChP->IndexAddr, ChP->BaudDiv);
2790
2791 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2792 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2793 ChP->TxControl[2] = 0;
2794 ChP->TxControl[3] = 0;
2795 out32(ChP->IndexAddr, ChP->TxControl);
2796
2797 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2798 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2799 ChP->RxControl[2] = 0;
2800 ChP->RxControl[3] = 0;
2801 out32(ChP->IndexAddr, ChP->RxControl);
2802
2803 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2804 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2805 ChP->TxEnables[2] = 0;
2806 ChP->TxEnables[3] = 0;
2807 out32(ChP->IndexAddr, ChP->TxEnables);
2808
2809 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2810 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2811 ChP->TxCompare[2] = 0;
2812 ChP->TxCompare[3] = 0;
2813 out32(ChP->IndexAddr, ChP->TxCompare);
2814
2815 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2816 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2817 ChP->TxReplace1[2] = 0;
2818 ChP->TxReplace1[3] = 0;
2819 out32(ChP->IndexAddr, ChP->TxReplace1);
2820
2821 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2822 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2823 ChP->TxReplace2[2] = 0;
2824 ChP->TxReplace2[3] = 0;
2825 out32(ChP->IndexAddr, ChP->TxReplace2);
2826
2827 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2828 ChP->TxFIFO = ChOff + _TX_FIFO;
2829
2830 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2831 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2832 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2833 sOutW(ChP->IndexData, 0);
2834 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2835 ChP->RxFIFO = ChOff + _RX_FIFO;
2836
2837 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2838 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2839 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2840 sOutW(ChP->IndexData, 0);
2841 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2842 sOutW(ChP->IndexData, 0);
2843 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2844 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2845 sOutB(ChP->IndexData, 0);
2846 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2847 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2848 sOutB(ChP->IndexData, 0);
2849 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2850 sEnRxProcessor(ChP); /* start the Rx processor */
2851
2852 return 1;
2853}
2854
2855/***************************************************************************
2856Function: sStopRxProcessor
2857Purpose: Stop the receive processor from processing a channel.
2858Call: sStopRxProcessor(ChP)
2859 CHANNEL_T *ChP; Ptr to channel structure
2860
2861Comments: The receive processor can be started again with sStartRxProcessor().
2862 This function causes the receive processor to skip over the
2863 stopped channel. It does not stop it from processing other channels.
2864
2865Warnings: No context switches are allowed while executing this function.
2866
2867 Do not leave the receive processor stopped for more than one
2868 character time.
2869
2870 After calling this function a delay of 4 uS is required to ensure
2871 that the receive processor is no longer processing this channel.
2872*/
2873static void sStopRxProcessor(CHANNEL_T * ChP)
2874{
2875 Byte_t R[4];
2876
2877 R[0] = ChP->R[0];
2878 R[1] = ChP->R[1];
2879 R[2] = 0x0a;
2880 R[3] = ChP->R[3];
2881 out32(ChP->IndexAddr, R);
2882}
2883
2884/***************************************************************************
2885Function: sFlushRxFIFO
2886Purpose: Flush the Rx FIFO
2887Call: sFlushRxFIFO(ChP)
2888 CHANNEL_T *ChP; Ptr to channel structure
2889Return: void
2890Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2891 while it is being flushed the receive processor is stopped
2892 and the transmitter is disabled. After these operations a
2893 4 uS delay is done before clearing the pointers to allow
2894 the receive processor to stop. These items are handled inside
2895 this function.
2896Warnings: No context switches are allowed while executing this function.
2897*/
2898static void sFlushRxFIFO(CHANNEL_T * ChP)
2899{
2900 int i;
2901 Byte_t Ch; /* channel number within AIOP */
2902 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2903
2904 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2905 return; /* don't need to flush */
2906
2907 RxFIFOEnabled = 0;
2908 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2909 RxFIFOEnabled = 1;
2910 sDisRxFIFO(ChP); /* disable it */
2911 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2912 sInB(ChP->IntChan); /* depends on bus i/o timing */
2913 }
2914 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2915 Ch = (Byte_t) sGetChanNum(ChP);
2916 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2917 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2918 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2919 sOutW(ChP->IndexData, 0);
2920 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2921 sOutW(ChP->IndexData, 0);
2922 if (RxFIFOEnabled)
2923 sEnRxFIFO(ChP); /* enable Rx FIFO */
2924}
2925
2926/***************************************************************************
2927Function: sFlushTxFIFO
2928Purpose: Flush the Tx FIFO
2929Call: sFlushTxFIFO(ChP)
2930 CHANNEL_T *ChP; Ptr to channel structure
2931Return: void
2932Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2933 while it is being flushed the receive processor is stopped
2934 and the transmitter is disabled. After these operations a
2935 4 uS delay is done before clearing the pointers to allow
2936 the receive processor to stop. These items are handled inside
2937 this function.
2938Warnings: No context switches are allowed while executing this function.
2939*/
2940static void sFlushTxFIFO(CHANNEL_T * ChP)
2941{
2942 int i;
2943 Byte_t Ch; /* channel number within AIOP */
2944 int TxEnabled; /* 1 if transmitter enabled */
2945
2946 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2947 return; /* don't need to flush */
2948
2949 TxEnabled = 0;
2950 if (ChP->TxControl[3] & TX_ENABLE) {
2951 TxEnabled = 1;
2952 sDisTransmit(ChP); /* disable transmitter */
2953 }
2954 sStopRxProcessor(ChP); /* stop Rx processor */
2955 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2956 sInB(ChP->IntChan); /* depends on bus i/o timing */
2957 Ch = (Byte_t) sGetChanNum(ChP);
2958 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2959 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2960 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2961 sOutW(ChP->IndexData, 0);
2962 if (TxEnabled)
2963 sEnTransmit(ChP); /* enable transmitter */
2964 sStartRxProcessor(ChP); /* restart Rx processor */
2965}
2966
2967/***************************************************************************
2968Function: sWriteTxPrioByte
2969Purpose: Write a byte of priority transmit data to a channel
2970Call: sWriteTxPrioByte(ChP,Data)
2971 CHANNEL_T *ChP; Ptr to channel structure
2972 Byte_t Data; The transmit data byte
2973
2974Return: int: 1 if the bytes is successfully written, otherwise 0.
2975
2976Comments: The priority byte is transmitted before any data in the Tx FIFO.
2977
2978Warnings: No context switches are allowed while executing this function.
2979*/
2980static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2981{
2982 Byte_t DWBuf[4]; /* buffer for double word writes */
2983 Word_t *WordPtr; /* must be far because Win SS != DS */
2984 register DWordIO_t IndexAddr;
2985
2986 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2987 IndexAddr = ChP->IndexAddr;
2988 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2989 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2990 return (0); /* nothing sent */
2991
2992 WordPtr = (Word_t *) (&DWBuf[0]);
2993 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2994
2995 DWBuf[2] = Data; /* data byte value */
2996 out32(IndexAddr, DWBuf); /* write it out */
2997
2998 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2999
3000 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3001 DWBuf[3] = 0; /* priority buffer pointer */
3002 out32(IndexAddr, DWBuf); /* write it out */
3003 } else { /* write it to Tx FIFO */
3004
3005 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3006 }
3007 return (1); /* 1 byte sent */
3008}
3009
3010/***************************************************************************
3011Function: sEnInterrupts
3012Purpose: Enable one or more interrupts for a channel
3013Call: sEnInterrupts(ChP,Flags)
3014 CHANNEL_T *ChP; Ptr to channel structure
3015 Word_t Flags: Interrupt enable flags, can be any combination
3016 of the following flags:
3017 TXINT_EN: Interrupt on Tx FIFO empty
3018 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3019 sSetRxTrigger())
3020 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3021 MCINT_EN: Interrupt on modem input change
3022 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3023 Interrupt Channel Register.
3024Return: void
3025Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3026 enabled. If an interrupt enable flag is not set in Flags, that
3027 interrupt will not be changed. Interrupts can be disabled with
3028 function sDisInterrupts().
3029
3030 This function sets the appropriate bit for the channel in the AIOP's
3031 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3032 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3033
3034 Interrupts must also be globally enabled before channel interrupts
3035 will be passed on to the host. This is done with function
3036 sEnGlobalInt().
3037
3038 In some cases it may be desirable to disable interrupts globally but
3039 enable channel interrupts. This would allow the global interrupt
3040 status register to be used to determine which AIOPs need service.
3041*/
3042static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3043{
3044 Byte_t Mask; /* Interrupt Mask Register */
3045
3046 ChP->RxControl[2] |=
3047 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3048
3049 out32(ChP->IndexAddr, ChP->RxControl);
3050
3051 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3052
3053 out32(ChP->IndexAddr, ChP->TxControl);
3054
3055 if (Flags & CHANINT_EN) {
3056 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3057 sOutB(ChP->IntMask, Mask);
3058 }
3059}
3060
3061/***************************************************************************
3062Function: sDisInterrupts
3063Purpose: Disable one or more interrupts for a channel
3064Call: sDisInterrupts(ChP,Flags)
3065 CHANNEL_T *ChP; Ptr to channel structure
3066 Word_t Flags: Interrupt flags, can be any combination
3067 of the following flags:
3068 TXINT_EN: Interrupt on Tx FIFO empty
3069 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3070 sSetRxTrigger())
3071 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3072 MCINT_EN: Interrupt on modem input change
3073 CHANINT_EN: Disable channel interrupt signal to the
3074 AIOP's Interrupt Channel Register.
3075Return: void
3076Comments: If an interrupt flag is set in Flags, that interrupt will be
3077 disabled. If an interrupt flag is not set in Flags, that
3078 interrupt will not be changed. Interrupts can be enabled with
3079 function sEnInterrupts().
3080
3081 This function clears the appropriate bit for the channel in the AIOP's
3082 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3083 this channel's bit from being set in the AIOP's Interrupt Channel
3084 Register.
3085*/
3086static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3087{
3088 Byte_t Mask; /* Interrupt Mask Register */
3089
3090 ChP->RxControl[2] &=
3091 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3092 out32(ChP->IndexAddr, ChP->RxControl);
3093 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3094 out32(ChP->IndexAddr, ChP->TxControl);
3095
3096 if (Flags & CHANINT_EN) {
3097 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3098 sOutB(ChP->IntMask, Mask);
3099 }
3100}
3101
3102static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3103{
3104 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3105}
3106
3107/*
3108 * Not an official SSCI function, but how to reset RocketModems.
3109 * ISA bus version
3110 */
3111static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3112{
3113 ByteIO_t addr;
3114 Byte_t val;
3115
3116 addr = CtlP->AiopIO[0] + 0x400;
3117 val = sInB(CtlP->MReg3IO);
3118 /* if AIOP[1] is not enabled, enable it */
3119 if ((val & 2) == 0) {
3120 val = sInB(CtlP->MReg2IO);
3121 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3122 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3123 }
3124
3125 sEnAiop(CtlP, 1);
3126 if (!on)
3127 addr += 8;
3128 sOutB(addr + chan, 0); /* apply or remove reset */
3129 sDisAiop(CtlP, 1);
3130}
3131
3132/*
3133 * Not an official SSCI function, but how to reset RocketModems.
3134 * PCI bus version
3135 */
3136static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3137{
3138 ByteIO_t addr;
3139
3140 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3141 if (!on)
3142 addr += 8;
3143 sOutB(addr + chan, 0); /* apply or remove reset */
3144}
3145
3146/* Returns the line number given the controller (board), aiop and channel number */
3147static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3148{
3149 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3150}
3151
3152/*
3153 * Stores the line number associated with a given controller (board), aiop
3154 * and channel number.
3155 * Returns: The line number assigned
3156 */
3157static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3158{
3159 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3160 return (nextLineNumber - 1);
3161}