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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OMAP2 McSPI controller driver
4 *
5 * Copyright (C) 2005, 2006 Nokia Corporation
6 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
7 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/platform_device.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/gcd.h>
27#include <linux/iopoll.h>
28
29#include <linux/spi/spi.h>
30
31#include <linux/platform_data/spi-omap2-mcspi.h>
32
33#define OMAP2_MCSPI_MAX_FREQ 48000000
34#define OMAP2_MCSPI_MAX_DIVIDER 4096
35#define OMAP2_MCSPI_MAX_FIFODEPTH 64
36#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
37#define SPI_AUTOSUSPEND_TIMEOUT 2000
38
39#define OMAP2_MCSPI_REVISION 0x00
40#define OMAP2_MCSPI_SYSSTATUS 0x14
41#define OMAP2_MCSPI_IRQSTATUS 0x18
42#define OMAP2_MCSPI_IRQENABLE 0x1c
43#define OMAP2_MCSPI_WAKEUPENABLE 0x20
44#define OMAP2_MCSPI_SYST 0x24
45#define OMAP2_MCSPI_MODULCTRL 0x28
46#define OMAP2_MCSPI_XFERLEVEL 0x7c
47
48/* per-channel banks, 0x14 bytes each, first is: */
49#define OMAP2_MCSPI_CHCONF0 0x2c
50#define OMAP2_MCSPI_CHSTAT0 0x30
51#define OMAP2_MCSPI_CHCTRL0 0x34
52#define OMAP2_MCSPI_TX0 0x38
53#define OMAP2_MCSPI_RX0 0x3c
54
55/* per-register bitmasks: */
56#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
57
58#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
59#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
60#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
61
62#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
63#define OMAP2_MCSPI_CHCONF_POL BIT(1)
64#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
65#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
66#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
67#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
68#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
69#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
70#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
71#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
72#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
73#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
74#define OMAP2_MCSPI_CHCONF_IS BIT(18)
75#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
76#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
77#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
78#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
79#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
80
81#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
82#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
83#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
84#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
85
86#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
87#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
88
89#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
90
91/* We have 2 DMA channels per CS, one for RX and one for TX */
92struct omap2_mcspi_dma {
93 struct dma_chan *dma_tx;
94 struct dma_chan *dma_rx;
95
96 struct completion dma_tx_completion;
97 struct completion dma_rx_completion;
98
99 char dma_rx_ch_name[14];
100 char dma_tx_ch_name[14];
101};
102
103/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
104 * cache operations; better heuristics consider wordsize and bitrate.
105 */
106#define DMA_MIN_BYTES 160
107
108
109/*
110 * Used for context save and restore, structure members to be updated whenever
111 * corresponding registers are modified.
112 */
113struct omap2_mcspi_regs {
114 u32 modulctrl;
115 u32 wakeupenable;
116 struct list_head cs;
117};
118
119struct omap2_mcspi {
120 struct completion txdone;
121 struct spi_master *master;
122 /* Virtual base address of the controller */
123 void __iomem *base;
124 unsigned long phys;
125 /* SPI1 has 4 channels, while SPI2 has 2 */
126 struct omap2_mcspi_dma *dma_channels;
127 struct device *dev;
128 struct omap2_mcspi_regs ctx;
129 int fifo_depth;
130 bool slave_aborted;
131 unsigned int pin_dir:1;
132 size_t max_xfer_len;
133};
134
135struct omap2_mcspi_cs {
136 void __iomem *base;
137 unsigned long phys;
138 int word_len;
139 u16 mode;
140 struct list_head node;
141 /* Context save and restore shadow register */
142 u32 chconf0, chctrl0;
143};
144
145static inline void mcspi_write_reg(struct spi_master *master,
146 int idx, u32 val)
147{
148 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
149
150 writel_relaxed(val, mcspi->base + idx);
151}
152
153static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
154{
155 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156
157 return readl_relaxed(mcspi->base + idx);
158}
159
160static inline void mcspi_write_cs_reg(const struct spi_device *spi,
161 int idx, u32 val)
162{
163 struct omap2_mcspi_cs *cs = spi->controller_state;
164
165 writel_relaxed(val, cs->base + idx);
166}
167
168static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169{
170 struct omap2_mcspi_cs *cs = spi->controller_state;
171
172 return readl_relaxed(cs->base + idx);
173}
174
175static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176{
177 struct omap2_mcspi_cs *cs = spi->controller_state;
178
179 return cs->chconf0;
180}
181
182static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183{
184 struct omap2_mcspi_cs *cs = spi->controller_state;
185
186 cs->chconf0 = val;
187 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
188 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
189}
190
191static inline int mcspi_bytes_per_word(int word_len)
192{
193 if (word_len <= 8)
194 return 1;
195 else if (word_len <= 16)
196 return 2;
197 else /* word_len <= 32 */
198 return 4;
199}
200
201static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
202 int is_read, int enable)
203{
204 u32 l, rw;
205
206 l = mcspi_cached_chconf0(spi);
207
208 if (is_read) /* 1 is read, 0 write */
209 rw = OMAP2_MCSPI_CHCONF_DMAR;
210 else
211 rw = OMAP2_MCSPI_CHCONF_DMAW;
212
213 if (enable)
214 l |= rw;
215 else
216 l &= ~rw;
217
218 mcspi_write_chconf0(spi, l);
219}
220
221static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
222{
223 struct omap2_mcspi_cs *cs = spi->controller_state;
224 u32 l;
225
226 l = cs->chctrl0;
227 if (enable)
228 l |= OMAP2_MCSPI_CHCTRL_EN;
229 else
230 l &= ~OMAP2_MCSPI_CHCTRL_EN;
231 cs->chctrl0 = l;
232 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
233 /* Flash post-writes */
234 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
235}
236
237static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
238{
239 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
240 u32 l;
241
242 /* The controller handles the inverted chip selects
243 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
244 * the inversion from the core spi_set_cs function.
245 */
246 if (spi->mode & SPI_CS_HIGH)
247 enable = !enable;
248
249 if (spi->controller_state) {
250 int err = pm_runtime_get_sync(mcspi->dev);
251 if (err < 0) {
252 pm_runtime_put_noidle(mcspi->dev);
253 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
254 return;
255 }
256
257 l = mcspi_cached_chconf0(spi);
258
259 if (enable)
260 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
261 else
262 l |= OMAP2_MCSPI_CHCONF_FORCE;
263
264 mcspi_write_chconf0(spi, l);
265
266 pm_runtime_mark_last_busy(mcspi->dev);
267 pm_runtime_put_autosuspend(mcspi->dev);
268 }
269}
270
271static void omap2_mcspi_set_mode(struct spi_master *master)
272{
273 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
274 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
275 u32 l;
276
277 /*
278 * Choose master or slave mode
279 */
280 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
281 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
282 if (spi_controller_is_slave(master)) {
283 l |= (OMAP2_MCSPI_MODULCTRL_MS);
284 } else {
285 l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
286 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
287 }
288 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
289
290 ctx->modulctrl = l;
291}
292
293static void omap2_mcspi_set_fifo(const struct spi_device *spi,
294 struct spi_transfer *t, int enable)
295{
296 struct spi_master *master = spi->master;
297 struct omap2_mcspi_cs *cs = spi->controller_state;
298 struct omap2_mcspi *mcspi;
299 unsigned int wcnt;
300 int max_fifo_depth, bytes_per_word;
301 u32 chconf, xferlevel;
302
303 mcspi = spi_master_get_devdata(master);
304
305 chconf = mcspi_cached_chconf0(spi);
306 if (enable) {
307 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
308 if (t->len % bytes_per_word != 0)
309 goto disable_fifo;
310
311 if (t->rx_buf != NULL && t->tx_buf != NULL)
312 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
313 else
314 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
315
316 wcnt = t->len / bytes_per_word;
317 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
318 goto disable_fifo;
319
320 xferlevel = wcnt << 16;
321 if (t->rx_buf != NULL) {
322 chconf |= OMAP2_MCSPI_CHCONF_FFER;
323 xferlevel |= (bytes_per_word - 1) << 8;
324 }
325
326 if (t->tx_buf != NULL) {
327 chconf |= OMAP2_MCSPI_CHCONF_FFET;
328 xferlevel |= bytes_per_word - 1;
329 }
330
331 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
332 mcspi_write_chconf0(spi, chconf);
333 mcspi->fifo_depth = max_fifo_depth;
334
335 return;
336 }
337
338disable_fifo:
339 if (t->rx_buf != NULL)
340 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
341
342 if (t->tx_buf != NULL)
343 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
344
345 mcspi_write_chconf0(spi, chconf);
346 mcspi->fifo_depth = 0;
347}
348
349static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
350{
351 u32 val;
352
353 return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC);
354}
355
356static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
357 struct completion *x)
358{
359 if (spi_controller_is_slave(mcspi->master)) {
360 if (wait_for_completion_interruptible(x) ||
361 mcspi->slave_aborted)
362 return -EINTR;
363 } else {
364 wait_for_completion(x);
365 }
366
367 return 0;
368}
369
370static void omap2_mcspi_rx_callback(void *data)
371{
372 struct spi_device *spi = data;
373 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
374 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
375
376 /* We must disable the DMA RX request */
377 omap2_mcspi_set_dma_req(spi, 1, 0);
378
379 complete(&mcspi_dma->dma_rx_completion);
380}
381
382static void omap2_mcspi_tx_callback(void *data)
383{
384 struct spi_device *spi = data;
385 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
386 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
387
388 /* We must disable the DMA TX request */
389 omap2_mcspi_set_dma_req(spi, 0, 0);
390
391 complete(&mcspi_dma->dma_tx_completion);
392}
393
394static void omap2_mcspi_tx_dma(struct spi_device *spi,
395 struct spi_transfer *xfer,
396 struct dma_slave_config cfg)
397{
398 struct omap2_mcspi *mcspi;
399 struct omap2_mcspi_dma *mcspi_dma;
400 struct dma_async_tx_descriptor *tx;
401
402 mcspi = spi_master_get_devdata(spi->master);
403 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
404
405 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
406
407 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
408 xfer->tx_sg.nents,
409 DMA_MEM_TO_DEV,
410 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
411 if (tx) {
412 tx->callback = omap2_mcspi_tx_callback;
413 tx->callback_param = spi;
414 dmaengine_submit(tx);
415 } else {
416 /* FIXME: fall back to PIO? */
417 }
418 dma_async_issue_pending(mcspi_dma->dma_tx);
419 omap2_mcspi_set_dma_req(spi, 0, 1);
420}
421
422static unsigned
423omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
424 struct dma_slave_config cfg,
425 unsigned es)
426{
427 struct omap2_mcspi *mcspi;
428 struct omap2_mcspi_dma *mcspi_dma;
429 unsigned int count, transfer_reduction = 0;
430 struct scatterlist *sg_out[2];
431 int nb_sizes = 0, out_mapped_nents[2], ret, x;
432 size_t sizes[2];
433 u32 l;
434 int elements = 0;
435 int word_len, element_count;
436 struct omap2_mcspi_cs *cs = spi->controller_state;
437 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
438 struct dma_async_tx_descriptor *tx;
439
440 mcspi = spi_master_get_devdata(spi->master);
441 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
442 count = xfer->len;
443
444 /*
445 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
446 * it mentions reducing DMA transfer length by one element in master
447 * normal mode.
448 */
449 if (mcspi->fifo_depth == 0)
450 transfer_reduction = es;
451
452 word_len = cs->word_len;
453 l = mcspi_cached_chconf0(spi);
454
455 if (word_len <= 8)
456 element_count = count;
457 else if (word_len <= 16)
458 element_count = count >> 1;
459 else /* word_len <= 32 */
460 element_count = count >> 2;
461
462
463 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
464
465 /*
466 * Reduce DMA transfer length by one more if McSPI is
467 * configured in turbo mode.
468 */
469 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
470 transfer_reduction += es;
471
472 if (transfer_reduction) {
473 /* Split sgl into two. The second sgl won't be used. */
474 sizes[0] = count - transfer_reduction;
475 sizes[1] = transfer_reduction;
476 nb_sizes = 2;
477 } else {
478 /*
479 * Don't bother splitting the sgl. This essentially
480 * clones the original sgl.
481 */
482 sizes[0] = count;
483 nb_sizes = 1;
484 }
485
486 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
487 sizes, sg_out, out_mapped_nents, GFP_KERNEL);
488
489 if (ret < 0) {
490 dev_err(&spi->dev, "sg_split failed\n");
491 return 0;
492 }
493
494 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
495 out_mapped_nents[0], DMA_DEV_TO_MEM,
496 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
497 if (tx) {
498 tx->callback = omap2_mcspi_rx_callback;
499 tx->callback_param = spi;
500 dmaengine_submit(tx);
501 } else {
502 /* FIXME: fall back to PIO? */
503 }
504
505 dma_async_issue_pending(mcspi_dma->dma_rx);
506 omap2_mcspi_set_dma_req(spi, 1, 1);
507
508 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
509 if (ret || mcspi->slave_aborted) {
510 dmaengine_terminate_sync(mcspi_dma->dma_rx);
511 omap2_mcspi_set_dma_req(spi, 1, 0);
512 return 0;
513 }
514
515 for (x = 0; x < nb_sizes; x++)
516 kfree(sg_out[x]);
517
518 if (mcspi->fifo_depth > 0)
519 return count;
520
521 /*
522 * Due to the DMA transfer length reduction the missing bytes must
523 * be read manually to receive all of the expected data.
524 */
525 omap2_mcspi_set_enable(spi, 0);
526
527 elements = element_count - 1;
528
529 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
530 elements--;
531
532 if (!mcspi_wait_for_reg_bit(chstat_reg,
533 OMAP2_MCSPI_CHSTAT_RXS)) {
534 u32 w;
535
536 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
537 if (word_len <= 8)
538 ((u8 *)xfer->rx_buf)[elements++] = w;
539 else if (word_len <= 16)
540 ((u16 *)xfer->rx_buf)[elements++] = w;
541 else /* word_len <= 32 */
542 ((u32 *)xfer->rx_buf)[elements++] = w;
543 } else {
544 int bytes_per_word = mcspi_bytes_per_word(word_len);
545 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
546 count -= (bytes_per_word << 1);
547 omap2_mcspi_set_enable(spi, 1);
548 return count;
549 }
550 }
551 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
552 u32 w;
553
554 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
555 if (word_len <= 8)
556 ((u8 *)xfer->rx_buf)[elements] = w;
557 else if (word_len <= 16)
558 ((u16 *)xfer->rx_buf)[elements] = w;
559 else /* word_len <= 32 */
560 ((u32 *)xfer->rx_buf)[elements] = w;
561 } else {
562 dev_err(&spi->dev, "DMA RX last word empty\n");
563 count -= mcspi_bytes_per_word(word_len);
564 }
565 omap2_mcspi_set_enable(spi, 1);
566 return count;
567}
568
569static unsigned
570omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
571{
572 struct omap2_mcspi *mcspi;
573 struct omap2_mcspi_cs *cs = spi->controller_state;
574 struct omap2_mcspi_dma *mcspi_dma;
575 unsigned int count;
576 u8 *rx;
577 const u8 *tx;
578 struct dma_slave_config cfg;
579 enum dma_slave_buswidth width;
580 unsigned es;
581 void __iomem *chstat_reg;
582 void __iomem *irqstat_reg;
583 int wait_res;
584
585 mcspi = spi_master_get_devdata(spi->master);
586 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
587
588 if (cs->word_len <= 8) {
589 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
590 es = 1;
591 } else if (cs->word_len <= 16) {
592 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
593 es = 2;
594 } else {
595 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
596 es = 4;
597 }
598
599 count = xfer->len;
600
601 memset(&cfg, 0, sizeof(cfg));
602 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
603 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
604 cfg.src_addr_width = width;
605 cfg.dst_addr_width = width;
606 cfg.src_maxburst = 1;
607 cfg.dst_maxburst = 1;
608
609 rx = xfer->rx_buf;
610 tx = xfer->tx_buf;
611
612 mcspi->slave_aborted = false;
613 reinit_completion(&mcspi_dma->dma_tx_completion);
614 reinit_completion(&mcspi_dma->dma_rx_completion);
615 reinit_completion(&mcspi->txdone);
616 if (tx) {
617 /* Enable EOW IRQ to know end of tx in slave mode */
618 if (spi_controller_is_slave(spi->master))
619 mcspi_write_reg(spi->master,
620 OMAP2_MCSPI_IRQENABLE,
621 OMAP2_MCSPI_IRQSTATUS_EOW);
622 omap2_mcspi_tx_dma(spi, xfer, cfg);
623 }
624
625 if (rx != NULL)
626 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
627
628 if (tx != NULL) {
629 int ret;
630
631 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
632 if (ret || mcspi->slave_aborted) {
633 dmaengine_terminate_sync(mcspi_dma->dma_tx);
634 omap2_mcspi_set_dma_req(spi, 0, 0);
635 return 0;
636 }
637
638 if (spi_controller_is_slave(mcspi->master)) {
639 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
640 if (ret || mcspi->slave_aborted)
641 return 0;
642 }
643
644 if (mcspi->fifo_depth > 0) {
645 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
646
647 if (mcspi_wait_for_reg_bit(irqstat_reg,
648 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
649 dev_err(&spi->dev, "EOW timed out\n");
650
651 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
652 OMAP2_MCSPI_IRQSTATUS_EOW);
653 }
654
655 /* for TX_ONLY mode, be sure all words have shifted out */
656 if (rx == NULL) {
657 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
658 if (mcspi->fifo_depth > 0) {
659 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
660 OMAP2_MCSPI_CHSTAT_TXFFE);
661 if (wait_res < 0)
662 dev_err(&spi->dev, "TXFFE timed out\n");
663 } else {
664 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
665 OMAP2_MCSPI_CHSTAT_TXS);
666 if (wait_res < 0)
667 dev_err(&spi->dev, "TXS timed out\n");
668 }
669 if (wait_res >= 0 &&
670 (mcspi_wait_for_reg_bit(chstat_reg,
671 OMAP2_MCSPI_CHSTAT_EOT) < 0))
672 dev_err(&spi->dev, "EOT timed out\n");
673 }
674 }
675 return count;
676}
677
678static unsigned
679omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
680{
681 struct omap2_mcspi_cs *cs = spi->controller_state;
682 unsigned int count, c;
683 u32 l;
684 void __iomem *base = cs->base;
685 void __iomem *tx_reg;
686 void __iomem *rx_reg;
687 void __iomem *chstat_reg;
688 int word_len;
689
690 count = xfer->len;
691 c = count;
692 word_len = cs->word_len;
693
694 l = mcspi_cached_chconf0(spi);
695
696 /* We store the pre-calculated register addresses on stack to speed
697 * up the transfer loop. */
698 tx_reg = base + OMAP2_MCSPI_TX0;
699 rx_reg = base + OMAP2_MCSPI_RX0;
700 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
701
702 if (c < (word_len>>3))
703 return 0;
704
705 if (word_len <= 8) {
706 u8 *rx;
707 const u8 *tx;
708
709 rx = xfer->rx_buf;
710 tx = xfer->tx_buf;
711
712 do {
713 c -= 1;
714 if (tx != NULL) {
715 if (mcspi_wait_for_reg_bit(chstat_reg,
716 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
717 dev_err(&spi->dev, "TXS timed out\n");
718 goto out;
719 }
720 dev_vdbg(&spi->dev, "write-%d %02x\n",
721 word_len, *tx);
722 writel_relaxed(*tx++, tx_reg);
723 }
724 if (rx != NULL) {
725 if (mcspi_wait_for_reg_bit(chstat_reg,
726 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
727 dev_err(&spi->dev, "RXS timed out\n");
728 goto out;
729 }
730
731 if (c == 1 && tx == NULL &&
732 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
733 omap2_mcspi_set_enable(spi, 0);
734 *rx++ = readl_relaxed(rx_reg);
735 dev_vdbg(&spi->dev, "read-%d %02x\n",
736 word_len, *(rx - 1));
737 if (mcspi_wait_for_reg_bit(chstat_reg,
738 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
739 dev_err(&spi->dev,
740 "RXS timed out\n");
741 goto out;
742 }
743 c = 0;
744 } else if (c == 0 && tx == NULL) {
745 omap2_mcspi_set_enable(spi, 0);
746 }
747
748 *rx++ = readl_relaxed(rx_reg);
749 dev_vdbg(&spi->dev, "read-%d %02x\n",
750 word_len, *(rx - 1));
751 }
752 } while (c);
753 } else if (word_len <= 16) {
754 u16 *rx;
755 const u16 *tx;
756
757 rx = xfer->rx_buf;
758 tx = xfer->tx_buf;
759 do {
760 c -= 2;
761 if (tx != NULL) {
762 if (mcspi_wait_for_reg_bit(chstat_reg,
763 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
764 dev_err(&spi->dev, "TXS timed out\n");
765 goto out;
766 }
767 dev_vdbg(&spi->dev, "write-%d %04x\n",
768 word_len, *tx);
769 writel_relaxed(*tx++, tx_reg);
770 }
771 if (rx != NULL) {
772 if (mcspi_wait_for_reg_bit(chstat_reg,
773 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
774 dev_err(&spi->dev, "RXS timed out\n");
775 goto out;
776 }
777
778 if (c == 2 && tx == NULL &&
779 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
780 omap2_mcspi_set_enable(spi, 0);
781 *rx++ = readl_relaxed(rx_reg);
782 dev_vdbg(&spi->dev, "read-%d %04x\n",
783 word_len, *(rx - 1));
784 if (mcspi_wait_for_reg_bit(chstat_reg,
785 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
786 dev_err(&spi->dev,
787 "RXS timed out\n");
788 goto out;
789 }
790 c = 0;
791 } else if (c == 0 && tx == NULL) {
792 omap2_mcspi_set_enable(spi, 0);
793 }
794
795 *rx++ = readl_relaxed(rx_reg);
796 dev_vdbg(&spi->dev, "read-%d %04x\n",
797 word_len, *(rx - 1));
798 }
799 } while (c >= 2);
800 } else if (word_len <= 32) {
801 u32 *rx;
802 const u32 *tx;
803
804 rx = xfer->rx_buf;
805 tx = xfer->tx_buf;
806 do {
807 c -= 4;
808 if (tx != NULL) {
809 if (mcspi_wait_for_reg_bit(chstat_reg,
810 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
811 dev_err(&spi->dev, "TXS timed out\n");
812 goto out;
813 }
814 dev_vdbg(&spi->dev, "write-%d %08x\n",
815 word_len, *tx);
816 writel_relaxed(*tx++, tx_reg);
817 }
818 if (rx != NULL) {
819 if (mcspi_wait_for_reg_bit(chstat_reg,
820 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
821 dev_err(&spi->dev, "RXS timed out\n");
822 goto out;
823 }
824
825 if (c == 4 && tx == NULL &&
826 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
827 omap2_mcspi_set_enable(spi, 0);
828 *rx++ = readl_relaxed(rx_reg);
829 dev_vdbg(&spi->dev, "read-%d %08x\n",
830 word_len, *(rx - 1));
831 if (mcspi_wait_for_reg_bit(chstat_reg,
832 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
833 dev_err(&spi->dev,
834 "RXS timed out\n");
835 goto out;
836 }
837 c = 0;
838 } else if (c == 0 && tx == NULL) {
839 omap2_mcspi_set_enable(spi, 0);
840 }
841
842 *rx++ = readl_relaxed(rx_reg);
843 dev_vdbg(&spi->dev, "read-%d %08x\n",
844 word_len, *(rx - 1));
845 }
846 } while (c >= 4);
847 }
848
849 /* for TX_ONLY mode, be sure all words have shifted out */
850 if (xfer->rx_buf == NULL) {
851 if (mcspi_wait_for_reg_bit(chstat_reg,
852 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
853 dev_err(&spi->dev, "TXS timed out\n");
854 } else if (mcspi_wait_for_reg_bit(chstat_reg,
855 OMAP2_MCSPI_CHSTAT_EOT) < 0)
856 dev_err(&spi->dev, "EOT timed out\n");
857
858 /* disable chan to purge rx datas received in TX_ONLY transfer,
859 * otherwise these rx datas will affect the direct following
860 * RX_ONLY transfer.
861 */
862 omap2_mcspi_set_enable(spi, 0);
863 }
864out:
865 omap2_mcspi_set_enable(spi, 1);
866 return count - c;
867}
868
869static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
870{
871 u32 div;
872
873 for (div = 0; div < 15; div++)
874 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
875 return div;
876
877 return 15;
878}
879
880/* called only when no transfer is active to this device */
881static int omap2_mcspi_setup_transfer(struct spi_device *spi,
882 struct spi_transfer *t)
883{
884 struct omap2_mcspi_cs *cs = spi->controller_state;
885 struct omap2_mcspi *mcspi;
886 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
887 u8 word_len = spi->bits_per_word;
888 u32 speed_hz = spi->max_speed_hz;
889
890 mcspi = spi_master_get_devdata(spi->master);
891
892 if (t != NULL && t->bits_per_word)
893 word_len = t->bits_per_word;
894
895 cs->word_len = word_len;
896
897 if (t && t->speed_hz)
898 speed_hz = t->speed_hz;
899
900 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
901 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
902 clkd = omap2_mcspi_calc_divisor(speed_hz);
903 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
904 clkg = 0;
905 } else {
906 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
907 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
908 clkd = (div - 1) & 0xf;
909 extclk = (div - 1) >> 4;
910 clkg = OMAP2_MCSPI_CHCONF_CLKG;
911 }
912
913 l = mcspi_cached_chconf0(spi);
914
915 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
916 * REVISIT: this controller could support SPI_3WIRE mode.
917 */
918 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
919 l &= ~OMAP2_MCSPI_CHCONF_IS;
920 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
921 l |= OMAP2_MCSPI_CHCONF_DPE0;
922 } else {
923 l |= OMAP2_MCSPI_CHCONF_IS;
924 l |= OMAP2_MCSPI_CHCONF_DPE1;
925 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
926 }
927
928 /* wordlength */
929 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
930 l |= (word_len - 1) << 7;
931
932 /* set chipselect polarity; manage with FORCE */
933 if (!(spi->mode & SPI_CS_HIGH))
934 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
935 else
936 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
937
938 /* set clock divisor */
939 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
940 l |= clkd << 2;
941
942 /* set clock granularity */
943 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
944 l |= clkg;
945 if (clkg) {
946 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
947 cs->chctrl0 |= extclk << 8;
948 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
949 }
950
951 /* set SPI mode 0..3 */
952 if (spi->mode & SPI_CPOL)
953 l |= OMAP2_MCSPI_CHCONF_POL;
954 else
955 l &= ~OMAP2_MCSPI_CHCONF_POL;
956 if (spi->mode & SPI_CPHA)
957 l |= OMAP2_MCSPI_CHCONF_PHA;
958 else
959 l &= ~OMAP2_MCSPI_CHCONF_PHA;
960
961 mcspi_write_chconf0(spi, l);
962
963 cs->mode = spi->mode;
964
965 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
966 speed_hz,
967 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
968 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
969
970 return 0;
971}
972
973/*
974 * Note that we currently allow DMA only if we get a channel
975 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
976 */
977static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
978 struct omap2_mcspi_dma *mcspi_dma)
979{
980 int ret = 0;
981
982 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
983 mcspi_dma->dma_rx_ch_name);
984 if (IS_ERR(mcspi_dma->dma_rx)) {
985 ret = PTR_ERR(mcspi_dma->dma_rx);
986 mcspi_dma->dma_rx = NULL;
987 goto no_dma;
988 }
989
990 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
991 mcspi_dma->dma_tx_ch_name);
992 if (IS_ERR(mcspi_dma->dma_tx)) {
993 ret = PTR_ERR(mcspi_dma->dma_tx);
994 mcspi_dma->dma_tx = NULL;
995 dma_release_channel(mcspi_dma->dma_rx);
996 mcspi_dma->dma_rx = NULL;
997 }
998
999 init_completion(&mcspi_dma->dma_rx_completion);
1000 init_completion(&mcspi_dma->dma_tx_completion);
1001
1002no_dma:
1003 return ret;
1004}
1005
1006static void omap2_mcspi_release_dma(struct spi_master *master)
1007{
1008 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1009 struct omap2_mcspi_dma *mcspi_dma;
1010 int i;
1011
1012 for (i = 0; i < master->num_chipselect; i++) {
1013 mcspi_dma = &mcspi->dma_channels[i];
1014
1015 if (mcspi_dma->dma_rx) {
1016 dma_release_channel(mcspi_dma->dma_rx);
1017 mcspi_dma->dma_rx = NULL;
1018 }
1019 if (mcspi_dma->dma_tx) {
1020 dma_release_channel(mcspi_dma->dma_tx);
1021 mcspi_dma->dma_tx = NULL;
1022 }
1023 }
1024}
1025
1026static int omap2_mcspi_setup(struct spi_device *spi)
1027{
1028 int ret;
1029 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1030 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1031 struct omap2_mcspi_cs *cs = spi->controller_state;
1032
1033 if (!cs) {
1034 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1035 if (!cs)
1036 return -ENOMEM;
1037 cs->base = mcspi->base + spi->chip_select * 0x14;
1038 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1039 cs->mode = 0;
1040 cs->chconf0 = 0;
1041 cs->chctrl0 = 0;
1042 spi->controller_state = cs;
1043 /* Link this to context save list */
1044 list_add_tail(&cs->node, &ctx->cs);
1045 }
1046
1047 ret = pm_runtime_get_sync(mcspi->dev);
1048 if (ret < 0) {
1049 pm_runtime_put_noidle(mcspi->dev);
1050
1051 return ret;
1052 }
1053
1054 ret = omap2_mcspi_setup_transfer(spi, NULL);
1055 pm_runtime_mark_last_busy(mcspi->dev);
1056 pm_runtime_put_autosuspend(mcspi->dev);
1057
1058 return ret;
1059}
1060
1061static void omap2_mcspi_cleanup(struct spi_device *spi)
1062{
1063 struct omap2_mcspi_cs *cs;
1064
1065 if (spi->controller_state) {
1066 /* Unlink controller state from context save list */
1067 cs = spi->controller_state;
1068 list_del(&cs->node);
1069
1070 kfree(cs);
1071 }
1072}
1073
1074static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
1075{
1076 struct omap2_mcspi *mcspi = data;
1077 u32 irqstat;
1078
1079 irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
1080 if (!irqstat)
1081 return IRQ_NONE;
1082
1083 /* Disable IRQ and wakeup slave xfer task */
1084 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
1085 if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1086 complete(&mcspi->txdone);
1087
1088 return IRQ_HANDLED;
1089}
1090
1091static int omap2_mcspi_slave_abort(struct spi_master *master)
1092{
1093 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1094 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1095
1096 mcspi->slave_aborted = true;
1097 complete(&mcspi_dma->dma_rx_completion);
1098 complete(&mcspi_dma->dma_tx_completion);
1099 complete(&mcspi->txdone);
1100
1101 return 0;
1102}
1103
1104static int omap2_mcspi_transfer_one(struct spi_master *master,
1105 struct spi_device *spi,
1106 struct spi_transfer *t)
1107{
1108
1109 /* We only enable one channel at a time -- the one whose message is
1110 * -- although this controller would gladly
1111 * arbitrate among multiple channels. This corresponds to "single
1112 * channel" master mode. As a side effect, we need to manage the
1113 * chipselect with the FORCE bit ... CS != channel enable.
1114 */
1115
1116 struct omap2_mcspi *mcspi;
1117 struct omap2_mcspi_dma *mcspi_dma;
1118 struct omap2_mcspi_cs *cs;
1119 struct omap2_mcspi_device_config *cd;
1120 int par_override = 0;
1121 int status = 0;
1122 u32 chconf;
1123
1124 mcspi = spi_master_get_devdata(master);
1125 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1126 cs = spi->controller_state;
1127 cd = spi->controller_data;
1128
1129 /*
1130 * The slave driver could have changed spi->mode in which case
1131 * it will be different from cs->mode (the current hardware setup).
1132 * If so, set par_override (even though its not a parity issue) so
1133 * omap2_mcspi_setup_transfer will be called to configure the hardware
1134 * with the correct mode on the first iteration of the loop below.
1135 */
1136 if (spi->mode != cs->mode)
1137 par_override = 1;
1138
1139 omap2_mcspi_set_enable(spi, 0);
1140
1141 if (spi->cs_gpiod)
1142 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1143
1144 if (par_override ||
1145 (t->speed_hz != spi->max_speed_hz) ||
1146 (t->bits_per_word != spi->bits_per_word)) {
1147 par_override = 1;
1148 status = omap2_mcspi_setup_transfer(spi, t);
1149 if (status < 0)
1150 goto out;
1151 if (t->speed_hz == spi->max_speed_hz &&
1152 t->bits_per_word == spi->bits_per_word)
1153 par_override = 0;
1154 }
1155 if (cd && cd->cs_per_word) {
1156 chconf = mcspi->ctx.modulctrl;
1157 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1158 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1159 mcspi->ctx.modulctrl =
1160 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1161 }
1162
1163 chconf = mcspi_cached_chconf0(spi);
1164 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1165 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1166
1167 if (t->tx_buf == NULL)
1168 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1169 else if (t->rx_buf == NULL)
1170 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1171
1172 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1173 /* Turbo mode is for more than one word */
1174 if (t->len > ((cs->word_len + 7) >> 3))
1175 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1176 }
1177
1178 mcspi_write_chconf0(spi, chconf);
1179
1180 if (t->len) {
1181 unsigned count;
1182
1183 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1184 master->cur_msg_mapped &&
1185 master->can_dma(master, spi, t))
1186 omap2_mcspi_set_fifo(spi, t, 1);
1187
1188 omap2_mcspi_set_enable(spi, 1);
1189
1190 /* RX_ONLY mode needs dummy data in TX reg */
1191 if (t->tx_buf == NULL)
1192 writel_relaxed(0, cs->base
1193 + OMAP2_MCSPI_TX0);
1194
1195 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1196 master->cur_msg_mapped &&
1197 master->can_dma(master, spi, t))
1198 count = omap2_mcspi_txrx_dma(spi, t);
1199 else
1200 count = omap2_mcspi_txrx_pio(spi, t);
1201
1202 if (count != t->len) {
1203 status = -EIO;
1204 goto out;
1205 }
1206 }
1207
1208 omap2_mcspi_set_enable(spi, 0);
1209
1210 if (mcspi->fifo_depth > 0)
1211 omap2_mcspi_set_fifo(spi, t, 0);
1212
1213out:
1214 /* Restore defaults if they were overriden */
1215 if (par_override) {
1216 par_override = 0;
1217 status = omap2_mcspi_setup_transfer(spi, NULL);
1218 }
1219
1220 if (cd && cd->cs_per_word) {
1221 chconf = mcspi->ctx.modulctrl;
1222 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1223 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1224 mcspi->ctx.modulctrl =
1225 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1226 }
1227
1228 omap2_mcspi_set_enable(spi, 0);
1229
1230 if (spi->cs_gpiod)
1231 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1232
1233 if (mcspi->fifo_depth > 0 && t)
1234 omap2_mcspi_set_fifo(spi, t, 0);
1235
1236 return status;
1237}
1238
1239static int omap2_mcspi_prepare_message(struct spi_master *master,
1240 struct spi_message *msg)
1241{
1242 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1243 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1244 struct omap2_mcspi_cs *cs;
1245
1246 /* Only a single channel can have the FORCE bit enabled
1247 * in its chconf0 register.
1248 * Scan all channels and disable them except the current one.
1249 * A FORCE can remain from a last transfer having cs_change enabled
1250 */
1251 list_for_each_entry(cs, &ctx->cs, node) {
1252 if (msg->spi->controller_state == cs)
1253 continue;
1254
1255 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1256 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1257 writel_relaxed(cs->chconf0,
1258 cs->base + OMAP2_MCSPI_CHCONF0);
1259 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1260 }
1261 }
1262
1263 return 0;
1264}
1265
1266static bool omap2_mcspi_can_dma(struct spi_master *master,
1267 struct spi_device *spi,
1268 struct spi_transfer *xfer)
1269{
1270 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1271 struct omap2_mcspi_dma *mcspi_dma =
1272 &mcspi->dma_channels[spi->chip_select];
1273
1274 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1275 return false;
1276
1277 if (spi_controller_is_slave(master))
1278 return true;
1279
1280 master->dma_rx = mcspi_dma->dma_rx;
1281 master->dma_tx = mcspi_dma->dma_tx;
1282
1283 return (xfer->len >= DMA_MIN_BYTES);
1284}
1285
1286static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
1287{
1288 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1289 struct omap2_mcspi_dma *mcspi_dma =
1290 &mcspi->dma_channels[spi->chip_select];
1291
1292 if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
1293 return mcspi->max_xfer_len;
1294
1295 return SIZE_MAX;
1296}
1297
1298static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1299{
1300 struct spi_master *master = mcspi->master;
1301 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1302 int ret = 0;
1303
1304 ret = pm_runtime_get_sync(mcspi->dev);
1305 if (ret < 0) {
1306 pm_runtime_put_noidle(mcspi->dev);
1307
1308 return ret;
1309 }
1310
1311 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1312 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1313 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1314
1315 omap2_mcspi_set_mode(master);
1316 pm_runtime_mark_last_busy(mcspi->dev);
1317 pm_runtime_put_autosuspend(mcspi->dev);
1318 return 0;
1319}
1320
1321/*
1322 * When SPI wake up from off-mode, CS is in activate state. If it was in
1323 * inactive state when driver was suspend, then force it to inactive state at
1324 * wake up.
1325 */
1326static int omap_mcspi_runtime_resume(struct device *dev)
1327{
1328 struct spi_master *master = dev_get_drvdata(dev);
1329 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1330 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1331 struct omap2_mcspi_cs *cs;
1332
1333 /* McSPI: context restore */
1334 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1335 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1336
1337 list_for_each_entry(cs, &ctx->cs, node) {
1338 /*
1339 * We need to toggle CS state for OMAP take this
1340 * change in account.
1341 */
1342 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1343 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1344 writel_relaxed(cs->chconf0,
1345 cs->base + OMAP2_MCSPI_CHCONF0);
1346 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1347 writel_relaxed(cs->chconf0,
1348 cs->base + OMAP2_MCSPI_CHCONF0);
1349 } else {
1350 writel_relaxed(cs->chconf0,
1351 cs->base + OMAP2_MCSPI_CHCONF0);
1352 }
1353 }
1354
1355 return 0;
1356}
1357
1358static struct omap2_mcspi_platform_config omap2_pdata = {
1359 .regs_offset = 0,
1360};
1361
1362static struct omap2_mcspi_platform_config omap4_pdata = {
1363 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1364};
1365
1366static struct omap2_mcspi_platform_config am654_pdata = {
1367 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1368 .max_xfer_len = SZ_4K - 1,
1369};
1370
1371static const struct of_device_id omap_mcspi_of_match[] = {
1372 {
1373 .compatible = "ti,omap2-mcspi",
1374 .data = &omap2_pdata,
1375 },
1376 {
1377 .compatible = "ti,omap4-mcspi",
1378 .data = &omap4_pdata,
1379 },
1380 {
1381 .compatible = "ti,am654-mcspi",
1382 .data = &am654_pdata,
1383 },
1384 { },
1385};
1386MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1387
1388static int omap2_mcspi_probe(struct platform_device *pdev)
1389{
1390 struct spi_master *master;
1391 const struct omap2_mcspi_platform_config *pdata;
1392 struct omap2_mcspi *mcspi;
1393 struct resource *r;
1394 int status = 0, i;
1395 u32 regs_offset = 0;
1396 struct device_node *node = pdev->dev.of_node;
1397 const struct of_device_id *match;
1398
1399 if (of_property_read_bool(node, "spi-slave"))
1400 master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
1401 else
1402 master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
1403 if (!master)
1404 return -ENOMEM;
1405
1406 /* the spi->mode bits understood by this driver: */
1407 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1408 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1409 master->setup = omap2_mcspi_setup;
1410 master->auto_runtime_pm = true;
1411 master->prepare_message = omap2_mcspi_prepare_message;
1412 master->can_dma = omap2_mcspi_can_dma;
1413 master->transfer_one = omap2_mcspi_transfer_one;
1414 master->set_cs = omap2_mcspi_set_cs;
1415 master->cleanup = omap2_mcspi_cleanup;
1416 master->slave_abort = omap2_mcspi_slave_abort;
1417 master->dev.of_node = node;
1418 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1419 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1420 master->use_gpio_descriptors = true;
1421
1422 platform_set_drvdata(pdev, master);
1423
1424 mcspi = spi_master_get_devdata(master);
1425 mcspi->master = master;
1426
1427 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1428 if (match) {
1429 u32 num_cs = 1; /* default number of chipselect */
1430 pdata = match->data;
1431
1432 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1433 master->num_chipselect = num_cs;
1434 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1435 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1436 } else {
1437 pdata = dev_get_platdata(&pdev->dev);
1438 master->num_chipselect = pdata->num_cs;
1439 mcspi->pin_dir = pdata->pin_dir;
1440 }
1441 regs_offset = pdata->regs_offset;
1442 if (pdata->max_xfer_len) {
1443 mcspi->max_xfer_len = pdata->max_xfer_len;
1444 master->max_transfer_size = omap2_mcspi_max_xfer_size;
1445 }
1446
1447 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1448 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1449 if (IS_ERR(mcspi->base)) {
1450 status = PTR_ERR(mcspi->base);
1451 goto free_master;
1452 }
1453 mcspi->phys = r->start + regs_offset;
1454 mcspi->base += regs_offset;
1455
1456 mcspi->dev = &pdev->dev;
1457
1458 INIT_LIST_HEAD(&mcspi->ctx.cs);
1459
1460 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1461 sizeof(struct omap2_mcspi_dma),
1462 GFP_KERNEL);
1463 if (mcspi->dma_channels == NULL) {
1464 status = -ENOMEM;
1465 goto free_master;
1466 }
1467
1468 for (i = 0; i < master->num_chipselect; i++) {
1469 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1470 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1471
1472 status = omap2_mcspi_request_dma(mcspi,
1473 &mcspi->dma_channels[i]);
1474 if (status == -EPROBE_DEFER)
1475 goto free_master;
1476 }
1477
1478 status = platform_get_irq(pdev, 0);
1479 if (status == -EPROBE_DEFER)
1480 goto free_master;
1481 if (status < 0) {
1482 dev_err(&pdev->dev, "no irq resource found\n");
1483 goto free_master;
1484 }
1485 init_completion(&mcspi->txdone);
1486 status = devm_request_irq(&pdev->dev, status,
1487 omap2_mcspi_irq_handler, 0, pdev->name,
1488 mcspi);
1489 if (status) {
1490 dev_err(&pdev->dev, "Cannot request IRQ");
1491 goto free_master;
1492 }
1493
1494 pm_runtime_use_autosuspend(&pdev->dev);
1495 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1496 pm_runtime_enable(&pdev->dev);
1497
1498 status = omap2_mcspi_controller_setup(mcspi);
1499 if (status < 0)
1500 goto disable_pm;
1501
1502 status = devm_spi_register_controller(&pdev->dev, master);
1503 if (status < 0)
1504 goto disable_pm;
1505
1506 return status;
1507
1508disable_pm:
1509 pm_runtime_dont_use_autosuspend(&pdev->dev);
1510 pm_runtime_put_sync(&pdev->dev);
1511 pm_runtime_disable(&pdev->dev);
1512free_master:
1513 omap2_mcspi_release_dma(master);
1514 spi_master_put(master);
1515 return status;
1516}
1517
1518static int omap2_mcspi_remove(struct platform_device *pdev)
1519{
1520 struct spi_master *master = platform_get_drvdata(pdev);
1521 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1522
1523 omap2_mcspi_release_dma(master);
1524
1525 pm_runtime_dont_use_autosuspend(mcspi->dev);
1526 pm_runtime_put_sync(mcspi->dev);
1527 pm_runtime_disable(&pdev->dev);
1528
1529 return 0;
1530}
1531
1532/* work with hotplug and coldplug */
1533MODULE_ALIAS("platform:omap2_mcspi");
1534
1535static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1536{
1537 struct spi_master *master = dev_get_drvdata(dev);
1538 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1539 int error;
1540
1541 error = pinctrl_pm_select_sleep_state(dev);
1542 if (error)
1543 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1544 __func__, error);
1545
1546 error = spi_master_suspend(master);
1547 if (error)
1548 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
1549 __func__, error);
1550
1551 return pm_runtime_force_suspend(dev);
1552}
1553
1554static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1555{
1556 struct spi_master *master = dev_get_drvdata(dev);
1557 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1558 int error;
1559
1560 error = pinctrl_pm_select_default_state(dev);
1561 if (error)
1562 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1563 __func__, error);
1564
1565 error = spi_master_resume(master);
1566 if (error)
1567 dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
1568 __func__, error);
1569
1570 return pm_runtime_force_resume(dev);
1571}
1572
1573static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1574 SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1575 omap2_mcspi_resume)
1576 .runtime_resume = omap_mcspi_runtime_resume,
1577};
1578
1579static struct platform_driver omap2_mcspi_driver = {
1580 .driver = {
1581 .name = "omap2_mcspi",
1582 .pm = &omap2_mcspi_pm_ops,
1583 .of_match_table = omap_mcspi_of_match,
1584 },
1585 .probe = omap2_mcspi_probe,
1586 .remove = omap2_mcspi_remove,
1587};
1588
1589module_platform_driver(omap2_mcspi_driver);
1590MODULE_LICENSE("GPL");
1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/io.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
37
38#include <linux/spi/spi.h>
39
40#include <plat/dma.h>
41#include <plat/clock.h>
42#include <plat/mcspi.h>
43
44#define OMAP2_MCSPI_MAX_FREQ 48000000
45
46/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
47#define OMAP2_MCSPI_MAX_CTRL 4
48
49#define OMAP2_MCSPI_REVISION 0x00
50#define OMAP2_MCSPI_SYSSTATUS 0x14
51#define OMAP2_MCSPI_IRQSTATUS 0x18
52#define OMAP2_MCSPI_IRQENABLE 0x1c
53#define OMAP2_MCSPI_WAKEUPENABLE 0x20
54#define OMAP2_MCSPI_SYST 0x24
55#define OMAP2_MCSPI_MODULCTRL 0x28
56
57/* per-channel banks, 0x14 bytes each, first is: */
58#define OMAP2_MCSPI_CHCONF0 0x2c
59#define OMAP2_MCSPI_CHSTAT0 0x30
60#define OMAP2_MCSPI_CHCTRL0 0x34
61#define OMAP2_MCSPI_TX0 0x38
62#define OMAP2_MCSPI_RX0 0x3c
63
64/* per-register bitmasks: */
65
66#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
67#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
68#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
69
70#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
71#define OMAP2_MCSPI_CHCONF_POL BIT(1)
72#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
73#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
74#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
75#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
76#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
77#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
78#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
79#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
80#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
81#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
82#define OMAP2_MCSPI_CHCONF_IS BIT(18)
83#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
84#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
85
86#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
87#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
88#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
89
90#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
91
92#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
93
94/* We have 2 DMA channels per CS, one for RX and one for TX */
95struct omap2_mcspi_dma {
96 int dma_tx_channel;
97 int dma_rx_channel;
98
99 int dma_tx_sync_dev;
100 int dma_rx_sync_dev;
101
102 struct completion dma_tx_completion;
103 struct completion dma_rx_completion;
104};
105
106/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107 * cache operations; better heuristics consider wordsize and bitrate.
108 */
109#define DMA_MIN_BYTES 160
110
111
112struct omap2_mcspi {
113 struct work_struct work;
114 /* lock protects queue and registers */
115 spinlock_t lock;
116 struct list_head msg_queue;
117 struct spi_master *master;
118 /* Virtual base address of the controller */
119 void __iomem *base;
120 unsigned long phys;
121 /* SPI1 has 4 channels, while SPI2 has 2 */
122 struct omap2_mcspi_dma *dma_channels;
123 struct device *dev;
124};
125
126struct omap2_mcspi_cs {
127 void __iomem *base;
128 unsigned long phys;
129 int word_len;
130 struct list_head node;
131 /* Context save and restore shadow register */
132 u32 chconf0;
133};
134
135/* used for context save and restore, structure members to be updated whenever
136 * corresponding registers are modified.
137 */
138struct omap2_mcspi_regs {
139 u32 modulctrl;
140 u32 wakeupenable;
141 struct list_head cs;
142};
143
144static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
145
146static struct workqueue_struct *omap2_mcspi_wq;
147
148#define MOD_REG_BIT(val, mask, set) do { \
149 if (set) \
150 val |= mask; \
151 else \
152 val &= ~mask; \
153} while (0)
154
155static inline void mcspi_write_reg(struct spi_master *master,
156 int idx, u32 val)
157{
158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
159
160 __raw_writel(val, mcspi->base + idx);
161}
162
163static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
164{
165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
166
167 return __raw_readl(mcspi->base + idx);
168}
169
170static inline void mcspi_write_cs_reg(const struct spi_device *spi,
171 int idx, u32 val)
172{
173 struct omap2_mcspi_cs *cs = spi->controller_state;
174
175 __raw_writel(val, cs->base + idx);
176}
177
178static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
179{
180 struct omap2_mcspi_cs *cs = spi->controller_state;
181
182 return __raw_readl(cs->base + idx);
183}
184
185static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
186{
187 struct omap2_mcspi_cs *cs = spi->controller_state;
188
189 return cs->chconf0;
190}
191
192static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
193{
194 struct omap2_mcspi_cs *cs = spi->controller_state;
195
196 cs->chconf0 = val;
197 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
199}
200
201static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
202 int is_read, int enable)
203{
204 u32 l, rw;
205
206 l = mcspi_cached_chconf0(spi);
207
208 if (is_read) /* 1 is read, 0 write */
209 rw = OMAP2_MCSPI_CHCONF_DMAR;
210 else
211 rw = OMAP2_MCSPI_CHCONF_DMAW;
212
213 MOD_REG_BIT(l, rw, enable);
214 mcspi_write_chconf0(spi, l);
215}
216
217static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
218{
219 u32 l;
220
221 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
222 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
223 /* Flash post-writes */
224 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
225}
226
227static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
228{
229 u32 l;
230
231 l = mcspi_cached_chconf0(spi);
232 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
233 mcspi_write_chconf0(spi, l);
234}
235
236static void omap2_mcspi_set_master_mode(struct spi_master *master)
237{
238 u32 l;
239
240 /* setup when switching from (reset default) slave mode
241 * to single-channel master mode
242 */
243 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
244 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
245 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
246 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
247 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
248
249 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
250}
251
252static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
253{
254 struct spi_master *spi_cntrl;
255 struct omap2_mcspi_cs *cs;
256 spi_cntrl = mcspi->master;
257
258 /* McSPI: context restore */
259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
260 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
261
262 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
263 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
264
265 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
266 node)
267 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
268}
269static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
270{
271 pm_runtime_put_sync(mcspi->dev);
272}
273
274static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
275{
276 return pm_runtime_get_sync(mcspi->dev);
277}
278
279static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
280{
281 unsigned long timeout;
282
283 timeout = jiffies + msecs_to_jiffies(1000);
284 while (!(__raw_readl(reg) & bit)) {
285 if (time_after(jiffies, timeout))
286 return -1;
287 cpu_relax();
288 }
289 return 0;
290}
291
292static unsigned
293omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
294{
295 struct omap2_mcspi *mcspi;
296 struct omap2_mcspi_cs *cs = spi->controller_state;
297 struct omap2_mcspi_dma *mcspi_dma;
298 unsigned int count, c;
299 unsigned long base, tx_reg, rx_reg;
300 int word_len, data_type, element_count;
301 int elements = 0;
302 u32 l;
303 u8 * rx;
304 const u8 * tx;
305 void __iomem *chstat_reg;
306
307 mcspi = spi_master_get_devdata(spi->master);
308 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
309 l = mcspi_cached_chconf0(spi);
310
311 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
312
313 count = xfer->len;
314 c = count;
315 word_len = cs->word_len;
316
317 base = cs->phys;
318 tx_reg = base + OMAP2_MCSPI_TX0;
319 rx_reg = base + OMAP2_MCSPI_RX0;
320 rx = xfer->rx_buf;
321 tx = xfer->tx_buf;
322
323 if (word_len <= 8) {
324 data_type = OMAP_DMA_DATA_TYPE_S8;
325 element_count = count;
326 } else if (word_len <= 16) {
327 data_type = OMAP_DMA_DATA_TYPE_S16;
328 element_count = count >> 1;
329 } else /* word_len <= 32 */ {
330 data_type = OMAP_DMA_DATA_TYPE_S32;
331 element_count = count >> 2;
332 }
333
334 if (tx != NULL) {
335 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
336 data_type, element_count, 1,
337 OMAP_DMA_SYNC_ELEMENT,
338 mcspi_dma->dma_tx_sync_dev, 0);
339
340 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
341 OMAP_DMA_AMODE_CONSTANT,
342 tx_reg, 0, 0);
343
344 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
345 OMAP_DMA_AMODE_POST_INC,
346 xfer->tx_dma, 0, 0);
347 }
348
349 if (rx != NULL) {
350 elements = element_count - 1;
351 if (l & OMAP2_MCSPI_CHCONF_TURBO)
352 elements--;
353
354 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
355 data_type, elements, 1,
356 OMAP_DMA_SYNC_ELEMENT,
357 mcspi_dma->dma_rx_sync_dev, 1);
358
359 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
360 OMAP_DMA_AMODE_CONSTANT,
361 rx_reg, 0, 0);
362
363 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
364 OMAP_DMA_AMODE_POST_INC,
365 xfer->rx_dma, 0, 0);
366 }
367
368 if (tx != NULL) {
369 omap_start_dma(mcspi_dma->dma_tx_channel);
370 omap2_mcspi_set_dma_req(spi, 0, 1);
371 }
372
373 if (rx != NULL) {
374 omap_start_dma(mcspi_dma->dma_rx_channel);
375 omap2_mcspi_set_dma_req(spi, 1, 1);
376 }
377
378 if (tx != NULL) {
379 wait_for_completion(&mcspi_dma->dma_tx_completion);
380 dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
381
382 /* for TX_ONLY mode, be sure all words have shifted out */
383 if (rx == NULL) {
384 if (mcspi_wait_for_reg_bit(chstat_reg,
385 OMAP2_MCSPI_CHSTAT_TXS) < 0)
386 dev_err(&spi->dev, "TXS timed out\n");
387 else if (mcspi_wait_for_reg_bit(chstat_reg,
388 OMAP2_MCSPI_CHSTAT_EOT) < 0)
389 dev_err(&spi->dev, "EOT timed out\n");
390 }
391 }
392
393 if (rx != NULL) {
394 wait_for_completion(&mcspi_dma->dma_rx_completion);
395 dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
396 omap2_mcspi_set_enable(spi, 0);
397
398 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
399
400 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
401 & OMAP2_MCSPI_CHSTAT_RXS)) {
402 u32 w;
403
404 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
405 if (word_len <= 8)
406 ((u8 *)xfer->rx_buf)[elements++] = w;
407 else if (word_len <= 16)
408 ((u16 *)xfer->rx_buf)[elements++] = w;
409 else /* word_len <= 32 */
410 ((u32 *)xfer->rx_buf)[elements++] = w;
411 } else {
412 dev_err(&spi->dev,
413 "DMA RX penultimate word empty");
414 count -= (word_len <= 8) ? 2 :
415 (word_len <= 16) ? 4 :
416 /* word_len <= 32 */ 8;
417 omap2_mcspi_set_enable(spi, 1);
418 return count;
419 }
420 }
421
422 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
423 & OMAP2_MCSPI_CHSTAT_RXS)) {
424 u32 w;
425
426 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
427 if (word_len <= 8)
428 ((u8 *)xfer->rx_buf)[elements] = w;
429 else if (word_len <= 16)
430 ((u16 *)xfer->rx_buf)[elements] = w;
431 else /* word_len <= 32 */
432 ((u32 *)xfer->rx_buf)[elements] = w;
433 } else {
434 dev_err(&spi->dev, "DMA RX last word empty");
435 count -= (word_len <= 8) ? 1 :
436 (word_len <= 16) ? 2 :
437 /* word_len <= 32 */ 4;
438 }
439 omap2_mcspi_set_enable(spi, 1);
440 }
441 return count;
442}
443
444static unsigned
445omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
446{
447 struct omap2_mcspi *mcspi;
448 struct omap2_mcspi_cs *cs = spi->controller_state;
449 unsigned int count, c;
450 u32 l;
451 void __iomem *base = cs->base;
452 void __iomem *tx_reg;
453 void __iomem *rx_reg;
454 void __iomem *chstat_reg;
455 int word_len;
456
457 mcspi = spi_master_get_devdata(spi->master);
458 count = xfer->len;
459 c = count;
460 word_len = cs->word_len;
461
462 l = mcspi_cached_chconf0(spi);
463
464 /* We store the pre-calculated register addresses on stack to speed
465 * up the transfer loop. */
466 tx_reg = base + OMAP2_MCSPI_TX0;
467 rx_reg = base + OMAP2_MCSPI_RX0;
468 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
469
470 if (c < (word_len>>3))
471 return 0;
472
473 if (word_len <= 8) {
474 u8 *rx;
475 const u8 *tx;
476
477 rx = xfer->rx_buf;
478 tx = xfer->tx_buf;
479
480 do {
481 c -= 1;
482 if (tx != NULL) {
483 if (mcspi_wait_for_reg_bit(chstat_reg,
484 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
485 dev_err(&spi->dev, "TXS timed out\n");
486 goto out;
487 }
488 dev_vdbg(&spi->dev, "write-%d %02x\n",
489 word_len, *tx);
490 __raw_writel(*tx++, tx_reg);
491 }
492 if (rx != NULL) {
493 if (mcspi_wait_for_reg_bit(chstat_reg,
494 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
495 dev_err(&spi->dev, "RXS timed out\n");
496 goto out;
497 }
498
499 if (c == 1 && tx == NULL &&
500 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
501 omap2_mcspi_set_enable(spi, 0);
502 *rx++ = __raw_readl(rx_reg);
503 dev_vdbg(&spi->dev, "read-%d %02x\n",
504 word_len, *(rx - 1));
505 if (mcspi_wait_for_reg_bit(chstat_reg,
506 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
507 dev_err(&spi->dev,
508 "RXS timed out\n");
509 goto out;
510 }
511 c = 0;
512 } else if (c == 0 && tx == NULL) {
513 omap2_mcspi_set_enable(spi, 0);
514 }
515
516 *rx++ = __raw_readl(rx_reg);
517 dev_vdbg(&spi->dev, "read-%d %02x\n",
518 word_len, *(rx - 1));
519 }
520 } while (c);
521 } else if (word_len <= 16) {
522 u16 *rx;
523 const u16 *tx;
524
525 rx = xfer->rx_buf;
526 tx = xfer->tx_buf;
527 do {
528 c -= 2;
529 if (tx != NULL) {
530 if (mcspi_wait_for_reg_bit(chstat_reg,
531 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
532 dev_err(&spi->dev, "TXS timed out\n");
533 goto out;
534 }
535 dev_vdbg(&spi->dev, "write-%d %04x\n",
536 word_len, *tx);
537 __raw_writel(*tx++, tx_reg);
538 }
539 if (rx != NULL) {
540 if (mcspi_wait_for_reg_bit(chstat_reg,
541 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
542 dev_err(&spi->dev, "RXS timed out\n");
543 goto out;
544 }
545
546 if (c == 2 && tx == NULL &&
547 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
548 omap2_mcspi_set_enable(spi, 0);
549 *rx++ = __raw_readl(rx_reg);
550 dev_vdbg(&spi->dev, "read-%d %04x\n",
551 word_len, *(rx - 1));
552 if (mcspi_wait_for_reg_bit(chstat_reg,
553 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
554 dev_err(&spi->dev,
555 "RXS timed out\n");
556 goto out;
557 }
558 c = 0;
559 } else if (c == 0 && tx == NULL) {
560 omap2_mcspi_set_enable(spi, 0);
561 }
562
563 *rx++ = __raw_readl(rx_reg);
564 dev_vdbg(&spi->dev, "read-%d %04x\n",
565 word_len, *(rx - 1));
566 }
567 } while (c >= 2);
568 } else if (word_len <= 32) {
569 u32 *rx;
570 const u32 *tx;
571
572 rx = xfer->rx_buf;
573 tx = xfer->tx_buf;
574 do {
575 c -= 4;
576 if (tx != NULL) {
577 if (mcspi_wait_for_reg_bit(chstat_reg,
578 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
579 dev_err(&spi->dev, "TXS timed out\n");
580 goto out;
581 }
582 dev_vdbg(&spi->dev, "write-%d %08x\n",
583 word_len, *tx);
584 __raw_writel(*tx++, tx_reg);
585 }
586 if (rx != NULL) {
587 if (mcspi_wait_for_reg_bit(chstat_reg,
588 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
589 dev_err(&spi->dev, "RXS timed out\n");
590 goto out;
591 }
592
593 if (c == 4 && tx == NULL &&
594 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
595 omap2_mcspi_set_enable(spi, 0);
596 *rx++ = __raw_readl(rx_reg);
597 dev_vdbg(&spi->dev, "read-%d %08x\n",
598 word_len, *(rx - 1));
599 if (mcspi_wait_for_reg_bit(chstat_reg,
600 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
601 dev_err(&spi->dev,
602 "RXS timed out\n");
603 goto out;
604 }
605 c = 0;
606 } else if (c == 0 && tx == NULL) {
607 omap2_mcspi_set_enable(spi, 0);
608 }
609
610 *rx++ = __raw_readl(rx_reg);
611 dev_vdbg(&spi->dev, "read-%d %08x\n",
612 word_len, *(rx - 1));
613 }
614 } while (c >= 4);
615 }
616
617 /* for TX_ONLY mode, be sure all words have shifted out */
618 if (xfer->rx_buf == NULL) {
619 if (mcspi_wait_for_reg_bit(chstat_reg,
620 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
621 dev_err(&spi->dev, "TXS timed out\n");
622 } else if (mcspi_wait_for_reg_bit(chstat_reg,
623 OMAP2_MCSPI_CHSTAT_EOT) < 0)
624 dev_err(&spi->dev, "EOT timed out\n");
625
626 /* disable chan to purge rx datas received in TX_ONLY transfer,
627 * otherwise these rx datas will affect the direct following
628 * RX_ONLY transfer.
629 */
630 omap2_mcspi_set_enable(spi, 0);
631 }
632out:
633 omap2_mcspi_set_enable(spi, 1);
634 return count - c;
635}
636
637static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
638{
639 u32 div;
640
641 for (div = 0; div < 15; div++)
642 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
643 return div;
644
645 return 15;
646}
647
648/* called only when no transfer is active to this device */
649static int omap2_mcspi_setup_transfer(struct spi_device *spi,
650 struct spi_transfer *t)
651{
652 struct omap2_mcspi_cs *cs = spi->controller_state;
653 struct omap2_mcspi *mcspi;
654 struct spi_master *spi_cntrl;
655 u32 l = 0, div = 0;
656 u8 word_len = spi->bits_per_word;
657 u32 speed_hz = spi->max_speed_hz;
658
659 mcspi = spi_master_get_devdata(spi->master);
660 spi_cntrl = mcspi->master;
661
662 if (t != NULL && t->bits_per_word)
663 word_len = t->bits_per_word;
664
665 cs->word_len = word_len;
666
667 if (t && t->speed_hz)
668 speed_hz = t->speed_hz;
669
670 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
671 div = omap2_mcspi_calc_divisor(speed_hz);
672
673 l = mcspi_cached_chconf0(spi);
674
675 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
676 * REVISIT: this controller could support SPI_3WIRE mode.
677 */
678 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
679 l |= OMAP2_MCSPI_CHCONF_DPE0;
680
681 /* wordlength */
682 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
683 l |= (word_len - 1) << 7;
684
685 /* set chipselect polarity; manage with FORCE */
686 if (!(spi->mode & SPI_CS_HIGH))
687 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
688 else
689 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
690
691 /* set clock divisor */
692 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
693 l |= div << 2;
694
695 /* set SPI mode 0..3 */
696 if (spi->mode & SPI_CPOL)
697 l |= OMAP2_MCSPI_CHCONF_POL;
698 else
699 l &= ~OMAP2_MCSPI_CHCONF_POL;
700 if (spi->mode & SPI_CPHA)
701 l |= OMAP2_MCSPI_CHCONF_PHA;
702 else
703 l &= ~OMAP2_MCSPI_CHCONF_PHA;
704
705 mcspi_write_chconf0(spi, l);
706
707 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
708 OMAP2_MCSPI_MAX_FREQ >> div,
709 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
710 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
711
712 return 0;
713}
714
715static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
716{
717 struct spi_device *spi = data;
718 struct omap2_mcspi *mcspi;
719 struct omap2_mcspi_dma *mcspi_dma;
720
721 mcspi = spi_master_get_devdata(spi->master);
722 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
723
724 complete(&mcspi_dma->dma_rx_completion);
725
726 /* We must disable the DMA RX request */
727 omap2_mcspi_set_dma_req(spi, 1, 0);
728}
729
730static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
731{
732 struct spi_device *spi = data;
733 struct omap2_mcspi *mcspi;
734 struct omap2_mcspi_dma *mcspi_dma;
735
736 mcspi = spi_master_get_devdata(spi->master);
737 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
738
739 complete(&mcspi_dma->dma_tx_completion);
740
741 /* We must disable the DMA TX request */
742 omap2_mcspi_set_dma_req(spi, 0, 0);
743}
744
745static int omap2_mcspi_request_dma(struct spi_device *spi)
746{
747 struct spi_master *master = spi->master;
748 struct omap2_mcspi *mcspi;
749 struct omap2_mcspi_dma *mcspi_dma;
750
751 mcspi = spi_master_get_devdata(master);
752 mcspi_dma = mcspi->dma_channels + spi->chip_select;
753
754 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
755 omap2_mcspi_dma_rx_callback, spi,
756 &mcspi_dma->dma_rx_channel)) {
757 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
758 return -EAGAIN;
759 }
760
761 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
762 omap2_mcspi_dma_tx_callback, spi,
763 &mcspi_dma->dma_tx_channel)) {
764 omap_free_dma(mcspi_dma->dma_rx_channel);
765 mcspi_dma->dma_rx_channel = -1;
766 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
767 return -EAGAIN;
768 }
769
770 init_completion(&mcspi_dma->dma_rx_completion);
771 init_completion(&mcspi_dma->dma_tx_completion);
772
773 return 0;
774}
775
776static int omap2_mcspi_setup(struct spi_device *spi)
777{
778 int ret;
779 struct omap2_mcspi *mcspi;
780 struct omap2_mcspi_dma *mcspi_dma;
781 struct omap2_mcspi_cs *cs = spi->controller_state;
782
783 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
784 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
785 spi->bits_per_word);
786 return -EINVAL;
787 }
788
789 mcspi = spi_master_get_devdata(spi->master);
790 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
791
792 if (!cs) {
793 cs = kzalloc(sizeof *cs, GFP_KERNEL);
794 if (!cs)
795 return -ENOMEM;
796 cs->base = mcspi->base + spi->chip_select * 0x14;
797 cs->phys = mcspi->phys + spi->chip_select * 0x14;
798 cs->chconf0 = 0;
799 spi->controller_state = cs;
800 /* Link this to context save list */
801 list_add_tail(&cs->node,
802 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
803 }
804
805 if (mcspi_dma->dma_rx_channel == -1
806 || mcspi_dma->dma_tx_channel == -1) {
807 ret = omap2_mcspi_request_dma(spi);
808 if (ret < 0)
809 return ret;
810 }
811
812 ret = omap2_mcspi_enable_clocks(mcspi);
813 if (ret < 0)
814 return ret;
815
816 ret = omap2_mcspi_setup_transfer(spi, NULL);
817 omap2_mcspi_disable_clocks(mcspi);
818
819 return ret;
820}
821
822static void omap2_mcspi_cleanup(struct spi_device *spi)
823{
824 struct omap2_mcspi *mcspi;
825 struct omap2_mcspi_dma *mcspi_dma;
826 struct omap2_mcspi_cs *cs;
827
828 mcspi = spi_master_get_devdata(spi->master);
829
830 if (spi->controller_state) {
831 /* Unlink controller state from context save list */
832 cs = spi->controller_state;
833 list_del(&cs->node);
834
835 kfree(spi->controller_state);
836 }
837
838 if (spi->chip_select < spi->master->num_chipselect) {
839 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
840
841 if (mcspi_dma->dma_rx_channel != -1) {
842 omap_free_dma(mcspi_dma->dma_rx_channel);
843 mcspi_dma->dma_rx_channel = -1;
844 }
845 if (mcspi_dma->dma_tx_channel != -1) {
846 omap_free_dma(mcspi_dma->dma_tx_channel);
847 mcspi_dma->dma_tx_channel = -1;
848 }
849 }
850}
851
852static void omap2_mcspi_work(struct work_struct *work)
853{
854 struct omap2_mcspi *mcspi;
855
856 mcspi = container_of(work, struct omap2_mcspi, work);
857
858 if (omap2_mcspi_enable_clocks(mcspi) < 0)
859 return;
860
861 spin_lock_irq(&mcspi->lock);
862
863 /* We only enable one channel at a time -- the one whose message is
864 * at the head of the queue -- although this controller would gladly
865 * arbitrate among multiple channels. This corresponds to "single
866 * channel" master mode. As a side effect, we need to manage the
867 * chipselect with the FORCE bit ... CS != channel enable.
868 */
869 while (!list_empty(&mcspi->msg_queue)) {
870 struct spi_message *m;
871 struct spi_device *spi;
872 struct spi_transfer *t = NULL;
873 int cs_active = 0;
874 struct omap2_mcspi_cs *cs;
875 struct omap2_mcspi_device_config *cd;
876 int par_override = 0;
877 int status = 0;
878 u32 chconf;
879
880 m = container_of(mcspi->msg_queue.next, struct spi_message,
881 queue);
882
883 list_del_init(&m->queue);
884 spin_unlock_irq(&mcspi->lock);
885
886 spi = m->spi;
887 cs = spi->controller_state;
888 cd = spi->controller_data;
889
890 omap2_mcspi_set_enable(spi, 1);
891 list_for_each_entry(t, &m->transfers, transfer_list) {
892 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
893 status = -EINVAL;
894 break;
895 }
896 if (par_override || t->speed_hz || t->bits_per_word) {
897 par_override = 1;
898 status = omap2_mcspi_setup_transfer(spi, t);
899 if (status < 0)
900 break;
901 if (!t->speed_hz && !t->bits_per_word)
902 par_override = 0;
903 }
904
905 if (!cs_active) {
906 omap2_mcspi_force_cs(spi, 1);
907 cs_active = 1;
908 }
909
910 chconf = mcspi_cached_chconf0(spi);
911 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
912 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
913
914 if (t->tx_buf == NULL)
915 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
916 else if (t->rx_buf == NULL)
917 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
918
919 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
920 /* Turbo mode is for more than one word */
921 if (t->len > ((cs->word_len + 7) >> 3))
922 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
923 }
924
925 mcspi_write_chconf0(spi, chconf);
926
927 if (t->len) {
928 unsigned count;
929
930 /* RX_ONLY mode needs dummy data in TX reg */
931 if (t->tx_buf == NULL)
932 __raw_writel(0, cs->base
933 + OMAP2_MCSPI_TX0);
934
935 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
936 count = omap2_mcspi_txrx_dma(spi, t);
937 else
938 count = omap2_mcspi_txrx_pio(spi, t);
939 m->actual_length += count;
940
941 if (count != t->len) {
942 status = -EIO;
943 break;
944 }
945 }
946
947 if (t->delay_usecs)
948 udelay(t->delay_usecs);
949
950 /* ignore the "leave it on after last xfer" hint */
951 if (t->cs_change) {
952 omap2_mcspi_force_cs(spi, 0);
953 cs_active = 0;
954 }
955 }
956
957 /* Restore defaults if they were overriden */
958 if (par_override) {
959 par_override = 0;
960 status = omap2_mcspi_setup_transfer(spi, NULL);
961 }
962
963 if (cs_active)
964 omap2_mcspi_force_cs(spi, 0);
965
966 omap2_mcspi_set_enable(spi, 0);
967
968 m->status = status;
969 m->complete(m->context);
970
971 spin_lock_irq(&mcspi->lock);
972 }
973
974 spin_unlock_irq(&mcspi->lock);
975
976 omap2_mcspi_disable_clocks(mcspi);
977}
978
979static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
980{
981 struct omap2_mcspi *mcspi;
982 unsigned long flags;
983 struct spi_transfer *t;
984
985 m->actual_length = 0;
986 m->status = 0;
987
988 /* reject invalid messages and transfers */
989 if (list_empty(&m->transfers) || !m->complete)
990 return -EINVAL;
991 list_for_each_entry(t, &m->transfers, transfer_list) {
992 const void *tx_buf = t->tx_buf;
993 void *rx_buf = t->rx_buf;
994 unsigned len = t->len;
995
996 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
997 || (len && !(rx_buf || tx_buf))
998 || (t->bits_per_word &&
999 ( t->bits_per_word < 4
1000 || t->bits_per_word > 32))) {
1001 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1002 t->speed_hz,
1003 len,
1004 tx_buf ? "tx" : "",
1005 rx_buf ? "rx" : "",
1006 t->bits_per_word);
1007 return -EINVAL;
1008 }
1009 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1010 dev_dbg(&spi->dev, "speed_hz %d below minimum %d Hz\n",
1011 t->speed_hz,
1012 OMAP2_MCSPI_MAX_FREQ >> 15);
1013 return -EINVAL;
1014 }
1015
1016 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1017 continue;
1018
1019 if (tx_buf != NULL) {
1020 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
1021 len, DMA_TO_DEVICE);
1022 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
1023 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1024 'T', len);
1025 return -EINVAL;
1026 }
1027 }
1028 if (rx_buf != NULL) {
1029 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
1030 DMA_FROM_DEVICE);
1031 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
1032 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1033 'R', len);
1034 if (tx_buf != NULL)
1035 dma_unmap_single(&spi->dev, t->tx_dma,
1036 len, DMA_TO_DEVICE);
1037 return -EINVAL;
1038 }
1039 }
1040 }
1041
1042 mcspi = spi_master_get_devdata(spi->master);
1043
1044 spin_lock_irqsave(&mcspi->lock, flags);
1045 list_add_tail(&m->queue, &mcspi->msg_queue);
1046 queue_work(omap2_mcspi_wq, &mcspi->work);
1047 spin_unlock_irqrestore(&mcspi->lock, flags);
1048
1049 return 0;
1050}
1051
1052static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1053{
1054 struct spi_master *master = mcspi->master;
1055 u32 tmp;
1056 int ret = 0;
1057
1058 ret = omap2_mcspi_enable_clocks(mcspi);
1059 if (ret < 0)
1060 return ret;
1061
1062 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1063 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1064 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
1065
1066 omap2_mcspi_set_master_mode(master);
1067 omap2_mcspi_disable_clocks(mcspi);
1068 return 0;
1069}
1070
1071static int omap_mcspi_runtime_resume(struct device *dev)
1072{
1073 struct omap2_mcspi *mcspi;
1074 struct spi_master *master;
1075
1076 master = dev_get_drvdata(dev);
1077 mcspi = spi_master_get_devdata(master);
1078 omap2_mcspi_restore_ctx(mcspi);
1079
1080 return 0;
1081}
1082
1083
1084static int __init omap2_mcspi_probe(struct platform_device *pdev)
1085{
1086 struct spi_master *master;
1087 struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
1088 struct omap2_mcspi *mcspi;
1089 struct resource *r;
1090 int status = 0, i;
1091
1092 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1093 if (master == NULL) {
1094 dev_dbg(&pdev->dev, "master allocation failed\n");
1095 return -ENOMEM;
1096 }
1097
1098 /* the spi->mode bits understood by this driver: */
1099 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1100
1101 if (pdev->id != -1)
1102 master->bus_num = pdev->id;
1103
1104 master->setup = omap2_mcspi_setup;
1105 master->transfer = omap2_mcspi_transfer;
1106 master->cleanup = omap2_mcspi_cleanup;
1107 master->num_chipselect = pdata->num_cs;
1108
1109 dev_set_drvdata(&pdev->dev, master);
1110
1111 mcspi = spi_master_get_devdata(master);
1112 mcspi->master = master;
1113
1114 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1115 if (r == NULL) {
1116 status = -ENODEV;
1117 goto err1;
1118 }
1119 if (!request_mem_region(r->start, resource_size(r),
1120 dev_name(&pdev->dev))) {
1121 status = -EBUSY;
1122 goto err1;
1123 }
1124
1125 r->start += pdata->regs_offset;
1126 r->end += pdata->regs_offset;
1127 mcspi->phys = r->start;
1128 mcspi->base = ioremap(r->start, resource_size(r));
1129 if (!mcspi->base) {
1130 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1131 status = -ENOMEM;
1132 goto err2;
1133 }
1134
1135 mcspi->dev = &pdev->dev;
1136 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1137
1138 spin_lock_init(&mcspi->lock);
1139 INIT_LIST_HEAD(&mcspi->msg_queue);
1140 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1141
1142 mcspi->dma_channels = kcalloc(master->num_chipselect,
1143 sizeof(struct omap2_mcspi_dma),
1144 GFP_KERNEL);
1145
1146 if (mcspi->dma_channels == NULL)
1147 goto err2;
1148
1149 for (i = 0; i < master->num_chipselect; i++) {
1150 char dma_ch_name[14];
1151 struct resource *dma_res;
1152
1153 sprintf(dma_ch_name, "rx%d", i);
1154 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1155 dma_ch_name);
1156 if (!dma_res) {
1157 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1158 status = -ENODEV;
1159 break;
1160 }
1161
1162 mcspi->dma_channels[i].dma_rx_channel = -1;
1163 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1164 sprintf(dma_ch_name, "tx%d", i);
1165 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1166 dma_ch_name);
1167 if (!dma_res) {
1168 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1169 status = -ENODEV;
1170 break;
1171 }
1172
1173 mcspi->dma_channels[i].dma_tx_channel = -1;
1174 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1175 }
1176
1177 pm_runtime_enable(&pdev->dev);
1178
1179 if (status || omap2_mcspi_master_setup(mcspi) < 0)
1180 goto err3;
1181
1182 status = spi_register_master(master);
1183 if (status < 0)
1184 goto err4;
1185
1186 return status;
1187
1188err4:
1189 spi_master_put(master);
1190err3:
1191 kfree(mcspi->dma_channels);
1192err2:
1193 release_mem_region(r->start, resource_size(r));
1194 iounmap(mcspi->base);
1195err1:
1196 return status;
1197}
1198
1199static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1200{
1201 struct spi_master *master;
1202 struct omap2_mcspi *mcspi;
1203 struct omap2_mcspi_dma *dma_channels;
1204 struct resource *r;
1205 void __iomem *base;
1206
1207 master = dev_get_drvdata(&pdev->dev);
1208 mcspi = spi_master_get_devdata(master);
1209 dma_channels = mcspi->dma_channels;
1210
1211 omap2_mcspi_disable_clocks(mcspi);
1212 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1213 release_mem_region(r->start, resource_size(r));
1214
1215 base = mcspi->base;
1216 spi_unregister_master(master);
1217 iounmap(base);
1218 kfree(dma_channels);
1219
1220 return 0;
1221}
1222
1223/* work with hotplug and coldplug */
1224MODULE_ALIAS("platform:omap2_mcspi");
1225
1226#ifdef CONFIG_SUSPEND
1227/*
1228 * When SPI wake up from off-mode, CS is in activate state. If it was in
1229 * unactive state when driver was suspend, then force it to unactive state at
1230 * wake up.
1231 */
1232static int omap2_mcspi_resume(struct device *dev)
1233{
1234 struct spi_master *master = dev_get_drvdata(dev);
1235 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1236 struct omap2_mcspi_cs *cs;
1237
1238 omap2_mcspi_enable_clocks(mcspi);
1239 list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
1240 node) {
1241 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1242
1243 /*
1244 * We need to toggle CS state for OMAP take this
1245 * change in account.
1246 */
1247 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
1248 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1249 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
1250 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1251 }
1252 }
1253 omap2_mcspi_disable_clocks(mcspi);
1254 return 0;
1255}
1256#else
1257#define omap2_mcspi_resume NULL
1258#endif
1259
1260static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1261 .resume = omap2_mcspi_resume,
1262 .runtime_resume = omap_mcspi_runtime_resume,
1263};
1264
1265static struct platform_driver omap2_mcspi_driver = {
1266 .driver = {
1267 .name = "omap2_mcspi",
1268 .owner = THIS_MODULE,
1269 .pm = &omap2_mcspi_pm_ops
1270 },
1271 .remove = __exit_p(omap2_mcspi_remove),
1272};
1273
1274
1275static int __init omap2_mcspi_init(void)
1276{
1277 omap2_mcspi_wq = create_singlethread_workqueue(
1278 omap2_mcspi_driver.driver.name);
1279 if (omap2_mcspi_wq == NULL)
1280 return -1;
1281 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1282}
1283subsys_initcall(omap2_mcspi_init);
1284
1285static void __exit omap2_mcspi_exit(void)
1286{
1287 platform_driver_unregister(&omap2_mcspi_driver);
1288
1289 destroy_workqueue(omap2_mcspi_wq);
1290}
1291module_exit(omap2_mcspi_exit);
1292
1293MODULE_LICENSE("GPL");