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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 *
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
7 *
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
9 */
10
11#include <linux/acpi.h>
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/dmi.h>
15#include <linux/init.h>
16#include <linux/msi.h>
17#include <linux/of.h>
18#include <linux/of_pci.h>
19#include <linux/pci.h>
20#include <linux/pm.h>
21#include <linux/slab.h>
22#include <linux/module.h>
23#include <linux/spinlock.h>
24#include <linux/string.h>
25#include <linux/log2.h>
26#include <linux/logic_pio.h>
27#include <linux/pm_wakeup.h>
28#include <linux/interrupt.h>
29#include <linux/device.h>
30#include <linux/pm_runtime.h>
31#include <linux/pci_hotplug.h>
32#include <linux/vmalloc.h>
33#include <linux/pci-ats.h>
34#include <asm/setup.h>
35#include <asm/dma.h>
36#include <linux/aer.h>
37#include "pci.h"
38
39DEFINE_MUTEX(pci_slot_mutex);
40
41const char *pci_power_names[] = {
42 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
43};
44EXPORT_SYMBOL_GPL(pci_power_names);
45
46int isa_dma_bridge_buggy;
47EXPORT_SYMBOL(isa_dma_bridge_buggy);
48
49int pci_pci_problems;
50EXPORT_SYMBOL(pci_pci_problems);
51
52unsigned int pci_pm_d3_delay;
53
54static void pci_pme_list_scan(struct work_struct *work);
55
56static LIST_HEAD(pci_pme_list);
57static DEFINE_MUTEX(pci_pme_list_mutex);
58static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59
60struct pci_pme_device {
61 struct list_head list;
62 struct pci_dev *dev;
63};
64
65#define PME_TIMEOUT 1000 /* How long between PME checks */
66
67static void pci_dev_d3_sleep(struct pci_dev *dev)
68{
69 unsigned int delay = dev->d3_delay;
70
71 if (delay < pci_pm_d3_delay)
72 delay = pci_pm_d3_delay;
73
74 if (delay)
75 msleep(delay);
76}
77
78#ifdef CONFIG_PCI_DOMAINS
79int pci_domains_supported = 1;
80#endif
81
82#define DEFAULT_CARDBUS_IO_SIZE (256)
83#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
84/* pci=cbmemsize=nnM,cbiosize=nn can override this */
85unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
86unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
87
88#define DEFAULT_HOTPLUG_IO_SIZE (256)
89#define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
90#define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
91/* hpiosize=nn can override this */
92unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
93/*
94 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
95 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
96 * pci=hpmemsize=nnM overrides both
97 */
98unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
99unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
100
101#define DEFAULT_HOTPLUG_BUS_SIZE 1
102unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
103
104enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
105
106/*
107 * The default CLS is used if arch didn't set CLS explicitly and not
108 * all pci devices agree on the same value. Arch can override either
109 * the dfl or actual value as it sees fit. Don't forget this is
110 * measured in 32-bit words, not bytes.
111 */
112u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
113u8 pci_cache_line_size;
114
115/*
116 * If we set up a device for bus mastering, we need to check the latency
117 * timer as certain BIOSes forget to set it properly.
118 */
119unsigned int pcibios_max_latency = 255;
120
121/* If set, the PCIe ARI capability will not be used. */
122static bool pcie_ari_disabled;
123
124/* If set, the PCIe ATS capability will not be used. */
125static bool pcie_ats_disabled;
126
127/* If set, the PCI config space of each device is printed during boot. */
128bool pci_early_dump;
129
130bool pci_ats_disabled(void)
131{
132 return pcie_ats_disabled;
133}
134EXPORT_SYMBOL_GPL(pci_ats_disabled);
135
136/* Disable bridge_d3 for all PCIe ports */
137static bool pci_bridge_d3_disable;
138/* Force bridge_d3 for all PCIe ports */
139static bool pci_bridge_d3_force;
140
141static int __init pcie_port_pm_setup(char *str)
142{
143 if (!strcmp(str, "off"))
144 pci_bridge_d3_disable = true;
145 else if (!strcmp(str, "force"))
146 pci_bridge_d3_force = true;
147 return 1;
148}
149__setup("pcie_port_pm=", pcie_port_pm_setup);
150
151/* Time to wait after a reset for device to become responsive */
152#define PCIE_RESET_READY_POLL_MS 60000
153
154/**
155 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
156 * @bus: pointer to PCI bus structure to search
157 *
158 * Given a PCI bus, returns the highest PCI bus number present in the set
159 * including the given PCI bus and its list of child PCI buses.
160 */
161unsigned char pci_bus_max_busnr(struct pci_bus *bus)
162{
163 struct pci_bus *tmp;
164 unsigned char max, n;
165
166 max = bus->busn_res.end;
167 list_for_each_entry(tmp, &bus->children, node) {
168 n = pci_bus_max_busnr(tmp);
169 if (n > max)
170 max = n;
171 }
172 return max;
173}
174EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
175
176/**
177 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
178 * @pdev: the PCI device
179 *
180 * Returns error bits set in PCI_STATUS and clears them.
181 */
182int pci_status_get_and_clear_errors(struct pci_dev *pdev)
183{
184 u16 status;
185 int ret;
186
187 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
188 if (ret != PCIBIOS_SUCCESSFUL)
189 return -EIO;
190
191 status &= PCI_STATUS_ERROR_BITS;
192 if (status)
193 pci_write_config_word(pdev, PCI_STATUS, status);
194
195 return status;
196}
197EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
198
199#ifdef CONFIG_HAS_IOMEM
200void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
201{
202 struct resource *res = &pdev->resource[bar];
203
204 /*
205 * Make sure the BAR is actually a memory resource, not an IO resource
206 */
207 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
208 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
209 return NULL;
210 }
211 return ioremap(res->start, resource_size(res));
212}
213EXPORT_SYMBOL_GPL(pci_ioremap_bar);
214
215void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
216{
217 /*
218 * Make sure the BAR is actually a memory resource, not an IO resource
219 */
220 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
221 WARN_ON(1);
222 return NULL;
223 }
224 return ioremap_wc(pci_resource_start(pdev, bar),
225 pci_resource_len(pdev, bar));
226}
227EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
228#endif
229
230/**
231 * pci_dev_str_match_path - test if a path string matches a device
232 * @dev: the PCI device to test
233 * @path: string to match the device against
234 * @endptr: pointer to the string after the match
235 *
236 * Test if a string (typically from a kernel parameter) formatted as a
237 * path of device/function addresses matches a PCI device. The string must
238 * be of the form:
239 *
240 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
241 *
242 * A path for a device can be obtained using 'lspci -t'. Using a path
243 * is more robust against bus renumbering than using only a single bus,
244 * device and function address.
245 *
246 * Returns 1 if the string matches the device, 0 if it does not and
247 * a negative error code if it fails to parse the string.
248 */
249static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
250 const char **endptr)
251{
252 int ret;
253 int seg, bus, slot, func;
254 char *wpath, *p;
255 char end;
256
257 *endptr = strchrnul(path, ';');
258
259 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
260 if (!wpath)
261 return -ENOMEM;
262
263 while (1) {
264 p = strrchr(wpath, '/');
265 if (!p)
266 break;
267 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
268 if (ret != 2) {
269 ret = -EINVAL;
270 goto free_and_exit;
271 }
272
273 if (dev->devfn != PCI_DEVFN(slot, func)) {
274 ret = 0;
275 goto free_and_exit;
276 }
277
278 /*
279 * Note: we don't need to get a reference to the upstream
280 * bridge because we hold a reference to the top level
281 * device which should hold a reference to the bridge,
282 * and so on.
283 */
284 dev = pci_upstream_bridge(dev);
285 if (!dev) {
286 ret = 0;
287 goto free_and_exit;
288 }
289
290 *p = 0;
291 }
292
293 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
294 &func, &end);
295 if (ret != 4) {
296 seg = 0;
297 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
298 if (ret != 3) {
299 ret = -EINVAL;
300 goto free_and_exit;
301 }
302 }
303
304 ret = (seg == pci_domain_nr(dev->bus) &&
305 bus == dev->bus->number &&
306 dev->devfn == PCI_DEVFN(slot, func));
307
308free_and_exit:
309 kfree(wpath);
310 return ret;
311}
312
313/**
314 * pci_dev_str_match - test if a string matches a device
315 * @dev: the PCI device to test
316 * @p: string to match the device against
317 * @endptr: pointer to the string after the match
318 *
319 * Test if a string (typically from a kernel parameter) matches a specified
320 * PCI device. The string may be of one of the following formats:
321 *
322 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
323 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
324 *
325 * The first format specifies a PCI bus/device/function address which
326 * may change if new hardware is inserted, if motherboard firmware changes,
327 * or due to changes caused in kernel parameters. If the domain is
328 * left unspecified, it is taken to be 0. In order to be robust against
329 * bus renumbering issues, a path of PCI device/function numbers may be used
330 * to address the specific device. The path for a device can be determined
331 * through the use of 'lspci -t'.
332 *
333 * The second format matches devices using IDs in the configuration
334 * space which may match multiple devices in the system. A value of 0
335 * for any field will match all devices. (Note: this differs from
336 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
337 * legacy reasons and convenience so users don't have to specify
338 * FFFFFFFFs on the command line.)
339 *
340 * Returns 1 if the string matches the device, 0 if it does not and
341 * a negative error code if the string cannot be parsed.
342 */
343static int pci_dev_str_match(struct pci_dev *dev, const char *p,
344 const char **endptr)
345{
346 int ret;
347 int count;
348 unsigned short vendor, device, subsystem_vendor, subsystem_device;
349
350 if (strncmp(p, "pci:", 4) == 0) {
351 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
352 p += 4;
353 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
354 &subsystem_vendor, &subsystem_device, &count);
355 if (ret != 4) {
356 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
357 if (ret != 2)
358 return -EINVAL;
359
360 subsystem_vendor = 0;
361 subsystem_device = 0;
362 }
363
364 p += count;
365
366 if ((!vendor || vendor == dev->vendor) &&
367 (!device || device == dev->device) &&
368 (!subsystem_vendor ||
369 subsystem_vendor == dev->subsystem_vendor) &&
370 (!subsystem_device ||
371 subsystem_device == dev->subsystem_device))
372 goto found;
373 } else {
374 /*
375 * PCI Bus, Device, Function IDs are specified
376 * (optionally, may include a path of devfns following it)
377 */
378 ret = pci_dev_str_match_path(dev, p, &p);
379 if (ret < 0)
380 return ret;
381 else if (ret)
382 goto found;
383 }
384
385 *endptr = p;
386 return 0;
387
388found:
389 *endptr = p;
390 return 1;
391}
392
393static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
394 u8 pos, int cap, int *ttl)
395{
396 u8 id;
397 u16 ent;
398
399 pci_bus_read_config_byte(bus, devfn, pos, &pos);
400
401 while ((*ttl)--) {
402 if (pos < 0x40)
403 break;
404 pos &= ~3;
405 pci_bus_read_config_word(bus, devfn, pos, &ent);
406
407 id = ent & 0xff;
408 if (id == 0xff)
409 break;
410 if (id == cap)
411 return pos;
412 pos = (ent >> 8);
413 }
414 return 0;
415}
416
417static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
418 u8 pos, int cap)
419{
420 int ttl = PCI_FIND_CAP_TTL;
421
422 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
423}
424
425int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
426{
427 return __pci_find_next_cap(dev->bus, dev->devfn,
428 pos + PCI_CAP_LIST_NEXT, cap);
429}
430EXPORT_SYMBOL_GPL(pci_find_next_capability);
431
432static int __pci_bus_find_cap_start(struct pci_bus *bus,
433 unsigned int devfn, u8 hdr_type)
434{
435 u16 status;
436
437 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
438 if (!(status & PCI_STATUS_CAP_LIST))
439 return 0;
440
441 switch (hdr_type) {
442 case PCI_HEADER_TYPE_NORMAL:
443 case PCI_HEADER_TYPE_BRIDGE:
444 return PCI_CAPABILITY_LIST;
445 case PCI_HEADER_TYPE_CARDBUS:
446 return PCI_CB_CAPABILITY_LIST;
447 }
448
449 return 0;
450}
451
452/**
453 * pci_find_capability - query for devices' capabilities
454 * @dev: PCI device to query
455 * @cap: capability code
456 *
457 * Tell if a device supports a given PCI capability.
458 * Returns the address of the requested capability structure within the
459 * device's PCI configuration space or 0 in case the device does not
460 * support it. Possible values for @cap include:
461 *
462 * %PCI_CAP_ID_PM Power Management
463 * %PCI_CAP_ID_AGP Accelerated Graphics Port
464 * %PCI_CAP_ID_VPD Vital Product Data
465 * %PCI_CAP_ID_SLOTID Slot Identification
466 * %PCI_CAP_ID_MSI Message Signalled Interrupts
467 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
468 * %PCI_CAP_ID_PCIX PCI-X
469 * %PCI_CAP_ID_EXP PCI Express
470 */
471int pci_find_capability(struct pci_dev *dev, int cap)
472{
473 int pos;
474
475 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
476 if (pos)
477 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
478
479 return pos;
480}
481EXPORT_SYMBOL(pci_find_capability);
482
483/**
484 * pci_bus_find_capability - query for devices' capabilities
485 * @bus: the PCI bus to query
486 * @devfn: PCI device to query
487 * @cap: capability code
488 *
489 * Like pci_find_capability() but works for PCI devices that do not have a
490 * pci_dev structure set up yet.
491 *
492 * Returns the address of the requested capability structure within the
493 * device's PCI configuration space or 0 in case the device does not
494 * support it.
495 */
496int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
497{
498 int pos;
499 u8 hdr_type;
500
501 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
502
503 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
504 if (pos)
505 pos = __pci_find_next_cap(bus, devfn, pos, cap);
506
507 return pos;
508}
509EXPORT_SYMBOL(pci_bus_find_capability);
510
511/**
512 * pci_find_next_ext_capability - Find an extended capability
513 * @dev: PCI device to query
514 * @start: address at which to start looking (0 to start at beginning of list)
515 * @cap: capability code
516 *
517 * Returns the address of the next matching extended capability structure
518 * within the device's PCI configuration space or 0 if the device does
519 * not support it. Some capabilities can occur several times, e.g., the
520 * vendor-specific capability, and this provides a way to find them all.
521 */
522int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
523{
524 u32 header;
525 int ttl;
526 int pos = PCI_CFG_SPACE_SIZE;
527
528 /* minimum 8 bytes per capability */
529 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
530
531 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
532 return 0;
533
534 if (start)
535 pos = start;
536
537 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
538 return 0;
539
540 /*
541 * If we have no capabilities, this is indicated by cap ID,
542 * cap version and next pointer all being 0.
543 */
544 if (header == 0)
545 return 0;
546
547 while (ttl-- > 0) {
548 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
549 return pos;
550
551 pos = PCI_EXT_CAP_NEXT(header);
552 if (pos < PCI_CFG_SPACE_SIZE)
553 break;
554
555 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
556 break;
557 }
558
559 return 0;
560}
561EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
562
563/**
564 * pci_find_ext_capability - Find an extended capability
565 * @dev: PCI device to query
566 * @cap: capability code
567 *
568 * Returns the address of the requested extended capability structure
569 * within the device's PCI configuration space or 0 if the device does
570 * not support it. Possible values for @cap include:
571 *
572 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
573 * %PCI_EXT_CAP_ID_VC Virtual Channel
574 * %PCI_EXT_CAP_ID_DSN Device Serial Number
575 * %PCI_EXT_CAP_ID_PWR Power Budgeting
576 */
577int pci_find_ext_capability(struct pci_dev *dev, int cap)
578{
579 return pci_find_next_ext_capability(dev, 0, cap);
580}
581EXPORT_SYMBOL_GPL(pci_find_ext_capability);
582
583/**
584 * pci_get_dsn - Read and return the 8-byte Device Serial Number
585 * @dev: PCI device to query
586 *
587 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
588 * Number.
589 *
590 * Returns the DSN, or zero if the capability does not exist.
591 */
592u64 pci_get_dsn(struct pci_dev *dev)
593{
594 u32 dword;
595 u64 dsn;
596 int pos;
597
598 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
599 if (!pos)
600 return 0;
601
602 /*
603 * The Device Serial Number is two dwords offset 4 bytes from the
604 * capability position. The specification says that the first dword is
605 * the lower half, and the second dword is the upper half.
606 */
607 pos += 4;
608 pci_read_config_dword(dev, pos, &dword);
609 dsn = (u64)dword;
610 pci_read_config_dword(dev, pos + 4, &dword);
611 dsn |= ((u64)dword) << 32;
612
613 return dsn;
614}
615EXPORT_SYMBOL_GPL(pci_get_dsn);
616
617static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
618{
619 int rc, ttl = PCI_FIND_CAP_TTL;
620 u8 cap, mask;
621
622 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
623 mask = HT_3BIT_CAP_MASK;
624 else
625 mask = HT_5BIT_CAP_MASK;
626
627 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
628 PCI_CAP_ID_HT, &ttl);
629 while (pos) {
630 rc = pci_read_config_byte(dev, pos + 3, &cap);
631 if (rc != PCIBIOS_SUCCESSFUL)
632 return 0;
633
634 if ((cap & mask) == ht_cap)
635 return pos;
636
637 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
638 pos + PCI_CAP_LIST_NEXT,
639 PCI_CAP_ID_HT, &ttl);
640 }
641
642 return 0;
643}
644/**
645 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
646 * @dev: PCI device to query
647 * @pos: Position from which to continue searching
648 * @ht_cap: Hypertransport capability code
649 *
650 * To be used in conjunction with pci_find_ht_capability() to search for
651 * all capabilities matching @ht_cap. @pos should always be a value returned
652 * from pci_find_ht_capability().
653 *
654 * NB. To be 100% safe against broken PCI devices, the caller should take
655 * steps to avoid an infinite loop.
656 */
657int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
658{
659 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
660}
661EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
662
663/**
664 * pci_find_ht_capability - query a device's Hypertransport capabilities
665 * @dev: PCI device to query
666 * @ht_cap: Hypertransport capability code
667 *
668 * Tell if a device supports a given Hypertransport capability.
669 * Returns an address within the device's PCI configuration space
670 * or 0 in case the device does not support the request capability.
671 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
672 * which has a Hypertransport capability matching @ht_cap.
673 */
674int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
675{
676 int pos;
677
678 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
679 if (pos)
680 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
681
682 return pos;
683}
684EXPORT_SYMBOL_GPL(pci_find_ht_capability);
685
686/**
687 * pci_find_parent_resource - return resource region of parent bus of given
688 * region
689 * @dev: PCI device structure contains resources to be searched
690 * @res: child resource record for which parent is sought
691 *
692 * For given resource region of given device, return the resource region of
693 * parent bus the given region is contained in.
694 */
695struct resource *pci_find_parent_resource(const struct pci_dev *dev,
696 struct resource *res)
697{
698 const struct pci_bus *bus = dev->bus;
699 struct resource *r;
700 int i;
701
702 pci_bus_for_each_resource(bus, r, i) {
703 if (!r)
704 continue;
705 if (resource_contains(r, res)) {
706
707 /*
708 * If the window is prefetchable but the BAR is
709 * not, the allocator made a mistake.
710 */
711 if (r->flags & IORESOURCE_PREFETCH &&
712 !(res->flags & IORESOURCE_PREFETCH))
713 return NULL;
714
715 /*
716 * If we're below a transparent bridge, there may
717 * be both a positively-decoded aperture and a
718 * subtractively-decoded region that contain the BAR.
719 * We want the positively-decoded one, so this depends
720 * on pci_bus_for_each_resource() giving us those
721 * first.
722 */
723 return r;
724 }
725 }
726 return NULL;
727}
728EXPORT_SYMBOL(pci_find_parent_resource);
729
730/**
731 * pci_find_resource - Return matching PCI device resource
732 * @dev: PCI device to query
733 * @res: Resource to look for
734 *
735 * Goes over standard PCI resources (BARs) and checks if the given resource
736 * is partially or fully contained in any of them. In that case the
737 * matching resource is returned, %NULL otherwise.
738 */
739struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
740{
741 int i;
742
743 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
744 struct resource *r = &dev->resource[i];
745
746 if (r->start && resource_contains(r, res))
747 return r;
748 }
749
750 return NULL;
751}
752EXPORT_SYMBOL(pci_find_resource);
753
754/**
755 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
756 * @dev: the PCI device to operate on
757 * @pos: config space offset of status word
758 * @mask: mask of bit(s) to care about in status word
759 *
760 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
761 */
762int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
763{
764 int i;
765
766 /* Wait for Transaction Pending bit clean */
767 for (i = 0; i < 4; i++) {
768 u16 status;
769 if (i)
770 msleep((1 << (i - 1)) * 100);
771
772 pci_read_config_word(dev, pos, &status);
773 if (!(status & mask))
774 return 1;
775 }
776
777 return 0;
778}
779
780static int pci_acs_enable;
781
782/**
783 * pci_request_acs - ask for ACS to be enabled if supported
784 */
785void pci_request_acs(void)
786{
787 pci_acs_enable = 1;
788}
789
790static const char *disable_acs_redir_param;
791
792/**
793 * pci_disable_acs_redir - disable ACS redirect capabilities
794 * @dev: the PCI device
795 *
796 * For only devices specified in the disable_acs_redir parameter.
797 */
798static void pci_disable_acs_redir(struct pci_dev *dev)
799{
800 int ret = 0;
801 const char *p;
802 int pos;
803 u16 ctrl;
804
805 if (!disable_acs_redir_param)
806 return;
807
808 p = disable_acs_redir_param;
809 while (*p) {
810 ret = pci_dev_str_match(dev, p, &p);
811 if (ret < 0) {
812 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
813 disable_acs_redir_param);
814
815 break;
816 } else if (ret == 1) {
817 /* Found a match */
818 break;
819 }
820
821 if (*p != ';' && *p != ',') {
822 /* End of param or invalid format */
823 break;
824 }
825 p++;
826 }
827
828 if (ret != 1)
829 return;
830
831 if (!pci_dev_specific_disable_acs_redir(dev))
832 return;
833
834 pos = dev->acs_cap;
835 if (!pos) {
836 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
837 return;
838 }
839
840 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
841
842 /* P2P Request & Completion Redirect */
843 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
844
845 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
846
847 pci_info(dev, "disabled ACS redirect\n");
848}
849
850/**
851 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
852 * @dev: the PCI device
853 */
854static void pci_std_enable_acs(struct pci_dev *dev)
855{
856 int pos;
857 u16 cap;
858 u16 ctrl;
859
860 pos = dev->acs_cap;
861 if (!pos)
862 return;
863
864 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
865 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
866
867 /* Source Validation */
868 ctrl |= (cap & PCI_ACS_SV);
869
870 /* P2P Request Redirect */
871 ctrl |= (cap & PCI_ACS_RR);
872
873 /* P2P Completion Redirect */
874 ctrl |= (cap & PCI_ACS_CR);
875
876 /* Upstream Forwarding */
877 ctrl |= (cap & PCI_ACS_UF);
878
879 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
880}
881
882/**
883 * pci_enable_acs - enable ACS if hardware support it
884 * @dev: the PCI device
885 */
886static void pci_enable_acs(struct pci_dev *dev)
887{
888 if (!pci_acs_enable)
889 goto disable_acs_redir;
890
891 if (!pci_dev_specific_enable_acs(dev))
892 goto disable_acs_redir;
893
894 pci_std_enable_acs(dev);
895
896disable_acs_redir:
897 /*
898 * Note: pci_disable_acs_redir() must be called even if ACS was not
899 * enabled by the kernel because it may have been enabled by
900 * platform firmware. So if we are told to disable it, we should
901 * always disable it after setting the kernel's default
902 * preferences.
903 */
904 pci_disable_acs_redir(dev);
905}
906
907/**
908 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
909 * @dev: PCI device to have its BARs restored
910 *
911 * Restore the BAR values for a given device, so as to make it
912 * accessible by its driver.
913 */
914static void pci_restore_bars(struct pci_dev *dev)
915{
916 int i;
917
918 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
919 pci_update_resource(dev, i);
920}
921
922static const struct pci_platform_pm_ops *pci_platform_pm;
923
924int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
925{
926 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
927 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
928 return -EINVAL;
929 pci_platform_pm = ops;
930 return 0;
931}
932
933static inline bool platform_pci_power_manageable(struct pci_dev *dev)
934{
935 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
936}
937
938static inline int platform_pci_set_power_state(struct pci_dev *dev,
939 pci_power_t t)
940{
941 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
942}
943
944static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
945{
946 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
947}
948
949static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
950{
951 if (pci_platform_pm && pci_platform_pm->refresh_state)
952 pci_platform_pm->refresh_state(dev);
953}
954
955static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
956{
957 return pci_platform_pm ?
958 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
959}
960
961static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
962{
963 return pci_platform_pm ?
964 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
965}
966
967static inline bool platform_pci_need_resume(struct pci_dev *dev)
968{
969 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
970}
971
972static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
973{
974 if (pci_platform_pm && pci_platform_pm->bridge_d3)
975 return pci_platform_pm->bridge_d3(dev);
976 return false;
977}
978
979/**
980 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
981 * given PCI device
982 * @dev: PCI device to handle.
983 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
984 *
985 * RETURN VALUE:
986 * -EINVAL if the requested state is invalid.
987 * -EIO if device does not support PCI PM or its PM capabilities register has a
988 * wrong version, or device doesn't support the requested state.
989 * 0 if device already is in the requested state.
990 * 0 if device's power state has been successfully changed.
991 */
992static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
993{
994 u16 pmcsr;
995 bool need_restore = false;
996
997 /* Check if we're already there */
998 if (dev->current_state == state)
999 return 0;
1000
1001 if (!dev->pm_cap)
1002 return -EIO;
1003
1004 if (state < PCI_D0 || state > PCI_D3hot)
1005 return -EINVAL;
1006
1007 /*
1008 * Validate transition: We can enter D0 from any state, but if
1009 * we're already in a low-power state, we can only go deeper. E.g.,
1010 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1011 * we'd have to go from D3 to D0, then to D1.
1012 */
1013 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1014 && dev->current_state > state) {
1015 pci_err(dev, "invalid power transition (from %s to %s)\n",
1016 pci_power_name(dev->current_state),
1017 pci_power_name(state));
1018 return -EINVAL;
1019 }
1020
1021 /* Check if this device supports the desired state */
1022 if ((state == PCI_D1 && !dev->d1_support)
1023 || (state == PCI_D2 && !dev->d2_support))
1024 return -EIO;
1025
1026 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1027 if (pmcsr == (u16) ~0) {
1028 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1029 pci_power_name(dev->current_state),
1030 pci_power_name(state));
1031 return -EIO;
1032 }
1033
1034 /*
1035 * If we're (effectively) in D3, force entire word to 0.
1036 * This doesn't affect PME_Status, disables PME_En, and
1037 * sets PowerState to 0.
1038 */
1039 switch (dev->current_state) {
1040 case PCI_D0:
1041 case PCI_D1:
1042 case PCI_D2:
1043 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1044 pmcsr |= state;
1045 break;
1046 case PCI_D3hot:
1047 case PCI_D3cold:
1048 case PCI_UNKNOWN: /* Boot-up */
1049 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1050 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1051 need_restore = true;
1052 fallthrough; /* force to D0 */
1053 default:
1054 pmcsr = 0;
1055 break;
1056 }
1057
1058 /* Enter specified state */
1059 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1060
1061 /*
1062 * Mandatory power management transition delays; see PCI PM 1.1
1063 * 5.6.1 table 18
1064 */
1065 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1066 pci_dev_d3_sleep(dev);
1067 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1068 msleep(PCI_PM_D2_DELAY);
1069
1070 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1071 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1072 if (dev->current_state != state)
1073 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1074 pci_power_name(dev->current_state),
1075 pci_power_name(state));
1076
1077 /*
1078 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1079 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1080 * from D3hot to D0 _may_ perform an internal reset, thereby
1081 * going to "D0 Uninitialized" rather than "D0 Initialized".
1082 * For example, at least some versions of the 3c905B and the
1083 * 3c556B exhibit this behaviour.
1084 *
1085 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1086 * devices in a D3hot state at boot. Consequently, we need to
1087 * restore at least the BARs so that the device will be
1088 * accessible to its driver.
1089 */
1090 if (need_restore)
1091 pci_restore_bars(dev);
1092
1093 if (dev->bus->self)
1094 pcie_aspm_pm_state_change(dev->bus->self);
1095
1096 return 0;
1097}
1098
1099/**
1100 * pci_update_current_state - Read power state of given device and cache it
1101 * @dev: PCI device to handle.
1102 * @state: State to cache in case the device doesn't have the PM capability
1103 *
1104 * The power state is read from the PMCSR register, which however is
1105 * inaccessible in D3cold. The platform firmware is therefore queried first
1106 * to detect accessibility of the register. In case the platform firmware
1107 * reports an incorrect state or the device isn't power manageable by the
1108 * platform at all, we try to detect D3cold by testing accessibility of the
1109 * vendor ID in config space.
1110 */
1111void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1112{
1113 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1114 !pci_device_is_present(dev)) {
1115 dev->current_state = PCI_D3cold;
1116 } else if (dev->pm_cap) {
1117 u16 pmcsr;
1118
1119 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1120 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1121 } else {
1122 dev->current_state = state;
1123 }
1124}
1125
1126/**
1127 * pci_refresh_power_state - Refresh the given device's power state data
1128 * @dev: Target PCI device.
1129 *
1130 * Ask the platform to refresh the devices power state information and invoke
1131 * pci_update_current_state() to update its current PCI power state.
1132 */
1133void pci_refresh_power_state(struct pci_dev *dev)
1134{
1135 if (platform_pci_power_manageable(dev))
1136 platform_pci_refresh_power_state(dev);
1137
1138 pci_update_current_state(dev, dev->current_state);
1139}
1140
1141/**
1142 * pci_platform_power_transition - Use platform to change device power state
1143 * @dev: PCI device to handle.
1144 * @state: State to put the device into.
1145 */
1146int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1147{
1148 int error;
1149
1150 if (platform_pci_power_manageable(dev)) {
1151 error = platform_pci_set_power_state(dev, state);
1152 if (!error)
1153 pci_update_current_state(dev, state);
1154 } else
1155 error = -ENODEV;
1156
1157 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1158 dev->current_state = PCI_D0;
1159
1160 return error;
1161}
1162EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1163
1164/**
1165 * pci_wakeup - Wake up a PCI device
1166 * @pci_dev: Device to handle.
1167 * @ign: ignored parameter
1168 */
1169static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1170{
1171 pci_wakeup_event(pci_dev);
1172 pm_request_resume(&pci_dev->dev);
1173 return 0;
1174}
1175
1176/**
1177 * pci_wakeup_bus - Walk given bus and wake up devices on it
1178 * @bus: Top bus of the subtree to walk.
1179 */
1180void pci_wakeup_bus(struct pci_bus *bus)
1181{
1182 if (bus)
1183 pci_walk_bus(bus, pci_wakeup, NULL);
1184}
1185
1186static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1187{
1188 int delay = 1;
1189 u32 id;
1190
1191 /*
1192 * After reset, the device should not silently discard config
1193 * requests, but it may still indicate that it needs more time by
1194 * responding to them with CRS completions. The Root Port will
1195 * generally synthesize ~0 data to complete the read (except when
1196 * CRS SV is enabled and the read was for the Vendor ID; in that
1197 * case it synthesizes 0x0001 data).
1198 *
1199 * Wait for the device to return a non-CRS completion. Read the
1200 * Command register instead of Vendor ID so we don't have to
1201 * contend with the CRS SV value.
1202 */
1203 pci_read_config_dword(dev, PCI_COMMAND, &id);
1204 while (id == ~0) {
1205 if (delay > timeout) {
1206 pci_warn(dev, "not ready %dms after %s; giving up\n",
1207 delay - 1, reset_type);
1208 return -ENOTTY;
1209 }
1210
1211 if (delay > 1000)
1212 pci_info(dev, "not ready %dms after %s; waiting\n",
1213 delay - 1, reset_type);
1214
1215 msleep(delay);
1216 delay *= 2;
1217 pci_read_config_dword(dev, PCI_COMMAND, &id);
1218 }
1219
1220 if (delay > 1000)
1221 pci_info(dev, "ready %dms after %s\n", delay - 1,
1222 reset_type);
1223
1224 return 0;
1225}
1226
1227/**
1228 * pci_power_up - Put the given device into D0
1229 * @dev: PCI device to power up
1230 */
1231int pci_power_up(struct pci_dev *dev)
1232{
1233 pci_platform_power_transition(dev, PCI_D0);
1234
1235 /*
1236 * Mandatory power management transition delays are handled in
1237 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1238 * corresponding bridge.
1239 */
1240 if (dev->runtime_d3cold) {
1241 /*
1242 * When powering on a bridge from D3cold, the whole hierarchy
1243 * may be powered on into D0uninitialized state, resume them to
1244 * give them a chance to suspend again
1245 */
1246 pci_wakeup_bus(dev->subordinate);
1247 }
1248
1249 return pci_raw_set_power_state(dev, PCI_D0);
1250}
1251
1252/**
1253 * __pci_dev_set_current_state - Set current state of a PCI device
1254 * @dev: Device to handle
1255 * @data: pointer to state to be set
1256 */
1257static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1258{
1259 pci_power_t state = *(pci_power_t *)data;
1260
1261 dev->current_state = state;
1262 return 0;
1263}
1264
1265/**
1266 * pci_bus_set_current_state - Walk given bus and set current state of devices
1267 * @bus: Top bus of the subtree to walk.
1268 * @state: state to be set
1269 */
1270void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1271{
1272 if (bus)
1273 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1274}
1275
1276/**
1277 * pci_set_power_state - Set the power state of a PCI device
1278 * @dev: PCI device to handle.
1279 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1280 *
1281 * Transition a device to a new power state, using the platform firmware and/or
1282 * the device's PCI PM registers.
1283 *
1284 * RETURN VALUE:
1285 * -EINVAL if the requested state is invalid.
1286 * -EIO if device does not support PCI PM or its PM capabilities register has a
1287 * wrong version, or device doesn't support the requested state.
1288 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1289 * 0 if device already is in the requested state.
1290 * 0 if the transition is to D3 but D3 is not supported.
1291 * 0 if device's power state has been successfully changed.
1292 */
1293int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1294{
1295 int error;
1296
1297 /* Bound the state we're entering */
1298 if (state > PCI_D3cold)
1299 state = PCI_D3cold;
1300 else if (state < PCI_D0)
1301 state = PCI_D0;
1302 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1303
1304 /*
1305 * If the device or the parent bridge do not support PCI
1306 * PM, ignore the request if we're doing anything other
1307 * than putting it into D0 (which would only happen on
1308 * boot).
1309 */
1310 return 0;
1311
1312 /* Check if we're already there */
1313 if (dev->current_state == state)
1314 return 0;
1315
1316 if (state == PCI_D0)
1317 return pci_power_up(dev);
1318
1319 /*
1320 * This device is quirked not to be put into D3, so don't put it in
1321 * D3
1322 */
1323 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1324 return 0;
1325
1326 /*
1327 * To put device in D3cold, we put device into D3hot in native
1328 * way, then put device into D3cold with platform ops
1329 */
1330 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1331 PCI_D3hot : state);
1332
1333 if (pci_platform_power_transition(dev, state))
1334 return error;
1335
1336 /* Powering off a bridge may power off the whole hierarchy */
1337 if (state == PCI_D3cold)
1338 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1339
1340 return 0;
1341}
1342EXPORT_SYMBOL(pci_set_power_state);
1343
1344/**
1345 * pci_choose_state - Choose the power state of a PCI device
1346 * @dev: PCI device to be suspended
1347 * @state: target sleep state for the whole system. This is the value
1348 * that is passed to suspend() function.
1349 *
1350 * Returns PCI power state suitable for given device and given system
1351 * message.
1352 */
1353pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1354{
1355 pci_power_t ret;
1356
1357 if (!dev->pm_cap)
1358 return PCI_D0;
1359
1360 ret = platform_pci_choose_state(dev);
1361 if (ret != PCI_POWER_ERROR)
1362 return ret;
1363
1364 switch (state.event) {
1365 case PM_EVENT_ON:
1366 return PCI_D0;
1367 case PM_EVENT_FREEZE:
1368 case PM_EVENT_PRETHAW:
1369 /* REVISIT both freeze and pre-thaw "should" use D0 */
1370 case PM_EVENT_SUSPEND:
1371 case PM_EVENT_HIBERNATE:
1372 return PCI_D3hot;
1373 default:
1374 pci_info(dev, "unrecognized suspend event %d\n",
1375 state.event);
1376 BUG();
1377 }
1378 return PCI_D0;
1379}
1380EXPORT_SYMBOL(pci_choose_state);
1381
1382#define PCI_EXP_SAVE_REGS 7
1383
1384static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1385 u16 cap, bool extended)
1386{
1387 struct pci_cap_saved_state *tmp;
1388
1389 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1390 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1391 return tmp;
1392 }
1393 return NULL;
1394}
1395
1396struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1397{
1398 return _pci_find_saved_cap(dev, cap, false);
1399}
1400
1401struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1402{
1403 return _pci_find_saved_cap(dev, cap, true);
1404}
1405
1406static int pci_save_pcie_state(struct pci_dev *dev)
1407{
1408 int i = 0;
1409 struct pci_cap_saved_state *save_state;
1410 u16 *cap;
1411
1412 if (!pci_is_pcie(dev))
1413 return 0;
1414
1415 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1416 if (!save_state) {
1417 pci_err(dev, "buffer not found in %s\n", __func__);
1418 return -ENOMEM;
1419 }
1420
1421 cap = (u16 *)&save_state->cap.data[0];
1422 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1423 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1424 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1425 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1426 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1427 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1428 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1429
1430 return 0;
1431}
1432
1433static void pci_restore_pcie_state(struct pci_dev *dev)
1434{
1435 int i = 0;
1436 struct pci_cap_saved_state *save_state;
1437 u16 *cap;
1438
1439 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1440 if (!save_state)
1441 return;
1442
1443 cap = (u16 *)&save_state->cap.data[0];
1444 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1445 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1446 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1447 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1448 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1449 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1450 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1451}
1452
1453static int pci_save_pcix_state(struct pci_dev *dev)
1454{
1455 int pos;
1456 struct pci_cap_saved_state *save_state;
1457
1458 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1459 if (!pos)
1460 return 0;
1461
1462 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1463 if (!save_state) {
1464 pci_err(dev, "buffer not found in %s\n", __func__);
1465 return -ENOMEM;
1466 }
1467
1468 pci_read_config_word(dev, pos + PCI_X_CMD,
1469 (u16 *)save_state->cap.data);
1470
1471 return 0;
1472}
1473
1474static void pci_restore_pcix_state(struct pci_dev *dev)
1475{
1476 int i = 0, pos;
1477 struct pci_cap_saved_state *save_state;
1478 u16 *cap;
1479
1480 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1481 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1482 if (!save_state || !pos)
1483 return;
1484 cap = (u16 *)&save_state->cap.data[0];
1485
1486 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1487}
1488
1489static void pci_save_ltr_state(struct pci_dev *dev)
1490{
1491 int ltr;
1492 struct pci_cap_saved_state *save_state;
1493 u16 *cap;
1494
1495 if (!pci_is_pcie(dev))
1496 return;
1497
1498 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1499 if (!ltr)
1500 return;
1501
1502 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1503 if (!save_state) {
1504 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1505 return;
1506 }
1507
1508 cap = (u16 *)&save_state->cap.data[0];
1509 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1510 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1511}
1512
1513static void pci_restore_ltr_state(struct pci_dev *dev)
1514{
1515 struct pci_cap_saved_state *save_state;
1516 int ltr;
1517 u16 *cap;
1518
1519 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1520 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1521 if (!save_state || !ltr)
1522 return;
1523
1524 cap = (u16 *)&save_state->cap.data[0];
1525 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1526 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1527}
1528
1529/**
1530 * pci_save_state - save the PCI configuration space of a device before
1531 * suspending
1532 * @dev: PCI device that we're dealing with
1533 */
1534int pci_save_state(struct pci_dev *dev)
1535{
1536 int i;
1537 /* XXX: 100% dword access ok here? */
1538 for (i = 0; i < 16; i++) {
1539 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1540 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1541 i * 4, dev->saved_config_space[i]);
1542 }
1543 dev->state_saved = true;
1544
1545 i = pci_save_pcie_state(dev);
1546 if (i != 0)
1547 return i;
1548
1549 i = pci_save_pcix_state(dev);
1550 if (i != 0)
1551 return i;
1552
1553 pci_save_ltr_state(dev);
1554 pci_save_dpc_state(dev);
1555 pci_save_aer_state(dev);
1556 return pci_save_vc_state(dev);
1557}
1558EXPORT_SYMBOL(pci_save_state);
1559
1560static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1561 u32 saved_val, int retry, bool force)
1562{
1563 u32 val;
1564
1565 pci_read_config_dword(pdev, offset, &val);
1566 if (!force && val == saved_val)
1567 return;
1568
1569 for (;;) {
1570 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1571 offset, val, saved_val);
1572 pci_write_config_dword(pdev, offset, saved_val);
1573 if (retry-- <= 0)
1574 return;
1575
1576 pci_read_config_dword(pdev, offset, &val);
1577 if (val == saved_val)
1578 return;
1579
1580 mdelay(1);
1581 }
1582}
1583
1584static void pci_restore_config_space_range(struct pci_dev *pdev,
1585 int start, int end, int retry,
1586 bool force)
1587{
1588 int index;
1589
1590 for (index = end; index >= start; index--)
1591 pci_restore_config_dword(pdev, 4 * index,
1592 pdev->saved_config_space[index],
1593 retry, force);
1594}
1595
1596static void pci_restore_config_space(struct pci_dev *pdev)
1597{
1598 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1599 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1600 /* Restore BARs before the command register. */
1601 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1602 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1603 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1604 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1605
1606 /*
1607 * Force rewriting of prefetch registers to avoid S3 resume
1608 * issues on Intel PCI bridges that occur when these
1609 * registers are not explicitly written.
1610 */
1611 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1612 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1613 } else {
1614 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1615 }
1616}
1617
1618static void pci_restore_rebar_state(struct pci_dev *pdev)
1619{
1620 unsigned int pos, nbars, i;
1621 u32 ctrl;
1622
1623 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1624 if (!pos)
1625 return;
1626
1627 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1628 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1629 PCI_REBAR_CTRL_NBAR_SHIFT;
1630
1631 for (i = 0; i < nbars; i++, pos += 8) {
1632 struct resource *res;
1633 int bar_idx, size;
1634
1635 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1636 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1637 res = pdev->resource + bar_idx;
1638 size = ilog2(resource_size(res)) - 20;
1639 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1640 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1641 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1642 }
1643}
1644
1645/**
1646 * pci_restore_state - Restore the saved state of a PCI device
1647 * @dev: PCI device that we're dealing with
1648 */
1649void pci_restore_state(struct pci_dev *dev)
1650{
1651 if (!dev->state_saved)
1652 return;
1653
1654 /*
1655 * Restore max latencies (in the LTR capability) before enabling
1656 * LTR itself (in the PCIe capability).
1657 */
1658 pci_restore_ltr_state(dev);
1659
1660 pci_restore_pcie_state(dev);
1661 pci_restore_pasid_state(dev);
1662 pci_restore_pri_state(dev);
1663 pci_restore_ats_state(dev);
1664 pci_restore_vc_state(dev);
1665 pci_restore_rebar_state(dev);
1666 pci_restore_dpc_state(dev);
1667
1668 pci_aer_clear_status(dev);
1669 pci_restore_aer_state(dev);
1670
1671 pci_restore_config_space(dev);
1672
1673 pci_restore_pcix_state(dev);
1674 pci_restore_msi_state(dev);
1675
1676 /* Restore ACS and IOV configuration state */
1677 pci_enable_acs(dev);
1678 pci_restore_iov_state(dev);
1679
1680 dev->state_saved = false;
1681}
1682EXPORT_SYMBOL(pci_restore_state);
1683
1684struct pci_saved_state {
1685 u32 config_space[16];
1686 struct pci_cap_saved_data cap[];
1687};
1688
1689/**
1690 * pci_store_saved_state - Allocate and return an opaque struct containing
1691 * the device saved state.
1692 * @dev: PCI device that we're dealing with
1693 *
1694 * Return NULL if no state or error.
1695 */
1696struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1697{
1698 struct pci_saved_state *state;
1699 struct pci_cap_saved_state *tmp;
1700 struct pci_cap_saved_data *cap;
1701 size_t size;
1702
1703 if (!dev->state_saved)
1704 return NULL;
1705
1706 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1707
1708 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1709 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1710
1711 state = kzalloc(size, GFP_KERNEL);
1712 if (!state)
1713 return NULL;
1714
1715 memcpy(state->config_space, dev->saved_config_space,
1716 sizeof(state->config_space));
1717
1718 cap = state->cap;
1719 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1720 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1721 memcpy(cap, &tmp->cap, len);
1722 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1723 }
1724 /* Empty cap_save terminates list */
1725
1726 return state;
1727}
1728EXPORT_SYMBOL_GPL(pci_store_saved_state);
1729
1730/**
1731 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1732 * @dev: PCI device that we're dealing with
1733 * @state: Saved state returned from pci_store_saved_state()
1734 */
1735int pci_load_saved_state(struct pci_dev *dev,
1736 struct pci_saved_state *state)
1737{
1738 struct pci_cap_saved_data *cap;
1739
1740 dev->state_saved = false;
1741
1742 if (!state)
1743 return 0;
1744
1745 memcpy(dev->saved_config_space, state->config_space,
1746 sizeof(state->config_space));
1747
1748 cap = state->cap;
1749 while (cap->size) {
1750 struct pci_cap_saved_state *tmp;
1751
1752 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1753 if (!tmp || tmp->cap.size != cap->size)
1754 return -EINVAL;
1755
1756 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1757 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1758 sizeof(struct pci_cap_saved_data) + cap->size);
1759 }
1760
1761 dev->state_saved = true;
1762 return 0;
1763}
1764EXPORT_SYMBOL_GPL(pci_load_saved_state);
1765
1766/**
1767 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1768 * and free the memory allocated for it.
1769 * @dev: PCI device that we're dealing with
1770 * @state: Pointer to saved state returned from pci_store_saved_state()
1771 */
1772int pci_load_and_free_saved_state(struct pci_dev *dev,
1773 struct pci_saved_state **state)
1774{
1775 int ret = pci_load_saved_state(dev, *state);
1776 kfree(*state);
1777 *state = NULL;
1778 return ret;
1779}
1780EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1781
1782int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1783{
1784 return pci_enable_resources(dev, bars);
1785}
1786
1787static int do_pci_enable_device(struct pci_dev *dev, int bars)
1788{
1789 int err;
1790 struct pci_dev *bridge;
1791 u16 cmd;
1792 u8 pin;
1793
1794 err = pci_set_power_state(dev, PCI_D0);
1795 if (err < 0 && err != -EIO)
1796 return err;
1797
1798 bridge = pci_upstream_bridge(dev);
1799 if (bridge)
1800 pcie_aspm_powersave_config_link(bridge);
1801
1802 err = pcibios_enable_device(dev, bars);
1803 if (err < 0)
1804 return err;
1805 pci_fixup_device(pci_fixup_enable, dev);
1806
1807 if (dev->msi_enabled || dev->msix_enabled)
1808 return 0;
1809
1810 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1811 if (pin) {
1812 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1813 if (cmd & PCI_COMMAND_INTX_DISABLE)
1814 pci_write_config_word(dev, PCI_COMMAND,
1815 cmd & ~PCI_COMMAND_INTX_DISABLE);
1816 }
1817
1818 return 0;
1819}
1820
1821/**
1822 * pci_reenable_device - Resume abandoned device
1823 * @dev: PCI device to be resumed
1824 *
1825 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1826 * to be called by normal code, write proper resume handler and use it instead.
1827 */
1828int pci_reenable_device(struct pci_dev *dev)
1829{
1830 if (pci_is_enabled(dev))
1831 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1832 return 0;
1833}
1834EXPORT_SYMBOL(pci_reenable_device);
1835
1836static void pci_enable_bridge(struct pci_dev *dev)
1837{
1838 struct pci_dev *bridge;
1839 int retval;
1840
1841 bridge = pci_upstream_bridge(dev);
1842 if (bridge)
1843 pci_enable_bridge(bridge);
1844
1845 if (pci_is_enabled(dev)) {
1846 if (!dev->is_busmaster)
1847 pci_set_master(dev);
1848 return;
1849 }
1850
1851 retval = pci_enable_device(dev);
1852 if (retval)
1853 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1854 retval);
1855 pci_set_master(dev);
1856}
1857
1858static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1859{
1860 struct pci_dev *bridge;
1861 int err;
1862 int i, bars = 0;
1863
1864 /*
1865 * Power state could be unknown at this point, either due to a fresh
1866 * boot or a device removal call. So get the current power state
1867 * so that things like MSI message writing will behave as expected
1868 * (e.g. if the device really is in D0 at enable time).
1869 */
1870 if (dev->pm_cap) {
1871 u16 pmcsr;
1872 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1873 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1874 }
1875
1876 if (atomic_inc_return(&dev->enable_cnt) > 1)
1877 return 0; /* already enabled */
1878
1879 bridge = pci_upstream_bridge(dev);
1880 if (bridge)
1881 pci_enable_bridge(bridge);
1882
1883 /* only skip sriov related */
1884 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1885 if (dev->resource[i].flags & flags)
1886 bars |= (1 << i);
1887 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1888 if (dev->resource[i].flags & flags)
1889 bars |= (1 << i);
1890
1891 err = do_pci_enable_device(dev, bars);
1892 if (err < 0)
1893 atomic_dec(&dev->enable_cnt);
1894 return err;
1895}
1896
1897/**
1898 * pci_enable_device_io - Initialize a device for use with IO space
1899 * @dev: PCI device to be initialized
1900 *
1901 * Initialize device before it's used by a driver. Ask low-level code
1902 * to enable I/O resources. Wake up the device if it was suspended.
1903 * Beware, this function can fail.
1904 */
1905int pci_enable_device_io(struct pci_dev *dev)
1906{
1907 return pci_enable_device_flags(dev, IORESOURCE_IO);
1908}
1909EXPORT_SYMBOL(pci_enable_device_io);
1910
1911/**
1912 * pci_enable_device_mem - Initialize a device for use with Memory space
1913 * @dev: PCI device to be initialized
1914 *
1915 * Initialize device before it's used by a driver. Ask low-level code
1916 * to enable Memory resources. Wake up the device if it was suspended.
1917 * Beware, this function can fail.
1918 */
1919int pci_enable_device_mem(struct pci_dev *dev)
1920{
1921 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1922}
1923EXPORT_SYMBOL(pci_enable_device_mem);
1924
1925/**
1926 * pci_enable_device - Initialize device before it's used by a driver.
1927 * @dev: PCI device to be initialized
1928 *
1929 * Initialize device before it's used by a driver. Ask low-level code
1930 * to enable I/O and memory. Wake up the device if it was suspended.
1931 * Beware, this function can fail.
1932 *
1933 * Note we don't actually enable the device many times if we call
1934 * this function repeatedly (we just increment the count).
1935 */
1936int pci_enable_device(struct pci_dev *dev)
1937{
1938 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1939}
1940EXPORT_SYMBOL(pci_enable_device);
1941
1942/*
1943 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1944 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1945 * there's no need to track it separately. pci_devres is initialized
1946 * when a device is enabled using managed PCI device enable interface.
1947 */
1948struct pci_devres {
1949 unsigned int enabled:1;
1950 unsigned int pinned:1;
1951 unsigned int orig_intx:1;
1952 unsigned int restore_intx:1;
1953 unsigned int mwi:1;
1954 u32 region_mask;
1955};
1956
1957static void pcim_release(struct device *gendev, void *res)
1958{
1959 struct pci_dev *dev = to_pci_dev(gendev);
1960 struct pci_devres *this = res;
1961 int i;
1962
1963 if (dev->msi_enabled)
1964 pci_disable_msi(dev);
1965 if (dev->msix_enabled)
1966 pci_disable_msix(dev);
1967
1968 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1969 if (this->region_mask & (1 << i))
1970 pci_release_region(dev, i);
1971
1972 if (this->mwi)
1973 pci_clear_mwi(dev);
1974
1975 if (this->restore_intx)
1976 pci_intx(dev, this->orig_intx);
1977
1978 if (this->enabled && !this->pinned)
1979 pci_disable_device(dev);
1980}
1981
1982static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1983{
1984 struct pci_devres *dr, *new_dr;
1985
1986 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1987 if (dr)
1988 return dr;
1989
1990 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1991 if (!new_dr)
1992 return NULL;
1993 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1994}
1995
1996static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1997{
1998 if (pci_is_managed(pdev))
1999 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2000 return NULL;
2001}
2002
2003/**
2004 * pcim_enable_device - Managed pci_enable_device()
2005 * @pdev: PCI device to be initialized
2006 *
2007 * Managed pci_enable_device().
2008 */
2009int pcim_enable_device(struct pci_dev *pdev)
2010{
2011 struct pci_devres *dr;
2012 int rc;
2013
2014 dr = get_pci_dr(pdev);
2015 if (unlikely(!dr))
2016 return -ENOMEM;
2017 if (dr->enabled)
2018 return 0;
2019
2020 rc = pci_enable_device(pdev);
2021 if (!rc) {
2022 pdev->is_managed = 1;
2023 dr->enabled = 1;
2024 }
2025 return rc;
2026}
2027EXPORT_SYMBOL(pcim_enable_device);
2028
2029/**
2030 * pcim_pin_device - Pin managed PCI device
2031 * @pdev: PCI device to pin
2032 *
2033 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2034 * driver detach. @pdev must have been enabled with
2035 * pcim_enable_device().
2036 */
2037void pcim_pin_device(struct pci_dev *pdev)
2038{
2039 struct pci_devres *dr;
2040
2041 dr = find_pci_dr(pdev);
2042 WARN_ON(!dr || !dr->enabled);
2043 if (dr)
2044 dr->pinned = 1;
2045}
2046EXPORT_SYMBOL(pcim_pin_device);
2047
2048/*
2049 * pcibios_add_device - provide arch specific hooks when adding device dev
2050 * @dev: the PCI device being added
2051 *
2052 * Permits the platform to provide architecture specific functionality when
2053 * devices are added. This is the default implementation. Architecture
2054 * implementations can override this.
2055 */
2056int __weak pcibios_add_device(struct pci_dev *dev)
2057{
2058 return 0;
2059}
2060
2061/**
2062 * pcibios_release_device - provide arch specific hooks when releasing
2063 * device dev
2064 * @dev: the PCI device being released
2065 *
2066 * Permits the platform to provide architecture specific functionality when
2067 * devices are released. This is the default implementation. Architecture
2068 * implementations can override this.
2069 */
2070void __weak pcibios_release_device(struct pci_dev *dev) {}
2071
2072/**
2073 * pcibios_disable_device - disable arch specific PCI resources for device dev
2074 * @dev: the PCI device to disable
2075 *
2076 * Disables architecture specific PCI resources for the device. This
2077 * is the default implementation. Architecture implementations can
2078 * override this.
2079 */
2080void __weak pcibios_disable_device(struct pci_dev *dev) {}
2081
2082/**
2083 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2084 * @irq: ISA IRQ to penalize
2085 * @active: IRQ active or not
2086 *
2087 * Permits the platform to provide architecture-specific functionality when
2088 * penalizing ISA IRQs. This is the default implementation. Architecture
2089 * implementations can override this.
2090 */
2091void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2092
2093static void do_pci_disable_device(struct pci_dev *dev)
2094{
2095 u16 pci_command;
2096
2097 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2098 if (pci_command & PCI_COMMAND_MASTER) {
2099 pci_command &= ~PCI_COMMAND_MASTER;
2100 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2101 }
2102
2103 pcibios_disable_device(dev);
2104}
2105
2106/**
2107 * pci_disable_enabled_device - Disable device without updating enable_cnt
2108 * @dev: PCI device to disable
2109 *
2110 * NOTE: This function is a backend of PCI power management routines and is
2111 * not supposed to be called drivers.
2112 */
2113void pci_disable_enabled_device(struct pci_dev *dev)
2114{
2115 if (pci_is_enabled(dev))
2116 do_pci_disable_device(dev);
2117}
2118
2119/**
2120 * pci_disable_device - Disable PCI device after use
2121 * @dev: PCI device to be disabled
2122 *
2123 * Signal to the system that the PCI device is not in use by the system
2124 * anymore. This only involves disabling PCI bus-mastering, if active.
2125 *
2126 * Note we don't actually disable the device until all callers of
2127 * pci_enable_device() have called pci_disable_device().
2128 */
2129void pci_disable_device(struct pci_dev *dev)
2130{
2131 struct pci_devres *dr;
2132
2133 dr = find_pci_dr(dev);
2134 if (dr)
2135 dr->enabled = 0;
2136
2137 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2138 "disabling already-disabled device");
2139
2140 if (atomic_dec_return(&dev->enable_cnt) != 0)
2141 return;
2142
2143 do_pci_disable_device(dev);
2144
2145 dev->is_busmaster = 0;
2146}
2147EXPORT_SYMBOL(pci_disable_device);
2148
2149/**
2150 * pcibios_set_pcie_reset_state - set reset state for device dev
2151 * @dev: the PCIe device reset
2152 * @state: Reset state to enter into
2153 *
2154 * Set the PCIe reset state for the device. This is the default
2155 * implementation. Architecture implementations can override this.
2156 */
2157int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2158 enum pcie_reset_state state)
2159{
2160 return -EINVAL;
2161}
2162
2163/**
2164 * pci_set_pcie_reset_state - set reset state for device dev
2165 * @dev: the PCIe device reset
2166 * @state: Reset state to enter into
2167 *
2168 * Sets the PCI reset state for the device.
2169 */
2170int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2171{
2172 return pcibios_set_pcie_reset_state(dev, state);
2173}
2174EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2175
2176void pcie_clear_device_status(struct pci_dev *dev)
2177{
2178 u16 sta;
2179
2180 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2181 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2182}
2183
2184/**
2185 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2186 * @dev: PCIe root port or event collector.
2187 */
2188void pcie_clear_root_pme_status(struct pci_dev *dev)
2189{
2190 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2191}
2192
2193/**
2194 * pci_check_pme_status - Check if given device has generated PME.
2195 * @dev: Device to check.
2196 *
2197 * Check the PME status of the device and if set, clear it and clear PME enable
2198 * (if set). Return 'true' if PME status and PME enable were both set or
2199 * 'false' otherwise.
2200 */
2201bool pci_check_pme_status(struct pci_dev *dev)
2202{
2203 int pmcsr_pos;
2204 u16 pmcsr;
2205 bool ret = false;
2206
2207 if (!dev->pm_cap)
2208 return false;
2209
2210 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2211 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2212 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2213 return false;
2214
2215 /* Clear PME status. */
2216 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2217 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2218 /* Disable PME to avoid interrupt flood. */
2219 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2220 ret = true;
2221 }
2222
2223 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2224
2225 return ret;
2226}
2227
2228/**
2229 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2230 * @dev: Device to handle.
2231 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2232 *
2233 * Check if @dev has generated PME and queue a resume request for it in that
2234 * case.
2235 */
2236static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2237{
2238 if (pme_poll_reset && dev->pme_poll)
2239 dev->pme_poll = false;
2240
2241 if (pci_check_pme_status(dev)) {
2242 pci_wakeup_event(dev);
2243 pm_request_resume(&dev->dev);
2244 }
2245 return 0;
2246}
2247
2248/**
2249 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2250 * @bus: Top bus of the subtree to walk.
2251 */
2252void pci_pme_wakeup_bus(struct pci_bus *bus)
2253{
2254 if (bus)
2255 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2256}
2257
2258
2259/**
2260 * pci_pme_capable - check the capability of PCI device to generate PME#
2261 * @dev: PCI device to handle.
2262 * @state: PCI state from which device will issue PME#.
2263 */
2264bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2265{
2266 if (!dev->pm_cap)
2267 return false;
2268
2269 return !!(dev->pme_support & (1 << state));
2270}
2271EXPORT_SYMBOL(pci_pme_capable);
2272
2273static void pci_pme_list_scan(struct work_struct *work)
2274{
2275 struct pci_pme_device *pme_dev, *n;
2276
2277 mutex_lock(&pci_pme_list_mutex);
2278 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2279 if (pme_dev->dev->pme_poll) {
2280 struct pci_dev *bridge;
2281
2282 bridge = pme_dev->dev->bus->self;
2283 /*
2284 * If bridge is in low power state, the
2285 * configuration space of subordinate devices
2286 * may be not accessible
2287 */
2288 if (bridge && bridge->current_state != PCI_D0)
2289 continue;
2290 /*
2291 * If the device is in D3cold it should not be
2292 * polled either.
2293 */
2294 if (pme_dev->dev->current_state == PCI_D3cold)
2295 continue;
2296
2297 pci_pme_wakeup(pme_dev->dev, NULL);
2298 } else {
2299 list_del(&pme_dev->list);
2300 kfree(pme_dev);
2301 }
2302 }
2303 if (!list_empty(&pci_pme_list))
2304 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2305 msecs_to_jiffies(PME_TIMEOUT));
2306 mutex_unlock(&pci_pme_list_mutex);
2307}
2308
2309static void __pci_pme_active(struct pci_dev *dev, bool enable)
2310{
2311 u16 pmcsr;
2312
2313 if (!dev->pme_support)
2314 return;
2315
2316 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2317 /* Clear PME_Status by writing 1 to it and enable PME# */
2318 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2319 if (!enable)
2320 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2321
2322 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2323}
2324
2325/**
2326 * pci_pme_restore - Restore PME configuration after config space restore.
2327 * @dev: PCI device to update.
2328 */
2329void pci_pme_restore(struct pci_dev *dev)
2330{
2331 u16 pmcsr;
2332
2333 if (!dev->pme_support)
2334 return;
2335
2336 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2337 if (dev->wakeup_prepared) {
2338 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2339 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2340 } else {
2341 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2342 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2343 }
2344 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2345}
2346
2347/**
2348 * pci_pme_active - enable or disable PCI device's PME# function
2349 * @dev: PCI device to handle.
2350 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2351 *
2352 * The caller must verify that the device is capable of generating PME# before
2353 * calling this function with @enable equal to 'true'.
2354 */
2355void pci_pme_active(struct pci_dev *dev, bool enable)
2356{
2357 __pci_pme_active(dev, enable);
2358
2359 /*
2360 * PCI (as opposed to PCIe) PME requires that the device have
2361 * its PME# line hooked up correctly. Not all hardware vendors
2362 * do this, so the PME never gets delivered and the device
2363 * remains asleep. The easiest way around this is to
2364 * periodically walk the list of suspended devices and check
2365 * whether any have their PME flag set. The assumption is that
2366 * we'll wake up often enough anyway that this won't be a huge
2367 * hit, and the power savings from the devices will still be a
2368 * win.
2369 *
2370 * Although PCIe uses in-band PME message instead of PME# line
2371 * to report PME, PME does not work for some PCIe devices in
2372 * reality. For example, there are devices that set their PME
2373 * status bits, but don't really bother to send a PME message;
2374 * there are PCI Express Root Ports that don't bother to
2375 * trigger interrupts when they receive PME messages from the
2376 * devices below. So PME poll is used for PCIe devices too.
2377 */
2378
2379 if (dev->pme_poll) {
2380 struct pci_pme_device *pme_dev;
2381 if (enable) {
2382 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2383 GFP_KERNEL);
2384 if (!pme_dev) {
2385 pci_warn(dev, "can't enable PME#\n");
2386 return;
2387 }
2388 pme_dev->dev = dev;
2389 mutex_lock(&pci_pme_list_mutex);
2390 list_add(&pme_dev->list, &pci_pme_list);
2391 if (list_is_singular(&pci_pme_list))
2392 queue_delayed_work(system_freezable_wq,
2393 &pci_pme_work,
2394 msecs_to_jiffies(PME_TIMEOUT));
2395 mutex_unlock(&pci_pme_list_mutex);
2396 } else {
2397 mutex_lock(&pci_pme_list_mutex);
2398 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2399 if (pme_dev->dev == dev) {
2400 list_del(&pme_dev->list);
2401 kfree(pme_dev);
2402 break;
2403 }
2404 }
2405 mutex_unlock(&pci_pme_list_mutex);
2406 }
2407 }
2408
2409 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2410}
2411EXPORT_SYMBOL(pci_pme_active);
2412
2413/**
2414 * __pci_enable_wake - enable PCI device as wakeup event source
2415 * @dev: PCI device affected
2416 * @state: PCI state from which device will issue wakeup events
2417 * @enable: True to enable event generation; false to disable
2418 *
2419 * This enables the device as a wakeup event source, or disables it.
2420 * When such events involves platform-specific hooks, those hooks are
2421 * called automatically by this routine.
2422 *
2423 * Devices with legacy power management (no standard PCI PM capabilities)
2424 * always require such platform hooks.
2425 *
2426 * RETURN VALUE:
2427 * 0 is returned on success
2428 * -EINVAL is returned if device is not supposed to wake up the system
2429 * Error code depending on the platform is returned if both the platform and
2430 * the native mechanism fail to enable the generation of wake-up events
2431 */
2432static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2433{
2434 int ret = 0;
2435
2436 /*
2437 * Bridges that are not power-manageable directly only signal
2438 * wakeup on behalf of subordinate devices which is set up
2439 * elsewhere, so skip them. However, bridges that are
2440 * power-manageable may signal wakeup for themselves (for example,
2441 * on a hotplug event) and they need to be covered here.
2442 */
2443 if (!pci_power_manageable(dev))
2444 return 0;
2445
2446 /* Don't do the same thing twice in a row for one device. */
2447 if (!!enable == !!dev->wakeup_prepared)
2448 return 0;
2449
2450 /*
2451 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2452 * Anderson we should be doing PME# wake enable followed by ACPI wake
2453 * enable. To disable wake-up we call the platform first, for symmetry.
2454 */
2455
2456 if (enable) {
2457 int error;
2458
2459 if (pci_pme_capable(dev, state))
2460 pci_pme_active(dev, true);
2461 else
2462 ret = 1;
2463 error = platform_pci_set_wakeup(dev, true);
2464 if (ret)
2465 ret = error;
2466 if (!ret)
2467 dev->wakeup_prepared = true;
2468 } else {
2469 platform_pci_set_wakeup(dev, false);
2470 pci_pme_active(dev, false);
2471 dev->wakeup_prepared = false;
2472 }
2473
2474 return ret;
2475}
2476
2477/**
2478 * pci_enable_wake - change wakeup settings for a PCI device
2479 * @pci_dev: Target device
2480 * @state: PCI state from which device will issue wakeup events
2481 * @enable: Whether or not to enable event generation
2482 *
2483 * If @enable is set, check device_may_wakeup() for the device before calling
2484 * __pci_enable_wake() for it.
2485 */
2486int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2487{
2488 if (enable && !device_may_wakeup(&pci_dev->dev))
2489 return -EINVAL;
2490
2491 return __pci_enable_wake(pci_dev, state, enable);
2492}
2493EXPORT_SYMBOL(pci_enable_wake);
2494
2495/**
2496 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2497 * @dev: PCI device to prepare
2498 * @enable: True to enable wake-up event generation; false to disable
2499 *
2500 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2501 * and this function allows them to set that up cleanly - pci_enable_wake()
2502 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2503 * ordering constraints.
2504 *
2505 * This function only returns error code if the device is not allowed to wake
2506 * up the system from sleep or it is not capable of generating PME# from both
2507 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2508 */
2509int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2510{
2511 return pci_pme_capable(dev, PCI_D3cold) ?
2512 pci_enable_wake(dev, PCI_D3cold, enable) :
2513 pci_enable_wake(dev, PCI_D3hot, enable);
2514}
2515EXPORT_SYMBOL(pci_wake_from_d3);
2516
2517/**
2518 * pci_target_state - find an appropriate low power state for a given PCI dev
2519 * @dev: PCI device
2520 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2521 *
2522 * Use underlying platform code to find a supported low power state for @dev.
2523 * If the platform can't manage @dev, return the deepest state from which it
2524 * can generate wake events, based on any available PME info.
2525 */
2526static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2527{
2528 pci_power_t target_state = PCI_D3hot;
2529
2530 if (platform_pci_power_manageable(dev)) {
2531 /*
2532 * Call the platform to find the target state for the device.
2533 */
2534 pci_power_t state = platform_pci_choose_state(dev);
2535
2536 switch (state) {
2537 case PCI_POWER_ERROR:
2538 case PCI_UNKNOWN:
2539 break;
2540 case PCI_D1:
2541 case PCI_D2:
2542 if (pci_no_d1d2(dev))
2543 break;
2544 fallthrough;
2545 default:
2546 target_state = state;
2547 }
2548
2549 return target_state;
2550 }
2551
2552 if (!dev->pm_cap)
2553 target_state = PCI_D0;
2554
2555 /*
2556 * If the device is in D3cold even though it's not power-manageable by
2557 * the platform, it may have been powered down by non-standard means.
2558 * Best to let it slumber.
2559 */
2560 if (dev->current_state == PCI_D3cold)
2561 target_state = PCI_D3cold;
2562
2563 if (wakeup) {
2564 /*
2565 * Find the deepest state from which the device can generate
2566 * PME#.
2567 */
2568 if (dev->pme_support) {
2569 while (target_state
2570 && !(dev->pme_support & (1 << target_state)))
2571 target_state--;
2572 }
2573 }
2574
2575 return target_state;
2576}
2577
2578/**
2579 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2580 * into a sleep state
2581 * @dev: Device to handle.
2582 *
2583 * Choose the power state appropriate for the device depending on whether
2584 * it can wake up the system and/or is power manageable by the platform
2585 * (PCI_D3hot is the default) and put the device into that state.
2586 */
2587int pci_prepare_to_sleep(struct pci_dev *dev)
2588{
2589 bool wakeup = device_may_wakeup(&dev->dev);
2590 pci_power_t target_state = pci_target_state(dev, wakeup);
2591 int error;
2592
2593 if (target_state == PCI_POWER_ERROR)
2594 return -EIO;
2595
2596 pci_enable_wake(dev, target_state, wakeup);
2597
2598 error = pci_set_power_state(dev, target_state);
2599
2600 if (error)
2601 pci_enable_wake(dev, target_state, false);
2602
2603 return error;
2604}
2605EXPORT_SYMBOL(pci_prepare_to_sleep);
2606
2607/**
2608 * pci_back_from_sleep - turn PCI device on during system-wide transition
2609 * into working state
2610 * @dev: Device to handle.
2611 *
2612 * Disable device's system wake-up capability and put it into D0.
2613 */
2614int pci_back_from_sleep(struct pci_dev *dev)
2615{
2616 pci_enable_wake(dev, PCI_D0, false);
2617 return pci_set_power_state(dev, PCI_D0);
2618}
2619EXPORT_SYMBOL(pci_back_from_sleep);
2620
2621/**
2622 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2623 * @dev: PCI device being suspended.
2624 *
2625 * Prepare @dev to generate wake-up events at run time and put it into a low
2626 * power state.
2627 */
2628int pci_finish_runtime_suspend(struct pci_dev *dev)
2629{
2630 pci_power_t target_state;
2631 int error;
2632
2633 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2634 if (target_state == PCI_POWER_ERROR)
2635 return -EIO;
2636
2637 dev->runtime_d3cold = target_state == PCI_D3cold;
2638
2639 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2640
2641 error = pci_set_power_state(dev, target_state);
2642
2643 if (error) {
2644 pci_enable_wake(dev, target_state, false);
2645 dev->runtime_d3cold = false;
2646 }
2647
2648 return error;
2649}
2650
2651/**
2652 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2653 * @dev: Device to check.
2654 *
2655 * Return true if the device itself is capable of generating wake-up events
2656 * (through the platform or using the native PCIe PME) or if the device supports
2657 * PME and one of its upstream bridges can generate wake-up events.
2658 */
2659bool pci_dev_run_wake(struct pci_dev *dev)
2660{
2661 struct pci_bus *bus = dev->bus;
2662
2663 if (!dev->pme_support)
2664 return false;
2665
2666 /* PME-capable in principle, but not from the target power state */
2667 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2668 return false;
2669
2670 if (device_can_wakeup(&dev->dev))
2671 return true;
2672
2673 while (bus->parent) {
2674 struct pci_dev *bridge = bus->self;
2675
2676 if (device_can_wakeup(&bridge->dev))
2677 return true;
2678
2679 bus = bus->parent;
2680 }
2681
2682 /* We have reached the root bus. */
2683 if (bus->bridge)
2684 return device_can_wakeup(bus->bridge);
2685
2686 return false;
2687}
2688EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2689
2690/**
2691 * pci_dev_need_resume - Check if it is necessary to resume the device.
2692 * @pci_dev: Device to check.
2693 *
2694 * Return 'true' if the device is not runtime-suspended or it has to be
2695 * reconfigured due to wakeup settings difference between system and runtime
2696 * suspend, or the current power state of it is not suitable for the upcoming
2697 * (system-wide) transition.
2698 */
2699bool pci_dev_need_resume(struct pci_dev *pci_dev)
2700{
2701 struct device *dev = &pci_dev->dev;
2702 pci_power_t target_state;
2703
2704 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2705 return true;
2706
2707 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2708
2709 /*
2710 * If the earlier platform check has not triggered, D3cold is just power
2711 * removal on top of D3hot, so no need to resume the device in that
2712 * case.
2713 */
2714 return target_state != pci_dev->current_state &&
2715 target_state != PCI_D3cold &&
2716 pci_dev->current_state != PCI_D3hot;
2717}
2718
2719/**
2720 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2721 * @pci_dev: Device to check.
2722 *
2723 * If the device is suspended and it is not configured for system wakeup,
2724 * disable PME for it to prevent it from waking up the system unnecessarily.
2725 *
2726 * Note that if the device's power state is D3cold and the platform check in
2727 * pci_dev_need_resume() has not triggered, the device's configuration need not
2728 * be changed.
2729 */
2730void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2731{
2732 struct device *dev = &pci_dev->dev;
2733
2734 spin_lock_irq(&dev->power.lock);
2735
2736 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2737 pci_dev->current_state < PCI_D3cold)
2738 __pci_pme_active(pci_dev, false);
2739
2740 spin_unlock_irq(&dev->power.lock);
2741}
2742
2743/**
2744 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2745 * @pci_dev: Device to handle.
2746 *
2747 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2748 * it might have been disabled during the prepare phase of system suspend if
2749 * the device was not configured for system wakeup.
2750 */
2751void pci_dev_complete_resume(struct pci_dev *pci_dev)
2752{
2753 struct device *dev = &pci_dev->dev;
2754
2755 if (!pci_dev_run_wake(pci_dev))
2756 return;
2757
2758 spin_lock_irq(&dev->power.lock);
2759
2760 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2761 __pci_pme_active(pci_dev, true);
2762
2763 spin_unlock_irq(&dev->power.lock);
2764}
2765
2766void pci_config_pm_runtime_get(struct pci_dev *pdev)
2767{
2768 struct device *dev = &pdev->dev;
2769 struct device *parent = dev->parent;
2770
2771 if (parent)
2772 pm_runtime_get_sync(parent);
2773 pm_runtime_get_noresume(dev);
2774 /*
2775 * pdev->current_state is set to PCI_D3cold during suspending,
2776 * so wait until suspending completes
2777 */
2778 pm_runtime_barrier(dev);
2779 /*
2780 * Only need to resume devices in D3cold, because config
2781 * registers are still accessible for devices suspended but
2782 * not in D3cold.
2783 */
2784 if (pdev->current_state == PCI_D3cold)
2785 pm_runtime_resume(dev);
2786}
2787
2788void pci_config_pm_runtime_put(struct pci_dev *pdev)
2789{
2790 struct device *dev = &pdev->dev;
2791 struct device *parent = dev->parent;
2792
2793 pm_runtime_put(dev);
2794 if (parent)
2795 pm_runtime_put_sync(parent);
2796}
2797
2798static const struct dmi_system_id bridge_d3_blacklist[] = {
2799#ifdef CONFIG_X86
2800 {
2801 /*
2802 * Gigabyte X299 root port is not marked as hotplug capable
2803 * which allows Linux to power manage it. However, this
2804 * confuses the BIOS SMI handler so don't power manage root
2805 * ports on that system.
2806 */
2807 .ident = "X299 DESIGNARE EX-CF",
2808 .matches = {
2809 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2810 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2811 },
2812 },
2813#endif
2814 { }
2815};
2816
2817/**
2818 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2819 * @bridge: Bridge to check
2820 *
2821 * This function checks if it is possible to move the bridge to D3.
2822 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2823 */
2824bool pci_bridge_d3_possible(struct pci_dev *bridge)
2825{
2826 if (!pci_is_pcie(bridge))
2827 return false;
2828
2829 switch (pci_pcie_type(bridge)) {
2830 case PCI_EXP_TYPE_ROOT_PORT:
2831 case PCI_EXP_TYPE_UPSTREAM:
2832 case PCI_EXP_TYPE_DOWNSTREAM:
2833 if (pci_bridge_d3_disable)
2834 return false;
2835
2836 /*
2837 * Hotplug ports handled by firmware in System Management Mode
2838 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2839 */
2840 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2841 return false;
2842
2843 if (pci_bridge_d3_force)
2844 return true;
2845
2846 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2847 if (bridge->is_thunderbolt)
2848 return true;
2849
2850 /* Platform might know better if the bridge supports D3 */
2851 if (platform_pci_bridge_d3(bridge))
2852 return true;
2853
2854 /*
2855 * Hotplug ports handled natively by the OS were not validated
2856 * by vendors for runtime D3 at least until 2018 because there
2857 * was no OS support.
2858 */
2859 if (bridge->is_hotplug_bridge)
2860 return false;
2861
2862 if (dmi_check_system(bridge_d3_blacklist))
2863 return false;
2864
2865 /*
2866 * It should be safe to put PCIe ports from 2015 or newer
2867 * to D3.
2868 */
2869 if (dmi_get_bios_year() >= 2015)
2870 return true;
2871 break;
2872 }
2873
2874 return false;
2875}
2876
2877static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2878{
2879 bool *d3cold_ok = data;
2880
2881 if (/* The device needs to be allowed to go D3cold ... */
2882 dev->no_d3cold || !dev->d3cold_allowed ||
2883
2884 /* ... and if it is wakeup capable to do so from D3cold. */
2885 (device_may_wakeup(&dev->dev) &&
2886 !pci_pme_capable(dev, PCI_D3cold)) ||
2887
2888 /* If it is a bridge it must be allowed to go to D3. */
2889 !pci_power_manageable(dev))
2890
2891 *d3cold_ok = false;
2892
2893 return !*d3cold_ok;
2894}
2895
2896/*
2897 * pci_bridge_d3_update - Update bridge D3 capabilities
2898 * @dev: PCI device which is changed
2899 *
2900 * Update upstream bridge PM capabilities accordingly depending on if the
2901 * device PM configuration was changed or the device is being removed. The
2902 * change is also propagated upstream.
2903 */
2904void pci_bridge_d3_update(struct pci_dev *dev)
2905{
2906 bool remove = !device_is_registered(&dev->dev);
2907 struct pci_dev *bridge;
2908 bool d3cold_ok = true;
2909
2910 bridge = pci_upstream_bridge(dev);
2911 if (!bridge || !pci_bridge_d3_possible(bridge))
2912 return;
2913
2914 /*
2915 * If D3 is currently allowed for the bridge, removing one of its
2916 * children won't change that.
2917 */
2918 if (remove && bridge->bridge_d3)
2919 return;
2920
2921 /*
2922 * If D3 is currently allowed for the bridge and a child is added or
2923 * changed, disallowance of D3 can only be caused by that child, so
2924 * we only need to check that single device, not any of its siblings.
2925 *
2926 * If D3 is currently not allowed for the bridge, checking the device
2927 * first may allow us to skip checking its siblings.
2928 */
2929 if (!remove)
2930 pci_dev_check_d3cold(dev, &d3cold_ok);
2931
2932 /*
2933 * If D3 is currently not allowed for the bridge, this may be caused
2934 * either by the device being changed/removed or any of its siblings,
2935 * so we need to go through all children to find out if one of them
2936 * continues to block D3.
2937 */
2938 if (d3cold_ok && !bridge->bridge_d3)
2939 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2940 &d3cold_ok);
2941
2942 if (bridge->bridge_d3 != d3cold_ok) {
2943 bridge->bridge_d3 = d3cold_ok;
2944 /* Propagate change to upstream bridges */
2945 pci_bridge_d3_update(bridge);
2946 }
2947}
2948
2949/**
2950 * pci_d3cold_enable - Enable D3cold for device
2951 * @dev: PCI device to handle
2952 *
2953 * This function can be used in drivers to enable D3cold from the device
2954 * they handle. It also updates upstream PCI bridge PM capabilities
2955 * accordingly.
2956 */
2957void pci_d3cold_enable(struct pci_dev *dev)
2958{
2959 if (dev->no_d3cold) {
2960 dev->no_d3cold = false;
2961 pci_bridge_d3_update(dev);
2962 }
2963}
2964EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2965
2966/**
2967 * pci_d3cold_disable - Disable D3cold for device
2968 * @dev: PCI device to handle
2969 *
2970 * This function can be used in drivers to disable D3cold from the device
2971 * they handle. It also updates upstream PCI bridge PM capabilities
2972 * accordingly.
2973 */
2974void pci_d3cold_disable(struct pci_dev *dev)
2975{
2976 if (!dev->no_d3cold) {
2977 dev->no_d3cold = true;
2978 pci_bridge_d3_update(dev);
2979 }
2980}
2981EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2982
2983/**
2984 * pci_pm_init - Initialize PM functions of given PCI device
2985 * @dev: PCI device to handle.
2986 */
2987void pci_pm_init(struct pci_dev *dev)
2988{
2989 int pm;
2990 u16 status;
2991 u16 pmc;
2992
2993 pm_runtime_forbid(&dev->dev);
2994 pm_runtime_set_active(&dev->dev);
2995 pm_runtime_enable(&dev->dev);
2996 device_enable_async_suspend(&dev->dev);
2997 dev->wakeup_prepared = false;
2998
2999 dev->pm_cap = 0;
3000 dev->pme_support = 0;
3001
3002 /* find PCI PM capability in list */
3003 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3004 if (!pm)
3005 return;
3006 /* Check device's ability to generate PME# */
3007 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3008
3009 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3010 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3011 pmc & PCI_PM_CAP_VER_MASK);
3012 return;
3013 }
3014
3015 dev->pm_cap = pm;
3016 dev->d3_delay = PCI_PM_D3_WAIT;
3017 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3018 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3019 dev->d3cold_allowed = true;
3020
3021 dev->d1_support = false;
3022 dev->d2_support = false;
3023 if (!pci_no_d1d2(dev)) {
3024 if (pmc & PCI_PM_CAP_D1)
3025 dev->d1_support = true;
3026 if (pmc & PCI_PM_CAP_D2)
3027 dev->d2_support = true;
3028
3029 if (dev->d1_support || dev->d2_support)
3030 pci_info(dev, "supports%s%s\n",
3031 dev->d1_support ? " D1" : "",
3032 dev->d2_support ? " D2" : "");
3033 }
3034
3035 pmc &= PCI_PM_CAP_PME_MASK;
3036 if (pmc) {
3037 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3038 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3039 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3040 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3041 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
3042 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3043 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3044 dev->pme_poll = true;
3045 /*
3046 * Make device's PM flags reflect the wake-up capability, but
3047 * let the user space enable it to wake up the system as needed.
3048 */
3049 device_set_wakeup_capable(&dev->dev, true);
3050 /* Disable the PME# generation functionality */
3051 pci_pme_active(dev, false);
3052 }
3053
3054 pci_read_config_word(dev, PCI_STATUS, &status);
3055 if (status & PCI_STATUS_IMM_READY)
3056 dev->imm_ready = 1;
3057}
3058
3059static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3060{
3061 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3062
3063 switch (prop) {
3064 case PCI_EA_P_MEM:
3065 case PCI_EA_P_VF_MEM:
3066 flags |= IORESOURCE_MEM;
3067 break;
3068 case PCI_EA_P_MEM_PREFETCH:
3069 case PCI_EA_P_VF_MEM_PREFETCH:
3070 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3071 break;
3072 case PCI_EA_P_IO:
3073 flags |= IORESOURCE_IO;
3074 break;
3075 default:
3076 return 0;
3077 }
3078
3079 return flags;
3080}
3081
3082static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3083 u8 prop)
3084{
3085 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3086 return &dev->resource[bei];
3087#ifdef CONFIG_PCI_IOV
3088 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3089 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3090 return &dev->resource[PCI_IOV_RESOURCES +
3091 bei - PCI_EA_BEI_VF_BAR0];
3092#endif
3093 else if (bei == PCI_EA_BEI_ROM)
3094 return &dev->resource[PCI_ROM_RESOURCE];
3095 else
3096 return NULL;
3097}
3098
3099/* Read an Enhanced Allocation (EA) entry */
3100static int pci_ea_read(struct pci_dev *dev, int offset)
3101{
3102 struct resource *res;
3103 int ent_size, ent_offset = offset;
3104 resource_size_t start, end;
3105 unsigned long flags;
3106 u32 dw0, bei, base, max_offset;
3107 u8 prop;
3108 bool support_64 = (sizeof(resource_size_t) >= 8);
3109
3110 pci_read_config_dword(dev, ent_offset, &dw0);
3111 ent_offset += 4;
3112
3113 /* Entry size field indicates DWORDs after 1st */
3114 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3115
3116 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3117 goto out;
3118
3119 bei = (dw0 & PCI_EA_BEI) >> 4;
3120 prop = (dw0 & PCI_EA_PP) >> 8;
3121
3122 /*
3123 * If the Property is in the reserved range, try the Secondary
3124 * Property instead.
3125 */
3126 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3127 prop = (dw0 & PCI_EA_SP) >> 16;
3128 if (prop > PCI_EA_P_BRIDGE_IO)
3129 goto out;
3130
3131 res = pci_ea_get_resource(dev, bei, prop);
3132 if (!res) {
3133 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3134 goto out;
3135 }
3136
3137 flags = pci_ea_flags(dev, prop);
3138 if (!flags) {
3139 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3140 goto out;
3141 }
3142
3143 /* Read Base */
3144 pci_read_config_dword(dev, ent_offset, &base);
3145 start = (base & PCI_EA_FIELD_MASK);
3146 ent_offset += 4;
3147
3148 /* Read MaxOffset */
3149 pci_read_config_dword(dev, ent_offset, &max_offset);
3150 ent_offset += 4;
3151
3152 /* Read Base MSBs (if 64-bit entry) */
3153 if (base & PCI_EA_IS_64) {
3154 u32 base_upper;
3155
3156 pci_read_config_dword(dev, ent_offset, &base_upper);
3157 ent_offset += 4;
3158
3159 flags |= IORESOURCE_MEM_64;
3160
3161 /* entry starts above 32-bit boundary, can't use */
3162 if (!support_64 && base_upper)
3163 goto out;
3164
3165 if (support_64)
3166 start |= ((u64)base_upper << 32);
3167 }
3168
3169 end = start + (max_offset | 0x03);
3170
3171 /* Read MaxOffset MSBs (if 64-bit entry) */
3172 if (max_offset & PCI_EA_IS_64) {
3173 u32 max_offset_upper;
3174
3175 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3176 ent_offset += 4;
3177
3178 flags |= IORESOURCE_MEM_64;
3179
3180 /* entry too big, can't use */
3181 if (!support_64 && max_offset_upper)
3182 goto out;
3183
3184 if (support_64)
3185 end += ((u64)max_offset_upper << 32);
3186 }
3187
3188 if (end < start) {
3189 pci_err(dev, "EA Entry crosses address boundary\n");
3190 goto out;
3191 }
3192
3193 if (ent_size != ent_offset - offset) {
3194 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3195 ent_size, ent_offset - offset);
3196 goto out;
3197 }
3198
3199 res->name = pci_name(dev);
3200 res->start = start;
3201 res->end = end;
3202 res->flags = flags;
3203
3204 if (bei <= PCI_EA_BEI_BAR5)
3205 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3206 bei, res, prop);
3207 else if (bei == PCI_EA_BEI_ROM)
3208 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3209 res, prop);
3210 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3211 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3212 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3213 else
3214 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3215 bei, res, prop);
3216
3217out:
3218 return offset + ent_size;
3219}
3220
3221/* Enhanced Allocation Initialization */
3222void pci_ea_init(struct pci_dev *dev)
3223{
3224 int ea;
3225 u8 num_ent;
3226 int offset;
3227 int i;
3228
3229 /* find PCI EA capability in list */
3230 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3231 if (!ea)
3232 return;
3233
3234 /* determine the number of entries */
3235 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3236 &num_ent);
3237 num_ent &= PCI_EA_NUM_ENT_MASK;
3238
3239 offset = ea + PCI_EA_FIRST_ENT;
3240
3241 /* Skip DWORD 2 for type 1 functions */
3242 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3243 offset += 4;
3244
3245 /* parse each EA entry */
3246 for (i = 0; i < num_ent; ++i)
3247 offset = pci_ea_read(dev, offset);
3248}
3249
3250static void pci_add_saved_cap(struct pci_dev *pci_dev,
3251 struct pci_cap_saved_state *new_cap)
3252{
3253 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3254}
3255
3256/**
3257 * _pci_add_cap_save_buffer - allocate buffer for saving given
3258 * capability registers
3259 * @dev: the PCI device
3260 * @cap: the capability to allocate the buffer for
3261 * @extended: Standard or Extended capability ID
3262 * @size: requested size of the buffer
3263 */
3264static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3265 bool extended, unsigned int size)
3266{
3267 int pos;
3268 struct pci_cap_saved_state *save_state;
3269
3270 if (extended)
3271 pos = pci_find_ext_capability(dev, cap);
3272 else
3273 pos = pci_find_capability(dev, cap);
3274
3275 if (!pos)
3276 return 0;
3277
3278 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3279 if (!save_state)
3280 return -ENOMEM;
3281
3282 save_state->cap.cap_nr = cap;
3283 save_state->cap.cap_extended = extended;
3284 save_state->cap.size = size;
3285 pci_add_saved_cap(dev, save_state);
3286
3287 return 0;
3288}
3289
3290int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3291{
3292 return _pci_add_cap_save_buffer(dev, cap, false, size);
3293}
3294
3295int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3296{
3297 return _pci_add_cap_save_buffer(dev, cap, true, size);
3298}
3299
3300/**
3301 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3302 * @dev: the PCI device
3303 */
3304void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3305{
3306 int error;
3307
3308 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3309 PCI_EXP_SAVE_REGS * sizeof(u16));
3310 if (error)
3311 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3312
3313 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3314 if (error)
3315 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3316
3317 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3318 2 * sizeof(u16));
3319 if (error)
3320 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3321
3322 pci_allocate_vc_save_buffers(dev);
3323}
3324
3325void pci_free_cap_save_buffers(struct pci_dev *dev)
3326{
3327 struct pci_cap_saved_state *tmp;
3328 struct hlist_node *n;
3329
3330 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3331 kfree(tmp);
3332}
3333
3334/**
3335 * pci_configure_ari - enable or disable ARI forwarding
3336 * @dev: the PCI device
3337 *
3338 * If @dev and its upstream bridge both support ARI, enable ARI in the
3339 * bridge. Otherwise, disable ARI in the bridge.
3340 */
3341void pci_configure_ari(struct pci_dev *dev)
3342{
3343 u32 cap;
3344 struct pci_dev *bridge;
3345
3346 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3347 return;
3348
3349 bridge = dev->bus->self;
3350 if (!bridge)
3351 return;
3352
3353 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3354 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3355 return;
3356
3357 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3358 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3359 PCI_EXP_DEVCTL2_ARI);
3360 bridge->ari_enabled = 1;
3361 } else {
3362 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3363 PCI_EXP_DEVCTL2_ARI);
3364 bridge->ari_enabled = 0;
3365 }
3366}
3367
3368static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3369{
3370 int pos;
3371 u16 cap, ctrl;
3372
3373 pos = pdev->acs_cap;
3374 if (!pos)
3375 return false;
3376
3377 /*
3378 * Except for egress control, capabilities are either required
3379 * or only required if controllable. Features missing from the
3380 * capability field can therefore be assumed as hard-wired enabled.
3381 */
3382 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3383 acs_flags &= (cap | PCI_ACS_EC);
3384
3385 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3386 return (ctrl & acs_flags) == acs_flags;
3387}
3388
3389/**
3390 * pci_acs_enabled - test ACS against required flags for a given device
3391 * @pdev: device to test
3392 * @acs_flags: required PCI ACS flags
3393 *
3394 * Return true if the device supports the provided flags. Automatically
3395 * filters out flags that are not implemented on multifunction devices.
3396 *
3397 * Note that this interface checks the effective ACS capabilities of the
3398 * device rather than the actual capabilities. For instance, most single
3399 * function endpoints are not required to support ACS because they have no
3400 * opportunity for peer-to-peer access. We therefore return 'true'
3401 * regardless of whether the device exposes an ACS capability. This makes
3402 * it much easier for callers of this function to ignore the actual type
3403 * or topology of the device when testing ACS support.
3404 */
3405bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3406{
3407 int ret;
3408
3409 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3410 if (ret >= 0)
3411 return ret > 0;
3412
3413 /*
3414 * Conventional PCI and PCI-X devices never support ACS, either
3415 * effectively or actually. The shared bus topology implies that
3416 * any device on the bus can receive or snoop DMA.
3417 */
3418 if (!pci_is_pcie(pdev))
3419 return false;
3420
3421 switch (pci_pcie_type(pdev)) {
3422 /*
3423 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3424 * but since their primary interface is PCI/X, we conservatively
3425 * handle them as we would a non-PCIe device.
3426 */
3427 case PCI_EXP_TYPE_PCIE_BRIDGE:
3428 /*
3429 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3430 * applicable... must never implement an ACS Extended Capability...".
3431 * This seems arbitrary, but we take a conservative interpretation
3432 * of this statement.
3433 */
3434 case PCI_EXP_TYPE_PCI_BRIDGE:
3435 case PCI_EXP_TYPE_RC_EC:
3436 return false;
3437 /*
3438 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3439 * implement ACS in order to indicate their peer-to-peer capabilities,
3440 * regardless of whether they are single- or multi-function devices.
3441 */
3442 case PCI_EXP_TYPE_DOWNSTREAM:
3443 case PCI_EXP_TYPE_ROOT_PORT:
3444 return pci_acs_flags_enabled(pdev, acs_flags);
3445 /*
3446 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3447 * implemented by the remaining PCIe types to indicate peer-to-peer
3448 * capabilities, but only when they are part of a multifunction
3449 * device. The footnote for section 6.12 indicates the specific
3450 * PCIe types included here.
3451 */
3452 case PCI_EXP_TYPE_ENDPOINT:
3453 case PCI_EXP_TYPE_UPSTREAM:
3454 case PCI_EXP_TYPE_LEG_END:
3455 case PCI_EXP_TYPE_RC_END:
3456 if (!pdev->multifunction)
3457 break;
3458
3459 return pci_acs_flags_enabled(pdev, acs_flags);
3460 }
3461
3462 /*
3463 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3464 * to single function devices with the exception of downstream ports.
3465 */
3466 return true;
3467}
3468
3469/**
3470 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3471 * @start: starting downstream device
3472 * @end: ending upstream device or NULL to search to the root bus
3473 * @acs_flags: required flags
3474 *
3475 * Walk up a device tree from start to end testing PCI ACS support. If
3476 * any step along the way does not support the required flags, return false.
3477 */
3478bool pci_acs_path_enabled(struct pci_dev *start,
3479 struct pci_dev *end, u16 acs_flags)
3480{
3481 struct pci_dev *pdev, *parent = start;
3482
3483 do {
3484 pdev = parent;
3485
3486 if (!pci_acs_enabled(pdev, acs_flags))
3487 return false;
3488
3489 if (pci_is_root_bus(pdev->bus))
3490 return (end == NULL);
3491
3492 parent = pdev->bus->self;
3493 } while (pdev != end);
3494
3495 return true;
3496}
3497
3498/**
3499 * pci_acs_init - Initialize ACS if hardware supports it
3500 * @dev: the PCI device
3501 */
3502void pci_acs_init(struct pci_dev *dev)
3503{
3504 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3505
3506 if (dev->acs_cap)
3507 pci_enable_acs(dev);
3508}
3509
3510/**
3511 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3512 * @pdev: PCI device
3513 * @bar: BAR to find
3514 *
3515 * Helper to find the position of the ctrl register for a BAR.
3516 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3517 * Returns -ENOENT if no ctrl register for the BAR could be found.
3518 */
3519static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3520{
3521 unsigned int pos, nbars, i;
3522 u32 ctrl;
3523
3524 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3525 if (!pos)
3526 return -ENOTSUPP;
3527
3528 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3529 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3530 PCI_REBAR_CTRL_NBAR_SHIFT;
3531
3532 for (i = 0; i < nbars; i++, pos += 8) {
3533 int bar_idx;
3534
3535 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3536 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3537 if (bar_idx == bar)
3538 return pos;
3539 }
3540
3541 return -ENOENT;
3542}
3543
3544/**
3545 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3546 * @pdev: PCI device
3547 * @bar: BAR to query
3548 *
3549 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3550 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3551 */
3552u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3553{
3554 int pos;
3555 u32 cap;
3556
3557 pos = pci_rebar_find_pos(pdev, bar);
3558 if (pos < 0)
3559 return 0;
3560
3561 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3562 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3563}
3564
3565/**
3566 * pci_rebar_get_current_size - get the current size of a BAR
3567 * @pdev: PCI device
3568 * @bar: BAR to set size to
3569 *
3570 * Read the size of a BAR from the resizable BAR config.
3571 * Returns size if found or negative error code.
3572 */
3573int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3574{
3575 int pos;
3576 u32 ctrl;
3577
3578 pos = pci_rebar_find_pos(pdev, bar);
3579 if (pos < 0)
3580 return pos;
3581
3582 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3583 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3584}
3585
3586/**
3587 * pci_rebar_set_size - set a new size for a BAR
3588 * @pdev: PCI device
3589 * @bar: BAR to set size to
3590 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3591 *
3592 * Set the new size of a BAR as defined in the spec.
3593 * Returns zero if resizing was successful, error code otherwise.
3594 */
3595int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3596{
3597 int pos;
3598 u32 ctrl;
3599
3600 pos = pci_rebar_find_pos(pdev, bar);
3601 if (pos < 0)
3602 return pos;
3603
3604 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3605 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3606 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3607 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3608 return 0;
3609}
3610
3611/**
3612 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3613 * @dev: the PCI device
3614 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3615 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3616 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3617 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3618 *
3619 * Return 0 if all upstream bridges support AtomicOp routing, egress
3620 * blocking is disabled on all upstream ports, and the root port supports
3621 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3622 * AtomicOp completion), or negative otherwise.
3623 */
3624int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3625{
3626 struct pci_bus *bus = dev->bus;
3627 struct pci_dev *bridge;
3628 u32 cap, ctl2;
3629
3630 if (!pci_is_pcie(dev))
3631 return -EINVAL;
3632
3633 /*
3634 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3635 * AtomicOp requesters. For now, we only support endpoints as
3636 * requesters and root ports as completers. No endpoints as
3637 * completers, and no peer-to-peer.
3638 */
3639
3640 switch (pci_pcie_type(dev)) {
3641 case PCI_EXP_TYPE_ENDPOINT:
3642 case PCI_EXP_TYPE_LEG_END:
3643 case PCI_EXP_TYPE_RC_END:
3644 break;
3645 default:
3646 return -EINVAL;
3647 }
3648
3649 while (bus->parent) {
3650 bridge = bus->self;
3651
3652 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3653
3654 switch (pci_pcie_type(bridge)) {
3655 /* Ensure switch ports support AtomicOp routing */
3656 case PCI_EXP_TYPE_UPSTREAM:
3657 case PCI_EXP_TYPE_DOWNSTREAM:
3658 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3659 return -EINVAL;
3660 break;
3661
3662 /* Ensure root port supports all the sizes we care about */
3663 case PCI_EXP_TYPE_ROOT_PORT:
3664 if ((cap & cap_mask) != cap_mask)
3665 return -EINVAL;
3666 break;
3667 }
3668
3669 /* Ensure upstream ports don't block AtomicOps on egress */
3670 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3671 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3672 &ctl2);
3673 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3674 return -EINVAL;
3675 }
3676
3677 bus = bus->parent;
3678 }
3679
3680 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3681 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3682 return 0;
3683}
3684EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3685
3686/**
3687 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3688 * @dev: the PCI device
3689 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3690 *
3691 * Perform INTx swizzling for a device behind one level of bridge. This is
3692 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3693 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3694 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3695 * the PCI Express Base Specification, Revision 2.1)
3696 */
3697u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3698{
3699 int slot;
3700
3701 if (pci_ari_enabled(dev->bus))
3702 slot = 0;
3703 else
3704 slot = PCI_SLOT(dev->devfn);
3705
3706 return (((pin - 1) + slot) % 4) + 1;
3707}
3708
3709int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3710{
3711 u8 pin;
3712
3713 pin = dev->pin;
3714 if (!pin)
3715 return -1;
3716
3717 while (!pci_is_root_bus(dev->bus)) {
3718 pin = pci_swizzle_interrupt_pin(dev, pin);
3719 dev = dev->bus->self;
3720 }
3721 *bridge = dev;
3722 return pin;
3723}
3724
3725/**
3726 * pci_common_swizzle - swizzle INTx all the way to root bridge
3727 * @dev: the PCI device
3728 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3729 *
3730 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3731 * bridges all the way up to a PCI root bus.
3732 */
3733u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3734{
3735 u8 pin = *pinp;
3736
3737 while (!pci_is_root_bus(dev->bus)) {
3738 pin = pci_swizzle_interrupt_pin(dev, pin);
3739 dev = dev->bus->self;
3740 }
3741 *pinp = pin;
3742 return PCI_SLOT(dev->devfn);
3743}
3744EXPORT_SYMBOL_GPL(pci_common_swizzle);
3745
3746/**
3747 * pci_release_region - Release a PCI bar
3748 * @pdev: PCI device whose resources were previously reserved by
3749 * pci_request_region()
3750 * @bar: BAR to release
3751 *
3752 * Releases the PCI I/O and memory resources previously reserved by a
3753 * successful call to pci_request_region(). Call this function only
3754 * after all use of the PCI regions has ceased.
3755 */
3756void pci_release_region(struct pci_dev *pdev, int bar)
3757{
3758 struct pci_devres *dr;
3759
3760 if (pci_resource_len(pdev, bar) == 0)
3761 return;
3762 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3763 release_region(pci_resource_start(pdev, bar),
3764 pci_resource_len(pdev, bar));
3765 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3766 release_mem_region(pci_resource_start(pdev, bar),
3767 pci_resource_len(pdev, bar));
3768
3769 dr = find_pci_dr(pdev);
3770 if (dr)
3771 dr->region_mask &= ~(1 << bar);
3772}
3773EXPORT_SYMBOL(pci_release_region);
3774
3775/**
3776 * __pci_request_region - Reserved PCI I/O and memory resource
3777 * @pdev: PCI device whose resources are to be reserved
3778 * @bar: BAR to be reserved
3779 * @res_name: Name to be associated with resource.
3780 * @exclusive: whether the region access is exclusive or not
3781 *
3782 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3783 * being reserved by owner @res_name. Do not access any
3784 * address inside the PCI regions unless this call returns
3785 * successfully.
3786 *
3787 * If @exclusive is set, then the region is marked so that userspace
3788 * is explicitly not allowed to map the resource via /dev/mem or
3789 * sysfs MMIO access.
3790 *
3791 * Returns 0 on success, or %EBUSY on error. A warning
3792 * message is also printed on failure.
3793 */
3794static int __pci_request_region(struct pci_dev *pdev, int bar,
3795 const char *res_name, int exclusive)
3796{
3797 struct pci_devres *dr;
3798
3799 if (pci_resource_len(pdev, bar) == 0)
3800 return 0;
3801
3802 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3803 if (!request_region(pci_resource_start(pdev, bar),
3804 pci_resource_len(pdev, bar), res_name))
3805 goto err_out;
3806 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3807 if (!__request_mem_region(pci_resource_start(pdev, bar),
3808 pci_resource_len(pdev, bar), res_name,
3809 exclusive))
3810 goto err_out;
3811 }
3812
3813 dr = find_pci_dr(pdev);
3814 if (dr)
3815 dr->region_mask |= 1 << bar;
3816
3817 return 0;
3818
3819err_out:
3820 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3821 &pdev->resource[bar]);
3822 return -EBUSY;
3823}
3824
3825/**
3826 * pci_request_region - Reserve PCI I/O and memory resource
3827 * @pdev: PCI device whose resources are to be reserved
3828 * @bar: BAR to be reserved
3829 * @res_name: Name to be associated with resource
3830 *
3831 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3832 * being reserved by owner @res_name. Do not access any
3833 * address inside the PCI regions unless this call returns
3834 * successfully.
3835 *
3836 * Returns 0 on success, or %EBUSY on error. A warning
3837 * message is also printed on failure.
3838 */
3839int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3840{
3841 return __pci_request_region(pdev, bar, res_name, 0);
3842}
3843EXPORT_SYMBOL(pci_request_region);
3844
3845/**
3846 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3847 * @pdev: PCI device whose resources were previously reserved
3848 * @bars: Bitmask of BARs to be released
3849 *
3850 * Release selected PCI I/O and memory resources previously reserved.
3851 * Call this function only after all use of the PCI regions has ceased.
3852 */
3853void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3854{
3855 int i;
3856
3857 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3858 if (bars & (1 << i))
3859 pci_release_region(pdev, i);
3860}
3861EXPORT_SYMBOL(pci_release_selected_regions);
3862
3863static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3864 const char *res_name, int excl)
3865{
3866 int i;
3867
3868 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3869 if (bars & (1 << i))
3870 if (__pci_request_region(pdev, i, res_name, excl))
3871 goto err_out;
3872 return 0;
3873
3874err_out:
3875 while (--i >= 0)
3876 if (bars & (1 << i))
3877 pci_release_region(pdev, i);
3878
3879 return -EBUSY;
3880}
3881
3882
3883/**
3884 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3885 * @pdev: PCI device whose resources are to be reserved
3886 * @bars: Bitmask of BARs to be requested
3887 * @res_name: Name to be associated with resource
3888 */
3889int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3890 const char *res_name)
3891{
3892 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3893}
3894EXPORT_SYMBOL(pci_request_selected_regions);
3895
3896int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3897 const char *res_name)
3898{
3899 return __pci_request_selected_regions(pdev, bars, res_name,
3900 IORESOURCE_EXCLUSIVE);
3901}
3902EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3903
3904/**
3905 * pci_release_regions - Release reserved PCI I/O and memory resources
3906 * @pdev: PCI device whose resources were previously reserved by
3907 * pci_request_regions()
3908 *
3909 * Releases all PCI I/O and memory resources previously reserved by a
3910 * successful call to pci_request_regions(). Call this function only
3911 * after all use of the PCI regions has ceased.
3912 */
3913
3914void pci_release_regions(struct pci_dev *pdev)
3915{
3916 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
3917}
3918EXPORT_SYMBOL(pci_release_regions);
3919
3920/**
3921 * pci_request_regions - Reserve PCI I/O and memory resources
3922 * @pdev: PCI device whose resources are to be reserved
3923 * @res_name: Name to be associated with resource.
3924 *
3925 * Mark all PCI regions associated with PCI device @pdev as
3926 * being reserved by owner @res_name. Do not access any
3927 * address inside the PCI regions unless this call returns
3928 * successfully.
3929 *
3930 * Returns 0 on success, or %EBUSY on error. A warning
3931 * message is also printed on failure.
3932 */
3933int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3934{
3935 return pci_request_selected_regions(pdev,
3936 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3937}
3938EXPORT_SYMBOL(pci_request_regions);
3939
3940/**
3941 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3942 * @pdev: PCI device whose resources are to be reserved
3943 * @res_name: Name to be associated with resource.
3944 *
3945 * Mark all PCI regions associated with PCI device @pdev as being reserved
3946 * by owner @res_name. Do not access any address inside the PCI regions
3947 * unless this call returns successfully.
3948 *
3949 * pci_request_regions_exclusive() will mark the region so that /dev/mem
3950 * and the sysfs MMIO access will not be allowed.
3951 *
3952 * Returns 0 on success, or %EBUSY on error. A warning message is also
3953 * printed on failure.
3954 */
3955int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3956{
3957 return pci_request_selected_regions_exclusive(pdev,
3958 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3959}
3960EXPORT_SYMBOL(pci_request_regions_exclusive);
3961
3962/*
3963 * Record the PCI IO range (expressed as CPU physical address + size).
3964 * Return a negative value if an error has occurred, zero otherwise
3965 */
3966int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3967 resource_size_t size)
3968{
3969 int ret = 0;
3970#ifdef PCI_IOBASE
3971 struct logic_pio_hwaddr *range;
3972
3973 if (!size || addr + size < addr)
3974 return -EINVAL;
3975
3976 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3977 if (!range)
3978 return -ENOMEM;
3979
3980 range->fwnode = fwnode;
3981 range->size = size;
3982 range->hw_start = addr;
3983 range->flags = LOGIC_PIO_CPU_MMIO;
3984
3985 ret = logic_pio_register_range(range);
3986 if (ret)
3987 kfree(range);
3988#endif
3989
3990 return ret;
3991}
3992
3993phys_addr_t pci_pio_to_address(unsigned long pio)
3994{
3995 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3996
3997#ifdef PCI_IOBASE
3998 if (pio >= MMIO_UPPER_LIMIT)
3999 return address;
4000
4001 address = logic_pio_to_hwaddr(pio);
4002#endif
4003
4004 return address;
4005}
4006
4007unsigned long __weak pci_address_to_pio(phys_addr_t address)
4008{
4009#ifdef PCI_IOBASE
4010 return logic_pio_trans_cpuaddr(address);
4011#else
4012 if (address > IO_SPACE_LIMIT)
4013 return (unsigned long)-1;
4014
4015 return (unsigned long) address;
4016#endif
4017}
4018
4019/**
4020 * pci_remap_iospace - Remap the memory mapped I/O space
4021 * @res: Resource describing the I/O space
4022 * @phys_addr: physical address of range to be mapped
4023 *
4024 * Remap the memory mapped I/O space described by the @res and the CPU
4025 * physical address @phys_addr into virtual address space. Only
4026 * architectures that have memory mapped IO functions defined (and the
4027 * PCI_IOBASE value defined) should call this function.
4028 */
4029int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4030{
4031#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4032 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4033
4034 if (!(res->flags & IORESOURCE_IO))
4035 return -EINVAL;
4036
4037 if (res->end > IO_SPACE_LIMIT)
4038 return -EINVAL;
4039
4040 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4041 pgprot_device(PAGE_KERNEL));
4042#else
4043 /*
4044 * This architecture does not have memory mapped I/O space,
4045 * so this function should never be called
4046 */
4047 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4048 return -ENODEV;
4049#endif
4050}
4051EXPORT_SYMBOL(pci_remap_iospace);
4052
4053/**
4054 * pci_unmap_iospace - Unmap the memory mapped I/O space
4055 * @res: resource to be unmapped
4056 *
4057 * Unmap the CPU virtual address @res from virtual address space. Only
4058 * architectures that have memory mapped IO functions defined (and the
4059 * PCI_IOBASE value defined) should call this function.
4060 */
4061void pci_unmap_iospace(struct resource *res)
4062{
4063#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4064 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4065
4066 unmap_kernel_range(vaddr, resource_size(res));
4067#endif
4068}
4069EXPORT_SYMBOL(pci_unmap_iospace);
4070
4071static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4072{
4073 struct resource **res = ptr;
4074
4075 pci_unmap_iospace(*res);
4076}
4077
4078/**
4079 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4080 * @dev: Generic device to remap IO address for
4081 * @res: Resource describing the I/O space
4082 * @phys_addr: physical address of range to be mapped
4083 *
4084 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4085 * detach.
4086 */
4087int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4088 phys_addr_t phys_addr)
4089{
4090 const struct resource **ptr;
4091 int error;
4092
4093 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4094 if (!ptr)
4095 return -ENOMEM;
4096
4097 error = pci_remap_iospace(res, phys_addr);
4098 if (error) {
4099 devres_free(ptr);
4100 } else {
4101 *ptr = res;
4102 devres_add(dev, ptr);
4103 }
4104
4105 return error;
4106}
4107EXPORT_SYMBOL(devm_pci_remap_iospace);
4108
4109/**
4110 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4111 * @dev: Generic device to remap IO address for
4112 * @offset: Resource address to map
4113 * @size: Size of map
4114 *
4115 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4116 * detach.
4117 */
4118void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4119 resource_size_t offset,
4120 resource_size_t size)
4121{
4122 void __iomem **ptr, *addr;
4123
4124 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4125 if (!ptr)
4126 return NULL;
4127
4128 addr = pci_remap_cfgspace(offset, size);
4129 if (addr) {
4130 *ptr = addr;
4131 devres_add(dev, ptr);
4132 } else
4133 devres_free(ptr);
4134
4135 return addr;
4136}
4137EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4138
4139/**
4140 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4141 * @dev: generic device to handle the resource for
4142 * @res: configuration space resource to be handled
4143 *
4144 * Checks that a resource is a valid memory region, requests the memory
4145 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4146 * proper PCI configuration space memory attributes are guaranteed.
4147 *
4148 * All operations are managed and will be undone on driver detach.
4149 *
4150 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4151 * on failure. Usage example::
4152 *
4153 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4154 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4155 * if (IS_ERR(base))
4156 * return PTR_ERR(base);
4157 */
4158void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4159 struct resource *res)
4160{
4161 resource_size_t size;
4162 const char *name;
4163 void __iomem *dest_ptr;
4164
4165 BUG_ON(!dev);
4166
4167 if (!res || resource_type(res) != IORESOURCE_MEM) {
4168 dev_err(dev, "invalid resource\n");
4169 return IOMEM_ERR_PTR(-EINVAL);
4170 }
4171
4172 size = resource_size(res);
4173 name = res->name ?: dev_name(dev);
4174
4175 if (!devm_request_mem_region(dev, res->start, size, name)) {
4176 dev_err(dev, "can't request region for resource %pR\n", res);
4177 return IOMEM_ERR_PTR(-EBUSY);
4178 }
4179
4180 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4181 if (!dest_ptr) {
4182 dev_err(dev, "ioremap failed for resource %pR\n", res);
4183 devm_release_mem_region(dev, res->start, size);
4184 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4185 }
4186
4187 return dest_ptr;
4188}
4189EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4190
4191static void __pci_set_master(struct pci_dev *dev, bool enable)
4192{
4193 u16 old_cmd, cmd;
4194
4195 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4196 if (enable)
4197 cmd = old_cmd | PCI_COMMAND_MASTER;
4198 else
4199 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4200 if (cmd != old_cmd) {
4201 pci_dbg(dev, "%s bus mastering\n",
4202 enable ? "enabling" : "disabling");
4203 pci_write_config_word(dev, PCI_COMMAND, cmd);
4204 }
4205 dev->is_busmaster = enable;
4206}
4207
4208/**
4209 * pcibios_setup - process "pci=" kernel boot arguments
4210 * @str: string used to pass in "pci=" kernel boot arguments
4211 *
4212 * Process kernel boot arguments. This is the default implementation.
4213 * Architecture specific implementations can override this as necessary.
4214 */
4215char * __weak __init pcibios_setup(char *str)
4216{
4217 return str;
4218}
4219
4220/**
4221 * pcibios_set_master - enable PCI bus-mastering for device dev
4222 * @dev: the PCI device to enable
4223 *
4224 * Enables PCI bus-mastering for the device. This is the default
4225 * implementation. Architecture specific implementations can override
4226 * this if necessary.
4227 */
4228void __weak pcibios_set_master(struct pci_dev *dev)
4229{
4230 u8 lat;
4231
4232 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4233 if (pci_is_pcie(dev))
4234 return;
4235
4236 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4237 if (lat < 16)
4238 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4239 else if (lat > pcibios_max_latency)
4240 lat = pcibios_max_latency;
4241 else
4242 return;
4243
4244 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4245}
4246
4247/**
4248 * pci_set_master - enables bus-mastering for device dev
4249 * @dev: the PCI device to enable
4250 *
4251 * Enables bus-mastering on the device and calls pcibios_set_master()
4252 * to do the needed arch specific settings.
4253 */
4254void pci_set_master(struct pci_dev *dev)
4255{
4256 __pci_set_master(dev, true);
4257 pcibios_set_master(dev);
4258}
4259EXPORT_SYMBOL(pci_set_master);
4260
4261/**
4262 * pci_clear_master - disables bus-mastering for device dev
4263 * @dev: the PCI device to disable
4264 */
4265void pci_clear_master(struct pci_dev *dev)
4266{
4267 __pci_set_master(dev, false);
4268}
4269EXPORT_SYMBOL(pci_clear_master);
4270
4271/**
4272 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4273 * @dev: the PCI device for which MWI is to be enabled
4274 *
4275 * Helper function for pci_set_mwi.
4276 * Originally copied from drivers/net/acenic.c.
4277 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4278 *
4279 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4280 */
4281int pci_set_cacheline_size(struct pci_dev *dev)
4282{
4283 u8 cacheline_size;
4284
4285 if (!pci_cache_line_size)
4286 return -EINVAL;
4287
4288 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4289 equal to or multiple of the right value. */
4290 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4291 if (cacheline_size >= pci_cache_line_size &&
4292 (cacheline_size % pci_cache_line_size) == 0)
4293 return 0;
4294
4295 /* Write the correct value. */
4296 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4297 /* Read it back. */
4298 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4299 if (cacheline_size == pci_cache_line_size)
4300 return 0;
4301
4302 pci_info(dev, "cache line size of %d is not supported\n",
4303 pci_cache_line_size << 2);
4304
4305 return -EINVAL;
4306}
4307EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4308
4309/**
4310 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4311 * @dev: the PCI device for which MWI is enabled
4312 *
4313 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4314 *
4315 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4316 */
4317int pci_set_mwi(struct pci_dev *dev)
4318{
4319#ifdef PCI_DISABLE_MWI
4320 return 0;
4321#else
4322 int rc;
4323 u16 cmd;
4324
4325 rc = pci_set_cacheline_size(dev);
4326 if (rc)
4327 return rc;
4328
4329 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4330 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4331 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4332 cmd |= PCI_COMMAND_INVALIDATE;
4333 pci_write_config_word(dev, PCI_COMMAND, cmd);
4334 }
4335 return 0;
4336#endif
4337}
4338EXPORT_SYMBOL(pci_set_mwi);
4339
4340/**
4341 * pcim_set_mwi - a device-managed pci_set_mwi()
4342 * @dev: the PCI device for which MWI is enabled
4343 *
4344 * Managed pci_set_mwi().
4345 *
4346 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4347 */
4348int pcim_set_mwi(struct pci_dev *dev)
4349{
4350 struct pci_devres *dr;
4351
4352 dr = find_pci_dr(dev);
4353 if (!dr)
4354 return -ENOMEM;
4355
4356 dr->mwi = 1;
4357 return pci_set_mwi(dev);
4358}
4359EXPORT_SYMBOL(pcim_set_mwi);
4360
4361/**
4362 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4363 * @dev: the PCI device for which MWI is enabled
4364 *
4365 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4366 * Callers are not required to check the return value.
4367 *
4368 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4369 */
4370int pci_try_set_mwi(struct pci_dev *dev)
4371{
4372#ifdef PCI_DISABLE_MWI
4373 return 0;
4374#else
4375 return pci_set_mwi(dev);
4376#endif
4377}
4378EXPORT_SYMBOL(pci_try_set_mwi);
4379
4380/**
4381 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4382 * @dev: the PCI device to disable
4383 *
4384 * Disables PCI Memory-Write-Invalidate transaction on the device
4385 */
4386void pci_clear_mwi(struct pci_dev *dev)
4387{
4388#ifndef PCI_DISABLE_MWI
4389 u16 cmd;
4390
4391 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4392 if (cmd & PCI_COMMAND_INVALIDATE) {
4393 cmd &= ~PCI_COMMAND_INVALIDATE;
4394 pci_write_config_word(dev, PCI_COMMAND, cmd);
4395 }
4396#endif
4397}
4398EXPORT_SYMBOL(pci_clear_mwi);
4399
4400/**
4401 * pci_intx - enables/disables PCI INTx for device dev
4402 * @pdev: the PCI device to operate on
4403 * @enable: boolean: whether to enable or disable PCI INTx
4404 *
4405 * Enables/disables PCI INTx for device @pdev
4406 */
4407void pci_intx(struct pci_dev *pdev, int enable)
4408{
4409 u16 pci_command, new;
4410
4411 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4412
4413 if (enable)
4414 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4415 else
4416 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4417
4418 if (new != pci_command) {
4419 struct pci_devres *dr;
4420
4421 pci_write_config_word(pdev, PCI_COMMAND, new);
4422
4423 dr = find_pci_dr(pdev);
4424 if (dr && !dr->restore_intx) {
4425 dr->restore_intx = 1;
4426 dr->orig_intx = !enable;
4427 }
4428 }
4429}
4430EXPORT_SYMBOL_GPL(pci_intx);
4431
4432static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4433{
4434 struct pci_bus *bus = dev->bus;
4435 bool mask_updated = true;
4436 u32 cmd_status_dword;
4437 u16 origcmd, newcmd;
4438 unsigned long flags;
4439 bool irq_pending;
4440
4441 /*
4442 * We do a single dword read to retrieve both command and status.
4443 * Document assumptions that make this possible.
4444 */
4445 BUILD_BUG_ON(PCI_COMMAND % 4);
4446 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4447
4448 raw_spin_lock_irqsave(&pci_lock, flags);
4449
4450 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4451
4452 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4453
4454 /*
4455 * Check interrupt status register to see whether our device
4456 * triggered the interrupt (when masking) or the next IRQ is
4457 * already pending (when unmasking).
4458 */
4459 if (mask != irq_pending) {
4460 mask_updated = false;
4461 goto done;
4462 }
4463
4464 origcmd = cmd_status_dword;
4465 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4466 if (mask)
4467 newcmd |= PCI_COMMAND_INTX_DISABLE;
4468 if (newcmd != origcmd)
4469 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4470
4471done:
4472 raw_spin_unlock_irqrestore(&pci_lock, flags);
4473
4474 return mask_updated;
4475}
4476
4477/**
4478 * pci_check_and_mask_intx - mask INTx on pending interrupt
4479 * @dev: the PCI device to operate on
4480 *
4481 * Check if the device dev has its INTx line asserted, mask it and return
4482 * true in that case. False is returned if no interrupt was pending.
4483 */
4484bool pci_check_and_mask_intx(struct pci_dev *dev)
4485{
4486 return pci_check_and_set_intx_mask(dev, true);
4487}
4488EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4489
4490/**
4491 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4492 * @dev: the PCI device to operate on
4493 *
4494 * Check if the device dev has its INTx line asserted, unmask it if not and
4495 * return true. False is returned and the mask remains active if there was
4496 * still an interrupt pending.
4497 */
4498bool pci_check_and_unmask_intx(struct pci_dev *dev)
4499{
4500 return pci_check_and_set_intx_mask(dev, false);
4501}
4502EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4503
4504/**
4505 * pci_wait_for_pending_transaction - wait for pending transaction
4506 * @dev: the PCI device to operate on
4507 *
4508 * Return 0 if transaction is pending 1 otherwise.
4509 */
4510int pci_wait_for_pending_transaction(struct pci_dev *dev)
4511{
4512 if (!pci_is_pcie(dev))
4513 return 1;
4514
4515 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4516 PCI_EXP_DEVSTA_TRPND);
4517}
4518EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4519
4520/**
4521 * pcie_has_flr - check if a device supports function level resets
4522 * @dev: device to check
4523 *
4524 * Returns true if the device advertises support for PCIe function level
4525 * resets.
4526 */
4527bool pcie_has_flr(struct pci_dev *dev)
4528{
4529 u32 cap;
4530
4531 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4532 return false;
4533
4534 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4535 return cap & PCI_EXP_DEVCAP_FLR;
4536}
4537EXPORT_SYMBOL_GPL(pcie_has_flr);
4538
4539/**
4540 * pcie_flr - initiate a PCIe function level reset
4541 * @dev: device to reset
4542 *
4543 * Initiate a function level reset on @dev. The caller should ensure the
4544 * device supports FLR before calling this function, e.g. by using the
4545 * pcie_has_flr() helper.
4546 */
4547int pcie_flr(struct pci_dev *dev)
4548{
4549 if (!pci_wait_for_pending_transaction(dev))
4550 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4551
4552 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4553
4554 if (dev->imm_ready)
4555 return 0;
4556
4557 /*
4558 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4559 * 100ms, but may silently discard requests while the FLR is in
4560 * progress. Wait 100ms before trying to access the device.
4561 */
4562 msleep(100);
4563
4564 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4565}
4566EXPORT_SYMBOL_GPL(pcie_flr);
4567
4568static int pci_af_flr(struct pci_dev *dev, int probe)
4569{
4570 int pos;
4571 u8 cap;
4572
4573 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4574 if (!pos)
4575 return -ENOTTY;
4576
4577 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4578 return -ENOTTY;
4579
4580 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4581 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4582 return -ENOTTY;
4583
4584 if (probe)
4585 return 0;
4586
4587 /*
4588 * Wait for Transaction Pending bit to clear. A word-aligned test
4589 * is used, so we use the control offset rather than status and shift
4590 * the test bit to match.
4591 */
4592 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4593 PCI_AF_STATUS_TP << 8))
4594 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4595
4596 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4597
4598 if (dev->imm_ready)
4599 return 0;
4600
4601 /*
4602 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4603 * updated 27 July 2006; a device must complete an FLR within
4604 * 100ms, but may silently discard requests while the FLR is in
4605 * progress. Wait 100ms before trying to access the device.
4606 */
4607 msleep(100);
4608
4609 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4610}
4611
4612/**
4613 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4614 * @dev: Device to reset.
4615 * @probe: If set, only check if the device can be reset this way.
4616 *
4617 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4618 * unset, it will be reinitialized internally when going from PCI_D3hot to
4619 * PCI_D0. If that's the case and the device is not in a low-power state
4620 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4621 *
4622 * NOTE: This causes the caller to sleep for twice the device power transition
4623 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4624 * by default (i.e. unless the @dev's d3_delay field has a different value).
4625 * Moreover, only devices in D0 can be reset by this function.
4626 */
4627static int pci_pm_reset(struct pci_dev *dev, int probe)
4628{
4629 u16 csr;
4630
4631 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4632 return -ENOTTY;
4633
4634 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4635 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4636 return -ENOTTY;
4637
4638 if (probe)
4639 return 0;
4640
4641 if (dev->current_state != PCI_D0)
4642 return -EINVAL;
4643
4644 csr &= ~PCI_PM_CTRL_STATE_MASK;
4645 csr |= PCI_D3hot;
4646 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4647 pci_dev_d3_sleep(dev);
4648
4649 csr &= ~PCI_PM_CTRL_STATE_MASK;
4650 csr |= PCI_D0;
4651 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4652 pci_dev_d3_sleep(dev);
4653
4654 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4655}
4656
4657/**
4658 * pcie_wait_for_link_delay - Wait until link is active or inactive
4659 * @pdev: Bridge device
4660 * @active: waiting for active or inactive?
4661 * @delay: Delay to wait after link has become active (in ms)
4662 *
4663 * Use this to wait till link becomes active or inactive.
4664 */
4665static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4666 int delay)
4667{
4668 int timeout = 1000;
4669 bool ret;
4670 u16 lnk_status;
4671
4672 /*
4673 * Some controllers might not implement link active reporting. In this
4674 * case, we wait for 1000 ms + any delay requested by the caller.
4675 */
4676 if (!pdev->link_active_reporting) {
4677 msleep(timeout + delay);
4678 return true;
4679 }
4680
4681 /*
4682 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4683 * after which we should expect an link active if the reset was
4684 * successful. If so, software must wait a minimum 100ms before sending
4685 * configuration requests to devices downstream this port.
4686 *
4687 * If the link fails to activate, either the device was physically
4688 * removed or the link is permanently failed.
4689 */
4690 if (active)
4691 msleep(20);
4692 for (;;) {
4693 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4694 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4695 if (ret == active)
4696 break;
4697 if (timeout <= 0)
4698 break;
4699 msleep(10);
4700 timeout -= 10;
4701 }
4702 if (active && ret)
4703 msleep(delay);
4704 else if (ret != active)
4705 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4706 active ? "set" : "cleared");
4707 return ret == active;
4708}
4709
4710/**
4711 * pcie_wait_for_link - Wait until link is active or inactive
4712 * @pdev: Bridge device
4713 * @active: waiting for active or inactive?
4714 *
4715 * Use this to wait till link becomes active or inactive.
4716 */
4717bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4718{
4719 return pcie_wait_for_link_delay(pdev, active, 100);
4720}
4721
4722/*
4723 * Find maximum D3cold delay required by all the devices on the bus. The
4724 * spec says 100 ms, but firmware can lower it and we allow drivers to
4725 * increase it as well.
4726 *
4727 * Called with @pci_bus_sem locked for reading.
4728 */
4729static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4730{
4731 const struct pci_dev *pdev;
4732 int min_delay = 100;
4733 int max_delay = 0;
4734
4735 list_for_each_entry(pdev, &bus->devices, bus_list) {
4736 if (pdev->d3cold_delay < min_delay)
4737 min_delay = pdev->d3cold_delay;
4738 if (pdev->d3cold_delay > max_delay)
4739 max_delay = pdev->d3cold_delay;
4740 }
4741
4742 return max(min_delay, max_delay);
4743}
4744
4745/**
4746 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4747 * @dev: PCI bridge
4748 *
4749 * Handle necessary delays before access to the devices on the secondary
4750 * side of the bridge are permitted after D3cold to D0 transition.
4751 *
4752 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4753 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4754 * 4.3.2.
4755 */
4756void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4757{
4758 struct pci_dev *child;
4759 int delay;
4760
4761 if (pci_dev_is_disconnected(dev))
4762 return;
4763
4764 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4765 return;
4766
4767 down_read(&pci_bus_sem);
4768
4769 /*
4770 * We only deal with devices that are present currently on the bus.
4771 * For any hot-added devices the access delay is handled in pciehp
4772 * board_added(). In case of ACPI hotplug the firmware is expected
4773 * to configure the devices before OS is notified.
4774 */
4775 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4776 up_read(&pci_bus_sem);
4777 return;
4778 }
4779
4780 /* Take d3cold_delay requirements into account */
4781 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4782 if (!delay) {
4783 up_read(&pci_bus_sem);
4784 return;
4785 }
4786
4787 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4788 bus_list);
4789 up_read(&pci_bus_sem);
4790
4791 /*
4792 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4793 * accessing the device after reset (that is 1000 ms + 100 ms). In
4794 * practice this should not be needed because we don't do power
4795 * management for them (see pci_bridge_d3_possible()).
4796 */
4797 if (!pci_is_pcie(dev)) {
4798 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4799 msleep(1000 + delay);
4800 return;
4801 }
4802
4803 /*
4804 * For PCIe downstream and root ports that do not support speeds
4805 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4806 * speeds (gen3) we need to wait first for the data link layer to
4807 * become active.
4808 *
4809 * However, 100 ms is the minimum and the PCIe spec says the
4810 * software must allow at least 1s before it can determine that the
4811 * device that did not respond is a broken device. There is
4812 * evidence that 100 ms is not always enough, for example certain
4813 * Titan Ridge xHCI controller does not always respond to
4814 * configuration requests if we only wait for 100 ms (see
4815 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4816 *
4817 * Therefore we wait for 100 ms and check for the device presence.
4818 * If it is still not present give it an additional 100 ms.
4819 */
4820 if (!pcie_downstream_port(dev))
4821 return;
4822
4823 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4824 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4825 msleep(delay);
4826 } else {
4827 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4828 delay);
4829 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4830 /* Did not train, no need to wait any further */
4831 return;
4832 }
4833 }
4834
4835 if (!pci_device_is_present(child)) {
4836 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4837 msleep(delay);
4838 }
4839}
4840
4841void pci_reset_secondary_bus(struct pci_dev *dev)
4842{
4843 u16 ctrl;
4844
4845 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4846 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4847 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4848
4849 /*
4850 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4851 * this to 2ms to ensure that we meet the minimum requirement.
4852 */
4853 msleep(2);
4854
4855 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4856 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4857
4858 /*
4859 * Trhfa for conventional PCI is 2^25 clock cycles.
4860 * Assuming a minimum 33MHz clock this results in a 1s
4861 * delay before we can consider subordinate devices to
4862 * be re-initialized. PCIe has some ways to shorten this,
4863 * but we don't make use of them yet.
4864 */
4865 ssleep(1);
4866}
4867
4868void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4869{
4870 pci_reset_secondary_bus(dev);
4871}
4872
4873/**
4874 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4875 * @dev: Bridge device
4876 *
4877 * Use the bridge control register to assert reset on the secondary bus.
4878 * Devices on the secondary bus are left in power-on state.
4879 */
4880int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4881{
4882 pcibios_reset_secondary_bus(dev);
4883
4884 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4885}
4886EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4887
4888static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4889{
4890 struct pci_dev *pdev;
4891
4892 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4893 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4894 return -ENOTTY;
4895
4896 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4897 if (pdev != dev)
4898 return -ENOTTY;
4899
4900 if (probe)
4901 return 0;
4902
4903 return pci_bridge_secondary_bus_reset(dev->bus->self);
4904}
4905
4906static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4907{
4908 int rc = -ENOTTY;
4909
4910 if (!hotplug || !try_module_get(hotplug->owner))
4911 return rc;
4912
4913 if (hotplug->ops->reset_slot)
4914 rc = hotplug->ops->reset_slot(hotplug, probe);
4915
4916 module_put(hotplug->owner);
4917
4918 return rc;
4919}
4920
4921static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4922{
4923 struct pci_dev *pdev;
4924
4925 if (dev->subordinate || !dev->slot ||
4926 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4927 return -ENOTTY;
4928
4929 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4930 if (pdev != dev && pdev->slot == dev->slot)
4931 return -ENOTTY;
4932
4933 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4934}
4935
4936static void pci_dev_lock(struct pci_dev *dev)
4937{
4938 pci_cfg_access_lock(dev);
4939 /* block PM suspend, driver probe, etc. */
4940 device_lock(&dev->dev);
4941}
4942
4943/* Return 1 on successful lock, 0 on contention */
4944static int pci_dev_trylock(struct pci_dev *dev)
4945{
4946 if (pci_cfg_access_trylock(dev)) {
4947 if (device_trylock(&dev->dev))
4948 return 1;
4949 pci_cfg_access_unlock(dev);
4950 }
4951
4952 return 0;
4953}
4954
4955static void pci_dev_unlock(struct pci_dev *dev)
4956{
4957 device_unlock(&dev->dev);
4958 pci_cfg_access_unlock(dev);
4959}
4960
4961static void pci_dev_save_and_disable(struct pci_dev *dev)
4962{
4963 const struct pci_error_handlers *err_handler =
4964 dev->driver ? dev->driver->err_handler : NULL;
4965
4966 /*
4967 * dev->driver->err_handler->reset_prepare() is protected against
4968 * races with ->remove() by the device lock, which must be held by
4969 * the caller.
4970 */
4971 if (err_handler && err_handler->reset_prepare)
4972 err_handler->reset_prepare(dev);
4973
4974 /*
4975 * Wake-up device prior to save. PM registers default to D0 after
4976 * reset and a simple register restore doesn't reliably return
4977 * to a non-D0 state anyway.
4978 */
4979 pci_set_power_state(dev, PCI_D0);
4980
4981 pci_save_state(dev);
4982 /*
4983 * Disable the device by clearing the Command register, except for
4984 * INTx-disable which is set. This not only disables MMIO and I/O port
4985 * BARs, but also prevents the device from being Bus Master, preventing
4986 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4987 * compliant devices, INTx-disable prevents legacy interrupts.
4988 */
4989 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4990}
4991
4992static void pci_dev_restore(struct pci_dev *dev)
4993{
4994 const struct pci_error_handlers *err_handler =
4995 dev->driver ? dev->driver->err_handler : NULL;
4996
4997 pci_restore_state(dev);
4998
4999 /*
5000 * dev->driver->err_handler->reset_done() is protected against
5001 * races with ->remove() by the device lock, which must be held by
5002 * the caller.
5003 */
5004 if (err_handler && err_handler->reset_done)
5005 err_handler->reset_done(dev);
5006}
5007
5008/**
5009 * __pci_reset_function_locked - reset a PCI device function while holding
5010 * the @dev mutex lock.
5011 * @dev: PCI device to reset
5012 *
5013 * Some devices allow an individual function to be reset without affecting
5014 * other functions in the same device. The PCI device must be responsive
5015 * to PCI config space in order to use this function.
5016 *
5017 * The device function is presumed to be unused and the caller is holding
5018 * the device mutex lock when this function is called.
5019 *
5020 * Resetting the device will make the contents of PCI configuration space
5021 * random, so any caller of this must be prepared to reinitialise the
5022 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5023 * etc.
5024 *
5025 * Returns 0 if the device function was successfully reset or negative if the
5026 * device doesn't support resetting a single function.
5027 */
5028int __pci_reset_function_locked(struct pci_dev *dev)
5029{
5030 int rc;
5031
5032 might_sleep();
5033
5034 /*
5035 * A reset method returns -ENOTTY if it doesn't support this device
5036 * and we should try the next method.
5037 *
5038 * If it returns 0 (success), we're finished. If it returns any
5039 * other error, we're also finished: this indicates that further
5040 * reset mechanisms might be broken on the device.
5041 */
5042 rc = pci_dev_specific_reset(dev, 0);
5043 if (rc != -ENOTTY)
5044 return rc;
5045 if (pcie_has_flr(dev)) {
5046 rc = pcie_flr(dev);
5047 if (rc != -ENOTTY)
5048 return rc;
5049 }
5050 rc = pci_af_flr(dev, 0);
5051 if (rc != -ENOTTY)
5052 return rc;
5053 rc = pci_pm_reset(dev, 0);
5054 if (rc != -ENOTTY)
5055 return rc;
5056 rc = pci_dev_reset_slot_function(dev, 0);
5057 if (rc != -ENOTTY)
5058 return rc;
5059 return pci_parent_bus_reset(dev, 0);
5060}
5061EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5062
5063/**
5064 * pci_probe_reset_function - check whether the device can be safely reset
5065 * @dev: PCI device to reset
5066 *
5067 * Some devices allow an individual function to be reset without affecting
5068 * other functions in the same device. The PCI device must be responsive
5069 * to PCI config space in order to use this function.
5070 *
5071 * Returns 0 if the device function can be reset or negative if the
5072 * device doesn't support resetting a single function.
5073 */
5074int pci_probe_reset_function(struct pci_dev *dev)
5075{
5076 int rc;
5077
5078 might_sleep();
5079
5080 rc = pci_dev_specific_reset(dev, 1);
5081 if (rc != -ENOTTY)
5082 return rc;
5083 if (pcie_has_flr(dev))
5084 return 0;
5085 rc = pci_af_flr(dev, 1);
5086 if (rc != -ENOTTY)
5087 return rc;
5088 rc = pci_pm_reset(dev, 1);
5089 if (rc != -ENOTTY)
5090 return rc;
5091 rc = pci_dev_reset_slot_function(dev, 1);
5092 if (rc != -ENOTTY)
5093 return rc;
5094
5095 return pci_parent_bus_reset(dev, 1);
5096}
5097
5098/**
5099 * pci_reset_function - quiesce and reset a PCI device function
5100 * @dev: PCI device to reset
5101 *
5102 * Some devices allow an individual function to be reset without affecting
5103 * other functions in the same device. The PCI device must be responsive
5104 * to PCI config space in order to use this function.
5105 *
5106 * This function does not just reset the PCI portion of a device, but
5107 * clears all the state associated with the device. This function differs
5108 * from __pci_reset_function_locked() in that it saves and restores device state
5109 * over the reset and takes the PCI device lock.
5110 *
5111 * Returns 0 if the device function was successfully reset or negative if the
5112 * device doesn't support resetting a single function.
5113 */
5114int pci_reset_function(struct pci_dev *dev)
5115{
5116 int rc;
5117
5118 if (!dev->reset_fn)
5119 return -ENOTTY;
5120
5121 pci_dev_lock(dev);
5122 pci_dev_save_and_disable(dev);
5123
5124 rc = __pci_reset_function_locked(dev);
5125
5126 pci_dev_restore(dev);
5127 pci_dev_unlock(dev);
5128
5129 return rc;
5130}
5131EXPORT_SYMBOL_GPL(pci_reset_function);
5132
5133/**
5134 * pci_reset_function_locked - quiesce and reset a PCI device function
5135 * @dev: PCI device to reset
5136 *
5137 * Some devices allow an individual function to be reset without affecting
5138 * other functions in the same device. The PCI device must be responsive
5139 * to PCI config space in order to use this function.
5140 *
5141 * This function does not just reset the PCI portion of a device, but
5142 * clears all the state associated with the device. This function differs
5143 * from __pci_reset_function_locked() in that it saves and restores device state
5144 * over the reset. It also differs from pci_reset_function() in that it
5145 * requires the PCI device lock to be held.
5146 *
5147 * Returns 0 if the device function was successfully reset or negative if the
5148 * device doesn't support resetting a single function.
5149 */
5150int pci_reset_function_locked(struct pci_dev *dev)
5151{
5152 int rc;
5153
5154 if (!dev->reset_fn)
5155 return -ENOTTY;
5156
5157 pci_dev_save_and_disable(dev);
5158
5159 rc = __pci_reset_function_locked(dev);
5160
5161 pci_dev_restore(dev);
5162
5163 return rc;
5164}
5165EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5166
5167/**
5168 * pci_try_reset_function - quiesce and reset a PCI device function
5169 * @dev: PCI device to reset
5170 *
5171 * Same as above, except return -EAGAIN if unable to lock device.
5172 */
5173int pci_try_reset_function(struct pci_dev *dev)
5174{
5175 int rc;
5176
5177 if (!dev->reset_fn)
5178 return -ENOTTY;
5179
5180 if (!pci_dev_trylock(dev))
5181 return -EAGAIN;
5182
5183 pci_dev_save_and_disable(dev);
5184 rc = __pci_reset_function_locked(dev);
5185 pci_dev_restore(dev);
5186 pci_dev_unlock(dev);
5187
5188 return rc;
5189}
5190EXPORT_SYMBOL_GPL(pci_try_reset_function);
5191
5192/* Do any devices on or below this bus prevent a bus reset? */
5193static bool pci_bus_resetable(struct pci_bus *bus)
5194{
5195 struct pci_dev *dev;
5196
5197
5198 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5199 return false;
5200
5201 list_for_each_entry(dev, &bus->devices, bus_list) {
5202 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5203 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5204 return false;
5205 }
5206
5207 return true;
5208}
5209
5210/* Lock devices from the top of the tree down */
5211static void pci_bus_lock(struct pci_bus *bus)
5212{
5213 struct pci_dev *dev;
5214
5215 list_for_each_entry(dev, &bus->devices, bus_list) {
5216 pci_dev_lock(dev);
5217 if (dev->subordinate)
5218 pci_bus_lock(dev->subordinate);
5219 }
5220}
5221
5222/* Unlock devices from the bottom of the tree up */
5223static void pci_bus_unlock(struct pci_bus *bus)
5224{
5225 struct pci_dev *dev;
5226
5227 list_for_each_entry(dev, &bus->devices, bus_list) {
5228 if (dev->subordinate)
5229 pci_bus_unlock(dev->subordinate);
5230 pci_dev_unlock(dev);
5231 }
5232}
5233
5234/* Return 1 on successful lock, 0 on contention */
5235static int pci_bus_trylock(struct pci_bus *bus)
5236{
5237 struct pci_dev *dev;
5238
5239 list_for_each_entry(dev, &bus->devices, bus_list) {
5240 if (!pci_dev_trylock(dev))
5241 goto unlock;
5242 if (dev->subordinate) {
5243 if (!pci_bus_trylock(dev->subordinate)) {
5244 pci_dev_unlock(dev);
5245 goto unlock;
5246 }
5247 }
5248 }
5249 return 1;
5250
5251unlock:
5252 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5253 if (dev->subordinate)
5254 pci_bus_unlock(dev->subordinate);
5255 pci_dev_unlock(dev);
5256 }
5257 return 0;
5258}
5259
5260/* Do any devices on or below this slot prevent a bus reset? */
5261static bool pci_slot_resetable(struct pci_slot *slot)
5262{
5263 struct pci_dev *dev;
5264
5265 if (slot->bus->self &&
5266 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5267 return false;
5268
5269 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5270 if (!dev->slot || dev->slot != slot)
5271 continue;
5272 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5273 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5274 return false;
5275 }
5276
5277 return true;
5278}
5279
5280/* Lock devices from the top of the tree down */
5281static void pci_slot_lock(struct pci_slot *slot)
5282{
5283 struct pci_dev *dev;
5284
5285 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5286 if (!dev->slot || dev->slot != slot)
5287 continue;
5288 pci_dev_lock(dev);
5289 if (dev->subordinate)
5290 pci_bus_lock(dev->subordinate);
5291 }
5292}
5293
5294/* Unlock devices from the bottom of the tree up */
5295static void pci_slot_unlock(struct pci_slot *slot)
5296{
5297 struct pci_dev *dev;
5298
5299 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5300 if (!dev->slot || dev->slot != slot)
5301 continue;
5302 if (dev->subordinate)
5303 pci_bus_unlock(dev->subordinate);
5304 pci_dev_unlock(dev);
5305 }
5306}
5307
5308/* Return 1 on successful lock, 0 on contention */
5309static int pci_slot_trylock(struct pci_slot *slot)
5310{
5311 struct pci_dev *dev;
5312
5313 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5314 if (!dev->slot || dev->slot != slot)
5315 continue;
5316 if (!pci_dev_trylock(dev))
5317 goto unlock;
5318 if (dev->subordinate) {
5319 if (!pci_bus_trylock(dev->subordinate)) {
5320 pci_dev_unlock(dev);
5321 goto unlock;
5322 }
5323 }
5324 }
5325 return 1;
5326
5327unlock:
5328 list_for_each_entry_continue_reverse(dev,
5329 &slot->bus->devices, bus_list) {
5330 if (!dev->slot || dev->slot != slot)
5331 continue;
5332 if (dev->subordinate)
5333 pci_bus_unlock(dev->subordinate);
5334 pci_dev_unlock(dev);
5335 }
5336 return 0;
5337}
5338
5339/*
5340 * Save and disable devices from the top of the tree down while holding
5341 * the @dev mutex lock for the entire tree.
5342 */
5343static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5344{
5345 struct pci_dev *dev;
5346
5347 list_for_each_entry(dev, &bus->devices, bus_list) {
5348 pci_dev_save_and_disable(dev);
5349 if (dev->subordinate)
5350 pci_bus_save_and_disable_locked(dev->subordinate);
5351 }
5352}
5353
5354/*
5355 * Restore devices from top of the tree down while holding @dev mutex lock
5356 * for the entire tree. Parent bridges need to be restored before we can
5357 * get to subordinate devices.
5358 */
5359static void pci_bus_restore_locked(struct pci_bus *bus)
5360{
5361 struct pci_dev *dev;
5362
5363 list_for_each_entry(dev, &bus->devices, bus_list) {
5364 pci_dev_restore(dev);
5365 if (dev->subordinate)
5366 pci_bus_restore_locked(dev->subordinate);
5367 }
5368}
5369
5370/*
5371 * Save and disable devices from the top of the tree down while holding
5372 * the @dev mutex lock for the entire tree.
5373 */
5374static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5375{
5376 struct pci_dev *dev;
5377
5378 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5379 if (!dev->slot || dev->slot != slot)
5380 continue;
5381 pci_dev_save_and_disable(dev);
5382 if (dev->subordinate)
5383 pci_bus_save_and_disable_locked(dev->subordinate);
5384 }
5385}
5386
5387/*
5388 * Restore devices from top of the tree down while holding @dev mutex lock
5389 * for the entire tree. Parent bridges need to be restored before we can
5390 * get to subordinate devices.
5391 */
5392static void pci_slot_restore_locked(struct pci_slot *slot)
5393{
5394 struct pci_dev *dev;
5395
5396 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5397 if (!dev->slot || dev->slot != slot)
5398 continue;
5399 pci_dev_restore(dev);
5400 if (dev->subordinate)
5401 pci_bus_restore_locked(dev->subordinate);
5402 }
5403}
5404
5405static int pci_slot_reset(struct pci_slot *slot, int probe)
5406{
5407 int rc;
5408
5409 if (!slot || !pci_slot_resetable(slot))
5410 return -ENOTTY;
5411
5412 if (!probe)
5413 pci_slot_lock(slot);
5414
5415 might_sleep();
5416
5417 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5418
5419 if (!probe)
5420 pci_slot_unlock(slot);
5421
5422 return rc;
5423}
5424
5425/**
5426 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5427 * @slot: PCI slot to probe
5428 *
5429 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5430 */
5431int pci_probe_reset_slot(struct pci_slot *slot)
5432{
5433 return pci_slot_reset(slot, 1);
5434}
5435EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5436
5437/**
5438 * __pci_reset_slot - Try to reset a PCI slot
5439 * @slot: PCI slot to reset
5440 *
5441 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5442 * independent of other slots. For instance, some slots may support slot power
5443 * control. In the case of a 1:1 bus to slot architecture, this function may
5444 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5445 * Generally a slot reset should be attempted before a bus reset. All of the
5446 * function of the slot and any subordinate buses behind the slot are reset
5447 * through this function. PCI config space of all devices in the slot and
5448 * behind the slot is saved before and restored after reset.
5449 *
5450 * Same as above except return -EAGAIN if the slot cannot be locked
5451 */
5452static int __pci_reset_slot(struct pci_slot *slot)
5453{
5454 int rc;
5455
5456 rc = pci_slot_reset(slot, 1);
5457 if (rc)
5458 return rc;
5459
5460 if (pci_slot_trylock(slot)) {
5461 pci_slot_save_and_disable_locked(slot);
5462 might_sleep();
5463 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5464 pci_slot_restore_locked(slot);
5465 pci_slot_unlock(slot);
5466 } else
5467 rc = -EAGAIN;
5468
5469 return rc;
5470}
5471
5472static int pci_bus_reset(struct pci_bus *bus, int probe)
5473{
5474 int ret;
5475
5476 if (!bus->self || !pci_bus_resetable(bus))
5477 return -ENOTTY;
5478
5479 if (probe)
5480 return 0;
5481
5482 pci_bus_lock(bus);
5483
5484 might_sleep();
5485
5486 ret = pci_bridge_secondary_bus_reset(bus->self);
5487
5488 pci_bus_unlock(bus);
5489
5490 return ret;
5491}
5492
5493/**
5494 * pci_bus_error_reset - reset the bridge's subordinate bus
5495 * @bridge: The parent device that connects to the bus to reset
5496 *
5497 * This function will first try to reset the slots on this bus if the method is
5498 * available. If slot reset fails or is not available, this will fall back to a
5499 * secondary bus reset.
5500 */
5501int pci_bus_error_reset(struct pci_dev *bridge)
5502{
5503 struct pci_bus *bus = bridge->subordinate;
5504 struct pci_slot *slot;
5505
5506 if (!bus)
5507 return -ENOTTY;
5508
5509 mutex_lock(&pci_slot_mutex);
5510 if (list_empty(&bus->slots))
5511 goto bus_reset;
5512
5513 list_for_each_entry(slot, &bus->slots, list)
5514 if (pci_probe_reset_slot(slot))
5515 goto bus_reset;
5516
5517 list_for_each_entry(slot, &bus->slots, list)
5518 if (pci_slot_reset(slot, 0))
5519 goto bus_reset;
5520
5521 mutex_unlock(&pci_slot_mutex);
5522 return 0;
5523bus_reset:
5524 mutex_unlock(&pci_slot_mutex);
5525 return pci_bus_reset(bridge->subordinate, 0);
5526}
5527
5528/**
5529 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5530 * @bus: PCI bus to probe
5531 *
5532 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5533 */
5534int pci_probe_reset_bus(struct pci_bus *bus)
5535{
5536 return pci_bus_reset(bus, 1);
5537}
5538EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5539
5540/**
5541 * __pci_reset_bus - Try to reset a PCI bus
5542 * @bus: top level PCI bus to reset
5543 *
5544 * Same as above except return -EAGAIN if the bus cannot be locked
5545 */
5546static int __pci_reset_bus(struct pci_bus *bus)
5547{
5548 int rc;
5549
5550 rc = pci_bus_reset(bus, 1);
5551 if (rc)
5552 return rc;
5553
5554 if (pci_bus_trylock(bus)) {
5555 pci_bus_save_and_disable_locked(bus);
5556 might_sleep();
5557 rc = pci_bridge_secondary_bus_reset(bus->self);
5558 pci_bus_restore_locked(bus);
5559 pci_bus_unlock(bus);
5560 } else
5561 rc = -EAGAIN;
5562
5563 return rc;
5564}
5565
5566/**
5567 * pci_reset_bus - Try to reset a PCI bus
5568 * @pdev: top level PCI device to reset via slot/bus
5569 *
5570 * Same as above except return -EAGAIN if the bus cannot be locked
5571 */
5572int pci_reset_bus(struct pci_dev *pdev)
5573{
5574 return (!pci_probe_reset_slot(pdev->slot)) ?
5575 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5576}
5577EXPORT_SYMBOL_GPL(pci_reset_bus);
5578
5579/**
5580 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5581 * @dev: PCI device to query
5582 *
5583 * Returns mmrbc: maximum designed memory read count in bytes or
5584 * appropriate error value.
5585 */
5586int pcix_get_max_mmrbc(struct pci_dev *dev)
5587{
5588 int cap;
5589 u32 stat;
5590
5591 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5592 if (!cap)
5593 return -EINVAL;
5594
5595 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5596 return -EINVAL;
5597
5598 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5599}
5600EXPORT_SYMBOL(pcix_get_max_mmrbc);
5601
5602/**
5603 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5604 * @dev: PCI device to query
5605 *
5606 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5607 * value.
5608 */
5609int pcix_get_mmrbc(struct pci_dev *dev)
5610{
5611 int cap;
5612 u16 cmd;
5613
5614 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5615 if (!cap)
5616 return -EINVAL;
5617
5618 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5619 return -EINVAL;
5620
5621 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5622}
5623EXPORT_SYMBOL(pcix_get_mmrbc);
5624
5625/**
5626 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5627 * @dev: PCI device to query
5628 * @mmrbc: maximum memory read count in bytes
5629 * valid values are 512, 1024, 2048, 4096
5630 *
5631 * If possible sets maximum memory read byte count, some bridges have errata
5632 * that prevent this.
5633 */
5634int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5635{
5636 int cap;
5637 u32 stat, v, o;
5638 u16 cmd;
5639
5640 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5641 return -EINVAL;
5642
5643 v = ffs(mmrbc) - 10;
5644
5645 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5646 if (!cap)
5647 return -EINVAL;
5648
5649 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5650 return -EINVAL;
5651
5652 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5653 return -E2BIG;
5654
5655 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5656 return -EINVAL;
5657
5658 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5659 if (o != v) {
5660 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5661 return -EIO;
5662
5663 cmd &= ~PCI_X_CMD_MAX_READ;
5664 cmd |= v << 2;
5665 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5666 return -EIO;
5667 }
5668 return 0;
5669}
5670EXPORT_SYMBOL(pcix_set_mmrbc);
5671
5672/**
5673 * pcie_get_readrq - get PCI Express read request size
5674 * @dev: PCI device to query
5675 *
5676 * Returns maximum memory read request in bytes or appropriate error value.
5677 */
5678int pcie_get_readrq(struct pci_dev *dev)
5679{
5680 u16 ctl;
5681
5682 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5683
5684 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5685}
5686EXPORT_SYMBOL(pcie_get_readrq);
5687
5688/**
5689 * pcie_set_readrq - set PCI Express maximum memory read request
5690 * @dev: PCI device to query
5691 * @rq: maximum memory read count in bytes
5692 * valid values are 128, 256, 512, 1024, 2048, 4096
5693 *
5694 * If possible sets maximum memory read request in bytes
5695 */
5696int pcie_set_readrq(struct pci_dev *dev, int rq)
5697{
5698 u16 v;
5699 int ret;
5700
5701 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5702 return -EINVAL;
5703
5704 /*
5705 * If using the "performance" PCIe config, we clamp the read rq
5706 * size to the max packet size to keep the host bridge from
5707 * generating requests larger than we can cope with.
5708 */
5709 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5710 int mps = pcie_get_mps(dev);
5711
5712 if (mps < rq)
5713 rq = mps;
5714 }
5715
5716 v = (ffs(rq) - 8) << 12;
5717
5718 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5719 PCI_EXP_DEVCTL_READRQ, v);
5720
5721 return pcibios_err_to_errno(ret);
5722}
5723EXPORT_SYMBOL(pcie_set_readrq);
5724
5725/**
5726 * pcie_get_mps - get PCI Express maximum payload size
5727 * @dev: PCI device to query
5728 *
5729 * Returns maximum payload size in bytes
5730 */
5731int pcie_get_mps(struct pci_dev *dev)
5732{
5733 u16 ctl;
5734
5735 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5736
5737 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5738}
5739EXPORT_SYMBOL(pcie_get_mps);
5740
5741/**
5742 * pcie_set_mps - set PCI Express maximum payload size
5743 * @dev: PCI device to query
5744 * @mps: maximum payload size in bytes
5745 * valid values are 128, 256, 512, 1024, 2048, 4096
5746 *
5747 * If possible sets maximum payload size
5748 */
5749int pcie_set_mps(struct pci_dev *dev, int mps)
5750{
5751 u16 v;
5752 int ret;
5753
5754 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5755 return -EINVAL;
5756
5757 v = ffs(mps) - 8;
5758 if (v > dev->pcie_mpss)
5759 return -EINVAL;
5760 v <<= 5;
5761
5762 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5763 PCI_EXP_DEVCTL_PAYLOAD, v);
5764
5765 return pcibios_err_to_errno(ret);
5766}
5767EXPORT_SYMBOL(pcie_set_mps);
5768
5769/**
5770 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5771 * device and its bandwidth limitation
5772 * @dev: PCI device to query
5773 * @limiting_dev: storage for device causing the bandwidth limitation
5774 * @speed: storage for speed of limiting device
5775 * @width: storage for width of limiting device
5776 *
5777 * Walk up the PCI device chain and find the point where the minimum
5778 * bandwidth is available. Return the bandwidth available there and (if
5779 * limiting_dev, speed, and width pointers are supplied) information about
5780 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5781 * raw bandwidth.
5782 */
5783u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5784 enum pci_bus_speed *speed,
5785 enum pcie_link_width *width)
5786{
5787 u16 lnksta;
5788 enum pci_bus_speed next_speed;
5789 enum pcie_link_width next_width;
5790 u32 bw, next_bw;
5791
5792 if (speed)
5793 *speed = PCI_SPEED_UNKNOWN;
5794 if (width)
5795 *width = PCIE_LNK_WIDTH_UNKNOWN;
5796
5797 bw = 0;
5798
5799 while (dev) {
5800 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5801
5802 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5803 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5804 PCI_EXP_LNKSTA_NLW_SHIFT;
5805
5806 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5807
5808 /* Check if current device limits the total bandwidth */
5809 if (!bw || next_bw <= bw) {
5810 bw = next_bw;
5811
5812 if (limiting_dev)
5813 *limiting_dev = dev;
5814 if (speed)
5815 *speed = next_speed;
5816 if (width)
5817 *width = next_width;
5818 }
5819
5820 dev = pci_upstream_bridge(dev);
5821 }
5822
5823 return bw;
5824}
5825EXPORT_SYMBOL(pcie_bandwidth_available);
5826
5827/**
5828 * pcie_get_speed_cap - query for the PCI device's link speed capability
5829 * @dev: PCI device to query
5830 *
5831 * Query the PCI device speed capability. Return the maximum link speed
5832 * supported by the device.
5833 */
5834enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5835{
5836 u32 lnkcap2, lnkcap;
5837
5838 /*
5839 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
5840 * implementation note there recommends using the Supported Link
5841 * Speeds Vector in Link Capabilities 2 when supported.
5842 *
5843 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5844 * should use the Supported Link Speeds field in Link Capabilities,
5845 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5846 */
5847 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5848
5849 /* PCIe r3.0-compliant */
5850 if (lnkcap2)
5851 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
5852
5853 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5854 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
5855 return PCIE_SPEED_5_0GT;
5856 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
5857 return PCIE_SPEED_2_5GT;
5858
5859 return PCI_SPEED_UNKNOWN;
5860}
5861EXPORT_SYMBOL(pcie_get_speed_cap);
5862
5863/**
5864 * pcie_get_width_cap - query for the PCI device's link width capability
5865 * @dev: PCI device to query
5866 *
5867 * Query the PCI device width capability. Return the maximum link width
5868 * supported by the device.
5869 */
5870enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5871{
5872 u32 lnkcap;
5873
5874 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5875 if (lnkcap)
5876 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5877
5878 return PCIE_LNK_WIDTH_UNKNOWN;
5879}
5880EXPORT_SYMBOL(pcie_get_width_cap);
5881
5882/**
5883 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5884 * @dev: PCI device
5885 * @speed: storage for link speed
5886 * @width: storage for link width
5887 *
5888 * Calculate a PCI device's link bandwidth by querying for its link speed
5889 * and width, multiplying them, and applying encoding overhead. The result
5890 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5891 */
5892u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5893 enum pcie_link_width *width)
5894{
5895 *speed = pcie_get_speed_cap(dev);
5896 *width = pcie_get_width_cap(dev);
5897
5898 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5899 return 0;
5900
5901 return *width * PCIE_SPEED2MBS_ENC(*speed);
5902}
5903
5904/**
5905 * __pcie_print_link_status - Report the PCI device's link speed and width
5906 * @dev: PCI device to query
5907 * @verbose: Print info even when enough bandwidth is available
5908 *
5909 * If the available bandwidth at the device is less than the device is
5910 * capable of, report the device's maximum possible bandwidth and the
5911 * upstream link that limits its performance. If @verbose, always print
5912 * the available bandwidth, even if the device isn't constrained.
5913 */
5914void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5915{
5916 enum pcie_link_width width, width_cap;
5917 enum pci_bus_speed speed, speed_cap;
5918 struct pci_dev *limiting_dev = NULL;
5919 u32 bw_avail, bw_cap;
5920
5921 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5922 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5923
5924 if (bw_avail >= bw_cap && verbose)
5925 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5926 bw_cap / 1000, bw_cap % 1000,
5927 pci_speed_string(speed_cap), width_cap);
5928 else if (bw_avail < bw_cap)
5929 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5930 bw_avail / 1000, bw_avail % 1000,
5931 pci_speed_string(speed), width,
5932 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5933 bw_cap / 1000, bw_cap % 1000,
5934 pci_speed_string(speed_cap), width_cap);
5935}
5936
5937/**
5938 * pcie_print_link_status - Report the PCI device's link speed and width
5939 * @dev: PCI device to query
5940 *
5941 * Report the available bandwidth at the device.
5942 */
5943void pcie_print_link_status(struct pci_dev *dev)
5944{
5945 __pcie_print_link_status(dev, true);
5946}
5947EXPORT_SYMBOL(pcie_print_link_status);
5948
5949/**
5950 * pci_select_bars - Make BAR mask from the type of resource
5951 * @dev: the PCI device for which BAR mask is made
5952 * @flags: resource type mask to be selected
5953 *
5954 * This helper routine makes bar mask from the type of resource.
5955 */
5956int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5957{
5958 int i, bars = 0;
5959 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5960 if (pci_resource_flags(dev, i) & flags)
5961 bars |= (1 << i);
5962 return bars;
5963}
5964EXPORT_SYMBOL(pci_select_bars);
5965
5966/* Some architectures require additional programming to enable VGA */
5967static arch_set_vga_state_t arch_set_vga_state;
5968
5969void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5970{
5971 arch_set_vga_state = func; /* NULL disables */
5972}
5973
5974static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5975 unsigned int command_bits, u32 flags)
5976{
5977 if (arch_set_vga_state)
5978 return arch_set_vga_state(dev, decode, command_bits,
5979 flags);
5980 return 0;
5981}
5982
5983/**
5984 * pci_set_vga_state - set VGA decode state on device and parents if requested
5985 * @dev: the PCI device
5986 * @decode: true = enable decoding, false = disable decoding
5987 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5988 * @flags: traverse ancestors and change bridges
5989 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5990 */
5991int pci_set_vga_state(struct pci_dev *dev, bool decode,
5992 unsigned int command_bits, u32 flags)
5993{
5994 struct pci_bus *bus;
5995 struct pci_dev *bridge;
5996 u16 cmd;
5997 int rc;
5998
5999 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6000
6001 /* ARCH specific VGA enables */
6002 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6003 if (rc)
6004 return rc;
6005
6006 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6007 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6008 if (decode == true)
6009 cmd |= command_bits;
6010 else
6011 cmd &= ~command_bits;
6012 pci_write_config_word(dev, PCI_COMMAND, cmd);
6013 }
6014
6015 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6016 return 0;
6017
6018 bus = dev->bus;
6019 while (bus) {
6020 bridge = bus->self;
6021 if (bridge) {
6022 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6023 &cmd);
6024 if (decode == true)
6025 cmd |= PCI_BRIDGE_CTL_VGA;
6026 else
6027 cmd &= ~PCI_BRIDGE_CTL_VGA;
6028 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6029 cmd);
6030 }
6031 bus = bus->parent;
6032 }
6033 return 0;
6034}
6035
6036#ifdef CONFIG_ACPI
6037bool pci_pr3_present(struct pci_dev *pdev)
6038{
6039 struct acpi_device *adev;
6040
6041 if (acpi_disabled)
6042 return false;
6043
6044 adev = ACPI_COMPANION(&pdev->dev);
6045 if (!adev)
6046 return false;
6047
6048 return adev->power.flags.power_resources &&
6049 acpi_has_method(adev->handle, "_PR3");
6050}
6051EXPORT_SYMBOL_GPL(pci_pr3_present);
6052#endif
6053
6054/**
6055 * pci_add_dma_alias - Add a DMA devfn alias for a device
6056 * @dev: the PCI device for which alias is added
6057 * @devfn_from: alias slot and function
6058 * @nr_devfns: number of subsequent devfns to alias
6059 *
6060 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6061 * which is used to program permissible bus-devfn source addresses for DMA
6062 * requests in an IOMMU. These aliases factor into IOMMU group creation
6063 * and are useful for devices generating DMA requests beyond or different
6064 * from their logical bus-devfn. Examples include device quirks where the
6065 * device simply uses the wrong devfn, as well as non-transparent bridges
6066 * where the alias may be a proxy for devices in another domain.
6067 *
6068 * IOMMU group creation is performed during device discovery or addition,
6069 * prior to any potential DMA mapping and therefore prior to driver probing
6070 * (especially for userspace assigned devices where IOMMU group definition
6071 * cannot be left as a userspace activity). DMA aliases should therefore
6072 * be configured via quirks, such as the PCI fixup header quirk.
6073 */
6074void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6075{
6076 int devfn_to;
6077
6078 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6079 devfn_to = devfn_from + nr_devfns - 1;
6080
6081 if (!dev->dma_alias_mask)
6082 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6083 if (!dev->dma_alias_mask) {
6084 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6085 return;
6086 }
6087
6088 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6089
6090 if (nr_devfns == 1)
6091 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6092 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6093 else if (nr_devfns > 1)
6094 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6095 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6096 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6097}
6098
6099bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6100{
6101 return (dev1->dma_alias_mask &&
6102 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6103 (dev2->dma_alias_mask &&
6104 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6105 pci_real_dma_dev(dev1) == dev2 ||
6106 pci_real_dma_dev(dev2) == dev1;
6107}
6108
6109bool pci_device_is_present(struct pci_dev *pdev)
6110{
6111 u32 v;
6112
6113 if (pci_dev_is_disconnected(pdev))
6114 return false;
6115 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6116}
6117EXPORT_SYMBOL_GPL(pci_device_is_present);
6118
6119void pci_ignore_hotplug(struct pci_dev *dev)
6120{
6121 struct pci_dev *bridge = dev->bus->self;
6122
6123 dev->ignore_hotplug = 1;
6124 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6125 if (bridge)
6126 bridge->ignore_hotplug = 1;
6127}
6128EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6129
6130/**
6131 * pci_real_dma_dev - Get PCI DMA device for PCI device
6132 * @dev: the PCI device that may have a PCI DMA alias
6133 *
6134 * Permits the platform to provide architecture-specific functionality to
6135 * devices needing to alias DMA to another PCI device on another PCI bus. If
6136 * the PCI device is on the same bus, it is recommended to use
6137 * pci_add_dma_alias(). This is the default implementation. Architecture
6138 * implementations can override this.
6139 */
6140struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6141{
6142 return dev;
6143}
6144
6145resource_size_t __weak pcibios_default_alignment(void)
6146{
6147 return 0;
6148}
6149
6150/*
6151 * Arches that don't want to expose struct resource to userland as-is in
6152 * sysfs and /proc can implement their own pci_resource_to_user().
6153 */
6154void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6155 const struct resource *rsrc,
6156 resource_size_t *start, resource_size_t *end)
6157{
6158 *start = rsrc->start;
6159 *end = rsrc->end;
6160}
6161
6162static char *resource_alignment_param;
6163static DEFINE_SPINLOCK(resource_alignment_lock);
6164
6165/**
6166 * pci_specified_resource_alignment - get resource alignment specified by user.
6167 * @dev: the PCI device to get
6168 * @resize: whether or not to change resources' size when reassigning alignment
6169 *
6170 * RETURNS: Resource alignment if it is specified.
6171 * Zero if it is not specified.
6172 */
6173static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6174 bool *resize)
6175{
6176 int align_order, count;
6177 resource_size_t align = pcibios_default_alignment();
6178 const char *p;
6179 int ret;
6180
6181 spin_lock(&resource_alignment_lock);
6182 p = resource_alignment_param;
6183 if (!p || !*p)
6184 goto out;
6185 if (pci_has_flag(PCI_PROBE_ONLY)) {
6186 align = 0;
6187 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6188 goto out;
6189 }
6190
6191 while (*p) {
6192 count = 0;
6193 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6194 p[count] == '@') {
6195 p += count + 1;
6196 } else {
6197 align_order = -1;
6198 }
6199
6200 ret = pci_dev_str_match(dev, p, &p);
6201 if (ret == 1) {
6202 *resize = true;
6203 if (align_order == -1)
6204 align = PAGE_SIZE;
6205 else
6206 align = 1 << align_order;
6207 break;
6208 } else if (ret < 0) {
6209 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6210 p);
6211 break;
6212 }
6213
6214 if (*p != ';' && *p != ',') {
6215 /* End of param or invalid format */
6216 break;
6217 }
6218 p++;
6219 }
6220out:
6221 spin_unlock(&resource_alignment_lock);
6222 return align;
6223}
6224
6225static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6226 resource_size_t align, bool resize)
6227{
6228 struct resource *r = &dev->resource[bar];
6229 resource_size_t size;
6230
6231 if (!(r->flags & IORESOURCE_MEM))
6232 return;
6233
6234 if (r->flags & IORESOURCE_PCI_FIXED) {
6235 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6236 bar, r, (unsigned long long)align);
6237 return;
6238 }
6239
6240 size = resource_size(r);
6241 if (size >= align)
6242 return;
6243
6244 /*
6245 * Increase the alignment of the resource. There are two ways we
6246 * can do this:
6247 *
6248 * 1) Increase the size of the resource. BARs are aligned on their
6249 * size, so when we reallocate space for this resource, we'll
6250 * allocate it with the larger alignment. This also prevents
6251 * assignment of any other BARs inside the alignment region, so
6252 * if we're requesting page alignment, this means no other BARs
6253 * will share the page.
6254 *
6255 * The disadvantage is that this makes the resource larger than
6256 * the hardware BAR, which may break drivers that compute things
6257 * based on the resource size, e.g., to find registers at a
6258 * fixed offset before the end of the BAR.
6259 *
6260 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6261 * set r->start to the desired alignment. By itself this
6262 * doesn't prevent other BARs being put inside the alignment
6263 * region, but if we realign *every* resource of every device in
6264 * the system, none of them will share an alignment region.
6265 *
6266 * When the user has requested alignment for only some devices via
6267 * the "pci=resource_alignment" argument, "resize" is true and we
6268 * use the first method. Otherwise we assume we're aligning all
6269 * devices and we use the second.
6270 */
6271
6272 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6273 bar, r, (unsigned long long)align);
6274
6275 if (resize) {
6276 r->start = 0;
6277 r->end = align - 1;
6278 } else {
6279 r->flags &= ~IORESOURCE_SIZEALIGN;
6280 r->flags |= IORESOURCE_STARTALIGN;
6281 r->start = align;
6282 r->end = r->start + size - 1;
6283 }
6284 r->flags |= IORESOURCE_UNSET;
6285}
6286
6287/*
6288 * This function disables memory decoding and releases memory resources
6289 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6290 * It also rounds up size to specified alignment.
6291 * Later on, the kernel will assign page-aligned memory resource back
6292 * to the device.
6293 */
6294void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6295{
6296 int i;
6297 struct resource *r;
6298 resource_size_t align;
6299 u16 command;
6300 bool resize = false;
6301
6302 /*
6303 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6304 * 3.4.1.11. Their resources are allocated from the space
6305 * described by the VF BARx register in the PF's SR-IOV capability.
6306 * We can't influence their alignment here.
6307 */
6308 if (dev->is_virtfn)
6309 return;
6310
6311 /* check if specified PCI is target device to reassign */
6312 align = pci_specified_resource_alignment(dev, &resize);
6313 if (!align)
6314 return;
6315
6316 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6317 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6318 pci_warn(dev, "Can't reassign resources to host bridge\n");
6319 return;
6320 }
6321
6322 pci_read_config_word(dev, PCI_COMMAND, &command);
6323 command &= ~PCI_COMMAND_MEMORY;
6324 pci_write_config_word(dev, PCI_COMMAND, command);
6325
6326 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6327 pci_request_resource_alignment(dev, i, align, resize);
6328
6329 /*
6330 * Need to disable bridge's resource window,
6331 * to enable the kernel to reassign new resource
6332 * window later on.
6333 */
6334 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6335 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6336 r = &dev->resource[i];
6337 if (!(r->flags & IORESOURCE_MEM))
6338 continue;
6339 r->flags |= IORESOURCE_UNSET;
6340 r->end = resource_size(r) - 1;
6341 r->start = 0;
6342 }
6343 pci_disable_bridge_window(dev);
6344 }
6345}
6346
6347static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6348{
6349 size_t count = 0;
6350
6351 spin_lock(&resource_alignment_lock);
6352 if (resource_alignment_param)
6353 count = snprintf(buf, PAGE_SIZE, "%s", resource_alignment_param);
6354 spin_unlock(&resource_alignment_lock);
6355
6356 /*
6357 * When set by the command line, resource_alignment_param will not
6358 * have a trailing line feed, which is ugly. So conditionally add
6359 * it here.
6360 */
6361 if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) {
6362 buf[count - 1] = '\n';
6363 buf[count++] = 0;
6364 }
6365
6366 return count;
6367}
6368
6369static ssize_t resource_alignment_store(struct bus_type *bus,
6370 const char *buf, size_t count)
6371{
6372 char *param = kstrndup(buf, count, GFP_KERNEL);
6373
6374 if (!param)
6375 return -ENOMEM;
6376
6377 spin_lock(&resource_alignment_lock);
6378 kfree(resource_alignment_param);
6379 resource_alignment_param = param;
6380 spin_unlock(&resource_alignment_lock);
6381 return count;
6382}
6383
6384static BUS_ATTR_RW(resource_alignment);
6385
6386static int __init pci_resource_alignment_sysfs_init(void)
6387{
6388 return bus_create_file(&pci_bus_type,
6389 &bus_attr_resource_alignment);
6390}
6391late_initcall(pci_resource_alignment_sysfs_init);
6392
6393static void pci_no_domains(void)
6394{
6395#ifdef CONFIG_PCI_DOMAINS
6396 pci_domains_supported = 0;
6397#endif
6398}
6399
6400#ifdef CONFIG_PCI_DOMAINS_GENERIC
6401static atomic_t __domain_nr = ATOMIC_INIT(-1);
6402
6403static int pci_get_new_domain_nr(void)
6404{
6405 return atomic_inc_return(&__domain_nr);
6406}
6407
6408static int of_pci_bus_find_domain_nr(struct device *parent)
6409{
6410 static int use_dt_domains = -1;
6411 int domain = -1;
6412
6413 if (parent)
6414 domain = of_get_pci_domain_nr(parent->of_node);
6415
6416 /*
6417 * Check DT domain and use_dt_domains values.
6418 *
6419 * If DT domain property is valid (domain >= 0) and
6420 * use_dt_domains != 0, the DT assignment is valid since this means
6421 * we have not previously allocated a domain number by using
6422 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6423 * 1, to indicate that we have just assigned a domain number from
6424 * DT.
6425 *
6426 * If DT domain property value is not valid (ie domain < 0), and we
6427 * have not previously assigned a domain number from DT
6428 * (use_dt_domains != 1) we should assign a domain number by
6429 * using the:
6430 *
6431 * pci_get_new_domain_nr()
6432 *
6433 * API and update the use_dt_domains value to keep track of method we
6434 * are using to assign domain numbers (use_dt_domains = 0).
6435 *
6436 * All other combinations imply we have a platform that is trying
6437 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6438 * which is a recipe for domain mishandling and it is prevented by
6439 * invalidating the domain value (domain = -1) and printing a
6440 * corresponding error.
6441 */
6442 if (domain >= 0 && use_dt_domains) {
6443 use_dt_domains = 1;
6444 } else if (domain < 0 && use_dt_domains != 1) {
6445 use_dt_domains = 0;
6446 domain = pci_get_new_domain_nr();
6447 } else {
6448 if (parent)
6449 pr_err("Node %pOF has ", parent->of_node);
6450 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6451 domain = -1;
6452 }
6453
6454 return domain;
6455}
6456
6457int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6458{
6459 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6460 acpi_pci_bus_find_domain_nr(bus);
6461}
6462#endif
6463
6464/**
6465 * pci_ext_cfg_avail - can we access extended PCI config space?
6466 *
6467 * Returns 1 if we can access PCI extended config space (offsets
6468 * greater than 0xff). This is the default implementation. Architecture
6469 * implementations can override this.
6470 */
6471int __weak pci_ext_cfg_avail(void)
6472{
6473 return 1;
6474}
6475
6476void __weak pci_fixup_cardbus(struct pci_bus *bus)
6477{
6478}
6479EXPORT_SYMBOL(pci_fixup_cardbus);
6480
6481static int __init pci_setup(char *str)
6482{
6483 while (str) {
6484 char *k = strchr(str, ',');
6485 if (k)
6486 *k++ = 0;
6487 if (*str && (str = pcibios_setup(str)) && *str) {
6488 if (!strcmp(str, "nomsi")) {
6489 pci_no_msi();
6490 } else if (!strncmp(str, "noats", 5)) {
6491 pr_info("PCIe: ATS is disabled\n");
6492 pcie_ats_disabled = true;
6493 } else if (!strcmp(str, "noaer")) {
6494 pci_no_aer();
6495 } else if (!strcmp(str, "earlydump")) {
6496 pci_early_dump = true;
6497 } else if (!strncmp(str, "realloc=", 8)) {
6498 pci_realloc_get_opt(str + 8);
6499 } else if (!strncmp(str, "realloc", 7)) {
6500 pci_realloc_get_opt("on");
6501 } else if (!strcmp(str, "nodomains")) {
6502 pci_no_domains();
6503 } else if (!strncmp(str, "noari", 5)) {
6504 pcie_ari_disabled = true;
6505 } else if (!strncmp(str, "cbiosize=", 9)) {
6506 pci_cardbus_io_size = memparse(str + 9, &str);
6507 } else if (!strncmp(str, "cbmemsize=", 10)) {
6508 pci_cardbus_mem_size = memparse(str + 10, &str);
6509 } else if (!strncmp(str, "resource_alignment=", 19)) {
6510 resource_alignment_param = str + 19;
6511 } else if (!strncmp(str, "ecrc=", 5)) {
6512 pcie_ecrc_get_policy(str + 5);
6513 } else if (!strncmp(str, "hpiosize=", 9)) {
6514 pci_hotplug_io_size = memparse(str + 9, &str);
6515 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6516 pci_hotplug_mmio_size = memparse(str + 11, &str);
6517 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6518 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6519 } else if (!strncmp(str, "hpmemsize=", 10)) {
6520 pci_hotplug_mmio_size = memparse(str + 10, &str);
6521 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6522 } else if (!strncmp(str, "hpbussize=", 10)) {
6523 pci_hotplug_bus_size =
6524 simple_strtoul(str + 10, &str, 0);
6525 if (pci_hotplug_bus_size > 0xff)
6526 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6527 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6528 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6529 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6530 pcie_bus_config = PCIE_BUS_SAFE;
6531 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6532 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6533 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6534 pcie_bus_config = PCIE_BUS_PEER2PEER;
6535 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6536 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6537 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6538 disable_acs_redir_param = str + 18;
6539 } else {
6540 pr_err("PCI: Unknown option `%s'\n", str);
6541 }
6542 }
6543 str = k;
6544 }
6545 return 0;
6546}
6547early_param("pci", pci_setup);
6548
6549/*
6550 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6551 * in pci_setup(), above, to point to data in the __initdata section which
6552 * will be freed after the init sequence is complete. We can't allocate memory
6553 * in pci_setup() because some architectures do not have any memory allocation
6554 * service available during an early_param() call. So we allocate memory and
6555 * copy the variable here before the init section is freed.
6556 *
6557 */
6558static int __init pci_realloc_setup_params(void)
6559{
6560 resource_alignment_param = kstrdup(resource_alignment_param,
6561 GFP_KERNEL);
6562 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6563
6564 return 0;
6565}
6566pure_initcall(pci_realloc_setup_params);
1/*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15#include <linux/slab.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19#include <linux/log2.h>
20#include <linux/pci-aspm.h>
21#include <linux/pm_wakeup.h>
22#include <linux/interrupt.h>
23#include <linux/device.h>
24#include <linux/pm_runtime.h>
25#include <asm/setup.h>
26#include "pci.h"
27
28const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30};
31EXPORT_SYMBOL_GPL(pci_power_names);
32
33int isa_dma_bridge_buggy;
34EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36int pci_pci_problems;
37EXPORT_SYMBOL(pci_pci_problems);
38
39unsigned int pci_pm_d3_delay;
40
41static void pci_pme_list_scan(struct work_struct *work);
42
43static LIST_HEAD(pci_pme_list);
44static DEFINE_MUTEX(pci_pme_list_mutex);
45static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
46
47struct pci_pme_device {
48 struct list_head list;
49 struct pci_dev *dev;
50};
51
52#define PME_TIMEOUT 1000 /* How long between PME checks */
53
54static void pci_dev_d3_sleep(struct pci_dev *dev)
55{
56 unsigned int delay = dev->d3_delay;
57
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
60
61 msleep(delay);
62}
63
64#ifdef CONFIG_PCI_DOMAINS
65int pci_domains_supported = 1;
66#endif
67
68#define DEFAULT_CARDBUS_IO_SIZE (256)
69#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70/* pci=cbmemsize=nnM,cbiosize=nn can override this */
71unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
73
74#define DEFAULT_HOTPLUG_IO_SIZE (256)
75#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76/* pci=hpmemsize=nnM,hpiosize=nn can override this */
77unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
79
80enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
81
82/*
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
87 */
88u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
89u8 pci_cache_line_size;
90
91/**
92 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
93 * @bus: pointer to PCI bus structure to search
94 *
95 * Given a PCI bus, returns the highest PCI bus number present in the set
96 * including the given PCI bus and its list of child PCI buses.
97 */
98unsigned char pci_bus_max_busnr(struct pci_bus* bus)
99{
100 struct list_head *tmp;
101 unsigned char max, n;
102
103 max = bus->subordinate;
104 list_for_each(tmp, &bus->children) {
105 n = pci_bus_max_busnr(pci_bus_b(tmp));
106 if(n > max)
107 max = n;
108 }
109 return max;
110}
111EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
112
113#ifdef CONFIG_HAS_IOMEM
114void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
115{
116 /*
117 * Make sure the BAR is actually a memory resource, not an IO resource
118 */
119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
120 WARN_ON(1);
121 return NULL;
122 }
123 return ioremap_nocache(pci_resource_start(pdev, bar),
124 pci_resource_len(pdev, bar));
125}
126EXPORT_SYMBOL_GPL(pci_ioremap_bar);
127#endif
128
129#if 0
130/**
131 * pci_max_busnr - returns maximum PCI bus number
132 *
133 * Returns the highest PCI bus number present in the system global list of
134 * PCI buses.
135 */
136unsigned char __devinit
137pci_max_busnr(void)
138{
139 struct pci_bus *bus = NULL;
140 unsigned char max, n;
141
142 max = 0;
143 while ((bus = pci_find_next_bus(bus)) != NULL) {
144 n = pci_bus_max_busnr(bus);
145 if(n > max)
146 max = n;
147 }
148 return max;
149}
150
151#endif /* 0 */
152
153#define PCI_FIND_CAP_TTL 48
154
155static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
156 u8 pos, int cap, int *ttl)
157{
158 u8 id;
159
160 while ((*ttl)--) {
161 pci_bus_read_config_byte(bus, devfn, pos, &pos);
162 if (pos < 0x40)
163 break;
164 pos &= ~3;
165 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
166 &id);
167 if (id == 0xff)
168 break;
169 if (id == cap)
170 return pos;
171 pos += PCI_CAP_LIST_NEXT;
172 }
173 return 0;
174}
175
176static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
177 u8 pos, int cap)
178{
179 int ttl = PCI_FIND_CAP_TTL;
180
181 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
182}
183
184int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
185{
186 return __pci_find_next_cap(dev->bus, dev->devfn,
187 pos + PCI_CAP_LIST_NEXT, cap);
188}
189EXPORT_SYMBOL_GPL(pci_find_next_capability);
190
191static int __pci_bus_find_cap_start(struct pci_bus *bus,
192 unsigned int devfn, u8 hdr_type)
193{
194 u16 status;
195
196 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
197 if (!(status & PCI_STATUS_CAP_LIST))
198 return 0;
199
200 switch (hdr_type) {
201 case PCI_HEADER_TYPE_NORMAL:
202 case PCI_HEADER_TYPE_BRIDGE:
203 return PCI_CAPABILITY_LIST;
204 case PCI_HEADER_TYPE_CARDBUS:
205 return PCI_CB_CAPABILITY_LIST;
206 default:
207 return 0;
208 }
209
210 return 0;
211}
212
213/**
214 * pci_find_capability - query for devices' capabilities
215 * @dev: PCI device to query
216 * @cap: capability code
217 *
218 * Tell if a device supports a given PCI capability.
219 * Returns the address of the requested capability structure within the
220 * device's PCI configuration space or 0 in case the device does not
221 * support it. Possible values for @cap:
222 *
223 * %PCI_CAP_ID_PM Power Management
224 * %PCI_CAP_ID_AGP Accelerated Graphics Port
225 * %PCI_CAP_ID_VPD Vital Product Data
226 * %PCI_CAP_ID_SLOTID Slot Identification
227 * %PCI_CAP_ID_MSI Message Signalled Interrupts
228 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
229 * %PCI_CAP_ID_PCIX PCI-X
230 * %PCI_CAP_ID_EXP PCI Express
231 */
232int pci_find_capability(struct pci_dev *dev, int cap)
233{
234 int pos;
235
236 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
237 if (pos)
238 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
239
240 return pos;
241}
242
243/**
244 * pci_bus_find_capability - query for devices' capabilities
245 * @bus: the PCI bus to query
246 * @devfn: PCI device to query
247 * @cap: capability code
248 *
249 * Like pci_find_capability() but works for pci devices that do not have a
250 * pci_dev structure set up yet.
251 *
252 * Returns the address of the requested capability structure within the
253 * device's PCI configuration space or 0 in case the device does not
254 * support it.
255 */
256int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
257{
258 int pos;
259 u8 hdr_type;
260
261 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
262
263 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
264 if (pos)
265 pos = __pci_find_next_cap(bus, devfn, pos, cap);
266
267 return pos;
268}
269
270/**
271 * pci_find_ext_capability - Find an extended capability
272 * @dev: PCI device to query
273 * @cap: capability code
274 *
275 * Returns the address of the requested extended capability structure
276 * within the device's PCI configuration space or 0 if the device does
277 * not support it. Possible values for @cap:
278 *
279 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
280 * %PCI_EXT_CAP_ID_VC Virtual Channel
281 * %PCI_EXT_CAP_ID_DSN Device Serial Number
282 * %PCI_EXT_CAP_ID_PWR Power Budgeting
283 */
284int pci_find_ext_capability(struct pci_dev *dev, int cap)
285{
286 u32 header;
287 int ttl;
288 int pos = PCI_CFG_SPACE_SIZE;
289
290 /* minimum 8 bytes per capability */
291 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
292
293 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
294 return 0;
295
296 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
297 return 0;
298
299 /*
300 * If we have no capabilities, this is indicated by cap ID,
301 * cap version and next pointer all being 0.
302 */
303 if (header == 0)
304 return 0;
305
306 while (ttl-- > 0) {
307 if (PCI_EXT_CAP_ID(header) == cap)
308 return pos;
309
310 pos = PCI_EXT_CAP_NEXT(header);
311 if (pos < PCI_CFG_SPACE_SIZE)
312 break;
313
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
315 break;
316 }
317
318 return 0;
319}
320EXPORT_SYMBOL_GPL(pci_find_ext_capability);
321
322/**
323 * pci_bus_find_ext_capability - find an extended capability
324 * @bus: the PCI bus to query
325 * @devfn: PCI device to query
326 * @cap: capability code
327 *
328 * Like pci_find_ext_capability() but works for pci devices that do not have a
329 * pci_dev structure set up yet.
330 *
331 * Returns the address of the requested capability structure within the
332 * device's PCI configuration space or 0 in case the device does not
333 * support it.
334 */
335int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
336 int cap)
337{
338 u32 header;
339 int ttl;
340 int pos = PCI_CFG_SPACE_SIZE;
341
342 /* minimum 8 bytes per capability */
343 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
344
345 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
346 return 0;
347 if (header == 0xffffffff || header == 0)
348 return 0;
349
350 while (ttl-- > 0) {
351 if (PCI_EXT_CAP_ID(header) == cap)
352 return pos;
353
354 pos = PCI_EXT_CAP_NEXT(header);
355 if (pos < PCI_CFG_SPACE_SIZE)
356 break;
357
358 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
359 break;
360 }
361
362 return 0;
363}
364
365static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
366{
367 int rc, ttl = PCI_FIND_CAP_TTL;
368 u8 cap, mask;
369
370 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
371 mask = HT_3BIT_CAP_MASK;
372 else
373 mask = HT_5BIT_CAP_MASK;
374
375 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
376 PCI_CAP_ID_HT, &ttl);
377 while (pos) {
378 rc = pci_read_config_byte(dev, pos + 3, &cap);
379 if (rc != PCIBIOS_SUCCESSFUL)
380 return 0;
381
382 if ((cap & mask) == ht_cap)
383 return pos;
384
385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
386 pos + PCI_CAP_LIST_NEXT,
387 PCI_CAP_ID_HT, &ttl);
388 }
389
390 return 0;
391}
392/**
393 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
394 * @dev: PCI device to query
395 * @pos: Position from which to continue searching
396 * @ht_cap: Hypertransport capability code
397 *
398 * To be used in conjunction with pci_find_ht_capability() to search for
399 * all capabilities matching @ht_cap. @pos should always be a value returned
400 * from pci_find_ht_capability().
401 *
402 * NB. To be 100% safe against broken PCI devices, the caller should take
403 * steps to avoid an infinite loop.
404 */
405int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
406{
407 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
408}
409EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
410
411/**
412 * pci_find_ht_capability - query a device's Hypertransport capabilities
413 * @dev: PCI device to query
414 * @ht_cap: Hypertransport capability code
415 *
416 * Tell if a device supports a given Hypertransport capability.
417 * Returns an address within the device's PCI configuration space
418 * or 0 in case the device does not support the request capability.
419 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
420 * which has a Hypertransport capability matching @ht_cap.
421 */
422int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
423{
424 int pos;
425
426 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
427 if (pos)
428 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
429
430 return pos;
431}
432EXPORT_SYMBOL_GPL(pci_find_ht_capability);
433
434/**
435 * pci_find_parent_resource - return resource region of parent bus of given region
436 * @dev: PCI device structure contains resources to be searched
437 * @res: child resource record for which parent is sought
438 *
439 * For given resource region of given device, return the resource
440 * region of parent bus the given region is contained in or where
441 * it should be allocated from.
442 */
443struct resource *
444pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
445{
446 const struct pci_bus *bus = dev->bus;
447 int i;
448 struct resource *best = NULL, *r;
449
450 pci_bus_for_each_resource(bus, r, i) {
451 if (!r)
452 continue;
453 if (res->start && !(res->start >= r->start && res->end <= r->end))
454 continue; /* Not contained */
455 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
456 continue; /* Wrong type */
457 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
458 return r; /* Exact match */
459 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
460 if (r->flags & IORESOURCE_PREFETCH)
461 continue;
462 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
463 if (!best)
464 best = r;
465 }
466 return best;
467}
468
469/**
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
472 *
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
475 */
476static void
477pci_restore_bars(struct pci_dev *dev)
478{
479 int i;
480
481 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
482 pci_update_resource(dev, i);
483}
484
485static struct pci_platform_pm_ops *pci_platform_pm;
486
487int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
488{
489 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
490 || !ops->sleep_wake || !ops->can_wakeup)
491 return -EINVAL;
492 pci_platform_pm = ops;
493 return 0;
494}
495
496static inline bool platform_pci_power_manageable(struct pci_dev *dev)
497{
498 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
499}
500
501static inline int platform_pci_set_power_state(struct pci_dev *dev,
502 pci_power_t t)
503{
504 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
505}
506
507static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
508{
509 return pci_platform_pm ?
510 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
511}
512
513static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
514{
515 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
516}
517
518static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
519{
520 return pci_platform_pm ?
521 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
522}
523
524static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
525{
526 return pci_platform_pm ?
527 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
528}
529
530/**
531 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
532 * given PCI device
533 * @dev: PCI device to handle.
534 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
535 *
536 * RETURN VALUE:
537 * -EINVAL if the requested state is invalid.
538 * -EIO if device does not support PCI PM or its PM capabilities register has a
539 * wrong version, or device doesn't support the requested state.
540 * 0 if device already is in the requested state.
541 * 0 if device's power state has been successfully changed.
542 */
543static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
544{
545 u16 pmcsr;
546 bool need_restore = false;
547
548 /* Check if we're already there */
549 if (dev->current_state == state)
550 return 0;
551
552 if (!dev->pm_cap)
553 return -EIO;
554
555 if (state < PCI_D0 || state > PCI_D3hot)
556 return -EINVAL;
557
558 /* Validate current state:
559 * Can enter D0 from any state, but if we can only go deeper
560 * to sleep if we're already in a low power state
561 */
562 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
563 && dev->current_state > state) {
564 dev_err(&dev->dev, "invalid power transition "
565 "(from state %d to %d)\n", dev->current_state, state);
566 return -EINVAL;
567 }
568
569 /* check if this device supports the desired state */
570 if ((state == PCI_D1 && !dev->d1_support)
571 || (state == PCI_D2 && !dev->d2_support))
572 return -EIO;
573
574 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
575
576 /* If we're (effectively) in D3, force entire word to 0.
577 * This doesn't affect PME_Status, disables PME_En, and
578 * sets PowerState to 0.
579 */
580 switch (dev->current_state) {
581 case PCI_D0:
582 case PCI_D1:
583 case PCI_D2:
584 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
585 pmcsr |= state;
586 break;
587 case PCI_D3hot:
588 case PCI_D3cold:
589 case PCI_UNKNOWN: /* Boot-up */
590 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
591 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
592 need_restore = true;
593 /* Fall-through: force to D0 */
594 default:
595 pmcsr = 0;
596 break;
597 }
598
599 /* enter specified state */
600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
601
602 /* Mandatory power management transition delays */
603 /* see PCI PM 1.1 5.6.1 table 18 */
604 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
605 pci_dev_d3_sleep(dev);
606 else if (state == PCI_D2 || dev->current_state == PCI_D2)
607 udelay(PCI_PM_D2_DELAY);
608
609 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
610 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
611 if (dev->current_state != state && printk_ratelimit())
612 dev_info(&dev->dev, "Refused to change power state, "
613 "currently in D%d\n", dev->current_state);
614
615 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
616 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
617 * from D3hot to D0 _may_ perform an internal reset, thereby
618 * going to "D0 Uninitialized" rather than "D0 Initialized".
619 * For example, at least some versions of the 3c905B and the
620 * 3c556B exhibit this behaviour.
621 *
622 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
623 * devices in a D3hot state at boot. Consequently, we need to
624 * restore at least the BARs so that the device will be
625 * accessible to its driver.
626 */
627 if (need_restore)
628 pci_restore_bars(dev);
629
630 if (dev->bus->self)
631 pcie_aspm_pm_state_change(dev->bus->self);
632
633 return 0;
634}
635
636/**
637 * pci_update_current_state - Read PCI power state of given device from its
638 * PCI PM registers and cache it
639 * @dev: PCI device to handle.
640 * @state: State to cache in case the device doesn't have the PM capability
641 */
642void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
643{
644 if (dev->pm_cap) {
645 u16 pmcsr;
646
647 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
648 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
649 } else {
650 dev->current_state = state;
651 }
652}
653
654/**
655 * pci_platform_power_transition - Use platform to change device power state
656 * @dev: PCI device to handle.
657 * @state: State to put the device into.
658 */
659static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
660{
661 int error;
662
663 if (platform_pci_power_manageable(dev)) {
664 error = platform_pci_set_power_state(dev, state);
665 if (!error)
666 pci_update_current_state(dev, state);
667 } else {
668 error = -ENODEV;
669 /* Fall back to PCI_D0 if native PM is not supported */
670 if (!dev->pm_cap)
671 dev->current_state = PCI_D0;
672 }
673
674 return error;
675}
676
677/**
678 * __pci_start_power_transition - Start power transition of a PCI device
679 * @dev: PCI device to handle.
680 * @state: State to put the device into.
681 */
682static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
683{
684 if (state == PCI_D0)
685 pci_platform_power_transition(dev, PCI_D0);
686}
687
688/**
689 * __pci_complete_power_transition - Complete power transition of a PCI device
690 * @dev: PCI device to handle.
691 * @state: State to put the device into.
692 *
693 * This function should not be called directly by device drivers.
694 */
695int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
696{
697 return state >= PCI_D0 ?
698 pci_platform_power_transition(dev, state) : -EINVAL;
699}
700EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
701
702/**
703 * pci_set_power_state - Set the power state of a PCI device
704 * @dev: PCI device to handle.
705 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
706 *
707 * Transition a device to a new power state, using the platform firmware and/or
708 * the device's PCI PM registers.
709 *
710 * RETURN VALUE:
711 * -EINVAL if the requested state is invalid.
712 * -EIO if device does not support PCI PM or its PM capabilities register has a
713 * wrong version, or device doesn't support the requested state.
714 * 0 if device already is in the requested state.
715 * 0 if device's power state has been successfully changed.
716 */
717int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
718{
719 int error;
720
721 /* bound the state we're entering */
722 if (state > PCI_D3hot)
723 state = PCI_D3hot;
724 else if (state < PCI_D0)
725 state = PCI_D0;
726 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
727 /*
728 * If the device or the parent bridge do not support PCI PM,
729 * ignore the request if we're doing anything other than putting
730 * it into D0 (which would only happen on boot).
731 */
732 return 0;
733
734 __pci_start_power_transition(dev, state);
735
736 /* This device is quirked not to be put into D3, so
737 don't put it in D3 */
738 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
739 return 0;
740
741 error = pci_raw_set_power_state(dev, state);
742
743 if (!__pci_complete_power_transition(dev, state))
744 error = 0;
745 /*
746 * When aspm_policy is "powersave" this call ensures
747 * that ASPM is configured.
748 */
749 if (!error && dev->bus->self)
750 pcie_aspm_powersave_config_link(dev->bus->self);
751
752 return error;
753}
754
755/**
756 * pci_choose_state - Choose the power state of a PCI device
757 * @dev: PCI device to be suspended
758 * @state: target sleep state for the whole system. This is the value
759 * that is passed to suspend() function.
760 *
761 * Returns PCI power state suitable for given device and given system
762 * message.
763 */
764
765pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
766{
767 pci_power_t ret;
768
769 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
770 return PCI_D0;
771
772 ret = platform_pci_choose_state(dev);
773 if (ret != PCI_POWER_ERROR)
774 return ret;
775
776 switch (state.event) {
777 case PM_EVENT_ON:
778 return PCI_D0;
779 case PM_EVENT_FREEZE:
780 case PM_EVENT_PRETHAW:
781 /* REVISIT both freeze and pre-thaw "should" use D0 */
782 case PM_EVENT_SUSPEND:
783 case PM_EVENT_HIBERNATE:
784 return PCI_D3hot;
785 default:
786 dev_info(&dev->dev, "unrecognized suspend event %d\n",
787 state.event);
788 BUG();
789 }
790 return PCI_D0;
791}
792
793EXPORT_SYMBOL(pci_choose_state);
794
795#define PCI_EXP_SAVE_REGS 7
796
797#define pcie_cap_has_devctl(type, flags) 1
798#define pcie_cap_has_lnkctl(type, flags) \
799 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
800 (type == PCI_EXP_TYPE_ROOT_PORT || \
801 type == PCI_EXP_TYPE_ENDPOINT || \
802 type == PCI_EXP_TYPE_LEG_END))
803#define pcie_cap_has_sltctl(type, flags) \
804 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
805 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
806 (type == PCI_EXP_TYPE_DOWNSTREAM && \
807 (flags & PCI_EXP_FLAGS_SLOT))))
808#define pcie_cap_has_rtctl(type, flags) \
809 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
810 (type == PCI_EXP_TYPE_ROOT_PORT || \
811 type == PCI_EXP_TYPE_RC_EC))
812#define pcie_cap_has_devctl2(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1)
814#define pcie_cap_has_lnkctl2(type, flags) \
815 ((flags & PCI_EXP_FLAGS_VERS) > 1)
816#define pcie_cap_has_sltctl2(type, flags) \
817 ((flags & PCI_EXP_FLAGS_VERS) > 1)
818
819static int pci_save_pcie_state(struct pci_dev *dev)
820{
821 int pos, i = 0;
822 struct pci_cap_saved_state *save_state;
823 u16 *cap;
824 u16 flags;
825
826 pos = pci_pcie_cap(dev);
827 if (!pos)
828 return 0;
829
830 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
831 if (!save_state) {
832 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
833 return -ENOMEM;
834 }
835 cap = (u16 *)&save_state->cap.data[0];
836
837 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
838
839 if (pcie_cap_has_devctl(dev->pcie_type, flags))
840 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
841 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
842 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
843 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
844 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
845 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
846 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
847 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
848 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
849 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
850 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
851 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
852 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
853
854 return 0;
855}
856
857static void pci_restore_pcie_state(struct pci_dev *dev)
858{
859 int i = 0, pos;
860 struct pci_cap_saved_state *save_state;
861 u16 *cap;
862 u16 flags;
863
864 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
865 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
866 if (!save_state || pos <= 0)
867 return;
868 cap = (u16 *)&save_state->cap.data[0];
869
870 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
871
872 if (pcie_cap_has_devctl(dev->pcie_type, flags))
873 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
874 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
875 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
876 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
877 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
878 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
879 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
880 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
881 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
882 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
883 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
884 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
885 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
886}
887
888
889static int pci_save_pcix_state(struct pci_dev *dev)
890{
891 int pos;
892 struct pci_cap_saved_state *save_state;
893
894 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
895 if (pos <= 0)
896 return 0;
897
898 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
899 if (!save_state) {
900 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
901 return -ENOMEM;
902 }
903
904 pci_read_config_word(dev, pos + PCI_X_CMD,
905 (u16 *)save_state->cap.data);
906
907 return 0;
908}
909
910static void pci_restore_pcix_state(struct pci_dev *dev)
911{
912 int i = 0, pos;
913 struct pci_cap_saved_state *save_state;
914 u16 *cap;
915
916 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
917 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
918 if (!save_state || pos <= 0)
919 return;
920 cap = (u16 *)&save_state->cap.data[0];
921
922 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
923}
924
925
926/**
927 * pci_save_state - save the PCI configuration space of a device before suspending
928 * @dev: - PCI device that we're dealing with
929 */
930int
931pci_save_state(struct pci_dev *dev)
932{
933 int i;
934 /* XXX: 100% dword access ok here? */
935 for (i = 0; i < 16; i++)
936 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
937 dev->state_saved = true;
938 if ((i = pci_save_pcie_state(dev)) != 0)
939 return i;
940 if ((i = pci_save_pcix_state(dev)) != 0)
941 return i;
942 return 0;
943}
944
945/**
946 * pci_restore_state - Restore the saved state of a PCI device
947 * @dev: - PCI device that we're dealing with
948 */
949void pci_restore_state(struct pci_dev *dev)
950{
951 int i;
952 u32 val;
953
954 if (!dev->state_saved)
955 return;
956
957 /* PCI Express register must be restored first */
958 pci_restore_pcie_state(dev);
959
960 /*
961 * The Base Address register should be programmed before the command
962 * register(s)
963 */
964 for (i = 15; i >= 0; i--) {
965 pci_read_config_dword(dev, i * 4, &val);
966 if (val != dev->saved_config_space[i]) {
967 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
968 "space at offset %#x (was %#x, writing %#x)\n",
969 i, val, (int)dev->saved_config_space[i]);
970 pci_write_config_dword(dev,i * 4,
971 dev->saved_config_space[i]);
972 }
973 }
974 pci_restore_pcix_state(dev);
975 pci_restore_msi_state(dev);
976 pci_restore_iov_state(dev);
977
978 dev->state_saved = false;
979}
980
981struct pci_saved_state {
982 u32 config_space[16];
983 struct pci_cap_saved_data cap[0];
984};
985
986/**
987 * pci_store_saved_state - Allocate and return an opaque struct containing
988 * the device saved state.
989 * @dev: PCI device that we're dealing with
990 *
991 * Rerturn NULL if no state or error.
992 */
993struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
994{
995 struct pci_saved_state *state;
996 struct pci_cap_saved_state *tmp;
997 struct pci_cap_saved_data *cap;
998 struct hlist_node *pos;
999 size_t size;
1000
1001 if (!dev->state_saved)
1002 return NULL;
1003
1004 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1005
1006 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1007 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1008
1009 state = kzalloc(size, GFP_KERNEL);
1010 if (!state)
1011 return NULL;
1012
1013 memcpy(state->config_space, dev->saved_config_space,
1014 sizeof(state->config_space));
1015
1016 cap = state->cap;
1017 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1018 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1019 memcpy(cap, &tmp->cap, len);
1020 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1021 }
1022 /* Empty cap_save terminates list */
1023
1024 return state;
1025}
1026EXPORT_SYMBOL_GPL(pci_store_saved_state);
1027
1028/**
1029 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1030 * @dev: PCI device that we're dealing with
1031 * @state: Saved state returned from pci_store_saved_state()
1032 */
1033int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1034{
1035 struct pci_cap_saved_data *cap;
1036
1037 dev->state_saved = false;
1038
1039 if (!state)
1040 return 0;
1041
1042 memcpy(dev->saved_config_space, state->config_space,
1043 sizeof(state->config_space));
1044
1045 cap = state->cap;
1046 while (cap->size) {
1047 struct pci_cap_saved_state *tmp;
1048
1049 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1050 if (!tmp || tmp->cap.size != cap->size)
1051 return -EINVAL;
1052
1053 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1054 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1055 sizeof(struct pci_cap_saved_data) + cap->size);
1056 }
1057
1058 dev->state_saved = true;
1059 return 0;
1060}
1061EXPORT_SYMBOL_GPL(pci_load_saved_state);
1062
1063/**
1064 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1065 * and free the memory allocated for it.
1066 * @dev: PCI device that we're dealing with
1067 * @state: Pointer to saved state returned from pci_store_saved_state()
1068 */
1069int pci_load_and_free_saved_state(struct pci_dev *dev,
1070 struct pci_saved_state **state)
1071{
1072 int ret = pci_load_saved_state(dev, *state);
1073 kfree(*state);
1074 *state = NULL;
1075 return ret;
1076}
1077EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1078
1079static int do_pci_enable_device(struct pci_dev *dev, int bars)
1080{
1081 int err;
1082
1083 err = pci_set_power_state(dev, PCI_D0);
1084 if (err < 0 && err != -EIO)
1085 return err;
1086 err = pcibios_enable_device(dev, bars);
1087 if (err < 0)
1088 return err;
1089 pci_fixup_device(pci_fixup_enable, dev);
1090
1091 return 0;
1092}
1093
1094/**
1095 * pci_reenable_device - Resume abandoned device
1096 * @dev: PCI device to be resumed
1097 *
1098 * Note this function is a backend of pci_default_resume and is not supposed
1099 * to be called by normal code, write proper resume handler and use it instead.
1100 */
1101int pci_reenable_device(struct pci_dev *dev)
1102{
1103 if (pci_is_enabled(dev))
1104 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1105 return 0;
1106}
1107
1108static int __pci_enable_device_flags(struct pci_dev *dev,
1109 resource_size_t flags)
1110{
1111 int err;
1112 int i, bars = 0;
1113
1114 /*
1115 * Power state could be unknown at this point, either due to a fresh
1116 * boot or a device removal call. So get the current power state
1117 * so that things like MSI message writing will behave as expected
1118 * (e.g. if the device really is in D0 at enable time).
1119 */
1120 if (dev->pm_cap) {
1121 u16 pmcsr;
1122 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1123 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1124 }
1125
1126 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1127 return 0; /* already enabled */
1128
1129 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1130 if (dev->resource[i].flags & flags)
1131 bars |= (1 << i);
1132
1133 err = do_pci_enable_device(dev, bars);
1134 if (err < 0)
1135 atomic_dec(&dev->enable_cnt);
1136 return err;
1137}
1138
1139/**
1140 * pci_enable_device_io - Initialize a device for use with IO space
1141 * @dev: PCI device to be initialized
1142 *
1143 * Initialize device before it's used by a driver. Ask low-level code
1144 * to enable I/O resources. Wake up the device if it was suspended.
1145 * Beware, this function can fail.
1146 */
1147int pci_enable_device_io(struct pci_dev *dev)
1148{
1149 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1150}
1151
1152/**
1153 * pci_enable_device_mem - Initialize a device for use with Memory space
1154 * @dev: PCI device to be initialized
1155 *
1156 * Initialize device before it's used by a driver. Ask low-level code
1157 * to enable Memory resources. Wake up the device if it was suspended.
1158 * Beware, this function can fail.
1159 */
1160int pci_enable_device_mem(struct pci_dev *dev)
1161{
1162 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1163}
1164
1165/**
1166 * pci_enable_device - Initialize device before it's used by a driver.
1167 * @dev: PCI device to be initialized
1168 *
1169 * Initialize device before it's used by a driver. Ask low-level code
1170 * to enable I/O and memory. Wake up the device if it was suspended.
1171 * Beware, this function can fail.
1172 *
1173 * Note we don't actually enable the device many times if we call
1174 * this function repeatedly (we just increment the count).
1175 */
1176int pci_enable_device(struct pci_dev *dev)
1177{
1178 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1179}
1180
1181/*
1182 * Managed PCI resources. This manages device on/off, intx/msi/msix
1183 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1184 * there's no need to track it separately. pci_devres is initialized
1185 * when a device is enabled using managed PCI device enable interface.
1186 */
1187struct pci_devres {
1188 unsigned int enabled:1;
1189 unsigned int pinned:1;
1190 unsigned int orig_intx:1;
1191 unsigned int restore_intx:1;
1192 u32 region_mask;
1193};
1194
1195static void pcim_release(struct device *gendev, void *res)
1196{
1197 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1198 struct pci_devres *this = res;
1199 int i;
1200
1201 if (dev->msi_enabled)
1202 pci_disable_msi(dev);
1203 if (dev->msix_enabled)
1204 pci_disable_msix(dev);
1205
1206 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1207 if (this->region_mask & (1 << i))
1208 pci_release_region(dev, i);
1209
1210 if (this->restore_intx)
1211 pci_intx(dev, this->orig_intx);
1212
1213 if (this->enabled && !this->pinned)
1214 pci_disable_device(dev);
1215}
1216
1217static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1218{
1219 struct pci_devres *dr, *new_dr;
1220
1221 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1222 if (dr)
1223 return dr;
1224
1225 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1226 if (!new_dr)
1227 return NULL;
1228 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1229}
1230
1231static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1232{
1233 if (pci_is_managed(pdev))
1234 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1235 return NULL;
1236}
1237
1238/**
1239 * pcim_enable_device - Managed pci_enable_device()
1240 * @pdev: PCI device to be initialized
1241 *
1242 * Managed pci_enable_device().
1243 */
1244int pcim_enable_device(struct pci_dev *pdev)
1245{
1246 struct pci_devres *dr;
1247 int rc;
1248
1249 dr = get_pci_dr(pdev);
1250 if (unlikely(!dr))
1251 return -ENOMEM;
1252 if (dr->enabled)
1253 return 0;
1254
1255 rc = pci_enable_device(pdev);
1256 if (!rc) {
1257 pdev->is_managed = 1;
1258 dr->enabled = 1;
1259 }
1260 return rc;
1261}
1262
1263/**
1264 * pcim_pin_device - Pin managed PCI device
1265 * @pdev: PCI device to pin
1266 *
1267 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1268 * driver detach. @pdev must have been enabled with
1269 * pcim_enable_device().
1270 */
1271void pcim_pin_device(struct pci_dev *pdev)
1272{
1273 struct pci_devres *dr;
1274
1275 dr = find_pci_dr(pdev);
1276 WARN_ON(!dr || !dr->enabled);
1277 if (dr)
1278 dr->pinned = 1;
1279}
1280
1281/**
1282 * pcibios_disable_device - disable arch specific PCI resources for device dev
1283 * @dev: the PCI device to disable
1284 *
1285 * Disables architecture specific PCI resources for the device. This
1286 * is the default implementation. Architecture implementations can
1287 * override this.
1288 */
1289void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1290
1291static void do_pci_disable_device(struct pci_dev *dev)
1292{
1293 u16 pci_command;
1294
1295 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1296 if (pci_command & PCI_COMMAND_MASTER) {
1297 pci_command &= ~PCI_COMMAND_MASTER;
1298 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1299 }
1300
1301 pcibios_disable_device(dev);
1302}
1303
1304/**
1305 * pci_disable_enabled_device - Disable device without updating enable_cnt
1306 * @dev: PCI device to disable
1307 *
1308 * NOTE: This function is a backend of PCI power management routines and is
1309 * not supposed to be called drivers.
1310 */
1311void pci_disable_enabled_device(struct pci_dev *dev)
1312{
1313 if (pci_is_enabled(dev))
1314 do_pci_disable_device(dev);
1315}
1316
1317/**
1318 * pci_disable_device - Disable PCI device after use
1319 * @dev: PCI device to be disabled
1320 *
1321 * Signal to the system that the PCI device is not in use by the system
1322 * anymore. This only involves disabling PCI bus-mastering, if active.
1323 *
1324 * Note we don't actually disable the device until all callers of
1325 * pci_enable_device() have called pci_disable_device().
1326 */
1327void
1328pci_disable_device(struct pci_dev *dev)
1329{
1330 struct pci_devres *dr;
1331
1332 dr = find_pci_dr(dev);
1333 if (dr)
1334 dr->enabled = 0;
1335
1336 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1337 return;
1338
1339 do_pci_disable_device(dev);
1340
1341 dev->is_busmaster = 0;
1342}
1343
1344/**
1345 * pcibios_set_pcie_reset_state - set reset state for device dev
1346 * @dev: the PCIe device reset
1347 * @state: Reset state to enter into
1348 *
1349 *
1350 * Sets the PCIe reset state for the device. This is the default
1351 * implementation. Architecture implementations can override this.
1352 */
1353int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1354 enum pcie_reset_state state)
1355{
1356 return -EINVAL;
1357}
1358
1359/**
1360 * pci_set_pcie_reset_state - set reset state for device dev
1361 * @dev: the PCIe device reset
1362 * @state: Reset state to enter into
1363 *
1364 *
1365 * Sets the PCI reset state for the device.
1366 */
1367int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1368{
1369 return pcibios_set_pcie_reset_state(dev, state);
1370}
1371
1372/**
1373 * pci_check_pme_status - Check if given device has generated PME.
1374 * @dev: Device to check.
1375 *
1376 * Check the PME status of the device and if set, clear it and clear PME enable
1377 * (if set). Return 'true' if PME status and PME enable were both set or
1378 * 'false' otherwise.
1379 */
1380bool pci_check_pme_status(struct pci_dev *dev)
1381{
1382 int pmcsr_pos;
1383 u16 pmcsr;
1384 bool ret = false;
1385
1386 if (!dev->pm_cap)
1387 return false;
1388
1389 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1390 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1391 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1392 return false;
1393
1394 /* Clear PME status. */
1395 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1396 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1397 /* Disable PME to avoid interrupt flood. */
1398 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1399 ret = true;
1400 }
1401
1402 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1403
1404 return ret;
1405}
1406
1407/**
1408 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1409 * @dev: Device to handle.
1410 * @ign: Ignored.
1411 *
1412 * Check if @dev has generated PME and queue a resume request for it in that
1413 * case.
1414 */
1415static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1416{
1417 if (pci_check_pme_status(dev)) {
1418 pci_wakeup_event(dev);
1419 pm_request_resume(&dev->dev);
1420 }
1421 return 0;
1422}
1423
1424/**
1425 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1426 * @bus: Top bus of the subtree to walk.
1427 */
1428void pci_pme_wakeup_bus(struct pci_bus *bus)
1429{
1430 if (bus)
1431 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1432}
1433
1434/**
1435 * pci_pme_capable - check the capability of PCI device to generate PME#
1436 * @dev: PCI device to handle.
1437 * @state: PCI state from which device will issue PME#.
1438 */
1439bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1440{
1441 if (!dev->pm_cap)
1442 return false;
1443
1444 return !!(dev->pme_support & (1 << state));
1445}
1446
1447static void pci_pme_list_scan(struct work_struct *work)
1448{
1449 struct pci_pme_device *pme_dev;
1450
1451 mutex_lock(&pci_pme_list_mutex);
1452 if (!list_empty(&pci_pme_list)) {
1453 list_for_each_entry(pme_dev, &pci_pme_list, list)
1454 pci_pme_wakeup(pme_dev->dev, NULL);
1455 schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1456 }
1457 mutex_unlock(&pci_pme_list_mutex);
1458}
1459
1460/**
1461 * pci_external_pme - is a device an external PCI PME source?
1462 * @dev: PCI device to check
1463 *
1464 */
1465
1466static bool pci_external_pme(struct pci_dev *dev)
1467{
1468 if (pci_is_pcie(dev) || dev->bus->number == 0)
1469 return false;
1470 return true;
1471}
1472
1473/**
1474 * pci_pme_active - enable or disable PCI device's PME# function
1475 * @dev: PCI device to handle.
1476 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1477 *
1478 * The caller must verify that the device is capable of generating PME# before
1479 * calling this function with @enable equal to 'true'.
1480 */
1481void pci_pme_active(struct pci_dev *dev, bool enable)
1482{
1483 u16 pmcsr;
1484
1485 if (!dev->pm_cap)
1486 return;
1487
1488 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1489 /* Clear PME_Status by writing 1 to it and enable PME# */
1490 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1491 if (!enable)
1492 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1493
1494 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1495
1496 /* PCI (as opposed to PCIe) PME requires that the device have
1497 its PME# line hooked up correctly. Not all hardware vendors
1498 do this, so the PME never gets delivered and the device
1499 remains asleep. The easiest way around this is to
1500 periodically walk the list of suspended devices and check
1501 whether any have their PME flag set. The assumption is that
1502 we'll wake up often enough anyway that this won't be a huge
1503 hit, and the power savings from the devices will still be a
1504 win. */
1505
1506 if (pci_external_pme(dev)) {
1507 struct pci_pme_device *pme_dev;
1508 if (enable) {
1509 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1510 GFP_KERNEL);
1511 if (!pme_dev)
1512 goto out;
1513 pme_dev->dev = dev;
1514 mutex_lock(&pci_pme_list_mutex);
1515 list_add(&pme_dev->list, &pci_pme_list);
1516 if (list_is_singular(&pci_pme_list))
1517 schedule_delayed_work(&pci_pme_work,
1518 msecs_to_jiffies(PME_TIMEOUT));
1519 mutex_unlock(&pci_pme_list_mutex);
1520 } else {
1521 mutex_lock(&pci_pme_list_mutex);
1522 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1523 if (pme_dev->dev == dev) {
1524 list_del(&pme_dev->list);
1525 kfree(pme_dev);
1526 break;
1527 }
1528 }
1529 mutex_unlock(&pci_pme_list_mutex);
1530 }
1531 }
1532
1533out:
1534 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1535 enable ? "enabled" : "disabled");
1536}
1537
1538/**
1539 * __pci_enable_wake - enable PCI device as wakeup event source
1540 * @dev: PCI device affected
1541 * @state: PCI state from which device will issue wakeup events
1542 * @runtime: True if the events are to be generated at run time
1543 * @enable: True to enable event generation; false to disable
1544 *
1545 * This enables the device as a wakeup event source, or disables it.
1546 * When such events involves platform-specific hooks, those hooks are
1547 * called automatically by this routine.
1548 *
1549 * Devices with legacy power management (no standard PCI PM capabilities)
1550 * always require such platform hooks.
1551 *
1552 * RETURN VALUE:
1553 * 0 is returned on success
1554 * -EINVAL is returned if device is not supposed to wake up the system
1555 * Error code depending on the platform is returned if both the platform and
1556 * the native mechanism fail to enable the generation of wake-up events
1557 */
1558int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1559 bool runtime, bool enable)
1560{
1561 int ret = 0;
1562
1563 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1564 return -EINVAL;
1565
1566 /* Don't do the same thing twice in a row for one device. */
1567 if (!!enable == !!dev->wakeup_prepared)
1568 return 0;
1569
1570 /*
1571 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1572 * Anderson we should be doing PME# wake enable followed by ACPI wake
1573 * enable. To disable wake-up we call the platform first, for symmetry.
1574 */
1575
1576 if (enable) {
1577 int error;
1578
1579 if (pci_pme_capable(dev, state))
1580 pci_pme_active(dev, true);
1581 else
1582 ret = 1;
1583 error = runtime ? platform_pci_run_wake(dev, true) :
1584 platform_pci_sleep_wake(dev, true);
1585 if (ret)
1586 ret = error;
1587 if (!ret)
1588 dev->wakeup_prepared = true;
1589 } else {
1590 if (runtime)
1591 platform_pci_run_wake(dev, false);
1592 else
1593 platform_pci_sleep_wake(dev, false);
1594 pci_pme_active(dev, false);
1595 dev->wakeup_prepared = false;
1596 }
1597
1598 return ret;
1599}
1600EXPORT_SYMBOL(__pci_enable_wake);
1601
1602/**
1603 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1604 * @dev: PCI device to prepare
1605 * @enable: True to enable wake-up event generation; false to disable
1606 *
1607 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1608 * and this function allows them to set that up cleanly - pci_enable_wake()
1609 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1610 * ordering constraints.
1611 *
1612 * This function only returns error code if the device is not capable of
1613 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1614 * enable wake-up power for it.
1615 */
1616int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1617{
1618 return pci_pme_capable(dev, PCI_D3cold) ?
1619 pci_enable_wake(dev, PCI_D3cold, enable) :
1620 pci_enable_wake(dev, PCI_D3hot, enable);
1621}
1622
1623/**
1624 * pci_target_state - find an appropriate low power state for a given PCI dev
1625 * @dev: PCI device
1626 *
1627 * Use underlying platform code to find a supported low power state for @dev.
1628 * If the platform can't manage @dev, return the deepest state from which it
1629 * can generate wake events, based on any available PME info.
1630 */
1631pci_power_t pci_target_state(struct pci_dev *dev)
1632{
1633 pci_power_t target_state = PCI_D3hot;
1634
1635 if (platform_pci_power_manageable(dev)) {
1636 /*
1637 * Call the platform to choose the target state of the device
1638 * and enable wake-up from this state if supported.
1639 */
1640 pci_power_t state = platform_pci_choose_state(dev);
1641
1642 switch (state) {
1643 case PCI_POWER_ERROR:
1644 case PCI_UNKNOWN:
1645 break;
1646 case PCI_D1:
1647 case PCI_D2:
1648 if (pci_no_d1d2(dev))
1649 break;
1650 default:
1651 target_state = state;
1652 }
1653 } else if (!dev->pm_cap) {
1654 target_state = PCI_D0;
1655 } else if (device_may_wakeup(&dev->dev)) {
1656 /*
1657 * Find the deepest state from which the device can generate
1658 * wake-up events, make it the target state and enable device
1659 * to generate PME#.
1660 */
1661 if (dev->pme_support) {
1662 while (target_state
1663 && !(dev->pme_support & (1 << target_state)))
1664 target_state--;
1665 }
1666 }
1667
1668 return target_state;
1669}
1670
1671/**
1672 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1673 * @dev: Device to handle.
1674 *
1675 * Choose the power state appropriate for the device depending on whether
1676 * it can wake up the system and/or is power manageable by the platform
1677 * (PCI_D3hot is the default) and put the device into that state.
1678 */
1679int pci_prepare_to_sleep(struct pci_dev *dev)
1680{
1681 pci_power_t target_state = pci_target_state(dev);
1682 int error;
1683
1684 if (target_state == PCI_POWER_ERROR)
1685 return -EIO;
1686
1687 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1688
1689 error = pci_set_power_state(dev, target_state);
1690
1691 if (error)
1692 pci_enable_wake(dev, target_state, false);
1693
1694 return error;
1695}
1696
1697/**
1698 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1699 * @dev: Device to handle.
1700 *
1701 * Disable device's system wake-up capability and put it into D0.
1702 */
1703int pci_back_from_sleep(struct pci_dev *dev)
1704{
1705 pci_enable_wake(dev, PCI_D0, false);
1706 return pci_set_power_state(dev, PCI_D0);
1707}
1708
1709/**
1710 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1711 * @dev: PCI device being suspended.
1712 *
1713 * Prepare @dev to generate wake-up events at run time and put it into a low
1714 * power state.
1715 */
1716int pci_finish_runtime_suspend(struct pci_dev *dev)
1717{
1718 pci_power_t target_state = pci_target_state(dev);
1719 int error;
1720
1721 if (target_state == PCI_POWER_ERROR)
1722 return -EIO;
1723
1724 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1725
1726 error = pci_set_power_state(dev, target_state);
1727
1728 if (error)
1729 __pci_enable_wake(dev, target_state, true, false);
1730
1731 return error;
1732}
1733
1734/**
1735 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1736 * @dev: Device to check.
1737 *
1738 * Return true if the device itself is cabable of generating wake-up events
1739 * (through the platform or using the native PCIe PME) or if the device supports
1740 * PME and one of its upstream bridges can generate wake-up events.
1741 */
1742bool pci_dev_run_wake(struct pci_dev *dev)
1743{
1744 struct pci_bus *bus = dev->bus;
1745
1746 if (device_run_wake(&dev->dev))
1747 return true;
1748
1749 if (!dev->pme_support)
1750 return false;
1751
1752 while (bus->parent) {
1753 struct pci_dev *bridge = bus->self;
1754
1755 if (device_run_wake(&bridge->dev))
1756 return true;
1757
1758 bus = bus->parent;
1759 }
1760
1761 /* We have reached the root bus. */
1762 if (bus->bridge)
1763 return device_run_wake(bus->bridge);
1764
1765 return false;
1766}
1767EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1768
1769/**
1770 * pci_pm_init - Initialize PM functions of given PCI device
1771 * @dev: PCI device to handle.
1772 */
1773void pci_pm_init(struct pci_dev *dev)
1774{
1775 int pm;
1776 u16 pmc;
1777
1778 pm_runtime_forbid(&dev->dev);
1779 device_enable_async_suspend(&dev->dev);
1780 dev->wakeup_prepared = false;
1781
1782 dev->pm_cap = 0;
1783
1784 /* find PCI PM capability in list */
1785 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1786 if (!pm)
1787 return;
1788 /* Check device's ability to generate PME# */
1789 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1790
1791 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1792 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1793 pmc & PCI_PM_CAP_VER_MASK);
1794 return;
1795 }
1796
1797 dev->pm_cap = pm;
1798 dev->d3_delay = PCI_PM_D3_WAIT;
1799
1800 dev->d1_support = false;
1801 dev->d2_support = false;
1802 if (!pci_no_d1d2(dev)) {
1803 if (pmc & PCI_PM_CAP_D1)
1804 dev->d1_support = true;
1805 if (pmc & PCI_PM_CAP_D2)
1806 dev->d2_support = true;
1807
1808 if (dev->d1_support || dev->d2_support)
1809 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1810 dev->d1_support ? " D1" : "",
1811 dev->d2_support ? " D2" : "");
1812 }
1813
1814 pmc &= PCI_PM_CAP_PME_MASK;
1815 if (pmc) {
1816 dev_printk(KERN_DEBUG, &dev->dev,
1817 "PME# supported from%s%s%s%s%s\n",
1818 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1819 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1820 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1821 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1822 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1823 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1824 /*
1825 * Make device's PM flags reflect the wake-up capability, but
1826 * let the user space enable it to wake up the system as needed.
1827 */
1828 device_set_wakeup_capable(&dev->dev, true);
1829 /* Disable the PME# generation functionality */
1830 pci_pme_active(dev, false);
1831 } else {
1832 dev->pme_support = 0;
1833 }
1834}
1835
1836/**
1837 * platform_pci_wakeup_init - init platform wakeup if present
1838 * @dev: PCI device
1839 *
1840 * Some devices don't have PCI PM caps but can still generate wakeup
1841 * events through platform methods (like ACPI events). If @dev supports
1842 * platform wakeup events, set the device flag to indicate as much. This
1843 * may be redundant if the device also supports PCI PM caps, but double
1844 * initialization should be safe in that case.
1845 */
1846void platform_pci_wakeup_init(struct pci_dev *dev)
1847{
1848 if (!platform_pci_can_wakeup(dev))
1849 return;
1850
1851 device_set_wakeup_capable(&dev->dev, true);
1852 platform_pci_sleep_wake(dev, false);
1853}
1854
1855/**
1856 * pci_add_save_buffer - allocate buffer for saving given capability registers
1857 * @dev: the PCI device
1858 * @cap: the capability to allocate the buffer for
1859 * @size: requested size of the buffer
1860 */
1861static int pci_add_cap_save_buffer(
1862 struct pci_dev *dev, char cap, unsigned int size)
1863{
1864 int pos;
1865 struct pci_cap_saved_state *save_state;
1866
1867 pos = pci_find_capability(dev, cap);
1868 if (pos <= 0)
1869 return 0;
1870
1871 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1872 if (!save_state)
1873 return -ENOMEM;
1874
1875 save_state->cap.cap_nr = cap;
1876 save_state->cap.size = size;
1877 pci_add_saved_cap(dev, save_state);
1878
1879 return 0;
1880}
1881
1882/**
1883 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1884 * @dev: the PCI device
1885 */
1886void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1887{
1888 int error;
1889
1890 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1891 PCI_EXP_SAVE_REGS * sizeof(u16));
1892 if (error)
1893 dev_err(&dev->dev,
1894 "unable to preallocate PCI Express save buffer\n");
1895
1896 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1897 if (error)
1898 dev_err(&dev->dev,
1899 "unable to preallocate PCI-X save buffer\n");
1900}
1901
1902/**
1903 * pci_enable_ari - enable ARI forwarding if hardware support it
1904 * @dev: the PCI device
1905 */
1906void pci_enable_ari(struct pci_dev *dev)
1907{
1908 int pos;
1909 u32 cap;
1910 u16 flags, ctrl;
1911 struct pci_dev *bridge;
1912
1913 if (!pci_is_pcie(dev) || dev->devfn)
1914 return;
1915
1916 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1917 if (!pos)
1918 return;
1919
1920 bridge = dev->bus->self;
1921 if (!bridge || !pci_is_pcie(bridge))
1922 return;
1923
1924 pos = pci_pcie_cap(bridge);
1925 if (!pos)
1926 return;
1927
1928 /* ARI is a PCIe v2 feature */
1929 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1930 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1931 return;
1932
1933 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1934 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1935 return;
1936
1937 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1938 ctrl |= PCI_EXP_DEVCTL2_ARI;
1939 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1940
1941 bridge->ari_enabled = 1;
1942}
1943
1944/**
1945 * pci_enable_ido - enable ID-based ordering on a device
1946 * @dev: the PCI device
1947 * @type: which types of IDO to enable
1948 *
1949 * Enable ID-based ordering on @dev. @type can contain the bits
1950 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1951 * which types of transactions are allowed to be re-ordered.
1952 */
1953void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1954{
1955 int pos;
1956 u16 ctrl;
1957
1958 pos = pci_pcie_cap(dev);
1959 if (!pos)
1960 return;
1961
1962 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1963 if (type & PCI_EXP_IDO_REQUEST)
1964 ctrl |= PCI_EXP_IDO_REQ_EN;
1965 if (type & PCI_EXP_IDO_COMPLETION)
1966 ctrl |= PCI_EXP_IDO_CMP_EN;
1967 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1968}
1969EXPORT_SYMBOL(pci_enable_ido);
1970
1971/**
1972 * pci_disable_ido - disable ID-based ordering on a device
1973 * @dev: the PCI device
1974 * @type: which types of IDO to disable
1975 */
1976void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1977{
1978 int pos;
1979 u16 ctrl;
1980
1981 if (!pci_is_pcie(dev))
1982 return;
1983
1984 pos = pci_pcie_cap(dev);
1985 if (!pos)
1986 return;
1987
1988 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1989 if (type & PCI_EXP_IDO_REQUEST)
1990 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1991 if (type & PCI_EXP_IDO_COMPLETION)
1992 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1993 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1994}
1995EXPORT_SYMBOL(pci_disable_ido);
1996
1997/**
1998 * pci_enable_obff - enable optimized buffer flush/fill
1999 * @dev: PCI device
2000 * @type: type of signaling to use
2001 *
2002 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2003 * signaling if possible, falling back to message signaling only if
2004 * WAKE# isn't supported. @type should indicate whether the PCIe link
2005 * be brought out of L0s or L1 to send the message. It should be either
2006 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2007 *
2008 * If your device can benefit from receiving all messages, even at the
2009 * power cost of bringing the link back up from a low power state, use
2010 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2011 * preferred type).
2012 *
2013 * RETURNS:
2014 * Zero on success, appropriate error number on failure.
2015 */
2016int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2017{
2018 int pos;
2019 u32 cap;
2020 u16 ctrl;
2021 int ret;
2022
2023 if (!pci_is_pcie(dev))
2024 return -ENOTSUPP;
2025
2026 pos = pci_pcie_cap(dev);
2027 if (!pos)
2028 return -ENOTSUPP;
2029
2030 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2031 if (!(cap & PCI_EXP_OBFF_MASK))
2032 return -ENOTSUPP; /* no OBFF support at all */
2033
2034 /* Make sure the topology supports OBFF as well */
2035 if (dev->bus) {
2036 ret = pci_enable_obff(dev->bus->self, type);
2037 if (ret)
2038 return ret;
2039 }
2040
2041 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2042 if (cap & PCI_EXP_OBFF_WAKE)
2043 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2044 else {
2045 switch (type) {
2046 case PCI_EXP_OBFF_SIGNAL_L0:
2047 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2048 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2049 break;
2050 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2051 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2052 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2053 break;
2054 default:
2055 WARN(1, "bad OBFF signal type\n");
2056 return -ENOTSUPP;
2057 }
2058 }
2059 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2060
2061 return 0;
2062}
2063EXPORT_SYMBOL(pci_enable_obff);
2064
2065/**
2066 * pci_disable_obff - disable optimized buffer flush/fill
2067 * @dev: PCI device
2068 *
2069 * Disable OBFF on @dev.
2070 */
2071void pci_disable_obff(struct pci_dev *dev)
2072{
2073 int pos;
2074 u16 ctrl;
2075
2076 if (!pci_is_pcie(dev))
2077 return;
2078
2079 pos = pci_pcie_cap(dev);
2080 if (!pos)
2081 return;
2082
2083 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2084 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2085 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2086}
2087EXPORT_SYMBOL(pci_disable_obff);
2088
2089/**
2090 * pci_ltr_supported - check whether a device supports LTR
2091 * @dev: PCI device
2092 *
2093 * RETURNS:
2094 * True if @dev supports latency tolerance reporting, false otherwise.
2095 */
2096bool pci_ltr_supported(struct pci_dev *dev)
2097{
2098 int pos;
2099 u32 cap;
2100
2101 if (!pci_is_pcie(dev))
2102 return false;
2103
2104 pos = pci_pcie_cap(dev);
2105 if (!pos)
2106 return false;
2107
2108 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2109
2110 return cap & PCI_EXP_DEVCAP2_LTR;
2111}
2112EXPORT_SYMBOL(pci_ltr_supported);
2113
2114/**
2115 * pci_enable_ltr - enable latency tolerance reporting
2116 * @dev: PCI device
2117 *
2118 * Enable LTR on @dev if possible, which means enabling it first on
2119 * upstream ports.
2120 *
2121 * RETURNS:
2122 * Zero on success, errno on failure.
2123 */
2124int pci_enable_ltr(struct pci_dev *dev)
2125{
2126 int pos;
2127 u16 ctrl;
2128 int ret;
2129
2130 if (!pci_ltr_supported(dev))
2131 return -ENOTSUPP;
2132
2133 pos = pci_pcie_cap(dev);
2134 if (!pos)
2135 return -ENOTSUPP;
2136
2137 /* Only primary function can enable/disable LTR */
2138 if (PCI_FUNC(dev->devfn) != 0)
2139 return -EINVAL;
2140
2141 /* Enable upstream ports first */
2142 if (dev->bus) {
2143 ret = pci_enable_ltr(dev->bus->self);
2144 if (ret)
2145 return ret;
2146 }
2147
2148 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2149 ctrl |= PCI_EXP_LTR_EN;
2150 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2151
2152 return 0;
2153}
2154EXPORT_SYMBOL(pci_enable_ltr);
2155
2156/**
2157 * pci_disable_ltr - disable latency tolerance reporting
2158 * @dev: PCI device
2159 */
2160void pci_disable_ltr(struct pci_dev *dev)
2161{
2162 int pos;
2163 u16 ctrl;
2164
2165 if (!pci_ltr_supported(dev))
2166 return;
2167
2168 pos = pci_pcie_cap(dev);
2169 if (!pos)
2170 return;
2171
2172 /* Only primary function can enable/disable LTR */
2173 if (PCI_FUNC(dev->devfn) != 0)
2174 return;
2175
2176 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2177 ctrl &= ~PCI_EXP_LTR_EN;
2178 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2179}
2180EXPORT_SYMBOL(pci_disable_ltr);
2181
2182static int __pci_ltr_scale(int *val)
2183{
2184 int scale = 0;
2185
2186 while (*val > 1023) {
2187 *val = (*val + 31) / 32;
2188 scale++;
2189 }
2190 return scale;
2191}
2192
2193/**
2194 * pci_set_ltr - set LTR latency values
2195 * @dev: PCI device
2196 * @snoop_lat_ns: snoop latency in nanoseconds
2197 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2198 *
2199 * Figure out the scale and set the LTR values accordingly.
2200 */
2201int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2202{
2203 int pos, ret, snoop_scale, nosnoop_scale;
2204 u16 val;
2205
2206 if (!pci_ltr_supported(dev))
2207 return -ENOTSUPP;
2208
2209 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2210 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2211
2212 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2213 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2214 return -EINVAL;
2215
2216 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2217 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2218 return -EINVAL;
2219
2220 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2221 if (!pos)
2222 return -ENOTSUPP;
2223
2224 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2225 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2226 if (ret != 4)
2227 return -EIO;
2228
2229 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2230 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2231 if (ret != 4)
2232 return -EIO;
2233
2234 return 0;
2235}
2236EXPORT_SYMBOL(pci_set_ltr);
2237
2238static int pci_acs_enable;
2239
2240/**
2241 * pci_request_acs - ask for ACS to be enabled if supported
2242 */
2243void pci_request_acs(void)
2244{
2245 pci_acs_enable = 1;
2246}
2247
2248/**
2249 * pci_enable_acs - enable ACS if hardware support it
2250 * @dev: the PCI device
2251 */
2252void pci_enable_acs(struct pci_dev *dev)
2253{
2254 int pos;
2255 u16 cap;
2256 u16 ctrl;
2257
2258 if (!pci_acs_enable)
2259 return;
2260
2261 if (!pci_is_pcie(dev))
2262 return;
2263
2264 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2265 if (!pos)
2266 return;
2267
2268 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2269 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2270
2271 /* Source Validation */
2272 ctrl |= (cap & PCI_ACS_SV);
2273
2274 /* P2P Request Redirect */
2275 ctrl |= (cap & PCI_ACS_RR);
2276
2277 /* P2P Completion Redirect */
2278 ctrl |= (cap & PCI_ACS_CR);
2279
2280 /* Upstream Forwarding */
2281 ctrl |= (cap & PCI_ACS_UF);
2282
2283 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2284}
2285
2286/**
2287 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2288 * @dev: the PCI device
2289 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2290 *
2291 * Perform INTx swizzling for a device behind one level of bridge. This is
2292 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2293 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2294 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2295 * the PCI Express Base Specification, Revision 2.1)
2296 */
2297u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2298{
2299 int slot;
2300
2301 if (pci_ari_enabled(dev->bus))
2302 slot = 0;
2303 else
2304 slot = PCI_SLOT(dev->devfn);
2305
2306 return (((pin - 1) + slot) % 4) + 1;
2307}
2308
2309int
2310pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2311{
2312 u8 pin;
2313
2314 pin = dev->pin;
2315 if (!pin)
2316 return -1;
2317
2318 while (!pci_is_root_bus(dev->bus)) {
2319 pin = pci_swizzle_interrupt_pin(dev, pin);
2320 dev = dev->bus->self;
2321 }
2322 *bridge = dev;
2323 return pin;
2324}
2325
2326/**
2327 * pci_common_swizzle - swizzle INTx all the way to root bridge
2328 * @dev: the PCI device
2329 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2330 *
2331 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2332 * bridges all the way up to a PCI root bus.
2333 */
2334u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2335{
2336 u8 pin = *pinp;
2337
2338 while (!pci_is_root_bus(dev->bus)) {
2339 pin = pci_swizzle_interrupt_pin(dev, pin);
2340 dev = dev->bus->self;
2341 }
2342 *pinp = pin;
2343 return PCI_SLOT(dev->devfn);
2344}
2345
2346/**
2347 * pci_release_region - Release a PCI bar
2348 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2349 * @bar: BAR to release
2350 *
2351 * Releases the PCI I/O and memory resources previously reserved by a
2352 * successful call to pci_request_region. Call this function only
2353 * after all use of the PCI regions has ceased.
2354 */
2355void pci_release_region(struct pci_dev *pdev, int bar)
2356{
2357 struct pci_devres *dr;
2358
2359 if (pci_resource_len(pdev, bar) == 0)
2360 return;
2361 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2362 release_region(pci_resource_start(pdev, bar),
2363 pci_resource_len(pdev, bar));
2364 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2365 release_mem_region(pci_resource_start(pdev, bar),
2366 pci_resource_len(pdev, bar));
2367
2368 dr = find_pci_dr(pdev);
2369 if (dr)
2370 dr->region_mask &= ~(1 << bar);
2371}
2372
2373/**
2374 * __pci_request_region - Reserved PCI I/O and memory resource
2375 * @pdev: PCI device whose resources are to be reserved
2376 * @bar: BAR to be reserved
2377 * @res_name: Name to be associated with resource.
2378 * @exclusive: whether the region access is exclusive or not
2379 *
2380 * Mark the PCI region associated with PCI device @pdev BR @bar as
2381 * being reserved by owner @res_name. Do not access any
2382 * address inside the PCI regions unless this call returns
2383 * successfully.
2384 *
2385 * If @exclusive is set, then the region is marked so that userspace
2386 * is explicitly not allowed to map the resource via /dev/mem or
2387 * sysfs MMIO access.
2388 *
2389 * Returns 0 on success, or %EBUSY on error. A warning
2390 * message is also printed on failure.
2391 */
2392static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2393 int exclusive)
2394{
2395 struct pci_devres *dr;
2396
2397 if (pci_resource_len(pdev, bar) == 0)
2398 return 0;
2399
2400 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2401 if (!request_region(pci_resource_start(pdev, bar),
2402 pci_resource_len(pdev, bar), res_name))
2403 goto err_out;
2404 }
2405 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2406 if (!__request_mem_region(pci_resource_start(pdev, bar),
2407 pci_resource_len(pdev, bar), res_name,
2408 exclusive))
2409 goto err_out;
2410 }
2411
2412 dr = find_pci_dr(pdev);
2413 if (dr)
2414 dr->region_mask |= 1 << bar;
2415
2416 return 0;
2417
2418err_out:
2419 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2420 &pdev->resource[bar]);
2421 return -EBUSY;
2422}
2423
2424/**
2425 * pci_request_region - Reserve PCI I/O and memory resource
2426 * @pdev: PCI device whose resources are to be reserved
2427 * @bar: BAR to be reserved
2428 * @res_name: Name to be associated with resource
2429 *
2430 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2431 * being reserved by owner @res_name. Do not access any
2432 * address inside the PCI regions unless this call returns
2433 * successfully.
2434 *
2435 * Returns 0 on success, or %EBUSY on error. A warning
2436 * message is also printed on failure.
2437 */
2438int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2439{
2440 return __pci_request_region(pdev, bar, res_name, 0);
2441}
2442
2443/**
2444 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2445 * @pdev: PCI device whose resources are to be reserved
2446 * @bar: BAR to be reserved
2447 * @res_name: Name to be associated with resource.
2448 *
2449 * Mark the PCI region associated with PCI device @pdev BR @bar as
2450 * being reserved by owner @res_name. Do not access any
2451 * address inside the PCI regions unless this call returns
2452 * successfully.
2453 *
2454 * Returns 0 on success, or %EBUSY on error. A warning
2455 * message is also printed on failure.
2456 *
2457 * The key difference that _exclusive makes it that userspace is
2458 * explicitly not allowed to map the resource via /dev/mem or
2459 * sysfs.
2460 */
2461int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2462{
2463 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2464}
2465/**
2466 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2467 * @pdev: PCI device whose resources were previously reserved
2468 * @bars: Bitmask of BARs to be released
2469 *
2470 * Release selected PCI I/O and memory resources previously reserved.
2471 * Call this function only after all use of the PCI regions has ceased.
2472 */
2473void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2474{
2475 int i;
2476
2477 for (i = 0; i < 6; i++)
2478 if (bars & (1 << i))
2479 pci_release_region(pdev, i);
2480}
2481
2482int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2483 const char *res_name, int excl)
2484{
2485 int i;
2486
2487 for (i = 0; i < 6; i++)
2488 if (bars & (1 << i))
2489 if (__pci_request_region(pdev, i, res_name, excl))
2490 goto err_out;
2491 return 0;
2492
2493err_out:
2494 while(--i >= 0)
2495 if (bars & (1 << i))
2496 pci_release_region(pdev, i);
2497
2498 return -EBUSY;
2499}
2500
2501
2502/**
2503 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2504 * @pdev: PCI device whose resources are to be reserved
2505 * @bars: Bitmask of BARs to be requested
2506 * @res_name: Name to be associated with resource
2507 */
2508int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2509 const char *res_name)
2510{
2511 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2512}
2513
2514int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2515 int bars, const char *res_name)
2516{
2517 return __pci_request_selected_regions(pdev, bars, res_name,
2518 IORESOURCE_EXCLUSIVE);
2519}
2520
2521/**
2522 * pci_release_regions - Release reserved PCI I/O and memory resources
2523 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2524 *
2525 * Releases all PCI I/O and memory resources previously reserved by a
2526 * successful call to pci_request_regions. Call this function only
2527 * after all use of the PCI regions has ceased.
2528 */
2529
2530void pci_release_regions(struct pci_dev *pdev)
2531{
2532 pci_release_selected_regions(pdev, (1 << 6) - 1);
2533}
2534
2535/**
2536 * pci_request_regions - Reserved PCI I/O and memory resources
2537 * @pdev: PCI device whose resources are to be reserved
2538 * @res_name: Name to be associated with resource.
2539 *
2540 * Mark all PCI regions associated with PCI device @pdev as
2541 * being reserved by owner @res_name. Do not access any
2542 * address inside the PCI regions unless this call returns
2543 * successfully.
2544 *
2545 * Returns 0 on success, or %EBUSY on error. A warning
2546 * message is also printed on failure.
2547 */
2548int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2549{
2550 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2551}
2552
2553/**
2554 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2555 * @pdev: PCI device whose resources are to be reserved
2556 * @res_name: Name to be associated with resource.
2557 *
2558 * Mark all PCI regions associated with PCI device @pdev as
2559 * being reserved by owner @res_name. Do not access any
2560 * address inside the PCI regions unless this call returns
2561 * successfully.
2562 *
2563 * pci_request_regions_exclusive() will mark the region so that
2564 * /dev/mem and the sysfs MMIO access will not be allowed.
2565 *
2566 * Returns 0 on success, or %EBUSY on error. A warning
2567 * message is also printed on failure.
2568 */
2569int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2570{
2571 return pci_request_selected_regions_exclusive(pdev,
2572 ((1 << 6) - 1), res_name);
2573}
2574
2575static void __pci_set_master(struct pci_dev *dev, bool enable)
2576{
2577 u16 old_cmd, cmd;
2578
2579 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2580 if (enable)
2581 cmd = old_cmd | PCI_COMMAND_MASTER;
2582 else
2583 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2584 if (cmd != old_cmd) {
2585 dev_dbg(&dev->dev, "%s bus mastering\n",
2586 enable ? "enabling" : "disabling");
2587 pci_write_config_word(dev, PCI_COMMAND, cmd);
2588 }
2589 dev->is_busmaster = enable;
2590}
2591
2592/**
2593 * pci_set_master - enables bus-mastering for device dev
2594 * @dev: the PCI device to enable
2595 *
2596 * Enables bus-mastering on the device and calls pcibios_set_master()
2597 * to do the needed arch specific settings.
2598 */
2599void pci_set_master(struct pci_dev *dev)
2600{
2601 __pci_set_master(dev, true);
2602 pcibios_set_master(dev);
2603}
2604
2605/**
2606 * pci_clear_master - disables bus-mastering for device dev
2607 * @dev: the PCI device to disable
2608 */
2609void pci_clear_master(struct pci_dev *dev)
2610{
2611 __pci_set_master(dev, false);
2612}
2613
2614/**
2615 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2616 * @dev: the PCI device for which MWI is to be enabled
2617 *
2618 * Helper function for pci_set_mwi.
2619 * Originally copied from drivers/net/acenic.c.
2620 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2621 *
2622 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2623 */
2624int pci_set_cacheline_size(struct pci_dev *dev)
2625{
2626 u8 cacheline_size;
2627
2628 if (!pci_cache_line_size)
2629 return -EINVAL;
2630
2631 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2632 equal to or multiple of the right value. */
2633 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2634 if (cacheline_size >= pci_cache_line_size &&
2635 (cacheline_size % pci_cache_line_size) == 0)
2636 return 0;
2637
2638 /* Write the correct value. */
2639 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2640 /* Read it back. */
2641 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2642 if (cacheline_size == pci_cache_line_size)
2643 return 0;
2644
2645 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2646 "supported\n", pci_cache_line_size << 2);
2647
2648 return -EINVAL;
2649}
2650EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2651
2652#ifdef PCI_DISABLE_MWI
2653int pci_set_mwi(struct pci_dev *dev)
2654{
2655 return 0;
2656}
2657
2658int pci_try_set_mwi(struct pci_dev *dev)
2659{
2660 return 0;
2661}
2662
2663void pci_clear_mwi(struct pci_dev *dev)
2664{
2665}
2666
2667#else
2668
2669/**
2670 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2671 * @dev: the PCI device for which MWI is enabled
2672 *
2673 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2674 *
2675 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2676 */
2677int
2678pci_set_mwi(struct pci_dev *dev)
2679{
2680 int rc;
2681 u16 cmd;
2682
2683 rc = pci_set_cacheline_size(dev);
2684 if (rc)
2685 return rc;
2686
2687 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2688 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2689 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2690 cmd |= PCI_COMMAND_INVALIDATE;
2691 pci_write_config_word(dev, PCI_COMMAND, cmd);
2692 }
2693
2694 return 0;
2695}
2696
2697/**
2698 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2699 * @dev: the PCI device for which MWI is enabled
2700 *
2701 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2702 * Callers are not required to check the return value.
2703 *
2704 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2705 */
2706int pci_try_set_mwi(struct pci_dev *dev)
2707{
2708 int rc = pci_set_mwi(dev);
2709 return rc;
2710}
2711
2712/**
2713 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2714 * @dev: the PCI device to disable
2715 *
2716 * Disables PCI Memory-Write-Invalidate transaction on the device
2717 */
2718void
2719pci_clear_mwi(struct pci_dev *dev)
2720{
2721 u16 cmd;
2722
2723 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2724 if (cmd & PCI_COMMAND_INVALIDATE) {
2725 cmd &= ~PCI_COMMAND_INVALIDATE;
2726 pci_write_config_word(dev, PCI_COMMAND, cmd);
2727 }
2728}
2729#endif /* ! PCI_DISABLE_MWI */
2730
2731/**
2732 * pci_intx - enables/disables PCI INTx for device dev
2733 * @pdev: the PCI device to operate on
2734 * @enable: boolean: whether to enable or disable PCI INTx
2735 *
2736 * Enables/disables PCI INTx for device dev
2737 */
2738void
2739pci_intx(struct pci_dev *pdev, int enable)
2740{
2741 u16 pci_command, new;
2742
2743 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2744
2745 if (enable) {
2746 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2747 } else {
2748 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2749 }
2750
2751 if (new != pci_command) {
2752 struct pci_devres *dr;
2753
2754 pci_write_config_word(pdev, PCI_COMMAND, new);
2755
2756 dr = find_pci_dr(pdev);
2757 if (dr && !dr->restore_intx) {
2758 dr->restore_intx = 1;
2759 dr->orig_intx = !enable;
2760 }
2761 }
2762}
2763
2764/**
2765 * pci_msi_off - disables any msi or msix capabilities
2766 * @dev: the PCI device to operate on
2767 *
2768 * If you want to use msi see pci_enable_msi and friends.
2769 * This is a lower level primitive that allows us to disable
2770 * msi operation at the device level.
2771 */
2772void pci_msi_off(struct pci_dev *dev)
2773{
2774 int pos;
2775 u16 control;
2776
2777 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2778 if (pos) {
2779 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2780 control &= ~PCI_MSI_FLAGS_ENABLE;
2781 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2782 }
2783 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2784 if (pos) {
2785 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2786 control &= ~PCI_MSIX_FLAGS_ENABLE;
2787 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2788 }
2789}
2790EXPORT_SYMBOL_GPL(pci_msi_off);
2791
2792int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2793{
2794 return dma_set_max_seg_size(&dev->dev, size);
2795}
2796EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2797
2798int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2799{
2800 return dma_set_seg_boundary(&dev->dev, mask);
2801}
2802EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2803
2804static int pcie_flr(struct pci_dev *dev, int probe)
2805{
2806 int i;
2807 int pos;
2808 u32 cap;
2809 u16 status, control;
2810
2811 pos = pci_pcie_cap(dev);
2812 if (!pos)
2813 return -ENOTTY;
2814
2815 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2816 if (!(cap & PCI_EXP_DEVCAP_FLR))
2817 return -ENOTTY;
2818
2819 if (probe)
2820 return 0;
2821
2822 /* Wait for Transaction Pending bit clean */
2823 for (i = 0; i < 4; i++) {
2824 if (i)
2825 msleep((1 << (i - 1)) * 100);
2826
2827 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2828 if (!(status & PCI_EXP_DEVSTA_TRPND))
2829 goto clear;
2830 }
2831
2832 dev_err(&dev->dev, "transaction is not cleared; "
2833 "proceeding with reset anyway\n");
2834
2835clear:
2836 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2837 control |= PCI_EXP_DEVCTL_BCR_FLR;
2838 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2839
2840 msleep(100);
2841
2842 return 0;
2843}
2844
2845static int pci_af_flr(struct pci_dev *dev, int probe)
2846{
2847 int i;
2848 int pos;
2849 u8 cap;
2850 u8 status;
2851
2852 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2853 if (!pos)
2854 return -ENOTTY;
2855
2856 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2857 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2858 return -ENOTTY;
2859
2860 if (probe)
2861 return 0;
2862
2863 /* Wait for Transaction Pending bit clean */
2864 for (i = 0; i < 4; i++) {
2865 if (i)
2866 msleep((1 << (i - 1)) * 100);
2867
2868 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2869 if (!(status & PCI_AF_STATUS_TP))
2870 goto clear;
2871 }
2872
2873 dev_err(&dev->dev, "transaction is not cleared; "
2874 "proceeding with reset anyway\n");
2875
2876clear:
2877 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2878 msleep(100);
2879
2880 return 0;
2881}
2882
2883/**
2884 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2885 * @dev: Device to reset.
2886 * @probe: If set, only check if the device can be reset this way.
2887 *
2888 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2889 * unset, it will be reinitialized internally when going from PCI_D3hot to
2890 * PCI_D0. If that's the case and the device is not in a low-power state
2891 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2892 *
2893 * NOTE: This causes the caller to sleep for twice the device power transition
2894 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2895 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2896 * Moreover, only devices in D0 can be reset by this function.
2897 */
2898static int pci_pm_reset(struct pci_dev *dev, int probe)
2899{
2900 u16 csr;
2901
2902 if (!dev->pm_cap)
2903 return -ENOTTY;
2904
2905 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2906 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2907 return -ENOTTY;
2908
2909 if (probe)
2910 return 0;
2911
2912 if (dev->current_state != PCI_D0)
2913 return -EINVAL;
2914
2915 csr &= ~PCI_PM_CTRL_STATE_MASK;
2916 csr |= PCI_D3hot;
2917 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2918 pci_dev_d3_sleep(dev);
2919
2920 csr &= ~PCI_PM_CTRL_STATE_MASK;
2921 csr |= PCI_D0;
2922 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2923 pci_dev_d3_sleep(dev);
2924
2925 return 0;
2926}
2927
2928static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2929{
2930 u16 ctrl;
2931 struct pci_dev *pdev;
2932
2933 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2934 return -ENOTTY;
2935
2936 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2937 if (pdev != dev)
2938 return -ENOTTY;
2939
2940 if (probe)
2941 return 0;
2942
2943 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2944 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2945 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2946 msleep(100);
2947
2948 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2949 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2950 msleep(100);
2951
2952 return 0;
2953}
2954
2955static int pci_dev_reset(struct pci_dev *dev, int probe)
2956{
2957 int rc;
2958
2959 might_sleep();
2960
2961 if (!probe) {
2962 pci_block_user_cfg_access(dev);
2963 /* block PM suspend, driver probe, etc. */
2964 device_lock(&dev->dev);
2965 }
2966
2967 rc = pci_dev_specific_reset(dev, probe);
2968 if (rc != -ENOTTY)
2969 goto done;
2970
2971 rc = pcie_flr(dev, probe);
2972 if (rc != -ENOTTY)
2973 goto done;
2974
2975 rc = pci_af_flr(dev, probe);
2976 if (rc != -ENOTTY)
2977 goto done;
2978
2979 rc = pci_pm_reset(dev, probe);
2980 if (rc != -ENOTTY)
2981 goto done;
2982
2983 rc = pci_parent_bus_reset(dev, probe);
2984done:
2985 if (!probe) {
2986 device_unlock(&dev->dev);
2987 pci_unblock_user_cfg_access(dev);
2988 }
2989
2990 return rc;
2991}
2992
2993/**
2994 * __pci_reset_function - reset a PCI device function
2995 * @dev: PCI device to reset
2996 *
2997 * Some devices allow an individual function to be reset without affecting
2998 * other functions in the same device. The PCI device must be responsive
2999 * to PCI config space in order to use this function.
3000 *
3001 * The device function is presumed to be unused when this function is called.
3002 * Resetting the device will make the contents of PCI configuration space
3003 * random, so any caller of this must be prepared to reinitialise the
3004 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3005 * etc.
3006 *
3007 * Returns 0 if the device function was successfully reset or negative if the
3008 * device doesn't support resetting a single function.
3009 */
3010int __pci_reset_function(struct pci_dev *dev)
3011{
3012 return pci_dev_reset(dev, 0);
3013}
3014EXPORT_SYMBOL_GPL(__pci_reset_function);
3015
3016/**
3017 * pci_probe_reset_function - check whether the device can be safely reset
3018 * @dev: PCI device to reset
3019 *
3020 * Some devices allow an individual function to be reset without affecting
3021 * other functions in the same device. The PCI device must be responsive
3022 * to PCI config space in order to use this function.
3023 *
3024 * Returns 0 if the device function can be reset or negative if the
3025 * device doesn't support resetting a single function.
3026 */
3027int pci_probe_reset_function(struct pci_dev *dev)
3028{
3029 return pci_dev_reset(dev, 1);
3030}
3031
3032/**
3033 * pci_reset_function - quiesce and reset a PCI device function
3034 * @dev: PCI device to reset
3035 *
3036 * Some devices allow an individual function to be reset without affecting
3037 * other functions in the same device. The PCI device must be responsive
3038 * to PCI config space in order to use this function.
3039 *
3040 * This function does not just reset the PCI portion of a device, but
3041 * clears all the state associated with the device. This function differs
3042 * from __pci_reset_function in that it saves and restores device state
3043 * over the reset.
3044 *
3045 * Returns 0 if the device function was successfully reset or negative if the
3046 * device doesn't support resetting a single function.
3047 */
3048int pci_reset_function(struct pci_dev *dev)
3049{
3050 int rc;
3051
3052 rc = pci_dev_reset(dev, 1);
3053 if (rc)
3054 return rc;
3055
3056 pci_save_state(dev);
3057
3058 /*
3059 * both INTx and MSI are disabled after the Interrupt Disable bit
3060 * is set and the Bus Master bit is cleared.
3061 */
3062 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3063
3064 rc = pci_dev_reset(dev, 0);
3065
3066 pci_restore_state(dev);
3067
3068 return rc;
3069}
3070EXPORT_SYMBOL_GPL(pci_reset_function);
3071
3072/**
3073 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3074 * @dev: PCI device to query
3075 *
3076 * Returns mmrbc: maximum designed memory read count in bytes
3077 * or appropriate error value.
3078 */
3079int pcix_get_max_mmrbc(struct pci_dev *dev)
3080{
3081 int cap;
3082 u32 stat;
3083
3084 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3085 if (!cap)
3086 return -EINVAL;
3087
3088 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3089 return -EINVAL;
3090
3091 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3092}
3093EXPORT_SYMBOL(pcix_get_max_mmrbc);
3094
3095/**
3096 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3097 * @dev: PCI device to query
3098 *
3099 * Returns mmrbc: maximum memory read count in bytes
3100 * or appropriate error value.
3101 */
3102int pcix_get_mmrbc(struct pci_dev *dev)
3103{
3104 int cap;
3105 u16 cmd;
3106
3107 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3108 if (!cap)
3109 return -EINVAL;
3110
3111 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3112 return -EINVAL;
3113
3114 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3115}
3116EXPORT_SYMBOL(pcix_get_mmrbc);
3117
3118/**
3119 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3120 * @dev: PCI device to query
3121 * @mmrbc: maximum memory read count in bytes
3122 * valid values are 512, 1024, 2048, 4096
3123 *
3124 * If possible sets maximum memory read byte count, some bridges have erratas
3125 * that prevent this.
3126 */
3127int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3128{
3129 int cap;
3130 u32 stat, v, o;
3131 u16 cmd;
3132
3133 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3134 return -EINVAL;
3135
3136 v = ffs(mmrbc) - 10;
3137
3138 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3139 if (!cap)
3140 return -EINVAL;
3141
3142 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3143 return -EINVAL;
3144
3145 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3146 return -E2BIG;
3147
3148 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3149 return -EINVAL;
3150
3151 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3152 if (o != v) {
3153 if (v > o && dev->bus &&
3154 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3155 return -EIO;
3156
3157 cmd &= ~PCI_X_CMD_MAX_READ;
3158 cmd |= v << 2;
3159 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3160 return -EIO;
3161 }
3162 return 0;
3163}
3164EXPORT_SYMBOL(pcix_set_mmrbc);
3165
3166/**
3167 * pcie_get_readrq - get PCI Express read request size
3168 * @dev: PCI device to query
3169 *
3170 * Returns maximum memory read request in bytes
3171 * or appropriate error value.
3172 */
3173int pcie_get_readrq(struct pci_dev *dev)
3174{
3175 int ret, cap;
3176 u16 ctl;
3177
3178 cap = pci_pcie_cap(dev);
3179 if (!cap)
3180 return -EINVAL;
3181
3182 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3183 if (!ret)
3184 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3185
3186 return ret;
3187}
3188EXPORT_SYMBOL(pcie_get_readrq);
3189
3190/**
3191 * pcie_set_readrq - set PCI Express maximum memory read request
3192 * @dev: PCI device to query
3193 * @rq: maximum memory read count in bytes
3194 * valid values are 128, 256, 512, 1024, 2048, 4096
3195 *
3196 * If possible sets maximum memory read request in bytes
3197 */
3198int pcie_set_readrq(struct pci_dev *dev, int rq)
3199{
3200 int cap, err = -EINVAL;
3201 u16 ctl, v;
3202
3203 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3204 goto out;
3205
3206 v = (ffs(rq) - 8) << 12;
3207
3208 cap = pci_pcie_cap(dev);
3209 if (!cap)
3210 goto out;
3211
3212 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3213 if (err)
3214 goto out;
3215
3216 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3217 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3218 ctl |= v;
3219 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3220 }
3221
3222out:
3223 return err;
3224}
3225EXPORT_SYMBOL(pcie_set_readrq);
3226
3227/**
3228 * pcie_get_mps - get PCI Express maximum payload size
3229 * @dev: PCI device to query
3230 *
3231 * Returns maximum payload size in bytes
3232 * or appropriate error value.
3233 */
3234int pcie_get_mps(struct pci_dev *dev)
3235{
3236 int ret, cap;
3237 u16 ctl;
3238
3239 cap = pci_pcie_cap(dev);
3240 if (!cap)
3241 return -EINVAL;
3242
3243 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3244 if (!ret)
3245 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3246
3247 return ret;
3248}
3249
3250/**
3251 * pcie_set_mps - set PCI Express maximum payload size
3252 * @dev: PCI device to query
3253 * @mps: maximum payload size in bytes
3254 * valid values are 128, 256, 512, 1024, 2048, 4096
3255 *
3256 * If possible sets maximum payload size
3257 */
3258int pcie_set_mps(struct pci_dev *dev, int mps)
3259{
3260 int cap, err = -EINVAL;
3261 u16 ctl, v;
3262
3263 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3264 goto out;
3265
3266 v = ffs(mps) - 8;
3267 if (v > dev->pcie_mpss)
3268 goto out;
3269 v <<= 5;
3270
3271 cap = pci_pcie_cap(dev);
3272 if (!cap)
3273 goto out;
3274
3275 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3276 if (err)
3277 goto out;
3278
3279 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3280 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3281 ctl |= v;
3282 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3283 }
3284out:
3285 return err;
3286}
3287
3288/**
3289 * pci_select_bars - Make BAR mask from the type of resource
3290 * @dev: the PCI device for which BAR mask is made
3291 * @flags: resource type mask to be selected
3292 *
3293 * This helper routine makes bar mask from the type of resource.
3294 */
3295int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3296{
3297 int i, bars = 0;
3298 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3299 if (pci_resource_flags(dev, i) & flags)
3300 bars |= (1 << i);
3301 return bars;
3302}
3303
3304/**
3305 * pci_resource_bar - get position of the BAR associated with a resource
3306 * @dev: the PCI device
3307 * @resno: the resource number
3308 * @type: the BAR type to be filled in
3309 *
3310 * Returns BAR position in config space, or 0 if the BAR is invalid.
3311 */
3312int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3313{
3314 int reg;
3315
3316 if (resno < PCI_ROM_RESOURCE) {
3317 *type = pci_bar_unknown;
3318 return PCI_BASE_ADDRESS_0 + 4 * resno;
3319 } else if (resno == PCI_ROM_RESOURCE) {
3320 *type = pci_bar_mem32;
3321 return dev->rom_base_reg;
3322 } else if (resno < PCI_BRIDGE_RESOURCES) {
3323 /* device specific resource */
3324 reg = pci_iov_resource_bar(dev, resno, type);
3325 if (reg)
3326 return reg;
3327 }
3328
3329 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3330 return 0;
3331}
3332
3333/* Some architectures require additional programming to enable VGA */
3334static arch_set_vga_state_t arch_set_vga_state;
3335
3336void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3337{
3338 arch_set_vga_state = func; /* NULL disables */
3339}
3340
3341static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3342 unsigned int command_bits, u32 flags)
3343{
3344 if (arch_set_vga_state)
3345 return arch_set_vga_state(dev, decode, command_bits,
3346 flags);
3347 return 0;
3348}
3349
3350/**
3351 * pci_set_vga_state - set VGA decode state on device and parents if requested
3352 * @dev: the PCI device
3353 * @decode: true = enable decoding, false = disable decoding
3354 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3355 * @flags: traverse ancestors and change bridges
3356 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3357 */
3358int pci_set_vga_state(struct pci_dev *dev, bool decode,
3359 unsigned int command_bits, u32 flags)
3360{
3361 struct pci_bus *bus;
3362 struct pci_dev *bridge;
3363 u16 cmd;
3364 int rc;
3365
3366 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3367
3368 /* ARCH specific VGA enables */
3369 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3370 if (rc)
3371 return rc;
3372
3373 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3374 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3375 if (decode == true)
3376 cmd |= command_bits;
3377 else
3378 cmd &= ~command_bits;
3379 pci_write_config_word(dev, PCI_COMMAND, cmd);
3380 }
3381
3382 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3383 return 0;
3384
3385 bus = dev->bus;
3386 while (bus) {
3387 bridge = bus->self;
3388 if (bridge) {
3389 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3390 &cmd);
3391 if (decode == true)
3392 cmd |= PCI_BRIDGE_CTL_VGA;
3393 else
3394 cmd &= ~PCI_BRIDGE_CTL_VGA;
3395 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3396 cmd);
3397 }
3398 bus = bus->parent;
3399 }
3400 return 0;
3401}
3402
3403#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3404static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3405static DEFINE_SPINLOCK(resource_alignment_lock);
3406
3407/**
3408 * pci_specified_resource_alignment - get resource alignment specified by user.
3409 * @dev: the PCI device to get
3410 *
3411 * RETURNS: Resource alignment if it is specified.
3412 * Zero if it is not specified.
3413 */
3414resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3415{
3416 int seg, bus, slot, func, align_order, count;
3417 resource_size_t align = 0;
3418 char *p;
3419
3420 spin_lock(&resource_alignment_lock);
3421 p = resource_alignment_param;
3422 while (*p) {
3423 count = 0;
3424 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3425 p[count] == '@') {
3426 p += count + 1;
3427 } else {
3428 align_order = -1;
3429 }
3430 if (sscanf(p, "%x:%x:%x.%x%n",
3431 &seg, &bus, &slot, &func, &count) != 4) {
3432 seg = 0;
3433 if (sscanf(p, "%x:%x.%x%n",
3434 &bus, &slot, &func, &count) != 3) {
3435 /* Invalid format */
3436 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3437 p);
3438 break;
3439 }
3440 }
3441 p += count;
3442 if (seg == pci_domain_nr(dev->bus) &&
3443 bus == dev->bus->number &&
3444 slot == PCI_SLOT(dev->devfn) &&
3445 func == PCI_FUNC(dev->devfn)) {
3446 if (align_order == -1) {
3447 align = PAGE_SIZE;
3448 } else {
3449 align = 1 << align_order;
3450 }
3451 /* Found */
3452 break;
3453 }
3454 if (*p != ';' && *p != ',') {
3455 /* End of param or invalid format */
3456 break;
3457 }
3458 p++;
3459 }
3460 spin_unlock(&resource_alignment_lock);
3461 return align;
3462}
3463
3464/**
3465 * pci_is_reassigndev - check if specified PCI is target device to reassign
3466 * @dev: the PCI device to check
3467 *
3468 * RETURNS: non-zero for PCI device is a target device to reassign,
3469 * or zero is not.
3470 */
3471int pci_is_reassigndev(struct pci_dev *dev)
3472{
3473 return (pci_specified_resource_alignment(dev) != 0);
3474}
3475
3476ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3477{
3478 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3479 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3480 spin_lock(&resource_alignment_lock);
3481 strncpy(resource_alignment_param, buf, count);
3482 resource_alignment_param[count] = '\0';
3483 spin_unlock(&resource_alignment_lock);
3484 return count;
3485}
3486
3487ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3488{
3489 size_t count;
3490 spin_lock(&resource_alignment_lock);
3491 count = snprintf(buf, size, "%s", resource_alignment_param);
3492 spin_unlock(&resource_alignment_lock);
3493 return count;
3494}
3495
3496static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3497{
3498 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3499}
3500
3501static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3502 const char *buf, size_t count)
3503{
3504 return pci_set_resource_alignment_param(buf, count);
3505}
3506
3507BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3508 pci_resource_alignment_store);
3509
3510static int __init pci_resource_alignment_sysfs_init(void)
3511{
3512 return bus_create_file(&pci_bus_type,
3513 &bus_attr_resource_alignment);
3514}
3515
3516late_initcall(pci_resource_alignment_sysfs_init);
3517
3518static void __devinit pci_no_domains(void)
3519{
3520#ifdef CONFIG_PCI_DOMAINS
3521 pci_domains_supported = 0;
3522#endif
3523}
3524
3525/**
3526 * pci_ext_cfg_enabled - can we access extended PCI config space?
3527 * @dev: The PCI device of the root bridge.
3528 *
3529 * Returns 1 if we can access PCI extended config space (offsets
3530 * greater than 0xff). This is the default implementation. Architecture
3531 * implementations can override this.
3532 */
3533int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3534{
3535 return 1;
3536}
3537
3538void __weak pci_fixup_cardbus(struct pci_bus *bus)
3539{
3540}
3541EXPORT_SYMBOL(pci_fixup_cardbus);
3542
3543static int __init pci_setup(char *str)
3544{
3545 while (str) {
3546 char *k = strchr(str, ',');
3547 if (k)
3548 *k++ = 0;
3549 if (*str && (str = pcibios_setup(str)) && *str) {
3550 if (!strcmp(str, "nomsi")) {
3551 pci_no_msi();
3552 } else if (!strcmp(str, "noaer")) {
3553 pci_no_aer();
3554 } else if (!strncmp(str, "realloc", 7)) {
3555 pci_realloc();
3556 } else if (!strcmp(str, "nodomains")) {
3557 pci_no_domains();
3558 } else if (!strncmp(str, "cbiosize=", 9)) {
3559 pci_cardbus_io_size = memparse(str + 9, &str);
3560 } else if (!strncmp(str, "cbmemsize=", 10)) {
3561 pci_cardbus_mem_size = memparse(str + 10, &str);
3562 } else if (!strncmp(str, "resource_alignment=", 19)) {
3563 pci_set_resource_alignment_param(str + 19,
3564 strlen(str + 19));
3565 } else if (!strncmp(str, "ecrc=", 5)) {
3566 pcie_ecrc_get_policy(str + 5);
3567 } else if (!strncmp(str, "hpiosize=", 9)) {
3568 pci_hotplug_io_size = memparse(str + 9, &str);
3569 } else if (!strncmp(str, "hpmemsize=", 10)) {
3570 pci_hotplug_mem_size = memparse(str + 10, &str);
3571 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3572 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3573 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3574 pcie_bus_config = PCIE_BUS_SAFE;
3575 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3576 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3577 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3578 pcie_bus_config = PCIE_BUS_PEER2PEER;
3579 } else {
3580 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3581 str);
3582 }
3583 }
3584 str = k;
3585 }
3586 return 0;
3587}
3588early_param("pci", pci_setup);
3589
3590EXPORT_SYMBOL(pci_reenable_device);
3591EXPORT_SYMBOL(pci_enable_device_io);
3592EXPORT_SYMBOL(pci_enable_device_mem);
3593EXPORT_SYMBOL(pci_enable_device);
3594EXPORT_SYMBOL(pcim_enable_device);
3595EXPORT_SYMBOL(pcim_pin_device);
3596EXPORT_SYMBOL(pci_disable_device);
3597EXPORT_SYMBOL(pci_find_capability);
3598EXPORT_SYMBOL(pci_bus_find_capability);
3599EXPORT_SYMBOL(pci_release_regions);
3600EXPORT_SYMBOL(pci_request_regions);
3601EXPORT_SYMBOL(pci_request_regions_exclusive);
3602EXPORT_SYMBOL(pci_release_region);
3603EXPORT_SYMBOL(pci_request_region);
3604EXPORT_SYMBOL(pci_request_region_exclusive);
3605EXPORT_SYMBOL(pci_release_selected_regions);
3606EXPORT_SYMBOL(pci_request_selected_regions);
3607EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3608EXPORT_SYMBOL(pci_set_master);
3609EXPORT_SYMBOL(pci_clear_master);
3610EXPORT_SYMBOL(pci_set_mwi);
3611EXPORT_SYMBOL(pci_try_set_mwi);
3612EXPORT_SYMBOL(pci_clear_mwi);
3613EXPORT_SYMBOL_GPL(pci_intx);
3614EXPORT_SYMBOL(pci_assign_resource);
3615EXPORT_SYMBOL(pci_find_parent_resource);
3616EXPORT_SYMBOL(pci_select_bars);
3617
3618EXPORT_SYMBOL(pci_set_power_state);
3619EXPORT_SYMBOL(pci_save_state);
3620EXPORT_SYMBOL(pci_restore_state);
3621EXPORT_SYMBOL(pci_pme_capable);
3622EXPORT_SYMBOL(pci_pme_active);
3623EXPORT_SYMBOL(pci_wake_from_d3);
3624EXPORT_SYMBOL(pci_target_state);
3625EXPORT_SYMBOL(pci_prepare_to_sleep);
3626EXPORT_SYMBOL(pci_back_from_sleep);
3627EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);