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1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
10 * Handle hardware traps and faults.
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/context_tracking.h>
16#include <linux/interrupt.h>
17#include <linux/kallsyms.h>
18#include <linux/spinlock.h>
19#include <linux/kprobes.h>
20#include <linux/uaccess.h>
21#include <linux/kdebug.h>
22#include <linux/kgdb.h>
23#include <linux/kernel.h>
24#include <linux/export.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/string.h>
28#include <linux/delay.h>
29#include <linux/errno.h>
30#include <linux/kexec.h>
31#include <linux/sched.h>
32#include <linux/sched/task_stack.h>
33#include <linux/timer.h>
34#include <linux/init.h>
35#include <linux/bug.h>
36#include <linux/nmi.h>
37#include <linux/mm.h>
38#include <linux/smp.h>
39#include <linux/io.h>
40
41#if defined(CONFIG_EDAC)
42#include <linux/edac.h>
43#endif
44
45#include <asm/stacktrace.h>
46#include <asm/processor.h>
47#include <asm/debugreg.h>
48#include <linux/atomic.h>
49#include <asm/text-patching.h>
50#include <asm/ftrace.h>
51#include <asm/traps.h>
52#include <asm/desc.h>
53#include <asm/fpu/internal.h>
54#include <asm/cpu_entry_area.h>
55#include <asm/mce.h>
56#include <asm/fixmap.h>
57#include <asm/mach_traps.h>
58#include <asm/alternative.h>
59#include <asm/fpu/xstate.h>
60#include <asm/trace/mpx.h>
61#include <asm/mpx.h>
62#include <asm/vm86.h>
63#include <asm/umip.h>
64
65#ifdef CONFIG_X86_64
66#include <asm/x86_init.h>
67#include <asm/pgalloc.h>
68#include <asm/proto.h>
69#else
70#include <asm/processor-flags.h>
71#include <asm/setup.h>
72#include <asm/proto.h>
73#endif
74
75DECLARE_BITMAP(system_vectors, NR_VECTORS);
76
77static inline void cond_local_irq_enable(struct pt_regs *regs)
78{
79 if (regs->flags & X86_EFLAGS_IF)
80 local_irq_enable();
81}
82
83static inline void cond_local_irq_disable(struct pt_regs *regs)
84{
85 if (regs->flags & X86_EFLAGS_IF)
86 local_irq_disable();
87}
88
89/*
90 * In IST context, we explicitly disable preemption. This serves two
91 * purposes: it makes it much less likely that we would accidentally
92 * schedule in IST context and it will force a warning if we somehow
93 * manage to schedule by accident.
94 */
95void ist_enter(struct pt_regs *regs)
96{
97 if (user_mode(regs)) {
98 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
99 } else {
100 /*
101 * We might have interrupted pretty much anything. In
102 * fact, if we're a machine check, we can even interrupt
103 * NMI processing. We don't want in_nmi() to return true,
104 * but we need to notify RCU.
105 */
106 rcu_nmi_enter();
107 }
108
109 preempt_disable();
110
111 /* This code is a bit fragile. Test it. */
112 RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work");
113}
114NOKPROBE_SYMBOL(ist_enter);
115
116void ist_exit(struct pt_regs *regs)
117{
118 preempt_enable_no_resched();
119
120 if (!user_mode(regs))
121 rcu_nmi_exit();
122}
123
124/**
125 * ist_begin_non_atomic() - begin a non-atomic section in an IST exception
126 * @regs: regs passed to the IST exception handler
127 *
128 * IST exception handlers normally cannot schedule. As a special
129 * exception, if the exception interrupted userspace code (i.e.
130 * user_mode(regs) would return true) and the exception was not
131 * a double fault, it can be safe to schedule. ist_begin_non_atomic()
132 * begins a non-atomic section within an ist_enter()/ist_exit() region.
133 * Callers are responsible for enabling interrupts themselves inside
134 * the non-atomic section, and callers must call ist_end_non_atomic()
135 * before ist_exit().
136 */
137void ist_begin_non_atomic(struct pt_regs *regs)
138{
139 BUG_ON(!user_mode(regs));
140
141 /*
142 * Sanity check: we need to be on the normal thread stack. This
143 * will catch asm bugs and any attempt to use ist_preempt_enable
144 * from double_fault.
145 */
146 BUG_ON(!on_thread_stack());
147
148 preempt_enable_no_resched();
149}
150
151/**
152 * ist_end_non_atomic() - begin a non-atomic section in an IST exception
153 *
154 * Ends a non-atomic section started with ist_begin_non_atomic().
155 */
156void ist_end_non_atomic(void)
157{
158 preempt_disable();
159}
160
161int is_valid_bugaddr(unsigned long addr)
162{
163 unsigned short ud;
164
165 if (addr < TASK_SIZE_MAX)
166 return 0;
167
168 if (probe_kernel_address((unsigned short *)addr, ud))
169 return 0;
170
171 return ud == INSN_UD0 || ud == INSN_UD2;
172}
173
174int fixup_bug(struct pt_regs *regs, int trapnr)
175{
176 if (trapnr != X86_TRAP_UD)
177 return 0;
178
179 switch (report_bug(regs->ip, regs)) {
180 case BUG_TRAP_TYPE_NONE:
181 case BUG_TRAP_TYPE_BUG:
182 break;
183
184 case BUG_TRAP_TYPE_WARN:
185 regs->ip += LEN_UD2;
186 return 1;
187 }
188
189 return 0;
190}
191
192static nokprobe_inline int
193do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
194 struct pt_regs *regs, long error_code)
195{
196 if (v8086_mode(regs)) {
197 /*
198 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
199 * On nmi (interrupt 2), do_trap should not be called.
200 */
201 if (trapnr < X86_TRAP_UD) {
202 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
203 error_code, trapnr))
204 return 0;
205 }
206 } else if (!user_mode(regs)) {
207 if (fixup_exception(regs, trapnr, error_code, 0))
208 return 0;
209
210 tsk->thread.error_code = error_code;
211 tsk->thread.trap_nr = trapnr;
212 die(str, regs, error_code);
213 }
214
215 /*
216 * We want error_code and trap_nr set for userspace faults and
217 * kernelspace faults which result in die(), but not
218 * kernelspace faults which are fixed up. die() gives the
219 * process no chance to handle the signal and notice the
220 * kernel fault information, so that won't result in polluting
221 * the information about previously queued, but not yet
222 * delivered, faults. See also do_general_protection below.
223 */
224 tsk->thread.error_code = error_code;
225 tsk->thread.trap_nr = trapnr;
226
227 return -1;
228}
229
230static void show_signal(struct task_struct *tsk, int signr,
231 const char *type, const char *desc,
232 struct pt_regs *regs, long error_code)
233{
234 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
235 printk_ratelimit()) {
236 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
237 tsk->comm, task_pid_nr(tsk), type, desc,
238 regs->ip, regs->sp, error_code);
239 print_vma_addr(KERN_CONT " in ", regs->ip);
240 pr_cont("\n");
241 }
242}
243
244static void
245do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
246 long error_code, int sicode, void __user *addr)
247{
248 struct task_struct *tsk = current;
249
250
251 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
252 return;
253
254 show_signal(tsk, signr, "trap ", str, regs, error_code);
255
256 if (!sicode)
257 force_sig(signr);
258 else
259 force_sig_fault(signr, sicode, addr);
260}
261NOKPROBE_SYMBOL(do_trap);
262
263static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
264 unsigned long trapnr, int signr, int sicode, void __user *addr)
265{
266 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
267
268 /*
269 * WARN*()s end up here; fix them up before we call the
270 * notifier chain.
271 */
272 if (!user_mode(regs) && fixup_bug(regs, trapnr))
273 return;
274
275 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
276 NOTIFY_STOP) {
277 cond_local_irq_enable(regs);
278 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
279 }
280}
281
282#define IP ((void __user *)uprobe_get_trap_addr(regs))
283#define DO_ERROR(trapnr, signr, sicode, addr, str, name) \
284dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
285{ \
286 do_error_trap(regs, error_code, str, trapnr, signr, sicode, addr); \
287}
288
289DO_ERROR(X86_TRAP_DE, SIGFPE, FPE_INTDIV, IP, "divide error", divide_error)
290DO_ERROR(X86_TRAP_OF, SIGSEGV, 0, NULL, "overflow", overflow)
291DO_ERROR(X86_TRAP_UD, SIGILL, ILL_ILLOPN, IP, "invalid opcode", invalid_op)
292DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, 0, NULL, "coprocessor segment overrun", coprocessor_segment_overrun)
293DO_ERROR(X86_TRAP_TS, SIGSEGV, 0, NULL, "invalid TSS", invalid_TSS)
294DO_ERROR(X86_TRAP_NP, SIGBUS, 0, NULL, "segment not present", segment_not_present)
295DO_ERROR(X86_TRAP_SS, SIGBUS, 0, NULL, "stack segment", stack_segment)
296DO_ERROR(X86_TRAP_AC, SIGBUS, BUS_ADRALN, NULL, "alignment check", alignment_check)
297#undef IP
298
299#ifdef CONFIG_VMAP_STACK
300__visible void __noreturn handle_stack_overflow(const char *message,
301 struct pt_regs *regs,
302 unsigned long fault_address)
303{
304 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
305 (void *)fault_address, current->stack,
306 (char *)current->stack + THREAD_SIZE - 1);
307 die(message, regs, 0);
308
309 /* Be absolutely certain we don't return. */
310 panic("%s", message);
311}
312#endif
313
314#ifdef CONFIG_X86_64
315/* Runs on IST stack */
316dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code, unsigned long cr2)
317{
318 static const char str[] = "double fault";
319 struct task_struct *tsk = current;
320
321#ifdef CONFIG_X86_ESPFIX64
322 extern unsigned char native_irq_return_iret[];
323
324 /*
325 * If IRET takes a non-IST fault on the espfix64 stack, then we
326 * end up promoting it to a doublefault. In that case, take
327 * advantage of the fact that we're not using the normal (TSS.sp0)
328 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
329 * and then modify our own IRET frame so that, when we return,
330 * we land directly at the #GP(0) vector with the stack already
331 * set up according to its expectations.
332 *
333 * The net result is that our #GP handler will think that we
334 * entered from usermode with the bad user context.
335 *
336 * No need for ist_enter here because we don't use RCU.
337 */
338 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
339 regs->cs == __KERNEL_CS &&
340 regs->ip == (unsigned long)native_irq_return_iret)
341 {
342 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
343
344 /*
345 * regs->sp points to the failing IRET frame on the
346 * ESPFIX64 stack. Copy it to the entry stack. This fills
347 * in gpregs->ss through gpregs->ip.
348 *
349 */
350 memmove(&gpregs->ip, (void *)regs->sp, 5*8);
351 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
352
353 /*
354 * Adjust our frame so that we return straight to the #GP
355 * vector with the expected RSP value. This is safe because
356 * we won't enable interupts or schedule before we invoke
357 * general_protection, so nothing will clobber the stack
358 * frame we just set up.
359 *
360 * We will enter general_protection with kernel GSBASE,
361 * which is what the stub expects, given that the faulting
362 * RIP will be the IRET instruction.
363 */
364 regs->ip = (unsigned long)general_protection;
365 regs->sp = (unsigned long)&gpregs->orig_ax;
366
367 return;
368 }
369#endif
370
371 ist_enter(regs);
372 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
373
374 tsk->thread.error_code = error_code;
375 tsk->thread.trap_nr = X86_TRAP_DF;
376
377#ifdef CONFIG_VMAP_STACK
378 /*
379 * If we overflow the stack into a guard page, the CPU will fail
380 * to deliver #PF and will send #DF instead. Similarly, if we
381 * take any non-IST exception while too close to the bottom of
382 * the stack, the processor will get a page fault while
383 * delivering the exception and will generate a double fault.
384 *
385 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
386 * Page-Fault Exception (#PF):
387 *
388 * Processors update CR2 whenever a page fault is detected. If a
389 * second page fault occurs while an earlier page fault is being
390 * delivered, the faulting linear address of the second fault will
391 * overwrite the contents of CR2 (replacing the previous
392 * address). These updates to CR2 occur even if the page fault
393 * results in a double fault or occurs during the delivery of a
394 * double fault.
395 *
396 * The logic below has a small possibility of incorrectly diagnosing
397 * some errors as stack overflows. For example, if the IDT or GDT
398 * gets corrupted such that #GP delivery fails due to a bad descriptor
399 * causing #GP and we hit this condition while CR2 coincidentally
400 * points to the stack guard page, we'll think we overflowed the
401 * stack. Given that we're going to panic one way or another
402 * if this happens, this isn't necessarily worth fixing.
403 *
404 * If necessary, we could improve the test by only diagnosing
405 * a stack overflow if the saved RSP points within 47 bytes of
406 * the bottom of the stack: if RSP == tsk_stack + 48 and we
407 * take an exception, the stack is already aligned and there
408 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
409 * possible error code, so a stack overflow would *not* double
410 * fault. With any less space left, exception delivery could
411 * fail, and, as a practical matter, we've overflowed the
412 * stack even if the actual trigger for the double fault was
413 * something else.
414 */
415 if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE)
416 handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2);
417#endif
418
419#ifdef CONFIG_DOUBLEFAULT
420 df_debug(regs, error_code);
421#endif
422 /*
423 * This is always a kernel trap and never fixable (and thus must
424 * never return).
425 */
426 for (;;)
427 die(str, regs, error_code);
428}
429#endif
430
431dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
432{
433 const struct mpx_bndcsr *bndcsr;
434
435 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
436 if (notify_die(DIE_TRAP, "bounds", regs, error_code,
437 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
438 return;
439 cond_local_irq_enable(regs);
440
441 if (!user_mode(regs))
442 die("bounds", regs, error_code);
443
444 if (!cpu_feature_enabled(X86_FEATURE_MPX)) {
445 /* The exception is not from Intel MPX */
446 goto exit_trap;
447 }
448
449 /*
450 * We need to look at BNDSTATUS to resolve this exception.
451 * A NULL here might mean that it is in its 'init state',
452 * which is all zeros which indicates MPX was not
453 * responsible for the exception.
454 */
455 bndcsr = get_xsave_field_ptr(XFEATURE_BNDCSR);
456 if (!bndcsr)
457 goto exit_trap;
458
459 trace_bounds_exception_mpx(bndcsr);
460 /*
461 * The error code field of the BNDSTATUS register communicates status
462 * information of a bound range exception #BR or operation involving
463 * bound directory.
464 */
465 switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) {
466 case 2: /* Bound directory has invalid entry. */
467 if (mpx_handle_bd_fault())
468 goto exit_trap;
469 break; /* Success, it was handled */
470 case 1: /* Bound violation. */
471 {
472 struct task_struct *tsk = current;
473 struct mpx_fault_info mpx;
474
475 if (mpx_fault_info(&mpx, regs)) {
476 /*
477 * We failed to decode the MPX instruction. Act as if
478 * the exception was not caused by MPX.
479 */
480 goto exit_trap;
481 }
482 /*
483 * Success, we decoded the instruction and retrieved
484 * an 'mpx' containing the address being accessed
485 * which caused the exception. This information
486 * allows and application to possibly handle the
487 * #BR exception itself.
488 */
489 if (!do_trap_no_signal(tsk, X86_TRAP_BR, "bounds", regs,
490 error_code))
491 break;
492
493 show_signal(tsk, SIGSEGV, "trap ", "bounds", regs, error_code);
494
495 force_sig_bnderr(mpx.addr, mpx.lower, mpx.upper);
496 break;
497 }
498 case 0: /* No exception caused by Intel MPX operations. */
499 goto exit_trap;
500 default:
501 die("bounds", regs, error_code);
502 }
503
504 return;
505
506exit_trap:
507 /*
508 * This path out is for all the cases where we could not
509 * handle the exception in some way (like allocating a
510 * table or telling userspace about it. We will also end
511 * up here if the kernel has MPX turned off at compile
512 * time..
513 */
514 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, 0, NULL);
515}
516
517dotraplinkage void
518do_general_protection(struct pt_regs *regs, long error_code)
519{
520 const char *desc = "general protection fault";
521 struct task_struct *tsk;
522
523 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
524 cond_local_irq_enable(regs);
525
526 if (static_cpu_has(X86_FEATURE_UMIP)) {
527 if (user_mode(regs) && fixup_umip_exception(regs))
528 return;
529 }
530
531 if (v8086_mode(regs)) {
532 local_irq_enable();
533 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
534 return;
535 }
536
537 tsk = current;
538 if (!user_mode(regs)) {
539 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
540 return;
541
542 tsk->thread.error_code = error_code;
543 tsk->thread.trap_nr = X86_TRAP_GP;
544
545 /*
546 * To be potentially processing a kprobe fault and to
547 * trust the result from kprobe_running(), we have to
548 * be non-preemptible.
549 */
550 if (!preemptible() && kprobe_running() &&
551 kprobe_fault_handler(regs, X86_TRAP_GP))
552 return;
553
554 if (notify_die(DIE_GPF, desc, regs, error_code,
555 X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP)
556 die(desc, regs, error_code);
557 return;
558 }
559
560 tsk->thread.error_code = error_code;
561 tsk->thread.trap_nr = X86_TRAP_GP;
562
563 show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
564
565 force_sig(SIGSEGV);
566}
567NOKPROBE_SYMBOL(do_general_protection);
568
569dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
570{
571#ifdef CONFIG_DYNAMIC_FTRACE
572 /*
573 * ftrace must be first, everything else may cause a recursive crash.
574 * See note by declaration of modifying_ftrace_code in ftrace.c
575 */
576 if (unlikely(atomic_read(&modifying_ftrace_code)) &&
577 ftrace_int3_handler(regs))
578 return;
579#endif
580 if (poke_int3_handler(regs))
581 return;
582
583 /*
584 * Use ist_enter despite the fact that we don't use an IST stack.
585 * We can be called from a kprobe in non-CONTEXT_KERNEL kernel
586 * mode or even during context tracking state changes.
587 *
588 * This means that we can't schedule. That's okay.
589 */
590 ist_enter(regs);
591 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
592#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
593 if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
594 SIGTRAP) == NOTIFY_STOP)
595 goto exit;
596#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
597
598#ifdef CONFIG_KPROBES
599 if (kprobe_int3_handler(regs))
600 goto exit;
601#endif
602
603 if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
604 SIGTRAP) == NOTIFY_STOP)
605 goto exit;
606
607 cond_local_irq_enable(regs);
608 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, 0, NULL);
609 cond_local_irq_disable(regs);
610
611exit:
612 ist_exit(regs);
613}
614NOKPROBE_SYMBOL(do_int3);
615
616#ifdef CONFIG_X86_64
617/*
618 * Help handler running on a per-cpu (IST or entry trampoline) stack
619 * to switch to the normal thread stack if the interrupted code was in
620 * user mode. The actual stack switch is done in entry_64.S
621 */
622asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs)
623{
624 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
625 if (regs != eregs)
626 *regs = *eregs;
627 return regs;
628}
629NOKPROBE_SYMBOL(sync_regs);
630
631struct bad_iret_stack {
632 void *error_entry_ret;
633 struct pt_regs regs;
634};
635
636asmlinkage __visible notrace
637struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
638{
639 /*
640 * This is called from entry_64.S early in handling a fault
641 * caused by a bad iret to user mode. To handle the fault
642 * correctly, we want to move our stack frame to where it would
643 * be had we entered directly on the entry stack (rather than
644 * just below the IRET frame) and we want to pretend that the
645 * exception came from the IRET target.
646 */
647 struct bad_iret_stack *new_stack =
648 (struct bad_iret_stack *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
649
650 /* Copy the IRET target to the new stack. */
651 memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
652
653 /* Copy the remainder of the stack from the current stack. */
654 memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
655
656 BUG_ON(!user_mode(&new_stack->regs));
657 return new_stack;
658}
659NOKPROBE_SYMBOL(fixup_bad_iret);
660#endif
661
662static bool is_sysenter_singlestep(struct pt_regs *regs)
663{
664 /*
665 * We don't try for precision here. If we're anywhere in the region of
666 * code that can be single-stepped in the SYSENTER entry path, then
667 * assume that this is a useless single-step trap due to SYSENTER
668 * being invoked with TF set. (We don't know in advance exactly
669 * which instructions will be hit because BTF could plausibly
670 * be set.)
671 */
672#ifdef CONFIG_X86_32
673 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
674 (unsigned long)__end_SYSENTER_singlestep_region -
675 (unsigned long)__begin_SYSENTER_singlestep_region;
676#elif defined(CONFIG_IA32_EMULATION)
677 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
678 (unsigned long)__end_entry_SYSENTER_compat -
679 (unsigned long)entry_SYSENTER_compat;
680#else
681 return false;
682#endif
683}
684
685/*
686 * Our handling of the processor debug registers is non-trivial.
687 * We do not clear them on entry and exit from the kernel. Therefore
688 * it is possible to get a watchpoint trap here from inside the kernel.
689 * However, the code in ./ptrace.c has ensured that the user can
690 * only set watchpoints on userspace addresses. Therefore the in-kernel
691 * watchpoint trap can only occur in code which is reading/writing
692 * from user space. Such code must not hold kernel locks (since it
693 * can equally take a page fault), therefore it is safe to call
694 * force_sig_info even though that claims and releases locks.
695 *
696 * Code in ./signal.c ensures that the debug control register
697 * is restored before we deliver any signal, and therefore that
698 * user code runs with the correct debug control register even though
699 * we clear it here.
700 *
701 * Being careful here means that we don't have to be as careful in a
702 * lot of more complicated places (task switching can be a bit lazy
703 * about restoring all the debug state, and ptrace doesn't have to
704 * find every occurrence of the TF bit that could be saved away even
705 * by user code)
706 *
707 * May run on IST stack.
708 */
709dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
710{
711 struct task_struct *tsk = current;
712 int user_icebp = 0;
713 unsigned long dr6;
714 int si_code;
715
716 ist_enter(regs);
717
718 get_debugreg(dr6, 6);
719 /*
720 * The Intel SDM says:
721 *
722 * Certain debug exceptions may clear bits 0-3. The remaining
723 * contents of the DR6 register are never cleared by the
724 * processor. To avoid confusion in identifying debug
725 * exceptions, debug handlers should clear the register before
726 * returning to the interrupted task.
727 *
728 * Keep it simple: clear DR6 immediately.
729 */
730 set_debugreg(0, 6);
731
732 /* Filter out all the reserved bits which are preset to 1 */
733 dr6 &= ~DR6_RESERVED;
734
735 /*
736 * The SDM says "The processor clears the BTF flag when it
737 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
738 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
739 */
740 clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
741
742 if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) &&
743 is_sysenter_singlestep(regs))) {
744 dr6 &= ~DR_STEP;
745 if (!dr6)
746 goto exit;
747 /*
748 * else we might have gotten a single-step trap and hit a
749 * watchpoint at the same time, in which case we should fall
750 * through and handle the watchpoint.
751 */
752 }
753
754 /*
755 * If dr6 has no reason to give us about the origin of this trap,
756 * then it's very likely the result of an icebp/int01 trap.
757 * User wants a sigtrap for that.
758 */
759 if (!dr6 && user_mode(regs))
760 user_icebp = 1;
761
762 /* Store the virtualized DR6 value */
763 tsk->thread.debugreg6 = dr6;
764
765#ifdef CONFIG_KPROBES
766 if (kprobe_debug_handler(regs))
767 goto exit;
768#endif
769
770 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
771 SIGTRAP) == NOTIFY_STOP)
772 goto exit;
773
774 /*
775 * Let others (NMI) know that the debug stack is in use
776 * as we may switch to the interrupt stack.
777 */
778 debug_stack_usage_inc();
779
780 /* It's safe to allow irq's after DR6 has been saved */
781 cond_local_irq_enable(regs);
782
783 if (v8086_mode(regs)) {
784 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
785 X86_TRAP_DB);
786 cond_local_irq_disable(regs);
787 debug_stack_usage_dec();
788 goto exit;
789 }
790
791 if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
792 /*
793 * Historical junk that used to handle SYSENTER single-stepping.
794 * This should be unreachable now. If we survive for a while
795 * without anyone hitting this warning, we'll turn this into
796 * an oops.
797 */
798 tsk->thread.debugreg6 &= ~DR_STEP;
799 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
800 regs->flags &= ~X86_EFLAGS_TF;
801 }
802 si_code = get_si_code(tsk->thread.debugreg6);
803 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
804 send_sigtrap(regs, error_code, si_code);
805 cond_local_irq_disable(regs);
806 debug_stack_usage_dec();
807
808exit:
809 ist_exit(regs);
810}
811NOKPROBE_SYMBOL(do_debug);
812
813/*
814 * Note that we play around with the 'TS' bit in an attempt to get
815 * the correct behaviour even in the presence of the asynchronous
816 * IRQ13 behaviour
817 */
818static void math_error(struct pt_regs *regs, int error_code, int trapnr)
819{
820 struct task_struct *task = current;
821 struct fpu *fpu = &task->thread.fpu;
822 int si_code;
823 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
824 "simd exception";
825
826 cond_local_irq_enable(regs);
827
828 if (!user_mode(regs)) {
829 if (fixup_exception(regs, trapnr, error_code, 0))
830 return;
831
832 task->thread.error_code = error_code;
833 task->thread.trap_nr = trapnr;
834
835 if (notify_die(DIE_TRAP, str, regs, error_code,
836 trapnr, SIGFPE) != NOTIFY_STOP)
837 die(str, regs, error_code);
838 return;
839 }
840
841 /*
842 * Save the info for the exception handler and clear the error.
843 */
844 fpu__save(fpu);
845
846 task->thread.trap_nr = trapnr;
847 task->thread.error_code = error_code;
848
849 si_code = fpu__exception_code(fpu, trapnr);
850 /* Retry when we get spurious exceptions: */
851 if (!si_code)
852 return;
853
854 force_sig_fault(SIGFPE, si_code,
855 (void __user *)uprobe_get_trap_addr(regs));
856}
857
858dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
859{
860 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
861 math_error(regs, error_code, X86_TRAP_MF);
862}
863
864dotraplinkage void
865do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
866{
867 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
868 math_error(regs, error_code, X86_TRAP_XF);
869}
870
871dotraplinkage void
872do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
873{
874 cond_local_irq_enable(regs);
875}
876
877dotraplinkage void
878do_device_not_available(struct pt_regs *regs, long error_code)
879{
880 unsigned long cr0 = read_cr0();
881
882 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
883
884#ifdef CONFIG_MATH_EMULATION
885 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
886 struct math_emu_info info = { };
887
888 cond_local_irq_enable(regs);
889
890 info.regs = regs;
891 math_emulate(&info);
892 return;
893 }
894#endif
895
896 /* This should not happen. */
897 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
898 /* Try to fix it up and carry on. */
899 write_cr0(cr0 & ~X86_CR0_TS);
900 } else {
901 /*
902 * Something terrible happened, and we're better off trying
903 * to kill the task than getting stuck in a never-ending
904 * loop of #NM faults.
905 */
906 die("unexpected #NM exception", regs, error_code);
907 }
908}
909NOKPROBE_SYMBOL(do_device_not_available);
910
911#ifdef CONFIG_X86_32
912dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
913{
914 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
915 local_irq_enable();
916
917 if (notify_die(DIE_TRAP, "iret exception", regs, error_code,
918 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
919 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
920 ILL_BADSTK, (void __user *)NULL);
921 }
922}
923#endif
924
925void __init trap_init(void)
926{
927 /* Init cpu_entry_area before IST entries are set up */
928 setup_cpu_entry_areas();
929
930 idt_setup_traps();
931
932 /*
933 * Set the IDT descriptor to a fixed read-only location, so that the
934 * "sidt" instruction will not leak the location of the kernel, and
935 * to defend the IDT against arbitrary memory write vulnerabilities.
936 * It will be reloaded in cpu_init() */
937 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
938 PAGE_KERNEL_RO);
939 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
940
941 /*
942 * Should be a barrier for any external CPU state:
943 */
944 cpu_init();
945
946 idt_setup_ist_traps();
947
948 x86_init.irqs.trap_init();
949
950 idt_setup_debugidt_traps();
951}
1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
10 * Handle hardware traps and faults.
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/context_tracking.h>
16#include <linux/interrupt.h>
17#include <linux/kallsyms.h>
18#include <linux/spinlock.h>
19#include <linux/kprobes.h>
20#include <linux/uaccess.h>
21#include <linux/kdebug.h>
22#include <linux/kgdb.h>
23#include <linux/kernel.h>
24#include <linux/export.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/string.h>
28#include <linux/delay.h>
29#include <linux/errno.h>
30#include <linux/kexec.h>
31#include <linux/sched.h>
32#include <linux/sched/task_stack.h>
33#include <linux/timer.h>
34#include <linux/init.h>
35#include <linux/bug.h>
36#include <linux/nmi.h>
37#include <linux/mm.h>
38#include <linux/smp.h>
39#include <linux/io.h>
40#include <linux/hardirq.h>
41#include <linux/atomic.h>
42
43#include <asm/stacktrace.h>
44#include <asm/processor.h>
45#include <asm/debugreg.h>
46#include <asm/text-patching.h>
47#include <asm/ftrace.h>
48#include <asm/traps.h>
49#include <asm/desc.h>
50#include <asm/fpu/internal.h>
51#include <asm/cpu.h>
52#include <asm/cpu_entry_area.h>
53#include <asm/mce.h>
54#include <asm/fixmap.h>
55#include <asm/mach_traps.h>
56#include <asm/alternative.h>
57#include <asm/fpu/xstate.h>
58#include <asm/vm86.h>
59#include <asm/umip.h>
60#include <asm/insn.h>
61#include <asm/insn-eval.h>
62
63#ifdef CONFIG_X86_64
64#include <asm/x86_init.h>
65#include <asm/proto.h>
66#else
67#include <asm/processor-flags.h>
68#include <asm/setup.h>
69#include <asm/proto.h>
70#endif
71
72DECLARE_BITMAP(system_vectors, NR_VECTORS);
73
74static inline void cond_local_irq_enable(struct pt_regs *regs)
75{
76 if (regs->flags & X86_EFLAGS_IF)
77 local_irq_enable();
78}
79
80static inline void cond_local_irq_disable(struct pt_regs *regs)
81{
82 if (regs->flags & X86_EFLAGS_IF)
83 local_irq_disable();
84}
85
86__always_inline int is_valid_bugaddr(unsigned long addr)
87{
88 if (addr < TASK_SIZE_MAX)
89 return 0;
90
91 /*
92 * We got #UD, if the text isn't readable we'd have gotten
93 * a different exception.
94 */
95 return *(unsigned short *)addr == INSN_UD2;
96}
97
98static nokprobe_inline int
99do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
100 struct pt_regs *regs, long error_code)
101{
102 if (v8086_mode(regs)) {
103 /*
104 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
105 * On nmi (interrupt 2), do_trap should not be called.
106 */
107 if (trapnr < X86_TRAP_UD) {
108 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
109 error_code, trapnr))
110 return 0;
111 }
112 } else if (!user_mode(regs)) {
113 if (fixup_exception(regs, trapnr, error_code, 0))
114 return 0;
115
116 tsk->thread.error_code = error_code;
117 tsk->thread.trap_nr = trapnr;
118 die(str, regs, error_code);
119 }
120
121 /*
122 * We want error_code and trap_nr set for userspace faults and
123 * kernelspace faults which result in die(), but not
124 * kernelspace faults which are fixed up. die() gives the
125 * process no chance to handle the signal and notice the
126 * kernel fault information, so that won't result in polluting
127 * the information about previously queued, but not yet
128 * delivered, faults. See also exc_general_protection below.
129 */
130 tsk->thread.error_code = error_code;
131 tsk->thread.trap_nr = trapnr;
132
133 return -1;
134}
135
136static void show_signal(struct task_struct *tsk, int signr,
137 const char *type, const char *desc,
138 struct pt_regs *regs, long error_code)
139{
140 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
141 printk_ratelimit()) {
142 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
143 tsk->comm, task_pid_nr(tsk), type, desc,
144 regs->ip, regs->sp, error_code);
145 print_vma_addr(KERN_CONT " in ", regs->ip);
146 pr_cont("\n");
147 }
148}
149
150static void
151do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
152 long error_code, int sicode, void __user *addr)
153{
154 struct task_struct *tsk = current;
155
156 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
157 return;
158
159 show_signal(tsk, signr, "trap ", str, regs, error_code);
160
161 if (!sicode)
162 force_sig(signr);
163 else
164 force_sig_fault(signr, sicode, addr);
165}
166NOKPROBE_SYMBOL(do_trap);
167
168static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
169 unsigned long trapnr, int signr, int sicode, void __user *addr)
170{
171 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
172
173 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
174 NOTIFY_STOP) {
175 cond_local_irq_enable(regs);
176 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
177 cond_local_irq_disable(regs);
178 }
179}
180
181/*
182 * Posix requires to provide the address of the faulting instruction for
183 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
184 *
185 * This address is usually regs->ip, but when an uprobe moved the code out
186 * of line then regs->ip points to the XOL code which would confuse
187 * anything which analyzes the fault address vs. the unmodified binary. If
188 * a trap happened in XOL code then uprobe maps regs->ip back to the
189 * original instruction address.
190 */
191static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
192{
193 return (void __user *)uprobe_get_trap_addr(regs);
194}
195
196DEFINE_IDTENTRY(exc_divide_error)
197{
198 do_error_trap(regs, 0, "divide_error", X86_TRAP_DE, SIGFPE,
199 FPE_INTDIV, error_get_trap_addr(regs));
200}
201
202DEFINE_IDTENTRY(exc_overflow)
203{
204 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
205}
206
207#ifdef CONFIG_X86_F00F_BUG
208void handle_invalid_op(struct pt_regs *regs)
209#else
210static inline void handle_invalid_op(struct pt_regs *regs)
211#endif
212{
213 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
214 ILL_ILLOPN, error_get_trap_addr(regs));
215}
216
217static noinstr bool handle_bug(struct pt_regs *regs)
218{
219 bool handled = false;
220
221 if (!is_valid_bugaddr(regs->ip))
222 return handled;
223
224 /*
225 * All lies, just get the WARN/BUG out.
226 */
227 instrumentation_begin();
228 /*
229 * Since we're emulating a CALL with exceptions, restore the interrupt
230 * state to what it was at the exception site.
231 */
232 if (regs->flags & X86_EFLAGS_IF)
233 raw_local_irq_enable();
234 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN) {
235 regs->ip += LEN_UD2;
236 handled = true;
237 }
238 if (regs->flags & X86_EFLAGS_IF)
239 raw_local_irq_disable();
240 instrumentation_end();
241
242 return handled;
243}
244
245DEFINE_IDTENTRY_RAW(exc_invalid_op)
246{
247 irqentry_state_t state;
248
249 /*
250 * We use UD2 as a short encoding for 'CALL __WARN', as such
251 * handle it before exception entry to avoid recursive WARN
252 * in case exception entry is the one triggering WARNs.
253 */
254 if (!user_mode(regs) && handle_bug(regs))
255 return;
256
257 state = irqentry_enter(regs);
258 instrumentation_begin();
259 handle_invalid_op(regs);
260 instrumentation_end();
261 irqentry_exit(regs, state);
262}
263
264DEFINE_IDTENTRY(exc_coproc_segment_overrun)
265{
266 do_error_trap(regs, 0, "coprocessor segment overrun",
267 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
268}
269
270DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
271{
272 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
273 0, NULL);
274}
275
276DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
277{
278 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
279 SIGBUS, 0, NULL);
280}
281
282DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
283{
284 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
285 0, NULL);
286}
287
288DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
289{
290 char *str = "alignment check";
291
292 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
293 return;
294
295 if (!user_mode(regs))
296 die("Split lock detected\n", regs, error_code);
297
298 local_irq_enable();
299
300 if (handle_user_split_lock(regs, error_code))
301 return;
302
303 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
304 error_code, BUS_ADRALN, NULL);
305
306 local_irq_disable();
307}
308
309#ifdef CONFIG_VMAP_STACK
310__visible void __noreturn handle_stack_overflow(const char *message,
311 struct pt_regs *regs,
312 unsigned long fault_address)
313{
314 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
315 (void *)fault_address, current->stack,
316 (char *)current->stack + THREAD_SIZE - 1);
317 die(message, regs, 0);
318
319 /* Be absolutely certain we don't return. */
320 panic("%s", message);
321}
322#endif
323
324/*
325 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
326 *
327 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
328 * SDM's warnings about double faults being unrecoverable, returning works as
329 * expected. Presumably what the SDM actually means is that the CPU may get
330 * the register state wrong on entry, so returning could be a bad idea.
331 *
332 * Various CPU engineers have promised that double faults due to an IRET fault
333 * while the stack is read-only are, in fact, recoverable.
334 *
335 * On x86_32, this is entered through a task gate, and regs are synthesized
336 * from the TSS. Returning is, in principle, okay, but changes to regs will
337 * be lost. If, for some reason, we need to return to a context with modified
338 * regs, the shim code could be adjusted to synchronize the registers.
339 *
340 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
341 * to be read before doing anything else.
342 */
343DEFINE_IDTENTRY_DF(exc_double_fault)
344{
345 static const char str[] = "double fault";
346 struct task_struct *tsk = current;
347
348#ifdef CONFIG_VMAP_STACK
349 unsigned long address = read_cr2();
350#endif
351
352#ifdef CONFIG_X86_ESPFIX64
353 extern unsigned char native_irq_return_iret[];
354
355 /*
356 * If IRET takes a non-IST fault on the espfix64 stack, then we
357 * end up promoting it to a doublefault. In that case, take
358 * advantage of the fact that we're not using the normal (TSS.sp0)
359 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
360 * and then modify our own IRET frame so that, when we return,
361 * we land directly at the #GP(0) vector with the stack already
362 * set up according to its expectations.
363 *
364 * The net result is that our #GP handler will think that we
365 * entered from usermode with the bad user context.
366 *
367 * No need for nmi_enter() here because we don't use RCU.
368 */
369 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
370 regs->cs == __KERNEL_CS &&
371 regs->ip == (unsigned long)native_irq_return_iret)
372 {
373 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
374 unsigned long *p = (unsigned long *)regs->sp;
375
376 /*
377 * regs->sp points to the failing IRET frame on the
378 * ESPFIX64 stack. Copy it to the entry stack. This fills
379 * in gpregs->ss through gpregs->ip.
380 *
381 */
382 gpregs->ip = p[0];
383 gpregs->cs = p[1];
384 gpregs->flags = p[2];
385 gpregs->sp = p[3];
386 gpregs->ss = p[4];
387 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
388
389 /*
390 * Adjust our frame so that we return straight to the #GP
391 * vector with the expected RSP value. This is safe because
392 * we won't enable interupts or schedule before we invoke
393 * general_protection, so nothing will clobber the stack
394 * frame we just set up.
395 *
396 * We will enter general_protection with kernel GSBASE,
397 * which is what the stub expects, given that the faulting
398 * RIP will be the IRET instruction.
399 */
400 regs->ip = (unsigned long)asm_exc_general_protection;
401 regs->sp = (unsigned long)&gpregs->orig_ax;
402
403 return;
404 }
405#endif
406
407 idtentry_enter_nmi(regs);
408 instrumentation_begin();
409 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
410
411 tsk->thread.error_code = error_code;
412 tsk->thread.trap_nr = X86_TRAP_DF;
413
414#ifdef CONFIG_VMAP_STACK
415 /*
416 * If we overflow the stack into a guard page, the CPU will fail
417 * to deliver #PF and will send #DF instead. Similarly, if we
418 * take any non-IST exception while too close to the bottom of
419 * the stack, the processor will get a page fault while
420 * delivering the exception and will generate a double fault.
421 *
422 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
423 * Page-Fault Exception (#PF):
424 *
425 * Processors update CR2 whenever a page fault is detected. If a
426 * second page fault occurs while an earlier page fault is being
427 * delivered, the faulting linear address of the second fault will
428 * overwrite the contents of CR2 (replacing the previous
429 * address). These updates to CR2 occur even if the page fault
430 * results in a double fault or occurs during the delivery of a
431 * double fault.
432 *
433 * The logic below has a small possibility of incorrectly diagnosing
434 * some errors as stack overflows. For example, if the IDT or GDT
435 * gets corrupted such that #GP delivery fails due to a bad descriptor
436 * causing #GP and we hit this condition while CR2 coincidentally
437 * points to the stack guard page, we'll think we overflowed the
438 * stack. Given that we're going to panic one way or another
439 * if this happens, this isn't necessarily worth fixing.
440 *
441 * If necessary, we could improve the test by only diagnosing
442 * a stack overflow if the saved RSP points within 47 bytes of
443 * the bottom of the stack: if RSP == tsk_stack + 48 and we
444 * take an exception, the stack is already aligned and there
445 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
446 * possible error code, so a stack overflow would *not* double
447 * fault. With any less space left, exception delivery could
448 * fail, and, as a practical matter, we've overflowed the
449 * stack even if the actual trigger for the double fault was
450 * something else.
451 */
452 if ((unsigned long)task_stack_page(tsk) - 1 - address < PAGE_SIZE) {
453 handle_stack_overflow("kernel stack overflow (double-fault)",
454 regs, address);
455 }
456#endif
457
458 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
459 die("double fault", regs, error_code);
460 panic("Machine halted.");
461 instrumentation_end();
462}
463
464DEFINE_IDTENTRY(exc_bounds)
465{
466 if (notify_die(DIE_TRAP, "bounds", regs, 0,
467 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
468 return;
469 cond_local_irq_enable(regs);
470
471 if (!user_mode(regs))
472 die("bounds", regs, 0);
473
474 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
475
476 cond_local_irq_disable(regs);
477}
478
479enum kernel_gp_hint {
480 GP_NO_HINT,
481 GP_NON_CANONICAL,
482 GP_CANONICAL
483};
484
485/*
486 * When an uncaught #GP occurs, try to determine the memory address accessed by
487 * the instruction and return that address to the caller. Also, try to figure
488 * out whether any part of the access to that address was non-canonical.
489 */
490static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
491 unsigned long *addr)
492{
493 u8 insn_buf[MAX_INSN_SIZE];
494 struct insn insn;
495
496 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
497 MAX_INSN_SIZE))
498 return GP_NO_HINT;
499
500 kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE);
501 insn_get_modrm(&insn);
502 insn_get_sib(&insn);
503
504 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
505 if (*addr == -1UL)
506 return GP_NO_HINT;
507
508#ifdef CONFIG_X86_64
509 /*
510 * Check that:
511 * - the operand is not in the kernel half
512 * - the last byte of the operand is not in the user canonical half
513 */
514 if (*addr < ~__VIRTUAL_MASK &&
515 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
516 return GP_NON_CANONICAL;
517#endif
518
519 return GP_CANONICAL;
520}
521
522#define GPFSTR "general protection fault"
523
524DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
525{
526 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
527 enum kernel_gp_hint hint = GP_NO_HINT;
528 struct task_struct *tsk;
529 unsigned long gp_addr;
530 int ret;
531
532 cond_local_irq_enable(regs);
533
534 if (static_cpu_has(X86_FEATURE_UMIP)) {
535 if (user_mode(regs) && fixup_umip_exception(regs))
536 goto exit;
537 }
538
539 if (v8086_mode(regs)) {
540 local_irq_enable();
541 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
542 local_irq_disable();
543 return;
544 }
545
546 tsk = current;
547
548 if (user_mode(regs)) {
549 tsk->thread.error_code = error_code;
550 tsk->thread.trap_nr = X86_TRAP_GP;
551
552 show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
553 force_sig(SIGSEGV);
554 goto exit;
555 }
556
557 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
558 goto exit;
559
560 tsk->thread.error_code = error_code;
561 tsk->thread.trap_nr = X86_TRAP_GP;
562
563 /*
564 * To be potentially processing a kprobe fault and to trust the result
565 * from kprobe_running(), we have to be non-preemptible.
566 */
567 if (!preemptible() &&
568 kprobe_running() &&
569 kprobe_fault_handler(regs, X86_TRAP_GP))
570 goto exit;
571
572 ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV);
573 if (ret == NOTIFY_STOP)
574 goto exit;
575
576 if (error_code)
577 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
578 else
579 hint = get_kernel_gp_address(regs, &gp_addr);
580
581 if (hint != GP_NO_HINT)
582 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
583 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
584 : "maybe for address",
585 gp_addr);
586
587 /*
588 * KASAN is interested only in the non-canonical case, clear it
589 * otherwise.
590 */
591 if (hint != GP_NON_CANONICAL)
592 gp_addr = 0;
593
594 die_addr(desc, regs, error_code, gp_addr);
595
596exit:
597 cond_local_irq_disable(regs);
598}
599
600static bool do_int3(struct pt_regs *regs)
601{
602 int res;
603
604#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
605 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
606 SIGTRAP) == NOTIFY_STOP)
607 return true;
608#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
609
610#ifdef CONFIG_KPROBES
611 if (kprobe_int3_handler(regs))
612 return true;
613#endif
614 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
615
616 return res == NOTIFY_STOP;
617}
618
619static void do_int3_user(struct pt_regs *regs)
620{
621 if (do_int3(regs))
622 return;
623
624 cond_local_irq_enable(regs);
625 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
626 cond_local_irq_disable(regs);
627}
628
629DEFINE_IDTENTRY_RAW(exc_int3)
630{
631 /*
632 * poke_int3_handler() is completely self contained code; it does (and
633 * must) *NOT* call out to anything, lest it hits upon yet another
634 * INT3.
635 */
636 if (poke_int3_handler(regs))
637 return;
638
639 /*
640 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
641 * and therefore can trigger INT3, hence poke_int3_handler() must
642 * be done before. If the entry came from kernel mode, then use
643 * nmi_enter() because the INT3 could have been hit in any context
644 * including NMI.
645 */
646 if (user_mode(regs)) {
647 irqentry_enter_from_user_mode(regs);
648 instrumentation_begin();
649 do_int3_user(regs);
650 instrumentation_end();
651 irqentry_exit_to_user_mode(regs);
652 } else {
653 bool irq_state = idtentry_enter_nmi(regs);
654 instrumentation_begin();
655 if (!do_int3(regs))
656 die("int3", regs, 0);
657 instrumentation_end();
658 idtentry_exit_nmi(regs, irq_state);
659 }
660}
661
662#ifdef CONFIG_X86_64
663/*
664 * Help handler running on a per-cpu (IST or entry trampoline) stack
665 * to switch to the normal thread stack if the interrupted code was in
666 * user mode. The actual stack switch is done in entry_64.S
667 */
668asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
669{
670 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
671 if (regs != eregs)
672 *regs = *eregs;
673 return regs;
674}
675
676struct bad_iret_stack {
677 void *error_entry_ret;
678 struct pt_regs regs;
679};
680
681asmlinkage __visible noinstr
682struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
683{
684 /*
685 * This is called from entry_64.S early in handling a fault
686 * caused by a bad iret to user mode. To handle the fault
687 * correctly, we want to move our stack frame to where it would
688 * be had we entered directly on the entry stack (rather than
689 * just below the IRET frame) and we want to pretend that the
690 * exception came from the IRET target.
691 */
692 struct bad_iret_stack tmp, *new_stack =
693 (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
694
695 /* Copy the IRET target to the temporary storage. */
696 __memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8);
697
698 /* Copy the remainder of the stack from the current stack. */
699 __memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip));
700
701 /* Update the entry stack */
702 __memcpy(new_stack, &tmp, sizeof(tmp));
703
704 BUG_ON(!user_mode(&new_stack->regs));
705 return new_stack;
706}
707#endif
708
709static bool is_sysenter_singlestep(struct pt_regs *regs)
710{
711 /*
712 * We don't try for precision here. If we're anywhere in the region of
713 * code that can be single-stepped in the SYSENTER entry path, then
714 * assume that this is a useless single-step trap due to SYSENTER
715 * being invoked with TF set. (We don't know in advance exactly
716 * which instructions will be hit because BTF could plausibly
717 * be set.)
718 */
719#ifdef CONFIG_X86_32
720 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
721 (unsigned long)__end_SYSENTER_singlestep_region -
722 (unsigned long)__begin_SYSENTER_singlestep_region;
723#elif defined(CONFIG_IA32_EMULATION)
724 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
725 (unsigned long)__end_entry_SYSENTER_compat -
726 (unsigned long)entry_SYSENTER_compat;
727#else
728 return false;
729#endif
730}
731
732static __always_inline unsigned long debug_read_clear_dr6(void)
733{
734 unsigned long dr6;
735
736 /*
737 * The Intel SDM says:
738 *
739 * Certain debug exceptions may clear bits 0-3. The remaining
740 * contents of the DR6 register are never cleared by the
741 * processor. To avoid confusion in identifying debug
742 * exceptions, debug handlers should clear the register before
743 * returning to the interrupted task.
744 *
745 * Keep it simple: clear DR6 immediately.
746 */
747 get_debugreg(dr6, 6);
748 set_debugreg(0, 6);
749 /* Filter out all the reserved bits which are preset to 1 */
750 dr6 &= ~DR6_RESERVED;
751
752 return dr6;
753}
754
755/*
756 * Our handling of the processor debug registers is non-trivial.
757 * We do not clear them on entry and exit from the kernel. Therefore
758 * it is possible to get a watchpoint trap here from inside the kernel.
759 * However, the code in ./ptrace.c has ensured that the user can
760 * only set watchpoints on userspace addresses. Therefore the in-kernel
761 * watchpoint trap can only occur in code which is reading/writing
762 * from user space. Such code must not hold kernel locks (since it
763 * can equally take a page fault), therefore it is safe to call
764 * force_sig_info even though that claims and releases locks.
765 *
766 * Code in ./signal.c ensures that the debug control register
767 * is restored before we deliver any signal, and therefore that
768 * user code runs with the correct debug control register even though
769 * we clear it here.
770 *
771 * Being careful here means that we don't have to be as careful in a
772 * lot of more complicated places (task switching can be a bit lazy
773 * about restoring all the debug state, and ptrace doesn't have to
774 * find every occurrence of the TF bit that could be saved away even
775 * by user code)
776 *
777 * May run on IST stack.
778 */
779static void handle_debug(struct pt_regs *regs, unsigned long dr6, bool user)
780{
781 struct task_struct *tsk = current;
782 bool user_icebp;
783 int si_code;
784
785 /*
786 * The SDM says "The processor clears the BTF flag when it
787 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
788 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
789 */
790 clear_thread_flag(TIF_BLOCKSTEP);
791
792 /*
793 * If DR6 is zero, no point in trying to handle it. The kernel is
794 * not using INT1.
795 */
796 if (!user && !dr6)
797 return;
798
799 /*
800 * If dr6 has no reason to give us about the origin of this trap,
801 * then it's very likely the result of an icebp/int01 trap.
802 * User wants a sigtrap for that.
803 */
804 user_icebp = user && !dr6;
805
806 /* Store the virtualized DR6 value */
807 tsk->thread.debugreg6 = dr6;
808
809#ifdef CONFIG_KPROBES
810 if (kprobe_debug_handler(regs)) {
811 return;
812 }
813#endif
814
815 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, 0,
816 SIGTRAP) == NOTIFY_STOP) {
817 return;
818 }
819
820 /* It's safe to allow irq's after DR6 has been saved */
821 cond_local_irq_enable(regs);
822
823 if (v8086_mode(regs)) {
824 handle_vm86_trap((struct kernel_vm86_regs *) regs, 0,
825 X86_TRAP_DB);
826 goto out;
827 }
828
829 if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
830 /*
831 * Historical junk that used to handle SYSENTER single-stepping.
832 * This should be unreachable now. If we survive for a while
833 * without anyone hitting this warning, we'll turn this into
834 * an oops.
835 */
836 tsk->thread.debugreg6 &= ~DR_STEP;
837 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
838 regs->flags &= ~X86_EFLAGS_TF;
839 }
840
841 si_code = get_si_code(tsk->thread.debugreg6);
842 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
843 send_sigtrap(regs, 0, si_code);
844
845out:
846 cond_local_irq_disable(regs);
847}
848
849static __always_inline void exc_debug_kernel(struct pt_regs *regs,
850 unsigned long dr6)
851{
852 /*
853 * Disable breakpoints during exception handling; recursive exceptions
854 * are exceedingly 'fun'.
855 *
856 * Since this function is NOKPROBE, and that also applies to
857 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
858 * HW_BREAKPOINT_W on our stack)
859 *
860 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
861 * includes the entry stack is excluded for everything.
862 */
863 unsigned long dr7 = local_db_save();
864 bool irq_state = idtentry_enter_nmi(regs);
865 instrumentation_begin();
866
867 /*
868 * If something gets miswired and we end up here for a user mode
869 * #DB, we will malfunction.
870 */
871 WARN_ON_ONCE(user_mode(regs));
872
873 /*
874 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
875 * watchpoint at the same time then that will still be handled.
876 */
877 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs))
878 dr6 &= ~DR_STEP;
879
880 handle_debug(regs, dr6, false);
881
882 instrumentation_end();
883 idtentry_exit_nmi(regs, irq_state);
884
885 local_db_restore(dr7);
886}
887
888static __always_inline void exc_debug_user(struct pt_regs *regs,
889 unsigned long dr6)
890{
891 /*
892 * If something gets miswired and we end up here for a kernel mode
893 * #DB, we will malfunction.
894 */
895 WARN_ON_ONCE(!user_mode(regs));
896
897 /*
898 * NB: We can't easily clear DR7 here because
899 * idtentry_exit_to_usermode() can invoke ptrace, schedule, access
900 * user memory, etc. This means that a recursive #DB is possible. If
901 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
902 * Since we're not on the IST stack right now, everything will be
903 * fine.
904 */
905
906 irqentry_enter_from_user_mode(regs);
907 instrumentation_begin();
908
909 handle_debug(regs, dr6, true);
910
911 instrumentation_end();
912 irqentry_exit_to_user_mode(regs);
913}
914
915#ifdef CONFIG_X86_64
916/* IST stack entry */
917DEFINE_IDTENTRY_DEBUG(exc_debug)
918{
919 exc_debug_kernel(regs, debug_read_clear_dr6());
920}
921
922/* User entry, runs on regular task stack */
923DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
924{
925 exc_debug_user(regs, debug_read_clear_dr6());
926}
927#else
928/* 32 bit does not have separate entry points. */
929DEFINE_IDTENTRY_RAW(exc_debug)
930{
931 unsigned long dr6 = debug_read_clear_dr6();
932
933 if (user_mode(regs))
934 exc_debug_user(regs, dr6);
935 else
936 exc_debug_kernel(regs, dr6);
937}
938#endif
939
940/*
941 * Note that we play around with the 'TS' bit in an attempt to get
942 * the correct behaviour even in the presence of the asynchronous
943 * IRQ13 behaviour
944 */
945static void math_error(struct pt_regs *regs, int trapnr)
946{
947 struct task_struct *task = current;
948 struct fpu *fpu = &task->thread.fpu;
949 int si_code;
950 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
951 "simd exception";
952
953 cond_local_irq_enable(regs);
954
955 if (!user_mode(regs)) {
956 if (fixup_exception(regs, trapnr, 0, 0))
957 goto exit;
958
959 task->thread.error_code = 0;
960 task->thread.trap_nr = trapnr;
961
962 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
963 SIGFPE) != NOTIFY_STOP)
964 die(str, regs, 0);
965 goto exit;
966 }
967
968 /*
969 * Save the info for the exception handler and clear the error.
970 */
971 fpu__save(fpu);
972
973 task->thread.trap_nr = trapnr;
974 task->thread.error_code = 0;
975
976 si_code = fpu__exception_code(fpu, trapnr);
977 /* Retry when we get spurious exceptions: */
978 if (!si_code)
979 goto exit;
980
981 force_sig_fault(SIGFPE, si_code,
982 (void __user *)uprobe_get_trap_addr(regs));
983exit:
984 cond_local_irq_disable(regs);
985}
986
987DEFINE_IDTENTRY(exc_coprocessor_error)
988{
989 math_error(regs, X86_TRAP_MF);
990}
991
992DEFINE_IDTENTRY(exc_simd_coprocessor_error)
993{
994 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
995 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
996 if (!static_cpu_has(X86_FEATURE_XMM)) {
997 __exc_general_protection(regs, 0);
998 return;
999 }
1000 }
1001 math_error(regs, X86_TRAP_XF);
1002}
1003
1004DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1005{
1006 /*
1007 * This addresses a Pentium Pro Erratum:
1008 *
1009 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1010 * Virtual Wire mode implemented through the local APIC, an
1011 * interrupt vector of 0Fh (Intel reserved encoding) may be
1012 * generated by the local APIC (Int 15). This vector may be
1013 * generated upon receipt of a spurious interrupt (an interrupt
1014 * which is removed before the system receives the INTA sequence)
1015 * instead of the programmed 8259 spurious interrupt vector.
1016 *
1017 * IMPLICATION: The spurious interrupt vector programmed in the
1018 * 8259 is normally handled by an operating system's spurious
1019 * interrupt handler. However, a vector of 0Fh is unknown to some
1020 * operating systems, which would crash if this erratum occurred.
1021 *
1022 * In theory this could be limited to 32bit, but the handler is not
1023 * hurting and who knows which other CPUs suffer from this.
1024 */
1025}
1026
1027DEFINE_IDTENTRY(exc_device_not_available)
1028{
1029 unsigned long cr0 = read_cr0();
1030
1031#ifdef CONFIG_MATH_EMULATION
1032 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1033 struct math_emu_info info = { };
1034
1035 cond_local_irq_enable(regs);
1036
1037 info.regs = regs;
1038 math_emulate(&info);
1039
1040 cond_local_irq_disable(regs);
1041 return;
1042 }
1043#endif
1044
1045 /* This should not happen. */
1046 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1047 /* Try to fix it up and carry on. */
1048 write_cr0(cr0 & ~X86_CR0_TS);
1049 } else {
1050 /*
1051 * Something terrible happened, and we're better off trying
1052 * to kill the task than getting stuck in a never-ending
1053 * loop of #NM faults.
1054 */
1055 die("unexpected #NM exception", regs, 0);
1056 }
1057}
1058
1059#ifdef CONFIG_X86_32
1060DEFINE_IDTENTRY_SW(iret_error)
1061{
1062 local_irq_enable();
1063 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1064 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1065 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1066 ILL_BADSTK, (void __user *)NULL);
1067 }
1068 local_irq_disable();
1069}
1070#endif
1071
1072void __init trap_init(void)
1073{
1074 /* Init cpu_entry_area before IST entries are set up */
1075 setup_cpu_entry_areas();
1076
1077 idt_setup_traps();
1078
1079 /*
1080 * Should be a barrier for any external CPU state:
1081 */
1082 cpu_init();
1083
1084 idt_setup_ist_traps();
1085}