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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_MMU_H
3#define __KVM_X86_MMU_H
4
5#include <linux/kvm_host.h>
6#include "kvm_cache_regs.h"
7#include "cpuid.h"
8
9#define PT64_PT_BITS 9
10#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
11#define PT32_PT_BITS 10
12#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
13
14#define PT_WRITABLE_SHIFT 1
15#define PT_USER_SHIFT 2
16
17#define PT_PRESENT_MASK (1ULL << 0)
18#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
19#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
20#define PT_PWT_MASK (1ULL << 3)
21#define PT_PCD_MASK (1ULL << 4)
22#define PT_ACCESSED_SHIFT 5
23#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
24#define PT_DIRTY_SHIFT 6
25#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
26#define PT_PAGE_SIZE_SHIFT 7
27#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
28#define PT_PAT_MASK (1ULL << 7)
29#define PT_GLOBAL_MASK (1ULL << 8)
30#define PT64_NX_SHIFT 63
31#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
32
33#define PT_PAT_SHIFT 7
34#define PT_DIR_PAT_SHIFT 12
35#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
36
37#define PT32_DIR_PSE36_SIZE 4
38#define PT32_DIR_PSE36_SHIFT 13
39#define PT32_DIR_PSE36_MASK \
40 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
41
42#define PT64_ROOT_5LEVEL 5
43#define PT64_ROOT_4LEVEL 4
44#define PT32_ROOT_LEVEL 2
45#define PT32E_ROOT_LEVEL 3
46
47#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | \
48 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE | \
49 X86_CR4_LA57)
50
51#define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
52
53static __always_inline u64 rsvd_bits(int s, int e)
54{
55 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
56
57 if (__builtin_constant_p(e))
58 BUILD_BUG_ON(e > 63);
59 else
60 e &= 63;
61
62 if (e < s)
63 return 0;
64
65 return ((2ULL << (e - s)) - 1) << s;
66}
67
68void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
69void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
70
71void kvm_init_mmu(struct kvm_vcpu *vcpu);
72void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
73 unsigned long cr4, u64 efer, gpa_t nested_cr3);
74void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
75 bool accessed_dirty, gpa_t new_eptp);
76bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
77int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
78 u64 fault_address, char *insn, int insn_len);
79
80int kvm_mmu_load(struct kvm_vcpu *vcpu);
81void kvm_mmu_unload(struct kvm_vcpu *vcpu);
82void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
83
84static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
85{
86 if (likely(vcpu->arch.mmu->root_hpa != INVALID_PAGE))
87 return 0;
88
89 return kvm_mmu_load(vcpu);
90}
91
92static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
93{
94 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
95
96 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
97 ? cr3 & X86_CR3_PCID_MASK
98 : 0;
99}
100
101static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
102{
103 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
104}
105
106static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
107{
108 u64 root_hpa = vcpu->arch.mmu->root_hpa;
109
110 if (!VALID_PAGE(root_hpa))
111 return;
112
113 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
114 vcpu->arch.mmu->shadow_root_level);
115}
116
117int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
118 bool prefault);
119
120static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
121 u32 err, bool prefault)
122{
123#ifdef CONFIG_RETPOLINE
124 if (likely(vcpu->arch.mmu->page_fault == kvm_tdp_page_fault))
125 return kvm_tdp_page_fault(vcpu, cr2_or_gpa, err, prefault);
126#endif
127 return vcpu->arch.mmu->page_fault(vcpu, cr2_or_gpa, err, prefault);
128}
129
130/*
131 * Currently, we have two sorts of write-protection, a) the first one
132 * write-protects guest page to sync the guest modification, b) another one is
133 * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
134 * between these two sorts are:
135 * 1) the first case clears MMU-writable bit.
136 * 2) the first case requires flushing tlb immediately avoiding corrupting
137 * shadow page table between all vcpus so it should be in the protection of
138 * mmu-lock. And the another case does not need to flush tlb until returning
139 * the dirty bitmap to userspace since it only write-protects the page
140 * logged in the bitmap, that means the page in the dirty bitmap is not
141 * missed, so it can flush tlb out of mmu-lock.
142 *
143 * So, there is the problem: the first case can meet the corrupted tlb caused
144 * by another case which write-protects pages but without flush tlb
145 * immediately. In order to making the first case be aware this problem we let
146 * it flush tlb if we try to write-protect a spte whose MMU-writable bit
147 * is set, it works since another case never touches MMU-writable bit.
148 *
149 * Anyway, whenever a spte is updated (only permission and status bits are
150 * changed) we need to check whether the spte with MMU-writable becomes
151 * readonly, if that happens, we need to flush tlb. Fortunately,
152 * mmu_spte_update() has already handled it perfectly.
153 *
154 * The rules to use MMU-writable and PT_WRITABLE_MASK:
155 * - if we want to see if it has writable tlb entry or if the spte can be
156 * writable on the mmu mapping, check MMU-writable, this is the most
157 * case, otherwise
158 * - if we fix page fault on the spte or do write-protection by dirty logging,
159 * check PT_WRITABLE_MASK.
160 *
161 * TODO: introduce APIs to split these two cases.
162 */
163static inline bool is_writable_pte(unsigned long pte)
164{
165 return pte & PT_WRITABLE_MASK;
166}
167
168/*
169 * Check if a given access (described through the I/D, W/R and U/S bits of a
170 * page fault error code pfec) causes a permission fault with the given PTE
171 * access rights (in ACC_* format).
172 *
173 * Return zero if the access does not fault; return the page fault error code
174 * if the access faults.
175 */
176static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
177 unsigned pte_access, unsigned pte_pkey,
178 unsigned pfec)
179{
180 int cpl = static_call(kvm_x86_get_cpl)(vcpu);
181 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
182
183 /*
184 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
185 *
186 * If CPL = 3, SMAP applies to all supervisor-mode data accesses
187 * (these are implicit supervisor accesses) regardless of the value
188 * of EFLAGS.AC.
189 *
190 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
191 * the result in X86_EFLAGS_AC. We then insert it in place of
192 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
193 * but it will be one in index if SMAP checks are being overridden.
194 * It is important to keep this branchless.
195 */
196 unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
197 int index = (pfec >> 1) +
198 (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
199 bool fault = (mmu->permissions[index] >> pte_access) & 1;
200 u32 errcode = PFERR_PRESENT_MASK;
201
202 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
203 if (unlikely(mmu->pkru_mask)) {
204 u32 pkru_bits, offset;
205
206 /*
207 * PKRU defines 32 bits, there are 16 domains and 2
208 * attribute bits per domain in pkru. pte_pkey is the
209 * index of the protection domain, so pte_pkey * 2 is
210 * is the index of the first bit for the domain.
211 */
212 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
213
214 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
215 offset = (pfec & ~1) +
216 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
217
218 pkru_bits &= mmu->pkru_mask >> offset;
219 errcode |= -pkru_bits & PFERR_PK_MASK;
220 fault |= (pkru_bits != 0);
221 }
222
223 return -(u32)fault & errcode;
224}
225
226void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
227
228int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
229
230int kvm_mmu_post_init_vm(struct kvm *kvm);
231void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
232
233static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
234{
235 /*
236 * Read memslot_have_rmaps before rmap pointers. Hence, threads reading
237 * memslots_have_rmaps in any lock context are guaranteed to see the
238 * pointers. Pairs with smp_store_release in alloc_all_memslots_rmaps.
239 */
240 return smp_load_acquire(&kvm->arch.memslots_have_rmaps);
241}
242
243#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __KVM_X86_MMU_H
3#define __KVM_X86_MMU_H
4
5#include <linux/kvm_host.h>
6#include "kvm_cache_regs.h"
7#include "cpuid.h"
8
9extern bool __read_mostly enable_mmio_caching;
10
11#define PT_WRITABLE_SHIFT 1
12#define PT_USER_SHIFT 2
13
14#define PT_PRESENT_MASK (1ULL << 0)
15#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
16#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
17#define PT_PWT_MASK (1ULL << 3)
18#define PT_PCD_MASK (1ULL << 4)
19#define PT_ACCESSED_SHIFT 5
20#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
21#define PT_DIRTY_SHIFT 6
22#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
23#define PT_PAGE_SIZE_SHIFT 7
24#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
25#define PT_PAT_MASK (1ULL << 7)
26#define PT_GLOBAL_MASK (1ULL << 8)
27#define PT64_NX_SHIFT 63
28#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
29
30#define PT_PAT_SHIFT 7
31#define PT_DIR_PAT_SHIFT 12
32#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
33
34#define PT64_ROOT_5LEVEL 5
35#define PT64_ROOT_4LEVEL 4
36#define PT32_ROOT_LEVEL 2
37#define PT32E_ROOT_LEVEL 3
38
39#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
40 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
41
42#define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
43#define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
44
45static __always_inline u64 rsvd_bits(int s, int e)
46{
47 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
48
49 if (__builtin_constant_p(e))
50 BUILD_BUG_ON(e > 63);
51 else
52 e &= 63;
53
54 if (e < s)
55 return 0;
56
57 return ((2ULL << (e - s)) - 1) << s;
58}
59
60/*
61 * The number of non-reserved physical address bits irrespective of features
62 * that repurpose legal bits, e.g. MKTME.
63 */
64extern u8 __read_mostly shadow_phys_bits;
65
66static inline gfn_t kvm_mmu_max_gfn(void)
67{
68 /*
69 * Note that this uses the host MAXPHYADDR, not the guest's.
70 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
71 * assuming KVM is running on bare metal, guest accesses beyond
72 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
73 * (either EPT Violation/Misconfig or #NPF), and so KVM will never
74 * install a SPTE for such addresses. If KVM is running as a VM
75 * itself, on the other hand, it might see a MAXPHYADDR that is less
76 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
77 * disallows such SPTEs entirely and simplifies the TDP MMU.
78 */
79 int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52;
80
81 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
82}
83
84static inline u8 kvm_get_shadow_phys_bits(void)
85{
86 /*
87 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
88 * in CPU detection code, but the processor treats those reduced bits as
89 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
90 * the physical address bits reported by CPUID.
91 */
92 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
93 return cpuid_eax(0x80000008) & 0xff;
94
95 /*
96 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
97 * custom CPUID. Proceed with whatever the kernel found since these features
98 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
99 */
100 return boot_cpu_data.x86_phys_bits;
101}
102
103void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
104void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
105void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
106
107void kvm_init_mmu(struct kvm_vcpu *vcpu);
108void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
109 unsigned long cr4, u64 efer, gpa_t nested_cr3);
110void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
111 int huge_page_level, bool accessed_dirty,
112 gpa_t new_eptp);
113bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
114int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
115 u64 fault_address, char *insn, int insn_len);
116
117int kvm_mmu_load(struct kvm_vcpu *vcpu);
118void kvm_mmu_unload(struct kvm_vcpu *vcpu);
119void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
120void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
121void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
122
123static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
124{
125 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
126 return 0;
127
128 return kvm_mmu_load(vcpu);
129}
130
131static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
132{
133 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
134
135 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
136 ? cr3 & X86_CR3_PCID_MASK
137 : 0;
138}
139
140static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
141{
142 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
143}
144
145static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
146{
147 u64 root_hpa = vcpu->arch.mmu->root.hpa;
148
149 if (!VALID_PAGE(root_hpa))
150 return;
151
152 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
153 vcpu->arch.mmu->root_role.level);
154}
155
156/*
157 * Check if a given access (described through the I/D, W/R and U/S bits of a
158 * page fault error code pfec) causes a permission fault with the given PTE
159 * access rights (in ACC_* format).
160 *
161 * Return zero if the access does not fault; return the page fault error code
162 * if the access faults.
163 */
164static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
165 unsigned pte_access, unsigned pte_pkey,
166 u64 access)
167{
168 /* strip nested paging fault error codes */
169 unsigned int pfec = access;
170 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
171
172 /*
173 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
174 * For implicit supervisor accesses, SMAP cannot be overridden.
175 *
176 * SMAP works on supervisor accesses only, and not_smap can
177 * be set or not set when user access with neither has any bearing
178 * on the result.
179 *
180 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
181 * this bit will always be zero in pfec, but it will be one in index
182 * if SMAP checks are being disabled.
183 */
184 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
185 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
186 int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1;
187 bool fault = (mmu->permissions[index] >> pte_access) & 1;
188 u32 errcode = PFERR_PRESENT_MASK;
189
190 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
191 if (unlikely(mmu->pkru_mask)) {
192 u32 pkru_bits, offset;
193
194 /*
195 * PKRU defines 32 bits, there are 16 domains and 2
196 * attribute bits per domain in pkru. pte_pkey is the
197 * index of the protection domain, so pte_pkey * 2 is
198 * is the index of the first bit for the domain.
199 */
200 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
201
202 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
203 offset = (pfec & ~1) +
204 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
205
206 pkru_bits &= mmu->pkru_mask >> offset;
207 errcode |= -pkru_bits & PFERR_PK_MASK;
208 fault |= (pkru_bits != 0);
209 }
210
211 return -(u32)fault & errcode;
212}
213
214void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
215
216int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
217
218int kvm_mmu_post_init_vm(struct kvm *kvm);
219void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
220
221static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
222{
223 /*
224 * Read shadow_root_allocated before related pointers. Hence, threads
225 * reading shadow_root_allocated in any lock context are guaranteed to
226 * see the pointers. Pairs with smp_store_release in
227 * mmu_first_shadow_root_alloc.
228 */
229 return smp_load_acquire(&kvm->arch.shadow_root_allocated);
230}
231
232#ifdef CONFIG_X86_64
233static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; }
234#else
235static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; }
236#endif
237
238static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
239{
240 return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm);
241}
242
243static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
244{
245 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
246 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
247 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
248}
249
250static inline unsigned long
251__kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
252 int level)
253{
254 return gfn_to_index(slot->base_gfn + npages - 1,
255 slot->base_gfn, level) + 1;
256}
257
258static inline unsigned long
259kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
260{
261 return __kvm_mmu_slot_lpages(slot, slot->npages, level);
262}
263
264static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
265{
266 atomic64_add(count, &kvm->stat.pages[level - 1]);
267}
268
269gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
270 struct x86_exception *exception);
271
272static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
273 struct kvm_mmu *mmu,
274 gpa_t gpa, u64 access,
275 struct x86_exception *exception)
276{
277 if (mmu != &vcpu->arch.nested_mmu)
278 return gpa;
279 return translate_nested_gpa(vcpu, gpa, access, exception);
280}
281#endif