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1/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/bitmap.h>
19#include <linux/cpu.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/log2.h>
23#include <linux/mm.h>
24#include <linux/msi.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_pci.h>
29#include <linux/of_platform.h>
30#include <linux/percpu.h>
31#include <linux/slab.h>
32
33#include <linux/irqchip.h>
34#include <linux/irqchip/arm-gic-v3.h>
35
36#include <asm/cacheflush.h>
37#include <asm/cputype.h>
38#include <asm/exception.h>
39
40#include "irq-gic-common.h"
41
42#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44
45#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46
47/*
48 * Collection structure - just an ID, and a redistributor address to
49 * ping. We use one per CPU as a bag of interrupts assigned to this
50 * CPU.
51 */
52struct its_collection {
53 u64 target_address;
54 u16 col_id;
55};
56
57/*
58 * The ITS structure - contains most of the infrastructure, with the
59 * top-level MSI domain, the command queue, the collections, and the
60 * list of devices writing to it.
61 */
62struct its_node {
63 raw_spinlock_t lock;
64 struct list_head entry;
65 void __iomem *base;
66 unsigned long phys_base;
67 struct its_cmd_block *cmd_base;
68 struct its_cmd_block *cmd_write;
69 struct {
70 void *base;
71 u32 order;
72 } tables[GITS_BASER_NR_REGS];
73 struct its_collection *collections;
74 struct list_head its_device_list;
75 u64 flags;
76 u32 ite_size;
77};
78
79#define ITS_ITT_ALIGN SZ_256
80
81/* Convert page order to size in bytes */
82#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
83
84struct event_lpi_map {
85 unsigned long *lpi_map;
86 u16 *col_map;
87 irq_hw_number_t lpi_base;
88 int nr_lpis;
89};
90
91/*
92 * The ITS view of a device - belongs to an ITS, a collection, owns an
93 * interrupt translation table, and a list of interrupts.
94 */
95struct its_device {
96 struct list_head entry;
97 struct its_node *its;
98 struct event_lpi_map event_map;
99 void *itt;
100 u32 nr_ites;
101 u32 device_id;
102};
103
104static LIST_HEAD(its_nodes);
105static DEFINE_SPINLOCK(its_lock);
106static struct rdists *gic_rdists;
107
108#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
109#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
110
111static struct its_collection *dev_event_to_col(struct its_device *its_dev,
112 u32 event)
113{
114 struct its_node *its = its_dev->its;
115
116 return its->collections + its_dev->event_map.col_map[event];
117}
118
119/*
120 * ITS command descriptors - parameters to be encoded in a command
121 * block.
122 */
123struct its_cmd_desc {
124 union {
125 struct {
126 struct its_device *dev;
127 u32 event_id;
128 } its_inv_cmd;
129
130 struct {
131 struct its_device *dev;
132 u32 event_id;
133 } its_int_cmd;
134
135 struct {
136 struct its_device *dev;
137 int valid;
138 } its_mapd_cmd;
139
140 struct {
141 struct its_collection *col;
142 int valid;
143 } its_mapc_cmd;
144
145 struct {
146 struct its_device *dev;
147 u32 phys_id;
148 u32 event_id;
149 } its_mapvi_cmd;
150
151 struct {
152 struct its_device *dev;
153 struct its_collection *col;
154 u32 event_id;
155 } its_movi_cmd;
156
157 struct {
158 struct its_device *dev;
159 u32 event_id;
160 } its_discard_cmd;
161
162 struct {
163 struct its_collection *col;
164 } its_invall_cmd;
165 };
166};
167
168/*
169 * The ITS command block, which is what the ITS actually parses.
170 */
171struct its_cmd_block {
172 u64 raw_cmd[4];
173};
174
175#define ITS_CMD_QUEUE_SZ SZ_64K
176#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
177
178typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
179 struct its_cmd_desc *);
180
181static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
182{
183 cmd->raw_cmd[0] &= ~0xffUL;
184 cmd->raw_cmd[0] |= cmd_nr;
185}
186
187static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
188{
189 cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
190 cmd->raw_cmd[0] |= ((u64)devid) << 32;
191}
192
193static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
194{
195 cmd->raw_cmd[1] &= ~0xffffffffUL;
196 cmd->raw_cmd[1] |= id;
197}
198
199static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
200{
201 cmd->raw_cmd[1] &= 0xffffffffUL;
202 cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
203}
204
205static void its_encode_size(struct its_cmd_block *cmd, u8 size)
206{
207 cmd->raw_cmd[1] &= ~0x1fUL;
208 cmd->raw_cmd[1] |= size & 0x1f;
209}
210
211static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
212{
213 cmd->raw_cmd[2] &= ~0xffffffffffffUL;
214 cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
215}
216
217static void its_encode_valid(struct its_cmd_block *cmd, int valid)
218{
219 cmd->raw_cmd[2] &= ~(1UL << 63);
220 cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
221}
222
223static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
224{
225 cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
226 cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
227}
228
229static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
230{
231 cmd->raw_cmd[2] &= ~0xffffUL;
232 cmd->raw_cmd[2] |= col;
233}
234
235static inline void its_fixup_cmd(struct its_cmd_block *cmd)
236{
237 /* Let's fixup BE commands */
238 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
239 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
240 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
241 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
242}
243
244static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
245 struct its_cmd_desc *desc)
246{
247 unsigned long itt_addr;
248 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
249
250 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
251 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
252
253 its_encode_cmd(cmd, GITS_CMD_MAPD);
254 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
255 its_encode_size(cmd, size - 1);
256 its_encode_itt(cmd, itt_addr);
257 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
258
259 its_fixup_cmd(cmd);
260
261 return NULL;
262}
263
264static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
265 struct its_cmd_desc *desc)
266{
267 its_encode_cmd(cmd, GITS_CMD_MAPC);
268 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
269 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
270 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
271
272 its_fixup_cmd(cmd);
273
274 return desc->its_mapc_cmd.col;
275}
276
277static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
278 struct its_cmd_desc *desc)
279{
280 struct its_collection *col;
281
282 col = dev_event_to_col(desc->its_mapvi_cmd.dev,
283 desc->its_mapvi_cmd.event_id);
284
285 its_encode_cmd(cmd, GITS_CMD_MAPVI);
286 its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
287 its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
288 its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
289 its_encode_collection(cmd, col->col_id);
290
291 its_fixup_cmd(cmd);
292
293 return col;
294}
295
296static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
297 struct its_cmd_desc *desc)
298{
299 struct its_collection *col;
300
301 col = dev_event_to_col(desc->its_movi_cmd.dev,
302 desc->its_movi_cmd.event_id);
303
304 its_encode_cmd(cmd, GITS_CMD_MOVI);
305 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
306 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
307 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
308
309 its_fixup_cmd(cmd);
310
311 return col;
312}
313
314static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
315 struct its_cmd_desc *desc)
316{
317 struct its_collection *col;
318
319 col = dev_event_to_col(desc->its_discard_cmd.dev,
320 desc->its_discard_cmd.event_id);
321
322 its_encode_cmd(cmd, GITS_CMD_DISCARD);
323 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
324 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
325
326 its_fixup_cmd(cmd);
327
328 return col;
329}
330
331static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
332 struct its_cmd_desc *desc)
333{
334 struct its_collection *col;
335
336 col = dev_event_to_col(desc->its_inv_cmd.dev,
337 desc->its_inv_cmd.event_id);
338
339 its_encode_cmd(cmd, GITS_CMD_INV);
340 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
341 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
342
343 its_fixup_cmd(cmd);
344
345 return col;
346}
347
348static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
349 struct its_cmd_desc *desc)
350{
351 its_encode_cmd(cmd, GITS_CMD_INVALL);
352 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
353
354 its_fixup_cmd(cmd);
355
356 return NULL;
357}
358
359static u64 its_cmd_ptr_to_offset(struct its_node *its,
360 struct its_cmd_block *ptr)
361{
362 return (ptr - its->cmd_base) * sizeof(*ptr);
363}
364
365static int its_queue_full(struct its_node *its)
366{
367 int widx;
368 int ridx;
369
370 widx = its->cmd_write - its->cmd_base;
371 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
372
373 /* This is incredibly unlikely to happen, unless the ITS locks up. */
374 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
375 return 1;
376
377 return 0;
378}
379
380static struct its_cmd_block *its_allocate_entry(struct its_node *its)
381{
382 struct its_cmd_block *cmd;
383 u32 count = 1000000; /* 1s! */
384
385 while (its_queue_full(its)) {
386 count--;
387 if (!count) {
388 pr_err_ratelimited("ITS queue not draining\n");
389 return NULL;
390 }
391 cpu_relax();
392 udelay(1);
393 }
394
395 cmd = its->cmd_write++;
396
397 /* Handle queue wrapping */
398 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
399 its->cmd_write = its->cmd_base;
400
401 return cmd;
402}
403
404static struct its_cmd_block *its_post_commands(struct its_node *its)
405{
406 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
407
408 writel_relaxed(wr, its->base + GITS_CWRITER);
409
410 return its->cmd_write;
411}
412
413static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
414{
415 /*
416 * Make sure the commands written to memory are observable by
417 * the ITS.
418 */
419 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
420 __flush_dcache_area(cmd, sizeof(*cmd));
421 else
422 dsb(ishst);
423}
424
425static void its_wait_for_range_completion(struct its_node *its,
426 struct its_cmd_block *from,
427 struct its_cmd_block *to)
428{
429 u64 rd_idx, from_idx, to_idx;
430 u32 count = 1000000; /* 1s! */
431
432 from_idx = its_cmd_ptr_to_offset(its, from);
433 to_idx = its_cmd_ptr_to_offset(its, to);
434
435 while (1) {
436 rd_idx = readl_relaxed(its->base + GITS_CREADR);
437 if (rd_idx >= to_idx || rd_idx < from_idx)
438 break;
439
440 count--;
441 if (!count) {
442 pr_err_ratelimited("ITS queue timeout\n");
443 return;
444 }
445 cpu_relax();
446 udelay(1);
447 }
448}
449
450static void its_send_single_command(struct its_node *its,
451 its_cmd_builder_t builder,
452 struct its_cmd_desc *desc)
453{
454 struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
455 struct its_collection *sync_col;
456 unsigned long flags;
457
458 raw_spin_lock_irqsave(&its->lock, flags);
459
460 cmd = its_allocate_entry(its);
461 if (!cmd) { /* We're soooooo screewed... */
462 pr_err_ratelimited("ITS can't allocate, dropping command\n");
463 raw_spin_unlock_irqrestore(&its->lock, flags);
464 return;
465 }
466 sync_col = builder(cmd, desc);
467 its_flush_cmd(its, cmd);
468
469 if (sync_col) {
470 sync_cmd = its_allocate_entry(its);
471 if (!sync_cmd) {
472 pr_err_ratelimited("ITS can't SYNC, skipping\n");
473 goto post;
474 }
475 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
476 its_encode_target(sync_cmd, sync_col->target_address);
477 its_fixup_cmd(sync_cmd);
478 its_flush_cmd(its, sync_cmd);
479 }
480
481post:
482 next_cmd = its_post_commands(its);
483 raw_spin_unlock_irqrestore(&its->lock, flags);
484
485 its_wait_for_range_completion(its, cmd, next_cmd);
486}
487
488static void its_send_inv(struct its_device *dev, u32 event_id)
489{
490 struct its_cmd_desc desc;
491
492 desc.its_inv_cmd.dev = dev;
493 desc.its_inv_cmd.event_id = event_id;
494
495 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
496}
497
498static void its_send_mapd(struct its_device *dev, int valid)
499{
500 struct its_cmd_desc desc;
501
502 desc.its_mapd_cmd.dev = dev;
503 desc.its_mapd_cmd.valid = !!valid;
504
505 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
506}
507
508static void its_send_mapc(struct its_node *its, struct its_collection *col,
509 int valid)
510{
511 struct its_cmd_desc desc;
512
513 desc.its_mapc_cmd.col = col;
514 desc.its_mapc_cmd.valid = !!valid;
515
516 its_send_single_command(its, its_build_mapc_cmd, &desc);
517}
518
519static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
520{
521 struct its_cmd_desc desc;
522
523 desc.its_mapvi_cmd.dev = dev;
524 desc.its_mapvi_cmd.phys_id = irq_id;
525 desc.its_mapvi_cmd.event_id = id;
526
527 its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
528}
529
530static void its_send_movi(struct its_device *dev,
531 struct its_collection *col, u32 id)
532{
533 struct its_cmd_desc desc;
534
535 desc.its_movi_cmd.dev = dev;
536 desc.its_movi_cmd.col = col;
537 desc.its_movi_cmd.event_id = id;
538
539 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
540}
541
542static void its_send_discard(struct its_device *dev, u32 id)
543{
544 struct its_cmd_desc desc;
545
546 desc.its_discard_cmd.dev = dev;
547 desc.its_discard_cmd.event_id = id;
548
549 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
550}
551
552static void its_send_invall(struct its_node *its, struct its_collection *col)
553{
554 struct its_cmd_desc desc;
555
556 desc.its_invall_cmd.col = col;
557
558 its_send_single_command(its, its_build_invall_cmd, &desc);
559}
560
561/*
562 * irqchip functions - assumes MSI, mostly.
563 */
564
565static inline u32 its_get_event_id(struct irq_data *d)
566{
567 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
568 return d->hwirq - its_dev->event_map.lpi_base;
569}
570
571static void lpi_set_config(struct irq_data *d, bool enable)
572{
573 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
574 irq_hw_number_t hwirq = d->hwirq;
575 u32 id = its_get_event_id(d);
576 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
577
578 if (enable)
579 *cfg |= LPI_PROP_ENABLED;
580 else
581 *cfg &= ~LPI_PROP_ENABLED;
582
583 /*
584 * Make the above write visible to the redistributors.
585 * And yes, we're flushing exactly: One. Single. Byte.
586 * Humpf...
587 */
588 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
589 __flush_dcache_area(cfg, sizeof(*cfg));
590 else
591 dsb(ishst);
592 its_send_inv(its_dev, id);
593}
594
595static void its_mask_irq(struct irq_data *d)
596{
597 lpi_set_config(d, false);
598}
599
600static void its_unmask_irq(struct irq_data *d)
601{
602 lpi_set_config(d, true);
603}
604
605static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
606 bool force)
607{
608 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
609 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
610 struct its_collection *target_col;
611 u32 id = its_get_event_id(d);
612
613 if (cpu >= nr_cpu_ids)
614 return -EINVAL;
615
616 target_col = &its_dev->its->collections[cpu];
617 its_send_movi(its_dev, target_col, id);
618 its_dev->event_map.col_map[id] = cpu;
619
620 return IRQ_SET_MASK_OK_DONE;
621}
622
623static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
624{
625 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
626 struct its_node *its;
627 u64 addr;
628
629 its = its_dev->its;
630 addr = its->phys_base + GITS_TRANSLATER;
631
632 msg->address_lo = addr & ((1UL << 32) - 1);
633 msg->address_hi = addr >> 32;
634 msg->data = its_get_event_id(d);
635}
636
637static struct irq_chip its_irq_chip = {
638 .name = "ITS",
639 .irq_mask = its_mask_irq,
640 .irq_unmask = its_unmask_irq,
641 .irq_eoi = irq_chip_eoi_parent,
642 .irq_set_affinity = its_set_affinity,
643 .irq_compose_msi_msg = its_irq_compose_msi_msg,
644};
645
646/*
647 * How we allocate LPIs:
648 *
649 * The GIC has id_bits bits for interrupt identifiers. From there, we
650 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
651 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
652 * bits to the right.
653 *
654 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
655 */
656#define IRQS_PER_CHUNK_SHIFT 5
657#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
658
659static unsigned long *lpi_bitmap;
660static u32 lpi_chunks;
661static DEFINE_SPINLOCK(lpi_lock);
662
663static int its_lpi_to_chunk(int lpi)
664{
665 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
666}
667
668static int its_chunk_to_lpi(int chunk)
669{
670 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
671}
672
673static int __init its_lpi_init(u32 id_bits)
674{
675 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
676
677 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
678 GFP_KERNEL);
679 if (!lpi_bitmap) {
680 lpi_chunks = 0;
681 return -ENOMEM;
682 }
683
684 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
685 return 0;
686}
687
688static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
689{
690 unsigned long *bitmap = NULL;
691 int chunk_id;
692 int nr_chunks;
693 int i;
694
695 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
696
697 spin_lock(&lpi_lock);
698
699 do {
700 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
701 0, nr_chunks, 0);
702 if (chunk_id < lpi_chunks)
703 break;
704
705 nr_chunks--;
706 } while (nr_chunks > 0);
707
708 if (!nr_chunks)
709 goto out;
710
711 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
712 GFP_ATOMIC);
713 if (!bitmap)
714 goto out;
715
716 for (i = 0; i < nr_chunks; i++)
717 set_bit(chunk_id + i, lpi_bitmap);
718
719 *base = its_chunk_to_lpi(chunk_id);
720 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
721
722out:
723 spin_unlock(&lpi_lock);
724
725 if (!bitmap)
726 *base = *nr_ids = 0;
727
728 return bitmap;
729}
730
731static void its_lpi_free(struct event_lpi_map *map)
732{
733 int base = map->lpi_base;
734 int nr_ids = map->nr_lpis;
735 int lpi;
736
737 spin_lock(&lpi_lock);
738
739 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
740 int chunk = its_lpi_to_chunk(lpi);
741 BUG_ON(chunk > lpi_chunks);
742 if (test_bit(chunk, lpi_bitmap)) {
743 clear_bit(chunk, lpi_bitmap);
744 } else {
745 pr_err("Bad LPI chunk %d\n", chunk);
746 }
747 }
748
749 spin_unlock(&lpi_lock);
750
751 kfree(map->lpi_map);
752 kfree(map->col_map);
753}
754
755/*
756 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
757 * deal with (one configuration byte per interrupt). PENDBASE has to
758 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
759 */
760#define LPI_PROPBASE_SZ SZ_64K
761#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
762
763/*
764 * This is how many bits of ID we need, including the useless ones.
765 */
766#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
767
768#define LPI_PROP_DEFAULT_PRIO 0xa0
769
770static int __init its_alloc_lpi_tables(void)
771{
772 phys_addr_t paddr;
773
774 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
775 get_order(LPI_PROPBASE_SZ));
776 if (!gic_rdists->prop_page) {
777 pr_err("Failed to allocate PROPBASE\n");
778 return -ENOMEM;
779 }
780
781 paddr = page_to_phys(gic_rdists->prop_page);
782 pr_info("GIC: using LPI property table @%pa\n", &paddr);
783
784 /* Priority 0xa0, Group-1, disabled */
785 memset(page_address(gic_rdists->prop_page),
786 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
787 LPI_PROPBASE_SZ);
788
789 /* Make sure the GIC will observe the written configuration */
790 __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
791
792 return 0;
793}
794
795static const char *its_base_type_string[] = {
796 [GITS_BASER_TYPE_DEVICE] = "Devices",
797 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
798 [GITS_BASER_TYPE_CPU] = "Physical CPUs",
799 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
800 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
801 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
802 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
803};
804
805static void its_free_tables(struct its_node *its)
806{
807 int i;
808
809 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
810 if (its->tables[i].base) {
811 free_pages((unsigned long)its->tables[i].base,
812 its->tables[i].order);
813 its->tables[i].base = NULL;
814 }
815 }
816}
817
818static int its_alloc_tables(const char *node_name, struct its_node *its)
819{
820 int err;
821 int i;
822 int psz = SZ_64K;
823 u64 shr = GITS_BASER_InnerShareable;
824 u64 cache;
825 u64 typer;
826 u32 ids;
827
828 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
829 /*
830 * erratum 22375: only alloc 8MB table size
831 * erratum 24313: ignore memory access type
832 */
833 cache = 0;
834 ids = 0x14; /* 20 bits, 8MB */
835 } else {
836 cache = GITS_BASER_WaWb;
837 typer = readq_relaxed(its->base + GITS_TYPER);
838 ids = GITS_TYPER_DEVBITS(typer);
839 }
840
841 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
842 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
843 u64 type = GITS_BASER_TYPE(val);
844 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
845 int order = get_order(psz);
846 int alloc_pages;
847 u64 tmp;
848 void *base;
849
850 if (type == GITS_BASER_TYPE_NONE)
851 continue;
852
853 /*
854 * Allocate as many entries as required to fit the
855 * range of device IDs that the ITS can grok... The ID
856 * space being incredibly sparse, this results in a
857 * massive waste of memory.
858 *
859 * For other tables, only allocate a single page.
860 */
861 if (type == GITS_BASER_TYPE_DEVICE) {
862 /*
863 * 'order' was initialized earlier to the default page
864 * granule of the the ITS. We can't have an allocation
865 * smaller than that. If the requested allocation
866 * is smaller, round up to the default page granule.
867 */
868 order = max(get_order((1UL << ids) * entry_size),
869 order);
870 if (order >= MAX_ORDER) {
871 order = MAX_ORDER - 1;
872 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
873 node_name, order);
874 }
875 }
876
877retry_alloc_baser:
878 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
879 if (alloc_pages > GITS_BASER_PAGES_MAX) {
880 alloc_pages = GITS_BASER_PAGES_MAX;
881 order = get_order(GITS_BASER_PAGES_MAX * psz);
882 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
883 node_name, order, alloc_pages);
884 }
885
886 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
887 if (!base) {
888 err = -ENOMEM;
889 goto out_free;
890 }
891
892 its->tables[i].base = base;
893 its->tables[i].order = order;
894
895retry_baser:
896 val = (virt_to_phys(base) |
897 (type << GITS_BASER_TYPE_SHIFT) |
898 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
899 cache |
900 shr |
901 GITS_BASER_VALID);
902
903 switch (psz) {
904 case SZ_4K:
905 val |= GITS_BASER_PAGE_SIZE_4K;
906 break;
907 case SZ_16K:
908 val |= GITS_BASER_PAGE_SIZE_16K;
909 break;
910 case SZ_64K:
911 val |= GITS_BASER_PAGE_SIZE_64K;
912 break;
913 }
914
915 val |= alloc_pages - 1;
916
917 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
918 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
919
920 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
921 /*
922 * Shareability didn't stick. Just use
923 * whatever the read reported, which is likely
924 * to be the only thing this redistributor
925 * supports. If that's zero, make it
926 * non-cacheable as well.
927 */
928 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
929 if (!shr) {
930 cache = GITS_BASER_nC;
931 __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
932 }
933 goto retry_baser;
934 }
935
936 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
937 /*
938 * Page size didn't stick. Let's try a smaller
939 * size and retry. If we reach 4K, then
940 * something is horribly wrong...
941 */
942 free_pages((unsigned long)base, order);
943 its->tables[i].base = NULL;
944
945 switch (psz) {
946 case SZ_16K:
947 psz = SZ_4K;
948 goto retry_alloc_baser;
949 case SZ_64K:
950 psz = SZ_16K;
951 goto retry_alloc_baser;
952 }
953 }
954
955 if (val != tmp) {
956 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
957 node_name, i,
958 (unsigned long) val, (unsigned long) tmp);
959 err = -ENXIO;
960 goto out_free;
961 }
962
963 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
964 (int)(PAGE_ORDER_TO_SIZE(order) / entry_size),
965 its_base_type_string[type],
966 (unsigned long)virt_to_phys(base),
967 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
968 }
969
970 return 0;
971
972out_free:
973 its_free_tables(its);
974
975 return err;
976}
977
978static int its_alloc_collections(struct its_node *its)
979{
980 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
981 GFP_KERNEL);
982 if (!its->collections)
983 return -ENOMEM;
984
985 return 0;
986}
987
988static void its_cpu_init_lpis(void)
989{
990 void __iomem *rbase = gic_data_rdist_rd_base();
991 struct page *pend_page;
992 u64 val, tmp;
993
994 /* If we didn't allocate the pending table yet, do it now */
995 pend_page = gic_data_rdist()->pend_page;
996 if (!pend_page) {
997 phys_addr_t paddr;
998 /*
999 * The pending pages have to be at least 64kB aligned,
1000 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1001 */
1002 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
1003 get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
1004 if (!pend_page) {
1005 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1006 smp_processor_id());
1007 return;
1008 }
1009
1010 /* Make sure the GIC will observe the zero-ed page */
1011 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1012
1013 paddr = page_to_phys(pend_page);
1014 pr_info("CPU%d: using LPI pending table @%pa\n",
1015 smp_processor_id(), &paddr);
1016 gic_data_rdist()->pend_page = pend_page;
1017 }
1018
1019 /* Disable LPIs */
1020 val = readl_relaxed(rbase + GICR_CTLR);
1021 val &= ~GICR_CTLR_ENABLE_LPIS;
1022 writel_relaxed(val, rbase + GICR_CTLR);
1023
1024 /*
1025 * Make sure any change to the table is observable by the GIC.
1026 */
1027 dsb(sy);
1028
1029 /* set PROPBASE */
1030 val = (page_to_phys(gic_rdists->prop_page) |
1031 GICR_PROPBASER_InnerShareable |
1032 GICR_PROPBASER_WaWb |
1033 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1034
1035 writeq_relaxed(val, rbase + GICR_PROPBASER);
1036 tmp = readq_relaxed(rbase + GICR_PROPBASER);
1037
1038 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1039 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1040 /*
1041 * The HW reports non-shareable, we must
1042 * remove the cacheability attributes as
1043 * well.
1044 */
1045 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1046 GICR_PROPBASER_CACHEABILITY_MASK);
1047 val |= GICR_PROPBASER_nC;
1048 writeq_relaxed(val, rbase + GICR_PROPBASER);
1049 }
1050 pr_info_once("GIC: using cache flushing for LPI property table\n");
1051 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1052 }
1053
1054 /* set PENDBASE */
1055 val = (page_to_phys(pend_page) |
1056 GICR_PENDBASER_InnerShareable |
1057 GICR_PENDBASER_WaWb);
1058
1059 writeq_relaxed(val, rbase + GICR_PENDBASER);
1060 tmp = readq_relaxed(rbase + GICR_PENDBASER);
1061
1062 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1063 /*
1064 * The HW reports non-shareable, we must remove the
1065 * cacheability attributes as well.
1066 */
1067 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1068 GICR_PENDBASER_CACHEABILITY_MASK);
1069 val |= GICR_PENDBASER_nC;
1070 writeq_relaxed(val, rbase + GICR_PENDBASER);
1071 }
1072
1073 /* Enable LPIs */
1074 val = readl_relaxed(rbase + GICR_CTLR);
1075 val |= GICR_CTLR_ENABLE_LPIS;
1076 writel_relaxed(val, rbase + GICR_CTLR);
1077
1078 /* Make sure the GIC has seen the above */
1079 dsb(sy);
1080}
1081
1082static void its_cpu_init_collection(void)
1083{
1084 struct its_node *its;
1085 int cpu;
1086
1087 spin_lock(&its_lock);
1088 cpu = smp_processor_id();
1089
1090 list_for_each_entry(its, &its_nodes, entry) {
1091 u64 target;
1092
1093 /*
1094 * We now have to bind each collection to its target
1095 * redistributor.
1096 */
1097 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1098 /*
1099 * This ITS wants the physical address of the
1100 * redistributor.
1101 */
1102 target = gic_data_rdist()->phys_base;
1103 } else {
1104 /*
1105 * This ITS wants a linear CPU number.
1106 */
1107 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1108 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1109 }
1110
1111 /* Perform collection mapping */
1112 its->collections[cpu].target_address = target;
1113 its->collections[cpu].col_id = cpu;
1114
1115 its_send_mapc(its, &its->collections[cpu], 1);
1116 its_send_invall(its, &its->collections[cpu]);
1117 }
1118
1119 spin_unlock(&its_lock);
1120}
1121
1122static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1123{
1124 struct its_device *its_dev = NULL, *tmp;
1125 unsigned long flags;
1126
1127 raw_spin_lock_irqsave(&its->lock, flags);
1128
1129 list_for_each_entry(tmp, &its->its_device_list, entry) {
1130 if (tmp->device_id == dev_id) {
1131 its_dev = tmp;
1132 break;
1133 }
1134 }
1135
1136 raw_spin_unlock_irqrestore(&its->lock, flags);
1137
1138 return its_dev;
1139}
1140
1141static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1142 int nvecs)
1143{
1144 struct its_device *dev;
1145 unsigned long *lpi_map;
1146 unsigned long flags;
1147 u16 *col_map = NULL;
1148 void *itt;
1149 int lpi_base;
1150 int nr_lpis;
1151 int nr_ites;
1152 int sz;
1153
1154 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1155 /*
1156 * At least one bit of EventID is being used, hence a minimum
1157 * of two entries. No, the architecture doesn't let you
1158 * express an ITT with a single entry.
1159 */
1160 nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1161 sz = nr_ites * its->ite_size;
1162 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1163 itt = kzalloc(sz, GFP_KERNEL);
1164 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1165 if (lpi_map)
1166 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1167
1168 if (!dev || !itt || !lpi_map || !col_map) {
1169 kfree(dev);
1170 kfree(itt);
1171 kfree(lpi_map);
1172 kfree(col_map);
1173 return NULL;
1174 }
1175
1176 __flush_dcache_area(itt, sz);
1177
1178 dev->its = its;
1179 dev->itt = itt;
1180 dev->nr_ites = nr_ites;
1181 dev->event_map.lpi_map = lpi_map;
1182 dev->event_map.col_map = col_map;
1183 dev->event_map.lpi_base = lpi_base;
1184 dev->event_map.nr_lpis = nr_lpis;
1185 dev->device_id = dev_id;
1186 INIT_LIST_HEAD(&dev->entry);
1187
1188 raw_spin_lock_irqsave(&its->lock, flags);
1189 list_add(&dev->entry, &its->its_device_list);
1190 raw_spin_unlock_irqrestore(&its->lock, flags);
1191
1192 /* Map device to its ITT */
1193 its_send_mapd(dev, 1);
1194
1195 return dev;
1196}
1197
1198static void its_free_device(struct its_device *its_dev)
1199{
1200 unsigned long flags;
1201
1202 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1203 list_del(&its_dev->entry);
1204 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1205 kfree(its_dev->itt);
1206 kfree(its_dev);
1207}
1208
1209static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1210{
1211 int idx;
1212
1213 idx = find_first_zero_bit(dev->event_map.lpi_map,
1214 dev->event_map.nr_lpis);
1215 if (idx == dev->event_map.nr_lpis)
1216 return -ENOSPC;
1217
1218 *hwirq = dev->event_map.lpi_base + idx;
1219 set_bit(idx, dev->event_map.lpi_map);
1220
1221 return 0;
1222}
1223
1224static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1225 int nvec, msi_alloc_info_t *info)
1226{
1227 struct its_node *its;
1228 struct its_device *its_dev;
1229 struct msi_domain_info *msi_info;
1230 u32 dev_id;
1231
1232 /*
1233 * We ignore "dev" entierely, and rely on the dev_id that has
1234 * been passed via the scratchpad. This limits this domain's
1235 * usefulness to upper layers that definitely know that they
1236 * are built on top of the ITS.
1237 */
1238 dev_id = info->scratchpad[0].ul;
1239
1240 msi_info = msi_get_domain_info(domain);
1241 its = msi_info->data;
1242
1243 its_dev = its_find_device(its, dev_id);
1244 if (its_dev) {
1245 /*
1246 * We already have seen this ID, probably through
1247 * another alias (PCI bridge of some sort). No need to
1248 * create the device.
1249 */
1250 pr_debug("Reusing ITT for devID %x\n", dev_id);
1251 goto out;
1252 }
1253
1254 its_dev = its_create_device(its, dev_id, nvec);
1255 if (!its_dev)
1256 return -ENOMEM;
1257
1258 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1259out:
1260 info->scratchpad[0].ptr = its_dev;
1261 return 0;
1262}
1263
1264static struct msi_domain_ops its_msi_domain_ops = {
1265 .msi_prepare = its_msi_prepare,
1266};
1267
1268static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1269 unsigned int virq,
1270 irq_hw_number_t hwirq)
1271{
1272 struct irq_fwspec fwspec;
1273
1274 if (irq_domain_get_of_node(domain->parent)) {
1275 fwspec.fwnode = domain->parent->fwnode;
1276 fwspec.param_count = 3;
1277 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1278 fwspec.param[1] = hwirq;
1279 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1280 } else {
1281 return -EINVAL;
1282 }
1283
1284 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1285}
1286
1287static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1288 unsigned int nr_irqs, void *args)
1289{
1290 msi_alloc_info_t *info = args;
1291 struct its_device *its_dev = info->scratchpad[0].ptr;
1292 irq_hw_number_t hwirq;
1293 int err;
1294 int i;
1295
1296 for (i = 0; i < nr_irqs; i++) {
1297 err = its_alloc_device_irq(its_dev, &hwirq);
1298 if (err)
1299 return err;
1300
1301 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1302 if (err)
1303 return err;
1304
1305 irq_domain_set_hwirq_and_chip(domain, virq + i,
1306 hwirq, &its_irq_chip, its_dev);
1307 pr_debug("ID:%d pID:%d vID:%d\n",
1308 (int)(hwirq - its_dev->event_map.lpi_base),
1309 (int) hwirq, virq + i);
1310 }
1311
1312 return 0;
1313}
1314
1315static void its_irq_domain_activate(struct irq_domain *domain,
1316 struct irq_data *d)
1317{
1318 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1319 u32 event = its_get_event_id(d);
1320
1321 /* Bind the LPI to the first possible CPU */
1322 its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1323
1324 /* Map the GIC IRQ and event to the device */
1325 its_send_mapvi(its_dev, d->hwirq, event);
1326}
1327
1328static void its_irq_domain_deactivate(struct irq_domain *domain,
1329 struct irq_data *d)
1330{
1331 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1332 u32 event = its_get_event_id(d);
1333
1334 /* Stop the delivery of interrupts */
1335 its_send_discard(its_dev, event);
1336}
1337
1338static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1339 unsigned int nr_irqs)
1340{
1341 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1342 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1343 int i;
1344
1345 for (i = 0; i < nr_irqs; i++) {
1346 struct irq_data *data = irq_domain_get_irq_data(domain,
1347 virq + i);
1348 u32 event = its_get_event_id(data);
1349
1350 /* Mark interrupt index as unused */
1351 clear_bit(event, its_dev->event_map.lpi_map);
1352
1353 /* Nuke the entry in the domain */
1354 irq_domain_reset_irq_data(data);
1355 }
1356
1357 /* If all interrupts have been freed, start mopping the floor */
1358 if (bitmap_empty(its_dev->event_map.lpi_map,
1359 its_dev->event_map.nr_lpis)) {
1360 its_lpi_free(&its_dev->event_map);
1361
1362 /* Unmap device/itt */
1363 its_send_mapd(its_dev, 0);
1364 its_free_device(its_dev);
1365 }
1366
1367 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1368}
1369
1370static const struct irq_domain_ops its_domain_ops = {
1371 .alloc = its_irq_domain_alloc,
1372 .free = its_irq_domain_free,
1373 .activate = its_irq_domain_activate,
1374 .deactivate = its_irq_domain_deactivate,
1375};
1376
1377static int its_force_quiescent(void __iomem *base)
1378{
1379 u32 count = 1000000; /* 1s */
1380 u32 val;
1381
1382 val = readl_relaxed(base + GITS_CTLR);
1383 if (val & GITS_CTLR_QUIESCENT)
1384 return 0;
1385
1386 /* Disable the generation of all interrupts to this ITS */
1387 val &= ~GITS_CTLR_ENABLE;
1388 writel_relaxed(val, base + GITS_CTLR);
1389
1390 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1391 while (1) {
1392 val = readl_relaxed(base + GITS_CTLR);
1393 if (val & GITS_CTLR_QUIESCENT)
1394 return 0;
1395
1396 count--;
1397 if (!count)
1398 return -EBUSY;
1399
1400 cpu_relax();
1401 udelay(1);
1402 }
1403}
1404
1405static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1406{
1407 struct its_node *its = data;
1408
1409 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1410}
1411
1412static const struct gic_quirk its_quirks[] = {
1413#ifdef CONFIG_CAVIUM_ERRATUM_22375
1414 {
1415 .desc = "ITS: Cavium errata 22375, 24313",
1416 .iidr = 0xa100034c, /* ThunderX pass 1.x */
1417 .mask = 0xffff0fff,
1418 .init = its_enable_quirk_cavium_22375,
1419 },
1420#endif
1421 {
1422 }
1423};
1424
1425static void its_enable_quirks(struct its_node *its)
1426{
1427 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1428
1429 gic_enable_quirks(iidr, its_quirks, its);
1430}
1431
1432static int __init its_probe(struct device_node *node,
1433 struct irq_domain *parent)
1434{
1435 struct resource res;
1436 struct its_node *its;
1437 void __iomem *its_base;
1438 struct irq_domain *inner_domain;
1439 u32 val;
1440 u64 baser, tmp;
1441 int err;
1442
1443 err = of_address_to_resource(node, 0, &res);
1444 if (err) {
1445 pr_warn("%s: no regs?\n", node->full_name);
1446 return -ENXIO;
1447 }
1448
1449 its_base = ioremap(res.start, resource_size(&res));
1450 if (!its_base) {
1451 pr_warn("%s: unable to map registers\n", node->full_name);
1452 return -ENOMEM;
1453 }
1454
1455 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1456 if (val != 0x30 && val != 0x40) {
1457 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1458 err = -ENODEV;
1459 goto out_unmap;
1460 }
1461
1462 err = its_force_quiescent(its_base);
1463 if (err) {
1464 pr_warn("%s: failed to quiesce, giving up\n",
1465 node->full_name);
1466 goto out_unmap;
1467 }
1468
1469 pr_info("ITS: %s\n", node->full_name);
1470
1471 its = kzalloc(sizeof(*its), GFP_KERNEL);
1472 if (!its) {
1473 err = -ENOMEM;
1474 goto out_unmap;
1475 }
1476
1477 raw_spin_lock_init(&its->lock);
1478 INIT_LIST_HEAD(&its->entry);
1479 INIT_LIST_HEAD(&its->its_device_list);
1480 its->base = its_base;
1481 its->phys_base = res.start;
1482 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1483
1484 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1485 if (!its->cmd_base) {
1486 err = -ENOMEM;
1487 goto out_free_its;
1488 }
1489 its->cmd_write = its->cmd_base;
1490
1491 its_enable_quirks(its);
1492
1493 err = its_alloc_tables(node->full_name, its);
1494 if (err)
1495 goto out_free_cmd;
1496
1497 err = its_alloc_collections(its);
1498 if (err)
1499 goto out_free_tables;
1500
1501 baser = (virt_to_phys(its->cmd_base) |
1502 GITS_CBASER_WaWb |
1503 GITS_CBASER_InnerShareable |
1504 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1505 GITS_CBASER_VALID);
1506
1507 writeq_relaxed(baser, its->base + GITS_CBASER);
1508 tmp = readq_relaxed(its->base + GITS_CBASER);
1509
1510 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1511 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1512 /*
1513 * The HW reports non-shareable, we must
1514 * remove the cacheability attributes as
1515 * well.
1516 */
1517 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1518 GITS_CBASER_CACHEABILITY_MASK);
1519 baser |= GITS_CBASER_nC;
1520 writeq_relaxed(baser, its->base + GITS_CBASER);
1521 }
1522 pr_info("ITS: using cache flushing for cmd queue\n");
1523 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1524 }
1525
1526 writeq_relaxed(0, its->base + GITS_CWRITER);
1527 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1528
1529 if (of_property_read_bool(node, "msi-controller")) {
1530 struct msi_domain_info *info;
1531
1532 info = kzalloc(sizeof(*info), GFP_KERNEL);
1533 if (!info) {
1534 err = -ENOMEM;
1535 goto out_free_tables;
1536 }
1537
1538 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1539 if (!inner_domain) {
1540 err = -ENOMEM;
1541 kfree(info);
1542 goto out_free_tables;
1543 }
1544
1545 inner_domain->parent = parent;
1546 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1547 info->ops = &its_msi_domain_ops;
1548 info->data = its;
1549 inner_domain->host_data = info;
1550 }
1551
1552 spin_lock(&its_lock);
1553 list_add(&its->entry, &its_nodes);
1554 spin_unlock(&its_lock);
1555
1556 return 0;
1557
1558out_free_tables:
1559 its_free_tables(its);
1560out_free_cmd:
1561 kfree(its->cmd_base);
1562out_free_its:
1563 kfree(its);
1564out_unmap:
1565 iounmap(its_base);
1566 pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1567 return err;
1568}
1569
1570static bool gic_rdists_supports_plpis(void)
1571{
1572 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1573}
1574
1575int its_cpu_init(void)
1576{
1577 if (!list_empty(&its_nodes)) {
1578 if (!gic_rdists_supports_plpis()) {
1579 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1580 return -ENXIO;
1581 }
1582 its_cpu_init_lpis();
1583 its_cpu_init_collection();
1584 }
1585
1586 return 0;
1587}
1588
1589static struct of_device_id its_device_id[] = {
1590 { .compatible = "arm,gic-v3-its", },
1591 {},
1592};
1593
1594int __init its_init(struct device_node *node, struct rdists *rdists,
1595 struct irq_domain *parent_domain)
1596{
1597 struct device_node *np;
1598
1599 for (np = of_find_matching_node(node, its_device_id); np;
1600 np = of_find_matching_node(np, its_device_id)) {
1601 its_probe(np, parent_domain);
1602 }
1603
1604 if (list_empty(&its_nodes)) {
1605 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1606 return -ENXIO;
1607 }
1608
1609 gic_rdists = rdists;
1610 its_alloc_lpi_tables();
1611 its_lpi_init(rdists->id_bits);
1612
1613 return 0;
1614}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <linux/acpi.h>
8#include <linux/acpi_iort.h>
9#include <linux/bitfield.h>
10#include <linux/bitmap.h>
11#include <linux/cpu.h>
12#include <linux/crash_dump.h>
13#include <linux/delay.h>
14#include <linux/efi.h>
15#include <linux/interrupt.h>
16#include <linux/iommu.h>
17#include <linux/iopoll.h>
18#include <linux/irqdomain.h>
19#include <linux/list.h>
20#include <linux/log2.h>
21#include <linux/memblock.h>
22#include <linux/mm.h>
23#include <linux/msi.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_pci.h>
28#include <linux/of_platform.h>
29#include <linux/percpu.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32
33#include <linux/irqchip.h>
34#include <linux/irqchip/arm-gic-v3.h>
35#include <linux/irqchip/arm-gic-v4.h>
36
37#include <asm/cputype.h>
38#include <asm/exception.h>
39
40#include "irq-gic-common.h"
41
42#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
45#define ITS_FLAGS_FORCE_NON_SHAREABLE (1ULL << 3)
46
47#define RD_LOCAL_LPI_ENABLED BIT(0)
48#define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1)
49#define RD_LOCAL_MEMRESERVE_DONE BIT(2)
50
51static u32 lpi_id_bits;
52
53/*
54 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
55 * deal with (one configuration byte per interrupt). PENDBASE has to
56 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
57 */
58#define LPI_NRBITS lpi_id_bits
59#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
60#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
61
62#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
63
64/*
65 * Collection structure - just an ID, and a redistributor address to
66 * ping. We use one per CPU as a bag of interrupts assigned to this
67 * CPU.
68 */
69struct its_collection {
70 u64 target_address;
71 u16 col_id;
72};
73
74/*
75 * The ITS_BASER structure - contains memory information, cached
76 * value of BASER register configuration and ITS page size.
77 */
78struct its_baser {
79 void *base;
80 u64 val;
81 u32 order;
82 u32 psz;
83};
84
85struct its_device;
86
87/*
88 * The ITS structure - contains most of the infrastructure, with the
89 * top-level MSI domain, the command queue, the collections, and the
90 * list of devices writing to it.
91 *
92 * dev_alloc_lock has to be taken for device allocations, while the
93 * spinlock must be taken to parse data structures such as the device
94 * list.
95 */
96struct its_node {
97 raw_spinlock_t lock;
98 struct mutex dev_alloc_lock;
99 struct list_head entry;
100 void __iomem *base;
101 void __iomem *sgir_base;
102 phys_addr_t phys_base;
103 struct its_cmd_block *cmd_base;
104 struct its_cmd_block *cmd_write;
105 struct its_baser tables[GITS_BASER_NR_REGS];
106 struct its_collection *collections;
107 struct fwnode_handle *fwnode_handle;
108 u64 (*get_msi_base)(struct its_device *its_dev);
109 u64 typer;
110 u64 cbaser_save;
111 u32 ctlr_save;
112 u32 mpidr;
113 struct list_head its_device_list;
114 u64 flags;
115 unsigned long list_nr;
116 int numa_node;
117 unsigned int msi_domain_flags;
118 u32 pre_its_base; /* for Socionext Synquacer */
119 int vlpi_redist_offset;
120};
121
122#define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
123#define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
124#define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
125
126#define ITS_ITT_ALIGN SZ_256
127
128/* The maximum number of VPEID bits supported by VLPI commands */
129#define ITS_MAX_VPEID_BITS \
130 ({ \
131 int nvpeid = 16; \
132 if (gic_rdists->has_rvpeid && \
133 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
134 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
135 GICD_TYPER2_VID); \
136 \
137 nvpeid; \
138 })
139#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
140
141/* Convert page order to size in bytes */
142#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
143
144struct event_lpi_map {
145 unsigned long *lpi_map;
146 u16 *col_map;
147 irq_hw_number_t lpi_base;
148 int nr_lpis;
149 raw_spinlock_t vlpi_lock;
150 struct its_vm *vm;
151 struct its_vlpi_map *vlpi_maps;
152 int nr_vlpis;
153};
154
155/*
156 * The ITS view of a device - belongs to an ITS, owns an interrupt
157 * translation table, and a list of interrupts. If it some of its
158 * LPIs are injected into a guest (GICv4), the event_map.vm field
159 * indicates which one.
160 */
161struct its_device {
162 struct list_head entry;
163 struct its_node *its;
164 struct event_lpi_map event_map;
165 void *itt;
166 u32 nr_ites;
167 u32 device_id;
168 bool shared;
169};
170
171static struct {
172 raw_spinlock_t lock;
173 struct its_device *dev;
174 struct its_vpe **vpes;
175 int next_victim;
176} vpe_proxy;
177
178struct cpu_lpi_count {
179 atomic_t managed;
180 atomic_t unmanaged;
181};
182
183static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
184
185static LIST_HEAD(its_nodes);
186static DEFINE_RAW_SPINLOCK(its_lock);
187static struct rdists *gic_rdists;
188static struct irq_domain *its_parent;
189
190static unsigned long its_list_map;
191static u16 vmovp_seq_num;
192static DEFINE_RAW_SPINLOCK(vmovp_lock);
193
194static DEFINE_IDA(its_vpeid_ida);
195
196#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
197#define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
198#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
199#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
200
201/*
202 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
203 * always have vSGIs mapped.
204 */
205static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
206{
207 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
208}
209
210static bool rdists_support_shareable(void)
211{
212 return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE);
213}
214
215static u16 get_its_list(struct its_vm *vm)
216{
217 struct its_node *its;
218 unsigned long its_list = 0;
219
220 list_for_each_entry(its, &its_nodes, entry) {
221 if (!is_v4(its))
222 continue;
223
224 if (require_its_list_vmovp(vm, its))
225 __set_bit(its->list_nr, &its_list);
226 }
227
228 return (u16)its_list;
229}
230
231static inline u32 its_get_event_id(struct irq_data *d)
232{
233 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
234 return d->hwirq - its_dev->event_map.lpi_base;
235}
236
237static struct its_collection *dev_event_to_col(struct its_device *its_dev,
238 u32 event)
239{
240 struct its_node *its = its_dev->its;
241
242 return its->collections + its_dev->event_map.col_map[event];
243}
244
245static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
246 u32 event)
247{
248 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
249 return NULL;
250
251 return &its_dev->event_map.vlpi_maps[event];
252}
253
254static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
255{
256 if (irqd_is_forwarded_to_vcpu(d)) {
257 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
258 u32 event = its_get_event_id(d);
259
260 return dev_event_to_vlpi_map(its_dev, event);
261 }
262
263 return NULL;
264}
265
266static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
267{
268 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
269 return vpe->col_idx;
270}
271
272static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
273{
274 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
275}
276
277static struct irq_chip its_vpe_irq_chip;
278
279static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
280{
281 struct its_vpe *vpe = NULL;
282 int cpu;
283
284 if (d->chip == &its_vpe_irq_chip) {
285 vpe = irq_data_get_irq_chip_data(d);
286 } else {
287 struct its_vlpi_map *map = get_vlpi_map(d);
288 if (map)
289 vpe = map->vpe;
290 }
291
292 if (vpe) {
293 cpu = vpe_to_cpuid_lock(vpe, flags);
294 } else {
295 /* Physical LPIs are already locked via the irq_desc lock */
296 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
297 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
298 /* Keep GCC quiet... */
299 *flags = 0;
300 }
301
302 return cpu;
303}
304
305static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
306{
307 struct its_vpe *vpe = NULL;
308
309 if (d->chip == &its_vpe_irq_chip) {
310 vpe = irq_data_get_irq_chip_data(d);
311 } else {
312 struct its_vlpi_map *map = get_vlpi_map(d);
313 if (map)
314 vpe = map->vpe;
315 }
316
317 if (vpe)
318 vpe_to_cpuid_unlock(vpe, flags);
319}
320
321static struct its_collection *valid_col(struct its_collection *col)
322{
323 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
324 return NULL;
325
326 return col;
327}
328
329static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
330{
331 if (valid_col(its->collections + vpe->col_idx))
332 return vpe;
333
334 return NULL;
335}
336
337/*
338 * ITS command descriptors - parameters to be encoded in a command
339 * block.
340 */
341struct its_cmd_desc {
342 union {
343 struct {
344 struct its_device *dev;
345 u32 event_id;
346 } its_inv_cmd;
347
348 struct {
349 struct its_device *dev;
350 u32 event_id;
351 } its_clear_cmd;
352
353 struct {
354 struct its_device *dev;
355 u32 event_id;
356 } its_int_cmd;
357
358 struct {
359 struct its_device *dev;
360 int valid;
361 } its_mapd_cmd;
362
363 struct {
364 struct its_collection *col;
365 int valid;
366 } its_mapc_cmd;
367
368 struct {
369 struct its_device *dev;
370 u32 phys_id;
371 u32 event_id;
372 } its_mapti_cmd;
373
374 struct {
375 struct its_device *dev;
376 struct its_collection *col;
377 u32 event_id;
378 } its_movi_cmd;
379
380 struct {
381 struct its_device *dev;
382 u32 event_id;
383 } its_discard_cmd;
384
385 struct {
386 struct its_collection *col;
387 } its_invall_cmd;
388
389 struct {
390 struct its_vpe *vpe;
391 } its_vinvall_cmd;
392
393 struct {
394 struct its_vpe *vpe;
395 struct its_collection *col;
396 bool valid;
397 } its_vmapp_cmd;
398
399 struct {
400 struct its_vpe *vpe;
401 struct its_device *dev;
402 u32 virt_id;
403 u32 event_id;
404 bool db_enabled;
405 } its_vmapti_cmd;
406
407 struct {
408 struct its_vpe *vpe;
409 struct its_device *dev;
410 u32 event_id;
411 bool db_enabled;
412 } its_vmovi_cmd;
413
414 struct {
415 struct its_vpe *vpe;
416 struct its_collection *col;
417 u16 seq_num;
418 u16 its_list;
419 } its_vmovp_cmd;
420
421 struct {
422 struct its_vpe *vpe;
423 } its_invdb_cmd;
424
425 struct {
426 struct its_vpe *vpe;
427 u8 sgi;
428 u8 priority;
429 bool enable;
430 bool group;
431 bool clear;
432 } its_vsgi_cmd;
433 };
434};
435
436/*
437 * The ITS command block, which is what the ITS actually parses.
438 */
439struct its_cmd_block {
440 union {
441 u64 raw_cmd[4];
442 __le64 raw_cmd_le[4];
443 };
444};
445
446#define ITS_CMD_QUEUE_SZ SZ_64K
447#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
448
449typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
450 struct its_cmd_block *,
451 struct its_cmd_desc *);
452
453typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
454 struct its_cmd_block *,
455 struct its_cmd_desc *);
456
457static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
458{
459 u64 mask = GENMASK_ULL(h, l);
460 *raw_cmd &= ~mask;
461 *raw_cmd |= (val << l) & mask;
462}
463
464static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
465{
466 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
467}
468
469static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
470{
471 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
472}
473
474static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
475{
476 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
477}
478
479static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
480{
481 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
482}
483
484static void its_encode_size(struct its_cmd_block *cmd, u8 size)
485{
486 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
487}
488
489static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
490{
491 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
492}
493
494static void its_encode_valid(struct its_cmd_block *cmd, int valid)
495{
496 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
497}
498
499static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
500{
501 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
502}
503
504static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
505{
506 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
507}
508
509static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
510{
511 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
512}
513
514static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
515{
516 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
517}
518
519static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
520{
521 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
522}
523
524static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
525{
526 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
527}
528
529static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
530{
531 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
532}
533
534static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
535{
536 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
537}
538
539static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
540{
541 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
542}
543
544static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
545{
546 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
547}
548
549static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
550{
551 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
552}
553
554static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
555{
556 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
557}
558
559static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
560{
561 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
562}
563
564static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
565 u32 vpe_db_lpi)
566{
567 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
568}
569
570static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
571 u32 vpe_db_lpi)
572{
573 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
574}
575
576static void its_encode_db(struct its_cmd_block *cmd, bool db)
577{
578 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
579}
580
581static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
582{
583 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
584}
585
586static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
587{
588 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
589}
590
591static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
592{
593 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
594}
595
596static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
597{
598 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
599}
600
601static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
602{
603 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
604}
605
606static inline void its_fixup_cmd(struct its_cmd_block *cmd)
607{
608 /* Let's fixup BE commands */
609 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
610 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
611 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
612 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
613}
614
615static struct its_collection *its_build_mapd_cmd(struct its_node *its,
616 struct its_cmd_block *cmd,
617 struct its_cmd_desc *desc)
618{
619 unsigned long itt_addr;
620 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
621
622 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
623 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
624
625 its_encode_cmd(cmd, GITS_CMD_MAPD);
626 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
627 its_encode_size(cmd, size - 1);
628 its_encode_itt(cmd, itt_addr);
629 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
630
631 its_fixup_cmd(cmd);
632
633 return NULL;
634}
635
636static struct its_collection *its_build_mapc_cmd(struct its_node *its,
637 struct its_cmd_block *cmd,
638 struct its_cmd_desc *desc)
639{
640 its_encode_cmd(cmd, GITS_CMD_MAPC);
641 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
642 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
643 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
644
645 its_fixup_cmd(cmd);
646
647 return desc->its_mapc_cmd.col;
648}
649
650static struct its_collection *its_build_mapti_cmd(struct its_node *its,
651 struct its_cmd_block *cmd,
652 struct its_cmd_desc *desc)
653{
654 struct its_collection *col;
655
656 col = dev_event_to_col(desc->its_mapti_cmd.dev,
657 desc->its_mapti_cmd.event_id);
658
659 its_encode_cmd(cmd, GITS_CMD_MAPTI);
660 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
661 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
662 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
663 its_encode_collection(cmd, col->col_id);
664
665 its_fixup_cmd(cmd);
666
667 return valid_col(col);
668}
669
670static struct its_collection *its_build_movi_cmd(struct its_node *its,
671 struct its_cmd_block *cmd,
672 struct its_cmd_desc *desc)
673{
674 struct its_collection *col;
675
676 col = dev_event_to_col(desc->its_movi_cmd.dev,
677 desc->its_movi_cmd.event_id);
678
679 its_encode_cmd(cmd, GITS_CMD_MOVI);
680 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
681 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
682 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
683
684 its_fixup_cmd(cmd);
685
686 return valid_col(col);
687}
688
689static struct its_collection *its_build_discard_cmd(struct its_node *its,
690 struct its_cmd_block *cmd,
691 struct its_cmd_desc *desc)
692{
693 struct its_collection *col;
694
695 col = dev_event_to_col(desc->its_discard_cmd.dev,
696 desc->its_discard_cmd.event_id);
697
698 its_encode_cmd(cmd, GITS_CMD_DISCARD);
699 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
700 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
701
702 its_fixup_cmd(cmd);
703
704 return valid_col(col);
705}
706
707static struct its_collection *its_build_inv_cmd(struct its_node *its,
708 struct its_cmd_block *cmd,
709 struct its_cmd_desc *desc)
710{
711 struct its_collection *col;
712
713 col = dev_event_to_col(desc->its_inv_cmd.dev,
714 desc->its_inv_cmd.event_id);
715
716 its_encode_cmd(cmd, GITS_CMD_INV);
717 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
718 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
719
720 its_fixup_cmd(cmd);
721
722 return valid_col(col);
723}
724
725static struct its_collection *its_build_int_cmd(struct its_node *its,
726 struct its_cmd_block *cmd,
727 struct its_cmd_desc *desc)
728{
729 struct its_collection *col;
730
731 col = dev_event_to_col(desc->its_int_cmd.dev,
732 desc->its_int_cmd.event_id);
733
734 its_encode_cmd(cmd, GITS_CMD_INT);
735 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
736 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
737
738 its_fixup_cmd(cmd);
739
740 return valid_col(col);
741}
742
743static struct its_collection *its_build_clear_cmd(struct its_node *its,
744 struct its_cmd_block *cmd,
745 struct its_cmd_desc *desc)
746{
747 struct its_collection *col;
748
749 col = dev_event_to_col(desc->its_clear_cmd.dev,
750 desc->its_clear_cmd.event_id);
751
752 its_encode_cmd(cmd, GITS_CMD_CLEAR);
753 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
754 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
755
756 its_fixup_cmd(cmd);
757
758 return valid_col(col);
759}
760
761static struct its_collection *its_build_invall_cmd(struct its_node *its,
762 struct its_cmd_block *cmd,
763 struct its_cmd_desc *desc)
764{
765 its_encode_cmd(cmd, GITS_CMD_INVALL);
766 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
767
768 its_fixup_cmd(cmd);
769
770 return desc->its_invall_cmd.col;
771}
772
773static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
774 struct its_cmd_block *cmd,
775 struct its_cmd_desc *desc)
776{
777 its_encode_cmd(cmd, GITS_CMD_VINVALL);
778 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
779
780 its_fixup_cmd(cmd);
781
782 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
783}
784
785static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
786 struct its_cmd_block *cmd,
787 struct its_cmd_desc *desc)
788{
789 struct its_vpe *vpe = valid_vpe(its, desc->its_vmapp_cmd.vpe);
790 unsigned long vpt_addr, vconf_addr;
791 u64 target;
792 bool alloc;
793
794 its_encode_cmd(cmd, GITS_CMD_VMAPP);
795 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
796 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
797
798 if (!desc->its_vmapp_cmd.valid) {
799 if (is_v4_1(its)) {
800 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
801 its_encode_alloc(cmd, alloc);
802 /*
803 * Unmapping a VPE is self-synchronizing on GICv4.1,
804 * no need to issue a VSYNC.
805 */
806 vpe = NULL;
807 }
808
809 goto out;
810 }
811
812 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
813 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
814
815 its_encode_target(cmd, target);
816 its_encode_vpt_addr(cmd, vpt_addr);
817 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
818
819 if (!is_v4_1(its))
820 goto out;
821
822 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
823
824 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
825
826 its_encode_alloc(cmd, alloc);
827
828 /*
829 * GICv4.1 provides a way to get the VLPI state, which needs the vPE
830 * to be unmapped first, and in this case, we may remap the vPE
831 * back while the VPT is not empty. So we can't assume that the
832 * VPT is empty on map. This is why we never advertise PTZ.
833 */
834 its_encode_ptz(cmd, false);
835 its_encode_vconf_addr(cmd, vconf_addr);
836 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
837
838out:
839 its_fixup_cmd(cmd);
840
841 return vpe;
842}
843
844static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
845 struct its_cmd_block *cmd,
846 struct its_cmd_desc *desc)
847{
848 u32 db;
849
850 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
851 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
852 else
853 db = 1023;
854
855 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
856 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
857 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
858 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
859 its_encode_db_phys_id(cmd, db);
860 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
861
862 its_fixup_cmd(cmd);
863
864 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
865}
866
867static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
868 struct its_cmd_block *cmd,
869 struct its_cmd_desc *desc)
870{
871 u32 db;
872
873 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
874 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
875 else
876 db = 1023;
877
878 its_encode_cmd(cmd, GITS_CMD_VMOVI);
879 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
880 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
881 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
882 its_encode_db_phys_id(cmd, db);
883 its_encode_db_valid(cmd, true);
884
885 its_fixup_cmd(cmd);
886
887 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
888}
889
890static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
891 struct its_cmd_block *cmd,
892 struct its_cmd_desc *desc)
893{
894 u64 target;
895
896 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
897 its_encode_cmd(cmd, GITS_CMD_VMOVP);
898 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
899 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
900 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
901 its_encode_target(cmd, target);
902
903 if (is_v4_1(its)) {
904 its_encode_db(cmd, true);
905 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
906 }
907
908 its_fixup_cmd(cmd);
909
910 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
911}
912
913static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
914 struct its_cmd_block *cmd,
915 struct its_cmd_desc *desc)
916{
917 struct its_vlpi_map *map;
918
919 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
920 desc->its_inv_cmd.event_id);
921
922 its_encode_cmd(cmd, GITS_CMD_INV);
923 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
924 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
925
926 its_fixup_cmd(cmd);
927
928 return valid_vpe(its, map->vpe);
929}
930
931static struct its_vpe *its_build_vint_cmd(struct its_node *its,
932 struct its_cmd_block *cmd,
933 struct its_cmd_desc *desc)
934{
935 struct its_vlpi_map *map;
936
937 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
938 desc->its_int_cmd.event_id);
939
940 its_encode_cmd(cmd, GITS_CMD_INT);
941 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
942 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
943
944 its_fixup_cmd(cmd);
945
946 return valid_vpe(its, map->vpe);
947}
948
949static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
950 struct its_cmd_block *cmd,
951 struct its_cmd_desc *desc)
952{
953 struct its_vlpi_map *map;
954
955 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
956 desc->its_clear_cmd.event_id);
957
958 its_encode_cmd(cmd, GITS_CMD_CLEAR);
959 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
960 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
961
962 its_fixup_cmd(cmd);
963
964 return valid_vpe(its, map->vpe);
965}
966
967static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
968 struct its_cmd_block *cmd,
969 struct its_cmd_desc *desc)
970{
971 if (WARN_ON(!is_v4_1(its)))
972 return NULL;
973
974 its_encode_cmd(cmd, GITS_CMD_INVDB);
975 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
976
977 its_fixup_cmd(cmd);
978
979 return valid_vpe(its, desc->its_invdb_cmd.vpe);
980}
981
982static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
983 struct its_cmd_block *cmd,
984 struct its_cmd_desc *desc)
985{
986 if (WARN_ON(!is_v4_1(its)))
987 return NULL;
988
989 its_encode_cmd(cmd, GITS_CMD_VSGI);
990 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
991 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
992 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
993 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
994 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
995 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
996
997 its_fixup_cmd(cmd);
998
999 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
1000}
1001
1002static u64 its_cmd_ptr_to_offset(struct its_node *its,
1003 struct its_cmd_block *ptr)
1004{
1005 return (ptr - its->cmd_base) * sizeof(*ptr);
1006}
1007
1008static int its_queue_full(struct its_node *its)
1009{
1010 int widx;
1011 int ridx;
1012
1013 widx = its->cmd_write - its->cmd_base;
1014 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
1015
1016 /* This is incredibly unlikely to happen, unless the ITS locks up. */
1017 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
1018 return 1;
1019
1020 return 0;
1021}
1022
1023static struct its_cmd_block *its_allocate_entry(struct its_node *its)
1024{
1025 struct its_cmd_block *cmd;
1026 u32 count = 1000000; /* 1s! */
1027
1028 while (its_queue_full(its)) {
1029 count--;
1030 if (!count) {
1031 pr_err_ratelimited("ITS queue not draining\n");
1032 return NULL;
1033 }
1034 cpu_relax();
1035 udelay(1);
1036 }
1037
1038 cmd = its->cmd_write++;
1039
1040 /* Handle queue wrapping */
1041 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1042 its->cmd_write = its->cmd_base;
1043
1044 /* Clear command */
1045 cmd->raw_cmd[0] = 0;
1046 cmd->raw_cmd[1] = 0;
1047 cmd->raw_cmd[2] = 0;
1048 cmd->raw_cmd[3] = 0;
1049
1050 return cmd;
1051}
1052
1053static struct its_cmd_block *its_post_commands(struct its_node *its)
1054{
1055 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1056
1057 writel_relaxed(wr, its->base + GITS_CWRITER);
1058
1059 return its->cmd_write;
1060}
1061
1062static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1063{
1064 /*
1065 * Make sure the commands written to memory are observable by
1066 * the ITS.
1067 */
1068 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1069 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1070 else
1071 dsb(ishst);
1072}
1073
1074static int its_wait_for_range_completion(struct its_node *its,
1075 u64 prev_idx,
1076 struct its_cmd_block *to)
1077{
1078 u64 rd_idx, to_idx, linear_idx;
1079 u32 count = 1000000; /* 1s! */
1080
1081 /* Linearize to_idx if the command set has wrapped around */
1082 to_idx = its_cmd_ptr_to_offset(its, to);
1083 if (to_idx < prev_idx)
1084 to_idx += ITS_CMD_QUEUE_SZ;
1085
1086 linear_idx = prev_idx;
1087
1088 while (1) {
1089 s64 delta;
1090
1091 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1092
1093 /*
1094 * Compute the read pointer progress, taking the
1095 * potential wrap-around into account.
1096 */
1097 delta = rd_idx - prev_idx;
1098 if (rd_idx < prev_idx)
1099 delta += ITS_CMD_QUEUE_SZ;
1100
1101 linear_idx += delta;
1102 if (linear_idx >= to_idx)
1103 break;
1104
1105 count--;
1106 if (!count) {
1107 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1108 to_idx, linear_idx);
1109 return -1;
1110 }
1111 prev_idx = rd_idx;
1112 cpu_relax();
1113 udelay(1);
1114 }
1115
1116 return 0;
1117}
1118
1119/* Warning, macro hell follows */
1120#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1121void name(struct its_node *its, \
1122 buildtype builder, \
1123 struct its_cmd_desc *desc) \
1124{ \
1125 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1126 synctype *sync_obj; \
1127 unsigned long flags; \
1128 u64 rd_idx; \
1129 \
1130 raw_spin_lock_irqsave(&its->lock, flags); \
1131 \
1132 cmd = its_allocate_entry(its); \
1133 if (!cmd) { /* We're soooooo screewed... */ \
1134 raw_spin_unlock_irqrestore(&its->lock, flags); \
1135 return; \
1136 } \
1137 sync_obj = builder(its, cmd, desc); \
1138 its_flush_cmd(its, cmd); \
1139 \
1140 if (sync_obj) { \
1141 sync_cmd = its_allocate_entry(its); \
1142 if (!sync_cmd) \
1143 goto post; \
1144 \
1145 buildfn(its, sync_cmd, sync_obj); \
1146 its_flush_cmd(its, sync_cmd); \
1147 } \
1148 \
1149post: \
1150 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1151 next_cmd = its_post_commands(its); \
1152 raw_spin_unlock_irqrestore(&its->lock, flags); \
1153 \
1154 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1155 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1156}
1157
1158static void its_build_sync_cmd(struct its_node *its,
1159 struct its_cmd_block *sync_cmd,
1160 struct its_collection *sync_col)
1161{
1162 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1163 its_encode_target(sync_cmd, sync_col->target_address);
1164
1165 its_fixup_cmd(sync_cmd);
1166}
1167
1168static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1169 struct its_collection, its_build_sync_cmd)
1170
1171static void its_build_vsync_cmd(struct its_node *its,
1172 struct its_cmd_block *sync_cmd,
1173 struct its_vpe *sync_vpe)
1174{
1175 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1176 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1177
1178 its_fixup_cmd(sync_cmd);
1179}
1180
1181static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1182 struct its_vpe, its_build_vsync_cmd)
1183
1184static void its_send_int(struct its_device *dev, u32 event_id)
1185{
1186 struct its_cmd_desc desc;
1187
1188 desc.its_int_cmd.dev = dev;
1189 desc.its_int_cmd.event_id = event_id;
1190
1191 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1192}
1193
1194static void its_send_clear(struct its_device *dev, u32 event_id)
1195{
1196 struct its_cmd_desc desc;
1197
1198 desc.its_clear_cmd.dev = dev;
1199 desc.its_clear_cmd.event_id = event_id;
1200
1201 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1202}
1203
1204static void its_send_inv(struct its_device *dev, u32 event_id)
1205{
1206 struct its_cmd_desc desc;
1207
1208 desc.its_inv_cmd.dev = dev;
1209 desc.its_inv_cmd.event_id = event_id;
1210
1211 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1212}
1213
1214static void its_send_mapd(struct its_device *dev, int valid)
1215{
1216 struct its_cmd_desc desc;
1217
1218 desc.its_mapd_cmd.dev = dev;
1219 desc.its_mapd_cmd.valid = !!valid;
1220
1221 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1222}
1223
1224static void its_send_mapc(struct its_node *its, struct its_collection *col,
1225 int valid)
1226{
1227 struct its_cmd_desc desc;
1228
1229 desc.its_mapc_cmd.col = col;
1230 desc.its_mapc_cmd.valid = !!valid;
1231
1232 its_send_single_command(its, its_build_mapc_cmd, &desc);
1233}
1234
1235static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1236{
1237 struct its_cmd_desc desc;
1238
1239 desc.its_mapti_cmd.dev = dev;
1240 desc.its_mapti_cmd.phys_id = irq_id;
1241 desc.its_mapti_cmd.event_id = id;
1242
1243 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1244}
1245
1246static void its_send_movi(struct its_device *dev,
1247 struct its_collection *col, u32 id)
1248{
1249 struct its_cmd_desc desc;
1250
1251 desc.its_movi_cmd.dev = dev;
1252 desc.its_movi_cmd.col = col;
1253 desc.its_movi_cmd.event_id = id;
1254
1255 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1256}
1257
1258static void its_send_discard(struct its_device *dev, u32 id)
1259{
1260 struct its_cmd_desc desc;
1261
1262 desc.its_discard_cmd.dev = dev;
1263 desc.its_discard_cmd.event_id = id;
1264
1265 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1266}
1267
1268static void its_send_invall(struct its_node *its, struct its_collection *col)
1269{
1270 struct its_cmd_desc desc;
1271
1272 desc.its_invall_cmd.col = col;
1273
1274 its_send_single_command(its, its_build_invall_cmd, &desc);
1275}
1276
1277static void its_send_vmapti(struct its_device *dev, u32 id)
1278{
1279 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1280 struct its_cmd_desc desc;
1281
1282 desc.its_vmapti_cmd.vpe = map->vpe;
1283 desc.its_vmapti_cmd.dev = dev;
1284 desc.its_vmapti_cmd.virt_id = map->vintid;
1285 desc.its_vmapti_cmd.event_id = id;
1286 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1287
1288 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1289}
1290
1291static void its_send_vmovi(struct its_device *dev, u32 id)
1292{
1293 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1294 struct its_cmd_desc desc;
1295
1296 desc.its_vmovi_cmd.vpe = map->vpe;
1297 desc.its_vmovi_cmd.dev = dev;
1298 desc.its_vmovi_cmd.event_id = id;
1299 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1300
1301 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1302}
1303
1304static void its_send_vmapp(struct its_node *its,
1305 struct its_vpe *vpe, bool valid)
1306{
1307 struct its_cmd_desc desc;
1308
1309 desc.its_vmapp_cmd.vpe = vpe;
1310 desc.its_vmapp_cmd.valid = valid;
1311 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1312
1313 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1314}
1315
1316static void its_send_vmovp(struct its_vpe *vpe)
1317{
1318 struct its_cmd_desc desc = {};
1319 struct its_node *its;
1320 unsigned long flags;
1321 int col_id = vpe->col_idx;
1322
1323 desc.its_vmovp_cmd.vpe = vpe;
1324
1325 if (!its_list_map) {
1326 its = list_first_entry(&its_nodes, struct its_node, entry);
1327 desc.its_vmovp_cmd.col = &its->collections[col_id];
1328 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1329 return;
1330 }
1331
1332 /*
1333 * Yet another marvel of the architecture. If using the
1334 * its_list "feature", we need to make sure that all ITSs
1335 * receive all VMOVP commands in the same order. The only way
1336 * to guarantee this is to make vmovp a serialization point.
1337 *
1338 * Wall <-- Head.
1339 */
1340 raw_spin_lock_irqsave(&vmovp_lock, flags);
1341
1342 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1343 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1344
1345 /* Emit VMOVPs */
1346 list_for_each_entry(its, &its_nodes, entry) {
1347 if (!is_v4(its))
1348 continue;
1349
1350 if (!require_its_list_vmovp(vpe->its_vm, its))
1351 continue;
1352
1353 desc.its_vmovp_cmd.col = &its->collections[col_id];
1354 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1355 }
1356
1357 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1358}
1359
1360static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1361{
1362 struct its_cmd_desc desc;
1363
1364 desc.its_vinvall_cmd.vpe = vpe;
1365 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1366}
1367
1368static void its_send_vinv(struct its_device *dev, u32 event_id)
1369{
1370 struct its_cmd_desc desc;
1371
1372 /*
1373 * There is no real VINV command. This is just a normal INV,
1374 * with a VSYNC instead of a SYNC.
1375 */
1376 desc.its_inv_cmd.dev = dev;
1377 desc.its_inv_cmd.event_id = event_id;
1378
1379 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1380}
1381
1382static void its_send_vint(struct its_device *dev, u32 event_id)
1383{
1384 struct its_cmd_desc desc;
1385
1386 /*
1387 * There is no real VINT command. This is just a normal INT,
1388 * with a VSYNC instead of a SYNC.
1389 */
1390 desc.its_int_cmd.dev = dev;
1391 desc.its_int_cmd.event_id = event_id;
1392
1393 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1394}
1395
1396static void its_send_vclear(struct its_device *dev, u32 event_id)
1397{
1398 struct its_cmd_desc desc;
1399
1400 /*
1401 * There is no real VCLEAR command. This is just a normal CLEAR,
1402 * with a VSYNC instead of a SYNC.
1403 */
1404 desc.its_clear_cmd.dev = dev;
1405 desc.its_clear_cmd.event_id = event_id;
1406
1407 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1408}
1409
1410static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1411{
1412 struct its_cmd_desc desc;
1413
1414 desc.its_invdb_cmd.vpe = vpe;
1415 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1416}
1417
1418/*
1419 * irqchip functions - assumes MSI, mostly.
1420 */
1421static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1422{
1423 struct its_vlpi_map *map = get_vlpi_map(d);
1424 irq_hw_number_t hwirq;
1425 void *va;
1426 u8 *cfg;
1427
1428 if (map) {
1429 va = page_address(map->vm->vprop_page);
1430 hwirq = map->vintid;
1431
1432 /* Remember the updated property */
1433 map->properties &= ~clr;
1434 map->properties |= set | LPI_PROP_GROUP1;
1435 } else {
1436 va = gic_rdists->prop_table_va;
1437 hwirq = d->hwirq;
1438 }
1439
1440 cfg = va + hwirq - 8192;
1441 *cfg &= ~clr;
1442 *cfg |= set | LPI_PROP_GROUP1;
1443
1444 /*
1445 * Make the above write visible to the redistributors.
1446 * And yes, we're flushing exactly: One. Single. Byte.
1447 * Humpf...
1448 */
1449 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1450 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1451 else
1452 dsb(ishst);
1453}
1454
1455static void wait_for_syncr(void __iomem *rdbase)
1456{
1457 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1458 cpu_relax();
1459}
1460
1461static void __direct_lpi_inv(struct irq_data *d, u64 val)
1462{
1463 void __iomem *rdbase;
1464 unsigned long flags;
1465 int cpu;
1466
1467 /* Target the redistributor this LPI is currently routed to */
1468 cpu = irq_to_cpuid_lock(d, &flags);
1469 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1470
1471 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1472 gic_write_lpir(val, rdbase + GICR_INVLPIR);
1473 wait_for_syncr(rdbase);
1474
1475 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1476 irq_to_cpuid_unlock(d, flags);
1477}
1478
1479static void direct_lpi_inv(struct irq_data *d)
1480{
1481 struct its_vlpi_map *map = get_vlpi_map(d);
1482 u64 val;
1483
1484 if (map) {
1485 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1486
1487 WARN_ON(!is_v4_1(its_dev->its));
1488
1489 val = GICR_INVLPIR_V;
1490 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1491 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1492 } else {
1493 val = d->hwirq;
1494 }
1495
1496 __direct_lpi_inv(d, val);
1497}
1498
1499static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1500{
1501 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1502
1503 lpi_write_config(d, clr, set);
1504 if (gic_rdists->has_direct_lpi &&
1505 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1506 direct_lpi_inv(d);
1507 else if (!irqd_is_forwarded_to_vcpu(d))
1508 its_send_inv(its_dev, its_get_event_id(d));
1509 else
1510 its_send_vinv(its_dev, its_get_event_id(d));
1511}
1512
1513static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1514{
1515 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1516 u32 event = its_get_event_id(d);
1517 struct its_vlpi_map *map;
1518
1519 /*
1520 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1521 * here.
1522 */
1523 if (is_v4_1(its_dev->its))
1524 return;
1525
1526 map = dev_event_to_vlpi_map(its_dev, event);
1527
1528 if (map->db_enabled == enable)
1529 return;
1530
1531 map->db_enabled = enable;
1532
1533 /*
1534 * More fun with the architecture:
1535 *
1536 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1537 * value or to 1023, depending on the enable bit. But that
1538 * would be issuing a mapping for an /existing/ DevID+EventID
1539 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1540 * to the /same/ vPE, using this opportunity to adjust the
1541 * doorbell. Mouahahahaha. We loves it, Precious.
1542 */
1543 its_send_vmovi(its_dev, event);
1544}
1545
1546static void its_mask_irq(struct irq_data *d)
1547{
1548 if (irqd_is_forwarded_to_vcpu(d))
1549 its_vlpi_set_doorbell(d, false);
1550
1551 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1552}
1553
1554static void its_unmask_irq(struct irq_data *d)
1555{
1556 if (irqd_is_forwarded_to_vcpu(d))
1557 its_vlpi_set_doorbell(d, true);
1558
1559 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1560}
1561
1562static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1563{
1564 if (irqd_affinity_is_managed(d))
1565 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1566
1567 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1568}
1569
1570static void its_inc_lpi_count(struct irq_data *d, int cpu)
1571{
1572 if (irqd_affinity_is_managed(d))
1573 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1574 else
1575 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1576}
1577
1578static void its_dec_lpi_count(struct irq_data *d, int cpu)
1579{
1580 if (irqd_affinity_is_managed(d))
1581 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1582 else
1583 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1584}
1585
1586static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1587 const struct cpumask *cpu_mask)
1588{
1589 unsigned int cpu = nr_cpu_ids, tmp;
1590 int count = S32_MAX;
1591
1592 for_each_cpu(tmp, cpu_mask) {
1593 int this_count = its_read_lpi_count(d, tmp);
1594 if (this_count < count) {
1595 cpu = tmp;
1596 count = this_count;
1597 }
1598 }
1599
1600 return cpu;
1601}
1602
1603/*
1604 * As suggested by Thomas Gleixner in:
1605 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1606 */
1607static int its_select_cpu(struct irq_data *d,
1608 const struct cpumask *aff_mask)
1609{
1610 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1611 static DEFINE_RAW_SPINLOCK(tmpmask_lock);
1612 static struct cpumask __tmpmask;
1613 struct cpumask *tmpmask;
1614 unsigned long flags;
1615 int cpu, node;
1616 node = its_dev->its->numa_node;
1617 tmpmask = &__tmpmask;
1618
1619 raw_spin_lock_irqsave(&tmpmask_lock, flags);
1620
1621 if (!irqd_affinity_is_managed(d)) {
1622 /* First try the NUMA node */
1623 if (node != NUMA_NO_NODE) {
1624 /*
1625 * Try the intersection of the affinity mask and the
1626 * node mask (and the online mask, just to be safe).
1627 */
1628 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1629 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1630
1631 /*
1632 * Ideally, we would check if the mask is empty, and
1633 * try again on the full node here.
1634 *
1635 * But it turns out that the way ACPI describes the
1636 * affinity for ITSs only deals about memory, and
1637 * not target CPUs, so it cannot describe a single
1638 * ITS placed next to two NUMA nodes.
1639 *
1640 * Instead, just fallback on the online mask. This
1641 * diverges from Thomas' suggestion above.
1642 */
1643 cpu = cpumask_pick_least_loaded(d, tmpmask);
1644 if (cpu < nr_cpu_ids)
1645 goto out;
1646
1647 /* If we can't cross sockets, give up */
1648 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1649 goto out;
1650
1651 /* If the above failed, expand the search */
1652 }
1653
1654 /* Try the intersection of the affinity and online masks */
1655 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1656
1657 /* If that doesn't fly, the online mask is the last resort */
1658 if (cpumask_empty(tmpmask))
1659 cpumask_copy(tmpmask, cpu_online_mask);
1660
1661 cpu = cpumask_pick_least_loaded(d, tmpmask);
1662 } else {
1663 cpumask_copy(tmpmask, aff_mask);
1664
1665 /* If we cannot cross sockets, limit the search to that node */
1666 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1667 node != NUMA_NO_NODE)
1668 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1669
1670 cpu = cpumask_pick_least_loaded(d, tmpmask);
1671 }
1672out:
1673 raw_spin_unlock_irqrestore(&tmpmask_lock, flags);
1674
1675 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1676 return cpu;
1677}
1678
1679static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1680 bool force)
1681{
1682 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1683 struct its_collection *target_col;
1684 u32 id = its_get_event_id(d);
1685 int cpu, prev_cpu;
1686
1687 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1688 if (irqd_is_forwarded_to_vcpu(d))
1689 return -EINVAL;
1690
1691 prev_cpu = its_dev->event_map.col_map[id];
1692 its_dec_lpi_count(d, prev_cpu);
1693
1694 if (!force)
1695 cpu = its_select_cpu(d, mask_val);
1696 else
1697 cpu = cpumask_pick_least_loaded(d, mask_val);
1698
1699 if (cpu < 0 || cpu >= nr_cpu_ids)
1700 goto err;
1701
1702 /* don't set the affinity when the target cpu is same as current one */
1703 if (cpu != prev_cpu) {
1704 target_col = &its_dev->its->collections[cpu];
1705 its_send_movi(its_dev, target_col, id);
1706 its_dev->event_map.col_map[id] = cpu;
1707 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1708 }
1709
1710 its_inc_lpi_count(d, cpu);
1711
1712 return IRQ_SET_MASK_OK_DONE;
1713
1714err:
1715 its_inc_lpi_count(d, prev_cpu);
1716 return -EINVAL;
1717}
1718
1719static u64 its_irq_get_msi_base(struct its_device *its_dev)
1720{
1721 struct its_node *its = its_dev->its;
1722
1723 return its->phys_base + GITS_TRANSLATER;
1724}
1725
1726static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1727{
1728 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1729 struct its_node *its;
1730 u64 addr;
1731
1732 its = its_dev->its;
1733 addr = its->get_msi_base(its_dev);
1734
1735 msg->address_lo = lower_32_bits(addr);
1736 msg->address_hi = upper_32_bits(addr);
1737 msg->data = its_get_event_id(d);
1738
1739 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1740}
1741
1742static int its_irq_set_irqchip_state(struct irq_data *d,
1743 enum irqchip_irq_state which,
1744 bool state)
1745{
1746 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1747 u32 event = its_get_event_id(d);
1748
1749 if (which != IRQCHIP_STATE_PENDING)
1750 return -EINVAL;
1751
1752 if (irqd_is_forwarded_to_vcpu(d)) {
1753 if (state)
1754 its_send_vint(its_dev, event);
1755 else
1756 its_send_vclear(its_dev, event);
1757 } else {
1758 if (state)
1759 its_send_int(its_dev, event);
1760 else
1761 its_send_clear(its_dev, event);
1762 }
1763
1764 return 0;
1765}
1766
1767static int its_irq_retrigger(struct irq_data *d)
1768{
1769 return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1770}
1771
1772/*
1773 * Two favourable cases:
1774 *
1775 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1776 * for vSGI delivery
1777 *
1778 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1779 * and we're better off mapping all VPEs always
1780 *
1781 * If neither (a) nor (b) is true, then we map vPEs on demand.
1782 *
1783 */
1784static bool gic_requires_eager_mapping(void)
1785{
1786 if (!its_list_map || gic_rdists->has_rvpeid)
1787 return true;
1788
1789 return false;
1790}
1791
1792static void its_map_vm(struct its_node *its, struct its_vm *vm)
1793{
1794 unsigned long flags;
1795
1796 if (gic_requires_eager_mapping())
1797 return;
1798
1799 raw_spin_lock_irqsave(&vmovp_lock, flags);
1800
1801 /*
1802 * If the VM wasn't mapped yet, iterate over the vpes and get
1803 * them mapped now.
1804 */
1805 vm->vlpi_count[its->list_nr]++;
1806
1807 if (vm->vlpi_count[its->list_nr] == 1) {
1808 int i;
1809
1810 for (i = 0; i < vm->nr_vpes; i++) {
1811 struct its_vpe *vpe = vm->vpes[i];
1812 struct irq_data *d = irq_get_irq_data(vpe->irq);
1813
1814 /* Map the VPE to the first possible CPU */
1815 vpe->col_idx = cpumask_first(cpu_online_mask);
1816 its_send_vmapp(its, vpe, true);
1817 its_send_vinvall(its, vpe);
1818 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1819 }
1820 }
1821
1822 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1823}
1824
1825static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1826{
1827 unsigned long flags;
1828
1829 /* Not using the ITS list? Everything is always mapped. */
1830 if (gic_requires_eager_mapping())
1831 return;
1832
1833 raw_spin_lock_irqsave(&vmovp_lock, flags);
1834
1835 if (!--vm->vlpi_count[its->list_nr]) {
1836 int i;
1837
1838 for (i = 0; i < vm->nr_vpes; i++)
1839 its_send_vmapp(its, vm->vpes[i], false);
1840 }
1841
1842 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1843}
1844
1845static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1846{
1847 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1848 u32 event = its_get_event_id(d);
1849 int ret = 0;
1850
1851 if (!info->map)
1852 return -EINVAL;
1853
1854 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1855
1856 if (!its_dev->event_map.vm) {
1857 struct its_vlpi_map *maps;
1858
1859 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1860 GFP_ATOMIC);
1861 if (!maps) {
1862 ret = -ENOMEM;
1863 goto out;
1864 }
1865
1866 its_dev->event_map.vm = info->map->vm;
1867 its_dev->event_map.vlpi_maps = maps;
1868 } else if (its_dev->event_map.vm != info->map->vm) {
1869 ret = -EINVAL;
1870 goto out;
1871 }
1872
1873 /* Get our private copy of the mapping information */
1874 its_dev->event_map.vlpi_maps[event] = *info->map;
1875
1876 if (irqd_is_forwarded_to_vcpu(d)) {
1877 /* Already mapped, move it around */
1878 its_send_vmovi(its_dev, event);
1879 } else {
1880 /* Ensure all the VPEs are mapped on this ITS */
1881 its_map_vm(its_dev->its, info->map->vm);
1882
1883 /*
1884 * Flag the interrupt as forwarded so that we can
1885 * start poking the virtual property table.
1886 */
1887 irqd_set_forwarded_to_vcpu(d);
1888
1889 /* Write out the property to the prop table */
1890 lpi_write_config(d, 0xff, info->map->properties);
1891
1892 /* Drop the physical mapping */
1893 its_send_discard(its_dev, event);
1894
1895 /* and install the virtual one */
1896 its_send_vmapti(its_dev, event);
1897
1898 /* Increment the number of VLPIs */
1899 its_dev->event_map.nr_vlpis++;
1900 }
1901
1902out:
1903 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1904 return ret;
1905}
1906
1907static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1908{
1909 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1910 struct its_vlpi_map *map;
1911 int ret = 0;
1912
1913 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1914
1915 map = get_vlpi_map(d);
1916
1917 if (!its_dev->event_map.vm || !map) {
1918 ret = -EINVAL;
1919 goto out;
1920 }
1921
1922 /* Copy our mapping information to the incoming request */
1923 *info->map = *map;
1924
1925out:
1926 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1927 return ret;
1928}
1929
1930static int its_vlpi_unmap(struct irq_data *d)
1931{
1932 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1933 u32 event = its_get_event_id(d);
1934 int ret = 0;
1935
1936 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1937
1938 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1939 ret = -EINVAL;
1940 goto out;
1941 }
1942
1943 /* Drop the virtual mapping */
1944 its_send_discard(its_dev, event);
1945
1946 /* and restore the physical one */
1947 irqd_clr_forwarded_to_vcpu(d);
1948 its_send_mapti(its_dev, d->hwirq, event);
1949 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1950 LPI_PROP_ENABLED |
1951 LPI_PROP_GROUP1));
1952
1953 /* Potentially unmap the VM from this ITS */
1954 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1955
1956 /*
1957 * Drop the refcount and make the device available again if
1958 * this was the last VLPI.
1959 */
1960 if (!--its_dev->event_map.nr_vlpis) {
1961 its_dev->event_map.vm = NULL;
1962 kfree(its_dev->event_map.vlpi_maps);
1963 }
1964
1965out:
1966 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1967 return ret;
1968}
1969
1970static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1971{
1972 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1973
1974 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1975 return -EINVAL;
1976
1977 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1978 lpi_update_config(d, 0xff, info->config);
1979 else
1980 lpi_write_config(d, 0xff, info->config);
1981 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1982
1983 return 0;
1984}
1985
1986static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1987{
1988 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1989 struct its_cmd_info *info = vcpu_info;
1990
1991 /* Need a v4 ITS */
1992 if (!is_v4(its_dev->its))
1993 return -EINVAL;
1994
1995 /* Unmap request? */
1996 if (!info)
1997 return its_vlpi_unmap(d);
1998
1999 switch (info->cmd_type) {
2000 case MAP_VLPI:
2001 return its_vlpi_map(d, info);
2002
2003 case GET_VLPI:
2004 return its_vlpi_get(d, info);
2005
2006 case PROP_UPDATE_VLPI:
2007 case PROP_UPDATE_AND_INV_VLPI:
2008 return its_vlpi_prop_update(d, info);
2009
2010 default:
2011 return -EINVAL;
2012 }
2013}
2014
2015static struct irq_chip its_irq_chip = {
2016 .name = "ITS",
2017 .irq_mask = its_mask_irq,
2018 .irq_unmask = its_unmask_irq,
2019 .irq_eoi = irq_chip_eoi_parent,
2020 .irq_set_affinity = its_set_affinity,
2021 .irq_compose_msi_msg = its_irq_compose_msi_msg,
2022 .irq_set_irqchip_state = its_irq_set_irqchip_state,
2023 .irq_retrigger = its_irq_retrigger,
2024 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
2025};
2026
2027
2028/*
2029 * How we allocate LPIs:
2030 *
2031 * lpi_range_list contains ranges of LPIs that are to available to
2032 * allocate from. To allocate LPIs, just pick the first range that
2033 * fits the required allocation, and reduce it by the required
2034 * amount. Once empty, remove the range from the list.
2035 *
2036 * To free a range of LPIs, add a free range to the list, sort it and
2037 * merge the result if the new range happens to be adjacent to an
2038 * already free block.
2039 *
2040 * The consequence of the above is that allocation is cost is low, but
2041 * freeing is expensive. We assumes that freeing rarely occurs.
2042 */
2043#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
2044
2045static DEFINE_MUTEX(lpi_range_lock);
2046static LIST_HEAD(lpi_range_list);
2047
2048struct lpi_range {
2049 struct list_head entry;
2050 u32 base_id;
2051 u32 span;
2052};
2053
2054static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2055{
2056 struct lpi_range *range;
2057
2058 range = kmalloc(sizeof(*range), GFP_KERNEL);
2059 if (range) {
2060 range->base_id = base;
2061 range->span = span;
2062 }
2063
2064 return range;
2065}
2066
2067static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2068{
2069 struct lpi_range *range, *tmp;
2070 int err = -ENOSPC;
2071
2072 mutex_lock(&lpi_range_lock);
2073
2074 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2075 if (range->span >= nr_lpis) {
2076 *base = range->base_id;
2077 range->base_id += nr_lpis;
2078 range->span -= nr_lpis;
2079
2080 if (range->span == 0) {
2081 list_del(&range->entry);
2082 kfree(range);
2083 }
2084
2085 err = 0;
2086 break;
2087 }
2088 }
2089
2090 mutex_unlock(&lpi_range_lock);
2091
2092 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2093 return err;
2094}
2095
2096static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2097{
2098 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2099 return;
2100 if (a->base_id + a->span != b->base_id)
2101 return;
2102 b->base_id = a->base_id;
2103 b->span += a->span;
2104 list_del(&a->entry);
2105 kfree(a);
2106}
2107
2108static int free_lpi_range(u32 base, u32 nr_lpis)
2109{
2110 struct lpi_range *new, *old;
2111
2112 new = mk_lpi_range(base, nr_lpis);
2113 if (!new)
2114 return -ENOMEM;
2115
2116 mutex_lock(&lpi_range_lock);
2117
2118 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2119 if (old->base_id < base)
2120 break;
2121 }
2122 /*
2123 * old is the last element with ->base_id smaller than base,
2124 * so new goes right after it. If there are no elements with
2125 * ->base_id smaller than base, &old->entry ends up pointing
2126 * at the head of the list, and inserting new it the start of
2127 * the list is the right thing to do in that case as well.
2128 */
2129 list_add(&new->entry, &old->entry);
2130 /*
2131 * Now check if we can merge with the preceding and/or
2132 * following ranges.
2133 */
2134 merge_lpi_ranges(old, new);
2135 merge_lpi_ranges(new, list_next_entry(new, entry));
2136
2137 mutex_unlock(&lpi_range_lock);
2138 return 0;
2139}
2140
2141static int __init its_lpi_init(u32 id_bits)
2142{
2143 u32 lpis = (1UL << id_bits) - 8192;
2144 u32 numlpis;
2145 int err;
2146
2147 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2148
2149 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2150 lpis = numlpis;
2151 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2152 lpis);
2153 }
2154
2155 /*
2156 * Initializing the allocator is just the same as freeing the
2157 * full range of LPIs.
2158 */
2159 err = free_lpi_range(8192, lpis);
2160 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2161 return err;
2162}
2163
2164static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2165{
2166 unsigned long *bitmap = NULL;
2167 int err = 0;
2168
2169 do {
2170 err = alloc_lpi_range(nr_irqs, base);
2171 if (!err)
2172 break;
2173
2174 nr_irqs /= 2;
2175 } while (nr_irqs > 0);
2176
2177 if (!nr_irqs)
2178 err = -ENOSPC;
2179
2180 if (err)
2181 goto out;
2182
2183 bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2184 if (!bitmap)
2185 goto out;
2186
2187 *nr_ids = nr_irqs;
2188
2189out:
2190 if (!bitmap)
2191 *base = *nr_ids = 0;
2192
2193 return bitmap;
2194}
2195
2196static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2197{
2198 WARN_ON(free_lpi_range(base, nr_ids));
2199 bitmap_free(bitmap);
2200}
2201
2202static void gic_reset_prop_table(void *va)
2203{
2204 /* Priority 0xa0, Group-1, disabled */
2205 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2206
2207 /* Make sure the GIC will observe the written configuration */
2208 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2209}
2210
2211static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2212{
2213 struct page *prop_page;
2214
2215 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2216 if (!prop_page)
2217 return NULL;
2218
2219 gic_reset_prop_table(page_address(prop_page));
2220
2221 return prop_page;
2222}
2223
2224static void its_free_prop_table(struct page *prop_page)
2225{
2226 free_pages((unsigned long)page_address(prop_page),
2227 get_order(LPI_PROPBASE_SZ));
2228}
2229
2230static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2231{
2232 phys_addr_t start, end, addr_end;
2233 u64 i;
2234
2235 /*
2236 * We don't bother checking for a kdump kernel as by
2237 * construction, the LPI tables are out of this kernel's
2238 * memory map.
2239 */
2240 if (is_kdump_kernel())
2241 return true;
2242
2243 addr_end = addr + size - 1;
2244
2245 for_each_reserved_mem_range(i, &start, &end) {
2246 if (addr >= start && addr_end <= end)
2247 return true;
2248 }
2249
2250 /* Not found, not a good sign... */
2251 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2252 &addr, &addr_end);
2253 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2254 return false;
2255}
2256
2257static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2258{
2259 if (efi_enabled(EFI_CONFIG_TABLES))
2260 return efi_mem_reserve_persistent(addr, size);
2261
2262 return 0;
2263}
2264
2265static int __init its_setup_lpi_prop_table(void)
2266{
2267 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2268 u64 val;
2269
2270 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2271 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2272
2273 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2274 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2275 LPI_PROPBASE_SZ,
2276 MEMREMAP_WB);
2277 gic_reset_prop_table(gic_rdists->prop_table_va);
2278 } else {
2279 struct page *page;
2280
2281 lpi_id_bits = min_t(u32,
2282 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2283 ITS_MAX_LPI_NRBITS);
2284 page = its_allocate_prop_table(GFP_NOWAIT);
2285 if (!page) {
2286 pr_err("Failed to allocate PROPBASE\n");
2287 return -ENOMEM;
2288 }
2289
2290 gic_rdists->prop_table_pa = page_to_phys(page);
2291 gic_rdists->prop_table_va = page_address(page);
2292 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2293 LPI_PROPBASE_SZ));
2294 }
2295
2296 pr_info("GICv3: using LPI property table @%pa\n",
2297 &gic_rdists->prop_table_pa);
2298
2299 return its_lpi_init(lpi_id_bits);
2300}
2301
2302static const char *its_base_type_string[] = {
2303 [GITS_BASER_TYPE_DEVICE] = "Devices",
2304 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
2305 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
2306 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2307 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2308 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2309 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2310};
2311
2312static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2313{
2314 u32 idx = baser - its->tables;
2315
2316 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2317}
2318
2319static void its_write_baser(struct its_node *its, struct its_baser *baser,
2320 u64 val)
2321{
2322 u32 idx = baser - its->tables;
2323
2324 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2325 baser->val = its_read_baser(its, baser);
2326}
2327
2328static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2329 u64 cache, u64 shr, u32 order, bool indirect)
2330{
2331 u64 val = its_read_baser(its, baser);
2332 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2333 u64 type = GITS_BASER_TYPE(val);
2334 u64 baser_phys, tmp;
2335 u32 alloc_pages, psz;
2336 struct page *page;
2337 void *base;
2338
2339 psz = baser->psz;
2340 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2341 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2342 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2343 &its->phys_base, its_base_type_string[type],
2344 alloc_pages, GITS_BASER_PAGES_MAX);
2345 alloc_pages = GITS_BASER_PAGES_MAX;
2346 order = get_order(GITS_BASER_PAGES_MAX * psz);
2347 }
2348
2349 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2350 if (!page)
2351 return -ENOMEM;
2352
2353 base = (void *)page_address(page);
2354 baser_phys = virt_to_phys(base);
2355
2356 /* Check if the physical address of the memory is above 48bits */
2357 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2358
2359 /* 52bit PA is supported only when PageSize=64K */
2360 if (psz != SZ_64K) {
2361 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2362 free_pages((unsigned long)base, order);
2363 return -ENXIO;
2364 }
2365
2366 /* Convert 52bit PA to 48bit field */
2367 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2368 }
2369
2370retry_baser:
2371 val = (baser_phys |
2372 (type << GITS_BASER_TYPE_SHIFT) |
2373 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2374 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2375 cache |
2376 shr |
2377 GITS_BASER_VALID);
2378
2379 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2380
2381 switch (psz) {
2382 case SZ_4K:
2383 val |= GITS_BASER_PAGE_SIZE_4K;
2384 break;
2385 case SZ_16K:
2386 val |= GITS_BASER_PAGE_SIZE_16K;
2387 break;
2388 case SZ_64K:
2389 val |= GITS_BASER_PAGE_SIZE_64K;
2390 break;
2391 }
2392
2393 if (!shr)
2394 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2395
2396 its_write_baser(its, baser, val);
2397 tmp = baser->val;
2398
2399 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2400 /*
2401 * Shareability didn't stick. Just use
2402 * whatever the read reported, which is likely
2403 * to be the only thing this redistributor
2404 * supports. If that's zero, make it
2405 * non-cacheable as well.
2406 */
2407 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2408 if (!shr)
2409 cache = GITS_BASER_nC;
2410
2411 goto retry_baser;
2412 }
2413
2414 if (val != tmp) {
2415 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2416 &its->phys_base, its_base_type_string[type],
2417 val, tmp);
2418 free_pages((unsigned long)base, order);
2419 return -ENXIO;
2420 }
2421
2422 baser->order = order;
2423 baser->base = base;
2424 baser->psz = psz;
2425 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2426
2427 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2428 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2429 its_base_type_string[type],
2430 (unsigned long)virt_to_phys(base),
2431 indirect ? "indirect" : "flat", (int)esz,
2432 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2433
2434 return 0;
2435}
2436
2437static bool its_parse_indirect_baser(struct its_node *its,
2438 struct its_baser *baser,
2439 u32 *order, u32 ids)
2440{
2441 u64 tmp = its_read_baser(its, baser);
2442 u64 type = GITS_BASER_TYPE(tmp);
2443 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2444 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2445 u32 new_order = *order;
2446 u32 psz = baser->psz;
2447 bool indirect = false;
2448
2449 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2450 if ((esz << ids) > (psz * 2)) {
2451 /*
2452 * Find out whether hw supports a single or two-level table by
2453 * table by reading bit at offset '62' after writing '1' to it.
2454 */
2455 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2456 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2457
2458 if (indirect) {
2459 /*
2460 * The size of the lvl2 table is equal to ITS page size
2461 * which is 'psz'. For computing lvl1 table size,
2462 * subtract ID bits that sparse lvl2 table from 'ids'
2463 * which is reported by ITS hardware times lvl1 table
2464 * entry size.
2465 */
2466 ids -= ilog2(psz / (int)esz);
2467 esz = GITS_LVL1_ENTRY_SIZE;
2468 }
2469 }
2470
2471 /*
2472 * Allocate as many entries as required to fit the
2473 * range of device IDs that the ITS can grok... The ID
2474 * space being incredibly sparse, this results in a
2475 * massive waste of memory if two-level device table
2476 * feature is not supported by hardware.
2477 */
2478 new_order = max_t(u32, get_order(esz << ids), new_order);
2479 if (new_order > MAX_PAGE_ORDER) {
2480 new_order = MAX_PAGE_ORDER;
2481 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2482 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2483 &its->phys_base, its_base_type_string[type],
2484 device_ids(its), ids);
2485 }
2486
2487 *order = new_order;
2488
2489 return indirect;
2490}
2491
2492static u32 compute_common_aff(u64 val)
2493{
2494 u32 aff, clpiaff;
2495
2496 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2497 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2498
2499 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2500}
2501
2502static u32 compute_its_aff(struct its_node *its)
2503{
2504 u64 val;
2505 u32 svpet;
2506
2507 /*
2508 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2509 * the resulting affinity. We then use that to see if this match
2510 * our own affinity.
2511 */
2512 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2513 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2514 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2515 return compute_common_aff(val);
2516}
2517
2518static struct its_node *find_sibling_its(struct its_node *cur_its)
2519{
2520 struct its_node *its;
2521 u32 aff;
2522
2523 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2524 return NULL;
2525
2526 aff = compute_its_aff(cur_its);
2527
2528 list_for_each_entry(its, &its_nodes, entry) {
2529 u64 baser;
2530
2531 if (!is_v4_1(its) || its == cur_its)
2532 continue;
2533
2534 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2535 continue;
2536
2537 if (aff != compute_its_aff(its))
2538 continue;
2539
2540 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2541 baser = its->tables[2].val;
2542 if (!(baser & GITS_BASER_VALID))
2543 continue;
2544
2545 return its;
2546 }
2547
2548 return NULL;
2549}
2550
2551static void its_free_tables(struct its_node *its)
2552{
2553 int i;
2554
2555 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2556 if (its->tables[i].base) {
2557 free_pages((unsigned long)its->tables[i].base,
2558 its->tables[i].order);
2559 its->tables[i].base = NULL;
2560 }
2561 }
2562}
2563
2564static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2565{
2566 u64 psz = SZ_64K;
2567
2568 while (psz) {
2569 u64 val, gpsz;
2570
2571 val = its_read_baser(its, baser);
2572 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2573
2574 switch (psz) {
2575 case SZ_64K:
2576 gpsz = GITS_BASER_PAGE_SIZE_64K;
2577 break;
2578 case SZ_16K:
2579 gpsz = GITS_BASER_PAGE_SIZE_16K;
2580 break;
2581 case SZ_4K:
2582 default:
2583 gpsz = GITS_BASER_PAGE_SIZE_4K;
2584 break;
2585 }
2586
2587 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2588
2589 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2590 its_write_baser(its, baser, val);
2591
2592 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2593 break;
2594
2595 switch (psz) {
2596 case SZ_64K:
2597 psz = SZ_16K;
2598 break;
2599 case SZ_16K:
2600 psz = SZ_4K;
2601 break;
2602 case SZ_4K:
2603 default:
2604 return -1;
2605 }
2606 }
2607
2608 baser->psz = psz;
2609 return 0;
2610}
2611
2612static int its_alloc_tables(struct its_node *its)
2613{
2614 u64 shr = GITS_BASER_InnerShareable;
2615 u64 cache = GITS_BASER_RaWaWb;
2616 int err, i;
2617
2618 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2619 /* erratum 24313: ignore memory access type */
2620 cache = GITS_BASER_nCnB;
2621
2622 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) {
2623 cache = GITS_BASER_nC;
2624 shr = 0;
2625 }
2626
2627 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2628 struct its_baser *baser = its->tables + i;
2629 u64 val = its_read_baser(its, baser);
2630 u64 type = GITS_BASER_TYPE(val);
2631 bool indirect = false;
2632 u32 order;
2633
2634 if (type == GITS_BASER_TYPE_NONE)
2635 continue;
2636
2637 if (its_probe_baser_psz(its, baser)) {
2638 its_free_tables(its);
2639 return -ENXIO;
2640 }
2641
2642 order = get_order(baser->psz);
2643
2644 switch (type) {
2645 case GITS_BASER_TYPE_DEVICE:
2646 indirect = its_parse_indirect_baser(its, baser, &order,
2647 device_ids(its));
2648 break;
2649
2650 case GITS_BASER_TYPE_VCPU:
2651 if (is_v4_1(its)) {
2652 struct its_node *sibling;
2653
2654 WARN_ON(i != 2);
2655 if ((sibling = find_sibling_its(its))) {
2656 *baser = sibling->tables[2];
2657 its_write_baser(its, baser, baser->val);
2658 continue;
2659 }
2660 }
2661
2662 indirect = its_parse_indirect_baser(its, baser, &order,
2663 ITS_MAX_VPEID_BITS);
2664 break;
2665 }
2666
2667 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2668 if (err < 0) {
2669 its_free_tables(its);
2670 return err;
2671 }
2672
2673 /* Update settings which will be used for next BASERn */
2674 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2675 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2676 }
2677
2678 return 0;
2679}
2680
2681static u64 inherit_vpe_l1_table_from_its(void)
2682{
2683 struct its_node *its;
2684 u64 val;
2685 u32 aff;
2686
2687 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2688 aff = compute_common_aff(val);
2689
2690 list_for_each_entry(its, &its_nodes, entry) {
2691 u64 baser, addr;
2692
2693 if (!is_v4_1(its))
2694 continue;
2695
2696 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2697 continue;
2698
2699 if (aff != compute_its_aff(its))
2700 continue;
2701
2702 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2703 baser = its->tables[2].val;
2704 if (!(baser & GITS_BASER_VALID))
2705 continue;
2706
2707 /* We have a winner! */
2708 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2709
2710 val = GICR_VPROPBASER_4_1_VALID;
2711 if (baser & GITS_BASER_INDIRECT)
2712 val |= GICR_VPROPBASER_4_1_INDIRECT;
2713 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2714 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2715 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2716 case GIC_PAGE_SIZE_64K:
2717 addr = GITS_BASER_ADDR_48_to_52(baser);
2718 break;
2719 default:
2720 addr = baser & GENMASK_ULL(47, 12);
2721 break;
2722 }
2723 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2724 if (rdists_support_shareable()) {
2725 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2726 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2727 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2728 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2729 }
2730 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2731
2732 return val;
2733 }
2734
2735 return 0;
2736}
2737
2738static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2739{
2740 u32 aff;
2741 u64 val;
2742 int cpu;
2743
2744 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2745 aff = compute_common_aff(val);
2746
2747 for_each_possible_cpu(cpu) {
2748 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2749
2750 if (!base || cpu == smp_processor_id())
2751 continue;
2752
2753 val = gic_read_typer(base + GICR_TYPER);
2754 if (aff != compute_common_aff(val))
2755 continue;
2756
2757 /*
2758 * At this point, we have a victim. This particular CPU
2759 * has already booted, and has an affinity that matches
2760 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2761 * Make sure we don't write the Z bit in that case.
2762 */
2763 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2764 val &= ~GICR_VPROPBASER_4_1_Z;
2765
2766 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2767 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2768
2769 return val;
2770 }
2771
2772 return 0;
2773}
2774
2775static bool allocate_vpe_l2_table(int cpu, u32 id)
2776{
2777 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2778 unsigned int psz, esz, idx, npg, gpsz;
2779 u64 val;
2780 struct page *page;
2781 __le64 *table;
2782
2783 if (!gic_rdists->has_rvpeid)
2784 return true;
2785
2786 /* Skip non-present CPUs */
2787 if (!base)
2788 return true;
2789
2790 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2791
2792 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2793 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2794 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2795
2796 switch (gpsz) {
2797 default:
2798 WARN_ON(1);
2799 fallthrough;
2800 case GIC_PAGE_SIZE_4K:
2801 psz = SZ_4K;
2802 break;
2803 case GIC_PAGE_SIZE_16K:
2804 psz = SZ_16K;
2805 break;
2806 case GIC_PAGE_SIZE_64K:
2807 psz = SZ_64K;
2808 break;
2809 }
2810
2811 /* Don't allow vpe_id that exceeds single, flat table limit */
2812 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2813 return (id < (npg * psz / (esz * SZ_8)));
2814
2815 /* Compute 1st level table index & check if that exceeds table limit */
2816 idx = id >> ilog2(psz / (esz * SZ_8));
2817 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2818 return false;
2819
2820 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2821
2822 /* Allocate memory for 2nd level table */
2823 if (!table[idx]) {
2824 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2825 if (!page)
2826 return false;
2827
2828 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2829 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2830 gic_flush_dcache_to_poc(page_address(page), psz);
2831
2832 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2833
2834 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2835 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2836 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2837
2838 /* Ensure updated table contents are visible to RD hardware */
2839 dsb(sy);
2840 }
2841
2842 return true;
2843}
2844
2845static int allocate_vpe_l1_table(void)
2846{
2847 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2848 u64 val, gpsz, npg, pa;
2849 unsigned int psz = SZ_64K;
2850 unsigned int np, epp, esz;
2851 struct page *page;
2852
2853 if (!gic_rdists->has_rvpeid)
2854 return 0;
2855
2856 /*
2857 * if VPENDBASER.Valid is set, disable any previously programmed
2858 * VPE by setting PendingLast while clearing Valid. This has the
2859 * effect of making sure no doorbell will be generated and we can
2860 * then safely clear VPROPBASER.Valid.
2861 */
2862 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2863 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2864 vlpi_base + GICR_VPENDBASER);
2865
2866 /*
2867 * If we can inherit the configuration from another RD, let's do
2868 * so. Otherwise, we have to go through the allocation process. We
2869 * assume that all RDs have the exact same requirements, as
2870 * nothing will work otherwise.
2871 */
2872 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2873 if (val & GICR_VPROPBASER_4_1_VALID)
2874 goto out;
2875
2876 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2877 if (!gic_data_rdist()->vpe_table_mask)
2878 return -ENOMEM;
2879
2880 val = inherit_vpe_l1_table_from_its();
2881 if (val & GICR_VPROPBASER_4_1_VALID)
2882 goto out;
2883
2884 /* First probe the page size */
2885 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2886 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2887 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2888 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2889 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2890
2891 switch (gpsz) {
2892 default:
2893 gpsz = GIC_PAGE_SIZE_4K;
2894 fallthrough;
2895 case GIC_PAGE_SIZE_4K:
2896 psz = SZ_4K;
2897 break;
2898 case GIC_PAGE_SIZE_16K:
2899 psz = SZ_16K;
2900 break;
2901 case GIC_PAGE_SIZE_64K:
2902 psz = SZ_64K;
2903 break;
2904 }
2905
2906 /*
2907 * Start populating the register from scratch, including RO fields
2908 * (which we want to print in debug cases...)
2909 */
2910 val = 0;
2911 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2912 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2913
2914 /* How many entries per GIC page? */
2915 esz++;
2916 epp = psz / (esz * SZ_8);
2917
2918 /*
2919 * If we need more than just a single L1 page, flag the table
2920 * as indirect and compute the number of required L1 pages.
2921 */
2922 if (epp < ITS_MAX_VPEID) {
2923 int nl2;
2924
2925 val |= GICR_VPROPBASER_4_1_INDIRECT;
2926
2927 /* Number of L2 pages required to cover the VPEID space */
2928 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2929
2930 /* Number of L1 pages to point to the L2 pages */
2931 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2932 } else {
2933 npg = 1;
2934 }
2935
2936 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2937
2938 /* Right, that's the number of CPU pages we need for L1 */
2939 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2940
2941 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2942 np, npg, psz, epp, esz);
2943 page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2944 if (!page)
2945 return -ENOMEM;
2946
2947 gic_data_rdist()->vpe_l1_base = page_address(page);
2948 pa = virt_to_phys(page_address(page));
2949 WARN_ON(!IS_ALIGNED(pa, psz));
2950
2951 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2952 if (rdists_support_shareable()) {
2953 val |= GICR_VPROPBASER_RaWb;
2954 val |= GICR_VPROPBASER_InnerShareable;
2955 }
2956 val |= GICR_VPROPBASER_4_1_Z;
2957 val |= GICR_VPROPBASER_4_1_VALID;
2958
2959out:
2960 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2961 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2962
2963 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2964 smp_processor_id(), val,
2965 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2966
2967 return 0;
2968}
2969
2970static int its_alloc_collections(struct its_node *its)
2971{
2972 int i;
2973
2974 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2975 GFP_KERNEL);
2976 if (!its->collections)
2977 return -ENOMEM;
2978
2979 for (i = 0; i < nr_cpu_ids; i++)
2980 its->collections[i].target_address = ~0ULL;
2981
2982 return 0;
2983}
2984
2985static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2986{
2987 struct page *pend_page;
2988
2989 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2990 get_order(LPI_PENDBASE_SZ));
2991 if (!pend_page)
2992 return NULL;
2993
2994 /* Make sure the GIC will observe the zero-ed page */
2995 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2996
2997 return pend_page;
2998}
2999
3000static void its_free_pending_table(struct page *pt)
3001{
3002 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
3003}
3004
3005/*
3006 * Booting with kdump and LPIs enabled is generally fine. Any other
3007 * case is wrong in the absence of firmware/EFI support.
3008 */
3009static bool enabled_lpis_allowed(void)
3010{
3011 phys_addr_t addr;
3012 u64 val;
3013
3014 /* Check whether the property table is in a reserved region */
3015 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
3016 addr = val & GENMASK_ULL(51, 12);
3017
3018 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
3019}
3020
3021static int __init allocate_lpi_tables(void)
3022{
3023 u64 val;
3024 int err, cpu;
3025
3026 /*
3027 * If LPIs are enabled while we run this from the boot CPU,
3028 * flag the RD tables as pre-allocated if the stars do align.
3029 */
3030 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
3031 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
3032 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
3033 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
3034 pr_info("GICv3: Using preallocated redistributor tables\n");
3035 }
3036
3037 err = its_setup_lpi_prop_table();
3038 if (err)
3039 return err;
3040
3041 /*
3042 * We allocate all the pending tables anyway, as we may have a
3043 * mix of RDs that have had LPIs enabled, and some that
3044 * don't. We'll free the unused ones as each CPU comes online.
3045 */
3046 for_each_possible_cpu(cpu) {
3047 struct page *pend_page;
3048
3049 pend_page = its_allocate_pending_table(GFP_NOWAIT);
3050 if (!pend_page) {
3051 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
3052 return -ENOMEM;
3053 }
3054
3055 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3056 }
3057
3058 return 0;
3059}
3060
3061static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
3062{
3063 u32 count = 1000000; /* 1s! */
3064 bool clean;
3065 u64 val;
3066
3067 do {
3068 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3069 clean = !(val & GICR_VPENDBASER_Dirty);
3070 if (!clean) {
3071 count--;
3072 cpu_relax();
3073 udelay(1);
3074 }
3075 } while (!clean && count);
3076
3077 if (unlikely(!clean))
3078 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3079
3080 return val;
3081}
3082
3083static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3084{
3085 u64 val;
3086
3087 /* Make sure we wait until the RD is done with the initial scan */
3088 val = read_vpend_dirty_clear(vlpi_base);
3089 val &= ~GICR_VPENDBASER_Valid;
3090 val &= ~clr;
3091 val |= set;
3092 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3093
3094 val = read_vpend_dirty_clear(vlpi_base);
3095 if (unlikely(val & GICR_VPENDBASER_Dirty))
3096 val |= GICR_VPENDBASER_PendingLast;
3097
3098 return val;
3099}
3100
3101static void its_cpu_init_lpis(void)
3102{
3103 void __iomem *rbase = gic_data_rdist_rd_base();
3104 struct page *pend_page;
3105 phys_addr_t paddr;
3106 u64 val, tmp;
3107
3108 if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)
3109 return;
3110
3111 val = readl_relaxed(rbase + GICR_CTLR);
3112 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3113 (val & GICR_CTLR_ENABLE_LPIS)) {
3114 /*
3115 * Check that we get the same property table on all
3116 * RDs. If we don't, this is hopeless.
3117 */
3118 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3119 paddr &= GENMASK_ULL(51, 12);
3120 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3121 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3122
3123 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3124 paddr &= GENMASK_ULL(51, 16);
3125
3126 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3127 gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED;
3128
3129 goto out;
3130 }
3131
3132 pend_page = gic_data_rdist()->pend_page;
3133 paddr = page_to_phys(pend_page);
3134
3135 /* set PROPBASE */
3136 val = (gic_rdists->prop_table_pa |
3137 GICR_PROPBASER_InnerShareable |
3138 GICR_PROPBASER_RaWaWb |
3139 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3140
3141 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3142 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3143
3144 if (!rdists_support_shareable())
3145 tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
3146
3147 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3148 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3149 /*
3150 * The HW reports non-shareable, we must
3151 * remove the cacheability attributes as
3152 * well.
3153 */
3154 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3155 GICR_PROPBASER_CACHEABILITY_MASK);
3156 val |= GICR_PROPBASER_nC;
3157 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3158 }
3159 pr_info_once("GIC: using cache flushing for LPI property table\n");
3160 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3161 }
3162
3163 /* set PENDBASE */
3164 val = (page_to_phys(pend_page) |
3165 GICR_PENDBASER_InnerShareable |
3166 GICR_PENDBASER_RaWaWb);
3167
3168 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3169 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3170
3171 if (!rdists_support_shareable())
3172 tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
3173
3174 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3175 /*
3176 * The HW reports non-shareable, we must remove the
3177 * cacheability attributes as well.
3178 */
3179 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3180 GICR_PENDBASER_CACHEABILITY_MASK);
3181 val |= GICR_PENDBASER_nC;
3182 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3183 }
3184
3185 /* Enable LPIs */
3186 val = readl_relaxed(rbase + GICR_CTLR);
3187 val |= GICR_CTLR_ENABLE_LPIS;
3188 writel_relaxed(val, rbase + GICR_CTLR);
3189
3190out:
3191 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3192 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3193
3194 /*
3195 * It's possible for CPU to receive VLPIs before it is
3196 * scheduled as a vPE, especially for the first CPU, and the
3197 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3198 * as out of range and dropped by GIC.
3199 * So we initialize IDbits to known value to avoid VLPI drop.
3200 */
3201 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3202 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3203 smp_processor_id(), val);
3204 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3205
3206 /*
3207 * Also clear Valid bit of GICR_VPENDBASER, in case some
3208 * ancient programming gets left in and has possibility of
3209 * corrupting memory.
3210 */
3211 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3212 }
3213
3214 if (allocate_vpe_l1_table()) {
3215 /*
3216 * If the allocation has failed, we're in massive trouble.
3217 * Disable direct injection, and pray that no VM was
3218 * already running...
3219 */
3220 gic_rdists->has_rvpeid = false;
3221 gic_rdists->has_vlpis = false;
3222 }
3223
3224 /* Make sure the GIC has seen the above */
3225 dsb(sy);
3226 gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED;
3227 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3228 smp_processor_id(),
3229 gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ?
3230 "reserved" : "allocated",
3231 &paddr);
3232}
3233
3234static void its_cpu_init_collection(struct its_node *its)
3235{
3236 int cpu = smp_processor_id();
3237 u64 target;
3238
3239 /* avoid cross node collections and its mapping */
3240 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3241 struct device_node *cpu_node;
3242
3243 cpu_node = of_get_cpu_node(cpu, NULL);
3244 if (its->numa_node != NUMA_NO_NODE &&
3245 its->numa_node != of_node_to_nid(cpu_node))
3246 return;
3247 }
3248
3249 /*
3250 * We now have to bind each collection to its target
3251 * redistributor.
3252 */
3253 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3254 /*
3255 * This ITS wants the physical address of the
3256 * redistributor.
3257 */
3258 target = gic_data_rdist()->phys_base;
3259 } else {
3260 /* This ITS wants a linear CPU number. */
3261 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3262 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3263 }
3264
3265 /* Perform collection mapping */
3266 its->collections[cpu].target_address = target;
3267 its->collections[cpu].col_id = cpu;
3268
3269 its_send_mapc(its, &its->collections[cpu], 1);
3270 its_send_invall(its, &its->collections[cpu]);
3271}
3272
3273static void its_cpu_init_collections(void)
3274{
3275 struct its_node *its;
3276
3277 raw_spin_lock(&its_lock);
3278
3279 list_for_each_entry(its, &its_nodes, entry)
3280 its_cpu_init_collection(its);
3281
3282 raw_spin_unlock(&its_lock);
3283}
3284
3285static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3286{
3287 struct its_device *its_dev = NULL, *tmp;
3288 unsigned long flags;
3289
3290 raw_spin_lock_irqsave(&its->lock, flags);
3291
3292 list_for_each_entry(tmp, &its->its_device_list, entry) {
3293 if (tmp->device_id == dev_id) {
3294 its_dev = tmp;
3295 break;
3296 }
3297 }
3298
3299 raw_spin_unlock_irqrestore(&its->lock, flags);
3300
3301 return its_dev;
3302}
3303
3304static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3305{
3306 int i;
3307
3308 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3309 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3310 return &its->tables[i];
3311 }
3312
3313 return NULL;
3314}
3315
3316static bool its_alloc_table_entry(struct its_node *its,
3317 struct its_baser *baser, u32 id)
3318{
3319 struct page *page;
3320 u32 esz, idx;
3321 __le64 *table;
3322
3323 /* Don't allow device id that exceeds single, flat table limit */
3324 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3325 if (!(baser->val & GITS_BASER_INDIRECT))
3326 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3327
3328 /* Compute 1st level table index & check if that exceeds table limit */
3329 idx = id >> ilog2(baser->psz / esz);
3330 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3331 return false;
3332
3333 table = baser->base;
3334
3335 /* Allocate memory for 2nd level table */
3336 if (!table[idx]) {
3337 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3338 get_order(baser->psz));
3339 if (!page)
3340 return false;
3341
3342 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3343 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3344 gic_flush_dcache_to_poc(page_address(page), baser->psz);
3345
3346 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3347
3348 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3349 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3350 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3351
3352 /* Ensure updated table contents are visible to ITS hardware */
3353 dsb(sy);
3354 }
3355
3356 return true;
3357}
3358
3359static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3360{
3361 struct its_baser *baser;
3362
3363 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3364
3365 /* Don't allow device id that exceeds ITS hardware limit */
3366 if (!baser)
3367 return (ilog2(dev_id) < device_ids(its));
3368
3369 return its_alloc_table_entry(its, baser, dev_id);
3370}
3371
3372static bool its_alloc_vpe_table(u32 vpe_id)
3373{
3374 struct its_node *its;
3375 int cpu;
3376
3377 /*
3378 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3379 * could try and only do it on ITSs corresponding to devices
3380 * that have interrupts targeted at this VPE, but the
3381 * complexity becomes crazy (and you have tons of memory
3382 * anyway, right?).
3383 */
3384 list_for_each_entry(its, &its_nodes, entry) {
3385 struct its_baser *baser;
3386
3387 if (!is_v4(its))
3388 continue;
3389
3390 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3391 if (!baser)
3392 return false;
3393
3394 if (!its_alloc_table_entry(its, baser, vpe_id))
3395 return false;
3396 }
3397
3398 /* Non v4.1? No need to iterate RDs and go back early. */
3399 if (!gic_rdists->has_rvpeid)
3400 return true;
3401
3402 /*
3403 * Make sure the L2 tables are allocated for all copies of
3404 * the L1 table on *all* v4.1 RDs.
3405 */
3406 for_each_possible_cpu(cpu) {
3407 if (!allocate_vpe_l2_table(cpu, vpe_id))
3408 return false;
3409 }
3410
3411 return true;
3412}
3413
3414static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3415 int nvecs, bool alloc_lpis)
3416{
3417 struct its_device *dev;
3418 unsigned long *lpi_map = NULL;
3419 unsigned long flags;
3420 u16 *col_map = NULL;
3421 void *itt;
3422 int lpi_base;
3423 int nr_lpis;
3424 int nr_ites;
3425 int sz;
3426
3427 if (!its_alloc_device_table(its, dev_id))
3428 return NULL;
3429
3430 if (WARN_ON(!is_power_of_2(nvecs)))
3431 nvecs = roundup_pow_of_two(nvecs);
3432
3433 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3434 /*
3435 * Even if the device wants a single LPI, the ITT must be
3436 * sized as a power of two (and you need at least one bit...).
3437 */
3438 nr_ites = max(2, nvecs);
3439 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3440 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3441 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3442 if (alloc_lpis) {
3443 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3444 if (lpi_map)
3445 col_map = kcalloc(nr_lpis, sizeof(*col_map),
3446 GFP_KERNEL);
3447 } else {
3448 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3449 nr_lpis = 0;
3450 lpi_base = 0;
3451 }
3452
3453 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
3454 kfree(dev);
3455 kfree(itt);
3456 bitmap_free(lpi_map);
3457 kfree(col_map);
3458 return NULL;
3459 }
3460
3461 gic_flush_dcache_to_poc(itt, sz);
3462
3463 dev->its = its;
3464 dev->itt = itt;
3465 dev->nr_ites = nr_ites;
3466 dev->event_map.lpi_map = lpi_map;
3467 dev->event_map.col_map = col_map;
3468 dev->event_map.lpi_base = lpi_base;
3469 dev->event_map.nr_lpis = nr_lpis;
3470 raw_spin_lock_init(&dev->event_map.vlpi_lock);
3471 dev->device_id = dev_id;
3472 INIT_LIST_HEAD(&dev->entry);
3473
3474 raw_spin_lock_irqsave(&its->lock, flags);
3475 list_add(&dev->entry, &its->its_device_list);
3476 raw_spin_unlock_irqrestore(&its->lock, flags);
3477
3478 /* Map device to its ITT */
3479 its_send_mapd(dev, 1);
3480
3481 return dev;
3482}
3483
3484static void its_free_device(struct its_device *its_dev)
3485{
3486 unsigned long flags;
3487
3488 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3489 list_del(&its_dev->entry);
3490 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3491 kfree(its_dev->event_map.col_map);
3492 kfree(its_dev->itt);
3493 kfree(its_dev);
3494}
3495
3496static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3497{
3498 int idx;
3499
3500 /* Find a free LPI region in lpi_map and allocate them. */
3501 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3502 dev->event_map.nr_lpis,
3503 get_count_order(nvecs));
3504 if (idx < 0)
3505 return -ENOSPC;
3506
3507 *hwirq = dev->event_map.lpi_base + idx;
3508
3509 return 0;
3510}
3511
3512static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3513 int nvec, msi_alloc_info_t *info)
3514{
3515 struct its_node *its;
3516 struct its_device *its_dev;
3517 struct msi_domain_info *msi_info;
3518 u32 dev_id;
3519 int err = 0;
3520
3521 /*
3522 * We ignore "dev" entirely, and rely on the dev_id that has
3523 * been passed via the scratchpad. This limits this domain's
3524 * usefulness to upper layers that definitely know that they
3525 * are built on top of the ITS.
3526 */
3527 dev_id = info->scratchpad[0].ul;
3528
3529 msi_info = msi_get_domain_info(domain);
3530 its = msi_info->data;
3531
3532 if (!gic_rdists->has_direct_lpi &&
3533 vpe_proxy.dev &&
3534 vpe_proxy.dev->its == its &&
3535 dev_id == vpe_proxy.dev->device_id) {
3536 /* Bad luck. Get yourself a better implementation */
3537 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3538 dev_id);
3539 return -EINVAL;
3540 }
3541
3542 mutex_lock(&its->dev_alloc_lock);
3543 its_dev = its_find_device(its, dev_id);
3544 if (its_dev) {
3545 /*
3546 * We already have seen this ID, probably through
3547 * another alias (PCI bridge of some sort). No need to
3548 * create the device.
3549 */
3550 its_dev->shared = true;
3551 pr_debug("Reusing ITT for devID %x\n", dev_id);
3552 goto out;
3553 }
3554
3555 its_dev = its_create_device(its, dev_id, nvec, true);
3556 if (!its_dev) {
3557 err = -ENOMEM;
3558 goto out;
3559 }
3560
3561 if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)
3562 its_dev->shared = true;
3563
3564 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3565out:
3566 mutex_unlock(&its->dev_alloc_lock);
3567 info->scratchpad[0].ptr = its_dev;
3568 return err;
3569}
3570
3571static struct msi_domain_ops its_msi_domain_ops = {
3572 .msi_prepare = its_msi_prepare,
3573};
3574
3575static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3576 unsigned int virq,
3577 irq_hw_number_t hwirq)
3578{
3579 struct irq_fwspec fwspec;
3580
3581 if (irq_domain_get_of_node(domain->parent)) {
3582 fwspec.fwnode = domain->parent->fwnode;
3583 fwspec.param_count = 3;
3584 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3585 fwspec.param[1] = hwirq;
3586 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3587 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3588 fwspec.fwnode = domain->parent->fwnode;
3589 fwspec.param_count = 2;
3590 fwspec.param[0] = hwirq;
3591 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3592 } else {
3593 return -EINVAL;
3594 }
3595
3596 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3597}
3598
3599static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3600 unsigned int nr_irqs, void *args)
3601{
3602 msi_alloc_info_t *info = args;
3603 struct its_device *its_dev = info->scratchpad[0].ptr;
3604 struct its_node *its = its_dev->its;
3605 struct irq_data *irqd;
3606 irq_hw_number_t hwirq;
3607 int err;
3608 int i;
3609
3610 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3611 if (err)
3612 return err;
3613
3614 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3615 if (err)
3616 return err;
3617
3618 for (i = 0; i < nr_irqs; i++) {
3619 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3620 if (err)
3621 return err;
3622
3623 irq_domain_set_hwirq_and_chip(domain, virq + i,
3624 hwirq + i, &its_irq_chip, its_dev);
3625 irqd = irq_get_irq_data(virq + i);
3626 irqd_set_single_target(irqd);
3627 irqd_set_affinity_on_activate(irqd);
3628 irqd_set_resend_when_in_progress(irqd);
3629 pr_debug("ID:%d pID:%d vID:%d\n",
3630 (int)(hwirq + i - its_dev->event_map.lpi_base),
3631 (int)(hwirq + i), virq + i);
3632 }
3633
3634 return 0;
3635}
3636
3637static int its_irq_domain_activate(struct irq_domain *domain,
3638 struct irq_data *d, bool reserve)
3639{
3640 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3641 u32 event = its_get_event_id(d);
3642 int cpu;
3643
3644 cpu = its_select_cpu(d, cpu_online_mask);
3645 if (cpu < 0 || cpu >= nr_cpu_ids)
3646 return -EINVAL;
3647
3648 its_inc_lpi_count(d, cpu);
3649 its_dev->event_map.col_map[event] = cpu;
3650 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3651
3652 /* Map the GIC IRQ and event to the device */
3653 its_send_mapti(its_dev, d->hwirq, event);
3654 return 0;
3655}
3656
3657static void its_irq_domain_deactivate(struct irq_domain *domain,
3658 struct irq_data *d)
3659{
3660 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3661 u32 event = its_get_event_id(d);
3662
3663 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3664 /* Stop the delivery of interrupts */
3665 its_send_discard(its_dev, event);
3666}
3667
3668static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3669 unsigned int nr_irqs)
3670{
3671 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3672 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3673 struct its_node *its = its_dev->its;
3674 int i;
3675
3676 bitmap_release_region(its_dev->event_map.lpi_map,
3677 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3678 get_count_order(nr_irqs));
3679
3680 for (i = 0; i < nr_irqs; i++) {
3681 struct irq_data *data = irq_domain_get_irq_data(domain,
3682 virq + i);
3683 /* Nuke the entry in the domain */
3684 irq_domain_reset_irq_data(data);
3685 }
3686
3687 mutex_lock(&its->dev_alloc_lock);
3688
3689 /*
3690 * If all interrupts have been freed, start mopping the
3691 * floor. This is conditioned on the device not being shared.
3692 */
3693 if (!its_dev->shared &&
3694 bitmap_empty(its_dev->event_map.lpi_map,
3695 its_dev->event_map.nr_lpis)) {
3696 its_lpi_free(its_dev->event_map.lpi_map,
3697 its_dev->event_map.lpi_base,
3698 its_dev->event_map.nr_lpis);
3699
3700 /* Unmap device/itt */
3701 its_send_mapd(its_dev, 0);
3702 its_free_device(its_dev);
3703 }
3704
3705 mutex_unlock(&its->dev_alloc_lock);
3706
3707 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3708}
3709
3710static const struct irq_domain_ops its_domain_ops = {
3711 .alloc = its_irq_domain_alloc,
3712 .free = its_irq_domain_free,
3713 .activate = its_irq_domain_activate,
3714 .deactivate = its_irq_domain_deactivate,
3715};
3716
3717/*
3718 * This is insane.
3719 *
3720 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3721 * likely), the only way to perform an invalidate is to use a fake
3722 * device to issue an INV command, implying that the LPI has first
3723 * been mapped to some event on that device. Since this is not exactly
3724 * cheap, we try to keep that mapping around as long as possible, and
3725 * only issue an UNMAP if we're short on available slots.
3726 *
3727 * Broken by design(tm).
3728 *
3729 * GICv4.1, on the other hand, mandates that we're able to invalidate
3730 * by writing to a MMIO register. It doesn't implement the whole of
3731 * DirectLPI, but that's good enough. And most of the time, we don't
3732 * even have to invalidate anything, as the redistributor can be told
3733 * whether to generate a doorbell or not (we thus leave it enabled,
3734 * always).
3735 */
3736static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3737{
3738 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3739 if (gic_rdists->has_rvpeid)
3740 return;
3741
3742 /* Already unmapped? */
3743 if (vpe->vpe_proxy_event == -1)
3744 return;
3745
3746 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3747 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3748
3749 /*
3750 * We don't track empty slots at all, so let's move the
3751 * next_victim pointer if we can quickly reuse that slot
3752 * instead of nuking an existing entry. Not clear that this is
3753 * always a win though, and this might just generate a ripple
3754 * effect... Let's just hope VPEs don't migrate too often.
3755 */
3756 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3757 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3758
3759 vpe->vpe_proxy_event = -1;
3760}
3761
3762static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3763{
3764 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3765 if (gic_rdists->has_rvpeid)
3766 return;
3767
3768 if (!gic_rdists->has_direct_lpi) {
3769 unsigned long flags;
3770
3771 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3772 its_vpe_db_proxy_unmap_locked(vpe);
3773 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3774 }
3775}
3776
3777static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3778{
3779 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3780 if (gic_rdists->has_rvpeid)
3781 return;
3782
3783 /* Already mapped? */
3784 if (vpe->vpe_proxy_event != -1)
3785 return;
3786
3787 /* This slot was already allocated. Kick the other VPE out. */
3788 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3789 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3790
3791 /* Map the new VPE instead */
3792 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3793 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3794 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3795
3796 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3797 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3798}
3799
3800static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3801{
3802 unsigned long flags;
3803 struct its_collection *target_col;
3804
3805 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3806 if (gic_rdists->has_rvpeid)
3807 return;
3808
3809 if (gic_rdists->has_direct_lpi) {
3810 void __iomem *rdbase;
3811
3812 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3813 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3814 wait_for_syncr(rdbase);
3815
3816 return;
3817 }
3818
3819 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3820
3821 its_vpe_db_proxy_map_locked(vpe);
3822
3823 target_col = &vpe_proxy.dev->its->collections[to];
3824 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3825 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3826
3827 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3828}
3829
3830static int its_vpe_set_affinity(struct irq_data *d,
3831 const struct cpumask *mask_val,
3832 bool force)
3833{
3834 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3835 struct cpumask common, *table_mask;
3836 unsigned long flags;
3837 int from, cpu;
3838
3839 /*
3840 * Changing affinity is mega expensive, so let's be as lazy as
3841 * we can and only do it if we really have to. Also, if mapped
3842 * into the proxy device, we need to move the doorbell
3843 * interrupt to its new location.
3844 *
3845 * Another thing is that changing the affinity of a vPE affects
3846 * *other interrupts* such as all the vLPIs that are routed to
3847 * this vPE. This means that the irq_desc lock is not enough to
3848 * protect us, and that we must ensure nobody samples vpe->col_idx
3849 * during the update, hence the lock below which must also be
3850 * taken on any vLPI handling path that evaluates vpe->col_idx.
3851 */
3852 from = vpe_to_cpuid_lock(vpe, &flags);
3853 table_mask = gic_data_rdist_cpu(from)->vpe_table_mask;
3854
3855 /*
3856 * If we are offered another CPU in the same GICv4.1 ITS
3857 * affinity, pick this one. Otherwise, any CPU will do.
3858 */
3859 if (table_mask && cpumask_and(&common, mask_val, table_mask))
3860 cpu = cpumask_test_cpu(from, &common) ? from : cpumask_first(&common);
3861 else
3862 cpu = cpumask_first(mask_val);
3863
3864 if (from == cpu)
3865 goto out;
3866
3867 vpe->col_idx = cpu;
3868
3869 its_send_vmovp(vpe);
3870 its_vpe_db_proxy_move(vpe, from, cpu);
3871
3872out:
3873 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3874 vpe_to_cpuid_unlock(vpe, flags);
3875
3876 return IRQ_SET_MASK_OK_DONE;
3877}
3878
3879static void its_wait_vpt_parse_complete(void)
3880{
3881 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3882 u64 val;
3883
3884 if (!gic_rdists->has_vpend_valid_dirty)
3885 return;
3886
3887 WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3888 val,
3889 !(val & GICR_VPENDBASER_Dirty),
3890 1, 500));
3891}
3892
3893static void its_vpe_schedule(struct its_vpe *vpe)
3894{
3895 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3896 u64 val;
3897
3898 /* Schedule the VPE */
3899 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3900 GENMASK_ULL(51, 12);
3901 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3902 if (rdists_support_shareable()) {
3903 val |= GICR_VPROPBASER_RaWb;
3904 val |= GICR_VPROPBASER_InnerShareable;
3905 }
3906 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3907
3908 val = virt_to_phys(page_address(vpe->vpt_page)) &
3909 GENMASK_ULL(51, 16);
3910 if (rdists_support_shareable()) {
3911 val |= GICR_VPENDBASER_RaWaWb;
3912 val |= GICR_VPENDBASER_InnerShareable;
3913 }
3914 /*
3915 * There is no good way of finding out if the pending table is
3916 * empty as we can race against the doorbell interrupt very
3917 * easily. So in the end, vpe->pending_last is only an
3918 * indication that the vcpu has something pending, not one
3919 * that the pending table is empty. A good implementation
3920 * would be able to read its coarse map pretty quickly anyway,
3921 * making this a tolerable issue.
3922 */
3923 val |= GICR_VPENDBASER_PendingLast;
3924 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3925 val |= GICR_VPENDBASER_Valid;
3926 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3927}
3928
3929static void its_vpe_deschedule(struct its_vpe *vpe)
3930{
3931 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3932 u64 val;
3933
3934 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3935
3936 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3937 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3938}
3939
3940static void its_vpe_invall(struct its_vpe *vpe)
3941{
3942 struct its_node *its;
3943
3944 list_for_each_entry(its, &its_nodes, entry) {
3945 if (!is_v4(its))
3946 continue;
3947
3948 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3949 continue;
3950
3951 /*
3952 * Sending a VINVALL to a single ITS is enough, as all
3953 * we need is to reach the redistributors.
3954 */
3955 its_send_vinvall(its, vpe);
3956 return;
3957 }
3958}
3959
3960static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3961{
3962 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3963 struct its_cmd_info *info = vcpu_info;
3964
3965 switch (info->cmd_type) {
3966 case SCHEDULE_VPE:
3967 its_vpe_schedule(vpe);
3968 return 0;
3969
3970 case DESCHEDULE_VPE:
3971 its_vpe_deschedule(vpe);
3972 return 0;
3973
3974 case COMMIT_VPE:
3975 its_wait_vpt_parse_complete();
3976 return 0;
3977
3978 case INVALL_VPE:
3979 its_vpe_invall(vpe);
3980 return 0;
3981
3982 default:
3983 return -EINVAL;
3984 }
3985}
3986
3987static void its_vpe_send_cmd(struct its_vpe *vpe,
3988 void (*cmd)(struct its_device *, u32))
3989{
3990 unsigned long flags;
3991
3992 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3993
3994 its_vpe_db_proxy_map_locked(vpe);
3995 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3996
3997 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3998}
3999
4000static void its_vpe_send_inv(struct irq_data *d)
4001{
4002 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4003
4004 if (gic_rdists->has_direct_lpi)
4005 __direct_lpi_inv(d, d->parent_data->hwirq);
4006 else
4007 its_vpe_send_cmd(vpe, its_send_inv);
4008}
4009
4010static void its_vpe_mask_irq(struct irq_data *d)
4011{
4012 /*
4013 * We need to unmask the LPI, which is described by the parent
4014 * irq_data. Instead of calling into the parent (which won't
4015 * exactly do the right thing, let's simply use the
4016 * parent_data pointer. Yes, I'm naughty.
4017 */
4018 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4019 its_vpe_send_inv(d);
4020}
4021
4022static void its_vpe_unmask_irq(struct irq_data *d)
4023{
4024 /* Same hack as above... */
4025 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4026 its_vpe_send_inv(d);
4027}
4028
4029static int its_vpe_set_irqchip_state(struct irq_data *d,
4030 enum irqchip_irq_state which,
4031 bool state)
4032{
4033 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4034
4035 if (which != IRQCHIP_STATE_PENDING)
4036 return -EINVAL;
4037
4038 if (gic_rdists->has_direct_lpi) {
4039 void __iomem *rdbase;
4040
4041 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
4042 if (state) {
4043 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
4044 } else {
4045 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
4046 wait_for_syncr(rdbase);
4047 }
4048 } else {
4049 if (state)
4050 its_vpe_send_cmd(vpe, its_send_int);
4051 else
4052 its_vpe_send_cmd(vpe, its_send_clear);
4053 }
4054
4055 return 0;
4056}
4057
4058static int its_vpe_retrigger(struct irq_data *d)
4059{
4060 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
4061}
4062
4063static struct irq_chip its_vpe_irq_chip = {
4064 .name = "GICv4-vpe",
4065 .irq_mask = its_vpe_mask_irq,
4066 .irq_unmask = its_vpe_unmask_irq,
4067 .irq_eoi = irq_chip_eoi_parent,
4068 .irq_set_affinity = its_vpe_set_affinity,
4069 .irq_retrigger = its_vpe_retrigger,
4070 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
4071 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
4072};
4073
4074static struct its_node *find_4_1_its(void)
4075{
4076 static struct its_node *its = NULL;
4077
4078 if (!its) {
4079 list_for_each_entry(its, &its_nodes, entry) {
4080 if (is_v4_1(its))
4081 return its;
4082 }
4083
4084 /* Oops? */
4085 its = NULL;
4086 }
4087
4088 return its;
4089}
4090
4091static void its_vpe_4_1_send_inv(struct irq_data *d)
4092{
4093 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4094 struct its_node *its;
4095
4096 /*
4097 * GICv4.1 wants doorbells to be invalidated using the
4098 * INVDB command in order to be broadcast to all RDs. Send
4099 * it to the first valid ITS, and let the HW do its magic.
4100 */
4101 its = find_4_1_its();
4102 if (its)
4103 its_send_invdb(its, vpe);
4104}
4105
4106static void its_vpe_4_1_mask_irq(struct irq_data *d)
4107{
4108 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4109 its_vpe_4_1_send_inv(d);
4110}
4111
4112static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4113{
4114 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4115 its_vpe_4_1_send_inv(d);
4116}
4117
4118static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4119 struct its_cmd_info *info)
4120{
4121 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4122 u64 val = 0;
4123
4124 /* Schedule the VPE */
4125 val |= GICR_VPENDBASER_Valid;
4126 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4127 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4128 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4129
4130 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4131}
4132
4133static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4134 struct its_cmd_info *info)
4135{
4136 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4137 u64 val;
4138
4139 if (info->req_db) {
4140 unsigned long flags;
4141
4142 /*
4143 * vPE is going to block: make the vPE non-resident with
4144 * PendingLast clear and DB set. The GIC guarantees that if
4145 * we read-back PendingLast clear, then a doorbell will be
4146 * delivered when an interrupt comes.
4147 *
4148 * Note the locking to deal with the concurrent update of
4149 * pending_last from the doorbell interrupt handler that can
4150 * run concurrently.
4151 */
4152 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4153 val = its_clear_vpend_valid(vlpi_base,
4154 GICR_VPENDBASER_PendingLast,
4155 GICR_VPENDBASER_4_1_DB);
4156 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4157 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4158 } else {
4159 /*
4160 * We're not blocking, so just make the vPE non-resident
4161 * with PendingLast set, indicating that we'll be back.
4162 */
4163 val = its_clear_vpend_valid(vlpi_base,
4164 0,
4165 GICR_VPENDBASER_PendingLast);
4166 vpe->pending_last = true;
4167 }
4168}
4169
4170static void its_vpe_4_1_invall(struct its_vpe *vpe)
4171{
4172 void __iomem *rdbase;
4173 unsigned long flags;
4174 u64 val;
4175 int cpu;
4176
4177 val = GICR_INVALLR_V;
4178 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4179
4180 /* Target the redistributor this vPE is currently known on */
4181 cpu = vpe_to_cpuid_lock(vpe, &flags);
4182 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4183 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4184 gic_write_lpir(val, rdbase + GICR_INVALLR);
4185
4186 wait_for_syncr(rdbase);
4187 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4188 vpe_to_cpuid_unlock(vpe, flags);
4189}
4190
4191static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4192{
4193 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4194 struct its_cmd_info *info = vcpu_info;
4195
4196 switch (info->cmd_type) {
4197 case SCHEDULE_VPE:
4198 its_vpe_4_1_schedule(vpe, info);
4199 return 0;
4200
4201 case DESCHEDULE_VPE:
4202 its_vpe_4_1_deschedule(vpe, info);
4203 return 0;
4204
4205 case COMMIT_VPE:
4206 its_wait_vpt_parse_complete();
4207 return 0;
4208
4209 case INVALL_VPE:
4210 its_vpe_4_1_invall(vpe);
4211 return 0;
4212
4213 default:
4214 return -EINVAL;
4215 }
4216}
4217
4218static struct irq_chip its_vpe_4_1_irq_chip = {
4219 .name = "GICv4.1-vpe",
4220 .irq_mask = its_vpe_4_1_mask_irq,
4221 .irq_unmask = its_vpe_4_1_unmask_irq,
4222 .irq_eoi = irq_chip_eoi_parent,
4223 .irq_set_affinity = its_vpe_set_affinity,
4224 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4225};
4226
4227static void its_configure_sgi(struct irq_data *d, bool clear)
4228{
4229 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4230 struct its_cmd_desc desc;
4231
4232 desc.its_vsgi_cmd.vpe = vpe;
4233 desc.its_vsgi_cmd.sgi = d->hwirq;
4234 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4235 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4236 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4237 desc.its_vsgi_cmd.clear = clear;
4238
4239 /*
4240 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4241 * destination VPE is mapped there. Since we map them eagerly at
4242 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4243 */
4244 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4245}
4246
4247static void its_sgi_mask_irq(struct irq_data *d)
4248{
4249 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4250
4251 vpe->sgi_config[d->hwirq].enabled = false;
4252 its_configure_sgi(d, false);
4253}
4254
4255static void its_sgi_unmask_irq(struct irq_data *d)
4256{
4257 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4258
4259 vpe->sgi_config[d->hwirq].enabled = true;
4260 its_configure_sgi(d, false);
4261}
4262
4263static int its_sgi_set_affinity(struct irq_data *d,
4264 const struct cpumask *mask_val,
4265 bool force)
4266{
4267 /*
4268 * There is no notion of affinity for virtual SGIs, at least
4269 * not on the host (since they can only be targeting a vPE).
4270 * Tell the kernel we've done whatever it asked for.
4271 */
4272 irq_data_update_effective_affinity(d, mask_val);
4273 return IRQ_SET_MASK_OK;
4274}
4275
4276static int its_sgi_set_irqchip_state(struct irq_data *d,
4277 enum irqchip_irq_state which,
4278 bool state)
4279{
4280 if (which != IRQCHIP_STATE_PENDING)
4281 return -EINVAL;
4282
4283 if (state) {
4284 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4285 struct its_node *its = find_4_1_its();
4286 u64 val;
4287
4288 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4289 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4290 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4291 } else {
4292 its_configure_sgi(d, true);
4293 }
4294
4295 return 0;
4296}
4297
4298static int its_sgi_get_irqchip_state(struct irq_data *d,
4299 enum irqchip_irq_state which, bool *val)
4300{
4301 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4302 void __iomem *base;
4303 unsigned long flags;
4304 u32 count = 1000000; /* 1s! */
4305 u32 status;
4306 int cpu;
4307
4308 if (which != IRQCHIP_STATE_PENDING)
4309 return -EINVAL;
4310
4311 /*
4312 * Locking galore! We can race against two different events:
4313 *
4314 * - Concurrent vPE affinity change: we must make sure it cannot
4315 * happen, or we'll talk to the wrong redistributor. This is
4316 * identical to what happens with vLPIs.
4317 *
4318 * - Concurrent VSGIPENDR access: As it involves accessing two
4319 * MMIO registers, this must be made atomic one way or another.
4320 */
4321 cpu = vpe_to_cpuid_lock(vpe, &flags);
4322 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4323 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4324 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4325 do {
4326 status = readl_relaxed(base + GICR_VSGIPENDR);
4327 if (!(status & GICR_VSGIPENDR_BUSY))
4328 goto out;
4329
4330 count--;
4331 if (!count) {
4332 pr_err_ratelimited("Unable to get SGI status\n");
4333 goto out;
4334 }
4335 cpu_relax();
4336 udelay(1);
4337 } while (count);
4338
4339out:
4340 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4341 vpe_to_cpuid_unlock(vpe, flags);
4342
4343 if (!count)
4344 return -ENXIO;
4345
4346 *val = !!(status & (1 << d->hwirq));
4347
4348 return 0;
4349}
4350
4351static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4352{
4353 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4354 struct its_cmd_info *info = vcpu_info;
4355
4356 switch (info->cmd_type) {
4357 case PROP_UPDATE_VSGI:
4358 vpe->sgi_config[d->hwirq].priority = info->priority;
4359 vpe->sgi_config[d->hwirq].group = info->group;
4360 its_configure_sgi(d, false);
4361 return 0;
4362
4363 default:
4364 return -EINVAL;
4365 }
4366}
4367
4368static struct irq_chip its_sgi_irq_chip = {
4369 .name = "GICv4.1-sgi",
4370 .irq_mask = its_sgi_mask_irq,
4371 .irq_unmask = its_sgi_unmask_irq,
4372 .irq_set_affinity = its_sgi_set_affinity,
4373 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4374 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
4375 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
4376};
4377
4378static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4379 unsigned int virq, unsigned int nr_irqs,
4380 void *args)
4381{
4382 struct its_vpe *vpe = args;
4383 int i;
4384
4385 /* Yes, we do want 16 SGIs */
4386 WARN_ON(nr_irqs != 16);
4387
4388 for (i = 0; i < 16; i++) {
4389 vpe->sgi_config[i].priority = 0;
4390 vpe->sgi_config[i].enabled = false;
4391 vpe->sgi_config[i].group = false;
4392
4393 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4394 &its_sgi_irq_chip, vpe);
4395 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4396 }
4397
4398 return 0;
4399}
4400
4401static void its_sgi_irq_domain_free(struct irq_domain *domain,
4402 unsigned int virq,
4403 unsigned int nr_irqs)
4404{
4405 /* Nothing to do */
4406}
4407
4408static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4409 struct irq_data *d, bool reserve)
4410{
4411 /* Write out the initial SGI configuration */
4412 its_configure_sgi(d, false);
4413 return 0;
4414}
4415
4416static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4417 struct irq_data *d)
4418{
4419 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4420
4421 /*
4422 * The VSGI command is awkward:
4423 *
4424 * - To change the configuration, CLEAR must be set to false,
4425 * leaving the pending bit unchanged.
4426 * - To clear the pending bit, CLEAR must be set to true, leaving
4427 * the configuration unchanged.
4428 *
4429 * You just can't do both at once, hence the two commands below.
4430 */
4431 vpe->sgi_config[d->hwirq].enabled = false;
4432 its_configure_sgi(d, false);
4433 its_configure_sgi(d, true);
4434}
4435
4436static const struct irq_domain_ops its_sgi_domain_ops = {
4437 .alloc = its_sgi_irq_domain_alloc,
4438 .free = its_sgi_irq_domain_free,
4439 .activate = its_sgi_irq_domain_activate,
4440 .deactivate = its_sgi_irq_domain_deactivate,
4441};
4442
4443static int its_vpe_id_alloc(void)
4444{
4445 return ida_alloc_max(&its_vpeid_ida, ITS_MAX_VPEID - 1, GFP_KERNEL);
4446}
4447
4448static void its_vpe_id_free(u16 id)
4449{
4450 ida_free(&its_vpeid_ida, id);
4451}
4452
4453static int its_vpe_init(struct its_vpe *vpe)
4454{
4455 struct page *vpt_page;
4456 int vpe_id;
4457
4458 /* Allocate vpe_id */
4459 vpe_id = its_vpe_id_alloc();
4460 if (vpe_id < 0)
4461 return vpe_id;
4462
4463 /* Allocate VPT */
4464 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4465 if (!vpt_page) {
4466 its_vpe_id_free(vpe_id);
4467 return -ENOMEM;
4468 }
4469
4470 if (!its_alloc_vpe_table(vpe_id)) {
4471 its_vpe_id_free(vpe_id);
4472 its_free_pending_table(vpt_page);
4473 return -ENOMEM;
4474 }
4475
4476 raw_spin_lock_init(&vpe->vpe_lock);
4477 vpe->vpe_id = vpe_id;
4478 vpe->vpt_page = vpt_page;
4479 if (gic_rdists->has_rvpeid)
4480 atomic_set(&vpe->vmapp_count, 0);
4481 else
4482 vpe->vpe_proxy_event = -1;
4483
4484 return 0;
4485}
4486
4487static void its_vpe_teardown(struct its_vpe *vpe)
4488{
4489 its_vpe_db_proxy_unmap(vpe);
4490 its_vpe_id_free(vpe->vpe_id);
4491 its_free_pending_table(vpe->vpt_page);
4492}
4493
4494static void its_vpe_irq_domain_free(struct irq_domain *domain,
4495 unsigned int virq,
4496 unsigned int nr_irqs)
4497{
4498 struct its_vm *vm = domain->host_data;
4499 int i;
4500
4501 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4502
4503 for (i = 0; i < nr_irqs; i++) {
4504 struct irq_data *data = irq_domain_get_irq_data(domain,
4505 virq + i);
4506 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4507
4508 BUG_ON(vm != vpe->its_vm);
4509
4510 clear_bit(data->hwirq, vm->db_bitmap);
4511 its_vpe_teardown(vpe);
4512 irq_domain_reset_irq_data(data);
4513 }
4514
4515 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4516 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4517 its_free_prop_table(vm->vprop_page);
4518 }
4519}
4520
4521static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4522 unsigned int nr_irqs, void *args)
4523{
4524 struct irq_chip *irqchip = &its_vpe_irq_chip;
4525 struct its_vm *vm = args;
4526 unsigned long *bitmap;
4527 struct page *vprop_page;
4528 int base, nr_ids, i, err = 0;
4529
4530 BUG_ON(!vm);
4531
4532 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4533 if (!bitmap)
4534 return -ENOMEM;
4535
4536 if (nr_ids < nr_irqs) {
4537 its_lpi_free(bitmap, base, nr_ids);
4538 return -ENOMEM;
4539 }
4540
4541 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4542 if (!vprop_page) {
4543 its_lpi_free(bitmap, base, nr_ids);
4544 return -ENOMEM;
4545 }
4546
4547 vm->db_bitmap = bitmap;
4548 vm->db_lpi_base = base;
4549 vm->nr_db_lpis = nr_ids;
4550 vm->vprop_page = vprop_page;
4551
4552 if (gic_rdists->has_rvpeid)
4553 irqchip = &its_vpe_4_1_irq_chip;
4554
4555 for (i = 0; i < nr_irqs; i++) {
4556 vm->vpes[i]->vpe_db_lpi = base + i;
4557 err = its_vpe_init(vm->vpes[i]);
4558 if (err)
4559 break;
4560 err = its_irq_gic_domain_alloc(domain, virq + i,
4561 vm->vpes[i]->vpe_db_lpi);
4562 if (err)
4563 break;
4564 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4565 irqchip, vm->vpes[i]);
4566 set_bit(i, bitmap);
4567 irqd_set_resend_when_in_progress(irq_get_irq_data(virq + i));
4568 }
4569
4570 if (err)
4571 its_vpe_irq_domain_free(domain, virq, i);
4572
4573 return err;
4574}
4575
4576static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4577 struct irq_data *d, bool reserve)
4578{
4579 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4580 struct its_node *its;
4581
4582 /*
4583 * If we use the list map, we issue VMAPP on demand... Unless
4584 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4585 * so that VSGIs can work.
4586 */
4587 if (!gic_requires_eager_mapping())
4588 return 0;
4589
4590 /* Map the VPE to the first possible CPU */
4591 vpe->col_idx = cpumask_first(cpu_online_mask);
4592
4593 list_for_each_entry(its, &its_nodes, entry) {
4594 if (!is_v4(its))
4595 continue;
4596
4597 its_send_vmapp(its, vpe, true);
4598 its_send_vinvall(its, vpe);
4599 }
4600
4601 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4602
4603 return 0;
4604}
4605
4606static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4607 struct irq_data *d)
4608{
4609 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4610 struct its_node *its;
4611
4612 /*
4613 * If we use the list map on GICv4.0, we unmap the VPE once no
4614 * VLPIs are associated with the VM.
4615 */
4616 if (!gic_requires_eager_mapping())
4617 return;
4618
4619 list_for_each_entry(its, &its_nodes, entry) {
4620 if (!is_v4(its))
4621 continue;
4622
4623 its_send_vmapp(its, vpe, false);
4624 }
4625
4626 /*
4627 * There may be a direct read to the VPT after unmapping the
4628 * vPE, to guarantee the validity of this, we make the VPT
4629 * memory coherent with the CPU caches here.
4630 */
4631 if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))
4632 gic_flush_dcache_to_poc(page_address(vpe->vpt_page),
4633 LPI_PENDBASE_SZ);
4634}
4635
4636static const struct irq_domain_ops its_vpe_domain_ops = {
4637 .alloc = its_vpe_irq_domain_alloc,
4638 .free = its_vpe_irq_domain_free,
4639 .activate = its_vpe_irq_domain_activate,
4640 .deactivate = its_vpe_irq_domain_deactivate,
4641};
4642
4643static int its_force_quiescent(void __iomem *base)
4644{
4645 u32 count = 1000000; /* 1s */
4646 u32 val;
4647
4648 val = readl_relaxed(base + GITS_CTLR);
4649 /*
4650 * GIC architecture specification requires the ITS to be both
4651 * disabled and quiescent for writes to GITS_BASER<n> or
4652 * GITS_CBASER to not have UNPREDICTABLE results.
4653 */
4654 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4655 return 0;
4656
4657 /* Disable the generation of all interrupts to this ITS */
4658 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4659 writel_relaxed(val, base + GITS_CTLR);
4660
4661 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4662 while (1) {
4663 val = readl_relaxed(base + GITS_CTLR);
4664 if (val & GITS_CTLR_QUIESCENT)
4665 return 0;
4666
4667 count--;
4668 if (!count)
4669 return -EBUSY;
4670
4671 cpu_relax();
4672 udelay(1);
4673 }
4674}
4675
4676static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4677{
4678 struct its_node *its = data;
4679
4680 /* erratum 22375: only alloc 8MB table size (20 bits) */
4681 its->typer &= ~GITS_TYPER_DEVBITS;
4682 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4683 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4684
4685 return true;
4686}
4687
4688static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4689{
4690 struct its_node *its = data;
4691
4692 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4693
4694 return true;
4695}
4696
4697static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4698{
4699 struct its_node *its = data;
4700
4701 /* On QDF2400, the size of the ITE is 16Bytes */
4702 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4703 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4704
4705 return true;
4706}
4707
4708static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4709{
4710 struct its_node *its = its_dev->its;
4711
4712 /*
4713 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4714 * which maps 32-bit writes targeted at a separate window of
4715 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4716 * with device ID taken from bits [device_id_bits + 1:2] of
4717 * the window offset.
4718 */
4719 return its->pre_its_base + (its_dev->device_id << 2);
4720}
4721
4722static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4723{
4724 struct its_node *its = data;
4725 u32 pre_its_window[2];
4726 u32 ids;
4727
4728 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4729 "socionext,synquacer-pre-its",
4730 pre_its_window,
4731 ARRAY_SIZE(pre_its_window))) {
4732
4733 its->pre_its_base = pre_its_window[0];
4734 its->get_msi_base = its_irq_get_msi_base_pre_its;
4735
4736 ids = ilog2(pre_its_window[1]) - 2;
4737 if (device_ids(its) > ids) {
4738 its->typer &= ~GITS_TYPER_DEVBITS;
4739 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4740 }
4741
4742 /* the pre-ITS breaks isolation, so disable MSI remapping */
4743 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI;
4744 return true;
4745 }
4746 return false;
4747}
4748
4749static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4750{
4751 struct its_node *its = data;
4752
4753 /*
4754 * Hip07 insists on using the wrong address for the VLPI
4755 * page. Trick it into doing the right thing...
4756 */
4757 its->vlpi_redist_offset = SZ_128K;
4758 return true;
4759}
4760
4761static bool __maybe_unused its_enable_rk3588001(void *data)
4762{
4763 struct its_node *its = data;
4764
4765 if (!of_machine_is_compatible("rockchip,rk3588") &&
4766 !of_machine_is_compatible("rockchip,rk3588s"))
4767 return false;
4768
4769 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
4770 gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;
4771
4772 return true;
4773}
4774
4775static bool its_set_non_coherent(void *data)
4776{
4777 struct its_node *its = data;
4778
4779 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
4780 return true;
4781}
4782
4783static const struct gic_quirk its_quirks[] = {
4784#ifdef CONFIG_CAVIUM_ERRATUM_22375
4785 {
4786 .desc = "ITS: Cavium errata 22375, 24313",
4787 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4788 .mask = 0xffff0fff,
4789 .init = its_enable_quirk_cavium_22375,
4790 },
4791#endif
4792#ifdef CONFIG_CAVIUM_ERRATUM_23144
4793 {
4794 .desc = "ITS: Cavium erratum 23144",
4795 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4796 .mask = 0xffff0fff,
4797 .init = its_enable_quirk_cavium_23144,
4798 },
4799#endif
4800#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4801 {
4802 .desc = "ITS: QDF2400 erratum 0065",
4803 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4804 .mask = 0xffffffff,
4805 .init = its_enable_quirk_qdf2400_e0065,
4806 },
4807#endif
4808#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4809 {
4810 /*
4811 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4812 * implementation, but with a 'pre-ITS' added that requires
4813 * special handling in software.
4814 */
4815 .desc = "ITS: Socionext Synquacer pre-ITS",
4816 .iidr = 0x0001143b,
4817 .mask = 0xffffffff,
4818 .init = its_enable_quirk_socionext_synquacer,
4819 },
4820#endif
4821#ifdef CONFIG_HISILICON_ERRATUM_161600802
4822 {
4823 .desc = "ITS: Hip07 erratum 161600802",
4824 .iidr = 0x00000004,
4825 .mask = 0xffffffff,
4826 .init = its_enable_quirk_hip07_161600802,
4827 },
4828#endif
4829#ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
4830 {
4831 .desc = "ITS: Rockchip erratum RK3588001",
4832 .iidr = 0x0201743b,
4833 .mask = 0xffffffff,
4834 .init = its_enable_rk3588001,
4835 },
4836#endif
4837 {
4838 .desc = "ITS: non-coherent attribute",
4839 .property = "dma-noncoherent",
4840 .init = its_set_non_coherent,
4841 },
4842 {
4843 }
4844};
4845
4846static void its_enable_quirks(struct its_node *its)
4847{
4848 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4849
4850 gic_enable_quirks(iidr, its_quirks, its);
4851
4852 if (is_of_node(its->fwnode_handle))
4853 gic_enable_of_quirks(to_of_node(its->fwnode_handle),
4854 its_quirks, its);
4855}
4856
4857static int its_save_disable(void)
4858{
4859 struct its_node *its;
4860 int err = 0;
4861
4862 raw_spin_lock(&its_lock);
4863 list_for_each_entry(its, &its_nodes, entry) {
4864 void __iomem *base;
4865
4866 base = its->base;
4867 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4868 err = its_force_quiescent(base);
4869 if (err) {
4870 pr_err("ITS@%pa: failed to quiesce: %d\n",
4871 &its->phys_base, err);
4872 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4873 goto err;
4874 }
4875
4876 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4877 }
4878
4879err:
4880 if (err) {
4881 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4882 void __iomem *base;
4883
4884 base = its->base;
4885 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4886 }
4887 }
4888 raw_spin_unlock(&its_lock);
4889
4890 return err;
4891}
4892
4893static void its_restore_enable(void)
4894{
4895 struct its_node *its;
4896 int ret;
4897
4898 raw_spin_lock(&its_lock);
4899 list_for_each_entry(its, &its_nodes, entry) {
4900 void __iomem *base;
4901 int i;
4902
4903 base = its->base;
4904
4905 /*
4906 * Make sure that the ITS is disabled. If it fails to quiesce,
4907 * don't restore it since writing to CBASER or BASER<n>
4908 * registers is undefined according to the GIC v3 ITS
4909 * Specification.
4910 *
4911 * Firmware resuming with the ITS enabled is terminally broken.
4912 */
4913 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
4914 ret = its_force_quiescent(base);
4915 if (ret) {
4916 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4917 &its->phys_base, ret);
4918 continue;
4919 }
4920
4921 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4922
4923 /*
4924 * Writing CBASER resets CREADR to 0, so make CWRITER and
4925 * cmd_write line up with it.
4926 */
4927 its->cmd_write = its->cmd_base;
4928 gits_write_cwriter(0, base + GITS_CWRITER);
4929
4930 /* Restore GITS_BASER from the value cache. */
4931 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4932 struct its_baser *baser = &its->tables[i];
4933
4934 if (!(baser->val & GITS_BASER_VALID))
4935 continue;
4936
4937 its_write_baser(its, baser, baser->val);
4938 }
4939 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4940
4941 /*
4942 * Reinit the collection if it's stored in the ITS. This is
4943 * indicated by the col_id being less than the HCC field.
4944 * CID < HCC as specified in the GIC v3 Documentation.
4945 */
4946 if (its->collections[smp_processor_id()].col_id <
4947 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4948 its_cpu_init_collection(its);
4949 }
4950 raw_spin_unlock(&its_lock);
4951}
4952
4953static struct syscore_ops its_syscore_ops = {
4954 .suspend = its_save_disable,
4955 .resume = its_restore_enable,
4956};
4957
4958static void __init __iomem *its_map_one(struct resource *res, int *err)
4959{
4960 void __iomem *its_base;
4961 u32 val;
4962
4963 its_base = ioremap(res->start, SZ_64K);
4964 if (!its_base) {
4965 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4966 *err = -ENOMEM;
4967 return NULL;
4968 }
4969
4970 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4971 if (val != 0x30 && val != 0x40) {
4972 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4973 *err = -ENODEV;
4974 goto out_unmap;
4975 }
4976
4977 *err = its_force_quiescent(its_base);
4978 if (*err) {
4979 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4980 goto out_unmap;
4981 }
4982
4983 return its_base;
4984
4985out_unmap:
4986 iounmap(its_base);
4987 return NULL;
4988}
4989
4990static int its_init_domain(struct its_node *its)
4991{
4992 struct irq_domain *inner_domain;
4993 struct msi_domain_info *info;
4994
4995 info = kzalloc(sizeof(*info), GFP_KERNEL);
4996 if (!info)
4997 return -ENOMEM;
4998
4999 info->ops = &its_msi_domain_ops;
5000 info->data = its;
5001
5002 inner_domain = irq_domain_create_hierarchy(its_parent,
5003 its->msi_domain_flags, 0,
5004 its->fwnode_handle, &its_domain_ops,
5005 info);
5006 if (!inner_domain) {
5007 kfree(info);
5008 return -ENOMEM;
5009 }
5010
5011 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
5012
5013 return 0;
5014}
5015
5016static int its_init_vpe_domain(void)
5017{
5018 struct its_node *its;
5019 u32 devid;
5020 int entries;
5021
5022 if (gic_rdists->has_direct_lpi) {
5023 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
5024 return 0;
5025 }
5026
5027 /* Any ITS will do, even if not v4 */
5028 its = list_first_entry(&its_nodes, struct its_node, entry);
5029
5030 entries = roundup_pow_of_two(nr_cpu_ids);
5031 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
5032 GFP_KERNEL);
5033 if (!vpe_proxy.vpes)
5034 return -ENOMEM;
5035
5036 /* Use the last possible DevID */
5037 devid = GENMASK(device_ids(its) - 1, 0);
5038 vpe_proxy.dev = its_create_device(its, devid, entries, false);
5039 if (!vpe_proxy.dev) {
5040 kfree(vpe_proxy.vpes);
5041 pr_err("ITS: Can't allocate GICv4 proxy device\n");
5042 return -ENOMEM;
5043 }
5044
5045 BUG_ON(entries > vpe_proxy.dev->nr_ites);
5046
5047 raw_spin_lock_init(&vpe_proxy.lock);
5048 vpe_proxy.next_victim = 0;
5049 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
5050 devid, vpe_proxy.dev->nr_ites);
5051
5052 return 0;
5053}
5054
5055static int __init its_compute_its_list_map(struct its_node *its)
5056{
5057 int its_number;
5058 u32 ctlr;
5059
5060 /*
5061 * This is assumed to be done early enough that we're
5062 * guaranteed to be single-threaded, hence no
5063 * locking. Should this change, we should address
5064 * this.
5065 */
5066 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
5067 if (its_number >= GICv4_ITS_LIST_MAX) {
5068 pr_err("ITS@%pa: No ITSList entry available!\n",
5069 &its->phys_base);
5070 return -EINVAL;
5071 }
5072
5073 ctlr = readl_relaxed(its->base + GITS_CTLR);
5074 ctlr &= ~GITS_CTLR_ITS_NUMBER;
5075 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
5076 writel_relaxed(ctlr, its->base + GITS_CTLR);
5077 ctlr = readl_relaxed(its->base + GITS_CTLR);
5078 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
5079 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
5080 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
5081 }
5082
5083 if (test_and_set_bit(its_number, &its_list_map)) {
5084 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
5085 &its->phys_base, its_number);
5086 return -EINVAL;
5087 }
5088
5089 return its_number;
5090}
5091
5092static int __init its_probe_one(struct its_node *its)
5093{
5094 u64 baser, tmp;
5095 struct page *page;
5096 u32 ctlr;
5097 int err;
5098
5099 its_enable_quirks(its);
5100
5101 if (is_v4(its)) {
5102 if (!(its->typer & GITS_TYPER_VMOVP)) {
5103 err = its_compute_its_list_map(its);
5104 if (err < 0)
5105 goto out;
5106
5107 its->list_nr = err;
5108
5109 pr_info("ITS@%pa: Using ITS number %d\n",
5110 &its->phys_base, err);
5111 } else {
5112 pr_info("ITS@%pa: Single VMOVP capable\n", &its->phys_base);
5113 }
5114
5115 if (is_v4_1(its)) {
5116 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
5117
5118 its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K);
5119 if (!its->sgir_base) {
5120 err = -ENOMEM;
5121 goto out;
5122 }
5123
5124 its->mpidr = readl_relaxed(its->base + GITS_MPIDR);
5125
5126 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5127 &its->phys_base, its->mpidr, svpet);
5128 }
5129 }
5130
5131 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5132 get_order(ITS_CMD_QUEUE_SZ));
5133 if (!page) {
5134 err = -ENOMEM;
5135 goto out_unmap_sgir;
5136 }
5137 its->cmd_base = (void *)page_address(page);
5138 its->cmd_write = its->cmd_base;
5139
5140 err = its_alloc_tables(its);
5141 if (err)
5142 goto out_free_cmd;
5143
5144 err = its_alloc_collections(its);
5145 if (err)
5146 goto out_free_tables;
5147
5148 baser = (virt_to_phys(its->cmd_base) |
5149 GITS_CBASER_RaWaWb |
5150 GITS_CBASER_InnerShareable |
5151 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5152 GITS_CBASER_VALID);
5153
5154 gits_write_cbaser(baser, its->base + GITS_CBASER);
5155 tmp = gits_read_cbaser(its->base + GITS_CBASER);
5156
5157 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
5158 tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
5159
5160 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5161 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5162 /*
5163 * The HW reports non-shareable, we must
5164 * remove the cacheability attributes as
5165 * well.
5166 */
5167 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5168 GITS_CBASER_CACHEABILITY_MASK);
5169 baser |= GITS_CBASER_nC;
5170 gits_write_cbaser(baser, its->base + GITS_CBASER);
5171 }
5172 pr_info("ITS: using cache flushing for cmd queue\n");
5173 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5174 }
5175
5176 gits_write_cwriter(0, its->base + GITS_CWRITER);
5177 ctlr = readl_relaxed(its->base + GITS_CTLR);
5178 ctlr |= GITS_CTLR_ENABLE;
5179 if (is_v4(its))
5180 ctlr |= GITS_CTLR_ImDe;
5181 writel_relaxed(ctlr, its->base + GITS_CTLR);
5182
5183 err = its_init_domain(its);
5184 if (err)
5185 goto out_free_tables;
5186
5187 raw_spin_lock(&its_lock);
5188 list_add(&its->entry, &its_nodes);
5189 raw_spin_unlock(&its_lock);
5190
5191 return 0;
5192
5193out_free_tables:
5194 its_free_tables(its);
5195out_free_cmd:
5196 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5197out_unmap_sgir:
5198 if (its->sgir_base)
5199 iounmap(its->sgir_base);
5200out:
5201 pr_err("ITS@%pa: failed probing (%d)\n", &its->phys_base, err);
5202 return err;
5203}
5204
5205static bool gic_rdists_supports_plpis(void)
5206{
5207 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5208}
5209
5210static int redist_disable_lpis(void)
5211{
5212 void __iomem *rbase = gic_data_rdist_rd_base();
5213 u64 timeout = USEC_PER_SEC;
5214 u64 val;
5215
5216 if (!gic_rdists_supports_plpis()) {
5217 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5218 return -ENXIO;
5219 }
5220
5221 val = readl_relaxed(rbase + GICR_CTLR);
5222 if (!(val & GICR_CTLR_ENABLE_LPIS))
5223 return 0;
5224
5225 /*
5226 * If coming via a CPU hotplug event, we don't need to disable
5227 * LPIs before trying to re-enable them. They are already
5228 * configured and all is well in the world.
5229 *
5230 * If running with preallocated tables, there is nothing to do.
5231 */
5232 if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||
5233 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5234 return 0;
5235
5236 /*
5237 * From that point on, we only try to do some damage control.
5238 */
5239 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5240 smp_processor_id());
5241 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5242
5243 /* Disable LPIs */
5244 val &= ~GICR_CTLR_ENABLE_LPIS;
5245 writel_relaxed(val, rbase + GICR_CTLR);
5246
5247 /* Make sure any change to GICR_CTLR is observable by the GIC */
5248 dsb(sy);
5249
5250 /*
5251 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5252 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5253 * Error out if we time out waiting for RWP to clear.
5254 */
5255 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5256 if (!timeout) {
5257 pr_err("CPU%d: Timeout while disabling LPIs\n",
5258 smp_processor_id());
5259 return -ETIMEDOUT;
5260 }
5261 udelay(1);
5262 timeout--;
5263 }
5264
5265 /*
5266 * After it has been written to 1, it is IMPLEMENTATION
5267 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5268 * cleared to 0. Error out if clearing the bit failed.
5269 */
5270 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5271 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5272 return -EBUSY;
5273 }
5274
5275 return 0;
5276}
5277
5278int its_cpu_init(void)
5279{
5280 if (!list_empty(&its_nodes)) {
5281 int ret;
5282
5283 ret = redist_disable_lpis();
5284 if (ret)
5285 return ret;
5286
5287 its_cpu_init_lpis();
5288 its_cpu_init_collections();
5289 }
5290
5291 return 0;
5292}
5293
5294static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)
5295{
5296 cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state);
5297 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5298}
5299
5300static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,
5301 rdist_memreserve_cpuhp_cleanup_workfn);
5302
5303static int its_cpu_memreserve_lpi(unsigned int cpu)
5304{
5305 struct page *pend_page;
5306 int ret = 0;
5307
5308 /* This gets to run exactly once per CPU */
5309 if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)
5310 return 0;
5311
5312 pend_page = gic_data_rdist()->pend_page;
5313 if (WARN_ON(!pend_page)) {
5314 ret = -ENOMEM;
5315 goto out;
5316 }
5317 /*
5318 * If the pending table was pre-programmed, free the memory we
5319 * preemptively allocated. Otherwise, reserve that memory for
5320 * later kexecs.
5321 */
5322 if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {
5323 its_free_pending_table(pend_page);
5324 gic_data_rdist()->pend_page = NULL;
5325 } else {
5326 phys_addr_t paddr = page_to_phys(pend_page);
5327 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
5328 }
5329
5330out:
5331 /* Last CPU being brought up gets to issue the cleanup */
5332 if (!IS_ENABLED(CONFIG_SMP) ||
5333 cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5334 schedule_work(&rdist_memreserve_cpuhp_cleanup_work);
5335
5336 gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
5337 return ret;
5338}
5339
5340/* Mark all the BASER registers as invalid before they get reprogrammed */
5341static int __init its_reset_one(struct resource *res)
5342{
5343 void __iomem *its_base;
5344 int err, i;
5345
5346 its_base = its_map_one(res, &err);
5347 if (!its_base)
5348 return err;
5349
5350 for (i = 0; i < GITS_BASER_NR_REGS; i++)
5351 gits_write_baser(0, its_base + GITS_BASER + (i << 3));
5352
5353 iounmap(its_base);
5354 return 0;
5355}
5356
5357static const struct of_device_id its_device_id[] = {
5358 { .compatible = "arm,gic-v3-its", },
5359 {},
5360};
5361
5362static struct its_node __init *its_node_init(struct resource *res,
5363 struct fwnode_handle *handle, int numa_node)
5364{
5365 void __iomem *its_base;
5366 struct its_node *its;
5367 int err;
5368
5369 its_base = its_map_one(res, &err);
5370 if (!its_base)
5371 return NULL;
5372
5373 pr_info("ITS %pR\n", res);
5374
5375 its = kzalloc(sizeof(*its), GFP_KERNEL);
5376 if (!its)
5377 goto out_unmap;
5378
5379 raw_spin_lock_init(&its->lock);
5380 mutex_init(&its->dev_alloc_lock);
5381 INIT_LIST_HEAD(&its->entry);
5382 INIT_LIST_HEAD(&its->its_device_list);
5383
5384 its->typer = gic_read_typer(its_base + GITS_TYPER);
5385 its->base = its_base;
5386 its->phys_base = res->start;
5387 its->get_msi_base = its_irq_get_msi_base;
5388 its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI;
5389
5390 its->numa_node = numa_node;
5391 its->fwnode_handle = handle;
5392
5393 return its;
5394
5395out_unmap:
5396 iounmap(its_base);
5397 return NULL;
5398}
5399
5400static void its_node_destroy(struct its_node *its)
5401{
5402 iounmap(its->base);
5403 kfree(its);
5404}
5405
5406static int __init its_of_probe(struct device_node *node)
5407{
5408 struct device_node *np;
5409 struct resource res;
5410 int err;
5411
5412 /*
5413 * Make sure *all* the ITS are reset before we probe any, as
5414 * they may be sharing memory. If any of the ITS fails to
5415 * reset, don't even try to go any further, as this could
5416 * result in something even worse.
5417 */
5418 for (np = of_find_matching_node(node, its_device_id); np;
5419 np = of_find_matching_node(np, its_device_id)) {
5420 if (!of_device_is_available(np) ||
5421 !of_property_read_bool(np, "msi-controller") ||
5422 of_address_to_resource(np, 0, &res))
5423 continue;
5424
5425 err = its_reset_one(&res);
5426 if (err)
5427 return err;
5428 }
5429
5430 for (np = of_find_matching_node(node, its_device_id); np;
5431 np = of_find_matching_node(np, its_device_id)) {
5432 struct its_node *its;
5433
5434 if (!of_device_is_available(np))
5435 continue;
5436 if (!of_property_read_bool(np, "msi-controller")) {
5437 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5438 np);
5439 continue;
5440 }
5441
5442 if (of_address_to_resource(np, 0, &res)) {
5443 pr_warn("%pOF: no regs?\n", np);
5444 continue;
5445 }
5446
5447
5448 its = its_node_init(&res, &np->fwnode, of_node_to_nid(np));
5449 if (!its)
5450 return -ENOMEM;
5451
5452 err = its_probe_one(its);
5453 if (err) {
5454 its_node_destroy(its);
5455 return err;
5456 }
5457 }
5458 return 0;
5459}
5460
5461#ifdef CONFIG_ACPI
5462
5463#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5464
5465#ifdef CONFIG_ACPI_NUMA
5466struct its_srat_map {
5467 /* numa node id */
5468 u32 numa_node;
5469 /* GIC ITS ID */
5470 u32 its_id;
5471};
5472
5473static struct its_srat_map *its_srat_maps __initdata;
5474static int its_in_srat __initdata;
5475
5476static int __init acpi_get_its_numa_node(u32 its_id)
5477{
5478 int i;
5479
5480 for (i = 0; i < its_in_srat; i++) {
5481 if (its_id == its_srat_maps[i].its_id)
5482 return its_srat_maps[i].numa_node;
5483 }
5484 return NUMA_NO_NODE;
5485}
5486
5487static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5488 const unsigned long end)
5489{
5490 return 0;
5491}
5492
5493static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5494 const unsigned long end)
5495{
5496 int node;
5497 struct acpi_srat_gic_its_affinity *its_affinity;
5498
5499 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5500 if (!its_affinity)
5501 return -EINVAL;
5502
5503 if (its_affinity->header.length < sizeof(*its_affinity)) {
5504 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5505 its_affinity->header.length);
5506 return -EINVAL;
5507 }
5508
5509 /*
5510 * Note that in theory a new proximity node could be created by this
5511 * entry as it is an SRAT resource allocation structure.
5512 * We do not currently support doing so.
5513 */
5514 node = pxm_to_node(its_affinity->proximity_domain);
5515
5516 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5517 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5518 return 0;
5519 }
5520
5521 its_srat_maps[its_in_srat].numa_node = node;
5522 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5523 its_in_srat++;
5524 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5525 its_affinity->proximity_domain, its_affinity->its_id, node);
5526
5527 return 0;
5528}
5529
5530static void __init acpi_table_parse_srat_its(void)
5531{
5532 int count;
5533
5534 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5535 sizeof(struct acpi_table_srat),
5536 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5537 gic_acpi_match_srat_its, 0);
5538 if (count <= 0)
5539 return;
5540
5541 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5542 GFP_KERNEL);
5543 if (!its_srat_maps)
5544 return;
5545
5546 acpi_table_parse_entries(ACPI_SIG_SRAT,
5547 sizeof(struct acpi_table_srat),
5548 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5549 gic_acpi_parse_srat_its, 0);
5550}
5551
5552/* free the its_srat_maps after ITS probing */
5553static void __init acpi_its_srat_maps_free(void)
5554{
5555 kfree(its_srat_maps);
5556}
5557#else
5558static void __init acpi_table_parse_srat_its(void) { }
5559static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5560static void __init acpi_its_srat_maps_free(void) { }
5561#endif
5562
5563static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5564 const unsigned long end)
5565{
5566 struct acpi_madt_generic_translator *its_entry;
5567 struct fwnode_handle *dom_handle;
5568 struct its_node *its;
5569 struct resource res;
5570 int err;
5571
5572 its_entry = (struct acpi_madt_generic_translator *)header;
5573 memset(&res, 0, sizeof(res));
5574 res.start = its_entry->base_address;
5575 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5576 res.flags = IORESOURCE_MEM;
5577
5578 dom_handle = irq_domain_alloc_fwnode(&res.start);
5579 if (!dom_handle) {
5580 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5581 &res.start);
5582 return -ENOMEM;
5583 }
5584
5585 err = iort_register_domain_token(its_entry->translation_id, res.start,
5586 dom_handle);
5587 if (err) {
5588 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5589 &res.start, its_entry->translation_id);
5590 goto dom_err;
5591 }
5592
5593 its = its_node_init(&res, dom_handle,
5594 acpi_get_its_numa_node(its_entry->translation_id));
5595 if (!its) {
5596 err = -ENOMEM;
5597 goto node_err;
5598 }
5599
5600 err = its_probe_one(its);
5601 if (!err)
5602 return 0;
5603
5604node_err:
5605 iort_deregister_domain_token(its_entry->translation_id);
5606dom_err:
5607 irq_domain_free_fwnode(dom_handle);
5608 return err;
5609}
5610
5611static int __init its_acpi_reset(union acpi_subtable_headers *header,
5612 const unsigned long end)
5613{
5614 struct acpi_madt_generic_translator *its_entry;
5615 struct resource res;
5616
5617 its_entry = (struct acpi_madt_generic_translator *)header;
5618 res = (struct resource) {
5619 .start = its_entry->base_address,
5620 .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
5621 .flags = IORESOURCE_MEM,
5622 };
5623
5624 return its_reset_one(&res);
5625}
5626
5627static void __init its_acpi_probe(void)
5628{
5629 acpi_table_parse_srat_its();
5630 /*
5631 * Make sure *all* the ITS are reset before we probe any, as
5632 * they may be sharing memory. If any of the ITS fails to
5633 * reset, don't even try to go any further, as this could
5634 * result in something even worse.
5635 */
5636 if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5637 its_acpi_reset, 0) > 0)
5638 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5639 gic_acpi_parse_madt_its, 0);
5640 acpi_its_srat_maps_free();
5641}
5642#else
5643static void __init its_acpi_probe(void) { }
5644#endif
5645
5646int __init its_lpi_memreserve_init(void)
5647{
5648 int state;
5649
5650 if (!efi_enabled(EFI_CONFIG_TABLES))
5651 return 0;
5652
5653 if (list_empty(&its_nodes))
5654 return 0;
5655
5656 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5657 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
5658 "irqchip/arm/gicv3/memreserve:online",
5659 its_cpu_memreserve_lpi,
5660 NULL);
5661 if (state < 0)
5662 return state;
5663
5664 gic_rdists->cpuhp_memreserve_state = state;
5665
5666 return 0;
5667}
5668
5669int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5670 struct irq_domain *parent_domain)
5671{
5672 struct device_node *of_node;
5673 struct its_node *its;
5674 bool has_v4 = false;
5675 bool has_v4_1 = false;
5676 int err;
5677
5678 gic_rdists = rdists;
5679
5680 its_parent = parent_domain;
5681 of_node = to_of_node(handle);
5682 if (of_node)
5683 its_of_probe(of_node);
5684 else
5685 its_acpi_probe();
5686
5687 if (list_empty(&its_nodes)) {
5688 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5689 return -ENXIO;
5690 }
5691
5692 err = allocate_lpi_tables();
5693 if (err)
5694 return err;
5695
5696 list_for_each_entry(its, &its_nodes, entry) {
5697 has_v4 |= is_v4(its);
5698 has_v4_1 |= is_v4_1(its);
5699 }
5700
5701 /* Don't bother with inconsistent systems */
5702 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5703 rdists->has_rvpeid = false;
5704
5705 if (has_v4 & rdists->has_vlpis) {
5706 const struct irq_domain_ops *sgi_ops;
5707
5708 if (has_v4_1)
5709 sgi_ops = &its_sgi_domain_ops;
5710 else
5711 sgi_ops = NULL;
5712
5713 if (its_init_vpe_domain() ||
5714 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5715 rdists->has_vlpis = false;
5716 pr_err("ITS: Disabling GICv4 support\n");
5717 }
5718 }
5719
5720 register_syscore_ops(&its_syscore_ops);
5721
5722 return 0;
5723}