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1/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/bitmap.h>
19#include <linux/cpu.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/log2.h>
23#include <linux/mm.h>
24#include <linux/msi.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_pci.h>
29#include <linux/of_platform.h>
30#include <linux/percpu.h>
31#include <linux/slab.h>
32
33#include <linux/irqchip.h>
34#include <linux/irqchip/arm-gic-v3.h>
35
36#include <asm/cacheflush.h>
37#include <asm/cputype.h>
38#include <asm/exception.h>
39
40#include "irq-gic-common.h"
41
42#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44
45#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46
47/*
48 * Collection structure - just an ID, and a redistributor address to
49 * ping. We use one per CPU as a bag of interrupts assigned to this
50 * CPU.
51 */
52struct its_collection {
53 u64 target_address;
54 u16 col_id;
55};
56
57/*
58 * The ITS structure - contains most of the infrastructure, with the
59 * top-level MSI domain, the command queue, the collections, and the
60 * list of devices writing to it.
61 */
62struct its_node {
63 raw_spinlock_t lock;
64 struct list_head entry;
65 void __iomem *base;
66 unsigned long phys_base;
67 struct its_cmd_block *cmd_base;
68 struct its_cmd_block *cmd_write;
69 struct {
70 void *base;
71 u32 order;
72 } tables[GITS_BASER_NR_REGS];
73 struct its_collection *collections;
74 struct list_head its_device_list;
75 u64 flags;
76 u32 ite_size;
77};
78
79#define ITS_ITT_ALIGN SZ_256
80
81/* Convert page order to size in bytes */
82#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
83
84struct event_lpi_map {
85 unsigned long *lpi_map;
86 u16 *col_map;
87 irq_hw_number_t lpi_base;
88 int nr_lpis;
89};
90
91/*
92 * The ITS view of a device - belongs to an ITS, a collection, owns an
93 * interrupt translation table, and a list of interrupts.
94 */
95struct its_device {
96 struct list_head entry;
97 struct its_node *its;
98 struct event_lpi_map event_map;
99 void *itt;
100 u32 nr_ites;
101 u32 device_id;
102};
103
104static LIST_HEAD(its_nodes);
105static DEFINE_SPINLOCK(its_lock);
106static struct rdists *gic_rdists;
107
108#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
109#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
110
111static struct its_collection *dev_event_to_col(struct its_device *its_dev,
112 u32 event)
113{
114 struct its_node *its = its_dev->its;
115
116 return its->collections + its_dev->event_map.col_map[event];
117}
118
119/*
120 * ITS command descriptors - parameters to be encoded in a command
121 * block.
122 */
123struct its_cmd_desc {
124 union {
125 struct {
126 struct its_device *dev;
127 u32 event_id;
128 } its_inv_cmd;
129
130 struct {
131 struct its_device *dev;
132 u32 event_id;
133 } its_int_cmd;
134
135 struct {
136 struct its_device *dev;
137 int valid;
138 } its_mapd_cmd;
139
140 struct {
141 struct its_collection *col;
142 int valid;
143 } its_mapc_cmd;
144
145 struct {
146 struct its_device *dev;
147 u32 phys_id;
148 u32 event_id;
149 } its_mapvi_cmd;
150
151 struct {
152 struct its_device *dev;
153 struct its_collection *col;
154 u32 event_id;
155 } its_movi_cmd;
156
157 struct {
158 struct its_device *dev;
159 u32 event_id;
160 } its_discard_cmd;
161
162 struct {
163 struct its_collection *col;
164 } its_invall_cmd;
165 };
166};
167
168/*
169 * The ITS command block, which is what the ITS actually parses.
170 */
171struct its_cmd_block {
172 u64 raw_cmd[4];
173};
174
175#define ITS_CMD_QUEUE_SZ SZ_64K
176#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
177
178typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
179 struct its_cmd_desc *);
180
181static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
182{
183 cmd->raw_cmd[0] &= ~0xffUL;
184 cmd->raw_cmd[0] |= cmd_nr;
185}
186
187static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
188{
189 cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
190 cmd->raw_cmd[0] |= ((u64)devid) << 32;
191}
192
193static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
194{
195 cmd->raw_cmd[1] &= ~0xffffffffUL;
196 cmd->raw_cmd[1] |= id;
197}
198
199static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
200{
201 cmd->raw_cmd[1] &= 0xffffffffUL;
202 cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
203}
204
205static void its_encode_size(struct its_cmd_block *cmd, u8 size)
206{
207 cmd->raw_cmd[1] &= ~0x1fUL;
208 cmd->raw_cmd[1] |= size & 0x1f;
209}
210
211static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
212{
213 cmd->raw_cmd[2] &= ~0xffffffffffffUL;
214 cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
215}
216
217static void its_encode_valid(struct its_cmd_block *cmd, int valid)
218{
219 cmd->raw_cmd[2] &= ~(1UL << 63);
220 cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
221}
222
223static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
224{
225 cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
226 cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
227}
228
229static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
230{
231 cmd->raw_cmd[2] &= ~0xffffUL;
232 cmd->raw_cmd[2] |= col;
233}
234
235static inline void its_fixup_cmd(struct its_cmd_block *cmd)
236{
237 /* Let's fixup BE commands */
238 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
239 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
240 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
241 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
242}
243
244static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
245 struct its_cmd_desc *desc)
246{
247 unsigned long itt_addr;
248 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
249
250 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
251 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
252
253 its_encode_cmd(cmd, GITS_CMD_MAPD);
254 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
255 its_encode_size(cmd, size - 1);
256 its_encode_itt(cmd, itt_addr);
257 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
258
259 its_fixup_cmd(cmd);
260
261 return NULL;
262}
263
264static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
265 struct its_cmd_desc *desc)
266{
267 its_encode_cmd(cmd, GITS_CMD_MAPC);
268 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
269 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
270 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
271
272 its_fixup_cmd(cmd);
273
274 return desc->its_mapc_cmd.col;
275}
276
277static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
278 struct its_cmd_desc *desc)
279{
280 struct its_collection *col;
281
282 col = dev_event_to_col(desc->its_mapvi_cmd.dev,
283 desc->its_mapvi_cmd.event_id);
284
285 its_encode_cmd(cmd, GITS_CMD_MAPVI);
286 its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
287 its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
288 its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
289 its_encode_collection(cmd, col->col_id);
290
291 its_fixup_cmd(cmd);
292
293 return col;
294}
295
296static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
297 struct its_cmd_desc *desc)
298{
299 struct its_collection *col;
300
301 col = dev_event_to_col(desc->its_movi_cmd.dev,
302 desc->its_movi_cmd.event_id);
303
304 its_encode_cmd(cmd, GITS_CMD_MOVI);
305 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
306 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
307 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
308
309 its_fixup_cmd(cmd);
310
311 return col;
312}
313
314static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
315 struct its_cmd_desc *desc)
316{
317 struct its_collection *col;
318
319 col = dev_event_to_col(desc->its_discard_cmd.dev,
320 desc->its_discard_cmd.event_id);
321
322 its_encode_cmd(cmd, GITS_CMD_DISCARD);
323 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
324 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
325
326 its_fixup_cmd(cmd);
327
328 return col;
329}
330
331static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
332 struct its_cmd_desc *desc)
333{
334 struct its_collection *col;
335
336 col = dev_event_to_col(desc->its_inv_cmd.dev,
337 desc->its_inv_cmd.event_id);
338
339 its_encode_cmd(cmd, GITS_CMD_INV);
340 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
341 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
342
343 its_fixup_cmd(cmd);
344
345 return col;
346}
347
348static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
349 struct its_cmd_desc *desc)
350{
351 its_encode_cmd(cmd, GITS_CMD_INVALL);
352 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
353
354 its_fixup_cmd(cmd);
355
356 return NULL;
357}
358
359static u64 its_cmd_ptr_to_offset(struct its_node *its,
360 struct its_cmd_block *ptr)
361{
362 return (ptr - its->cmd_base) * sizeof(*ptr);
363}
364
365static int its_queue_full(struct its_node *its)
366{
367 int widx;
368 int ridx;
369
370 widx = its->cmd_write - its->cmd_base;
371 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
372
373 /* This is incredibly unlikely to happen, unless the ITS locks up. */
374 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
375 return 1;
376
377 return 0;
378}
379
380static struct its_cmd_block *its_allocate_entry(struct its_node *its)
381{
382 struct its_cmd_block *cmd;
383 u32 count = 1000000; /* 1s! */
384
385 while (its_queue_full(its)) {
386 count--;
387 if (!count) {
388 pr_err_ratelimited("ITS queue not draining\n");
389 return NULL;
390 }
391 cpu_relax();
392 udelay(1);
393 }
394
395 cmd = its->cmd_write++;
396
397 /* Handle queue wrapping */
398 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
399 its->cmd_write = its->cmd_base;
400
401 return cmd;
402}
403
404static struct its_cmd_block *its_post_commands(struct its_node *its)
405{
406 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
407
408 writel_relaxed(wr, its->base + GITS_CWRITER);
409
410 return its->cmd_write;
411}
412
413static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
414{
415 /*
416 * Make sure the commands written to memory are observable by
417 * the ITS.
418 */
419 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
420 __flush_dcache_area(cmd, sizeof(*cmd));
421 else
422 dsb(ishst);
423}
424
425static void its_wait_for_range_completion(struct its_node *its,
426 struct its_cmd_block *from,
427 struct its_cmd_block *to)
428{
429 u64 rd_idx, from_idx, to_idx;
430 u32 count = 1000000; /* 1s! */
431
432 from_idx = its_cmd_ptr_to_offset(its, from);
433 to_idx = its_cmd_ptr_to_offset(its, to);
434
435 while (1) {
436 rd_idx = readl_relaxed(its->base + GITS_CREADR);
437 if (rd_idx >= to_idx || rd_idx < from_idx)
438 break;
439
440 count--;
441 if (!count) {
442 pr_err_ratelimited("ITS queue timeout\n");
443 return;
444 }
445 cpu_relax();
446 udelay(1);
447 }
448}
449
450static void its_send_single_command(struct its_node *its,
451 its_cmd_builder_t builder,
452 struct its_cmd_desc *desc)
453{
454 struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
455 struct its_collection *sync_col;
456 unsigned long flags;
457
458 raw_spin_lock_irqsave(&its->lock, flags);
459
460 cmd = its_allocate_entry(its);
461 if (!cmd) { /* We're soooooo screewed... */
462 pr_err_ratelimited("ITS can't allocate, dropping command\n");
463 raw_spin_unlock_irqrestore(&its->lock, flags);
464 return;
465 }
466 sync_col = builder(cmd, desc);
467 its_flush_cmd(its, cmd);
468
469 if (sync_col) {
470 sync_cmd = its_allocate_entry(its);
471 if (!sync_cmd) {
472 pr_err_ratelimited("ITS can't SYNC, skipping\n");
473 goto post;
474 }
475 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
476 its_encode_target(sync_cmd, sync_col->target_address);
477 its_fixup_cmd(sync_cmd);
478 its_flush_cmd(its, sync_cmd);
479 }
480
481post:
482 next_cmd = its_post_commands(its);
483 raw_spin_unlock_irqrestore(&its->lock, flags);
484
485 its_wait_for_range_completion(its, cmd, next_cmd);
486}
487
488static void its_send_inv(struct its_device *dev, u32 event_id)
489{
490 struct its_cmd_desc desc;
491
492 desc.its_inv_cmd.dev = dev;
493 desc.its_inv_cmd.event_id = event_id;
494
495 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
496}
497
498static void its_send_mapd(struct its_device *dev, int valid)
499{
500 struct its_cmd_desc desc;
501
502 desc.its_mapd_cmd.dev = dev;
503 desc.its_mapd_cmd.valid = !!valid;
504
505 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
506}
507
508static void its_send_mapc(struct its_node *its, struct its_collection *col,
509 int valid)
510{
511 struct its_cmd_desc desc;
512
513 desc.its_mapc_cmd.col = col;
514 desc.its_mapc_cmd.valid = !!valid;
515
516 its_send_single_command(its, its_build_mapc_cmd, &desc);
517}
518
519static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
520{
521 struct its_cmd_desc desc;
522
523 desc.its_mapvi_cmd.dev = dev;
524 desc.its_mapvi_cmd.phys_id = irq_id;
525 desc.its_mapvi_cmd.event_id = id;
526
527 its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
528}
529
530static void its_send_movi(struct its_device *dev,
531 struct its_collection *col, u32 id)
532{
533 struct its_cmd_desc desc;
534
535 desc.its_movi_cmd.dev = dev;
536 desc.its_movi_cmd.col = col;
537 desc.its_movi_cmd.event_id = id;
538
539 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
540}
541
542static void its_send_discard(struct its_device *dev, u32 id)
543{
544 struct its_cmd_desc desc;
545
546 desc.its_discard_cmd.dev = dev;
547 desc.its_discard_cmd.event_id = id;
548
549 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
550}
551
552static void its_send_invall(struct its_node *its, struct its_collection *col)
553{
554 struct its_cmd_desc desc;
555
556 desc.its_invall_cmd.col = col;
557
558 its_send_single_command(its, its_build_invall_cmd, &desc);
559}
560
561/*
562 * irqchip functions - assumes MSI, mostly.
563 */
564
565static inline u32 its_get_event_id(struct irq_data *d)
566{
567 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
568 return d->hwirq - its_dev->event_map.lpi_base;
569}
570
571static void lpi_set_config(struct irq_data *d, bool enable)
572{
573 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
574 irq_hw_number_t hwirq = d->hwirq;
575 u32 id = its_get_event_id(d);
576 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
577
578 if (enable)
579 *cfg |= LPI_PROP_ENABLED;
580 else
581 *cfg &= ~LPI_PROP_ENABLED;
582
583 /*
584 * Make the above write visible to the redistributors.
585 * And yes, we're flushing exactly: One. Single. Byte.
586 * Humpf...
587 */
588 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
589 __flush_dcache_area(cfg, sizeof(*cfg));
590 else
591 dsb(ishst);
592 its_send_inv(its_dev, id);
593}
594
595static void its_mask_irq(struct irq_data *d)
596{
597 lpi_set_config(d, false);
598}
599
600static void its_unmask_irq(struct irq_data *d)
601{
602 lpi_set_config(d, true);
603}
604
605static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
606 bool force)
607{
608 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
609 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
610 struct its_collection *target_col;
611 u32 id = its_get_event_id(d);
612
613 if (cpu >= nr_cpu_ids)
614 return -EINVAL;
615
616 target_col = &its_dev->its->collections[cpu];
617 its_send_movi(its_dev, target_col, id);
618 its_dev->event_map.col_map[id] = cpu;
619
620 return IRQ_SET_MASK_OK_DONE;
621}
622
623static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
624{
625 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
626 struct its_node *its;
627 u64 addr;
628
629 its = its_dev->its;
630 addr = its->phys_base + GITS_TRANSLATER;
631
632 msg->address_lo = addr & ((1UL << 32) - 1);
633 msg->address_hi = addr >> 32;
634 msg->data = its_get_event_id(d);
635}
636
637static struct irq_chip its_irq_chip = {
638 .name = "ITS",
639 .irq_mask = its_mask_irq,
640 .irq_unmask = its_unmask_irq,
641 .irq_eoi = irq_chip_eoi_parent,
642 .irq_set_affinity = its_set_affinity,
643 .irq_compose_msi_msg = its_irq_compose_msi_msg,
644};
645
646/*
647 * How we allocate LPIs:
648 *
649 * The GIC has id_bits bits for interrupt identifiers. From there, we
650 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
651 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
652 * bits to the right.
653 *
654 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
655 */
656#define IRQS_PER_CHUNK_SHIFT 5
657#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
658
659static unsigned long *lpi_bitmap;
660static u32 lpi_chunks;
661static DEFINE_SPINLOCK(lpi_lock);
662
663static int its_lpi_to_chunk(int lpi)
664{
665 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
666}
667
668static int its_chunk_to_lpi(int chunk)
669{
670 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
671}
672
673static int __init its_lpi_init(u32 id_bits)
674{
675 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
676
677 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
678 GFP_KERNEL);
679 if (!lpi_bitmap) {
680 lpi_chunks = 0;
681 return -ENOMEM;
682 }
683
684 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
685 return 0;
686}
687
688static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
689{
690 unsigned long *bitmap = NULL;
691 int chunk_id;
692 int nr_chunks;
693 int i;
694
695 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
696
697 spin_lock(&lpi_lock);
698
699 do {
700 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
701 0, nr_chunks, 0);
702 if (chunk_id < lpi_chunks)
703 break;
704
705 nr_chunks--;
706 } while (nr_chunks > 0);
707
708 if (!nr_chunks)
709 goto out;
710
711 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
712 GFP_ATOMIC);
713 if (!bitmap)
714 goto out;
715
716 for (i = 0; i < nr_chunks; i++)
717 set_bit(chunk_id + i, lpi_bitmap);
718
719 *base = its_chunk_to_lpi(chunk_id);
720 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
721
722out:
723 spin_unlock(&lpi_lock);
724
725 if (!bitmap)
726 *base = *nr_ids = 0;
727
728 return bitmap;
729}
730
731static void its_lpi_free(struct event_lpi_map *map)
732{
733 int base = map->lpi_base;
734 int nr_ids = map->nr_lpis;
735 int lpi;
736
737 spin_lock(&lpi_lock);
738
739 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
740 int chunk = its_lpi_to_chunk(lpi);
741 BUG_ON(chunk > lpi_chunks);
742 if (test_bit(chunk, lpi_bitmap)) {
743 clear_bit(chunk, lpi_bitmap);
744 } else {
745 pr_err("Bad LPI chunk %d\n", chunk);
746 }
747 }
748
749 spin_unlock(&lpi_lock);
750
751 kfree(map->lpi_map);
752 kfree(map->col_map);
753}
754
755/*
756 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
757 * deal with (one configuration byte per interrupt). PENDBASE has to
758 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
759 */
760#define LPI_PROPBASE_SZ SZ_64K
761#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
762
763/*
764 * This is how many bits of ID we need, including the useless ones.
765 */
766#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
767
768#define LPI_PROP_DEFAULT_PRIO 0xa0
769
770static int __init its_alloc_lpi_tables(void)
771{
772 phys_addr_t paddr;
773
774 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
775 get_order(LPI_PROPBASE_SZ));
776 if (!gic_rdists->prop_page) {
777 pr_err("Failed to allocate PROPBASE\n");
778 return -ENOMEM;
779 }
780
781 paddr = page_to_phys(gic_rdists->prop_page);
782 pr_info("GIC: using LPI property table @%pa\n", &paddr);
783
784 /* Priority 0xa0, Group-1, disabled */
785 memset(page_address(gic_rdists->prop_page),
786 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
787 LPI_PROPBASE_SZ);
788
789 /* Make sure the GIC will observe the written configuration */
790 __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
791
792 return 0;
793}
794
795static const char *its_base_type_string[] = {
796 [GITS_BASER_TYPE_DEVICE] = "Devices",
797 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
798 [GITS_BASER_TYPE_CPU] = "Physical CPUs",
799 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
800 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
801 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
802 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
803};
804
805static void its_free_tables(struct its_node *its)
806{
807 int i;
808
809 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
810 if (its->tables[i].base) {
811 free_pages((unsigned long)its->tables[i].base,
812 its->tables[i].order);
813 its->tables[i].base = NULL;
814 }
815 }
816}
817
818static int its_alloc_tables(const char *node_name, struct its_node *its)
819{
820 int err;
821 int i;
822 int psz = SZ_64K;
823 u64 shr = GITS_BASER_InnerShareable;
824 u64 cache;
825 u64 typer;
826 u32 ids;
827
828 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
829 /*
830 * erratum 22375: only alloc 8MB table size
831 * erratum 24313: ignore memory access type
832 */
833 cache = 0;
834 ids = 0x14; /* 20 bits, 8MB */
835 } else {
836 cache = GITS_BASER_WaWb;
837 typer = readq_relaxed(its->base + GITS_TYPER);
838 ids = GITS_TYPER_DEVBITS(typer);
839 }
840
841 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
842 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
843 u64 type = GITS_BASER_TYPE(val);
844 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
845 int order = get_order(psz);
846 int alloc_pages;
847 u64 tmp;
848 void *base;
849
850 if (type == GITS_BASER_TYPE_NONE)
851 continue;
852
853 /*
854 * Allocate as many entries as required to fit the
855 * range of device IDs that the ITS can grok... The ID
856 * space being incredibly sparse, this results in a
857 * massive waste of memory.
858 *
859 * For other tables, only allocate a single page.
860 */
861 if (type == GITS_BASER_TYPE_DEVICE) {
862 /*
863 * 'order' was initialized earlier to the default page
864 * granule of the the ITS. We can't have an allocation
865 * smaller than that. If the requested allocation
866 * is smaller, round up to the default page granule.
867 */
868 order = max(get_order((1UL << ids) * entry_size),
869 order);
870 if (order >= MAX_ORDER) {
871 order = MAX_ORDER - 1;
872 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
873 node_name, order);
874 }
875 }
876
877retry_alloc_baser:
878 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
879 if (alloc_pages > GITS_BASER_PAGES_MAX) {
880 alloc_pages = GITS_BASER_PAGES_MAX;
881 order = get_order(GITS_BASER_PAGES_MAX * psz);
882 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
883 node_name, order, alloc_pages);
884 }
885
886 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
887 if (!base) {
888 err = -ENOMEM;
889 goto out_free;
890 }
891
892 its->tables[i].base = base;
893 its->tables[i].order = order;
894
895retry_baser:
896 val = (virt_to_phys(base) |
897 (type << GITS_BASER_TYPE_SHIFT) |
898 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
899 cache |
900 shr |
901 GITS_BASER_VALID);
902
903 switch (psz) {
904 case SZ_4K:
905 val |= GITS_BASER_PAGE_SIZE_4K;
906 break;
907 case SZ_16K:
908 val |= GITS_BASER_PAGE_SIZE_16K;
909 break;
910 case SZ_64K:
911 val |= GITS_BASER_PAGE_SIZE_64K;
912 break;
913 }
914
915 val |= alloc_pages - 1;
916
917 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
918 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
919
920 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
921 /*
922 * Shareability didn't stick. Just use
923 * whatever the read reported, which is likely
924 * to be the only thing this redistributor
925 * supports. If that's zero, make it
926 * non-cacheable as well.
927 */
928 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
929 if (!shr) {
930 cache = GITS_BASER_nC;
931 __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
932 }
933 goto retry_baser;
934 }
935
936 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
937 /*
938 * Page size didn't stick. Let's try a smaller
939 * size and retry. If we reach 4K, then
940 * something is horribly wrong...
941 */
942 free_pages((unsigned long)base, order);
943 its->tables[i].base = NULL;
944
945 switch (psz) {
946 case SZ_16K:
947 psz = SZ_4K;
948 goto retry_alloc_baser;
949 case SZ_64K:
950 psz = SZ_16K;
951 goto retry_alloc_baser;
952 }
953 }
954
955 if (val != tmp) {
956 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
957 node_name, i,
958 (unsigned long) val, (unsigned long) tmp);
959 err = -ENXIO;
960 goto out_free;
961 }
962
963 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
964 (int)(PAGE_ORDER_TO_SIZE(order) / entry_size),
965 its_base_type_string[type],
966 (unsigned long)virt_to_phys(base),
967 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
968 }
969
970 return 0;
971
972out_free:
973 its_free_tables(its);
974
975 return err;
976}
977
978static int its_alloc_collections(struct its_node *its)
979{
980 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
981 GFP_KERNEL);
982 if (!its->collections)
983 return -ENOMEM;
984
985 return 0;
986}
987
988static void its_cpu_init_lpis(void)
989{
990 void __iomem *rbase = gic_data_rdist_rd_base();
991 struct page *pend_page;
992 u64 val, tmp;
993
994 /* If we didn't allocate the pending table yet, do it now */
995 pend_page = gic_data_rdist()->pend_page;
996 if (!pend_page) {
997 phys_addr_t paddr;
998 /*
999 * The pending pages have to be at least 64kB aligned,
1000 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1001 */
1002 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
1003 get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
1004 if (!pend_page) {
1005 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1006 smp_processor_id());
1007 return;
1008 }
1009
1010 /* Make sure the GIC will observe the zero-ed page */
1011 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1012
1013 paddr = page_to_phys(pend_page);
1014 pr_info("CPU%d: using LPI pending table @%pa\n",
1015 smp_processor_id(), &paddr);
1016 gic_data_rdist()->pend_page = pend_page;
1017 }
1018
1019 /* Disable LPIs */
1020 val = readl_relaxed(rbase + GICR_CTLR);
1021 val &= ~GICR_CTLR_ENABLE_LPIS;
1022 writel_relaxed(val, rbase + GICR_CTLR);
1023
1024 /*
1025 * Make sure any change to the table is observable by the GIC.
1026 */
1027 dsb(sy);
1028
1029 /* set PROPBASE */
1030 val = (page_to_phys(gic_rdists->prop_page) |
1031 GICR_PROPBASER_InnerShareable |
1032 GICR_PROPBASER_WaWb |
1033 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1034
1035 writeq_relaxed(val, rbase + GICR_PROPBASER);
1036 tmp = readq_relaxed(rbase + GICR_PROPBASER);
1037
1038 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1039 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1040 /*
1041 * The HW reports non-shareable, we must
1042 * remove the cacheability attributes as
1043 * well.
1044 */
1045 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1046 GICR_PROPBASER_CACHEABILITY_MASK);
1047 val |= GICR_PROPBASER_nC;
1048 writeq_relaxed(val, rbase + GICR_PROPBASER);
1049 }
1050 pr_info_once("GIC: using cache flushing for LPI property table\n");
1051 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1052 }
1053
1054 /* set PENDBASE */
1055 val = (page_to_phys(pend_page) |
1056 GICR_PENDBASER_InnerShareable |
1057 GICR_PENDBASER_WaWb);
1058
1059 writeq_relaxed(val, rbase + GICR_PENDBASER);
1060 tmp = readq_relaxed(rbase + GICR_PENDBASER);
1061
1062 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1063 /*
1064 * The HW reports non-shareable, we must remove the
1065 * cacheability attributes as well.
1066 */
1067 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1068 GICR_PENDBASER_CACHEABILITY_MASK);
1069 val |= GICR_PENDBASER_nC;
1070 writeq_relaxed(val, rbase + GICR_PENDBASER);
1071 }
1072
1073 /* Enable LPIs */
1074 val = readl_relaxed(rbase + GICR_CTLR);
1075 val |= GICR_CTLR_ENABLE_LPIS;
1076 writel_relaxed(val, rbase + GICR_CTLR);
1077
1078 /* Make sure the GIC has seen the above */
1079 dsb(sy);
1080}
1081
1082static void its_cpu_init_collection(void)
1083{
1084 struct its_node *its;
1085 int cpu;
1086
1087 spin_lock(&its_lock);
1088 cpu = smp_processor_id();
1089
1090 list_for_each_entry(its, &its_nodes, entry) {
1091 u64 target;
1092
1093 /*
1094 * We now have to bind each collection to its target
1095 * redistributor.
1096 */
1097 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1098 /*
1099 * This ITS wants the physical address of the
1100 * redistributor.
1101 */
1102 target = gic_data_rdist()->phys_base;
1103 } else {
1104 /*
1105 * This ITS wants a linear CPU number.
1106 */
1107 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1108 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1109 }
1110
1111 /* Perform collection mapping */
1112 its->collections[cpu].target_address = target;
1113 its->collections[cpu].col_id = cpu;
1114
1115 its_send_mapc(its, &its->collections[cpu], 1);
1116 its_send_invall(its, &its->collections[cpu]);
1117 }
1118
1119 spin_unlock(&its_lock);
1120}
1121
1122static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1123{
1124 struct its_device *its_dev = NULL, *tmp;
1125 unsigned long flags;
1126
1127 raw_spin_lock_irqsave(&its->lock, flags);
1128
1129 list_for_each_entry(tmp, &its->its_device_list, entry) {
1130 if (tmp->device_id == dev_id) {
1131 its_dev = tmp;
1132 break;
1133 }
1134 }
1135
1136 raw_spin_unlock_irqrestore(&its->lock, flags);
1137
1138 return its_dev;
1139}
1140
1141static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1142 int nvecs)
1143{
1144 struct its_device *dev;
1145 unsigned long *lpi_map;
1146 unsigned long flags;
1147 u16 *col_map = NULL;
1148 void *itt;
1149 int lpi_base;
1150 int nr_lpis;
1151 int nr_ites;
1152 int sz;
1153
1154 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1155 /*
1156 * At least one bit of EventID is being used, hence a minimum
1157 * of two entries. No, the architecture doesn't let you
1158 * express an ITT with a single entry.
1159 */
1160 nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1161 sz = nr_ites * its->ite_size;
1162 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1163 itt = kzalloc(sz, GFP_KERNEL);
1164 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1165 if (lpi_map)
1166 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1167
1168 if (!dev || !itt || !lpi_map || !col_map) {
1169 kfree(dev);
1170 kfree(itt);
1171 kfree(lpi_map);
1172 kfree(col_map);
1173 return NULL;
1174 }
1175
1176 __flush_dcache_area(itt, sz);
1177
1178 dev->its = its;
1179 dev->itt = itt;
1180 dev->nr_ites = nr_ites;
1181 dev->event_map.lpi_map = lpi_map;
1182 dev->event_map.col_map = col_map;
1183 dev->event_map.lpi_base = lpi_base;
1184 dev->event_map.nr_lpis = nr_lpis;
1185 dev->device_id = dev_id;
1186 INIT_LIST_HEAD(&dev->entry);
1187
1188 raw_spin_lock_irqsave(&its->lock, flags);
1189 list_add(&dev->entry, &its->its_device_list);
1190 raw_spin_unlock_irqrestore(&its->lock, flags);
1191
1192 /* Map device to its ITT */
1193 its_send_mapd(dev, 1);
1194
1195 return dev;
1196}
1197
1198static void its_free_device(struct its_device *its_dev)
1199{
1200 unsigned long flags;
1201
1202 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1203 list_del(&its_dev->entry);
1204 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1205 kfree(its_dev->itt);
1206 kfree(its_dev);
1207}
1208
1209static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1210{
1211 int idx;
1212
1213 idx = find_first_zero_bit(dev->event_map.lpi_map,
1214 dev->event_map.nr_lpis);
1215 if (idx == dev->event_map.nr_lpis)
1216 return -ENOSPC;
1217
1218 *hwirq = dev->event_map.lpi_base + idx;
1219 set_bit(idx, dev->event_map.lpi_map);
1220
1221 return 0;
1222}
1223
1224static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1225 int nvec, msi_alloc_info_t *info)
1226{
1227 struct its_node *its;
1228 struct its_device *its_dev;
1229 struct msi_domain_info *msi_info;
1230 u32 dev_id;
1231
1232 /*
1233 * We ignore "dev" entierely, and rely on the dev_id that has
1234 * been passed via the scratchpad. This limits this domain's
1235 * usefulness to upper layers that definitely know that they
1236 * are built on top of the ITS.
1237 */
1238 dev_id = info->scratchpad[0].ul;
1239
1240 msi_info = msi_get_domain_info(domain);
1241 its = msi_info->data;
1242
1243 its_dev = its_find_device(its, dev_id);
1244 if (its_dev) {
1245 /*
1246 * We already have seen this ID, probably through
1247 * another alias (PCI bridge of some sort). No need to
1248 * create the device.
1249 */
1250 pr_debug("Reusing ITT for devID %x\n", dev_id);
1251 goto out;
1252 }
1253
1254 its_dev = its_create_device(its, dev_id, nvec);
1255 if (!its_dev)
1256 return -ENOMEM;
1257
1258 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1259out:
1260 info->scratchpad[0].ptr = its_dev;
1261 return 0;
1262}
1263
1264static struct msi_domain_ops its_msi_domain_ops = {
1265 .msi_prepare = its_msi_prepare,
1266};
1267
1268static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1269 unsigned int virq,
1270 irq_hw_number_t hwirq)
1271{
1272 struct irq_fwspec fwspec;
1273
1274 if (irq_domain_get_of_node(domain->parent)) {
1275 fwspec.fwnode = domain->parent->fwnode;
1276 fwspec.param_count = 3;
1277 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1278 fwspec.param[1] = hwirq;
1279 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1280 } else {
1281 return -EINVAL;
1282 }
1283
1284 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1285}
1286
1287static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1288 unsigned int nr_irqs, void *args)
1289{
1290 msi_alloc_info_t *info = args;
1291 struct its_device *its_dev = info->scratchpad[0].ptr;
1292 irq_hw_number_t hwirq;
1293 int err;
1294 int i;
1295
1296 for (i = 0; i < nr_irqs; i++) {
1297 err = its_alloc_device_irq(its_dev, &hwirq);
1298 if (err)
1299 return err;
1300
1301 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1302 if (err)
1303 return err;
1304
1305 irq_domain_set_hwirq_and_chip(domain, virq + i,
1306 hwirq, &its_irq_chip, its_dev);
1307 pr_debug("ID:%d pID:%d vID:%d\n",
1308 (int)(hwirq - its_dev->event_map.lpi_base),
1309 (int) hwirq, virq + i);
1310 }
1311
1312 return 0;
1313}
1314
1315static void its_irq_domain_activate(struct irq_domain *domain,
1316 struct irq_data *d)
1317{
1318 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1319 u32 event = its_get_event_id(d);
1320
1321 /* Bind the LPI to the first possible CPU */
1322 its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1323
1324 /* Map the GIC IRQ and event to the device */
1325 its_send_mapvi(its_dev, d->hwirq, event);
1326}
1327
1328static void its_irq_domain_deactivate(struct irq_domain *domain,
1329 struct irq_data *d)
1330{
1331 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1332 u32 event = its_get_event_id(d);
1333
1334 /* Stop the delivery of interrupts */
1335 its_send_discard(its_dev, event);
1336}
1337
1338static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1339 unsigned int nr_irqs)
1340{
1341 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1342 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1343 int i;
1344
1345 for (i = 0; i < nr_irqs; i++) {
1346 struct irq_data *data = irq_domain_get_irq_data(domain,
1347 virq + i);
1348 u32 event = its_get_event_id(data);
1349
1350 /* Mark interrupt index as unused */
1351 clear_bit(event, its_dev->event_map.lpi_map);
1352
1353 /* Nuke the entry in the domain */
1354 irq_domain_reset_irq_data(data);
1355 }
1356
1357 /* If all interrupts have been freed, start mopping the floor */
1358 if (bitmap_empty(its_dev->event_map.lpi_map,
1359 its_dev->event_map.nr_lpis)) {
1360 its_lpi_free(&its_dev->event_map);
1361
1362 /* Unmap device/itt */
1363 its_send_mapd(its_dev, 0);
1364 its_free_device(its_dev);
1365 }
1366
1367 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1368}
1369
1370static const struct irq_domain_ops its_domain_ops = {
1371 .alloc = its_irq_domain_alloc,
1372 .free = its_irq_domain_free,
1373 .activate = its_irq_domain_activate,
1374 .deactivate = its_irq_domain_deactivate,
1375};
1376
1377static int its_force_quiescent(void __iomem *base)
1378{
1379 u32 count = 1000000; /* 1s */
1380 u32 val;
1381
1382 val = readl_relaxed(base + GITS_CTLR);
1383 if (val & GITS_CTLR_QUIESCENT)
1384 return 0;
1385
1386 /* Disable the generation of all interrupts to this ITS */
1387 val &= ~GITS_CTLR_ENABLE;
1388 writel_relaxed(val, base + GITS_CTLR);
1389
1390 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1391 while (1) {
1392 val = readl_relaxed(base + GITS_CTLR);
1393 if (val & GITS_CTLR_QUIESCENT)
1394 return 0;
1395
1396 count--;
1397 if (!count)
1398 return -EBUSY;
1399
1400 cpu_relax();
1401 udelay(1);
1402 }
1403}
1404
1405static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1406{
1407 struct its_node *its = data;
1408
1409 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1410}
1411
1412static const struct gic_quirk its_quirks[] = {
1413#ifdef CONFIG_CAVIUM_ERRATUM_22375
1414 {
1415 .desc = "ITS: Cavium errata 22375, 24313",
1416 .iidr = 0xa100034c, /* ThunderX pass 1.x */
1417 .mask = 0xffff0fff,
1418 .init = its_enable_quirk_cavium_22375,
1419 },
1420#endif
1421 {
1422 }
1423};
1424
1425static void its_enable_quirks(struct its_node *its)
1426{
1427 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1428
1429 gic_enable_quirks(iidr, its_quirks, its);
1430}
1431
1432static int __init its_probe(struct device_node *node,
1433 struct irq_domain *parent)
1434{
1435 struct resource res;
1436 struct its_node *its;
1437 void __iomem *its_base;
1438 struct irq_domain *inner_domain;
1439 u32 val;
1440 u64 baser, tmp;
1441 int err;
1442
1443 err = of_address_to_resource(node, 0, &res);
1444 if (err) {
1445 pr_warn("%s: no regs?\n", node->full_name);
1446 return -ENXIO;
1447 }
1448
1449 its_base = ioremap(res.start, resource_size(&res));
1450 if (!its_base) {
1451 pr_warn("%s: unable to map registers\n", node->full_name);
1452 return -ENOMEM;
1453 }
1454
1455 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1456 if (val != 0x30 && val != 0x40) {
1457 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1458 err = -ENODEV;
1459 goto out_unmap;
1460 }
1461
1462 err = its_force_quiescent(its_base);
1463 if (err) {
1464 pr_warn("%s: failed to quiesce, giving up\n",
1465 node->full_name);
1466 goto out_unmap;
1467 }
1468
1469 pr_info("ITS: %s\n", node->full_name);
1470
1471 its = kzalloc(sizeof(*its), GFP_KERNEL);
1472 if (!its) {
1473 err = -ENOMEM;
1474 goto out_unmap;
1475 }
1476
1477 raw_spin_lock_init(&its->lock);
1478 INIT_LIST_HEAD(&its->entry);
1479 INIT_LIST_HEAD(&its->its_device_list);
1480 its->base = its_base;
1481 its->phys_base = res.start;
1482 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1483
1484 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1485 if (!its->cmd_base) {
1486 err = -ENOMEM;
1487 goto out_free_its;
1488 }
1489 its->cmd_write = its->cmd_base;
1490
1491 its_enable_quirks(its);
1492
1493 err = its_alloc_tables(node->full_name, its);
1494 if (err)
1495 goto out_free_cmd;
1496
1497 err = its_alloc_collections(its);
1498 if (err)
1499 goto out_free_tables;
1500
1501 baser = (virt_to_phys(its->cmd_base) |
1502 GITS_CBASER_WaWb |
1503 GITS_CBASER_InnerShareable |
1504 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1505 GITS_CBASER_VALID);
1506
1507 writeq_relaxed(baser, its->base + GITS_CBASER);
1508 tmp = readq_relaxed(its->base + GITS_CBASER);
1509
1510 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1511 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1512 /*
1513 * The HW reports non-shareable, we must
1514 * remove the cacheability attributes as
1515 * well.
1516 */
1517 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1518 GITS_CBASER_CACHEABILITY_MASK);
1519 baser |= GITS_CBASER_nC;
1520 writeq_relaxed(baser, its->base + GITS_CBASER);
1521 }
1522 pr_info("ITS: using cache flushing for cmd queue\n");
1523 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1524 }
1525
1526 writeq_relaxed(0, its->base + GITS_CWRITER);
1527 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1528
1529 if (of_property_read_bool(node, "msi-controller")) {
1530 struct msi_domain_info *info;
1531
1532 info = kzalloc(sizeof(*info), GFP_KERNEL);
1533 if (!info) {
1534 err = -ENOMEM;
1535 goto out_free_tables;
1536 }
1537
1538 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1539 if (!inner_domain) {
1540 err = -ENOMEM;
1541 kfree(info);
1542 goto out_free_tables;
1543 }
1544
1545 inner_domain->parent = parent;
1546 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1547 info->ops = &its_msi_domain_ops;
1548 info->data = its;
1549 inner_domain->host_data = info;
1550 }
1551
1552 spin_lock(&its_lock);
1553 list_add(&its->entry, &its_nodes);
1554 spin_unlock(&its_lock);
1555
1556 return 0;
1557
1558out_free_tables:
1559 its_free_tables(its);
1560out_free_cmd:
1561 kfree(its->cmd_base);
1562out_free_its:
1563 kfree(its);
1564out_unmap:
1565 iounmap(its_base);
1566 pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1567 return err;
1568}
1569
1570static bool gic_rdists_supports_plpis(void)
1571{
1572 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1573}
1574
1575int its_cpu_init(void)
1576{
1577 if (!list_empty(&its_nodes)) {
1578 if (!gic_rdists_supports_plpis()) {
1579 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1580 return -ENXIO;
1581 }
1582 its_cpu_init_lpis();
1583 its_cpu_init_collection();
1584 }
1585
1586 return 0;
1587}
1588
1589static struct of_device_id its_device_id[] = {
1590 { .compatible = "arm,gic-v3-its", },
1591 {},
1592};
1593
1594int __init its_init(struct device_node *node, struct rdists *rdists,
1595 struct irq_domain *parent_domain)
1596{
1597 struct device_node *np;
1598
1599 for (np = of_find_matching_node(node, its_device_id); np;
1600 np = of_find_matching_node(np, its_device_id)) {
1601 its_probe(np, parent_domain);
1602 }
1603
1604 if (list_empty(&its_nodes)) {
1605 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1606 return -ENXIO;
1607 }
1608
1609 gic_rdists = rdists;
1610 its_alloc_lpi_tables();
1611 its_lpi_init(rdists->id_bits);
1612
1613 return 0;
1614}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <linux/acpi.h>
8#include <linux/acpi_iort.h>
9#include <linux/bitfield.h>
10#include <linux/bitmap.h>
11#include <linux/cpu.h>
12#include <linux/crash_dump.h>
13#include <linux/delay.h>
14#include <linux/efi.h>
15#include <linux/genalloc.h>
16#include <linux/interrupt.h>
17#include <linux/iommu.h>
18#include <linux/iopoll.h>
19#include <linux/irqdomain.h>
20#include <linux/list.h>
21#include <linux/log2.h>
22#include <linux/mem_encrypt.h>
23#include <linux/memblock.h>
24#include <linux/mm.h>
25#include <linux/msi.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/of_pci.h>
30#include <linux/of_platform.h>
31#include <linux/percpu.h>
32#include <linux/set_memory.h>
33#include <linux/slab.h>
34#include <linux/syscore_ops.h>
35
36#include <linux/irqchip.h>
37#include <linux/irqchip/arm-gic-v3.h>
38#include <linux/irqchip/arm-gic-v4.h>
39
40#include <asm/cputype.h>
41#include <asm/exception.h>
42
43#include "irq-gic-common.h"
44#include "irq-msi-lib.h"
45
46#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
47#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
48#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
49#define ITS_FLAGS_FORCE_NON_SHAREABLE (1ULL << 3)
50#define ITS_FLAGS_WORKAROUND_HISILICON_162100801 (1ULL << 4)
51
52#define RD_LOCAL_LPI_ENABLED BIT(0)
53#define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1)
54#define RD_LOCAL_MEMRESERVE_DONE BIT(2)
55
56static u32 lpi_id_bits;
57
58/*
59 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
60 * deal with (one configuration byte per interrupt). PENDBASE has to
61 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
62 */
63#define LPI_NRBITS lpi_id_bits
64#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
65#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
66
67static u8 __ro_after_init lpi_prop_prio;
68static struct its_node *find_4_1_its(void);
69
70/*
71 * Collection structure - just an ID, and a redistributor address to
72 * ping. We use one per CPU as a bag of interrupts assigned to this
73 * CPU.
74 */
75struct its_collection {
76 u64 target_address;
77 u16 col_id;
78};
79
80/*
81 * The ITS_BASER structure - contains memory information, cached
82 * value of BASER register configuration and ITS page size.
83 */
84struct its_baser {
85 void *base;
86 u64 val;
87 u32 order;
88 u32 psz;
89};
90
91struct its_device;
92
93/*
94 * The ITS structure - contains most of the infrastructure, with the
95 * top-level MSI domain, the command queue, the collections, and the
96 * list of devices writing to it.
97 *
98 * dev_alloc_lock has to be taken for device allocations, while the
99 * spinlock must be taken to parse data structures such as the device
100 * list.
101 */
102struct its_node {
103 raw_spinlock_t lock;
104 struct mutex dev_alloc_lock;
105 struct list_head entry;
106 void __iomem *base;
107 void __iomem *sgir_base;
108 phys_addr_t phys_base;
109 struct its_cmd_block *cmd_base;
110 struct its_cmd_block *cmd_write;
111 struct its_baser tables[GITS_BASER_NR_REGS];
112 struct its_collection *collections;
113 struct fwnode_handle *fwnode_handle;
114 u64 (*get_msi_base)(struct its_device *its_dev);
115 u64 typer;
116 u64 cbaser_save;
117 u32 ctlr_save;
118 u32 mpidr;
119 struct list_head its_device_list;
120 u64 flags;
121 unsigned long list_nr;
122 int numa_node;
123 unsigned int msi_domain_flags;
124 u32 pre_its_base; /* for Socionext Synquacer */
125 int vlpi_redist_offset;
126};
127
128#define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
129#define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
130#define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
131
132#define ITS_ITT_ALIGN SZ_256
133
134/* The maximum number of VPEID bits supported by VLPI commands */
135#define ITS_MAX_VPEID_BITS \
136 ({ \
137 int nvpeid = 16; \
138 if (gic_rdists->has_rvpeid && \
139 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
140 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
141 GICD_TYPER2_VID); \
142 \
143 nvpeid; \
144 })
145#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
146
147/* Convert page order to size in bytes */
148#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
149
150struct event_lpi_map {
151 unsigned long *lpi_map;
152 u16 *col_map;
153 irq_hw_number_t lpi_base;
154 int nr_lpis;
155 raw_spinlock_t vlpi_lock;
156 struct its_vm *vm;
157 struct its_vlpi_map *vlpi_maps;
158 int nr_vlpis;
159};
160
161/*
162 * The ITS view of a device - belongs to an ITS, owns an interrupt
163 * translation table, and a list of interrupts. If it some of its
164 * LPIs are injected into a guest (GICv4), the event_map.vm field
165 * indicates which one.
166 */
167struct its_device {
168 struct list_head entry;
169 struct its_node *its;
170 struct event_lpi_map event_map;
171 void *itt;
172 u32 itt_sz;
173 u32 nr_ites;
174 u32 device_id;
175 bool shared;
176};
177
178static struct {
179 raw_spinlock_t lock;
180 struct its_device *dev;
181 struct its_vpe **vpes;
182 int next_victim;
183} vpe_proxy;
184
185struct cpu_lpi_count {
186 atomic_t managed;
187 atomic_t unmanaged;
188};
189
190static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
191
192static LIST_HEAD(its_nodes);
193static DEFINE_RAW_SPINLOCK(its_lock);
194static struct rdists *gic_rdists;
195static struct irq_domain *its_parent;
196
197static unsigned long its_list_map;
198static u16 vmovp_seq_num;
199static DEFINE_RAW_SPINLOCK(vmovp_lock);
200
201static DEFINE_IDA(its_vpeid_ida);
202
203#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
204#define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
205#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
206#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
207
208static struct page *its_alloc_pages_node(int node, gfp_t gfp,
209 unsigned int order)
210{
211 struct page *page;
212 int ret = 0;
213
214 page = alloc_pages_node(node, gfp, order);
215
216 if (!page)
217 return NULL;
218
219 ret = set_memory_decrypted((unsigned long)page_address(page),
220 1 << order);
221 /*
222 * If set_memory_decrypted() fails then we don't know what state the
223 * page is in, so we can't free it. Instead we leak it.
224 * set_memory_decrypted() will already have WARNed.
225 */
226 if (ret)
227 return NULL;
228
229 return page;
230}
231
232static struct page *its_alloc_pages(gfp_t gfp, unsigned int order)
233{
234 return its_alloc_pages_node(NUMA_NO_NODE, gfp, order);
235}
236
237static void its_free_pages(void *addr, unsigned int order)
238{
239 /*
240 * If the memory cannot be encrypted again then we must leak the pages.
241 * set_memory_encrypted() will already have WARNed.
242 */
243 if (set_memory_encrypted((unsigned long)addr, 1 << order))
244 return;
245 free_pages((unsigned long)addr, order);
246}
247
248static struct gen_pool *itt_pool;
249
250static void *itt_alloc_pool(int node, int size)
251{
252 unsigned long addr;
253 struct page *page;
254
255 if (size >= PAGE_SIZE) {
256 page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, get_order(size));
257
258 return page ? page_address(page) : NULL;
259 }
260
261 do {
262 addr = gen_pool_alloc(itt_pool, size);
263 if (addr)
264 break;
265
266 page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0);
267 if (!page)
268 break;
269
270 gen_pool_add(itt_pool, (unsigned long)page_address(page), PAGE_SIZE, node);
271 } while (!addr);
272
273 return (void *)addr;
274}
275
276static void itt_free_pool(void *addr, int size)
277{
278 if (!addr)
279 return;
280
281 if (size >= PAGE_SIZE) {
282 its_free_pages(addr, get_order(size));
283 return;
284 }
285
286 gen_pool_free(itt_pool, (unsigned long)addr, size);
287}
288
289/*
290 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
291 * always have vSGIs mapped.
292 */
293static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
294{
295 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
296}
297
298static bool rdists_support_shareable(void)
299{
300 return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE);
301}
302
303static u16 get_its_list(struct its_vm *vm)
304{
305 struct its_node *its;
306 unsigned long its_list = 0;
307
308 list_for_each_entry(its, &its_nodes, entry) {
309 if (!is_v4(its))
310 continue;
311
312 if (require_its_list_vmovp(vm, its))
313 __set_bit(its->list_nr, &its_list);
314 }
315
316 return (u16)its_list;
317}
318
319static inline u32 its_get_event_id(struct irq_data *d)
320{
321 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
322 return d->hwirq - its_dev->event_map.lpi_base;
323}
324
325static struct its_collection *dev_event_to_col(struct its_device *its_dev,
326 u32 event)
327{
328 struct its_node *its = its_dev->its;
329
330 return its->collections + its_dev->event_map.col_map[event];
331}
332
333static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
334 u32 event)
335{
336 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
337 return NULL;
338
339 return &its_dev->event_map.vlpi_maps[event];
340}
341
342static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
343{
344 if (irqd_is_forwarded_to_vcpu(d)) {
345 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
346 u32 event = its_get_event_id(d);
347
348 return dev_event_to_vlpi_map(its_dev, event);
349 }
350
351 return NULL;
352}
353
354static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
355{
356 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
357 return vpe->col_idx;
358}
359
360static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
361{
362 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
363}
364
365static struct irq_chip its_vpe_irq_chip;
366
367static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
368{
369 struct its_vpe *vpe = NULL;
370 int cpu;
371
372 if (d->chip == &its_vpe_irq_chip) {
373 vpe = irq_data_get_irq_chip_data(d);
374 } else {
375 struct its_vlpi_map *map = get_vlpi_map(d);
376 if (map)
377 vpe = map->vpe;
378 }
379
380 if (vpe) {
381 cpu = vpe_to_cpuid_lock(vpe, flags);
382 } else {
383 /* Physical LPIs are already locked via the irq_desc lock */
384 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
385 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
386 /* Keep GCC quiet... */
387 *flags = 0;
388 }
389
390 return cpu;
391}
392
393static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
394{
395 struct its_vpe *vpe = NULL;
396
397 if (d->chip == &its_vpe_irq_chip) {
398 vpe = irq_data_get_irq_chip_data(d);
399 } else {
400 struct its_vlpi_map *map = get_vlpi_map(d);
401 if (map)
402 vpe = map->vpe;
403 }
404
405 if (vpe)
406 vpe_to_cpuid_unlock(vpe, flags);
407}
408
409static struct its_collection *valid_col(struct its_collection *col)
410{
411 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
412 return NULL;
413
414 return col;
415}
416
417static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
418{
419 if (valid_col(its->collections + vpe->col_idx))
420 return vpe;
421
422 return NULL;
423}
424
425/*
426 * ITS command descriptors - parameters to be encoded in a command
427 * block.
428 */
429struct its_cmd_desc {
430 union {
431 struct {
432 struct its_device *dev;
433 u32 event_id;
434 } its_inv_cmd;
435
436 struct {
437 struct its_device *dev;
438 u32 event_id;
439 } its_clear_cmd;
440
441 struct {
442 struct its_device *dev;
443 u32 event_id;
444 } its_int_cmd;
445
446 struct {
447 struct its_device *dev;
448 int valid;
449 } its_mapd_cmd;
450
451 struct {
452 struct its_collection *col;
453 int valid;
454 } its_mapc_cmd;
455
456 struct {
457 struct its_device *dev;
458 u32 phys_id;
459 u32 event_id;
460 } its_mapti_cmd;
461
462 struct {
463 struct its_device *dev;
464 struct its_collection *col;
465 u32 event_id;
466 } its_movi_cmd;
467
468 struct {
469 struct its_device *dev;
470 u32 event_id;
471 } its_discard_cmd;
472
473 struct {
474 struct its_collection *col;
475 } its_invall_cmd;
476
477 struct {
478 struct its_vpe *vpe;
479 } its_vinvall_cmd;
480
481 struct {
482 struct its_vpe *vpe;
483 struct its_collection *col;
484 bool valid;
485 } its_vmapp_cmd;
486
487 struct {
488 struct its_vpe *vpe;
489 struct its_device *dev;
490 u32 virt_id;
491 u32 event_id;
492 bool db_enabled;
493 } its_vmapti_cmd;
494
495 struct {
496 struct its_vpe *vpe;
497 struct its_device *dev;
498 u32 event_id;
499 bool db_enabled;
500 } its_vmovi_cmd;
501
502 struct {
503 struct its_vpe *vpe;
504 struct its_collection *col;
505 u16 seq_num;
506 u16 its_list;
507 } its_vmovp_cmd;
508
509 struct {
510 struct its_vpe *vpe;
511 } its_invdb_cmd;
512
513 struct {
514 struct its_vpe *vpe;
515 u8 sgi;
516 u8 priority;
517 bool enable;
518 bool group;
519 bool clear;
520 } its_vsgi_cmd;
521 };
522};
523
524/*
525 * The ITS command block, which is what the ITS actually parses.
526 */
527struct its_cmd_block {
528 union {
529 u64 raw_cmd[4];
530 __le64 raw_cmd_le[4];
531 };
532};
533
534#define ITS_CMD_QUEUE_SZ SZ_64K
535#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
536
537typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
538 struct its_cmd_block *,
539 struct its_cmd_desc *);
540
541typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
542 struct its_cmd_block *,
543 struct its_cmd_desc *);
544
545static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
546{
547 u64 mask = GENMASK_ULL(h, l);
548 *raw_cmd &= ~mask;
549 *raw_cmd |= (val << l) & mask;
550}
551
552static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
553{
554 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
555}
556
557static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
558{
559 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
560}
561
562static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
563{
564 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
565}
566
567static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
568{
569 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
570}
571
572static void its_encode_size(struct its_cmd_block *cmd, u8 size)
573{
574 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
575}
576
577static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
578{
579 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
580}
581
582static void its_encode_valid(struct its_cmd_block *cmd, int valid)
583{
584 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
585}
586
587static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
588{
589 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
590}
591
592static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
593{
594 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
595}
596
597static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
598{
599 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
600}
601
602static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
603{
604 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
605}
606
607static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
608{
609 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
610}
611
612static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
613{
614 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
615}
616
617static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
618{
619 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
620}
621
622static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
623{
624 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
625}
626
627static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
628{
629 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
630}
631
632static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
633{
634 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
635}
636
637static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
638{
639 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
640}
641
642static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
643{
644 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
645}
646
647static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
648{
649 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
650}
651
652static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
653 u32 vpe_db_lpi)
654{
655 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
656}
657
658static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
659 u32 vpe_db_lpi)
660{
661 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
662}
663
664static void its_encode_db(struct its_cmd_block *cmd, bool db)
665{
666 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
667}
668
669static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
670{
671 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
672}
673
674static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
675{
676 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
677}
678
679static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
680{
681 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
682}
683
684static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
685{
686 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
687}
688
689static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
690{
691 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
692}
693
694static inline void its_fixup_cmd(struct its_cmd_block *cmd)
695{
696 /* Let's fixup BE commands */
697 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
698 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
699 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
700 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
701}
702
703static struct its_collection *its_build_mapd_cmd(struct its_node *its,
704 struct its_cmd_block *cmd,
705 struct its_cmd_desc *desc)
706{
707 unsigned long itt_addr;
708 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
709
710 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
711
712 its_encode_cmd(cmd, GITS_CMD_MAPD);
713 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
714 its_encode_size(cmd, size - 1);
715 its_encode_itt(cmd, itt_addr);
716 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
717
718 its_fixup_cmd(cmd);
719
720 return NULL;
721}
722
723static struct its_collection *its_build_mapc_cmd(struct its_node *its,
724 struct its_cmd_block *cmd,
725 struct its_cmd_desc *desc)
726{
727 its_encode_cmd(cmd, GITS_CMD_MAPC);
728 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
729 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
730 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
731
732 its_fixup_cmd(cmd);
733
734 return desc->its_mapc_cmd.col;
735}
736
737static struct its_collection *its_build_mapti_cmd(struct its_node *its,
738 struct its_cmd_block *cmd,
739 struct its_cmd_desc *desc)
740{
741 struct its_collection *col;
742
743 col = dev_event_to_col(desc->its_mapti_cmd.dev,
744 desc->its_mapti_cmd.event_id);
745
746 its_encode_cmd(cmd, GITS_CMD_MAPTI);
747 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
748 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
749 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
750 its_encode_collection(cmd, col->col_id);
751
752 its_fixup_cmd(cmd);
753
754 return valid_col(col);
755}
756
757static struct its_collection *its_build_movi_cmd(struct its_node *its,
758 struct its_cmd_block *cmd,
759 struct its_cmd_desc *desc)
760{
761 struct its_collection *col;
762
763 col = dev_event_to_col(desc->its_movi_cmd.dev,
764 desc->its_movi_cmd.event_id);
765
766 its_encode_cmd(cmd, GITS_CMD_MOVI);
767 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
768 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
769 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
770
771 its_fixup_cmd(cmd);
772
773 return valid_col(col);
774}
775
776static struct its_collection *its_build_discard_cmd(struct its_node *its,
777 struct its_cmd_block *cmd,
778 struct its_cmd_desc *desc)
779{
780 struct its_collection *col;
781
782 col = dev_event_to_col(desc->its_discard_cmd.dev,
783 desc->its_discard_cmd.event_id);
784
785 its_encode_cmd(cmd, GITS_CMD_DISCARD);
786 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
787 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
788
789 its_fixup_cmd(cmd);
790
791 return valid_col(col);
792}
793
794static struct its_collection *its_build_inv_cmd(struct its_node *its,
795 struct its_cmd_block *cmd,
796 struct its_cmd_desc *desc)
797{
798 struct its_collection *col;
799
800 col = dev_event_to_col(desc->its_inv_cmd.dev,
801 desc->its_inv_cmd.event_id);
802
803 its_encode_cmd(cmd, GITS_CMD_INV);
804 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
805 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
806
807 its_fixup_cmd(cmd);
808
809 return valid_col(col);
810}
811
812static struct its_collection *its_build_int_cmd(struct its_node *its,
813 struct its_cmd_block *cmd,
814 struct its_cmd_desc *desc)
815{
816 struct its_collection *col;
817
818 col = dev_event_to_col(desc->its_int_cmd.dev,
819 desc->its_int_cmd.event_id);
820
821 its_encode_cmd(cmd, GITS_CMD_INT);
822 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
823 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
824
825 its_fixup_cmd(cmd);
826
827 return valid_col(col);
828}
829
830static struct its_collection *its_build_clear_cmd(struct its_node *its,
831 struct its_cmd_block *cmd,
832 struct its_cmd_desc *desc)
833{
834 struct its_collection *col;
835
836 col = dev_event_to_col(desc->its_clear_cmd.dev,
837 desc->its_clear_cmd.event_id);
838
839 its_encode_cmd(cmd, GITS_CMD_CLEAR);
840 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
841 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
842
843 its_fixup_cmd(cmd);
844
845 return valid_col(col);
846}
847
848static struct its_collection *its_build_invall_cmd(struct its_node *its,
849 struct its_cmd_block *cmd,
850 struct its_cmd_desc *desc)
851{
852 its_encode_cmd(cmd, GITS_CMD_INVALL);
853 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
854
855 its_fixup_cmd(cmd);
856
857 return desc->its_invall_cmd.col;
858}
859
860static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
861 struct its_cmd_block *cmd,
862 struct its_cmd_desc *desc)
863{
864 its_encode_cmd(cmd, GITS_CMD_VINVALL);
865 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
866
867 its_fixup_cmd(cmd);
868
869 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
870}
871
872static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
873 struct its_cmd_block *cmd,
874 struct its_cmd_desc *desc)
875{
876 struct its_vpe *vpe = valid_vpe(its, desc->its_vmapp_cmd.vpe);
877 unsigned long vpt_addr, vconf_addr;
878 u64 target;
879 bool alloc;
880
881 its_encode_cmd(cmd, GITS_CMD_VMAPP);
882 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
883 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
884
885 if (!desc->its_vmapp_cmd.valid) {
886 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
887 if (is_v4_1(its)) {
888 its_encode_alloc(cmd, alloc);
889 /*
890 * Unmapping a VPE is self-synchronizing on GICv4.1,
891 * no need to issue a VSYNC.
892 */
893 vpe = NULL;
894 }
895
896 goto out;
897 }
898
899 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
900 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
901
902 its_encode_target(cmd, target);
903 its_encode_vpt_addr(cmd, vpt_addr);
904 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
905
906 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
907
908 if (!is_v4_1(its))
909 goto out;
910
911 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
912
913 its_encode_alloc(cmd, alloc);
914
915 /*
916 * GICv4.1 provides a way to get the VLPI state, which needs the vPE
917 * to be unmapped first, and in this case, we may remap the vPE
918 * back while the VPT is not empty. So we can't assume that the
919 * VPT is empty on map. This is why we never advertise PTZ.
920 */
921 its_encode_ptz(cmd, false);
922 its_encode_vconf_addr(cmd, vconf_addr);
923 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
924
925out:
926 its_fixup_cmd(cmd);
927
928 return vpe;
929}
930
931static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
932 struct its_cmd_block *cmd,
933 struct its_cmd_desc *desc)
934{
935 u32 db;
936
937 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
938 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
939 else
940 db = 1023;
941
942 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
943 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
944 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
945 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
946 its_encode_db_phys_id(cmd, db);
947 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
948
949 its_fixup_cmd(cmd);
950
951 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
952}
953
954static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
955 struct its_cmd_block *cmd,
956 struct its_cmd_desc *desc)
957{
958 u32 db;
959
960 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
961 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
962 else
963 db = 1023;
964
965 its_encode_cmd(cmd, GITS_CMD_VMOVI);
966 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
967 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
968 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
969 its_encode_db_phys_id(cmd, db);
970 its_encode_db_valid(cmd, true);
971
972 its_fixup_cmd(cmd);
973
974 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
975}
976
977static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
978 struct its_cmd_block *cmd,
979 struct its_cmd_desc *desc)
980{
981 u64 target;
982
983 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
984 its_encode_cmd(cmd, GITS_CMD_VMOVP);
985 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
986 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
987 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
988 its_encode_target(cmd, target);
989
990 if (is_v4_1(its)) {
991 its_encode_db(cmd, true);
992 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
993 }
994
995 its_fixup_cmd(cmd);
996
997 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
998}
999
1000static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
1001 struct its_cmd_block *cmd,
1002 struct its_cmd_desc *desc)
1003{
1004 struct its_vlpi_map *map;
1005
1006 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
1007 desc->its_inv_cmd.event_id);
1008
1009 its_encode_cmd(cmd, GITS_CMD_INV);
1010 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
1011 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
1012
1013 its_fixup_cmd(cmd);
1014
1015 return valid_vpe(its, map->vpe);
1016}
1017
1018static struct its_vpe *its_build_vint_cmd(struct its_node *its,
1019 struct its_cmd_block *cmd,
1020 struct its_cmd_desc *desc)
1021{
1022 struct its_vlpi_map *map;
1023
1024 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
1025 desc->its_int_cmd.event_id);
1026
1027 its_encode_cmd(cmd, GITS_CMD_INT);
1028 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
1029 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
1030
1031 its_fixup_cmd(cmd);
1032
1033 return valid_vpe(its, map->vpe);
1034}
1035
1036static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
1037 struct its_cmd_block *cmd,
1038 struct its_cmd_desc *desc)
1039{
1040 struct its_vlpi_map *map;
1041
1042 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
1043 desc->its_clear_cmd.event_id);
1044
1045 its_encode_cmd(cmd, GITS_CMD_CLEAR);
1046 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
1047 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
1048
1049 its_fixup_cmd(cmd);
1050
1051 return valid_vpe(its, map->vpe);
1052}
1053
1054static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
1055 struct its_cmd_block *cmd,
1056 struct its_cmd_desc *desc)
1057{
1058 if (WARN_ON(!is_v4_1(its)))
1059 return NULL;
1060
1061 its_encode_cmd(cmd, GITS_CMD_INVDB);
1062 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
1063
1064 its_fixup_cmd(cmd);
1065
1066 return valid_vpe(its, desc->its_invdb_cmd.vpe);
1067}
1068
1069static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
1070 struct its_cmd_block *cmd,
1071 struct its_cmd_desc *desc)
1072{
1073 if (WARN_ON(!is_v4_1(its)))
1074 return NULL;
1075
1076 its_encode_cmd(cmd, GITS_CMD_VSGI);
1077 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
1078 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
1079 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
1080 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
1081 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
1082 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
1083
1084 its_fixup_cmd(cmd);
1085
1086 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
1087}
1088
1089static u64 its_cmd_ptr_to_offset(struct its_node *its,
1090 struct its_cmd_block *ptr)
1091{
1092 return (ptr - its->cmd_base) * sizeof(*ptr);
1093}
1094
1095static int its_queue_full(struct its_node *its)
1096{
1097 int widx;
1098 int ridx;
1099
1100 widx = its->cmd_write - its->cmd_base;
1101 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
1102
1103 /* This is incredibly unlikely to happen, unless the ITS locks up. */
1104 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
1105 return 1;
1106
1107 return 0;
1108}
1109
1110static struct its_cmd_block *its_allocate_entry(struct its_node *its)
1111{
1112 struct its_cmd_block *cmd;
1113 u32 count = 1000000; /* 1s! */
1114
1115 while (its_queue_full(its)) {
1116 count--;
1117 if (!count) {
1118 pr_err_ratelimited("ITS queue not draining\n");
1119 return NULL;
1120 }
1121 cpu_relax();
1122 udelay(1);
1123 }
1124
1125 cmd = its->cmd_write++;
1126
1127 /* Handle queue wrapping */
1128 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1129 its->cmd_write = its->cmd_base;
1130
1131 /* Clear command */
1132 cmd->raw_cmd[0] = 0;
1133 cmd->raw_cmd[1] = 0;
1134 cmd->raw_cmd[2] = 0;
1135 cmd->raw_cmd[3] = 0;
1136
1137 return cmd;
1138}
1139
1140static struct its_cmd_block *its_post_commands(struct its_node *its)
1141{
1142 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1143
1144 writel_relaxed(wr, its->base + GITS_CWRITER);
1145
1146 return its->cmd_write;
1147}
1148
1149static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1150{
1151 /*
1152 * Make sure the commands written to memory are observable by
1153 * the ITS.
1154 */
1155 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1156 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1157 else
1158 dsb(ishst);
1159}
1160
1161static int its_wait_for_range_completion(struct its_node *its,
1162 u64 prev_idx,
1163 struct its_cmd_block *to)
1164{
1165 u64 rd_idx, to_idx, linear_idx;
1166 u32 count = 1000000; /* 1s! */
1167
1168 /* Linearize to_idx if the command set has wrapped around */
1169 to_idx = its_cmd_ptr_to_offset(its, to);
1170 if (to_idx < prev_idx)
1171 to_idx += ITS_CMD_QUEUE_SZ;
1172
1173 linear_idx = prev_idx;
1174
1175 while (1) {
1176 s64 delta;
1177
1178 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1179
1180 /*
1181 * Compute the read pointer progress, taking the
1182 * potential wrap-around into account.
1183 */
1184 delta = rd_idx - prev_idx;
1185 if (rd_idx < prev_idx)
1186 delta += ITS_CMD_QUEUE_SZ;
1187
1188 linear_idx += delta;
1189 if (linear_idx >= to_idx)
1190 break;
1191
1192 count--;
1193 if (!count) {
1194 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1195 to_idx, linear_idx);
1196 return -1;
1197 }
1198 prev_idx = rd_idx;
1199 cpu_relax();
1200 udelay(1);
1201 }
1202
1203 return 0;
1204}
1205
1206/* Warning, macro hell follows */
1207#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1208void name(struct its_node *its, \
1209 buildtype builder, \
1210 struct its_cmd_desc *desc) \
1211{ \
1212 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1213 synctype *sync_obj; \
1214 unsigned long flags; \
1215 u64 rd_idx; \
1216 \
1217 raw_spin_lock_irqsave(&its->lock, flags); \
1218 \
1219 cmd = its_allocate_entry(its); \
1220 if (!cmd) { /* We're soooooo screewed... */ \
1221 raw_spin_unlock_irqrestore(&its->lock, flags); \
1222 return; \
1223 } \
1224 sync_obj = builder(its, cmd, desc); \
1225 its_flush_cmd(its, cmd); \
1226 \
1227 if (sync_obj) { \
1228 sync_cmd = its_allocate_entry(its); \
1229 if (!sync_cmd) \
1230 goto post; \
1231 \
1232 buildfn(its, sync_cmd, sync_obj); \
1233 its_flush_cmd(its, sync_cmd); \
1234 } \
1235 \
1236post: \
1237 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1238 next_cmd = its_post_commands(its); \
1239 raw_spin_unlock_irqrestore(&its->lock, flags); \
1240 \
1241 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1242 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1243}
1244
1245static void its_build_sync_cmd(struct its_node *its,
1246 struct its_cmd_block *sync_cmd,
1247 struct its_collection *sync_col)
1248{
1249 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1250 its_encode_target(sync_cmd, sync_col->target_address);
1251
1252 its_fixup_cmd(sync_cmd);
1253}
1254
1255static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1256 struct its_collection, its_build_sync_cmd)
1257
1258static void its_build_vsync_cmd(struct its_node *its,
1259 struct its_cmd_block *sync_cmd,
1260 struct its_vpe *sync_vpe)
1261{
1262 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1263 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1264
1265 its_fixup_cmd(sync_cmd);
1266}
1267
1268static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1269 struct its_vpe, its_build_vsync_cmd)
1270
1271static void its_send_int(struct its_device *dev, u32 event_id)
1272{
1273 struct its_cmd_desc desc;
1274
1275 desc.its_int_cmd.dev = dev;
1276 desc.its_int_cmd.event_id = event_id;
1277
1278 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1279}
1280
1281static void its_send_clear(struct its_device *dev, u32 event_id)
1282{
1283 struct its_cmd_desc desc;
1284
1285 desc.its_clear_cmd.dev = dev;
1286 desc.its_clear_cmd.event_id = event_id;
1287
1288 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1289}
1290
1291static void its_send_inv(struct its_device *dev, u32 event_id)
1292{
1293 struct its_cmd_desc desc;
1294
1295 desc.its_inv_cmd.dev = dev;
1296 desc.its_inv_cmd.event_id = event_id;
1297
1298 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1299}
1300
1301static void its_send_mapd(struct its_device *dev, int valid)
1302{
1303 struct its_cmd_desc desc;
1304
1305 desc.its_mapd_cmd.dev = dev;
1306 desc.its_mapd_cmd.valid = !!valid;
1307
1308 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1309}
1310
1311static void its_send_mapc(struct its_node *its, struct its_collection *col,
1312 int valid)
1313{
1314 struct its_cmd_desc desc;
1315
1316 desc.its_mapc_cmd.col = col;
1317 desc.its_mapc_cmd.valid = !!valid;
1318
1319 its_send_single_command(its, its_build_mapc_cmd, &desc);
1320}
1321
1322static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1323{
1324 struct its_cmd_desc desc;
1325
1326 desc.its_mapti_cmd.dev = dev;
1327 desc.its_mapti_cmd.phys_id = irq_id;
1328 desc.its_mapti_cmd.event_id = id;
1329
1330 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1331}
1332
1333static void its_send_movi(struct its_device *dev,
1334 struct its_collection *col, u32 id)
1335{
1336 struct its_cmd_desc desc;
1337
1338 desc.its_movi_cmd.dev = dev;
1339 desc.its_movi_cmd.col = col;
1340 desc.its_movi_cmd.event_id = id;
1341
1342 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1343}
1344
1345static void its_send_discard(struct its_device *dev, u32 id)
1346{
1347 struct its_cmd_desc desc;
1348
1349 desc.its_discard_cmd.dev = dev;
1350 desc.its_discard_cmd.event_id = id;
1351
1352 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1353}
1354
1355static void its_send_invall(struct its_node *its, struct its_collection *col)
1356{
1357 struct its_cmd_desc desc;
1358
1359 desc.its_invall_cmd.col = col;
1360
1361 its_send_single_command(its, its_build_invall_cmd, &desc);
1362}
1363
1364static void its_send_vmapti(struct its_device *dev, u32 id)
1365{
1366 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1367 struct its_cmd_desc desc;
1368
1369 desc.its_vmapti_cmd.vpe = map->vpe;
1370 desc.its_vmapti_cmd.dev = dev;
1371 desc.its_vmapti_cmd.virt_id = map->vintid;
1372 desc.its_vmapti_cmd.event_id = id;
1373 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1374
1375 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1376}
1377
1378static void its_send_vmovi(struct its_device *dev, u32 id)
1379{
1380 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1381 struct its_cmd_desc desc;
1382
1383 desc.its_vmovi_cmd.vpe = map->vpe;
1384 desc.its_vmovi_cmd.dev = dev;
1385 desc.its_vmovi_cmd.event_id = id;
1386 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1387
1388 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1389}
1390
1391static void its_send_vmapp(struct its_node *its,
1392 struct its_vpe *vpe, bool valid)
1393{
1394 struct its_cmd_desc desc;
1395
1396 desc.its_vmapp_cmd.vpe = vpe;
1397 desc.its_vmapp_cmd.valid = valid;
1398 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1399
1400 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1401}
1402
1403static void its_send_vmovp(struct its_vpe *vpe)
1404{
1405 struct its_cmd_desc desc = {};
1406 struct its_node *its;
1407 int col_id = vpe->col_idx;
1408
1409 desc.its_vmovp_cmd.vpe = vpe;
1410
1411 if (!its_list_map) {
1412 its = list_first_entry(&its_nodes, struct its_node, entry);
1413 desc.its_vmovp_cmd.col = &its->collections[col_id];
1414 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1415 return;
1416 }
1417
1418 /*
1419 * Yet another marvel of the architecture. If using the
1420 * its_list "feature", we need to make sure that all ITSs
1421 * receive all VMOVP commands in the same order. The only way
1422 * to guarantee this is to make vmovp a serialization point.
1423 *
1424 * Wall <-- Head.
1425 */
1426 guard(raw_spinlock)(&vmovp_lock);
1427 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1428 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1429
1430 /* Emit VMOVPs */
1431 list_for_each_entry(its, &its_nodes, entry) {
1432 if (!is_v4(its))
1433 continue;
1434
1435 if (!require_its_list_vmovp(vpe->its_vm, its))
1436 continue;
1437
1438 desc.its_vmovp_cmd.col = &its->collections[col_id];
1439 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1440 }
1441}
1442
1443static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1444{
1445 struct its_cmd_desc desc;
1446
1447 desc.its_vinvall_cmd.vpe = vpe;
1448 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1449}
1450
1451static void its_send_vinv(struct its_device *dev, u32 event_id)
1452{
1453 struct its_cmd_desc desc;
1454
1455 /*
1456 * There is no real VINV command. This is just a normal INV,
1457 * with a VSYNC instead of a SYNC.
1458 */
1459 desc.its_inv_cmd.dev = dev;
1460 desc.its_inv_cmd.event_id = event_id;
1461
1462 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1463}
1464
1465static void its_send_vint(struct its_device *dev, u32 event_id)
1466{
1467 struct its_cmd_desc desc;
1468
1469 /*
1470 * There is no real VINT command. This is just a normal INT,
1471 * with a VSYNC instead of a SYNC.
1472 */
1473 desc.its_int_cmd.dev = dev;
1474 desc.its_int_cmd.event_id = event_id;
1475
1476 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1477}
1478
1479static void its_send_vclear(struct its_device *dev, u32 event_id)
1480{
1481 struct its_cmd_desc desc;
1482
1483 /*
1484 * There is no real VCLEAR command. This is just a normal CLEAR,
1485 * with a VSYNC instead of a SYNC.
1486 */
1487 desc.its_clear_cmd.dev = dev;
1488 desc.its_clear_cmd.event_id = event_id;
1489
1490 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1491}
1492
1493static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1494{
1495 struct its_cmd_desc desc;
1496
1497 desc.its_invdb_cmd.vpe = vpe;
1498 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1499}
1500
1501/*
1502 * irqchip functions - assumes MSI, mostly.
1503 */
1504static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1505{
1506 struct its_vlpi_map *map = get_vlpi_map(d);
1507 irq_hw_number_t hwirq;
1508 void *va;
1509 u8 *cfg;
1510
1511 if (map) {
1512 va = page_address(map->vm->vprop_page);
1513 hwirq = map->vintid;
1514
1515 /* Remember the updated property */
1516 map->properties &= ~clr;
1517 map->properties |= set | LPI_PROP_GROUP1;
1518 } else {
1519 va = gic_rdists->prop_table_va;
1520 hwirq = d->hwirq;
1521 }
1522
1523 cfg = va + hwirq - 8192;
1524 *cfg &= ~clr;
1525 *cfg |= set | LPI_PROP_GROUP1;
1526
1527 /*
1528 * Make the above write visible to the redistributors.
1529 * And yes, we're flushing exactly: One. Single. Byte.
1530 * Humpf...
1531 */
1532 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1533 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1534 else
1535 dsb(ishst);
1536}
1537
1538static void wait_for_syncr(void __iomem *rdbase)
1539{
1540 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1541 cpu_relax();
1542}
1543
1544static void __direct_lpi_inv(struct irq_data *d, u64 val)
1545{
1546 void __iomem *rdbase;
1547 unsigned long flags;
1548 int cpu;
1549
1550 /* Target the redistributor this LPI is currently routed to */
1551 cpu = irq_to_cpuid_lock(d, &flags);
1552 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1553
1554 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1555 gic_write_lpir(val, rdbase + GICR_INVLPIR);
1556 wait_for_syncr(rdbase);
1557
1558 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1559 irq_to_cpuid_unlock(d, flags);
1560}
1561
1562static void direct_lpi_inv(struct irq_data *d)
1563{
1564 struct its_vlpi_map *map = get_vlpi_map(d);
1565 u64 val;
1566
1567 if (map) {
1568 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1569
1570 WARN_ON(!is_v4_1(its_dev->its));
1571
1572 val = GICR_INVLPIR_V;
1573 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1574 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1575 } else {
1576 val = d->hwirq;
1577 }
1578
1579 __direct_lpi_inv(d, val);
1580}
1581
1582static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1583{
1584 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1585
1586 lpi_write_config(d, clr, set);
1587 if (gic_rdists->has_direct_lpi &&
1588 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1589 direct_lpi_inv(d);
1590 else if (!irqd_is_forwarded_to_vcpu(d))
1591 its_send_inv(its_dev, its_get_event_id(d));
1592 else
1593 its_send_vinv(its_dev, its_get_event_id(d));
1594}
1595
1596static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1597{
1598 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1599 u32 event = its_get_event_id(d);
1600 struct its_vlpi_map *map;
1601
1602 /*
1603 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1604 * here.
1605 */
1606 if (is_v4_1(its_dev->its))
1607 return;
1608
1609 map = dev_event_to_vlpi_map(its_dev, event);
1610
1611 if (map->db_enabled == enable)
1612 return;
1613
1614 map->db_enabled = enable;
1615
1616 /*
1617 * More fun with the architecture:
1618 *
1619 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1620 * value or to 1023, depending on the enable bit. But that
1621 * would be issuing a mapping for an /existing/ DevID+EventID
1622 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1623 * to the /same/ vPE, using this opportunity to adjust the
1624 * doorbell. Mouahahahaha. We loves it, Precious.
1625 */
1626 its_send_vmovi(its_dev, event);
1627}
1628
1629static void its_mask_irq(struct irq_data *d)
1630{
1631 if (irqd_is_forwarded_to_vcpu(d))
1632 its_vlpi_set_doorbell(d, false);
1633
1634 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1635}
1636
1637static void its_unmask_irq(struct irq_data *d)
1638{
1639 if (irqd_is_forwarded_to_vcpu(d))
1640 its_vlpi_set_doorbell(d, true);
1641
1642 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1643}
1644
1645static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1646{
1647 if (irqd_affinity_is_managed(d))
1648 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1649
1650 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1651}
1652
1653static void its_inc_lpi_count(struct irq_data *d, int cpu)
1654{
1655 if (irqd_affinity_is_managed(d))
1656 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1657 else
1658 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1659}
1660
1661static void its_dec_lpi_count(struct irq_data *d, int cpu)
1662{
1663 if (irqd_affinity_is_managed(d))
1664 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1665 else
1666 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1667}
1668
1669static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1670 const struct cpumask *cpu_mask)
1671{
1672 unsigned int cpu = nr_cpu_ids, tmp;
1673 int count = S32_MAX;
1674
1675 for_each_cpu(tmp, cpu_mask) {
1676 int this_count = its_read_lpi_count(d, tmp);
1677 if (this_count < count) {
1678 cpu = tmp;
1679 count = this_count;
1680 }
1681 }
1682
1683 return cpu;
1684}
1685
1686/*
1687 * As suggested by Thomas Gleixner in:
1688 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1689 */
1690static int its_select_cpu(struct irq_data *d,
1691 const struct cpumask *aff_mask)
1692{
1693 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1694 static DEFINE_RAW_SPINLOCK(tmpmask_lock);
1695 static struct cpumask __tmpmask;
1696 struct cpumask *tmpmask;
1697 unsigned long flags;
1698 int cpu, node;
1699 node = its_dev->its->numa_node;
1700 tmpmask = &__tmpmask;
1701
1702 raw_spin_lock_irqsave(&tmpmask_lock, flags);
1703
1704 if (!irqd_affinity_is_managed(d)) {
1705 /* First try the NUMA node */
1706 if (node != NUMA_NO_NODE) {
1707 /*
1708 * Try the intersection of the affinity mask and the
1709 * node mask (and the online mask, just to be safe).
1710 */
1711 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1712 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1713
1714 /*
1715 * Ideally, we would check if the mask is empty, and
1716 * try again on the full node here.
1717 *
1718 * But it turns out that the way ACPI describes the
1719 * affinity for ITSs only deals about memory, and
1720 * not target CPUs, so it cannot describe a single
1721 * ITS placed next to two NUMA nodes.
1722 *
1723 * Instead, just fallback on the online mask. This
1724 * diverges from Thomas' suggestion above.
1725 */
1726 cpu = cpumask_pick_least_loaded(d, tmpmask);
1727 if (cpu < nr_cpu_ids)
1728 goto out;
1729
1730 /* If we can't cross sockets, give up */
1731 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1732 goto out;
1733
1734 /* If the above failed, expand the search */
1735 }
1736
1737 /* Try the intersection of the affinity and online masks */
1738 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1739
1740 /* If that doesn't fly, the online mask is the last resort */
1741 if (cpumask_empty(tmpmask))
1742 cpumask_copy(tmpmask, cpu_online_mask);
1743
1744 cpu = cpumask_pick_least_loaded(d, tmpmask);
1745 } else {
1746 cpumask_copy(tmpmask, aff_mask);
1747
1748 /* If we cannot cross sockets, limit the search to that node */
1749 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1750 node != NUMA_NO_NODE)
1751 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1752
1753 cpu = cpumask_pick_least_loaded(d, tmpmask);
1754 }
1755out:
1756 raw_spin_unlock_irqrestore(&tmpmask_lock, flags);
1757
1758 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1759 return cpu;
1760}
1761
1762static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1763 bool force)
1764{
1765 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1766 struct its_collection *target_col;
1767 u32 id = its_get_event_id(d);
1768 int cpu, prev_cpu;
1769
1770 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1771 if (irqd_is_forwarded_to_vcpu(d))
1772 return -EINVAL;
1773
1774 prev_cpu = its_dev->event_map.col_map[id];
1775 its_dec_lpi_count(d, prev_cpu);
1776
1777 if (!force)
1778 cpu = its_select_cpu(d, mask_val);
1779 else
1780 cpu = cpumask_pick_least_loaded(d, mask_val);
1781
1782 if (cpu < 0 || cpu >= nr_cpu_ids)
1783 goto err;
1784
1785 /* don't set the affinity when the target cpu is same as current one */
1786 if (cpu != prev_cpu) {
1787 target_col = &its_dev->its->collections[cpu];
1788 its_send_movi(its_dev, target_col, id);
1789 its_dev->event_map.col_map[id] = cpu;
1790 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1791 }
1792
1793 its_inc_lpi_count(d, cpu);
1794
1795 return IRQ_SET_MASK_OK_DONE;
1796
1797err:
1798 its_inc_lpi_count(d, prev_cpu);
1799 return -EINVAL;
1800}
1801
1802static u64 its_irq_get_msi_base(struct its_device *its_dev)
1803{
1804 struct its_node *its = its_dev->its;
1805
1806 return its->phys_base + GITS_TRANSLATER;
1807}
1808
1809static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1810{
1811 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1812 struct its_node *its;
1813 u64 addr;
1814
1815 its = its_dev->its;
1816 addr = its->get_msi_base(its_dev);
1817
1818 msg->address_lo = lower_32_bits(addr);
1819 msg->address_hi = upper_32_bits(addr);
1820 msg->data = its_get_event_id(d);
1821
1822 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1823}
1824
1825static int its_irq_set_irqchip_state(struct irq_data *d,
1826 enum irqchip_irq_state which,
1827 bool state)
1828{
1829 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1830 u32 event = its_get_event_id(d);
1831
1832 if (which != IRQCHIP_STATE_PENDING)
1833 return -EINVAL;
1834
1835 if (irqd_is_forwarded_to_vcpu(d)) {
1836 if (state)
1837 its_send_vint(its_dev, event);
1838 else
1839 its_send_vclear(its_dev, event);
1840 } else {
1841 if (state)
1842 its_send_int(its_dev, event);
1843 else
1844 its_send_clear(its_dev, event);
1845 }
1846
1847 return 0;
1848}
1849
1850static int its_irq_retrigger(struct irq_data *d)
1851{
1852 return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1853}
1854
1855/*
1856 * Two favourable cases:
1857 *
1858 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1859 * for vSGI delivery
1860 *
1861 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1862 * and we're better off mapping all VPEs always
1863 *
1864 * If neither (a) nor (b) is true, then we map vPEs on demand.
1865 *
1866 */
1867static bool gic_requires_eager_mapping(void)
1868{
1869 if (!its_list_map || gic_rdists->has_rvpeid)
1870 return true;
1871
1872 return false;
1873}
1874
1875static void its_map_vm(struct its_node *its, struct its_vm *vm)
1876{
1877 if (gic_requires_eager_mapping())
1878 return;
1879
1880 guard(raw_spinlock_irqsave)(&vm->vmapp_lock);
1881
1882 /*
1883 * If the VM wasn't mapped yet, iterate over the vpes and get
1884 * them mapped now.
1885 */
1886 vm->vlpi_count[its->list_nr]++;
1887
1888 if (vm->vlpi_count[its->list_nr] == 1) {
1889 int i;
1890
1891 for (i = 0; i < vm->nr_vpes; i++) {
1892 struct its_vpe *vpe = vm->vpes[i];
1893
1894 scoped_guard(raw_spinlock, &vpe->vpe_lock)
1895 its_send_vmapp(its, vpe, true);
1896
1897 its_send_vinvall(its, vpe);
1898 }
1899 }
1900}
1901
1902static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1903{
1904 /* Not using the ITS list? Everything is always mapped. */
1905 if (gic_requires_eager_mapping())
1906 return;
1907
1908 guard(raw_spinlock_irqsave)(&vm->vmapp_lock);
1909
1910 if (!--vm->vlpi_count[its->list_nr]) {
1911 int i;
1912
1913 for (i = 0; i < vm->nr_vpes; i++) {
1914 guard(raw_spinlock)(&vm->vpes[i]->vpe_lock);
1915 its_send_vmapp(its, vm->vpes[i], false);
1916 }
1917 }
1918}
1919
1920static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1921{
1922 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1923 u32 event = its_get_event_id(d);
1924
1925 if (!info->map)
1926 return -EINVAL;
1927
1928 if (!its_dev->event_map.vm) {
1929 struct its_vlpi_map *maps;
1930
1931 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1932 GFP_ATOMIC);
1933 if (!maps)
1934 return -ENOMEM;
1935
1936 its_dev->event_map.vm = info->map->vm;
1937 its_dev->event_map.vlpi_maps = maps;
1938 } else if (its_dev->event_map.vm != info->map->vm) {
1939 return -EINVAL;
1940 }
1941
1942 /* Get our private copy of the mapping information */
1943 its_dev->event_map.vlpi_maps[event] = *info->map;
1944
1945 if (irqd_is_forwarded_to_vcpu(d)) {
1946 /* Already mapped, move it around */
1947 its_send_vmovi(its_dev, event);
1948 } else {
1949 /* Ensure all the VPEs are mapped on this ITS */
1950 its_map_vm(its_dev->its, info->map->vm);
1951
1952 /*
1953 * Flag the interrupt as forwarded so that we can
1954 * start poking the virtual property table.
1955 */
1956 irqd_set_forwarded_to_vcpu(d);
1957
1958 /* Write out the property to the prop table */
1959 lpi_write_config(d, 0xff, info->map->properties);
1960
1961 /* Drop the physical mapping */
1962 its_send_discard(its_dev, event);
1963
1964 /* and install the virtual one */
1965 its_send_vmapti(its_dev, event);
1966
1967 /* Increment the number of VLPIs */
1968 its_dev->event_map.nr_vlpis++;
1969 }
1970
1971 return 0;
1972}
1973
1974static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1975{
1976 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1977 struct its_vlpi_map *map;
1978
1979 map = get_vlpi_map(d);
1980
1981 if (!its_dev->event_map.vm || !map)
1982 return -EINVAL;
1983
1984 /* Copy our mapping information to the incoming request */
1985 *info->map = *map;
1986
1987 return 0;
1988}
1989
1990static int its_vlpi_unmap(struct irq_data *d)
1991{
1992 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1993 u32 event = its_get_event_id(d);
1994
1995 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1996 return -EINVAL;
1997
1998 /* Drop the virtual mapping */
1999 its_send_discard(its_dev, event);
2000
2001 /* and restore the physical one */
2002 irqd_clr_forwarded_to_vcpu(d);
2003 its_send_mapti(its_dev, d->hwirq, event);
2004 lpi_update_config(d, 0xff, (lpi_prop_prio |
2005 LPI_PROP_ENABLED |
2006 LPI_PROP_GROUP1));
2007
2008 /* Potentially unmap the VM from this ITS */
2009 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
2010
2011 /*
2012 * Drop the refcount and make the device available again if
2013 * this was the last VLPI.
2014 */
2015 if (!--its_dev->event_map.nr_vlpis) {
2016 its_dev->event_map.vm = NULL;
2017 kfree(its_dev->event_map.vlpi_maps);
2018 }
2019
2020 return 0;
2021}
2022
2023static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
2024{
2025 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2026
2027 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
2028 return -EINVAL;
2029
2030 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
2031 lpi_update_config(d, 0xff, info->config);
2032 else
2033 lpi_write_config(d, 0xff, info->config);
2034 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
2035
2036 return 0;
2037}
2038
2039static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2040{
2041 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2042 struct its_cmd_info *info = vcpu_info;
2043
2044 /* Need a v4 ITS */
2045 if (!is_v4(its_dev->its))
2046 return -EINVAL;
2047
2048 guard(raw_spinlock)(&its_dev->event_map.vlpi_lock);
2049
2050 /* Unmap request? */
2051 if (!info)
2052 return its_vlpi_unmap(d);
2053
2054 switch (info->cmd_type) {
2055 case MAP_VLPI:
2056 return its_vlpi_map(d, info);
2057
2058 case GET_VLPI:
2059 return its_vlpi_get(d, info);
2060
2061 case PROP_UPDATE_VLPI:
2062 case PROP_UPDATE_AND_INV_VLPI:
2063 return its_vlpi_prop_update(d, info);
2064
2065 default:
2066 return -EINVAL;
2067 }
2068}
2069
2070static struct irq_chip its_irq_chip = {
2071 .name = "ITS",
2072 .irq_mask = its_mask_irq,
2073 .irq_unmask = its_unmask_irq,
2074 .irq_eoi = irq_chip_eoi_parent,
2075 .irq_set_affinity = its_set_affinity,
2076 .irq_compose_msi_msg = its_irq_compose_msi_msg,
2077 .irq_set_irqchip_state = its_irq_set_irqchip_state,
2078 .irq_retrigger = its_irq_retrigger,
2079 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
2080};
2081
2082
2083/*
2084 * How we allocate LPIs:
2085 *
2086 * lpi_range_list contains ranges of LPIs that are to available to
2087 * allocate from. To allocate LPIs, just pick the first range that
2088 * fits the required allocation, and reduce it by the required
2089 * amount. Once empty, remove the range from the list.
2090 *
2091 * To free a range of LPIs, add a free range to the list, sort it and
2092 * merge the result if the new range happens to be adjacent to an
2093 * already free block.
2094 *
2095 * The consequence of the above is that allocation is cost is low, but
2096 * freeing is expensive. We assumes that freeing rarely occurs.
2097 */
2098#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
2099
2100static DEFINE_MUTEX(lpi_range_lock);
2101static LIST_HEAD(lpi_range_list);
2102
2103struct lpi_range {
2104 struct list_head entry;
2105 u32 base_id;
2106 u32 span;
2107};
2108
2109static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2110{
2111 struct lpi_range *range;
2112
2113 range = kmalloc(sizeof(*range), GFP_KERNEL);
2114 if (range) {
2115 range->base_id = base;
2116 range->span = span;
2117 }
2118
2119 return range;
2120}
2121
2122static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2123{
2124 struct lpi_range *range, *tmp;
2125 int err = -ENOSPC;
2126
2127 mutex_lock(&lpi_range_lock);
2128
2129 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2130 if (range->span >= nr_lpis) {
2131 *base = range->base_id;
2132 range->base_id += nr_lpis;
2133 range->span -= nr_lpis;
2134
2135 if (range->span == 0) {
2136 list_del(&range->entry);
2137 kfree(range);
2138 }
2139
2140 err = 0;
2141 break;
2142 }
2143 }
2144
2145 mutex_unlock(&lpi_range_lock);
2146
2147 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2148 return err;
2149}
2150
2151static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2152{
2153 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2154 return;
2155 if (a->base_id + a->span != b->base_id)
2156 return;
2157 b->base_id = a->base_id;
2158 b->span += a->span;
2159 list_del(&a->entry);
2160 kfree(a);
2161}
2162
2163static int free_lpi_range(u32 base, u32 nr_lpis)
2164{
2165 struct lpi_range *new, *old;
2166
2167 new = mk_lpi_range(base, nr_lpis);
2168 if (!new)
2169 return -ENOMEM;
2170
2171 mutex_lock(&lpi_range_lock);
2172
2173 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2174 if (old->base_id < base)
2175 break;
2176 }
2177 /*
2178 * old is the last element with ->base_id smaller than base,
2179 * so new goes right after it. If there are no elements with
2180 * ->base_id smaller than base, &old->entry ends up pointing
2181 * at the head of the list, and inserting new it the start of
2182 * the list is the right thing to do in that case as well.
2183 */
2184 list_add(&new->entry, &old->entry);
2185 /*
2186 * Now check if we can merge with the preceding and/or
2187 * following ranges.
2188 */
2189 merge_lpi_ranges(old, new);
2190 merge_lpi_ranges(new, list_next_entry(new, entry));
2191
2192 mutex_unlock(&lpi_range_lock);
2193 return 0;
2194}
2195
2196static int __init its_lpi_init(u32 id_bits)
2197{
2198 u32 lpis = (1UL << id_bits) - 8192;
2199 u32 numlpis;
2200 int err;
2201
2202 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2203
2204 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2205 lpis = numlpis;
2206 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2207 lpis);
2208 }
2209
2210 /*
2211 * Initializing the allocator is just the same as freeing the
2212 * full range of LPIs.
2213 */
2214 err = free_lpi_range(8192, lpis);
2215 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2216 return err;
2217}
2218
2219static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2220{
2221 unsigned long *bitmap = NULL;
2222 int err = 0;
2223
2224 do {
2225 err = alloc_lpi_range(nr_irqs, base);
2226 if (!err)
2227 break;
2228
2229 nr_irqs /= 2;
2230 } while (nr_irqs > 0);
2231
2232 if (!nr_irqs)
2233 err = -ENOSPC;
2234
2235 if (err)
2236 goto out;
2237
2238 bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2239 if (!bitmap)
2240 goto out;
2241
2242 *nr_ids = nr_irqs;
2243
2244out:
2245 if (!bitmap)
2246 *base = *nr_ids = 0;
2247
2248 return bitmap;
2249}
2250
2251static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2252{
2253 WARN_ON(free_lpi_range(base, nr_ids));
2254 bitmap_free(bitmap);
2255}
2256
2257static void gic_reset_prop_table(void *va)
2258{
2259 /* Regular IRQ priority, Group-1, disabled */
2260 memset(va, lpi_prop_prio | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2261
2262 /* Make sure the GIC will observe the written configuration */
2263 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2264}
2265
2266static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2267{
2268 struct page *prop_page;
2269
2270 prop_page = its_alloc_pages(gfp_flags,
2271 get_order(LPI_PROPBASE_SZ));
2272 if (!prop_page)
2273 return NULL;
2274
2275 gic_reset_prop_table(page_address(prop_page));
2276
2277 return prop_page;
2278}
2279
2280static void its_free_prop_table(struct page *prop_page)
2281{
2282 its_free_pages(page_address(prop_page), get_order(LPI_PROPBASE_SZ));
2283}
2284
2285static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2286{
2287 phys_addr_t start, end, addr_end;
2288 u64 i;
2289
2290 /*
2291 * We don't bother checking for a kdump kernel as by
2292 * construction, the LPI tables are out of this kernel's
2293 * memory map.
2294 */
2295 if (is_kdump_kernel())
2296 return true;
2297
2298 addr_end = addr + size - 1;
2299
2300 for_each_reserved_mem_range(i, &start, &end) {
2301 if (addr >= start && addr_end <= end)
2302 return true;
2303 }
2304
2305 /* Not found, not a good sign... */
2306 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2307 &addr, &addr_end);
2308 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2309 return false;
2310}
2311
2312static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2313{
2314 if (efi_enabled(EFI_CONFIG_TABLES))
2315 return efi_mem_reserve_persistent(addr, size);
2316
2317 return 0;
2318}
2319
2320static int __init its_setup_lpi_prop_table(void)
2321{
2322 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2323 u64 val;
2324
2325 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2326 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2327
2328 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2329 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2330 LPI_PROPBASE_SZ,
2331 MEMREMAP_WB);
2332 gic_reset_prop_table(gic_rdists->prop_table_va);
2333 } else {
2334 struct page *page;
2335
2336 lpi_id_bits = min_t(u32,
2337 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2338 ITS_MAX_LPI_NRBITS);
2339 page = its_allocate_prop_table(GFP_NOWAIT);
2340 if (!page) {
2341 pr_err("Failed to allocate PROPBASE\n");
2342 return -ENOMEM;
2343 }
2344
2345 gic_rdists->prop_table_pa = page_to_phys(page);
2346 gic_rdists->prop_table_va = page_address(page);
2347 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2348 LPI_PROPBASE_SZ));
2349 }
2350
2351 pr_info("GICv3: using LPI property table @%pa\n",
2352 &gic_rdists->prop_table_pa);
2353
2354 return its_lpi_init(lpi_id_bits);
2355}
2356
2357static const char *its_base_type_string[] = {
2358 [GITS_BASER_TYPE_DEVICE] = "Devices",
2359 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
2360 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
2361 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2362 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2363 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2364 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2365};
2366
2367static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2368{
2369 u32 idx = baser - its->tables;
2370
2371 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2372}
2373
2374static void its_write_baser(struct its_node *its, struct its_baser *baser,
2375 u64 val)
2376{
2377 u32 idx = baser - its->tables;
2378
2379 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2380 baser->val = its_read_baser(its, baser);
2381}
2382
2383static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2384 u64 cache, u64 shr, u32 order, bool indirect)
2385{
2386 u64 val = its_read_baser(its, baser);
2387 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2388 u64 type = GITS_BASER_TYPE(val);
2389 u64 baser_phys, tmp;
2390 u32 alloc_pages, psz;
2391 struct page *page;
2392 void *base;
2393
2394 psz = baser->psz;
2395 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2396 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2397 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2398 &its->phys_base, its_base_type_string[type],
2399 alloc_pages, GITS_BASER_PAGES_MAX);
2400 alloc_pages = GITS_BASER_PAGES_MAX;
2401 order = get_order(GITS_BASER_PAGES_MAX * psz);
2402 }
2403
2404 page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2405 if (!page)
2406 return -ENOMEM;
2407
2408 base = (void *)page_address(page);
2409 baser_phys = virt_to_phys(base);
2410
2411 /* Check if the physical address of the memory is above 48bits */
2412 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2413
2414 /* 52bit PA is supported only when PageSize=64K */
2415 if (psz != SZ_64K) {
2416 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2417 its_free_pages(base, order);
2418 return -ENXIO;
2419 }
2420
2421 /* Convert 52bit PA to 48bit field */
2422 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2423 }
2424
2425retry_baser:
2426 val = (baser_phys |
2427 (type << GITS_BASER_TYPE_SHIFT) |
2428 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2429 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2430 cache |
2431 shr |
2432 GITS_BASER_VALID);
2433
2434 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2435
2436 switch (psz) {
2437 case SZ_4K:
2438 val |= GITS_BASER_PAGE_SIZE_4K;
2439 break;
2440 case SZ_16K:
2441 val |= GITS_BASER_PAGE_SIZE_16K;
2442 break;
2443 case SZ_64K:
2444 val |= GITS_BASER_PAGE_SIZE_64K;
2445 break;
2446 }
2447
2448 if (!shr)
2449 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2450
2451 its_write_baser(its, baser, val);
2452 tmp = baser->val;
2453
2454 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2455 /*
2456 * Shareability didn't stick. Just use
2457 * whatever the read reported, which is likely
2458 * to be the only thing this redistributor
2459 * supports. If that's zero, make it
2460 * non-cacheable as well.
2461 */
2462 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2463 if (!shr)
2464 cache = GITS_BASER_nC;
2465
2466 goto retry_baser;
2467 }
2468
2469 if (val != tmp) {
2470 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2471 &its->phys_base, its_base_type_string[type],
2472 val, tmp);
2473 its_free_pages(base, order);
2474 return -ENXIO;
2475 }
2476
2477 baser->order = order;
2478 baser->base = base;
2479 baser->psz = psz;
2480 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2481
2482 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2483 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2484 its_base_type_string[type],
2485 (unsigned long)virt_to_phys(base),
2486 indirect ? "indirect" : "flat", (int)esz,
2487 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2488
2489 return 0;
2490}
2491
2492static bool its_parse_indirect_baser(struct its_node *its,
2493 struct its_baser *baser,
2494 u32 *order, u32 ids)
2495{
2496 u64 tmp = its_read_baser(its, baser);
2497 u64 type = GITS_BASER_TYPE(tmp);
2498 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2499 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2500 u32 new_order = *order;
2501 u32 psz = baser->psz;
2502 bool indirect = false;
2503
2504 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2505 if ((esz << ids) > (psz * 2)) {
2506 /*
2507 * Find out whether hw supports a single or two-level table by
2508 * table by reading bit at offset '62' after writing '1' to it.
2509 */
2510 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2511 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2512
2513 if (indirect) {
2514 /*
2515 * The size of the lvl2 table is equal to ITS page size
2516 * which is 'psz'. For computing lvl1 table size,
2517 * subtract ID bits that sparse lvl2 table from 'ids'
2518 * which is reported by ITS hardware times lvl1 table
2519 * entry size.
2520 */
2521 ids -= ilog2(psz / (int)esz);
2522 esz = GITS_LVL1_ENTRY_SIZE;
2523 }
2524 }
2525
2526 /*
2527 * Allocate as many entries as required to fit the
2528 * range of device IDs that the ITS can grok... The ID
2529 * space being incredibly sparse, this results in a
2530 * massive waste of memory if two-level device table
2531 * feature is not supported by hardware.
2532 */
2533 new_order = max_t(u32, get_order(esz << ids), new_order);
2534 if (new_order > MAX_PAGE_ORDER) {
2535 new_order = MAX_PAGE_ORDER;
2536 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2537 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2538 &its->phys_base, its_base_type_string[type],
2539 device_ids(its), ids);
2540 }
2541
2542 *order = new_order;
2543
2544 return indirect;
2545}
2546
2547static u32 compute_common_aff(u64 val)
2548{
2549 u32 aff, clpiaff;
2550
2551 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2552 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2553
2554 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2555}
2556
2557static u32 compute_its_aff(struct its_node *its)
2558{
2559 u64 val;
2560 u32 svpet;
2561
2562 /*
2563 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2564 * the resulting affinity. We then use that to see if this match
2565 * our own affinity.
2566 */
2567 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2568 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2569 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2570 return compute_common_aff(val);
2571}
2572
2573static struct its_node *find_sibling_its(struct its_node *cur_its)
2574{
2575 struct its_node *its;
2576 u32 aff;
2577
2578 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2579 return NULL;
2580
2581 aff = compute_its_aff(cur_its);
2582
2583 list_for_each_entry(its, &its_nodes, entry) {
2584 u64 baser;
2585
2586 if (!is_v4_1(its) || its == cur_its)
2587 continue;
2588
2589 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2590 continue;
2591
2592 if (aff != compute_its_aff(its))
2593 continue;
2594
2595 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2596 baser = its->tables[2].val;
2597 if (!(baser & GITS_BASER_VALID))
2598 continue;
2599
2600 return its;
2601 }
2602
2603 return NULL;
2604}
2605
2606static void its_free_tables(struct its_node *its)
2607{
2608 int i;
2609
2610 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2611 if (its->tables[i].base) {
2612 its_free_pages(its->tables[i].base, its->tables[i].order);
2613 its->tables[i].base = NULL;
2614 }
2615 }
2616}
2617
2618static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2619{
2620 u64 psz = SZ_64K;
2621
2622 while (psz) {
2623 u64 val, gpsz;
2624
2625 val = its_read_baser(its, baser);
2626 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2627
2628 switch (psz) {
2629 case SZ_64K:
2630 gpsz = GITS_BASER_PAGE_SIZE_64K;
2631 break;
2632 case SZ_16K:
2633 gpsz = GITS_BASER_PAGE_SIZE_16K;
2634 break;
2635 case SZ_4K:
2636 default:
2637 gpsz = GITS_BASER_PAGE_SIZE_4K;
2638 break;
2639 }
2640
2641 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2642
2643 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2644 its_write_baser(its, baser, val);
2645
2646 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2647 break;
2648
2649 switch (psz) {
2650 case SZ_64K:
2651 psz = SZ_16K;
2652 break;
2653 case SZ_16K:
2654 psz = SZ_4K;
2655 break;
2656 case SZ_4K:
2657 default:
2658 return -1;
2659 }
2660 }
2661
2662 baser->psz = psz;
2663 return 0;
2664}
2665
2666static int its_alloc_tables(struct its_node *its)
2667{
2668 u64 shr = GITS_BASER_InnerShareable;
2669 u64 cache = GITS_BASER_RaWaWb;
2670 int err, i;
2671
2672 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2673 /* erratum 24313: ignore memory access type */
2674 cache = GITS_BASER_nCnB;
2675
2676 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) {
2677 cache = GITS_BASER_nC;
2678 shr = 0;
2679 }
2680
2681 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2682 struct its_baser *baser = its->tables + i;
2683 u64 val = its_read_baser(its, baser);
2684 u64 type = GITS_BASER_TYPE(val);
2685 bool indirect = false;
2686 u32 order;
2687
2688 if (type == GITS_BASER_TYPE_NONE)
2689 continue;
2690
2691 if (its_probe_baser_psz(its, baser)) {
2692 its_free_tables(its);
2693 return -ENXIO;
2694 }
2695
2696 order = get_order(baser->psz);
2697
2698 switch (type) {
2699 case GITS_BASER_TYPE_DEVICE:
2700 indirect = its_parse_indirect_baser(its, baser, &order,
2701 device_ids(its));
2702 break;
2703
2704 case GITS_BASER_TYPE_VCPU:
2705 if (is_v4_1(its)) {
2706 struct its_node *sibling;
2707
2708 WARN_ON(i != 2);
2709 if ((sibling = find_sibling_its(its))) {
2710 *baser = sibling->tables[2];
2711 its_write_baser(its, baser, baser->val);
2712 continue;
2713 }
2714 }
2715
2716 indirect = its_parse_indirect_baser(its, baser, &order,
2717 ITS_MAX_VPEID_BITS);
2718 break;
2719 }
2720
2721 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2722 if (err < 0) {
2723 its_free_tables(its);
2724 return err;
2725 }
2726
2727 /* Update settings which will be used for next BASERn */
2728 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2729 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2730 }
2731
2732 return 0;
2733}
2734
2735static u64 inherit_vpe_l1_table_from_its(void)
2736{
2737 struct its_node *its;
2738 u64 val;
2739 u32 aff;
2740
2741 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2742 aff = compute_common_aff(val);
2743
2744 list_for_each_entry(its, &its_nodes, entry) {
2745 u64 baser, addr;
2746
2747 if (!is_v4_1(its))
2748 continue;
2749
2750 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2751 continue;
2752
2753 if (aff != compute_its_aff(its))
2754 continue;
2755
2756 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2757 baser = its->tables[2].val;
2758 if (!(baser & GITS_BASER_VALID))
2759 continue;
2760
2761 /* We have a winner! */
2762 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2763
2764 val = GICR_VPROPBASER_4_1_VALID;
2765 if (baser & GITS_BASER_INDIRECT)
2766 val |= GICR_VPROPBASER_4_1_INDIRECT;
2767 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2768 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2769 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2770 case GIC_PAGE_SIZE_64K:
2771 addr = GITS_BASER_ADDR_48_to_52(baser);
2772 break;
2773 default:
2774 addr = baser & GENMASK_ULL(47, 12);
2775 break;
2776 }
2777 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2778 if (rdists_support_shareable()) {
2779 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2780 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2781 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2782 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2783 }
2784 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2785
2786 return val;
2787 }
2788
2789 return 0;
2790}
2791
2792static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2793{
2794 u32 aff;
2795 u64 val;
2796 int cpu;
2797
2798 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2799 aff = compute_common_aff(val);
2800
2801 for_each_possible_cpu(cpu) {
2802 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2803
2804 if (!base || cpu == smp_processor_id())
2805 continue;
2806
2807 val = gic_read_typer(base + GICR_TYPER);
2808 if (aff != compute_common_aff(val))
2809 continue;
2810
2811 /*
2812 * At this point, we have a victim. This particular CPU
2813 * has already booted, and has an affinity that matches
2814 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2815 * Make sure we don't write the Z bit in that case.
2816 */
2817 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2818 val &= ~GICR_VPROPBASER_4_1_Z;
2819
2820 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2821 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2822
2823 return val;
2824 }
2825
2826 return 0;
2827}
2828
2829static bool allocate_vpe_l2_table(int cpu, u32 id)
2830{
2831 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2832 unsigned int psz, esz, idx, npg, gpsz;
2833 u64 val;
2834 struct page *page;
2835 __le64 *table;
2836
2837 if (!gic_rdists->has_rvpeid)
2838 return true;
2839
2840 /* Skip non-present CPUs */
2841 if (!base)
2842 return true;
2843
2844 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2845
2846 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2847 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2848 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2849
2850 switch (gpsz) {
2851 default:
2852 WARN_ON(1);
2853 fallthrough;
2854 case GIC_PAGE_SIZE_4K:
2855 psz = SZ_4K;
2856 break;
2857 case GIC_PAGE_SIZE_16K:
2858 psz = SZ_16K;
2859 break;
2860 case GIC_PAGE_SIZE_64K:
2861 psz = SZ_64K;
2862 break;
2863 }
2864
2865 /* Don't allow vpe_id that exceeds single, flat table limit */
2866 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2867 return (id < (npg * psz / (esz * SZ_8)));
2868
2869 /* Compute 1st level table index & check if that exceeds table limit */
2870 idx = id >> ilog2(psz / (esz * SZ_8));
2871 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2872 return false;
2873
2874 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2875
2876 /* Allocate memory for 2nd level table */
2877 if (!table[idx]) {
2878 page = its_alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2879 if (!page)
2880 return false;
2881
2882 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2883 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2884 gic_flush_dcache_to_poc(page_address(page), psz);
2885
2886 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2887
2888 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2889 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2890 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2891
2892 /* Ensure updated table contents are visible to RD hardware */
2893 dsb(sy);
2894 }
2895
2896 return true;
2897}
2898
2899static int allocate_vpe_l1_table(void)
2900{
2901 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2902 u64 val, gpsz, npg, pa;
2903 unsigned int psz = SZ_64K;
2904 unsigned int np, epp, esz;
2905 struct page *page;
2906
2907 if (!gic_rdists->has_rvpeid)
2908 return 0;
2909
2910 /*
2911 * if VPENDBASER.Valid is set, disable any previously programmed
2912 * VPE by setting PendingLast while clearing Valid. This has the
2913 * effect of making sure no doorbell will be generated and we can
2914 * then safely clear VPROPBASER.Valid.
2915 */
2916 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2917 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2918 vlpi_base + GICR_VPENDBASER);
2919
2920 /*
2921 * If we can inherit the configuration from another RD, let's do
2922 * so. Otherwise, we have to go through the allocation process. We
2923 * assume that all RDs have the exact same requirements, as
2924 * nothing will work otherwise.
2925 */
2926 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2927 if (val & GICR_VPROPBASER_4_1_VALID)
2928 goto out;
2929
2930 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2931 if (!gic_data_rdist()->vpe_table_mask)
2932 return -ENOMEM;
2933
2934 val = inherit_vpe_l1_table_from_its();
2935 if (val & GICR_VPROPBASER_4_1_VALID)
2936 goto out;
2937
2938 /* First probe the page size */
2939 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2940 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2941 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2942 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2943 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2944
2945 switch (gpsz) {
2946 default:
2947 gpsz = GIC_PAGE_SIZE_4K;
2948 fallthrough;
2949 case GIC_PAGE_SIZE_4K:
2950 psz = SZ_4K;
2951 break;
2952 case GIC_PAGE_SIZE_16K:
2953 psz = SZ_16K;
2954 break;
2955 case GIC_PAGE_SIZE_64K:
2956 psz = SZ_64K;
2957 break;
2958 }
2959
2960 /*
2961 * Start populating the register from scratch, including RO fields
2962 * (which we want to print in debug cases...)
2963 */
2964 val = 0;
2965 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2966 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2967
2968 /* How many entries per GIC page? */
2969 esz++;
2970 epp = psz / (esz * SZ_8);
2971
2972 /*
2973 * If we need more than just a single L1 page, flag the table
2974 * as indirect and compute the number of required L1 pages.
2975 */
2976 if (epp < ITS_MAX_VPEID) {
2977 int nl2;
2978
2979 val |= GICR_VPROPBASER_4_1_INDIRECT;
2980
2981 /* Number of L2 pages required to cover the VPEID space */
2982 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2983
2984 /* Number of L1 pages to point to the L2 pages */
2985 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2986 } else {
2987 npg = 1;
2988 }
2989
2990 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2991
2992 /* Right, that's the number of CPU pages we need for L1 */
2993 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2994
2995 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2996 np, npg, psz, epp, esz);
2997 page = its_alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2998 if (!page)
2999 return -ENOMEM;
3000
3001 gic_data_rdist()->vpe_l1_base = page_address(page);
3002 pa = virt_to_phys(page_address(page));
3003 WARN_ON(!IS_ALIGNED(pa, psz));
3004
3005 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
3006 if (rdists_support_shareable()) {
3007 val |= GICR_VPROPBASER_RaWb;
3008 val |= GICR_VPROPBASER_InnerShareable;
3009 }
3010 val |= GICR_VPROPBASER_4_1_Z;
3011 val |= GICR_VPROPBASER_4_1_VALID;
3012
3013out:
3014 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3015 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
3016
3017 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
3018 smp_processor_id(), val,
3019 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
3020
3021 return 0;
3022}
3023
3024static int its_alloc_collections(struct its_node *its)
3025{
3026 int i;
3027
3028 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
3029 GFP_KERNEL);
3030 if (!its->collections)
3031 return -ENOMEM;
3032
3033 for (i = 0; i < nr_cpu_ids; i++)
3034 its->collections[i].target_address = ~0ULL;
3035
3036 return 0;
3037}
3038
3039static struct page *its_allocate_pending_table(gfp_t gfp_flags)
3040{
3041 struct page *pend_page;
3042
3043 pend_page = its_alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ));
3044 if (!pend_page)
3045 return NULL;
3046
3047 /* Make sure the GIC will observe the zero-ed page */
3048 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
3049
3050 return pend_page;
3051}
3052
3053static void its_free_pending_table(struct page *pt)
3054{
3055 its_free_pages(page_address(pt), get_order(LPI_PENDBASE_SZ));
3056}
3057
3058/*
3059 * Booting with kdump and LPIs enabled is generally fine. Any other
3060 * case is wrong in the absence of firmware/EFI support.
3061 */
3062static bool enabled_lpis_allowed(void)
3063{
3064 phys_addr_t addr;
3065 u64 val;
3066
3067 /* Check whether the property table is in a reserved region */
3068 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
3069 addr = val & GENMASK_ULL(51, 12);
3070
3071 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
3072}
3073
3074static int __init allocate_lpi_tables(void)
3075{
3076 u64 val;
3077 int err, cpu;
3078
3079 /*
3080 * If LPIs are enabled while we run this from the boot CPU,
3081 * flag the RD tables as pre-allocated if the stars do align.
3082 */
3083 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
3084 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
3085 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
3086 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
3087 pr_info("GICv3: Using preallocated redistributor tables\n");
3088 }
3089
3090 err = its_setup_lpi_prop_table();
3091 if (err)
3092 return err;
3093
3094 /*
3095 * We allocate all the pending tables anyway, as we may have a
3096 * mix of RDs that have had LPIs enabled, and some that
3097 * don't. We'll free the unused ones as each CPU comes online.
3098 */
3099 for_each_possible_cpu(cpu) {
3100 struct page *pend_page;
3101
3102 pend_page = its_allocate_pending_table(GFP_NOWAIT);
3103 if (!pend_page) {
3104 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
3105 return -ENOMEM;
3106 }
3107
3108 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3109 }
3110
3111 return 0;
3112}
3113
3114static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
3115{
3116 u32 count = 1000000; /* 1s! */
3117 bool clean;
3118 u64 val;
3119
3120 do {
3121 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3122 clean = !(val & GICR_VPENDBASER_Dirty);
3123 if (!clean) {
3124 count--;
3125 cpu_relax();
3126 udelay(1);
3127 }
3128 } while (!clean && count);
3129
3130 if (unlikely(!clean))
3131 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3132
3133 return val;
3134}
3135
3136static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3137{
3138 u64 val;
3139
3140 /* Make sure we wait until the RD is done with the initial scan */
3141 val = read_vpend_dirty_clear(vlpi_base);
3142 val &= ~GICR_VPENDBASER_Valid;
3143 val &= ~clr;
3144 val |= set;
3145 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3146
3147 val = read_vpend_dirty_clear(vlpi_base);
3148 if (unlikely(val & GICR_VPENDBASER_Dirty))
3149 val |= GICR_VPENDBASER_PendingLast;
3150
3151 return val;
3152}
3153
3154static void its_cpu_init_lpis(void)
3155{
3156 void __iomem *rbase = gic_data_rdist_rd_base();
3157 struct page *pend_page;
3158 phys_addr_t paddr;
3159 u64 val, tmp;
3160
3161 if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)
3162 return;
3163
3164 val = readl_relaxed(rbase + GICR_CTLR);
3165 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3166 (val & GICR_CTLR_ENABLE_LPIS)) {
3167 /*
3168 * Check that we get the same property table on all
3169 * RDs. If we don't, this is hopeless.
3170 */
3171 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3172 paddr &= GENMASK_ULL(51, 12);
3173 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3174 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3175
3176 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3177 paddr &= GENMASK_ULL(51, 16);
3178
3179 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3180 gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED;
3181
3182 goto out;
3183 }
3184
3185 pend_page = gic_data_rdist()->pend_page;
3186 paddr = page_to_phys(pend_page);
3187
3188 /* set PROPBASE */
3189 val = (gic_rdists->prop_table_pa |
3190 GICR_PROPBASER_InnerShareable |
3191 GICR_PROPBASER_RaWaWb |
3192 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3193
3194 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3195 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3196
3197 if (!rdists_support_shareable())
3198 tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
3199
3200 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3201 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3202 /*
3203 * The HW reports non-shareable, we must
3204 * remove the cacheability attributes as
3205 * well.
3206 */
3207 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3208 GICR_PROPBASER_CACHEABILITY_MASK);
3209 val |= GICR_PROPBASER_nC;
3210 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3211 }
3212 pr_info_once("GIC: using cache flushing for LPI property table\n");
3213 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3214 }
3215
3216 /* set PENDBASE */
3217 val = (page_to_phys(pend_page) |
3218 GICR_PENDBASER_InnerShareable |
3219 GICR_PENDBASER_RaWaWb);
3220
3221 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3222 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3223
3224 if (!rdists_support_shareable())
3225 tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
3226
3227 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3228 /*
3229 * The HW reports non-shareable, we must remove the
3230 * cacheability attributes as well.
3231 */
3232 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3233 GICR_PENDBASER_CACHEABILITY_MASK);
3234 val |= GICR_PENDBASER_nC;
3235 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3236 }
3237
3238 /* Enable LPIs */
3239 val = readl_relaxed(rbase + GICR_CTLR);
3240 val |= GICR_CTLR_ENABLE_LPIS;
3241 writel_relaxed(val, rbase + GICR_CTLR);
3242
3243out:
3244 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3245 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3246
3247 /*
3248 * It's possible for CPU to receive VLPIs before it is
3249 * scheduled as a vPE, especially for the first CPU, and the
3250 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3251 * as out of range and dropped by GIC.
3252 * So we initialize IDbits to known value to avoid VLPI drop.
3253 */
3254 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3255 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3256 smp_processor_id(), val);
3257 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3258
3259 /*
3260 * Also clear Valid bit of GICR_VPENDBASER, in case some
3261 * ancient programming gets left in and has possibility of
3262 * corrupting memory.
3263 */
3264 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3265 }
3266
3267 if (allocate_vpe_l1_table()) {
3268 /*
3269 * If the allocation has failed, we're in massive trouble.
3270 * Disable direct injection, and pray that no VM was
3271 * already running...
3272 */
3273 gic_rdists->has_rvpeid = false;
3274 gic_rdists->has_vlpis = false;
3275 }
3276
3277 /* Make sure the GIC has seen the above */
3278 dsb(sy);
3279 gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED;
3280 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3281 smp_processor_id(),
3282 gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ?
3283 "reserved" : "allocated",
3284 &paddr);
3285}
3286
3287static void its_cpu_init_collection(struct its_node *its)
3288{
3289 int cpu = smp_processor_id();
3290 u64 target;
3291
3292 /* avoid cross node collections and its mapping */
3293 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3294 struct device_node *cpu_node;
3295
3296 cpu_node = of_get_cpu_node(cpu, NULL);
3297 if (its->numa_node != NUMA_NO_NODE &&
3298 its->numa_node != of_node_to_nid(cpu_node))
3299 return;
3300 }
3301
3302 /*
3303 * We now have to bind each collection to its target
3304 * redistributor.
3305 */
3306 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3307 /*
3308 * This ITS wants the physical address of the
3309 * redistributor.
3310 */
3311 target = gic_data_rdist()->phys_base;
3312 } else {
3313 /* This ITS wants a linear CPU number. */
3314 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3315 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3316 }
3317
3318 /* Perform collection mapping */
3319 its->collections[cpu].target_address = target;
3320 its->collections[cpu].col_id = cpu;
3321
3322 its_send_mapc(its, &its->collections[cpu], 1);
3323 its_send_invall(its, &its->collections[cpu]);
3324}
3325
3326static void its_cpu_init_collections(void)
3327{
3328 struct its_node *its;
3329
3330 raw_spin_lock(&its_lock);
3331
3332 list_for_each_entry(its, &its_nodes, entry)
3333 its_cpu_init_collection(its);
3334
3335 raw_spin_unlock(&its_lock);
3336}
3337
3338static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3339{
3340 struct its_device *its_dev = NULL, *tmp;
3341 unsigned long flags;
3342
3343 raw_spin_lock_irqsave(&its->lock, flags);
3344
3345 list_for_each_entry(tmp, &its->its_device_list, entry) {
3346 if (tmp->device_id == dev_id) {
3347 its_dev = tmp;
3348 break;
3349 }
3350 }
3351
3352 raw_spin_unlock_irqrestore(&its->lock, flags);
3353
3354 return its_dev;
3355}
3356
3357static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3358{
3359 int i;
3360
3361 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3362 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3363 return &its->tables[i];
3364 }
3365
3366 return NULL;
3367}
3368
3369static bool its_alloc_table_entry(struct its_node *its,
3370 struct its_baser *baser, u32 id)
3371{
3372 struct page *page;
3373 u32 esz, idx;
3374 __le64 *table;
3375
3376 /* Don't allow device id that exceeds single, flat table limit */
3377 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3378 if (!(baser->val & GITS_BASER_INDIRECT))
3379 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3380
3381 /* Compute 1st level table index & check if that exceeds table limit */
3382 idx = id >> ilog2(baser->psz / esz);
3383 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3384 return false;
3385
3386 table = baser->base;
3387
3388 /* Allocate memory for 2nd level table */
3389 if (!table[idx]) {
3390 page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3391 get_order(baser->psz));
3392 if (!page)
3393 return false;
3394
3395 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3396 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3397 gic_flush_dcache_to_poc(page_address(page), baser->psz);
3398
3399 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3400
3401 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3402 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3403 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3404
3405 /* Ensure updated table contents are visible to ITS hardware */
3406 dsb(sy);
3407 }
3408
3409 return true;
3410}
3411
3412static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3413{
3414 struct its_baser *baser;
3415
3416 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3417
3418 /* Don't allow device id that exceeds ITS hardware limit */
3419 if (!baser)
3420 return (ilog2(dev_id) < device_ids(its));
3421
3422 return its_alloc_table_entry(its, baser, dev_id);
3423}
3424
3425static bool its_alloc_vpe_table(u32 vpe_id)
3426{
3427 struct its_node *its;
3428 int cpu;
3429
3430 /*
3431 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3432 * could try and only do it on ITSs corresponding to devices
3433 * that have interrupts targeted at this VPE, but the
3434 * complexity becomes crazy (and you have tons of memory
3435 * anyway, right?).
3436 */
3437 list_for_each_entry(its, &its_nodes, entry) {
3438 struct its_baser *baser;
3439
3440 if (!is_v4(its))
3441 continue;
3442
3443 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3444 if (!baser)
3445 return false;
3446
3447 if (!its_alloc_table_entry(its, baser, vpe_id))
3448 return false;
3449 }
3450
3451 /* Non v4.1? No need to iterate RDs and go back early. */
3452 if (!gic_rdists->has_rvpeid)
3453 return true;
3454
3455 /*
3456 * Make sure the L2 tables are allocated for all copies of
3457 * the L1 table on *all* v4.1 RDs.
3458 */
3459 for_each_possible_cpu(cpu) {
3460 if (!allocate_vpe_l2_table(cpu, vpe_id))
3461 return false;
3462 }
3463
3464 return true;
3465}
3466
3467static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3468 int nvecs, bool alloc_lpis)
3469{
3470 struct its_device *dev;
3471 unsigned long *lpi_map = NULL;
3472 unsigned long flags;
3473 u16 *col_map = NULL;
3474 void *itt;
3475 int lpi_base;
3476 int nr_lpis;
3477 int nr_ites;
3478 int sz;
3479
3480 if (!its_alloc_device_table(its, dev_id))
3481 return NULL;
3482
3483 if (WARN_ON(!is_power_of_2(nvecs)))
3484 nvecs = roundup_pow_of_two(nvecs);
3485
3486 /*
3487 * Even if the device wants a single LPI, the ITT must be
3488 * sized as a power of two (and you need at least one bit...).
3489 */
3490 nr_ites = max(2, nvecs);
3491 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3492 sz = max(sz, ITS_ITT_ALIGN);
3493
3494 itt = itt_alloc_pool(its->numa_node, sz);
3495
3496 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3497
3498 if (alloc_lpis) {
3499 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3500 if (lpi_map)
3501 col_map = kcalloc(nr_lpis, sizeof(*col_map),
3502 GFP_KERNEL);
3503 } else {
3504 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3505 nr_lpis = 0;
3506 lpi_base = 0;
3507 }
3508
3509 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
3510 kfree(dev);
3511 itt_free_pool(itt, sz);
3512 bitmap_free(lpi_map);
3513 kfree(col_map);
3514 return NULL;
3515 }
3516
3517 gic_flush_dcache_to_poc(itt, sz);
3518
3519 dev->its = its;
3520 dev->itt = itt;
3521 dev->itt_sz = sz;
3522 dev->nr_ites = nr_ites;
3523 dev->event_map.lpi_map = lpi_map;
3524 dev->event_map.col_map = col_map;
3525 dev->event_map.lpi_base = lpi_base;
3526 dev->event_map.nr_lpis = nr_lpis;
3527 raw_spin_lock_init(&dev->event_map.vlpi_lock);
3528 dev->device_id = dev_id;
3529 INIT_LIST_HEAD(&dev->entry);
3530
3531 raw_spin_lock_irqsave(&its->lock, flags);
3532 list_add(&dev->entry, &its->its_device_list);
3533 raw_spin_unlock_irqrestore(&its->lock, flags);
3534
3535 /* Map device to its ITT */
3536 its_send_mapd(dev, 1);
3537
3538 return dev;
3539}
3540
3541static void its_free_device(struct its_device *its_dev)
3542{
3543 unsigned long flags;
3544
3545 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3546 list_del(&its_dev->entry);
3547 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3548 kfree(its_dev->event_map.col_map);
3549 itt_free_pool(its_dev->itt, its_dev->itt_sz);
3550 kfree(its_dev);
3551}
3552
3553static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3554{
3555 int idx;
3556
3557 /* Find a free LPI region in lpi_map and allocate them. */
3558 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3559 dev->event_map.nr_lpis,
3560 get_count_order(nvecs));
3561 if (idx < 0)
3562 return -ENOSPC;
3563
3564 *hwirq = dev->event_map.lpi_base + idx;
3565
3566 return 0;
3567}
3568
3569static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3570 int nvec, msi_alloc_info_t *info)
3571{
3572 struct its_node *its;
3573 struct its_device *its_dev;
3574 struct msi_domain_info *msi_info;
3575 u32 dev_id;
3576 int err = 0;
3577
3578 /*
3579 * We ignore "dev" entirely, and rely on the dev_id that has
3580 * been passed via the scratchpad. This limits this domain's
3581 * usefulness to upper layers that definitely know that they
3582 * are built on top of the ITS.
3583 */
3584 dev_id = info->scratchpad[0].ul;
3585
3586 msi_info = msi_get_domain_info(domain);
3587 its = msi_info->data;
3588
3589 if (!gic_rdists->has_direct_lpi &&
3590 vpe_proxy.dev &&
3591 vpe_proxy.dev->its == its &&
3592 dev_id == vpe_proxy.dev->device_id) {
3593 /* Bad luck. Get yourself a better implementation */
3594 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3595 dev_id);
3596 return -EINVAL;
3597 }
3598
3599 mutex_lock(&its->dev_alloc_lock);
3600 its_dev = its_find_device(its, dev_id);
3601 if (its_dev) {
3602 /*
3603 * We already have seen this ID, probably through
3604 * another alias (PCI bridge of some sort). No need to
3605 * create the device.
3606 */
3607 its_dev->shared = true;
3608 pr_debug("Reusing ITT for devID %x\n", dev_id);
3609 goto out;
3610 }
3611
3612 its_dev = its_create_device(its, dev_id, nvec, true);
3613 if (!its_dev) {
3614 err = -ENOMEM;
3615 goto out;
3616 }
3617
3618 if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)
3619 its_dev->shared = true;
3620
3621 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3622out:
3623 mutex_unlock(&its->dev_alloc_lock);
3624 info->scratchpad[0].ptr = its_dev;
3625 return err;
3626}
3627
3628static struct msi_domain_ops its_msi_domain_ops = {
3629 .msi_prepare = its_msi_prepare,
3630};
3631
3632static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3633 unsigned int virq,
3634 irq_hw_number_t hwirq)
3635{
3636 struct irq_fwspec fwspec;
3637
3638 if (irq_domain_get_of_node(domain->parent)) {
3639 fwspec.fwnode = domain->parent->fwnode;
3640 fwspec.param_count = 3;
3641 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3642 fwspec.param[1] = hwirq;
3643 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3644 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3645 fwspec.fwnode = domain->parent->fwnode;
3646 fwspec.param_count = 2;
3647 fwspec.param[0] = hwirq;
3648 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3649 } else {
3650 return -EINVAL;
3651 }
3652
3653 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3654}
3655
3656static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3657 unsigned int nr_irqs, void *args)
3658{
3659 msi_alloc_info_t *info = args;
3660 struct its_device *its_dev = info->scratchpad[0].ptr;
3661 struct its_node *its = its_dev->its;
3662 struct irq_data *irqd;
3663 irq_hw_number_t hwirq;
3664 int err;
3665 int i;
3666
3667 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3668 if (err)
3669 return err;
3670
3671 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3672 if (err)
3673 return err;
3674
3675 for (i = 0; i < nr_irqs; i++) {
3676 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3677 if (err)
3678 return err;
3679
3680 irq_domain_set_hwirq_and_chip(domain, virq + i,
3681 hwirq + i, &its_irq_chip, its_dev);
3682 irqd = irq_get_irq_data(virq + i);
3683 irqd_set_single_target(irqd);
3684 irqd_set_affinity_on_activate(irqd);
3685 irqd_set_resend_when_in_progress(irqd);
3686 pr_debug("ID:%d pID:%d vID:%d\n",
3687 (int)(hwirq + i - its_dev->event_map.lpi_base),
3688 (int)(hwirq + i), virq + i);
3689 }
3690
3691 return 0;
3692}
3693
3694static int its_irq_domain_activate(struct irq_domain *domain,
3695 struct irq_data *d, bool reserve)
3696{
3697 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3698 u32 event = its_get_event_id(d);
3699 int cpu;
3700
3701 cpu = its_select_cpu(d, cpu_online_mask);
3702 if (cpu < 0 || cpu >= nr_cpu_ids)
3703 return -EINVAL;
3704
3705 its_inc_lpi_count(d, cpu);
3706 its_dev->event_map.col_map[event] = cpu;
3707 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3708
3709 /* Map the GIC IRQ and event to the device */
3710 its_send_mapti(its_dev, d->hwirq, event);
3711 return 0;
3712}
3713
3714static void its_irq_domain_deactivate(struct irq_domain *domain,
3715 struct irq_data *d)
3716{
3717 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3718 u32 event = its_get_event_id(d);
3719
3720 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3721 /* Stop the delivery of interrupts */
3722 its_send_discard(its_dev, event);
3723}
3724
3725static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3726 unsigned int nr_irqs)
3727{
3728 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3729 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3730 struct its_node *its = its_dev->its;
3731 int i;
3732
3733 bitmap_release_region(its_dev->event_map.lpi_map,
3734 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3735 get_count_order(nr_irqs));
3736
3737 for (i = 0; i < nr_irqs; i++) {
3738 struct irq_data *data = irq_domain_get_irq_data(domain,
3739 virq + i);
3740 /* Nuke the entry in the domain */
3741 irq_domain_reset_irq_data(data);
3742 }
3743
3744 mutex_lock(&its->dev_alloc_lock);
3745
3746 /*
3747 * If all interrupts have been freed, start mopping the
3748 * floor. This is conditioned on the device not being shared.
3749 */
3750 if (!its_dev->shared &&
3751 bitmap_empty(its_dev->event_map.lpi_map,
3752 its_dev->event_map.nr_lpis)) {
3753 its_lpi_free(its_dev->event_map.lpi_map,
3754 its_dev->event_map.lpi_base,
3755 its_dev->event_map.nr_lpis);
3756
3757 /* Unmap device/itt */
3758 its_send_mapd(its_dev, 0);
3759 its_free_device(its_dev);
3760 }
3761
3762 mutex_unlock(&its->dev_alloc_lock);
3763
3764 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3765}
3766
3767static const struct irq_domain_ops its_domain_ops = {
3768 .select = msi_lib_irq_domain_select,
3769 .alloc = its_irq_domain_alloc,
3770 .free = its_irq_domain_free,
3771 .activate = its_irq_domain_activate,
3772 .deactivate = its_irq_domain_deactivate,
3773};
3774
3775/*
3776 * This is insane.
3777 *
3778 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3779 * likely), the only way to perform an invalidate is to use a fake
3780 * device to issue an INV command, implying that the LPI has first
3781 * been mapped to some event on that device. Since this is not exactly
3782 * cheap, we try to keep that mapping around as long as possible, and
3783 * only issue an UNMAP if we're short on available slots.
3784 *
3785 * Broken by design(tm).
3786 *
3787 * GICv4.1, on the other hand, mandates that we're able to invalidate
3788 * by writing to a MMIO register. It doesn't implement the whole of
3789 * DirectLPI, but that's good enough. And most of the time, we don't
3790 * even have to invalidate anything, as the redistributor can be told
3791 * whether to generate a doorbell or not (we thus leave it enabled,
3792 * always).
3793 */
3794static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3795{
3796 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3797 if (gic_rdists->has_rvpeid)
3798 return;
3799
3800 /* Already unmapped? */
3801 if (vpe->vpe_proxy_event == -1)
3802 return;
3803
3804 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3805 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3806
3807 /*
3808 * We don't track empty slots at all, so let's move the
3809 * next_victim pointer if we can quickly reuse that slot
3810 * instead of nuking an existing entry. Not clear that this is
3811 * always a win though, and this might just generate a ripple
3812 * effect... Let's just hope VPEs don't migrate too often.
3813 */
3814 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3815 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3816
3817 vpe->vpe_proxy_event = -1;
3818}
3819
3820static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3821{
3822 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3823 if (gic_rdists->has_rvpeid)
3824 return;
3825
3826 if (!gic_rdists->has_direct_lpi) {
3827 unsigned long flags;
3828
3829 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3830 its_vpe_db_proxy_unmap_locked(vpe);
3831 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3832 }
3833}
3834
3835static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3836{
3837 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3838 if (gic_rdists->has_rvpeid)
3839 return;
3840
3841 /* Already mapped? */
3842 if (vpe->vpe_proxy_event != -1)
3843 return;
3844
3845 /* This slot was already allocated. Kick the other VPE out. */
3846 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3847 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3848
3849 /* Map the new VPE instead */
3850 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3851 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3852 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3853
3854 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3855 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3856}
3857
3858static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3859{
3860 unsigned long flags;
3861 struct its_collection *target_col;
3862
3863 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3864 if (gic_rdists->has_rvpeid)
3865 return;
3866
3867 if (gic_rdists->has_direct_lpi) {
3868 void __iomem *rdbase;
3869
3870 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3871 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3872 wait_for_syncr(rdbase);
3873
3874 return;
3875 }
3876
3877 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3878
3879 its_vpe_db_proxy_map_locked(vpe);
3880
3881 target_col = &vpe_proxy.dev->its->collections[to];
3882 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3883 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3884
3885 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3886}
3887
3888static void its_vpe_4_1_invall_locked(int cpu, struct its_vpe *vpe)
3889{
3890 void __iomem *rdbase;
3891 u64 val;
3892
3893 val = GICR_INVALLR_V;
3894 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
3895
3896 guard(raw_spinlock)(&gic_data_rdist_cpu(cpu)->rd_lock);
3897 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
3898 gic_write_lpir(val, rdbase + GICR_INVALLR);
3899 wait_for_syncr(rdbase);
3900}
3901
3902static int its_vpe_set_affinity(struct irq_data *d,
3903 const struct cpumask *mask_val,
3904 bool force)
3905{
3906 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3907 unsigned int from, cpu = nr_cpu_ids;
3908 struct cpumask *table_mask;
3909 struct its_node *its;
3910 unsigned long flags;
3911
3912 /*
3913 * Check if we're racing against a VPE being destroyed, for
3914 * which we don't want to allow a VMOVP.
3915 */
3916 if (!atomic_read(&vpe->vmapp_count)) {
3917 if (gic_requires_eager_mapping())
3918 return -EINVAL;
3919
3920 /*
3921 * If we lazily map the VPEs, this isn't an error and
3922 * we can exit cleanly.
3923 */
3924 cpu = cpumask_first(mask_val);
3925 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3926 return IRQ_SET_MASK_OK_DONE;
3927 }
3928
3929 /*
3930 * Changing affinity is mega expensive, so let's be as lazy as
3931 * we can and only do it if we really have to. Also, if mapped
3932 * into the proxy device, we need to move the doorbell
3933 * interrupt to its new location.
3934 *
3935 * Another thing is that changing the affinity of a vPE affects
3936 * *other interrupts* such as all the vLPIs that are routed to
3937 * this vPE. This means that the irq_desc lock is not enough to
3938 * protect us, and that we must ensure nobody samples vpe->col_idx
3939 * during the update, hence the lock below which must also be
3940 * taken on any vLPI handling path that evaluates vpe->col_idx.
3941 *
3942 * Finally, we must protect ourselves against concurrent updates of
3943 * the mapping state on this VM should the ITS list be in use (see
3944 * the shortcut in its_send_vmovp() otherewise).
3945 */
3946 if (its_list_map)
3947 raw_spin_lock(&vpe->its_vm->vmapp_lock);
3948
3949 from = vpe_to_cpuid_lock(vpe, &flags);
3950 table_mask = gic_data_rdist_cpu(from)->vpe_table_mask;
3951
3952 /*
3953 * If we are offered another CPU in the same GICv4.1 ITS
3954 * affinity, pick this one. Otherwise, any CPU will do.
3955 */
3956 if (table_mask)
3957 cpu = cpumask_any_and(mask_val, table_mask);
3958 if (cpu < nr_cpu_ids) {
3959 if (cpumask_test_cpu(from, mask_val) &&
3960 cpumask_test_cpu(from, table_mask))
3961 cpu = from;
3962 } else {
3963 cpu = cpumask_first(mask_val);
3964 }
3965
3966 if (from == cpu)
3967 goto out;
3968
3969 vpe->col_idx = cpu;
3970
3971 its_send_vmovp(vpe);
3972
3973 its = find_4_1_its();
3974 if (its && its->flags & ITS_FLAGS_WORKAROUND_HISILICON_162100801)
3975 its_vpe_4_1_invall_locked(cpu, vpe);
3976
3977 its_vpe_db_proxy_move(vpe, from, cpu);
3978
3979out:
3980 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3981 vpe_to_cpuid_unlock(vpe, flags);
3982
3983 if (its_list_map)
3984 raw_spin_unlock(&vpe->its_vm->vmapp_lock);
3985
3986 return IRQ_SET_MASK_OK_DONE;
3987}
3988
3989static void its_wait_vpt_parse_complete(void)
3990{
3991 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3992 u64 val;
3993
3994 if (!gic_rdists->has_vpend_valid_dirty)
3995 return;
3996
3997 WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3998 val,
3999 !(val & GICR_VPENDBASER_Dirty),
4000 1, 500));
4001}
4002
4003static void its_vpe_schedule(struct its_vpe *vpe)
4004{
4005 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4006 u64 val;
4007
4008 /* Schedule the VPE */
4009 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
4010 GENMASK_ULL(51, 12);
4011 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
4012 if (rdists_support_shareable()) {
4013 val |= GICR_VPROPBASER_RaWb;
4014 val |= GICR_VPROPBASER_InnerShareable;
4015 }
4016 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
4017
4018 val = virt_to_phys(page_address(vpe->vpt_page)) &
4019 GENMASK_ULL(51, 16);
4020 if (rdists_support_shareable()) {
4021 val |= GICR_VPENDBASER_RaWaWb;
4022 val |= GICR_VPENDBASER_InnerShareable;
4023 }
4024 /*
4025 * There is no good way of finding out if the pending table is
4026 * empty as we can race against the doorbell interrupt very
4027 * easily. So in the end, vpe->pending_last is only an
4028 * indication that the vcpu has something pending, not one
4029 * that the pending table is empty. A good implementation
4030 * would be able to read its coarse map pretty quickly anyway,
4031 * making this a tolerable issue.
4032 */
4033 val |= GICR_VPENDBASER_PendingLast;
4034 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
4035 val |= GICR_VPENDBASER_Valid;
4036 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4037}
4038
4039static void its_vpe_deschedule(struct its_vpe *vpe)
4040{
4041 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4042 u64 val;
4043
4044 val = its_clear_vpend_valid(vlpi_base, 0, 0);
4045
4046 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
4047 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4048}
4049
4050static void its_vpe_invall(struct its_vpe *vpe)
4051{
4052 struct its_node *its;
4053
4054 guard(raw_spinlock_irqsave)(&vpe->its_vm->vmapp_lock);
4055
4056 list_for_each_entry(its, &its_nodes, entry) {
4057 if (!is_v4(its))
4058 continue;
4059
4060 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
4061 continue;
4062
4063 /*
4064 * Sending a VINVALL to a single ITS is enough, as all
4065 * we need is to reach the redistributors.
4066 */
4067 its_send_vinvall(its, vpe);
4068 return;
4069 }
4070}
4071
4072static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4073{
4074 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4075 struct its_cmd_info *info = vcpu_info;
4076
4077 switch (info->cmd_type) {
4078 case SCHEDULE_VPE:
4079 its_vpe_schedule(vpe);
4080 return 0;
4081
4082 case DESCHEDULE_VPE:
4083 its_vpe_deschedule(vpe);
4084 return 0;
4085
4086 case COMMIT_VPE:
4087 its_wait_vpt_parse_complete();
4088 return 0;
4089
4090 case INVALL_VPE:
4091 its_vpe_invall(vpe);
4092 return 0;
4093
4094 default:
4095 return -EINVAL;
4096 }
4097}
4098
4099static void its_vpe_send_cmd(struct its_vpe *vpe,
4100 void (*cmd)(struct its_device *, u32))
4101{
4102 unsigned long flags;
4103
4104 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
4105
4106 its_vpe_db_proxy_map_locked(vpe);
4107 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
4108
4109 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
4110}
4111
4112static void its_vpe_send_inv(struct irq_data *d)
4113{
4114 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4115
4116 if (gic_rdists->has_direct_lpi)
4117 __direct_lpi_inv(d, d->parent_data->hwirq);
4118 else
4119 its_vpe_send_cmd(vpe, its_send_inv);
4120}
4121
4122static void its_vpe_mask_irq(struct irq_data *d)
4123{
4124 /*
4125 * We need to unmask the LPI, which is described by the parent
4126 * irq_data. Instead of calling into the parent (which won't
4127 * exactly do the right thing, let's simply use the
4128 * parent_data pointer. Yes, I'm naughty.
4129 */
4130 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4131 its_vpe_send_inv(d);
4132}
4133
4134static void its_vpe_unmask_irq(struct irq_data *d)
4135{
4136 /* Same hack as above... */
4137 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4138 its_vpe_send_inv(d);
4139}
4140
4141static int its_vpe_set_irqchip_state(struct irq_data *d,
4142 enum irqchip_irq_state which,
4143 bool state)
4144{
4145 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4146
4147 if (which != IRQCHIP_STATE_PENDING)
4148 return -EINVAL;
4149
4150 if (gic_rdists->has_direct_lpi) {
4151 void __iomem *rdbase;
4152
4153 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
4154 if (state) {
4155 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
4156 } else {
4157 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
4158 wait_for_syncr(rdbase);
4159 }
4160 } else {
4161 if (state)
4162 its_vpe_send_cmd(vpe, its_send_int);
4163 else
4164 its_vpe_send_cmd(vpe, its_send_clear);
4165 }
4166
4167 return 0;
4168}
4169
4170static int its_vpe_retrigger(struct irq_data *d)
4171{
4172 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
4173}
4174
4175static struct irq_chip its_vpe_irq_chip = {
4176 .name = "GICv4-vpe",
4177 .irq_mask = its_vpe_mask_irq,
4178 .irq_unmask = its_vpe_unmask_irq,
4179 .irq_eoi = irq_chip_eoi_parent,
4180 .irq_set_affinity = its_vpe_set_affinity,
4181 .irq_retrigger = its_vpe_retrigger,
4182 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
4183 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
4184};
4185
4186static struct its_node *find_4_1_its(void)
4187{
4188 static struct its_node *its = NULL;
4189
4190 if (!its) {
4191 list_for_each_entry(its, &its_nodes, entry) {
4192 if (is_v4_1(its))
4193 return its;
4194 }
4195
4196 /* Oops? */
4197 its = NULL;
4198 }
4199
4200 return its;
4201}
4202
4203static void its_vpe_4_1_send_inv(struct irq_data *d)
4204{
4205 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4206 struct its_node *its;
4207
4208 /*
4209 * GICv4.1 wants doorbells to be invalidated using the
4210 * INVDB command in order to be broadcast to all RDs. Send
4211 * it to the first valid ITS, and let the HW do its magic.
4212 */
4213 its = find_4_1_its();
4214 if (its)
4215 its_send_invdb(its, vpe);
4216}
4217
4218static void its_vpe_4_1_mask_irq(struct irq_data *d)
4219{
4220 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4221 its_vpe_4_1_send_inv(d);
4222}
4223
4224static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4225{
4226 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4227 its_vpe_4_1_send_inv(d);
4228}
4229
4230static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4231 struct its_cmd_info *info)
4232{
4233 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4234 u64 val = 0;
4235
4236 /* Schedule the VPE */
4237 val |= GICR_VPENDBASER_Valid;
4238 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4239 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4240 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4241
4242 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4243}
4244
4245static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4246 struct its_cmd_info *info)
4247{
4248 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4249 u64 val;
4250
4251 if (info->req_db) {
4252 unsigned long flags;
4253
4254 /*
4255 * vPE is going to block: make the vPE non-resident with
4256 * PendingLast clear and DB set. The GIC guarantees that if
4257 * we read-back PendingLast clear, then a doorbell will be
4258 * delivered when an interrupt comes.
4259 *
4260 * Note the locking to deal with the concurrent update of
4261 * pending_last from the doorbell interrupt handler that can
4262 * run concurrently.
4263 */
4264 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4265 val = its_clear_vpend_valid(vlpi_base,
4266 GICR_VPENDBASER_PendingLast,
4267 GICR_VPENDBASER_4_1_DB);
4268 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4269 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4270 } else {
4271 /*
4272 * We're not blocking, so just make the vPE non-resident
4273 * with PendingLast set, indicating that we'll be back.
4274 */
4275 val = its_clear_vpend_valid(vlpi_base,
4276 0,
4277 GICR_VPENDBASER_PendingLast);
4278 vpe->pending_last = true;
4279 }
4280}
4281
4282static void its_vpe_4_1_invall(struct its_vpe *vpe)
4283{
4284 unsigned long flags;
4285 int cpu;
4286
4287 /* Target the redistributor this vPE is currently known on */
4288 cpu = vpe_to_cpuid_lock(vpe, &flags);
4289 its_vpe_4_1_invall_locked(cpu, vpe);
4290 vpe_to_cpuid_unlock(vpe, flags);
4291}
4292
4293static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4294{
4295 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4296 struct its_cmd_info *info = vcpu_info;
4297
4298 switch (info->cmd_type) {
4299 case SCHEDULE_VPE:
4300 its_vpe_4_1_schedule(vpe, info);
4301 return 0;
4302
4303 case DESCHEDULE_VPE:
4304 its_vpe_4_1_deschedule(vpe, info);
4305 return 0;
4306
4307 case COMMIT_VPE:
4308 its_wait_vpt_parse_complete();
4309 return 0;
4310
4311 case INVALL_VPE:
4312 its_vpe_4_1_invall(vpe);
4313 return 0;
4314
4315 default:
4316 return -EINVAL;
4317 }
4318}
4319
4320static struct irq_chip its_vpe_4_1_irq_chip = {
4321 .name = "GICv4.1-vpe",
4322 .irq_mask = its_vpe_4_1_mask_irq,
4323 .irq_unmask = its_vpe_4_1_unmask_irq,
4324 .irq_eoi = irq_chip_eoi_parent,
4325 .irq_set_affinity = its_vpe_set_affinity,
4326 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4327};
4328
4329static void its_configure_sgi(struct irq_data *d, bool clear)
4330{
4331 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4332 struct its_cmd_desc desc;
4333
4334 desc.its_vsgi_cmd.vpe = vpe;
4335 desc.its_vsgi_cmd.sgi = d->hwirq;
4336 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4337 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4338 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4339 desc.its_vsgi_cmd.clear = clear;
4340
4341 /*
4342 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4343 * destination VPE is mapped there. Since we map them eagerly at
4344 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4345 */
4346 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4347}
4348
4349static void its_sgi_mask_irq(struct irq_data *d)
4350{
4351 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4352
4353 vpe->sgi_config[d->hwirq].enabled = false;
4354 its_configure_sgi(d, false);
4355}
4356
4357static void its_sgi_unmask_irq(struct irq_data *d)
4358{
4359 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4360
4361 vpe->sgi_config[d->hwirq].enabled = true;
4362 its_configure_sgi(d, false);
4363}
4364
4365static int its_sgi_set_affinity(struct irq_data *d,
4366 const struct cpumask *mask_val,
4367 bool force)
4368{
4369 /*
4370 * There is no notion of affinity for virtual SGIs, at least
4371 * not on the host (since they can only be targeting a vPE).
4372 * Tell the kernel we've done whatever it asked for.
4373 */
4374 irq_data_update_effective_affinity(d, mask_val);
4375 return IRQ_SET_MASK_OK;
4376}
4377
4378static int its_sgi_set_irqchip_state(struct irq_data *d,
4379 enum irqchip_irq_state which,
4380 bool state)
4381{
4382 if (which != IRQCHIP_STATE_PENDING)
4383 return -EINVAL;
4384
4385 if (state) {
4386 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4387 struct its_node *its = find_4_1_its();
4388 u64 val;
4389
4390 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4391 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4392 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4393 } else {
4394 its_configure_sgi(d, true);
4395 }
4396
4397 return 0;
4398}
4399
4400static int its_sgi_get_irqchip_state(struct irq_data *d,
4401 enum irqchip_irq_state which, bool *val)
4402{
4403 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4404 void __iomem *base;
4405 unsigned long flags;
4406 u32 count = 1000000; /* 1s! */
4407 u32 status;
4408 int cpu;
4409
4410 if (which != IRQCHIP_STATE_PENDING)
4411 return -EINVAL;
4412
4413 /*
4414 * Locking galore! We can race against two different events:
4415 *
4416 * - Concurrent vPE affinity change: we must make sure it cannot
4417 * happen, or we'll talk to the wrong redistributor. This is
4418 * identical to what happens with vLPIs.
4419 *
4420 * - Concurrent VSGIPENDR access: As it involves accessing two
4421 * MMIO registers, this must be made atomic one way or another.
4422 */
4423 cpu = vpe_to_cpuid_lock(vpe, &flags);
4424 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4425 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4426 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4427 do {
4428 status = readl_relaxed(base + GICR_VSGIPENDR);
4429 if (!(status & GICR_VSGIPENDR_BUSY))
4430 goto out;
4431
4432 count--;
4433 if (!count) {
4434 pr_err_ratelimited("Unable to get SGI status\n");
4435 goto out;
4436 }
4437 cpu_relax();
4438 udelay(1);
4439 } while (count);
4440
4441out:
4442 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4443 vpe_to_cpuid_unlock(vpe, flags);
4444
4445 if (!count)
4446 return -ENXIO;
4447
4448 *val = !!(status & (1 << d->hwirq));
4449
4450 return 0;
4451}
4452
4453static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4454{
4455 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4456 struct its_cmd_info *info = vcpu_info;
4457
4458 switch (info->cmd_type) {
4459 case PROP_UPDATE_VSGI:
4460 vpe->sgi_config[d->hwirq].priority = info->priority;
4461 vpe->sgi_config[d->hwirq].group = info->group;
4462 its_configure_sgi(d, false);
4463 return 0;
4464
4465 default:
4466 return -EINVAL;
4467 }
4468}
4469
4470static struct irq_chip its_sgi_irq_chip = {
4471 .name = "GICv4.1-sgi",
4472 .irq_mask = its_sgi_mask_irq,
4473 .irq_unmask = its_sgi_unmask_irq,
4474 .irq_set_affinity = its_sgi_set_affinity,
4475 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4476 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
4477 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
4478};
4479
4480static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4481 unsigned int virq, unsigned int nr_irqs,
4482 void *args)
4483{
4484 struct its_vpe *vpe = args;
4485 int i;
4486
4487 /* Yes, we do want 16 SGIs */
4488 WARN_ON(nr_irqs != 16);
4489
4490 for (i = 0; i < 16; i++) {
4491 vpe->sgi_config[i].priority = 0;
4492 vpe->sgi_config[i].enabled = false;
4493 vpe->sgi_config[i].group = false;
4494
4495 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4496 &its_sgi_irq_chip, vpe);
4497 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4498 }
4499
4500 return 0;
4501}
4502
4503static void its_sgi_irq_domain_free(struct irq_domain *domain,
4504 unsigned int virq,
4505 unsigned int nr_irqs)
4506{
4507 /* Nothing to do */
4508}
4509
4510static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4511 struct irq_data *d, bool reserve)
4512{
4513 /* Write out the initial SGI configuration */
4514 its_configure_sgi(d, false);
4515 return 0;
4516}
4517
4518static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4519 struct irq_data *d)
4520{
4521 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4522
4523 /*
4524 * The VSGI command is awkward:
4525 *
4526 * - To change the configuration, CLEAR must be set to false,
4527 * leaving the pending bit unchanged.
4528 * - To clear the pending bit, CLEAR must be set to true, leaving
4529 * the configuration unchanged.
4530 *
4531 * You just can't do both at once, hence the two commands below.
4532 */
4533 vpe->sgi_config[d->hwirq].enabled = false;
4534 its_configure_sgi(d, false);
4535 its_configure_sgi(d, true);
4536}
4537
4538static const struct irq_domain_ops its_sgi_domain_ops = {
4539 .alloc = its_sgi_irq_domain_alloc,
4540 .free = its_sgi_irq_domain_free,
4541 .activate = its_sgi_irq_domain_activate,
4542 .deactivate = its_sgi_irq_domain_deactivate,
4543};
4544
4545static int its_vpe_id_alloc(void)
4546{
4547 return ida_alloc_max(&its_vpeid_ida, ITS_MAX_VPEID - 1, GFP_KERNEL);
4548}
4549
4550static void its_vpe_id_free(u16 id)
4551{
4552 ida_free(&its_vpeid_ida, id);
4553}
4554
4555static int its_vpe_init(struct its_vpe *vpe)
4556{
4557 struct page *vpt_page;
4558 int vpe_id;
4559
4560 /* Allocate vpe_id */
4561 vpe_id = its_vpe_id_alloc();
4562 if (vpe_id < 0)
4563 return vpe_id;
4564
4565 /* Allocate VPT */
4566 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4567 if (!vpt_page) {
4568 its_vpe_id_free(vpe_id);
4569 return -ENOMEM;
4570 }
4571
4572 if (!its_alloc_vpe_table(vpe_id)) {
4573 its_vpe_id_free(vpe_id);
4574 its_free_pending_table(vpt_page);
4575 return -ENOMEM;
4576 }
4577
4578 raw_spin_lock_init(&vpe->vpe_lock);
4579 vpe->vpe_id = vpe_id;
4580 vpe->vpt_page = vpt_page;
4581 atomic_set(&vpe->vmapp_count, 0);
4582 if (!gic_rdists->has_rvpeid)
4583 vpe->vpe_proxy_event = -1;
4584
4585 return 0;
4586}
4587
4588static void its_vpe_teardown(struct its_vpe *vpe)
4589{
4590 its_vpe_db_proxy_unmap(vpe);
4591 its_vpe_id_free(vpe->vpe_id);
4592 its_free_pending_table(vpe->vpt_page);
4593}
4594
4595static void its_vpe_irq_domain_free(struct irq_domain *domain,
4596 unsigned int virq,
4597 unsigned int nr_irqs)
4598{
4599 struct its_vm *vm = domain->host_data;
4600 int i;
4601
4602 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4603
4604 for (i = 0; i < nr_irqs; i++) {
4605 struct irq_data *data = irq_domain_get_irq_data(domain,
4606 virq + i);
4607 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4608
4609 BUG_ON(vm != vpe->its_vm);
4610
4611 clear_bit(data->hwirq, vm->db_bitmap);
4612 its_vpe_teardown(vpe);
4613 irq_domain_reset_irq_data(data);
4614 }
4615
4616 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4617 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4618 its_free_prop_table(vm->vprop_page);
4619 }
4620}
4621
4622static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4623 unsigned int nr_irqs, void *args)
4624{
4625 struct irq_chip *irqchip = &its_vpe_irq_chip;
4626 struct its_vm *vm = args;
4627 unsigned long *bitmap;
4628 struct page *vprop_page;
4629 int base, nr_ids, i, err = 0;
4630
4631 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4632 if (!bitmap)
4633 return -ENOMEM;
4634
4635 if (nr_ids < nr_irqs) {
4636 its_lpi_free(bitmap, base, nr_ids);
4637 return -ENOMEM;
4638 }
4639
4640 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4641 if (!vprop_page) {
4642 its_lpi_free(bitmap, base, nr_ids);
4643 return -ENOMEM;
4644 }
4645
4646 vm->db_bitmap = bitmap;
4647 vm->db_lpi_base = base;
4648 vm->nr_db_lpis = nr_ids;
4649 vm->vprop_page = vprop_page;
4650 raw_spin_lock_init(&vm->vmapp_lock);
4651
4652 if (gic_rdists->has_rvpeid)
4653 irqchip = &its_vpe_4_1_irq_chip;
4654
4655 for (i = 0; i < nr_irqs; i++) {
4656 vm->vpes[i]->vpe_db_lpi = base + i;
4657 err = its_vpe_init(vm->vpes[i]);
4658 if (err)
4659 break;
4660 err = its_irq_gic_domain_alloc(domain, virq + i,
4661 vm->vpes[i]->vpe_db_lpi);
4662 if (err)
4663 break;
4664 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4665 irqchip, vm->vpes[i]);
4666 set_bit(i, bitmap);
4667 irqd_set_resend_when_in_progress(irq_get_irq_data(virq + i));
4668 }
4669
4670 if (err)
4671 its_vpe_irq_domain_free(domain, virq, i);
4672
4673 return err;
4674}
4675
4676static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4677 struct irq_data *d, bool reserve)
4678{
4679 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4680 struct its_node *its;
4681
4682 /* Map the VPE to the first possible CPU */
4683 vpe->col_idx = cpumask_first(cpu_online_mask);
4684 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4685
4686 /*
4687 * If we use the list map, we issue VMAPP on demand... Unless
4688 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4689 * so that VSGIs can work.
4690 */
4691 if (!gic_requires_eager_mapping())
4692 return 0;
4693
4694 list_for_each_entry(its, &its_nodes, entry) {
4695 if (!is_v4(its))
4696 continue;
4697
4698 its_send_vmapp(its, vpe, true);
4699 its_send_vinvall(its, vpe);
4700 }
4701
4702 return 0;
4703}
4704
4705static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4706 struct irq_data *d)
4707{
4708 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4709 struct its_node *its;
4710
4711 /*
4712 * If we use the list map on GICv4.0, we unmap the VPE once no
4713 * VLPIs are associated with the VM.
4714 */
4715 if (!gic_requires_eager_mapping())
4716 return;
4717
4718 list_for_each_entry(its, &its_nodes, entry) {
4719 if (!is_v4(its))
4720 continue;
4721
4722 its_send_vmapp(its, vpe, false);
4723 }
4724
4725 /*
4726 * There may be a direct read to the VPT after unmapping the
4727 * vPE, to guarantee the validity of this, we make the VPT
4728 * memory coherent with the CPU caches here.
4729 */
4730 if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))
4731 gic_flush_dcache_to_poc(page_address(vpe->vpt_page),
4732 LPI_PENDBASE_SZ);
4733}
4734
4735static const struct irq_domain_ops its_vpe_domain_ops = {
4736 .alloc = its_vpe_irq_domain_alloc,
4737 .free = its_vpe_irq_domain_free,
4738 .activate = its_vpe_irq_domain_activate,
4739 .deactivate = its_vpe_irq_domain_deactivate,
4740};
4741
4742static int its_force_quiescent(void __iomem *base)
4743{
4744 u32 count = 1000000; /* 1s */
4745 u32 val;
4746
4747 val = readl_relaxed(base + GITS_CTLR);
4748 /*
4749 * GIC architecture specification requires the ITS to be both
4750 * disabled and quiescent for writes to GITS_BASER<n> or
4751 * GITS_CBASER to not have UNPREDICTABLE results.
4752 */
4753 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4754 return 0;
4755
4756 /* Disable the generation of all interrupts to this ITS */
4757 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4758 writel_relaxed(val, base + GITS_CTLR);
4759
4760 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4761 while (1) {
4762 val = readl_relaxed(base + GITS_CTLR);
4763 if (val & GITS_CTLR_QUIESCENT)
4764 return 0;
4765
4766 count--;
4767 if (!count)
4768 return -EBUSY;
4769
4770 cpu_relax();
4771 udelay(1);
4772 }
4773}
4774
4775static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4776{
4777 struct its_node *its = data;
4778
4779 /* erratum 22375: only alloc 8MB table size (20 bits) */
4780 its->typer &= ~GITS_TYPER_DEVBITS;
4781 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4782 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4783
4784 return true;
4785}
4786
4787static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4788{
4789 struct its_node *its = data;
4790
4791 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4792
4793 return true;
4794}
4795
4796static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4797{
4798 struct its_node *its = data;
4799
4800 /* On QDF2400, the size of the ITE is 16Bytes */
4801 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4802 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4803
4804 return true;
4805}
4806
4807static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4808{
4809 struct its_node *its = its_dev->its;
4810
4811 /*
4812 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4813 * which maps 32-bit writes targeted at a separate window of
4814 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4815 * with device ID taken from bits [device_id_bits + 1:2] of
4816 * the window offset.
4817 */
4818 return its->pre_its_base + (its_dev->device_id << 2);
4819}
4820
4821static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4822{
4823 struct its_node *its = data;
4824 u32 pre_its_window[2];
4825 u32 ids;
4826
4827 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4828 "socionext,synquacer-pre-its",
4829 pre_its_window,
4830 ARRAY_SIZE(pre_its_window))) {
4831
4832 its->pre_its_base = pre_its_window[0];
4833 its->get_msi_base = its_irq_get_msi_base_pre_its;
4834
4835 ids = ilog2(pre_its_window[1]) - 2;
4836 if (device_ids(its) > ids) {
4837 its->typer &= ~GITS_TYPER_DEVBITS;
4838 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4839 }
4840
4841 /* the pre-ITS breaks isolation, so disable MSI remapping */
4842 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI;
4843 return true;
4844 }
4845 return false;
4846}
4847
4848static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4849{
4850 struct its_node *its = data;
4851
4852 /*
4853 * Hip07 insists on using the wrong address for the VLPI
4854 * page. Trick it into doing the right thing...
4855 */
4856 its->vlpi_redist_offset = SZ_128K;
4857 return true;
4858}
4859
4860static bool __maybe_unused its_enable_rk3588001(void *data)
4861{
4862 struct its_node *its = data;
4863
4864 if (!of_machine_is_compatible("rockchip,rk3588") &&
4865 !of_machine_is_compatible("rockchip,rk3588s"))
4866 return false;
4867
4868 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
4869 gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;
4870
4871 return true;
4872}
4873
4874static bool its_set_non_coherent(void *data)
4875{
4876 struct its_node *its = data;
4877
4878 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
4879 return true;
4880}
4881
4882static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)
4883{
4884 struct its_node *its = data;
4885
4886 its->flags |= ITS_FLAGS_WORKAROUND_HISILICON_162100801;
4887 return true;
4888}
4889
4890static const struct gic_quirk its_quirks[] = {
4891#ifdef CONFIG_CAVIUM_ERRATUM_22375
4892 {
4893 .desc = "ITS: Cavium errata 22375, 24313",
4894 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4895 .mask = 0xffff0fff,
4896 .init = its_enable_quirk_cavium_22375,
4897 },
4898#endif
4899#ifdef CONFIG_CAVIUM_ERRATUM_23144
4900 {
4901 .desc = "ITS: Cavium erratum 23144",
4902 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4903 .mask = 0xffff0fff,
4904 .init = its_enable_quirk_cavium_23144,
4905 },
4906#endif
4907#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4908 {
4909 .desc = "ITS: QDF2400 erratum 0065",
4910 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4911 .mask = 0xffffffff,
4912 .init = its_enable_quirk_qdf2400_e0065,
4913 },
4914#endif
4915#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4916 {
4917 /*
4918 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4919 * implementation, but with a 'pre-ITS' added that requires
4920 * special handling in software.
4921 */
4922 .desc = "ITS: Socionext Synquacer pre-ITS",
4923 .iidr = 0x0001143b,
4924 .mask = 0xffffffff,
4925 .init = its_enable_quirk_socionext_synquacer,
4926 },
4927#endif
4928#ifdef CONFIG_HISILICON_ERRATUM_161600802
4929 {
4930 .desc = "ITS: Hip07 erratum 161600802",
4931 .iidr = 0x00000004,
4932 .mask = 0xffffffff,
4933 .init = its_enable_quirk_hip07_161600802,
4934 },
4935#endif
4936#ifdef CONFIG_HISILICON_ERRATUM_162100801
4937 {
4938 .desc = "ITS: Hip09 erratum 162100801",
4939 .iidr = 0x00051736,
4940 .mask = 0xffffffff,
4941 .init = its_enable_quirk_hip09_162100801,
4942 },
4943#endif
4944#ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
4945 {
4946 .desc = "ITS: Rockchip erratum RK3588001",
4947 .iidr = 0x0201743b,
4948 .mask = 0xffffffff,
4949 .init = its_enable_rk3588001,
4950 },
4951#endif
4952 {
4953 .desc = "ITS: non-coherent attribute",
4954 .property = "dma-noncoherent",
4955 .init = its_set_non_coherent,
4956 },
4957 {
4958 }
4959};
4960
4961static void its_enable_quirks(struct its_node *its)
4962{
4963 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4964
4965 gic_enable_quirks(iidr, its_quirks, its);
4966
4967 if (is_of_node(its->fwnode_handle))
4968 gic_enable_of_quirks(to_of_node(its->fwnode_handle),
4969 its_quirks, its);
4970}
4971
4972static int its_save_disable(void)
4973{
4974 struct its_node *its;
4975 int err = 0;
4976
4977 raw_spin_lock(&its_lock);
4978 list_for_each_entry(its, &its_nodes, entry) {
4979 void __iomem *base;
4980
4981 base = its->base;
4982 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4983 err = its_force_quiescent(base);
4984 if (err) {
4985 pr_err("ITS@%pa: failed to quiesce: %d\n",
4986 &its->phys_base, err);
4987 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4988 goto err;
4989 }
4990
4991 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4992 }
4993
4994err:
4995 if (err) {
4996 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4997 void __iomem *base;
4998
4999 base = its->base;
5000 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
5001 }
5002 }
5003 raw_spin_unlock(&its_lock);
5004
5005 return err;
5006}
5007
5008static void its_restore_enable(void)
5009{
5010 struct its_node *its;
5011 int ret;
5012
5013 raw_spin_lock(&its_lock);
5014 list_for_each_entry(its, &its_nodes, entry) {
5015 void __iomem *base;
5016 int i;
5017
5018 base = its->base;
5019
5020 /*
5021 * Make sure that the ITS is disabled. If it fails to quiesce,
5022 * don't restore it since writing to CBASER or BASER<n>
5023 * registers is undefined according to the GIC v3 ITS
5024 * Specification.
5025 *
5026 * Firmware resuming with the ITS enabled is terminally broken.
5027 */
5028 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
5029 ret = its_force_quiescent(base);
5030 if (ret) {
5031 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
5032 &its->phys_base, ret);
5033 continue;
5034 }
5035
5036 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
5037
5038 /*
5039 * Writing CBASER resets CREADR to 0, so make CWRITER and
5040 * cmd_write line up with it.
5041 */
5042 its->cmd_write = its->cmd_base;
5043 gits_write_cwriter(0, base + GITS_CWRITER);
5044
5045 /* Restore GITS_BASER from the value cache. */
5046 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
5047 struct its_baser *baser = &its->tables[i];
5048
5049 if (!(baser->val & GITS_BASER_VALID))
5050 continue;
5051
5052 its_write_baser(its, baser, baser->val);
5053 }
5054 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
5055
5056 /*
5057 * Reinit the collection if it's stored in the ITS. This is
5058 * indicated by the col_id being less than the HCC field.
5059 * CID < HCC as specified in the GIC v3 Documentation.
5060 */
5061 if (its->collections[smp_processor_id()].col_id <
5062 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
5063 its_cpu_init_collection(its);
5064 }
5065 raw_spin_unlock(&its_lock);
5066}
5067
5068static struct syscore_ops its_syscore_ops = {
5069 .suspend = its_save_disable,
5070 .resume = its_restore_enable,
5071};
5072
5073static void __init __iomem *its_map_one(struct resource *res, int *err)
5074{
5075 void __iomem *its_base;
5076 u32 val;
5077
5078 its_base = ioremap(res->start, SZ_64K);
5079 if (!its_base) {
5080 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
5081 *err = -ENOMEM;
5082 return NULL;
5083 }
5084
5085 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
5086 if (val != 0x30 && val != 0x40) {
5087 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
5088 *err = -ENODEV;
5089 goto out_unmap;
5090 }
5091
5092 *err = its_force_quiescent(its_base);
5093 if (*err) {
5094 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
5095 goto out_unmap;
5096 }
5097
5098 return its_base;
5099
5100out_unmap:
5101 iounmap(its_base);
5102 return NULL;
5103}
5104
5105static int its_init_domain(struct its_node *its)
5106{
5107 struct irq_domain *inner_domain;
5108 struct msi_domain_info *info;
5109
5110 info = kzalloc(sizeof(*info), GFP_KERNEL);
5111 if (!info)
5112 return -ENOMEM;
5113
5114 info->ops = &its_msi_domain_ops;
5115 info->data = its;
5116
5117 inner_domain = irq_domain_create_hierarchy(its_parent,
5118 its->msi_domain_flags, 0,
5119 its->fwnode_handle, &its_domain_ops,
5120 info);
5121 if (!inner_domain) {
5122 kfree(info);
5123 return -ENOMEM;
5124 }
5125
5126 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
5127
5128 inner_domain->msi_parent_ops = &gic_v3_its_msi_parent_ops;
5129 inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
5130
5131 return 0;
5132}
5133
5134static int its_init_vpe_domain(void)
5135{
5136 struct its_node *its;
5137 u32 devid;
5138 int entries;
5139
5140 if (gic_rdists->has_direct_lpi) {
5141 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
5142 return 0;
5143 }
5144
5145 /* Any ITS will do, even if not v4 */
5146 its = list_first_entry(&its_nodes, struct its_node, entry);
5147
5148 entries = roundup_pow_of_two(nr_cpu_ids);
5149 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
5150 GFP_KERNEL);
5151 if (!vpe_proxy.vpes)
5152 return -ENOMEM;
5153
5154 /* Use the last possible DevID */
5155 devid = GENMASK(device_ids(its) - 1, 0);
5156 vpe_proxy.dev = its_create_device(its, devid, entries, false);
5157 if (!vpe_proxy.dev) {
5158 kfree(vpe_proxy.vpes);
5159 pr_err("ITS: Can't allocate GICv4 proxy device\n");
5160 return -ENOMEM;
5161 }
5162
5163 BUG_ON(entries > vpe_proxy.dev->nr_ites);
5164
5165 raw_spin_lock_init(&vpe_proxy.lock);
5166 vpe_proxy.next_victim = 0;
5167 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
5168 devid, vpe_proxy.dev->nr_ites);
5169
5170 return 0;
5171}
5172
5173static int __init its_compute_its_list_map(struct its_node *its)
5174{
5175 int its_number;
5176 u32 ctlr;
5177
5178 /*
5179 * This is assumed to be done early enough that we're
5180 * guaranteed to be single-threaded, hence no
5181 * locking. Should this change, we should address
5182 * this.
5183 */
5184 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
5185 if (its_number >= GICv4_ITS_LIST_MAX) {
5186 pr_err("ITS@%pa: No ITSList entry available!\n",
5187 &its->phys_base);
5188 return -EINVAL;
5189 }
5190
5191 ctlr = readl_relaxed(its->base + GITS_CTLR);
5192 ctlr &= ~GITS_CTLR_ITS_NUMBER;
5193 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
5194 writel_relaxed(ctlr, its->base + GITS_CTLR);
5195 ctlr = readl_relaxed(its->base + GITS_CTLR);
5196 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
5197 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
5198 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
5199 }
5200
5201 if (test_and_set_bit(its_number, &its_list_map)) {
5202 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
5203 &its->phys_base, its_number);
5204 return -EINVAL;
5205 }
5206
5207 return its_number;
5208}
5209
5210static int __init its_probe_one(struct its_node *its)
5211{
5212 u64 baser, tmp;
5213 struct page *page;
5214 u32 ctlr;
5215 int err;
5216
5217 its_enable_quirks(its);
5218
5219 if (is_v4(its)) {
5220 if (!(its->typer & GITS_TYPER_VMOVP)) {
5221 err = its_compute_its_list_map(its);
5222 if (err < 0)
5223 goto out;
5224
5225 its->list_nr = err;
5226
5227 pr_info("ITS@%pa: Using ITS number %d\n",
5228 &its->phys_base, err);
5229 } else {
5230 pr_info("ITS@%pa: Single VMOVP capable\n", &its->phys_base);
5231 }
5232
5233 if (is_v4_1(its)) {
5234 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
5235
5236 its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K);
5237 if (!its->sgir_base) {
5238 err = -ENOMEM;
5239 goto out;
5240 }
5241
5242 its->mpidr = readl_relaxed(its->base + GITS_MPIDR);
5243
5244 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5245 &its->phys_base, its->mpidr, svpet);
5246 }
5247 }
5248
5249 page = its_alloc_pages_node(its->numa_node,
5250 GFP_KERNEL | __GFP_ZERO,
5251 get_order(ITS_CMD_QUEUE_SZ));
5252 if (!page) {
5253 err = -ENOMEM;
5254 goto out_unmap_sgir;
5255 }
5256 its->cmd_base = (void *)page_address(page);
5257 its->cmd_write = its->cmd_base;
5258
5259 err = its_alloc_tables(its);
5260 if (err)
5261 goto out_free_cmd;
5262
5263 err = its_alloc_collections(its);
5264 if (err)
5265 goto out_free_tables;
5266
5267 baser = (virt_to_phys(its->cmd_base) |
5268 GITS_CBASER_RaWaWb |
5269 GITS_CBASER_InnerShareable |
5270 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5271 GITS_CBASER_VALID);
5272
5273 gits_write_cbaser(baser, its->base + GITS_CBASER);
5274 tmp = gits_read_cbaser(its->base + GITS_CBASER);
5275
5276 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
5277 tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
5278
5279 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5280 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5281 /*
5282 * The HW reports non-shareable, we must
5283 * remove the cacheability attributes as
5284 * well.
5285 */
5286 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5287 GITS_CBASER_CACHEABILITY_MASK);
5288 baser |= GITS_CBASER_nC;
5289 gits_write_cbaser(baser, its->base + GITS_CBASER);
5290 }
5291 pr_info("ITS: using cache flushing for cmd queue\n");
5292 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5293 }
5294
5295 gits_write_cwriter(0, its->base + GITS_CWRITER);
5296 ctlr = readl_relaxed(its->base + GITS_CTLR);
5297 ctlr |= GITS_CTLR_ENABLE;
5298 if (is_v4(its))
5299 ctlr |= GITS_CTLR_ImDe;
5300 writel_relaxed(ctlr, its->base + GITS_CTLR);
5301
5302 err = its_init_domain(its);
5303 if (err)
5304 goto out_free_tables;
5305
5306 raw_spin_lock(&its_lock);
5307 list_add(&its->entry, &its_nodes);
5308 raw_spin_unlock(&its_lock);
5309
5310 return 0;
5311
5312out_free_tables:
5313 its_free_tables(its);
5314out_free_cmd:
5315 its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5316out_unmap_sgir:
5317 if (its->sgir_base)
5318 iounmap(its->sgir_base);
5319out:
5320 pr_err("ITS@%pa: failed probing (%d)\n", &its->phys_base, err);
5321 return err;
5322}
5323
5324static bool gic_rdists_supports_plpis(void)
5325{
5326 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5327}
5328
5329static int redist_disable_lpis(void)
5330{
5331 void __iomem *rbase = gic_data_rdist_rd_base();
5332 u64 timeout = USEC_PER_SEC;
5333 u64 val;
5334
5335 if (!gic_rdists_supports_plpis()) {
5336 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5337 return -ENXIO;
5338 }
5339
5340 val = readl_relaxed(rbase + GICR_CTLR);
5341 if (!(val & GICR_CTLR_ENABLE_LPIS))
5342 return 0;
5343
5344 /*
5345 * If coming via a CPU hotplug event, we don't need to disable
5346 * LPIs before trying to re-enable them. They are already
5347 * configured and all is well in the world.
5348 *
5349 * If running with preallocated tables, there is nothing to do.
5350 */
5351 if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||
5352 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5353 return 0;
5354
5355 /*
5356 * From that point on, we only try to do some damage control.
5357 */
5358 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5359 smp_processor_id());
5360 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5361
5362 /* Disable LPIs */
5363 val &= ~GICR_CTLR_ENABLE_LPIS;
5364 writel_relaxed(val, rbase + GICR_CTLR);
5365
5366 /* Make sure any change to GICR_CTLR is observable by the GIC */
5367 dsb(sy);
5368
5369 /*
5370 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5371 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5372 * Error out if we time out waiting for RWP to clear.
5373 */
5374 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5375 if (!timeout) {
5376 pr_err("CPU%d: Timeout while disabling LPIs\n",
5377 smp_processor_id());
5378 return -ETIMEDOUT;
5379 }
5380 udelay(1);
5381 timeout--;
5382 }
5383
5384 /*
5385 * After it has been written to 1, it is IMPLEMENTATION
5386 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5387 * cleared to 0. Error out if clearing the bit failed.
5388 */
5389 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5390 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5391 return -EBUSY;
5392 }
5393
5394 return 0;
5395}
5396
5397int its_cpu_init(void)
5398{
5399 if (!list_empty(&its_nodes)) {
5400 int ret;
5401
5402 ret = redist_disable_lpis();
5403 if (ret)
5404 return ret;
5405
5406 its_cpu_init_lpis();
5407 its_cpu_init_collections();
5408 }
5409
5410 return 0;
5411}
5412
5413static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)
5414{
5415 cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state);
5416 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5417}
5418
5419static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,
5420 rdist_memreserve_cpuhp_cleanup_workfn);
5421
5422static int its_cpu_memreserve_lpi(unsigned int cpu)
5423{
5424 struct page *pend_page;
5425 int ret = 0;
5426
5427 /* This gets to run exactly once per CPU */
5428 if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)
5429 return 0;
5430
5431 pend_page = gic_data_rdist()->pend_page;
5432 if (WARN_ON(!pend_page)) {
5433 ret = -ENOMEM;
5434 goto out;
5435 }
5436 /*
5437 * If the pending table was pre-programmed, free the memory we
5438 * preemptively allocated. Otherwise, reserve that memory for
5439 * later kexecs.
5440 */
5441 if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {
5442 its_free_pending_table(pend_page);
5443 gic_data_rdist()->pend_page = NULL;
5444 } else {
5445 phys_addr_t paddr = page_to_phys(pend_page);
5446 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
5447 }
5448
5449out:
5450 /* Last CPU being brought up gets to issue the cleanup */
5451 if (!IS_ENABLED(CONFIG_SMP) ||
5452 cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5453 schedule_work(&rdist_memreserve_cpuhp_cleanup_work);
5454
5455 gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
5456 return ret;
5457}
5458
5459/* Mark all the BASER registers as invalid before they get reprogrammed */
5460static int __init its_reset_one(struct resource *res)
5461{
5462 void __iomem *its_base;
5463 int err, i;
5464
5465 its_base = its_map_one(res, &err);
5466 if (!its_base)
5467 return err;
5468
5469 for (i = 0; i < GITS_BASER_NR_REGS; i++)
5470 gits_write_baser(0, its_base + GITS_BASER + (i << 3));
5471
5472 iounmap(its_base);
5473 return 0;
5474}
5475
5476static const struct of_device_id its_device_id[] = {
5477 { .compatible = "arm,gic-v3-its", },
5478 {},
5479};
5480
5481static struct its_node __init *its_node_init(struct resource *res,
5482 struct fwnode_handle *handle, int numa_node)
5483{
5484 void __iomem *its_base;
5485 struct its_node *its;
5486 int err;
5487
5488 its_base = its_map_one(res, &err);
5489 if (!its_base)
5490 return NULL;
5491
5492 pr_info("ITS %pR\n", res);
5493
5494 its = kzalloc(sizeof(*its), GFP_KERNEL);
5495 if (!its)
5496 goto out_unmap;
5497
5498 raw_spin_lock_init(&its->lock);
5499 mutex_init(&its->dev_alloc_lock);
5500 INIT_LIST_HEAD(&its->entry);
5501 INIT_LIST_HEAD(&its->its_device_list);
5502
5503 its->typer = gic_read_typer(its_base + GITS_TYPER);
5504 its->base = its_base;
5505 its->phys_base = res->start;
5506 its->get_msi_base = its_irq_get_msi_base;
5507 its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI;
5508
5509 its->numa_node = numa_node;
5510 its->fwnode_handle = handle;
5511
5512 return its;
5513
5514out_unmap:
5515 iounmap(its_base);
5516 return NULL;
5517}
5518
5519static void its_node_destroy(struct its_node *its)
5520{
5521 iounmap(its->base);
5522 kfree(its);
5523}
5524
5525static int __init its_of_probe(struct device_node *node)
5526{
5527 struct device_node *np;
5528 struct resource res;
5529 int err;
5530
5531 /*
5532 * Make sure *all* the ITS are reset before we probe any, as
5533 * they may be sharing memory. If any of the ITS fails to
5534 * reset, don't even try to go any further, as this could
5535 * result in something even worse.
5536 */
5537 for (np = of_find_matching_node(node, its_device_id); np;
5538 np = of_find_matching_node(np, its_device_id)) {
5539 if (!of_device_is_available(np) ||
5540 !of_property_read_bool(np, "msi-controller") ||
5541 of_address_to_resource(np, 0, &res))
5542 continue;
5543
5544 err = its_reset_one(&res);
5545 if (err)
5546 return err;
5547 }
5548
5549 for (np = of_find_matching_node(node, its_device_id); np;
5550 np = of_find_matching_node(np, its_device_id)) {
5551 struct its_node *its;
5552
5553 if (!of_device_is_available(np))
5554 continue;
5555 if (!of_property_read_bool(np, "msi-controller")) {
5556 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5557 np);
5558 continue;
5559 }
5560
5561 if (of_address_to_resource(np, 0, &res)) {
5562 pr_warn("%pOF: no regs?\n", np);
5563 continue;
5564 }
5565
5566
5567 its = its_node_init(&res, &np->fwnode, of_node_to_nid(np));
5568 if (!its)
5569 return -ENOMEM;
5570
5571 err = its_probe_one(its);
5572 if (err) {
5573 its_node_destroy(its);
5574 return err;
5575 }
5576 }
5577 return 0;
5578}
5579
5580#ifdef CONFIG_ACPI
5581
5582#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5583
5584#ifdef CONFIG_ACPI_NUMA
5585struct its_srat_map {
5586 /* numa node id */
5587 u32 numa_node;
5588 /* GIC ITS ID */
5589 u32 its_id;
5590};
5591
5592static struct its_srat_map *its_srat_maps __initdata;
5593static int its_in_srat __initdata;
5594
5595static int __init acpi_get_its_numa_node(u32 its_id)
5596{
5597 int i;
5598
5599 for (i = 0; i < its_in_srat; i++) {
5600 if (its_id == its_srat_maps[i].its_id)
5601 return its_srat_maps[i].numa_node;
5602 }
5603 return NUMA_NO_NODE;
5604}
5605
5606static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5607 const unsigned long end)
5608{
5609 return 0;
5610}
5611
5612static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5613 const unsigned long end)
5614{
5615 int node;
5616 struct acpi_srat_gic_its_affinity *its_affinity;
5617
5618 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5619 if (!its_affinity)
5620 return -EINVAL;
5621
5622 if (its_affinity->header.length < sizeof(*its_affinity)) {
5623 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5624 its_affinity->header.length);
5625 return -EINVAL;
5626 }
5627
5628 /*
5629 * Note that in theory a new proximity node could be created by this
5630 * entry as it is an SRAT resource allocation structure.
5631 * We do not currently support doing so.
5632 */
5633 node = pxm_to_node(its_affinity->proximity_domain);
5634
5635 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5636 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5637 return 0;
5638 }
5639
5640 its_srat_maps[its_in_srat].numa_node = node;
5641 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5642 its_in_srat++;
5643 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5644 its_affinity->proximity_domain, its_affinity->its_id, node);
5645
5646 return 0;
5647}
5648
5649static void __init acpi_table_parse_srat_its(void)
5650{
5651 int count;
5652
5653 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5654 sizeof(struct acpi_table_srat),
5655 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5656 gic_acpi_match_srat_its, 0);
5657 if (count <= 0)
5658 return;
5659
5660 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5661 GFP_KERNEL);
5662 if (!its_srat_maps)
5663 return;
5664
5665 acpi_table_parse_entries(ACPI_SIG_SRAT,
5666 sizeof(struct acpi_table_srat),
5667 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5668 gic_acpi_parse_srat_its, 0);
5669}
5670
5671/* free the its_srat_maps after ITS probing */
5672static void __init acpi_its_srat_maps_free(void)
5673{
5674 kfree(its_srat_maps);
5675}
5676#else
5677static void __init acpi_table_parse_srat_its(void) { }
5678static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5679static void __init acpi_its_srat_maps_free(void) { }
5680#endif
5681
5682static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5683 const unsigned long end)
5684{
5685 struct acpi_madt_generic_translator *its_entry;
5686 struct fwnode_handle *dom_handle;
5687 struct its_node *its;
5688 struct resource res;
5689 int err;
5690
5691 its_entry = (struct acpi_madt_generic_translator *)header;
5692 memset(&res, 0, sizeof(res));
5693 res.start = its_entry->base_address;
5694 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5695 res.flags = IORESOURCE_MEM;
5696
5697 dom_handle = irq_domain_alloc_fwnode(&res.start);
5698 if (!dom_handle) {
5699 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5700 &res.start);
5701 return -ENOMEM;
5702 }
5703
5704 err = iort_register_domain_token(its_entry->translation_id, res.start,
5705 dom_handle);
5706 if (err) {
5707 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5708 &res.start, its_entry->translation_id);
5709 goto dom_err;
5710 }
5711
5712 its = its_node_init(&res, dom_handle,
5713 acpi_get_its_numa_node(its_entry->translation_id));
5714 if (!its) {
5715 err = -ENOMEM;
5716 goto node_err;
5717 }
5718
5719 if (acpi_get_madt_revision() >= 7 &&
5720 (its_entry->flags & ACPI_MADT_ITS_NON_COHERENT))
5721 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
5722
5723 err = its_probe_one(its);
5724 if (!err)
5725 return 0;
5726
5727node_err:
5728 iort_deregister_domain_token(its_entry->translation_id);
5729dom_err:
5730 irq_domain_free_fwnode(dom_handle);
5731 return err;
5732}
5733
5734static int __init its_acpi_reset(union acpi_subtable_headers *header,
5735 const unsigned long end)
5736{
5737 struct acpi_madt_generic_translator *its_entry;
5738 struct resource res;
5739
5740 its_entry = (struct acpi_madt_generic_translator *)header;
5741 res = (struct resource) {
5742 .start = its_entry->base_address,
5743 .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
5744 .flags = IORESOURCE_MEM,
5745 };
5746
5747 return its_reset_one(&res);
5748}
5749
5750static void __init its_acpi_probe(void)
5751{
5752 acpi_table_parse_srat_its();
5753 /*
5754 * Make sure *all* the ITS are reset before we probe any, as
5755 * they may be sharing memory. If any of the ITS fails to
5756 * reset, don't even try to go any further, as this could
5757 * result in something even worse.
5758 */
5759 if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5760 its_acpi_reset, 0) > 0)
5761 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5762 gic_acpi_parse_madt_its, 0);
5763 acpi_its_srat_maps_free();
5764}
5765#else
5766static void __init its_acpi_probe(void) { }
5767#endif
5768
5769int __init its_lpi_memreserve_init(void)
5770{
5771 int state;
5772
5773 if (!efi_enabled(EFI_CONFIG_TABLES))
5774 return 0;
5775
5776 if (list_empty(&its_nodes))
5777 return 0;
5778
5779 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5780 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
5781 "irqchip/arm/gicv3/memreserve:online",
5782 its_cpu_memreserve_lpi,
5783 NULL);
5784 if (state < 0)
5785 return state;
5786
5787 gic_rdists->cpuhp_memreserve_state = state;
5788
5789 return 0;
5790}
5791
5792int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5793 struct irq_domain *parent_domain, u8 irq_prio)
5794{
5795 struct device_node *of_node;
5796 struct its_node *its;
5797 bool has_v4 = false;
5798 bool has_v4_1 = false;
5799 int err;
5800
5801 itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1);
5802 if (!itt_pool)
5803 return -ENOMEM;
5804
5805 gic_rdists = rdists;
5806
5807 lpi_prop_prio = irq_prio;
5808 its_parent = parent_domain;
5809 of_node = to_of_node(handle);
5810 if (of_node)
5811 its_of_probe(of_node);
5812 else
5813 its_acpi_probe();
5814
5815 if (list_empty(&its_nodes)) {
5816 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5817 return -ENXIO;
5818 }
5819
5820 err = allocate_lpi_tables();
5821 if (err)
5822 return err;
5823
5824 list_for_each_entry(its, &its_nodes, entry) {
5825 has_v4 |= is_v4(its);
5826 has_v4_1 |= is_v4_1(its);
5827 }
5828
5829 /* Don't bother with inconsistent systems */
5830 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5831 rdists->has_rvpeid = false;
5832
5833 if (has_v4 & rdists->has_vlpis) {
5834 const struct irq_domain_ops *sgi_ops;
5835
5836 if (has_v4_1)
5837 sgi_ops = &its_sgi_domain_ops;
5838 else
5839 sgi_ops = NULL;
5840
5841 if (its_init_vpe_domain() ||
5842 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5843 rdists->has_vlpis = false;
5844 pr_err("ITS: Disabling GICv4 support\n");
5845 }
5846 }
5847
5848 register_syscore_ops(&its_syscore_ops);
5849
5850 return 0;
5851}