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1/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/bitmap.h>
19#include <linux/cpu.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/log2.h>
23#include <linux/mm.h>
24#include <linux/msi.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_pci.h>
29#include <linux/of_platform.h>
30#include <linux/percpu.h>
31#include <linux/slab.h>
32
33#include <linux/irqchip.h>
34#include <linux/irqchip/arm-gic-v3.h>
35
36#include <asm/cacheflush.h>
37#include <asm/cputype.h>
38#include <asm/exception.h>
39
40#include "irq-gic-common.h"
41
42#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44
45#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46
47/*
48 * Collection structure - just an ID, and a redistributor address to
49 * ping. We use one per CPU as a bag of interrupts assigned to this
50 * CPU.
51 */
52struct its_collection {
53 u64 target_address;
54 u16 col_id;
55};
56
57/*
58 * The ITS structure - contains most of the infrastructure, with the
59 * top-level MSI domain, the command queue, the collections, and the
60 * list of devices writing to it.
61 */
62struct its_node {
63 raw_spinlock_t lock;
64 struct list_head entry;
65 void __iomem *base;
66 unsigned long phys_base;
67 struct its_cmd_block *cmd_base;
68 struct its_cmd_block *cmd_write;
69 struct {
70 void *base;
71 u32 order;
72 } tables[GITS_BASER_NR_REGS];
73 struct its_collection *collections;
74 struct list_head its_device_list;
75 u64 flags;
76 u32 ite_size;
77};
78
79#define ITS_ITT_ALIGN SZ_256
80
81/* Convert page order to size in bytes */
82#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
83
84struct event_lpi_map {
85 unsigned long *lpi_map;
86 u16 *col_map;
87 irq_hw_number_t lpi_base;
88 int nr_lpis;
89};
90
91/*
92 * The ITS view of a device - belongs to an ITS, a collection, owns an
93 * interrupt translation table, and a list of interrupts.
94 */
95struct its_device {
96 struct list_head entry;
97 struct its_node *its;
98 struct event_lpi_map event_map;
99 void *itt;
100 u32 nr_ites;
101 u32 device_id;
102};
103
104static LIST_HEAD(its_nodes);
105static DEFINE_SPINLOCK(its_lock);
106static struct rdists *gic_rdists;
107
108#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
109#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
110
111static struct its_collection *dev_event_to_col(struct its_device *its_dev,
112 u32 event)
113{
114 struct its_node *its = its_dev->its;
115
116 return its->collections + its_dev->event_map.col_map[event];
117}
118
119/*
120 * ITS command descriptors - parameters to be encoded in a command
121 * block.
122 */
123struct its_cmd_desc {
124 union {
125 struct {
126 struct its_device *dev;
127 u32 event_id;
128 } its_inv_cmd;
129
130 struct {
131 struct its_device *dev;
132 u32 event_id;
133 } its_int_cmd;
134
135 struct {
136 struct its_device *dev;
137 int valid;
138 } its_mapd_cmd;
139
140 struct {
141 struct its_collection *col;
142 int valid;
143 } its_mapc_cmd;
144
145 struct {
146 struct its_device *dev;
147 u32 phys_id;
148 u32 event_id;
149 } its_mapvi_cmd;
150
151 struct {
152 struct its_device *dev;
153 struct its_collection *col;
154 u32 event_id;
155 } its_movi_cmd;
156
157 struct {
158 struct its_device *dev;
159 u32 event_id;
160 } its_discard_cmd;
161
162 struct {
163 struct its_collection *col;
164 } its_invall_cmd;
165 };
166};
167
168/*
169 * The ITS command block, which is what the ITS actually parses.
170 */
171struct its_cmd_block {
172 u64 raw_cmd[4];
173};
174
175#define ITS_CMD_QUEUE_SZ SZ_64K
176#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
177
178typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
179 struct its_cmd_desc *);
180
181static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
182{
183 cmd->raw_cmd[0] &= ~0xffUL;
184 cmd->raw_cmd[0] |= cmd_nr;
185}
186
187static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
188{
189 cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
190 cmd->raw_cmd[0] |= ((u64)devid) << 32;
191}
192
193static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
194{
195 cmd->raw_cmd[1] &= ~0xffffffffUL;
196 cmd->raw_cmd[1] |= id;
197}
198
199static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
200{
201 cmd->raw_cmd[1] &= 0xffffffffUL;
202 cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
203}
204
205static void its_encode_size(struct its_cmd_block *cmd, u8 size)
206{
207 cmd->raw_cmd[1] &= ~0x1fUL;
208 cmd->raw_cmd[1] |= size & 0x1f;
209}
210
211static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
212{
213 cmd->raw_cmd[2] &= ~0xffffffffffffUL;
214 cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
215}
216
217static void its_encode_valid(struct its_cmd_block *cmd, int valid)
218{
219 cmd->raw_cmd[2] &= ~(1UL << 63);
220 cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
221}
222
223static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
224{
225 cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
226 cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
227}
228
229static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
230{
231 cmd->raw_cmd[2] &= ~0xffffUL;
232 cmd->raw_cmd[2] |= col;
233}
234
235static inline void its_fixup_cmd(struct its_cmd_block *cmd)
236{
237 /* Let's fixup BE commands */
238 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
239 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
240 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
241 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
242}
243
244static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
245 struct its_cmd_desc *desc)
246{
247 unsigned long itt_addr;
248 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
249
250 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
251 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
252
253 its_encode_cmd(cmd, GITS_CMD_MAPD);
254 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
255 its_encode_size(cmd, size - 1);
256 its_encode_itt(cmd, itt_addr);
257 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
258
259 its_fixup_cmd(cmd);
260
261 return NULL;
262}
263
264static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
265 struct its_cmd_desc *desc)
266{
267 its_encode_cmd(cmd, GITS_CMD_MAPC);
268 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
269 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
270 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
271
272 its_fixup_cmd(cmd);
273
274 return desc->its_mapc_cmd.col;
275}
276
277static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
278 struct its_cmd_desc *desc)
279{
280 struct its_collection *col;
281
282 col = dev_event_to_col(desc->its_mapvi_cmd.dev,
283 desc->its_mapvi_cmd.event_id);
284
285 its_encode_cmd(cmd, GITS_CMD_MAPVI);
286 its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
287 its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
288 its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
289 its_encode_collection(cmd, col->col_id);
290
291 its_fixup_cmd(cmd);
292
293 return col;
294}
295
296static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
297 struct its_cmd_desc *desc)
298{
299 struct its_collection *col;
300
301 col = dev_event_to_col(desc->its_movi_cmd.dev,
302 desc->its_movi_cmd.event_id);
303
304 its_encode_cmd(cmd, GITS_CMD_MOVI);
305 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
306 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
307 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
308
309 its_fixup_cmd(cmd);
310
311 return col;
312}
313
314static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
315 struct its_cmd_desc *desc)
316{
317 struct its_collection *col;
318
319 col = dev_event_to_col(desc->its_discard_cmd.dev,
320 desc->its_discard_cmd.event_id);
321
322 its_encode_cmd(cmd, GITS_CMD_DISCARD);
323 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
324 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
325
326 its_fixup_cmd(cmd);
327
328 return col;
329}
330
331static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
332 struct its_cmd_desc *desc)
333{
334 struct its_collection *col;
335
336 col = dev_event_to_col(desc->its_inv_cmd.dev,
337 desc->its_inv_cmd.event_id);
338
339 its_encode_cmd(cmd, GITS_CMD_INV);
340 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
341 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
342
343 its_fixup_cmd(cmd);
344
345 return col;
346}
347
348static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
349 struct its_cmd_desc *desc)
350{
351 its_encode_cmd(cmd, GITS_CMD_INVALL);
352 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
353
354 its_fixup_cmd(cmd);
355
356 return NULL;
357}
358
359static u64 its_cmd_ptr_to_offset(struct its_node *its,
360 struct its_cmd_block *ptr)
361{
362 return (ptr - its->cmd_base) * sizeof(*ptr);
363}
364
365static int its_queue_full(struct its_node *its)
366{
367 int widx;
368 int ridx;
369
370 widx = its->cmd_write - its->cmd_base;
371 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
372
373 /* This is incredibly unlikely to happen, unless the ITS locks up. */
374 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
375 return 1;
376
377 return 0;
378}
379
380static struct its_cmd_block *its_allocate_entry(struct its_node *its)
381{
382 struct its_cmd_block *cmd;
383 u32 count = 1000000; /* 1s! */
384
385 while (its_queue_full(its)) {
386 count--;
387 if (!count) {
388 pr_err_ratelimited("ITS queue not draining\n");
389 return NULL;
390 }
391 cpu_relax();
392 udelay(1);
393 }
394
395 cmd = its->cmd_write++;
396
397 /* Handle queue wrapping */
398 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
399 its->cmd_write = its->cmd_base;
400
401 return cmd;
402}
403
404static struct its_cmd_block *its_post_commands(struct its_node *its)
405{
406 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
407
408 writel_relaxed(wr, its->base + GITS_CWRITER);
409
410 return its->cmd_write;
411}
412
413static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
414{
415 /*
416 * Make sure the commands written to memory are observable by
417 * the ITS.
418 */
419 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
420 __flush_dcache_area(cmd, sizeof(*cmd));
421 else
422 dsb(ishst);
423}
424
425static void its_wait_for_range_completion(struct its_node *its,
426 struct its_cmd_block *from,
427 struct its_cmd_block *to)
428{
429 u64 rd_idx, from_idx, to_idx;
430 u32 count = 1000000; /* 1s! */
431
432 from_idx = its_cmd_ptr_to_offset(its, from);
433 to_idx = its_cmd_ptr_to_offset(its, to);
434
435 while (1) {
436 rd_idx = readl_relaxed(its->base + GITS_CREADR);
437 if (rd_idx >= to_idx || rd_idx < from_idx)
438 break;
439
440 count--;
441 if (!count) {
442 pr_err_ratelimited("ITS queue timeout\n");
443 return;
444 }
445 cpu_relax();
446 udelay(1);
447 }
448}
449
450static void its_send_single_command(struct its_node *its,
451 its_cmd_builder_t builder,
452 struct its_cmd_desc *desc)
453{
454 struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
455 struct its_collection *sync_col;
456 unsigned long flags;
457
458 raw_spin_lock_irqsave(&its->lock, flags);
459
460 cmd = its_allocate_entry(its);
461 if (!cmd) { /* We're soooooo screewed... */
462 pr_err_ratelimited("ITS can't allocate, dropping command\n");
463 raw_spin_unlock_irqrestore(&its->lock, flags);
464 return;
465 }
466 sync_col = builder(cmd, desc);
467 its_flush_cmd(its, cmd);
468
469 if (sync_col) {
470 sync_cmd = its_allocate_entry(its);
471 if (!sync_cmd) {
472 pr_err_ratelimited("ITS can't SYNC, skipping\n");
473 goto post;
474 }
475 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
476 its_encode_target(sync_cmd, sync_col->target_address);
477 its_fixup_cmd(sync_cmd);
478 its_flush_cmd(its, sync_cmd);
479 }
480
481post:
482 next_cmd = its_post_commands(its);
483 raw_spin_unlock_irqrestore(&its->lock, flags);
484
485 its_wait_for_range_completion(its, cmd, next_cmd);
486}
487
488static void its_send_inv(struct its_device *dev, u32 event_id)
489{
490 struct its_cmd_desc desc;
491
492 desc.its_inv_cmd.dev = dev;
493 desc.its_inv_cmd.event_id = event_id;
494
495 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
496}
497
498static void its_send_mapd(struct its_device *dev, int valid)
499{
500 struct its_cmd_desc desc;
501
502 desc.its_mapd_cmd.dev = dev;
503 desc.its_mapd_cmd.valid = !!valid;
504
505 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
506}
507
508static void its_send_mapc(struct its_node *its, struct its_collection *col,
509 int valid)
510{
511 struct its_cmd_desc desc;
512
513 desc.its_mapc_cmd.col = col;
514 desc.its_mapc_cmd.valid = !!valid;
515
516 its_send_single_command(its, its_build_mapc_cmd, &desc);
517}
518
519static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
520{
521 struct its_cmd_desc desc;
522
523 desc.its_mapvi_cmd.dev = dev;
524 desc.its_mapvi_cmd.phys_id = irq_id;
525 desc.its_mapvi_cmd.event_id = id;
526
527 its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
528}
529
530static void its_send_movi(struct its_device *dev,
531 struct its_collection *col, u32 id)
532{
533 struct its_cmd_desc desc;
534
535 desc.its_movi_cmd.dev = dev;
536 desc.its_movi_cmd.col = col;
537 desc.its_movi_cmd.event_id = id;
538
539 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
540}
541
542static void its_send_discard(struct its_device *dev, u32 id)
543{
544 struct its_cmd_desc desc;
545
546 desc.its_discard_cmd.dev = dev;
547 desc.its_discard_cmd.event_id = id;
548
549 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
550}
551
552static void its_send_invall(struct its_node *its, struct its_collection *col)
553{
554 struct its_cmd_desc desc;
555
556 desc.its_invall_cmd.col = col;
557
558 its_send_single_command(its, its_build_invall_cmd, &desc);
559}
560
561/*
562 * irqchip functions - assumes MSI, mostly.
563 */
564
565static inline u32 its_get_event_id(struct irq_data *d)
566{
567 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
568 return d->hwirq - its_dev->event_map.lpi_base;
569}
570
571static void lpi_set_config(struct irq_data *d, bool enable)
572{
573 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
574 irq_hw_number_t hwirq = d->hwirq;
575 u32 id = its_get_event_id(d);
576 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
577
578 if (enable)
579 *cfg |= LPI_PROP_ENABLED;
580 else
581 *cfg &= ~LPI_PROP_ENABLED;
582
583 /*
584 * Make the above write visible to the redistributors.
585 * And yes, we're flushing exactly: One. Single. Byte.
586 * Humpf...
587 */
588 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
589 __flush_dcache_area(cfg, sizeof(*cfg));
590 else
591 dsb(ishst);
592 its_send_inv(its_dev, id);
593}
594
595static void its_mask_irq(struct irq_data *d)
596{
597 lpi_set_config(d, false);
598}
599
600static void its_unmask_irq(struct irq_data *d)
601{
602 lpi_set_config(d, true);
603}
604
605static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
606 bool force)
607{
608 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
609 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
610 struct its_collection *target_col;
611 u32 id = its_get_event_id(d);
612
613 if (cpu >= nr_cpu_ids)
614 return -EINVAL;
615
616 target_col = &its_dev->its->collections[cpu];
617 its_send_movi(its_dev, target_col, id);
618 its_dev->event_map.col_map[id] = cpu;
619
620 return IRQ_SET_MASK_OK_DONE;
621}
622
623static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
624{
625 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
626 struct its_node *its;
627 u64 addr;
628
629 its = its_dev->its;
630 addr = its->phys_base + GITS_TRANSLATER;
631
632 msg->address_lo = addr & ((1UL << 32) - 1);
633 msg->address_hi = addr >> 32;
634 msg->data = its_get_event_id(d);
635}
636
637static struct irq_chip its_irq_chip = {
638 .name = "ITS",
639 .irq_mask = its_mask_irq,
640 .irq_unmask = its_unmask_irq,
641 .irq_eoi = irq_chip_eoi_parent,
642 .irq_set_affinity = its_set_affinity,
643 .irq_compose_msi_msg = its_irq_compose_msi_msg,
644};
645
646/*
647 * How we allocate LPIs:
648 *
649 * The GIC has id_bits bits for interrupt identifiers. From there, we
650 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
651 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
652 * bits to the right.
653 *
654 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
655 */
656#define IRQS_PER_CHUNK_SHIFT 5
657#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
658
659static unsigned long *lpi_bitmap;
660static u32 lpi_chunks;
661static DEFINE_SPINLOCK(lpi_lock);
662
663static int its_lpi_to_chunk(int lpi)
664{
665 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
666}
667
668static int its_chunk_to_lpi(int chunk)
669{
670 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
671}
672
673static int __init its_lpi_init(u32 id_bits)
674{
675 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
676
677 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
678 GFP_KERNEL);
679 if (!lpi_bitmap) {
680 lpi_chunks = 0;
681 return -ENOMEM;
682 }
683
684 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
685 return 0;
686}
687
688static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
689{
690 unsigned long *bitmap = NULL;
691 int chunk_id;
692 int nr_chunks;
693 int i;
694
695 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
696
697 spin_lock(&lpi_lock);
698
699 do {
700 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
701 0, nr_chunks, 0);
702 if (chunk_id < lpi_chunks)
703 break;
704
705 nr_chunks--;
706 } while (nr_chunks > 0);
707
708 if (!nr_chunks)
709 goto out;
710
711 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
712 GFP_ATOMIC);
713 if (!bitmap)
714 goto out;
715
716 for (i = 0; i < nr_chunks; i++)
717 set_bit(chunk_id + i, lpi_bitmap);
718
719 *base = its_chunk_to_lpi(chunk_id);
720 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
721
722out:
723 spin_unlock(&lpi_lock);
724
725 if (!bitmap)
726 *base = *nr_ids = 0;
727
728 return bitmap;
729}
730
731static void its_lpi_free(struct event_lpi_map *map)
732{
733 int base = map->lpi_base;
734 int nr_ids = map->nr_lpis;
735 int lpi;
736
737 spin_lock(&lpi_lock);
738
739 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
740 int chunk = its_lpi_to_chunk(lpi);
741 BUG_ON(chunk > lpi_chunks);
742 if (test_bit(chunk, lpi_bitmap)) {
743 clear_bit(chunk, lpi_bitmap);
744 } else {
745 pr_err("Bad LPI chunk %d\n", chunk);
746 }
747 }
748
749 spin_unlock(&lpi_lock);
750
751 kfree(map->lpi_map);
752 kfree(map->col_map);
753}
754
755/*
756 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
757 * deal with (one configuration byte per interrupt). PENDBASE has to
758 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
759 */
760#define LPI_PROPBASE_SZ SZ_64K
761#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
762
763/*
764 * This is how many bits of ID we need, including the useless ones.
765 */
766#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
767
768#define LPI_PROP_DEFAULT_PRIO 0xa0
769
770static int __init its_alloc_lpi_tables(void)
771{
772 phys_addr_t paddr;
773
774 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
775 get_order(LPI_PROPBASE_SZ));
776 if (!gic_rdists->prop_page) {
777 pr_err("Failed to allocate PROPBASE\n");
778 return -ENOMEM;
779 }
780
781 paddr = page_to_phys(gic_rdists->prop_page);
782 pr_info("GIC: using LPI property table @%pa\n", &paddr);
783
784 /* Priority 0xa0, Group-1, disabled */
785 memset(page_address(gic_rdists->prop_page),
786 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
787 LPI_PROPBASE_SZ);
788
789 /* Make sure the GIC will observe the written configuration */
790 __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
791
792 return 0;
793}
794
795static const char *its_base_type_string[] = {
796 [GITS_BASER_TYPE_DEVICE] = "Devices",
797 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
798 [GITS_BASER_TYPE_CPU] = "Physical CPUs",
799 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
800 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
801 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
802 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
803};
804
805static void its_free_tables(struct its_node *its)
806{
807 int i;
808
809 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
810 if (its->tables[i].base) {
811 free_pages((unsigned long)its->tables[i].base,
812 its->tables[i].order);
813 its->tables[i].base = NULL;
814 }
815 }
816}
817
818static int its_alloc_tables(const char *node_name, struct its_node *its)
819{
820 int err;
821 int i;
822 int psz = SZ_64K;
823 u64 shr = GITS_BASER_InnerShareable;
824 u64 cache;
825 u64 typer;
826 u32 ids;
827
828 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
829 /*
830 * erratum 22375: only alloc 8MB table size
831 * erratum 24313: ignore memory access type
832 */
833 cache = 0;
834 ids = 0x14; /* 20 bits, 8MB */
835 } else {
836 cache = GITS_BASER_WaWb;
837 typer = readq_relaxed(its->base + GITS_TYPER);
838 ids = GITS_TYPER_DEVBITS(typer);
839 }
840
841 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
842 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
843 u64 type = GITS_BASER_TYPE(val);
844 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
845 int order = get_order(psz);
846 int alloc_pages;
847 u64 tmp;
848 void *base;
849
850 if (type == GITS_BASER_TYPE_NONE)
851 continue;
852
853 /*
854 * Allocate as many entries as required to fit the
855 * range of device IDs that the ITS can grok... The ID
856 * space being incredibly sparse, this results in a
857 * massive waste of memory.
858 *
859 * For other tables, only allocate a single page.
860 */
861 if (type == GITS_BASER_TYPE_DEVICE) {
862 /*
863 * 'order' was initialized earlier to the default page
864 * granule of the the ITS. We can't have an allocation
865 * smaller than that. If the requested allocation
866 * is smaller, round up to the default page granule.
867 */
868 order = max(get_order((1UL << ids) * entry_size),
869 order);
870 if (order >= MAX_ORDER) {
871 order = MAX_ORDER - 1;
872 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
873 node_name, order);
874 }
875 }
876
877retry_alloc_baser:
878 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
879 if (alloc_pages > GITS_BASER_PAGES_MAX) {
880 alloc_pages = GITS_BASER_PAGES_MAX;
881 order = get_order(GITS_BASER_PAGES_MAX * psz);
882 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
883 node_name, order, alloc_pages);
884 }
885
886 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
887 if (!base) {
888 err = -ENOMEM;
889 goto out_free;
890 }
891
892 its->tables[i].base = base;
893 its->tables[i].order = order;
894
895retry_baser:
896 val = (virt_to_phys(base) |
897 (type << GITS_BASER_TYPE_SHIFT) |
898 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
899 cache |
900 shr |
901 GITS_BASER_VALID);
902
903 switch (psz) {
904 case SZ_4K:
905 val |= GITS_BASER_PAGE_SIZE_4K;
906 break;
907 case SZ_16K:
908 val |= GITS_BASER_PAGE_SIZE_16K;
909 break;
910 case SZ_64K:
911 val |= GITS_BASER_PAGE_SIZE_64K;
912 break;
913 }
914
915 val |= alloc_pages - 1;
916
917 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
918 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
919
920 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
921 /*
922 * Shareability didn't stick. Just use
923 * whatever the read reported, which is likely
924 * to be the only thing this redistributor
925 * supports. If that's zero, make it
926 * non-cacheable as well.
927 */
928 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
929 if (!shr) {
930 cache = GITS_BASER_nC;
931 __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
932 }
933 goto retry_baser;
934 }
935
936 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
937 /*
938 * Page size didn't stick. Let's try a smaller
939 * size and retry. If we reach 4K, then
940 * something is horribly wrong...
941 */
942 free_pages((unsigned long)base, order);
943 its->tables[i].base = NULL;
944
945 switch (psz) {
946 case SZ_16K:
947 psz = SZ_4K;
948 goto retry_alloc_baser;
949 case SZ_64K:
950 psz = SZ_16K;
951 goto retry_alloc_baser;
952 }
953 }
954
955 if (val != tmp) {
956 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
957 node_name, i,
958 (unsigned long) val, (unsigned long) tmp);
959 err = -ENXIO;
960 goto out_free;
961 }
962
963 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
964 (int)(PAGE_ORDER_TO_SIZE(order) / entry_size),
965 its_base_type_string[type],
966 (unsigned long)virt_to_phys(base),
967 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
968 }
969
970 return 0;
971
972out_free:
973 its_free_tables(its);
974
975 return err;
976}
977
978static int its_alloc_collections(struct its_node *its)
979{
980 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
981 GFP_KERNEL);
982 if (!its->collections)
983 return -ENOMEM;
984
985 return 0;
986}
987
988static void its_cpu_init_lpis(void)
989{
990 void __iomem *rbase = gic_data_rdist_rd_base();
991 struct page *pend_page;
992 u64 val, tmp;
993
994 /* If we didn't allocate the pending table yet, do it now */
995 pend_page = gic_data_rdist()->pend_page;
996 if (!pend_page) {
997 phys_addr_t paddr;
998 /*
999 * The pending pages have to be at least 64kB aligned,
1000 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1001 */
1002 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
1003 get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
1004 if (!pend_page) {
1005 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1006 smp_processor_id());
1007 return;
1008 }
1009
1010 /* Make sure the GIC will observe the zero-ed page */
1011 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1012
1013 paddr = page_to_phys(pend_page);
1014 pr_info("CPU%d: using LPI pending table @%pa\n",
1015 smp_processor_id(), &paddr);
1016 gic_data_rdist()->pend_page = pend_page;
1017 }
1018
1019 /* Disable LPIs */
1020 val = readl_relaxed(rbase + GICR_CTLR);
1021 val &= ~GICR_CTLR_ENABLE_LPIS;
1022 writel_relaxed(val, rbase + GICR_CTLR);
1023
1024 /*
1025 * Make sure any change to the table is observable by the GIC.
1026 */
1027 dsb(sy);
1028
1029 /* set PROPBASE */
1030 val = (page_to_phys(gic_rdists->prop_page) |
1031 GICR_PROPBASER_InnerShareable |
1032 GICR_PROPBASER_WaWb |
1033 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1034
1035 writeq_relaxed(val, rbase + GICR_PROPBASER);
1036 tmp = readq_relaxed(rbase + GICR_PROPBASER);
1037
1038 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1039 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1040 /*
1041 * The HW reports non-shareable, we must
1042 * remove the cacheability attributes as
1043 * well.
1044 */
1045 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1046 GICR_PROPBASER_CACHEABILITY_MASK);
1047 val |= GICR_PROPBASER_nC;
1048 writeq_relaxed(val, rbase + GICR_PROPBASER);
1049 }
1050 pr_info_once("GIC: using cache flushing for LPI property table\n");
1051 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1052 }
1053
1054 /* set PENDBASE */
1055 val = (page_to_phys(pend_page) |
1056 GICR_PENDBASER_InnerShareable |
1057 GICR_PENDBASER_WaWb);
1058
1059 writeq_relaxed(val, rbase + GICR_PENDBASER);
1060 tmp = readq_relaxed(rbase + GICR_PENDBASER);
1061
1062 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1063 /*
1064 * The HW reports non-shareable, we must remove the
1065 * cacheability attributes as well.
1066 */
1067 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1068 GICR_PENDBASER_CACHEABILITY_MASK);
1069 val |= GICR_PENDBASER_nC;
1070 writeq_relaxed(val, rbase + GICR_PENDBASER);
1071 }
1072
1073 /* Enable LPIs */
1074 val = readl_relaxed(rbase + GICR_CTLR);
1075 val |= GICR_CTLR_ENABLE_LPIS;
1076 writel_relaxed(val, rbase + GICR_CTLR);
1077
1078 /* Make sure the GIC has seen the above */
1079 dsb(sy);
1080}
1081
1082static void its_cpu_init_collection(void)
1083{
1084 struct its_node *its;
1085 int cpu;
1086
1087 spin_lock(&its_lock);
1088 cpu = smp_processor_id();
1089
1090 list_for_each_entry(its, &its_nodes, entry) {
1091 u64 target;
1092
1093 /*
1094 * We now have to bind each collection to its target
1095 * redistributor.
1096 */
1097 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1098 /*
1099 * This ITS wants the physical address of the
1100 * redistributor.
1101 */
1102 target = gic_data_rdist()->phys_base;
1103 } else {
1104 /*
1105 * This ITS wants a linear CPU number.
1106 */
1107 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1108 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1109 }
1110
1111 /* Perform collection mapping */
1112 its->collections[cpu].target_address = target;
1113 its->collections[cpu].col_id = cpu;
1114
1115 its_send_mapc(its, &its->collections[cpu], 1);
1116 its_send_invall(its, &its->collections[cpu]);
1117 }
1118
1119 spin_unlock(&its_lock);
1120}
1121
1122static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1123{
1124 struct its_device *its_dev = NULL, *tmp;
1125 unsigned long flags;
1126
1127 raw_spin_lock_irqsave(&its->lock, flags);
1128
1129 list_for_each_entry(tmp, &its->its_device_list, entry) {
1130 if (tmp->device_id == dev_id) {
1131 its_dev = tmp;
1132 break;
1133 }
1134 }
1135
1136 raw_spin_unlock_irqrestore(&its->lock, flags);
1137
1138 return its_dev;
1139}
1140
1141static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1142 int nvecs)
1143{
1144 struct its_device *dev;
1145 unsigned long *lpi_map;
1146 unsigned long flags;
1147 u16 *col_map = NULL;
1148 void *itt;
1149 int lpi_base;
1150 int nr_lpis;
1151 int nr_ites;
1152 int sz;
1153
1154 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1155 /*
1156 * At least one bit of EventID is being used, hence a minimum
1157 * of two entries. No, the architecture doesn't let you
1158 * express an ITT with a single entry.
1159 */
1160 nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1161 sz = nr_ites * its->ite_size;
1162 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1163 itt = kzalloc(sz, GFP_KERNEL);
1164 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1165 if (lpi_map)
1166 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1167
1168 if (!dev || !itt || !lpi_map || !col_map) {
1169 kfree(dev);
1170 kfree(itt);
1171 kfree(lpi_map);
1172 kfree(col_map);
1173 return NULL;
1174 }
1175
1176 __flush_dcache_area(itt, sz);
1177
1178 dev->its = its;
1179 dev->itt = itt;
1180 dev->nr_ites = nr_ites;
1181 dev->event_map.lpi_map = lpi_map;
1182 dev->event_map.col_map = col_map;
1183 dev->event_map.lpi_base = lpi_base;
1184 dev->event_map.nr_lpis = nr_lpis;
1185 dev->device_id = dev_id;
1186 INIT_LIST_HEAD(&dev->entry);
1187
1188 raw_spin_lock_irqsave(&its->lock, flags);
1189 list_add(&dev->entry, &its->its_device_list);
1190 raw_spin_unlock_irqrestore(&its->lock, flags);
1191
1192 /* Map device to its ITT */
1193 its_send_mapd(dev, 1);
1194
1195 return dev;
1196}
1197
1198static void its_free_device(struct its_device *its_dev)
1199{
1200 unsigned long flags;
1201
1202 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1203 list_del(&its_dev->entry);
1204 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1205 kfree(its_dev->itt);
1206 kfree(its_dev);
1207}
1208
1209static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1210{
1211 int idx;
1212
1213 idx = find_first_zero_bit(dev->event_map.lpi_map,
1214 dev->event_map.nr_lpis);
1215 if (idx == dev->event_map.nr_lpis)
1216 return -ENOSPC;
1217
1218 *hwirq = dev->event_map.lpi_base + idx;
1219 set_bit(idx, dev->event_map.lpi_map);
1220
1221 return 0;
1222}
1223
1224static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1225 int nvec, msi_alloc_info_t *info)
1226{
1227 struct its_node *its;
1228 struct its_device *its_dev;
1229 struct msi_domain_info *msi_info;
1230 u32 dev_id;
1231
1232 /*
1233 * We ignore "dev" entierely, and rely on the dev_id that has
1234 * been passed via the scratchpad. This limits this domain's
1235 * usefulness to upper layers that definitely know that they
1236 * are built on top of the ITS.
1237 */
1238 dev_id = info->scratchpad[0].ul;
1239
1240 msi_info = msi_get_domain_info(domain);
1241 its = msi_info->data;
1242
1243 its_dev = its_find_device(its, dev_id);
1244 if (its_dev) {
1245 /*
1246 * We already have seen this ID, probably through
1247 * another alias (PCI bridge of some sort). No need to
1248 * create the device.
1249 */
1250 pr_debug("Reusing ITT for devID %x\n", dev_id);
1251 goto out;
1252 }
1253
1254 its_dev = its_create_device(its, dev_id, nvec);
1255 if (!its_dev)
1256 return -ENOMEM;
1257
1258 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1259out:
1260 info->scratchpad[0].ptr = its_dev;
1261 return 0;
1262}
1263
1264static struct msi_domain_ops its_msi_domain_ops = {
1265 .msi_prepare = its_msi_prepare,
1266};
1267
1268static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1269 unsigned int virq,
1270 irq_hw_number_t hwirq)
1271{
1272 struct irq_fwspec fwspec;
1273
1274 if (irq_domain_get_of_node(domain->parent)) {
1275 fwspec.fwnode = domain->parent->fwnode;
1276 fwspec.param_count = 3;
1277 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1278 fwspec.param[1] = hwirq;
1279 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1280 } else {
1281 return -EINVAL;
1282 }
1283
1284 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1285}
1286
1287static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1288 unsigned int nr_irqs, void *args)
1289{
1290 msi_alloc_info_t *info = args;
1291 struct its_device *its_dev = info->scratchpad[0].ptr;
1292 irq_hw_number_t hwirq;
1293 int err;
1294 int i;
1295
1296 for (i = 0; i < nr_irqs; i++) {
1297 err = its_alloc_device_irq(its_dev, &hwirq);
1298 if (err)
1299 return err;
1300
1301 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1302 if (err)
1303 return err;
1304
1305 irq_domain_set_hwirq_and_chip(domain, virq + i,
1306 hwirq, &its_irq_chip, its_dev);
1307 pr_debug("ID:%d pID:%d vID:%d\n",
1308 (int)(hwirq - its_dev->event_map.lpi_base),
1309 (int) hwirq, virq + i);
1310 }
1311
1312 return 0;
1313}
1314
1315static void its_irq_domain_activate(struct irq_domain *domain,
1316 struct irq_data *d)
1317{
1318 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1319 u32 event = its_get_event_id(d);
1320
1321 /* Bind the LPI to the first possible CPU */
1322 its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1323
1324 /* Map the GIC IRQ and event to the device */
1325 its_send_mapvi(its_dev, d->hwirq, event);
1326}
1327
1328static void its_irq_domain_deactivate(struct irq_domain *domain,
1329 struct irq_data *d)
1330{
1331 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1332 u32 event = its_get_event_id(d);
1333
1334 /* Stop the delivery of interrupts */
1335 its_send_discard(its_dev, event);
1336}
1337
1338static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1339 unsigned int nr_irqs)
1340{
1341 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1342 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1343 int i;
1344
1345 for (i = 0; i < nr_irqs; i++) {
1346 struct irq_data *data = irq_domain_get_irq_data(domain,
1347 virq + i);
1348 u32 event = its_get_event_id(data);
1349
1350 /* Mark interrupt index as unused */
1351 clear_bit(event, its_dev->event_map.lpi_map);
1352
1353 /* Nuke the entry in the domain */
1354 irq_domain_reset_irq_data(data);
1355 }
1356
1357 /* If all interrupts have been freed, start mopping the floor */
1358 if (bitmap_empty(its_dev->event_map.lpi_map,
1359 its_dev->event_map.nr_lpis)) {
1360 its_lpi_free(&its_dev->event_map);
1361
1362 /* Unmap device/itt */
1363 its_send_mapd(its_dev, 0);
1364 its_free_device(its_dev);
1365 }
1366
1367 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1368}
1369
1370static const struct irq_domain_ops its_domain_ops = {
1371 .alloc = its_irq_domain_alloc,
1372 .free = its_irq_domain_free,
1373 .activate = its_irq_domain_activate,
1374 .deactivate = its_irq_domain_deactivate,
1375};
1376
1377static int its_force_quiescent(void __iomem *base)
1378{
1379 u32 count = 1000000; /* 1s */
1380 u32 val;
1381
1382 val = readl_relaxed(base + GITS_CTLR);
1383 if (val & GITS_CTLR_QUIESCENT)
1384 return 0;
1385
1386 /* Disable the generation of all interrupts to this ITS */
1387 val &= ~GITS_CTLR_ENABLE;
1388 writel_relaxed(val, base + GITS_CTLR);
1389
1390 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1391 while (1) {
1392 val = readl_relaxed(base + GITS_CTLR);
1393 if (val & GITS_CTLR_QUIESCENT)
1394 return 0;
1395
1396 count--;
1397 if (!count)
1398 return -EBUSY;
1399
1400 cpu_relax();
1401 udelay(1);
1402 }
1403}
1404
1405static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1406{
1407 struct its_node *its = data;
1408
1409 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1410}
1411
1412static const struct gic_quirk its_quirks[] = {
1413#ifdef CONFIG_CAVIUM_ERRATUM_22375
1414 {
1415 .desc = "ITS: Cavium errata 22375, 24313",
1416 .iidr = 0xa100034c, /* ThunderX pass 1.x */
1417 .mask = 0xffff0fff,
1418 .init = its_enable_quirk_cavium_22375,
1419 },
1420#endif
1421 {
1422 }
1423};
1424
1425static void its_enable_quirks(struct its_node *its)
1426{
1427 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1428
1429 gic_enable_quirks(iidr, its_quirks, its);
1430}
1431
1432static int __init its_probe(struct device_node *node,
1433 struct irq_domain *parent)
1434{
1435 struct resource res;
1436 struct its_node *its;
1437 void __iomem *its_base;
1438 struct irq_domain *inner_domain;
1439 u32 val;
1440 u64 baser, tmp;
1441 int err;
1442
1443 err = of_address_to_resource(node, 0, &res);
1444 if (err) {
1445 pr_warn("%s: no regs?\n", node->full_name);
1446 return -ENXIO;
1447 }
1448
1449 its_base = ioremap(res.start, resource_size(&res));
1450 if (!its_base) {
1451 pr_warn("%s: unable to map registers\n", node->full_name);
1452 return -ENOMEM;
1453 }
1454
1455 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1456 if (val != 0x30 && val != 0x40) {
1457 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1458 err = -ENODEV;
1459 goto out_unmap;
1460 }
1461
1462 err = its_force_quiescent(its_base);
1463 if (err) {
1464 pr_warn("%s: failed to quiesce, giving up\n",
1465 node->full_name);
1466 goto out_unmap;
1467 }
1468
1469 pr_info("ITS: %s\n", node->full_name);
1470
1471 its = kzalloc(sizeof(*its), GFP_KERNEL);
1472 if (!its) {
1473 err = -ENOMEM;
1474 goto out_unmap;
1475 }
1476
1477 raw_spin_lock_init(&its->lock);
1478 INIT_LIST_HEAD(&its->entry);
1479 INIT_LIST_HEAD(&its->its_device_list);
1480 its->base = its_base;
1481 its->phys_base = res.start;
1482 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1483
1484 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1485 if (!its->cmd_base) {
1486 err = -ENOMEM;
1487 goto out_free_its;
1488 }
1489 its->cmd_write = its->cmd_base;
1490
1491 its_enable_quirks(its);
1492
1493 err = its_alloc_tables(node->full_name, its);
1494 if (err)
1495 goto out_free_cmd;
1496
1497 err = its_alloc_collections(its);
1498 if (err)
1499 goto out_free_tables;
1500
1501 baser = (virt_to_phys(its->cmd_base) |
1502 GITS_CBASER_WaWb |
1503 GITS_CBASER_InnerShareable |
1504 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1505 GITS_CBASER_VALID);
1506
1507 writeq_relaxed(baser, its->base + GITS_CBASER);
1508 tmp = readq_relaxed(its->base + GITS_CBASER);
1509
1510 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1511 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1512 /*
1513 * The HW reports non-shareable, we must
1514 * remove the cacheability attributes as
1515 * well.
1516 */
1517 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1518 GITS_CBASER_CACHEABILITY_MASK);
1519 baser |= GITS_CBASER_nC;
1520 writeq_relaxed(baser, its->base + GITS_CBASER);
1521 }
1522 pr_info("ITS: using cache flushing for cmd queue\n");
1523 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1524 }
1525
1526 writeq_relaxed(0, its->base + GITS_CWRITER);
1527 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1528
1529 if (of_property_read_bool(node, "msi-controller")) {
1530 struct msi_domain_info *info;
1531
1532 info = kzalloc(sizeof(*info), GFP_KERNEL);
1533 if (!info) {
1534 err = -ENOMEM;
1535 goto out_free_tables;
1536 }
1537
1538 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1539 if (!inner_domain) {
1540 err = -ENOMEM;
1541 kfree(info);
1542 goto out_free_tables;
1543 }
1544
1545 inner_domain->parent = parent;
1546 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1547 info->ops = &its_msi_domain_ops;
1548 info->data = its;
1549 inner_domain->host_data = info;
1550 }
1551
1552 spin_lock(&its_lock);
1553 list_add(&its->entry, &its_nodes);
1554 spin_unlock(&its_lock);
1555
1556 return 0;
1557
1558out_free_tables:
1559 its_free_tables(its);
1560out_free_cmd:
1561 kfree(its->cmd_base);
1562out_free_its:
1563 kfree(its);
1564out_unmap:
1565 iounmap(its_base);
1566 pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1567 return err;
1568}
1569
1570static bool gic_rdists_supports_plpis(void)
1571{
1572 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1573}
1574
1575int its_cpu_init(void)
1576{
1577 if (!list_empty(&its_nodes)) {
1578 if (!gic_rdists_supports_plpis()) {
1579 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1580 return -ENXIO;
1581 }
1582 its_cpu_init_lpis();
1583 its_cpu_init_collection();
1584 }
1585
1586 return 0;
1587}
1588
1589static struct of_device_id its_device_id[] = {
1590 { .compatible = "arm,gic-v3-its", },
1591 {},
1592};
1593
1594int __init its_init(struct device_node *node, struct rdists *rdists,
1595 struct irq_domain *parent_domain)
1596{
1597 struct device_node *np;
1598
1599 for (np = of_find_matching_node(node, its_device_id); np;
1600 np = of_find_matching_node(np, its_device_id)) {
1601 its_probe(np, parent_domain);
1602 }
1603
1604 if (list_empty(&its_nodes)) {
1605 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1606 return -ENXIO;
1607 }
1608
1609 gic_rdists = rdists;
1610 its_alloc_lpi_tables();
1611 its_lpi_init(rdists->id_bits);
1612
1613 return 0;
1614}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <linux/acpi.h>
8#include <linux/acpi_iort.h>
9#include <linux/bitmap.h>
10#include <linux/cpu.h>
11#include <linux/crash_dump.h>
12#include <linux/delay.h>
13#include <linux/dma-iommu.h>
14#include <linux/efi.h>
15#include <linux/interrupt.h>
16#include <linux/irqdomain.h>
17#include <linux/list.h>
18#include <linux/log2.h>
19#include <linux/memblock.h>
20#include <linux/mm.h>
21#include <linux/msi.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/of_platform.h>
27#include <linux/percpu.h>
28#include <linux/slab.h>
29#include <linux/syscore_ops.h>
30
31#include <linux/irqchip.h>
32#include <linux/irqchip/arm-gic-v3.h>
33#include <linux/irqchip/arm-gic-v4.h>
34
35#include <asm/cputype.h>
36#include <asm/exception.h>
37
38#include "irq-gic-common.h"
39
40#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
41#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
42#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
43#define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
44
45#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
47
48static u32 lpi_id_bits;
49
50/*
51 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
52 * deal with (one configuration byte per interrupt). PENDBASE has to
53 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
54 */
55#define LPI_NRBITS lpi_id_bits
56#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
57#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
58
59#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
60
61/*
62 * Collection structure - just an ID, and a redistributor address to
63 * ping. We use one per CPU as a bag of interrupts assigned to this
64 * CPU.
65 */
66struct its_collection {
67 u64 target_address;
68 u16 col_id;
69};
70
71/*
72 * The ITS_BASER structure - contains memory information, cached
73 * value of BASER register configuration and ITS page size.
74 */
75struct its_baser {
76 void *base;
77 u64 val;
78 u32 order;
79 u32 psz;
80};
81
82struct its_device;
83
84/*
85 * The ITS structure - contains most of the infrastructure, with the
86 * top-level MSI domain, the command queue, the collections, and the
87 * list of devices writing to it.
88 *
89 * dev_alloc_lock has to be taken for device allocations, while the
90 * spinlock must be taken to parse data structures such as the device
91 * list.
92 */
93struct its_node {
94 raw_spinlock_t lock;
95 struct mutex dev_alloc_lock;
96 struct list_head entry;
97 void __iomem *base;
98 phys_addr_t phys_base;
99 struct its_cmd_block *cmd_base;
100 struct its_cmd_block *cmd_write;
101 struct its_baser tables[GITS_BASER_NR_REGS];
102 struct its_collection *collections;
103 struct fwnode_handle *fwnode_handle;
104 u64 (*get_msi_base)(struct its_device *its_dev);
105 u64 cbaser_save;
106 u32 ctlr_save;
107 struct list_head its_device_list;
108 u64 flags;
109 unsigned long list_nr;
110 u32 ite_size;
111 u32 device_ids;
112 int numa_node;
113 unsigned int msi_domain_flags;
114 u32 pre_its_base; /* for Socionext Synquacer */
115 bool is_v4;
116 int vlpi_redist_offset;
117};
118
119#define ITS_ITT_ALIGN SZ_256
120
121/* The maximum number of VPEID bits supported by VLPI commands */
122#define ITS_MAX_VPEID_BITS (16)
123#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
124
125/* Convert page order to size in bytes */
126#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
127
128struct event_lpi_map {
129 unsigned long *lpi_map;
130 u16 *col_map;
131 irq_hw_number_t lpi_base;
132 int nr_lpis;
133 struct mutex vlpi_lock;
134 struct its_vm *vm;
135 struct its_vlpi_map *vlpi_maps;
136 int nr_vlpis;
137};
138
139/*
140 * The ITS view of a device - belongs to an ITS, owns an interrupt
141 * translation table, and a list of interrupts. If it some of its
142 * LPIs are injected into a guest (GICv4), the event_map.vm field
143 * indicates which one.
144 */
145struct its_device {
146 struct list_head entry;
147 struct its_node *its;
148 struct event_lpi_map event_map;
149 void *itt;
150 u32 nr_ites;
151 u32 device_id;
152 bool shared;
153};
154
155static struct {
156 raw_spinlock_t lock;
157 struct its_device *dev;
158 struct its_vpe **vpes;
159 int next_victim;
160} vpe_proxy;
161
162static LIST_HEAD(its_nodes);
163static DEFINE_RAW_SPINLOCK(its_lock);
164static struct rdists *gic_rdists;
165static struct irq_domain *its_parent;
166
167static unsigned long its_list_map;
168static u16 vmovp_seq_num;
169static DEFINE_RAW_SPINLOCK(vmovp_lock);
170
171static DEFINE_IDA(its_vpeid_ida);
172
173#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
174#define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
175#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
176#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
177
178static u16 get_its_list(struct its_vm *vm)
179{
180 struct its_node *its;
181 unsigned long its_list = 0;
182
183 list_for_each_entry(its, &its_nodes, entry) {
184 if (!its->is_v4)
185 continue;
186
187 if (vm->vlpi_count[its->list_nr])
188 __set_bit(its->list_nr, &its_list);
189 }
190
191 return (u16)its_list;
192}
193
194static struct its_collection *dev_event_to_col(struct its_device *its_dev,
195 u32 event)
196{
197 struct its_node *its = its_dev->its;
198
199 return its->collections + its_dev->event_map.col_map[event];
200}
201
202static struct its_collection *valid_col(struct its_collection *col)
203{
204 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
205 return NULL;
206
207 return col;
208}
209
210static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
211{
212 if (valid_col(its->collections + vpe->col_idx))
213 return vpe;
214
215 return NULL;
216}
217
218/*
219 * ITS command descriptors - parameters to be encoded in a command
220 * block.
221 */
222struct its_cmd_desc {
223 union {
224 struct {
225 struct its_device *dev;
226 u32 event_id;
227 } its_inv_cmd;
228
229 struct {
230 struct its_device *dev;
231 u32 event_id;
232 } its_clear_cmd;
233
234 struct {
235 struct its_device *dev;
236 u32 event_id;
237 } its_int_cmd;
238
239 struct {
240 struct its_device *dev;
241 int valid;
242 } its_mapd_cmd;
243
244 struct {
245 struct its_collection *col;
246 int valid;
247 } its_mapc_cmd;
248
249 struct {
250 struct its_device *dev;
251 u32 phys_id;
252 u32 event_id;
253 } its_mapti_cmd;
254
255 struct {
256 struct its_device *dev;
257 struct its_collection *col;
258 u32 event_id;
259 } its_movi_cmd;
260
261 struct {
262 struct its_device *dev;
263 u32 event_id;
264 } its_discard_cmd;
265
266 struct {
267 struct its_collection *col;
268 } its_invall_cmd;
269
270 struct {
271 struct its_vpe *vpe;
272 } its_vinvall_cmd;
273
274 struct {
275 struct its_vpe *vpe;
276 struct its_collection *col;
277 bool valid;
278 } its_vmapp_cmd;
279
280 struct {
281 struct its_vpe *vpe;
282 struct its_device *dev;
283 u32 virt_id;
284 u32 event_id;
285 bool db_enabled;
286 } its_vmapti_cmd;
287
288 struct {
289 struct its_vpe *vpe;
290 struct its_device *dev;
291 u32 event_id;
292 bool db_enabled;
293 } its_vmovi_cmd;
294
295 struct {
296 struct its_vpe *vpe;
297 struct its_collection *col;
298 u16 seq_num;
299 u16 its_list;
300 } its_vmovp_cmd;
301 };
302};
303
304/*
305 * The ITS command block, which is what the ITS actually parses.
306 */
307struct its_cmd_block {
308 u64 raw_cmd[4];
309};
310
311#define ITS_CMD_QUEUE_SZ SZ_64K
312#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
313
314typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
315 struct its_cmd_block *,
316 struct its_cmd_desc *);
317
318typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
319 struct its_cmd_block *,
320 struct its_cmd_desc *);
321
322static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
323{
324 u64 mask = GENMASK_ULL(h, l);
325 *raw_cmd &= ~mask;
326 *raw_cmd |= (val << l) & mask;
327}
328
329static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
330{
331 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
332}
333
334static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
335{
336 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
337}
338
339static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
340{
341 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
342}
343
344static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
345{
346 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
347}
348
349static void its_encode_size(struct its_cmd_block *cmd, u8 size)
350{
351 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
352}
353
354static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
355{
356 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
357}
358
359static void its_encode_valid(struct its_cmd_block *cmd, int valid)
360{
361 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
362}
363
364static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
365{
366 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
367}
368
369static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
370{
371 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
372}
373
374static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
375{
376 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
377}
378
379static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
380{
381 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
382}
383
384static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
385{
386 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
387}
388
389static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
390{
391 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
392}
393
394static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
395{
396 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
397}
398
399static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
400{
401 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
402}
403
404static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
405{
406 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
407}
408
409static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
410{
411 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
412}
413
414static inline void its_fixup_cmd(struct its_cmd_block *cmd)
415{
416 /* Let's fixup BE commands */
417 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
418 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
419 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
420 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
421}
422
423static struct its_collection *its_build_mapd_cmd(struct its_node *its,
424 struct its_cmd_block *cmd,
425 struct its_cmd_desc *desc)
426{
427 unsigned long itt_addr;
428 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
429
430 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
431 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
432
433 its_encode_cmd(cmd, GITS_CMD_MAPD);
434 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
435 its_encode_size(cmd, size - 1);
436 its_encode_itt(cmd, itt_addr);
437 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
438
439 its_fixup_cmd(cmd);
440
441 return NULL;
442}
443
444static struct its_collection *its_build_mapc_cmd(struct its_node *its,
445 struct its_cmd_block *cmd,
446 struct its_cmd_desc *desc)
447{
448 its_encode_cmd(cmd, GITS_CMD_MAPC);
449 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
450 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
451 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
452
453 its_fixup_cmd(cmd);
454
455 return desc->its_mapc_cmd.col;
456}
457
458static struct its_collection *its_build_mapti_cmd(struct its_node *its,
459 struct its_cmd_block *cmd,
460 struct its_cmd_desc *desc)
461{
462 struct its_collection *col;
463
464 col = dev_event_to_col(desc->its_mapti_cmd.dev,
465 desc->its_mapti_cmd.event_id);
466
467 its_encode_cmd(cmd, GITS_CMD_MAPTI);
468 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
469 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
470 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
471 its_encode_collection(cmd, col->col_id);
472
473 its_fixup_cmd(cmd);
474
475 return valid_col(col);
476}
477
478static struct its_collection *its_build_movi_cmd(struct its_node *its,
479 struct its_cmd_block *cmd,
480 struct its_cmd_desc *desc)
481{
482 struct its_collection *col;
483
484 col = dev_event_to_col(desc->its_movi_cmd.dev,
485 desc->its_movi_cmd.event_id);
486
487 its_encode_cmd(cmd, GITS_CMD_MOVI);
488 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
489 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
490 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
491
492 its_fixup_cmd(cmd);
493
494 return valid_col(col);
495}
496
497static struct its_collection *its_build_discard_cmd(struct its_node *its,
498 struct its_cmd_block *cmd,
499 struct its_cmd_desc *desc)
500{
501 struct its_collection *col;
502
503 col = dev_event_to_col(desc->its_discard_cmd.dev,
504 desc->its_discard_cmd.event_id);
505
506 its_encode_cmd(cmd, GITS_CMD_DISCARD);
507 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
508 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
509
510 its_fixup_cmd(cmd);
511
512 return valid_col(col);
513}
514
515static struct its_collection *its_build_inv_cmd(struct its_node *its,
516 struct its_cmd_block *cmd,
517 struct its_cmd_desc *desc)
518{
519 struct its_collection *col;
520
521 col = dev_event_to_col(desc->its_inv_cmd.dev,
522 desc->its_inv_cmd.event_id);
523
524 its_encode_cmd(cmd, GITS_CMD_INV);
525 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
526 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
527
528 its_fixup_cmd(cmd);
529
530 return valid_col(col);
531}
532
533static struct its_collection *its_build_int_cmd(struct its_node *its,
534 struct its_cmd_block *cmd,
535 struct its_cmd_desc *desc)
536{
537 struct its_collection *col;
538
539 col = dev_event_to_col(desc->its_int_cmd.dev,
540 desc->its_int_cmd.event_id);
541
542 its_encode_cmd(cmd, GITS_CMD_INT);
543 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
544 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
545
546 its_fixup_cmd(cmd);
547
548 return valid_col(col);
549}
550
551static struct its_collection *its_build_clear_cmd(struct its_node *its,
552 struct its_cmd_block *cmd,
553 struct its_cmd_desc *desc)
554{
555 struct its_collection *col;
556
557 col = dev_event_to_col(desc->its_clear_cmd.dev,
558 desc->its_clear_cmd.event_id);
559
560 its_encode_cmd(cmd, GITS_CMD_CLEAR);
561 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
562 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
563
564 its_fixup_cmd(cmd);
565
566 return valid_col(col);
567}
568
569static struct its_collection *its_build_invall_cmd(struct its_node *its,
570 struct its_cmd_block *cmd,
571 struct its_cmd_desc *desc)
572{
573 its_encode_cmd(cmd, GITS_CMD_INVALL);
574 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
575
576 its_fixup_cmd(cmd);
577
578 return NULL;
579}
580
581static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
582 struct its_cmd_block *cmd,
583 struct its_cmd_desc *desc)
584{
585 its_encode_cmd(cmd, GITS_CMD_VINVALL);
586 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
587
588 its_fixup_cmd(cmd);
589
590 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
591}
592
593static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
594 struct its_cmd_block *cmd,
595 struct its_cmd_desc *desc)
596{
597 unsigned long vpt_addr;
598 u64 target;
599
600 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
601 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
602
603 its_encode_cmd(cmd, GITS_CMD_VMAPP);
604 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
605 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
606 its_encode_target(cmd, target);
607 its_encode_vpt_addr(cmd, vpt_addr);
608 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
609
610 its_fixup_cmd(cmd);
611
612 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
613}
614
615static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
616 struct its_cmd_block *cmd,
617 struct its_cmd_desc *desc)
618{
619 u32 db;
620
621 if (desc->its_vmapti_cmd.db_enabled)
622 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
623 else
624 db = 1023;
625
626 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
627 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
628 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
629 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
630 its_encode_db_phys_id(cmd, db);
631 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
632
633 its_fixup_cmd(cmd);
634
635 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
636}
637
638static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
639 struct its_cmd_block *cmd,
640 struct its_cmd_desc *desc)
641{
642 u32 db;
643
644 if (desc->its_vmovi_cmd.db_enabled)
645 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
646 else
647 db = 1023;
648
649 its_encode_cmd(cmd, GITS_CMD_VMOVI);
650 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
651 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
652 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
653 its_encode_db_phys_id(cmd, db);
654 its_encode_db_valid(cmd, true);
655
656 its_fixup_cmd(cmd);
657
658 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
659}
660
661static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
662 struct its_cmd_block *cmd,
663 struct its_cmd_desc *desc)
664{
665 u64 target;
666
667 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
668 its_encode_cmd(cmd, GITS_CMD_VMOVP);
669 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
670 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
671 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
672 its_encode_target(cmd, target);
673
674 its_fixup_cmd(cmd);
675
676 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
677}
678
679static u64 its_cmd_ptr_to_offset(struct its_node *its,
680 struct its_cmd_block *ptr)
681{
682 return (ptr - its->cmd_base) * sizeof(*ptr);
683}
684
685static int its_queue_full(struct its_node *its)
686{
687 int widx;
688 int ridx;
689
690 widx = its->cmd_write - its->cmd_base;
691 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
692
693 /* This is incredibly unlikely to happen, unless the ITS locks up. */
694 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
695 return 1;
696
697 return 0;
698}
699
700static struct its_cmd_block *its_allocate_entry(struct its_node *its)
701{
702 struct its_cmd_block *cmd;
703 u32 count = 1000000; /* 1s! */
704
705 while (its_queue_full(its)) {
706 count--;
707 if (!count) {
708 pr_err_ratelimited("ITS queue not draining\n");
709 return NULL;
710 }
711 cpu_relax();
712 udelay(1);
713 }
714
715 cmd = its->cmd_write++;
716
717 /* Handle queue wrapping */
718 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
719 its->cmd_write = its->cmd_base;
720
721 /* Clear command */
722 cmd->raw_cmd[0] = 0;
723 cmd->raw_cmd[1] = 0;
724 cmd->raw_cmd[2] = 0;
725 cmd->raw_cmd[3] = 0;
726
727 return cmd;
728}
729
730static struct its_cmd_block *its_post_commands(struct its_node *its)
731{
732 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
733
734 writel_relaxed(wr, its->base + GITS_CWRITER);
735
736 return its->cmd_write;
737}
738
739static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
740{
741 /*
742 * Make sure the commands written to memory are observable by
743 * the ITS.
744 */
745 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
746 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
747 else
748 dsb(ishst);
749}
750
751static int its_wait_for_range_completion(struct its_node *its,
752 u64 prev_idx,
753 struct its_cmd_block *to)
754{
755 u64 rd_idx, to_idx, linear_idx;
756 u32 count = 1000000; /* 1s! */
757
758 /* Linearize to_idx if the command set has wrapped around */
759 to_idx = its_cmd_ptr_to_offset(its, to);
760 if (to_idx < prev_idx)
761 to_idx += ITS_CMD_QUEUE_SZ;
762
763 linear_idx = prev_idx;
764
765 while (1) {
766 s64 delta;
767
768 rd_idx = readl_relaxed(its->base + GITS_CREADR);
769
770 /*
771 * Compute the read pointer progress, taking the
772 * potential wrap-around into account.
773 */
774 delta = rd_idx - prev_idx;
775 if (rd_idx < prev_idx)
776 delta += ITS_CMD_QUEUE_SZ;
777
778 linear_idx += delta;
779 if (linear_idx >= to_idx)
780 break;
781
782 count--;
783 if (!count) {
784 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
785 to_idx, linear_idx);
786 return -1;
787 }
788 prev_idx = rd_idx;
789 cpu_relax();
790 udelay(1);
791 }
792
793 return 0;
794}
795
796/* Warning, macro hell follows */
797#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
798void name(struct its_node *its, \
799 buildtype builder, \
800 struct its_cmd_desc *desc) \
801{ \
802 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
803 synctype *sync_obj; \
804 unsigned long flags; \
805 u64 rd_idx; \
806 \
807 raw_spin_lock_irqsave(&its->lock, flags); \
808 \
809 cmd = its_allocate_entry(its); \
810 if (!cmd) { /* We're soooooo screewed... */ \
811 raw_spin_unlock_irqrestore(&its->lock, flags); \
812 return; \
813 } \
814 sync_obj = builder(its, cmd, desc); \
815 its_flush_cmd(its, cmd); \
816 \
817 if (sync_obj) { \
818 sync_cmd = its_allocate_entry(its); \
819 if (!sync_cmd) \
820 goto post; \
821 \
822 buildfn(its, sync_cmd, sync_obj); \
823 its_flush_cmd(its, sync_cmd); \
824 } \
825 \
826post: \
827 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
828 next_cmd = its_post_commands(its); \
829 raw_spin_unlock_irqrestore(&its->lock, flags); \
830 \
831 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
832 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
833}
834
835static void its_build_sync_cmd(struct its_node *its,
836 struct its_cmd_block *sync_cmd,
837 struct its_collection *sync_col)
838{
839 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
840 its_encode_target(sync_cmd, sync_col->target_address);
841
842 its_fixup_cmd(sync_cmd);
843}
844
845static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
846 struct its_collection, its_build_sync_cmd)
847
848static void its_build_vsync_cmd(struct its_node *its,
849 struct its_cmd_block *sync_cmd,
850 struct its_vpe *sync_vpe)
851{
852 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
853 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
854
855 its_fixup_cmd(sync_cmd);
856}
857
858static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
859 struct its_vpe, its_build_vsync_cmd)
860
861static void its_send_int(struct its_device *dev, u32 event_id)
862{
863 struct its_cmd_desc desc;
864
865 desc.its_int_cmd.dev = dev;
866 desc.its_int_cmd.event_id = event_id;
867
868 its_send_single_command(dev->its, its_build_int_cmd, &desc);
869}
870
871static void its_send_clear(struct its_device *dev, u32 event_id)
872{
873 struct its_cmd_desc desc;
874
875 desc.its_clear_cmd.dev = dev;
876 desc.its_clear_cmd.event_id = event_id;
877
878 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
879}
880
881static void its_send_inv(struct its_device *dev, u32 event_id)
882{
883 struct its_cmd_desc desc;
884
885 desc.its_inv_cmd.dev = dev;
886 desc.its_inv_cmd.event_id = event_id;
887
888 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
889}
890
891static void its_send_mapd(struct its_device *dev, int valid)
892{
893 struct its_cmd_desc desc;
894
895 desc.its_mapd_cmd.dev = dev;
896 desc.its_mapd_cmd.valid = !!valid;
897
898 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
899}
900
901static void its_send_mapc(struct its_node *its, struct its_collection *col,
902 int valid)
903{
904 struct its_cmd_desc desc;
905
906 desc.its_mapc_cmd.col = col;
907 desc.its_mapc_cmd.valid = !!valid;
908
909 its_send_single_command(its, its_build_mapc_cmd, &desc);
910}
911
912static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
913{
914 struct its_cmd_desc desc;
915
916 desc.its_mapti_cmd.dev = dev;
917 desc.its_mapti_cmd.phys_id = irq_id;
918 desc.its_mapti_cmd.event_id = id;
919
920 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
921}
922
923static void its_send_movi(struct its_device *dev,
924 struct its_collection *col, u32 id)
925{
926 struct its_cmd_desc desc;
927
928 desc.its_movi_cmd.dev = dev;
929 desc.its_movi_cmd.col = col;
930 desc.its_movi_cmd.event_id = id;
931
932 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
933}
934
935static void its_send_discard(struct its_device *dev, u32 id)
936{
937 struct its_cmd_desc desc;
938
939 desc.its_discard_cmd.dev = dev;
940 desc.its_discard_cmd.event_id = id;
941
942 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
943}
944
945static void its_send_invall(struct its_node *its, struct its_collection *col)
946{
947 struct its_cmd_desc desc;
948
949 desc.its_invall_cmd.col = col;
950
951 its_send_single_command(its, its_build_invall_cmd, &desc);
952}
953
954static void its_send_vmapti(struct its_device *dev, u32 id)
955{
956 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
957 struct its_cmd_desc desc;
958
959 desc.its_vmapti_cmd.vpe = map->vpe;
960 desc.its_vmapti_cmd.dev = dev;
961 desc.its_vmapti_cmd.virt_id = map->vintid;
962 desc.its_vmapti_cmd.event_id = id;
963 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
964
965 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
966}
967
968static void its_send_vmovi(struct its_device *dev, u32 id)
969{
970 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
971 struct its_cmd_desc desc;
972
973 desc.its_vmovi_cmd.vpe = map->vpe;
974 desc.its_vmovi_cmd.dev = dev;
975 desc.its_vmovi_cmd.event_id = id;
976 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
977
978 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
979}
980
981static void its_send_vmapp(struct its_node *its,
982 struct its_vpe *vpe, bool valid)
983{
984 struct its_cmd_desc desc;
985
986 desc.its_vmapp_cmd.vpe = vpe;
987 desc.its_vmapp_cmd.valid = valid;
988 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
989
990 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
991}
992
993static void its_send_vmovp(struct its_vpe *vpe)
994{
995 struct its_cmd_desc desc = {};
996 struct its_node *its;
997 unsigned long flags;
998 int col_id = vpe->col_idx;
999
1000 desc.its_vmovp_cmd.vpe = vpe;
1001
1002 if (!its_list_map) {
1003 its = list_first_entry(&its_nodes, struct its_node, entry);
1004 desc.its_vmovp_cmd.col = &its->collections[col_id];
1005 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1006 return;
1007 }
1008
1009 /*
1010 * Yet another marvel of the architecture. If using the
1011 * its_list "feature", we need to make sure that all ITSs
1012 * receive all VMOVP commands in the same order. The only way
1013 * to guarantee this is to make vmovp a serialization point.
1014 *
1015 * Wall <-- Head.
1016 */
1017 raw_spin_lock_irqsave(&vmovp_lock, flags);
1018
1019 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1020 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1021
1022 /* Emit VMOVPs */
1023 list_for_each_entry(its, &its_nodes, entry) {
1024 if (!its->is_v4)
1025 continue;
1026
1027 if (!vpe->its_vm->vlpi_count[its->list_nr])
1028 continue;
1029
1030 desc.its_vmovp_cmd.col = &its->collections[col_id];
1031 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1032 }
1033
1034 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1035}
1036
1037static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1038{
1039 struct its_cmd_desc desc;
1040
1041 desc.its_vinvall_cmd.vpe = vpe;
1042 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1043}
1044
1045/*
1046 * irqchip functions - assumes MSI, mostly.
1047 */
1048
1049static inline u32 its_get_event_id(struct irq_data *d)
1050{
1051 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1052 return d->hwirq - its_dev->event_map.lpi_base;
1053}
1054
1055static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1056{
1057 irq_hw_number_t hwirq;
1058 void *va;
1059 u8 *cfg;
1060
1061 if (irqd_is_forwarded_to_vcpu(d)) {
1062 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1063 u32 event = its_get_event_id(d);
1064 struct its_vlpi_map *map;
1065
1066 va = page_address(its_dev->event_map.vm->vprop_page);
1067 map = &its_dev->event_map.vlpi_maps[event];
1068 hwirq = map->vintid;
1069
1070 /* Remember the updated property */
1071 map->properties &= ~clr;
1072 map->properties |= set | LPI_PROP_GROUP1;
1073 } else {
1074 va = gic_rdists->prop_table_va;
1075 hwirq = d->hwirq;
1076 }
1077
1078 cfg = va + hwirq - 8192;
1079 *cfg &= ~clr;
1080 *cfg |= set | LPI_PROP_GROUP1;
1081
1082 /*
1083 * Make the above write visible to the redistributors.
1084 * And yes, we're flushing exactly: One. Single. Byte.
1085 * Humpf...
1086 */
1087 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1088 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1089 else
1090 dsb(ishst);
1091}
1092
1093static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1094{
1095 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1096
1097 lpi_write_config(d, clr, set);
1098 its_send_inv(its_dev, its_get_event_id(d));
1099}
1100
1101static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1102{
1103 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1104 u32 event = its_get_event_id(d);
1105
1106 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1107 return;
1108
1109 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1110
1111 /*
1112 * More fun with the architecture:
1113 *
1114 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1115 * value or to 1023, depending on the enable bit. But that
1116 * would be issueing a mapping for an /existing/ DevID+EventID
1117 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1118 * to the /same/ vPE, using this opportunity to adjust the
1119 * doorbell. Mouahahahaha. We loves it, Precious.
1120 */
1121 its_send_vmovi(its_dev, event);
1122}
1123
1124static void its_mask_irq(struct irq_data *d)
1125{
1126 if (irqd_is_forwarded_to_vcpu(d))
1127 its_vlpi_set_doorbell(d, false);
1128
1129 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1130}
1131
1132static void its_unmask_irq(struct irq_data *d)
1133{
1134 if (irqd_is_forwarded_to_vcpu(d))
1135 its_vlpi_set_doorbell(d, true);
1136
1137 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1138}
1139
1140static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1141 bool force)
1142{
1143 unsigned int cpu;
1144 const struct cpumask *cpu_mask = cpu_online_mask;
1145 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1146 struct its_collection *target_col;
1147 u32 id = its_get_event_id(d);
1148
1149 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1150 if (irqd_is_forwarded_to_vcpu(d))
1151 return -EINVAL;
1152
1153 /* lpi cannot be routed to a redistributor that is on a foreign node */
1154 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1155 if (its_dev->its->numa_node >= 0) {
1156 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1157 if (!cpumask_intersects(mask_val, cpu_mask))
1158 return -EINVAL;
1159 }
1160 }
1161
1162 cpu = cpumask_any_and(mask_val, cpu_mask);
1163
1164 if (cpu >= nr_cpu_ids)
1165 return -EINVAL;
1166
1167 /* don't set the affinity when the target cpu is same as current one */
1168 if (cpu != its_dev->event_map.col_map[id]) {
1169 target_col = &its_dev->its->collections[cpu];
1170 its_send_movi(its_dev, target_col, id);
1171 its_dev->event_map.col_map[id] = cpu;
1172 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1173 }
1174
1175 return IRQ_SET_MASK_OK_DONE;
1176}
1177
1178static u64 its_irq_get_msi_base(struct its_device *its_dev)
1179{
1180 struct its_node *its = its_dev->its;
1181
1182 return its->phys_base + GITS_TRANSLATER;
1183}
1184
1185static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1186{
1187 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1188 struct its_node *its;
1189 u64 addr;
1190
1191 its = its_dev->its;
1192 addr = its->get_msi_base(its_dev);
1193
1194 msg->address_lo = lower_32_bits(addr);
1195 msg->address_hi = upper_32_bits(addr);
1196 msg->data = its_get_event_id(d);
1197
1198 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1199}
1200
1201static int its_irq_set_irqchip_state(struct irq_data *d,
1202 enum irqchip_irq_state which,
1203 bool state)
1204{
1205 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1206 u32 event = its_get_event_id(d);
1207
1208 if (which != IRQCHIP_STATE_PENDING)
1209 return -EINVAL;
1210
1211 if (state)
1212 its_send_int(its_dev, event);
1213 else
1214 its_send_clear(its_dev, event);
1215
1216 return 0;
1217}
1218
1219static void its_map_vm(struct its_node *its, struct its_vm *vm)
1220{
1221 unsigned long flags;
1222
1223 /* Not using the ITS list? Everything is always mapped. */
1224 if (!its_list_map)
1225 return;
1226
1227 raw_spin_lock_irqsave(&vmovp_lock, flags);
1228
1229 /*
1230 * If the VM wasn't mapped yet, iterate over the vpes and get
1231 * them mapped now.
1232 */
1233 vm->vlpi_count[its->list_nr]++;
1234
1235 if (vm->vlpi_count[its->list_nr] == 1) {
1236 int i;
1237
1238 for (i = 0; i < vm->nr_vpes; i++) {
1239 struct its_vpe *vpe = vm->vpes[i];
1240 struct irq_data *d = irq_get_irq_data(vpe->irq);
1241
1242 /* Map the VPE to the first possible CPU */
1243 vpe->col_idx = cpumask_first(cpu_online_mask);
1244 its_send_vmapp(its, vpe, true);
1245 its_send_vinvall(its, vpe);
1246 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1247 }
1248 }
1249
1250 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1251}
1252
1253static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1254{
1255 unsigned long flags;
1256
1257 /* Not using the ITS list? Everything is always mapped. */
1258 if (!its_list_map)
1259 return;
1260
1261 raw_spin_lock_irqsave(&vmovp_lock, flags);
1262
1263 if (!--vm->vlpi_count[its->list_nr]) {
1264 int i;
1265
1266 for (i = 0; i < vm->nr_vpes; i++)
1267 its_send_vmapp(its, vm->vpes[i], false);
1268 }
1269
1270 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1271}
1272
1273static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1274{
1275 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1276 u32 event = its_get_event_id(d);
1277 int ret = 0;
1278
1279 if (!info->map)
1280 return -EINVAL;
1281
1282 mutex_lock(&its_dev->event_map.vlpi_lock);
1283
1284 if (!its_dev->event_map.vm) {
1285 struct its_vlpi_map *maps;
1286
1287 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1288 GFP_KERNEL);
1289 if (!maps) {
1290 ret = -ENOMEM;
1291 goto out;
1292 }
1293
1294 its_dev->event_map.vm = info->map->vm;
1295 its_dev->event_map.vlpi_maps = maps;
1296 } else if (its_dev->event_map.vm != info->map->vm) {
1297 ret = -EINVAL;
1298 goto out;
1299 }
1300
1301 /* Get our private copy of the mapping information */
1302 its_dev->event_map.vlpi_maps[event] = *info->map;
1303
1304 if (irqd_is_forwarded_to_vcpu(d)) {
1305 /* Already mapped, move it around */
1306 its_send_vmovi(its_dev, event);
1307 } else {
1308 /* Ensure all the VPEs are mapped on this ITS */
1309 its_map_vm(its_dev->its, info->map->vm);
1310
1311 /*
1312 * Flag the interrupt as forwarded so that we can
1313 * start poking the virtual property table.
1314 */
1315 irqd_set_forwarded_to_vcpu(d);
1316
1317 /* Write out the property to the prop table */
1318 lpi_write_config(d, 0xff, info->map->properties);
1319
1320 /* Drop the physical mapping */
1321 its_send_discard(its_dev, event);
1322
1323 /* and install the virtual one */
1324 its_send_vmapti(its_dev, event);
1325
1326 /* Increment the number of VLPIs */
1327 its_dev->event_map.nr_vlpis++;
1328 }
1329
1330out:
1331 mutex_unlock(&its_dev->event_map.vlpi_lock);
1332 return ret;
1333}
1334
1335static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1336{
1337 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1338 u32 event = its_get_event_id(d);
1339 int ret = 0;
1340
1341 mutex_lock(&its_dev->event_map.vlpi_lock);
1342
1343 if (!its_dev->event_map.vm ||
1344 !its_dev->event_map.vlpi_maps[event].vm) {
1345 ret = -EINVAL;
1346 goto out;
1347 }
1348
1349 /* Copy our mapping information to the incoming request */
1350 *info->map = its_dev->event_map.vlpi_maps[event];
1351
1352out:
1353 mutex_unlock(&its_dev->event_map.vlpi_lock);
1354 return ret;
1355}
1356
1357static int its_vlpi_unmap(struct irq_data *d)
1358{
1359 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1360 u32 event = its_get_event_id(d);
1361 int ret = 0;
1362
1363 mutex_lock(&its_dev->event_map.vlpi_lock);
1364
1365 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1366 ret = -EINVAL;
1367 goto out;
1368 }
1369
1370 /* Drop the virtual mapping */
1371 its_send_discard(its_dev, event);
1372
1373 /* and restore the physical one */
1374 irqd_clr_forwarded_to_vcpu(d);
1375 its_send_mapti(its_dev, d->hwirq, event);
1376 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1377 LPI_PROP_ENABLED |
1378 LPI_PROP_GROUP1));
1379
1380 /* Potentially unmap the VM from this ITS */
1381 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1382
1383 /*
1384 * Drop the refcount and make the device available again if
1385 * this was the last VLPI.
1386 */
1387 if (!--its_dev->event_map.nr_vlpis) {
1388 its_dev->event_map.vm = NULL;
1389 kfree(its_dev->event_map.vlpi_maps);
1390 }
1391
1392out:
1393 mutex_unlock(&its_dev->event_map.vlpi_lock);
1394 return ret;
1395}
1396
1397static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1398{
1399 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1400
1401 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1402 return -EINVAL;
1403
1404 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1405 lpi_update_config(d, 0xff, info->config);
1406 else
1407 lpi_write_config(d, 0xff, info->config);
1408 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1409
1410 return 0;
1411}
1412
1413static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1414{
1415 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1416 struct its_cmd_info *info = vcpu_info;
1417
1418 /* Need a v4 ITS */
1419 if (!its_dev->its->is_v4)
1420 return -EINVAL;
1421
1422 /* Unmap request? */
1423 if (!info)
1424 return its_vlpi_unmap(d);
1425
1426 switch (info->cmd_type) {
1427 case MAP_VLPI:
1428 return its_vlpi_map(d, info);
1429
1430 case GET_VLPI:
1431 return its_vlpi_get(d, info);
1432
1433 case PROP_UPDATE_VLPI:
1434 case PROP_UPDATE_AND_INV_VLPI:
1435 return its_vlpi_prop_update(d, info);
1436
1437 default:
1438 return -EINVAL;
1439 }
1440}
1441
1442static struct irq_chip its_irq_chip = {
1443 .name = "ITS",
1444 .irq_mask = its_mask_irq,
1445 .irq_unmask = its_unmask_irq,
1446 .irq_eoi = irq_chip_eoi_parent,
1447 .irq_set_affinity = its_set_affinity,
1448 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1449 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1450 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1451};
1452
1453
1454/*
1455 * How we allocate LPIs:
1456 *
1457 * lpi_range_list contains ranges of LPIs that are to available to
1458 * allocate from. To allocate LPIs, just pick the first range that
1459 * fits the required allocation, and reduce it by the required
1460 * amount. Once empty, remove the range from the list.
1461 *
1462 * To free a range of LPIs, add a free range to the list, sort it and
1463 * merge the result if the new range happens to be adjacent to an
1464 * already free block.
1465 *
1466 * The consequence of the above is that allocation is cost is low, but
1467 * freeing is expensive. We assumes that freeing rarely occurs.
1468 */
1469#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1470
1471static DEFINE_MUTEX(lpi_range_lock);
1472static LIST_HEAD(lpi_range_list);
1473
1474struct lpi_range {
1475 struct list_head entry;
1476 u32 base_id;
1477 u32 span;
1478};
1479
1480static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1481{
1482 struct lpi_range *range;
1483
1484 range = kmalloc(sizeof(*range), GFP_KERNEL);
1485 if (range) {
1486 range->base_id = base;
1487 range->span = span;
1488 }
1489
1490 return range;
1491}
1492
1493static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1494{
1495 struct lpi_range *range, *tmp;
1496 int err = -ENOSPC;
1497
1498 mutex_lock(&lpi_range_lock);
1499
1500 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1501 if (range->span >= nr_lpis) {
1502 *base = range->base_id;
1503 range->base_id += nr_lpis;
1504 range->span -= nr_lpis;
1505
1506 if (range->span == 0) {
1507 list_del(&range->entry);
1508 kfree(range);
1509 }
1510
1511 err = 0;
1512 break;
1513 }
1514 }
1515
1516 mutex_unlock(&lpi_range_lock);
1517
1518 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1519 return err;
1520}
1521
1522static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1523{
1524 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1525 return;
1526 if (a->base_id + a->span != b->base_id)
1527 return;
1528 b->base_id = a->base_id;
1529 b->span += a->span;
1530 list_del(&a->entry);
1531 kfree(a);
1532}
1533
1534static int free_lpi_range(u32 base, u32 nr_lpis)
1535{
1536 struct lpi_range *new, *old;
1537
1538 new = mk_lpi_range(base, nr_lpis);
1539 if (!new)
1540 return -ENOMEM;
1541
1542 mutex_lock(&lpi_range_lock);
1543
1544 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1545 if (old->base_id < base)
1546 break;
1547 }
1548 /*
1549 * old is the last element with ->base_id smaller than base,
1550 * so new goes right after it. If there are no elements with
1551 * ->base_id smaller than base, &old->entry ends up pointing
1552 * at the head of the list, and inserting new it the start of
1553 * the list is the right thing to do in that case as well.
1554 */
1555 list_add(&new->entry, &old->entry);
1556 /*
1557 * Now check if we can merge with the preceding and/or
1558 * following ranges.
1559 */
1560 merge_lpi_ranges(old, new);
1561 merge_lpi_ranges(new, list_next_entry(new, entry));
1562
1563 mutex_unlock(&lpi_range_lock);
1564 return 0;
1565}
1566
1567static int __init its_lpi_init(u32 id_bits)
1568{
1569 u32 lpis = (1UL << id_bits) - 8192;
1570 u32 numlpis;
1571 int err;
1572
1573 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1574
1575 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1576 lpis = numlpis;
1577 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1578 lpis);
1579 }
1580
1581 /*
1582 * Initializing the allocator is just the same as freeing the
1583 * full range of LPIs.
1584 */
1585 err = free_lpi_range(8192, lpis);
1586 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1587 return err;
1588}
1589
1590static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1591{
1592 unsigned long *bitmap = NULL;
1593 int err = 0;
1594
1595 do {
1596 err = alloc_lpi_range(nr_irqs, base);
1597 if (!err)
1598 break;
1599
1600 nr_irqs /= 2;
1601 } while (nr_irqs > 0);
1602
1603 if (!nr_irqs)
1604 err = -ENOSPC;
1605
1606 if (err)
1607 goto out;
1608
1609 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1610 if (!bitmap)
1611 goto out;
1612
1613 *nr_ids = nr_irqs;
1614
1615out:
1616 if (!bitmap)
1617 *base = *nr_ids = 0;
1618
1619 return bitmap;
1620}
1621
1622static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1623{
1624 WARN_ON(free_lpi_range(base, nr_ids));
1625 kfree(bitmap);
1626}
1627
1628static void gic_reset_prop_table(void *va)
1629{
1630 /* Priority 0xa0, Group-1, disabled */
1631 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1632
1633 /* Make sure the GIC will observe the written configuration */
1634 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1635}
1636
1637static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1638{
1639 struct page *prop_page;
1640
1641 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1642 if (!prop_page)
1643 return NULL;
1644
1645 gic_reset_prop_table(page_address(prop_page));
1646
1647 return prop_page;
1648}
1649
1650static void its_free_prop_table(struct page *prop_page)
1651{
1652 free_pages((unsigned long)page_address(prop_page),
1653 get_order(LPI_PROPBASE_SZ));
1654}
1655
1656static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1657{
1658 phys_addr_t start, end, addr_end;
1659 u64 i;
1660
1661 /*
1662 * We don't bother checking for a kdump kernel as by
1663 * construction, the LPI tables are out of this kernel's
1664 * memory map.
1665 */
1666 if (is_kdump_kernel())
1667 return true;
1668
1669 addr_end = addr + size - 1;
1670
1671 for_each_reserved_mem_region(i, &start, &end) {
1672 if (addr >= start && addr_end <= end)
1673 return true;
1674 }
1675
1676 /* Not found, not a good sign... */
1677 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1678 &addr, &addr_end);
1679 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1680 return false;
1681}
1682
1683static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1684{
1685 if (efi_enabled(EFI_CONFIG_TABLES))
1686 return efi_mem_reserve_persistent(addr, size);
1687
1688 return 0;
1689}
1690
1691static int __init its_setup_lpi_prop_table(void)
1692{
1693 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1694 u64 val;
1695
1696 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1697 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1698
1699 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1700 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1701 LPI_PROPBASE_SZ,
1702 MEMREMAP_WB);
1703 gic_reset_prop_table(gic_rdists->prop_table_va);
1704 } else {
1705 struct page *page;
1706
1707 lpi_id_bits = min_t(u32,
1708 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1709 ITS_MAX_LPI_NRBITS);
1710 page = its_allocate_prop_table(GFP_NOWAIT);
1711 if (!page) {
1712 pr_err("Failed to allocate PROPBASE\n");
1713 return -ENOMEM;
1714 }
1715
1716 gic_rdists->prop_table_pa = page_to_phys(page);
1717 gic_rdists->prop_table_va = page_address(page);
1718 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1719 LPI_PROPBASE_SZ));
1720 }
1721
1722 pr_info("GICv3: using LPI property table @%pa\n",
1723 &gic_rdists->prop_table_pa);
1724
1725 return its_lpi_init(lpi_id_bits);
1726}
1727
1728static const char *its_base_type_string[] = {
1729 [GITS_BASER_TYPE_DEVICE] = "Devices",
1730 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1731 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1732 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1733 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1734 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1735 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1736};
1737
1738static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1739{
1740 u32 idx = baser - its->tables;
1741
1742 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1743}
1744
1745static void its_write_baser(struct its_node *its, struct its_baser *baser,
1746 u64 val)
1747{
1748 u32 idx = baser - its->tables;
1749
1750 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1751 baser->val = its_read_baser(its, baser);
1752}
1753
1754static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1755 u64 cache, u64 shr, u32 psz, u32 order,
1756 bool indirect)
1757{
1758 u64 val = its_read_baser(its, baser);
1759 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1760 u64 type = GITS_BASER_TYPE(val);
1761 u64 baser_phys, tmp;
1762 u32 alloc_pages;
1763 struct page *page;
1764 void *base;
1765
1766retry_alloc_baser:
1767 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1768 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1769 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1770 &its->phys_base, its_base_type_string[type],
1771 alloc_pages, GITS_BASER_PAGES_MAX);
1772 alloc_pages = GITS_BASER_PAGES_MAX;
1773 order = get_order(GITS_BASER_PAGES_MAX * psz);
1774 }
1775
1776 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1777 if (!page)
1778 return -ENOMEM;
1779
1780 base = (void *)page_address(page);
1781 baser_phys = virt_to_phys(base);
1782
1783 /* Check if the physical address of the memory is above 48bits */
1784 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1785
1786 /* 52bit PA is supported only when PageSize=64K */
1787 if (psz != SZ_64K) {
1788 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1789 free_pages((unsigned long)base, order);
1790 return -ENXIO;
1791 }
1792
1793 /* Convert 52bit PA to 48bit field */
1794 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1795 }
1796
1797retry_baser:
1798 val = (baser_phys |
1799 (type << GITS_BASER_TYPE_SHIFT) |
1800 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1801 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1802 cache |
1803 shr |
1804 GITS_BASER_VALID);
1805
1806 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1807
1808 switch (psz) {
1809 case SZ_4K:
1810 val |= GITS_BASER_PAGE_SIZE_4K;
1811 break;
1812 case SZ_16K:
1813 val |= GITS_BASER_PAGE_SIZE_16K;
1814 break;
1815 case SZ_64K:
1816 val |= GITS_BASER_PAGE_SIZE_64K;
1817 break;
1818 }
1819
1820 its_write_baser(its, baser, val);
1821 tmp = baser->val;
1822
1823 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1824 /*
1825 * Shareability didn't stick. Just use
1826 * whatever the read reported, which is likely
1827 * to be the only thing this redistributor
1828 * supports. If that's zero, make it
1829 * non-cacheable as well.
1830 */
1831 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1832 if (!shr) {
1833 cache = GITS_BASER_nC;
1834 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1835 }
1836 goto retry_baser;
1837 }
1838
1839 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1840 /*
1841 * Page size didn't stick. Let's try a smaller
1842 * size and retry. If we reach 4K, then
1843 * something is horribly wrong...
1844 */
1845 free_pages((unsigned long)base, order);
1846 baser->base = NULL;
1847
1848 switch (psz) {
1849 case SZ_16K:
1850 psz = SZ_4K;
1851 goto retry_alloc_baser;
1852 case SZ_64K:
1853 psz = SZ_16K;
1854 goto retry_alloc_baser;
1855 }
1856 }
1857
1858 if (val != tmp) {
1859 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1860 &its->phys_base, its_base_type_string[type],
1861 val, tmp);
1862 free_pages((unsigned long)base, order);
1863 return -ENXIO;
1864 }
1865
1866 baser->order = order;
1867 baser->base = base;
1868 baser->psz = psz;
1869 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1870
1871 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1872 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1873 its_base_type_string[type],
1874 (unsigned long)virt_to_phys(base),
1875 indirect ? "indirect" : "flat", (int)esz,
1876 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1877
1878 return 0;
1879}
1880
1881static bool its_parse_indirect_baser(struct its_node *its,
1882 struct its_baser *baser,
1883 u32 psz, u32 *order, u32 ids)
1884{
1885 u64 tmp = its_read_baser(its, baser);
1886 u64 type = GITS_BASER_TYPE(tmp);
1887 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1888 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1889 u32 new_order = *order;
1890 bool indirect = false;
1891
1892 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1893 if ((esz << ids) > (psz * 2)) {
1894 /*
1895 * Find out whether hw supports a single or two-level table by
1896 * table by reading bit at offset '62' after writing '1' to it.
1897 */
1898 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1899 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1900
1901 if (indirect) {
1902 /*
1903 * The size of the lvl2 table is equal to ITS page size
1904 * which is 'psz'. For computing lvl1 table size,
1905 * subtract ID bits that sparse lvl2 table from 'ids'
1906 * which is reported by ITS hardware times lvl1 table
1907 * entry size.
1908 */
1909 ids -= ilog2(psz / (int)esz);
1910 esz = GITS_LVL1_ENTRY_SIZE;
1911 }
1912 }
1913
1914 /*
1915 * Allocate as many entries as required to fit the
1916 * range of device IDs that the ITS can grok... The ID
1917 * space being incredibly sparse, this results in a
1918 * massive waste of memory if two-level device table
1919 * feature is not supported by hardware.
1920 */
1921 new_order = max_t(u32, get_order(esz << ids), new_order);
1922 if (new_order >= MAX_ORDER) {
1923 new_order = MAX_ORDER - 1;
1924 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1925 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1926 &its->phys_base, its_base_type_string[type],
1927 its->device_ids, ids);
1928 }
1929
1930 *order = new_order;
1931
1932 return indirect;
1933}
1934
1935static void its_free_tables(struct its_node *its)
1936{
1937 int i;
1938
1939 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1940 if (its->tables[i].base) {
1941 free_pages((unsigned long)its->tables[i].base,
1942 its->tables[i].order);
1943 its->tables[i].base = NULL;
1944 }
1945 }
1946}
1947
1948static int its_alloc_tables(struct its_node *its)
1949{
1950 u64 shr = GITS_BASER_InnerShareable;
1951 u64 cache = GITS_BASER_RaWaWb;
1952 u32 psz = SZ_64K;
1953 int err, i;
1954
1955 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1956 /* erratum 24313: ignore memory access type */
1957 cache = GITS_BASER_nCnB;
1958
1959 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1960 struct its_baser *baser = its->tables + i;
1961 u64 val = its_read_baser(its, baser);
1962 u64 type = GITS_BASER_TYPE(val);
1963 u32 order = get_order(psz);
1964 bool indirect = false;
1965
1966 switch (type) {
1967 case GITS_BASER_TYPE_NONE:
1968 continue;
1969
1970 case GITS_BASER_TYPE_DEVICE:
1971 indirect = its_parse_indirect_baser(its, baser,
1972 psz, &order,
1973 its->device_ids);
1974 break;
1975
1976 case GITS_BASER_TYPE_VCPU:
1977 indirect = its_parse_indirect_baser(its, baser,
1978 psz, &order,
1979 ITS_MAX_VPEID_BITS);
1980 break;
1981 }
1982
1983 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1984 if (err < 0) {
1985 its_free_tables(its);
1986 return err;
1987 }
1988
1989 /* Update settings which will be used for next BASERn */
1990 psz = baser->psz;
1991 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1992 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1993 }
1994
1995 return 0;
1996}
1997
1998static int its_alloc_collections(struct its_node *its)
1999{
2000 int i;
2001
2002 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2003 GFP_KERNEL);
2004 if (!its->collections)
2005 return -ENOMEM;
2006
2007 for (i = 0; i < nr_cpu_ids; i++)
2008 its->collections[i].target_address = ~0ULL;
2009
2010 return 0;
2011}
2012
2013static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2014{
2015 struct page *pend_page;
2016
2017 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2018 get_order(LPI_PENDBASE_SZ));
2019 if (!pend_page)
2020 return NULL;
2021
2022 /* Make sure the GIC will observe the zero-ed page */
2023 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2024
2025 return pend_page;
2026}
2027
2028static void its_free_pending_table(struct page *pt)
2029{
2030 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2031}
2032
2033/*
2034 * Booting with kdump and LPIs enabled is generally fine. Any other
2035 * case is wrong in the absence of firmware/EFI support.
2036 */
2037static bool enabled_lpis_allowed(void)
2038{
2039 phys_addr_t addr;
2040 u64 val;
2041
2042 /* Check whether the property table is in a reserved region */
2043 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2044 addr = val & GENMASK_ULL(51, 12);
2045
2046 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2047}
2048
2049static int __init allocate_lpi_tables(void)
2050{
2051 u64 val;
2052 int err, cpu;
2053
2054 /*
2055 * If LPIs are enabled while we run this from the boot CPU,
2056 * flag the RD tables as pre-allocated if the stars do align.
2057 */
2058 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2059 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2060 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2061 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2062 pr_info("GICv3: Using preallocated redistributor tables\n");
2063 }
2064
2065 err = its_setup_lpi_prop_table();
2066 if (err)
2067 return err;
2068
2069 /*
2070 * We allocate all the pending tables anyway, as we may have a
2071 * mix of RDs that have had LPIs enabled, and some that
2072 * don't. We'll free the unused ones as each CPU comes online.
2073 */
2074 for_each_possible_cpu(cpu) {
2075 struct page *pend_page;
2076
2077 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2078 if (!pend_page) {
2079 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2080 return -ENOMEM;
2081 }
2082
2083 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2084 }
2085
2086 return 0;
2087}
2088
2089static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2090{
2091 u32 count = 1000000; /* 1s! */
2092 bool clean;
2093 u64 val;
2094
2095 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2096 val &= ~GICR_VPENDBASER_Valid;
2097 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2098
2099 do {
2100 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2101 clean = !(val & GICR_VPENDBASER_Dirty);
2102 if (!clean) {
2103 count--;
2104 cpu_relax();
2105 udelay(1);
2106 }
2107 } while (!clean && count);
2108
2109 return val;
2110}
2111
2112static void its_cpu_init_lpis(void)
2113{
2114 void __iomem *rbase = gic_data_rdist_rd_base();
2115 struct page *pend_page;
2116 phys_addr_t paddr;
2117 u64 val, tmp;
2118
2119 if (gic_data_rdist()->lpi_enabled)
2120 return;
2121
2122 val = readl_relaxed(rbase + GICR_CTLR);
2123 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2124 (val & GICR_CTLR_ENABLE_LPIS)) {
2125 /*
2126 * Check that we get the same property table on all
2127 * RDs. If we don't, this is hopeless.
2128 */
2129 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2130 paddr &= GENMASK_ULL(51, 12);
2131 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2132 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2133
2134 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2135 paddr &= GENMASK_ULL(51, 16);
2136
2137 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2138 its_free_pending_table(gic_data_rdist()->pend_page);
2139 gic_data_rdist()->pend_page = NULL;
2140
2141 goto out;
2142 }
2143
2144 pend_page = gic_data_rdist()->pend_page;
2145 paddr = page_to_phys(pend_page);
2146 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2147
2148 /* set PROPBASE */
2149 val = (gic_rdists->prop_table_pa |
2150 GICR_PROPBASER_InnerShareable |
2151 GICR_PROPBASER_RaWaWb |
2152 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2153
2154 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2155 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2156
2157 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2158 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2159 /*
2160 * The HW reports non-shareable, we must
2161 * remove the cacheability attributes as
2162 * well.
2163 */
2164 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2165 GICR_PROPBASER_CACHEABILITY_MASK);
2166 val |= GICR_PROPBASER_nC;
2167 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2168 }
2169 pr_info_once("GIC: using cache flushing for LPI property table\n");
2170 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2171 }
2172
2173 /* set PENDBASE */
2174 val = (page_to_phys(pend_page) |
2175 GICR_PENDBASER_InnerShareable |
2176 GICR_PENDBASER_RaWaWb);
2177
2178 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2179 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2180
2181 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2182 /*
2183 * The HW reports non-shareable, we must remove the
2184 * cacheability attributes as well.
2185 */
2186 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2187 GICR_PENDBASER_CACHEABILITY_MASK);
2188 val |= GICR_PENDBASER_nC;
2189 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2190 }
2191
2192 /* Enable LPIs */
2193 val = readl_relaxed(rbase + GICR_CTLR);
2194 val |= GICR_CTLR_ENABLE_LPIS;
2195 writel_relaxed(val, rbase + GICR_CTLR);
2196
2197 if (gic_rdists->has_vlpis) {
2198 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2199
2200 /*
2201 * It's possible for CPU to receive VLPIs before it is
2202 * sheduled as a vPE, especially for the first CPU, and the
2203 * VLPI with INTID larger than 2^(IDbits+1) will be considered
2204 * as out of range and dropped by GIC.
2205 * So we initialize IDbits to known value to avoid VLPI drop.
2206 */
2207 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2208 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2209 smp_processor_id(), val);
2210 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2211
2212 /*
2213 * Also clear Valid bit of GICR_VPENDBASER, in case some
2214 * ancient programming gets left in and has possibility of
2215 * corrupting memory.
2216 */
2217 val = its_clear_vpend_valid(vlpi_base);
2218 WARN_ON(val & GICR_VPENDBASER_Dirty);
2219 }
2220
2221 /* Make sure the GIC has seen the above */
2222 dsb(sy);
2223out:
2224 gic_data_rdist()->lpi_enabled = true;
2225 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2226 smp_processor_id(),
2227 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2228 &paddr);
2229}
2230
2231static void its_cpu_init_collection(struct its_node *its)
2232{
2233 int cpu = smp_processor_id();
2234 u64 target;
2235
2236 /* avoid cross node collections and its mapping */
2237 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2238 struct device_node *cpu_node;
2239
2240 cpu_node = of_get_cpu_node(cpu, NULL);
2241 if (its->numa_node != NUMA_NO_NODE &&
2242 its->numa_node != of_node_to_nid(cpu_node))
2243 return;
2244 }
2245
2246 /*
2247 * We now have to bind each collection to its target
2248 * redistributor.
2249 */
2250 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2251 /*
2252 * This ITS wants the physical address of the
2253 * redistributor.
2254 */
2255 target = gic_data_rdist()->phys_base;
2256 } else {
2257 /* This ITS wants a linear CPU number. */
2258 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2259 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2260 }
2261
2262 /* Perform collection mapping */
2263 its->collections[cpu].target_address = target;
2264 its->collections[cpu].col_id = cpu;
2265
2266 its_send_mapc(its, &its->collections[cpu], 1);
2267 its_send_invall(its, &its->collections[cpu]);
2268}
2269
2270static void its_cpu_init_collections(void)
2271{
2272 struct its_node *its;
2273
2274 raw_spin_lock(&its_lock);
2275
2276 list_for_each_entry(its, &its_nodes, entry)
2277 its_cpu_init_collection(its);
2278
2279 raw_spin_unlock(&its_lock);
2280}
2281
2282static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2283{
2284 struct its_device *its_dev = NULL, *tmp;
2285 unsigned long flags;
2286
2287 raw_spin_lock_irqsave(&its->lock, flags);
2288
2289 list_for_each_entry(tmp, &its->its_device_list, entry) {
2290 if (tmp->device_id == dev_id) {
2291 its_dev = tmp;
2292 break;
2293 }
2294 }
2295
2296 raw_spin_unlock_irqrestore(&its->lock, flags);
2297
2298 return its_dev;
2299}
2300
2301static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2302{
2303 int i;
2304
2305 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2306 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2307 return &its->tables[i];
2308 }
2309
2310 return NULL;
2311}
2312
2313static bool its_alloc_table_entry(struct its_node *its,
2314 struct its_baser *baser, u32 id)
2315{
2316 struct page *page;
2317 u32 esz, idx;
2318 __le64 *table;
2319
2320 /* Don't allow device id that exceeds single, flat table limit */
2321 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2322 if (!(baser->val & GITS_BASER_INDIRECT))
2323 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2324
2325 /* Compute 1st level table index & check if that exceeds table limit */
2326 idx = id >> ilog2(baser->psz / esz);
2327 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2328 return false;
2329
2330 table = baser->base;
2331
2332 /* Allocate memory for 2nd level table */
2333 if (!table[idx]) {
2334 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2335 get_order(baser->psz));
2336 if (!page)
2337 return false;
2338
2339 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2340 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2341 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2342
2343 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2344
2345 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2346 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2347 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2348
2349 /* Ensure updated table contents are visible to ITS hardware */
2350 dsb(sy);
2351 }
2352
2353 return true;
2354}
2355
2356static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2357{
2358 struct its_baser *baser;
2359
2360 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2361
2362 /* Don't allow device id that exceeds ITS hardware limit */
2363 if (!baser)
2364 return (ilog2(dev_id) < its->device_ids);
2365
2366 return its_alloc_table_entry(its, baser, dev_id);
2367}
2368
2369static bool its_alloc_vpe_table(u32 vpe_id)
2370{
2371 struct its_node *its;
2372
2373 /*
2374 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2375 * could try and only do it on ITSs corresponding to devices
2376 * that have interrupts targeted at this VPE, but the
2377 * complexity becomes crazy (and you have tons of memory
2378 * anyway, right?).
2379 */
2380 list_for_each_entry(its, &its_nodes, entry) {
2381 struct its_baser *baser;
2382
2383 if (!its->is_v4)
2384 continue;
2385
2386 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2387 if (!baser)
2388 return false;
2389
2390 if (!its_alloc_table_entry(its, baser, vpe_id))
2391 return false;
2392 }
2393
2394 return true;
2395}
2396
2397static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2398 int nvecs, bool alloc_lpis)
2399{
2400 struct its_device *dev;
2401 unsigned long *lpi_map = NULL;
2402 unsigned long flags;
2403 u16 *col_map = NULL;
2404 void *itt;
2405 int lpi_base;
2406 int nr_lpis;
2407 int nr_ites;
2408 int sz;
2409
2410 if (!its_alloc_device_table(its, dev_id))
2411 return NULL;
2412
2413 if (WARN_ON(!is_power_of_2(nvecs)))
2414 nvecs = roundup_pow_of_two(nvecs);
2415
2416 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2417 /*
2418 * Even if the device wants a single LPI, the ITT must be
2419 * sized as a power of two (and you need at least one bit...).
2420 */
2421 nr_ites = max(2, nvecs);
2422 sz = nr_ites * its->ite_size;
2423 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2424 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2425 if (alloc_lpis) {
2426 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2427 if (lpi_map)
2428 col_map = kcalloc(nr_lpis, sizeof(*col_map),
2429 GFP_KERNEL);
2430 } else {
2431 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2432 nr_lpis = 0;
2433 lpi_base = 0;
2434 }
2435
2436 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2437 kfree(dev);
2438 kfree(itt);
2439 kfree(lpi_map);
2440 kfree(col_map);
2441 return NULL;
2442 }
2443
2444 gic_flush_dcache_to_poc(itt, sz);
2445
2446 dev->its = its;
2447 dev->itt = itt;
2448 dev->nr_ites = nr_ites;
2449 dev->event_map.lpi_map = lpi_map;
2450 dev->event_map.col_map = col_map;
2451 dev->event_map.lpi_base = lpi_base;
2452 dev->event_map.nr_lpis = nr_lpis;
2453 mutex_init(&dev->event_map.vlpi_lock);
2454 dev->device_id = dev_id;
2455 INIT_LIST_HEAD(&dev->entry);
2456
2457 raw_spin_lock_irqsave(&its->lock, flags);
2458 list_add(&dev->entry, &its->its_device_list);
2459 raw_spin_unlock_irqrestore(&its->lock, flags);
2460
2461 /* Map device to its ITT */
2462 its_send_mapd(dev, 1);
2463
2464 return dev;
2465}
2466
2467static void its_free_device(struct its_device *its_dev)
2468{
2469 unsigned long flags;
2470
2471 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2472 list_del(&its_dev->entry);
2473 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2474 kfree(its_dev->itt);
2475 kfree(its_dev);
2476}
2477
2478static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2479{
2480 int idx;
2481
2482 /* Find a free LPI region in lpi_map and allocate them. */
2483 idx = bitmap_find_free_region(dev->event_map.lpi_map,
2484 dev->event_map.nr_lpis,
2485 get_count_order(nvecs));
2486 if (idx < 0)
2487 return -ENOSPC;
2488
2489 *hwirq = dev->event_map.lpi_base + idx;
2490
2491 return 0;
2492}
2493
2494static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2495 int nvec, msi_alloc_info_t *info)
2496{
2497 struct its_node *its;
2498 struct its_device *its_dev;
2499 struct msi_domain_info *msi_info;
2500 u32 dev_id;
2501 int err = 0;
2502
2503 /*
2504 * We ignore "dev" entirely, and rely on the dev_id that has
2505 * been passed via the scratchpad. This limits this domain's
2506 * usefulness to upper layers that definitely know that they
2507 * are built on top of the ITS.
2508 */
2509 dev_id = info->scratchpad[0].ul;
2510
2511 msi_info = msi_get_domain_info(domain);
2512 its = msi_info->data;
2513
2514 if (!gic_rdists->has_direct_lpi &&
2515 vpe_proxy.dev &&
2516 vpe_proxy.dev->its == its &&
2517 dev_id == vpe_proxy.dev->device_id) {
2518 /* Bad luck. Get yourself a better implementation */
2519 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2520 dev_id);
2521 return -EINVAL;
2522 }
2523
2524 mutex_lock(&its->dev_alloc_lock);
2525 its_dev = its_find_device(its, dev_id);
2526 if (its_dev) {
2527 /*
2528 * We already have seen this ID, probably through
2529 * another alias (PCI bridge of some sort). No need to
2530 * create the device.
2531 */
2532 its_dev->shared = true;
2533 pr_debug("Reusing ITT for devID %x\n", dev_id);
2534 goto out;
2535 }
2536
2537 its_dev = its_create_device(its, dev_id, nvec, true);
2538 if (!its_dev) {
2539 err = -ENOMEM;
2540 goto out;
2541 }
2542
2543 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2544out:
2545 mutex_unlock(&its->dev_alloc_lock);
2546 info->scratchpad[0].ptr = its_dev;
2547 return err;
2548}
2549
2550static struct msi_domain_ops its_msi_domain_ops = {
2551 .msi_prepare = its_msi_prepare,
2552};
2553
2554static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2555 unsigned int virq,
2556 irq_hw_number_t hwirq)
2557{
2558 struct irq_fwspec fwspec;
2559
2560 if (irq_domain_get_of_node(domain->parent)) {
2561 fwspec.fwnode = domain->parent->fwnode;
2562 fwspec.param_count = 3;
2563 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2564 fwspec.param[1] = hwirq;
2565 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2566 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2567 fwspec.fwnode = domain->parent->fwnode;
2568 fwspec.param_count = 2;
2569 fwspec.param[0] = hwirq;
2570 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2571 } else {
2572 return -EINVAL;
2573 }
2574
2575 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2576}
2577
2578static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2579 unsigned int nr_irqs, void *args)
2580{
2581 msi_alloc_info_t *info = args;
2582 struct its_device *its_dev = info->scratchpad[0].ptr;
2583 struct its_node *its = its_dev->its;
2584 irq_hw_number_t hwirq;
2585 int err;
2586 int i;
2587
2588 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2589 if (err)
2590 return err;
2591
2592 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2593 if (err)
2594 return err;
2595
2596 for (i = 0; i < nr_irqs; i++) {
2597 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2598 if (err)
2599 return err;
2600
2601 irq_domain_set_hwirq_and_chip(domain, virq + i,
2602 hwirq + i, &its_irq_chip, its_dev);
2603 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2604 pr_debug("ID:%d pID:%d vID:%d\n",
2605 (int)(hwirq + i - its_dev->event_map.lpi_base),
2606 (int)(hwirq + i), virq + i);
2607 }
2608
2609 return 0;
2610}
2611
2612static int its_irq_domain_activate(struct irq_domain *domain,
2613 struct irq_data *d, bool reserve)
2614{
2615 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2616 u32 event = its_get_event_id(d);
2617 const struct cpumask *cpu_mask = cpu_online_mask;
2618 int cpu;
2619
2620 /* get the cpu_mask of local node */
2621 if (its_dev->its->numa_node >= 0)
2622 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2623
2624 /* Bind the LPI to the first possible CPU */
2625 cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2626 if (cpu >= nr_cpu_ids) {
2627 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2628 return -EINVAL;
2629
2630 cpu = cpumask_first(cpu_online_mask);
2631 }
2632
2633 its_dev->event_map.col_map[event] = cpu;
2634 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2635
2636 /* Map the GIC IRQ and event to the device */
2637 its_send_mapti(its_dev, d->hwirq, event);
2638 return 0;
2639}
2640
2641static void its_irq_domain_deactivate(struct irq_domain *domain,
2642 struct irq_data *d)
2643{
2644 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2645 u32 event = its_get_event_id(d);
2646
2647 /* Stop the delivery of interrupts */
2648 its_send_discard(its_dev, event);
2649}
2650
2651static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2652 unsigned int nr_irqs)
2653{
2654 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2655 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2656 struct its_node *its = its_dev->its;
2657 int i;
2658
2659 bitmap_release_region(its_dev->event_map.lpi_map,
2660 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
2661 get_count_order(nr_irqs));
2662
2663 for (i = 0; i < nr_irqs; i++) {
2664 struct irq_data *data = irq_domain_get_irq_data(domain,
2665 virq + i);
2666 /* Nuke the entry in the domain */
2667 irq_domain_reset_irq_data(data);
2668 }
2669
2670 mutex_lock(&its->dev_alloc_lock);
2671
2672 /*
2673 * If all interrupts have been freed, start mopping the
2674 * floor. This is conditionned on the device not being shared.
2675 */
2676 if (!its_dev->shared &&
2677 bitmap_empty(its_dev->event_map.lpi_map,
2678 its_dev->event_map.nr_lpis)) {
2679 its_lpi_free(its_dev->event_map.lpi_map,
2680 its_dev->event_map.lpi_base,
2681 its_dev->event_map.nr_lpis);
2682 kfree(its_dev->event_map.col_map);
2683
2684 /* Unmap device/itt */
2685 its_send_mapd(its_dev, 0);
2686 its_free_device(its_dev);
2687 }
2688
2689 mutex_unlock(&its->dev_alloc_lock);
2690
2691 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2692}
2693
2694static const struct irq_domain_ops its_domain_ops = {
2695 .alloc = its_irq_domain_alloc,
2696 .free = its_irq_domain_free,
2697 .activate = its_irq_domain_activate,
2698 .deactivate = its_irq_domain_deactivate,
2699};
2700
2701/*
2702 * This is insane.
2703 *
2704 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2705 * likely), the only way to perform an invalidate is to use a fake
2706 * device to issue an INV command, implying that the LPI has first
2707 * been mapped to some event on that device. Since this is not exactly
2708 * cheap, we try to keep that mapping around as long as possible, and
2709 * only issue an UNMAP if we're short on available slots.
2710 *
2711 * Broken by design(tm).
2712 */
2713static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2714{
2715 /* Already unmapped? */
2716 if (vpe->vpe_proxy_event == -1)
2717 return;
2718
2719 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2720 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2721
2722 /*
2723 * We don't track empty slots at all, so let's move the
2724 * next_victim pointer if we can quickly reuse that slot
2725 * instead of nuking an existing entry. Not clear that this is
2726 * always a win though, and this might just generate a ripple
2727 * effect... Let's just hope VPEs don't migrate too often.
2728 */
2729 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2730 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2731
2732 vpe->vpe_proxy_event = -1;
2733}
2734
2735static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2736{
2737 if (!gic_rdists->has_direct_lpi) {
2738 unsigned long flags;
2739
2740 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2741 its_vpe_db_proxy_unmap_locked(vpe);
2742 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2743 }
2744}
2745
2746static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2747{
2748 /* Already mapped? */
2749 if (vpe->vpe_proxy_event != -1)
2750 return;
2751
2752 /* This slot was already allocated. Kick the other VPE out. */
2753 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2754 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2755
2756 /* Map the new VPE instead */
2757 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2758 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2759 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2760
2761 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2762 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2763}
2764
2765static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2766{
2767 unsigned long flags;
2768 struct its_collection *target_col;
2769
2770 if (gic_rdists->has_direct_lpi) {
2771 void __iomem *rdbase;
2772
2773 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2774 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2775 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2776 cpu_relax();
2777
2778 return;
2779 }
2780
2781 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2782
2783 its_vpe_db_proxy_map_locked(vpe);
2784
2785 target_col = &vpe_proxy.dev->its->collections[to];
2786 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2787 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2788
2789 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2790}
2791
2792static int its_vpe_set_affinity(struct irq_data *d,
2793 const struct cpumask *mask_val,
2794 bool force)
2795{
2796 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2797 int cpu = cpumask_first(mask_val);
2798
2799 /*
2800 * Changing affinity is mega expensive, so let's be as lazy as
2801 * we can and only do it if we really have to. Also, if mapped
2802 * into the proxy device, we need to move the doorbell
2803 * interrupt to its new location.
2804 */
2805 if (vpe->col_idx != cpu) {
2806 int from = vpe->col_idx;
2807
2808 vpe->col_idx = cpu;
2809 its_send_vmovp(vpe);
2810 its_vpe_db_proxy_move(vpe, from, cpu);
2811 }
2812
2813 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2814
2815 return IRQ_SET_MASK_OK_DONE;
2816}
2817
2818static void its_vpe_schedule(struct its_vpe *vpe)
2819{
2820 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2821 u64 val;
2822
2823 /* Schedule the VPE */
2824 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2825 GENMASK_ULL(51, 12);
2826 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2827 val |= GICR_VPROPBASER_RaWb;
2828 val |= GICR_VPROPBASER_InnerShareable;
2829 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2830
2831 val = virt_to_phys(page_address(vpe->vpt_page)) &
2832 GENMASK_ULL(51, 16);
2833 val |= GICR_VPENDBASER_RaWaWb;
2834 val |= GICR_VPENDBASER_NonShareable;
2835 /*
2836 * There is no good way of finding out if the pending table is
2837 * empty as we can race against the doorbell interrupt very
2838 * easily. So in the end, vpe->pending_last is only an
2839 * indication that the vcpu has something pending, not one
2840 * that the pending table is empty. A good implementation
2841 * would be able to read its coarse map pretty quickly anyway,
2842 * making this a tolerable issue.
2843 */
2844 val |= GICR_VPENDBASER_PendingLast;
2845 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2846 val |= GICR_VPENDBASER_Valid;
2847 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2848}
2849
2850static void its_vpe_deschedule(struct its_vpe *vpe)
2851{
2852 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2853 u64 val;
2854
2855 val = its_clear_vpend_valid(vlpi_base);
2856
2857 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2858 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2859 vpe->idai = false;
2860 vpe->pending_last = true;
2861 } else {
2862 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2863 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2864 }
2865}
2866
2867static void its_vpe_invall(struct its_vpe *vpe)
2868{
2869 struct its_node *its;
2870
2871 list_for_each_entry(its, &its_nodes, entry) {
2872 if (!its->is_v4)
2873 continue;
2874
2875 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2876 continue;
2877
2878 /*
2879 * Sending a VINVALL to a single ITS is enough, as all
2880 * we need is to reach the redistributors.
2881 */
2882 its_send_vinvall(its, vpe);
2883 return;
2884 }
2885}
2886
2887static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2888{
2889 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2890 struct its_cmd_info *info = vcpu_info;
2891
2892 switch (info->cmd_type) {
2893 case SCHEDULE_VPE:
2894 its_vpe_schedule(vpe);
2895 return 0;
2896
2897 case DESCHEDULE_VPE:
2898 its_vpe_deschedule(vpe);
2899 return 0;
2900
2901 case INVALL_VPE:
2902 its_vpe_invall(vpe);
2903 return 0;
2904
2905 default:
2906 return -EINVAL;
2907 }
2908}
2909
2910static void its_vpe_send_cmd(struct its_vpe *vpe,
2911 void (*cmd)(struct its_device *, u32))
2912{
2913 unsigned long flags;
2914
2915 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2916
2917 its_vpe_db_proxy_map_locked(vpe);
2918 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2919
2920 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2921}
2922
2923static void its_vpe_send_inv(struct irq_data *d)
2924{
2925 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2926
2927 if (gic_rdists->has_direct_lpi) {
2928 void __iomem *rdbase;
2929
2930 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2931 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2932 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2933 cpu_relax();
2934 } else {
2935 its_vpe_send_cmd(vpe, its_send_inv);
2936 }
2937}
2938
2939static void its_vpe_mask_irq(struct irq_data *d)
2940{
2941 /*
2942 * We need to unmask the LPI, which is described by the parent
2943 * irq_data. Instead of calling into the parent (which won't
2944 * exactly do the right thing, let's simply use the
2945 * parent_data pointer. Yes, I'm naughty.
2946 */
2947 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2948 its_vpe_send_inv(d);
2949}
2950
2951static void its_vpe_unmask_irq(struct irq_data *d)
2952{
2953 /* Same hack as above... */
2954 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2955 its_vpe_send_inv(d);
2956}
2957
2958static int its_vpe_set_irqchip_state(struct irq_data *d,
2959 enum irqchip_irq_state which,
2960 bool state)
2961{
2962 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2963
2964 if (which != IRQCHIP_STATE_PENDING)
2965 return -EINVAL;
2966
2967 if (gic_rdists->has_direct_lpi) {
2968 void __iomem *rdbase;
2969
2970 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2971 if (state) {
2972 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2973 } else {
2974 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2975 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2976 cpu_relax();
2977 }
2978 } else {
2979 if (state)
2980 its_vpe_send_cmd(vpe, its_send_int);
2981 else
2982 its_vpe_send_cmd(vpe, its_send_clear);
2983 }
2984
2985 return 0;
2986}
2987
2988static struct irq_chip its_vpe_irq_chip = {
2989 .name = "GICv4-vpe",
2990 .irq_mask = its_vpe_mask_irq,
2991 .irq_unmask = its_vpe_unmask_irq,
2992 .irq_eoi = irq_chip_eoi_parent,
2993 .irq_set_affinity = its_vpe_set_affinity,
2994 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
2995 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
2996};
2997
2998static int its_vpe_id_alloc(void)
2999{
3000 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
3001}
3002
3003static void its_vpe_id_free(u16 id)
3004{
3005 ida_simple_remove(&its_vpeid_ida, id);
3006}
3007
3008static int its_vpe_init(struct its_vpe *vpe)
3009{
3010 struct page *vpt_page;
3011 int vpe_id;
3012
3013 /* Allocate vpe_id */
3014 vpe_id = its_vpe_id_alloc();
3015 if (vpe_id < 0)
3016 return vpe_id;
3017
3018 /* Allocate VPT */
3019 vpt_page = its_allocate_pending_table(GFP_KERNEL);
3020 if (!vpt_page) {
3021 its_vpe_id_free(vpe_id);
3022 return -ENOMEM;
3023 }
3024
3025 if (!its_alloc_vpe_table(vpe_id)) {
3026 its_vpe_id_free(vpe_id);
3027 its_free_pending_table(vpt_page);
3028 return -ENOMEM;
3029 }
3030
3031 vpe->vpe_id = vpe_id;
3032 vpe->vpt_page = vpt_page;
3033 vpe->vpe_proxy_event = -1;
3034
3035 return 0;
3036}
3037
3038static void its_vpe_teardown(struct its_vpe *vpe)
3039{
3040 its_vpe_db_proxy_unmap(vpe);
3041 its_vpe_id_free(vpe->vpe_id);
3042 its_free_pending_table(vpe->vpt_page);
3043}
3044
3045static void its_vpe_irq_domain_free(struct irq_domain *domain,
3046 unsigned int virq,
3047 unsigned int nr_irqs)
3048{
3049 struct its_vm *vm = domain->host_data;
3050 int i;
3051
3052 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3053
3054 for (i = 0; i < nr_irqs; i++) {
3055 struct irq_data *data = irq_domain_get_irq_data(domain,
3056 virq + i);
3057 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3058
3059 BUG_ON(vm != vpe->its_vm);
3060
3061 clear_bit(data->hwirq, vm->db_bitmap);
3062 its_vpe_teardown(vpe);
3063 irq_domain_reset_irq_data(data);
3064 }
3065
3066 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3067 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3068 its_free_prop_table(vm->vprop_page);
3069 }
3070}
3071
3072static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3073 unsigned int nr_irqs, void *args)
3074{
3075 struct its_vm *vm = args;
3076 unsigned long *bitmap;
3077 struct page *vprop_page;
3078 int base, nr_ids, i, err = 0;
3079
3080 BUG_ON(!vm);
3081
3082 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3083 if (!bitmap)
3084 return -ENOMEM;
3085
3086 if (nr_ids < nr_irqs) {
3087 its_lpi_free(bitmap, base, nr_ids);
3088 return -ENOMEM;
3089 }
3090
3091 vprop_page = its_allocate_prop_table(GFP_KERNEL);
3092 if (!vprop_page) {
3093 its_lpi_free(bitmap, base, nr_ids);
3094 return -ENOMEM;
3095 }
3096
3097 vm->db_bitmap = bitmap;
3098 vm->db_lpi_base = base;
3099 vm->nr_db_lpis = nr_ids;
3100 vm->vprop_page = vprop_page;
3101
3102 for (i = 0; i < nr_irqs; i++) {
3103 vm->vpes[i]->vpe_db_lpi = base + i;
3104 err = its_vpe_init(vm->vpes[i]);
3105 if (err)
3106 break;
3107 err = its_irq_gic_domain_alloc(domain, virq + i,
3108 vm->vpes[i]->vpe_db_lpi);
3109 if (err)
3110 break;
3111 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3112 &its_vpe_irq_chip, vm->vpes[i]);
3113 set_bit(i, bitmap);
3114 }
3115
3116 if (err) {
3117 if (i > 0)
3118 its_vpe_irq_domain_free(domain, virq, i - 1);
3119
3120 its_lpi_free(bitmap, base, nr_ids);
3121 its_free_prop_table(vprop_page);
3122 }
3123
3124 return err;
3125}
3126
3127static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3128 struct irq_data *d, bool reserve)
3129{
3130 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3131 struct its_node *its;
3132
3133 /* If we use the list map, we issue VMAPP on demand... */
3134 if (its_list_map)
3135 return 0;
3136
3137 /* Map the VPE to the first possible CPU */
3138 vpe->col_idx = cpumask_first(cpu_online_mask);
3139
3140 list_for_each_entry(its, &its_nodes, entry) {
3141 if (!its->is_v4)
3142 continue;
3143
3144 its_send_vmapp(its, vpe, true);
3145 its_send_vinvall(its, vpe);
3146 }
3147
3148 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3149
3150 return 0;
3151}
3152
3153static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3154 struct irq_data *d)
3155{
3156 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3157 struct its_node *its;
3158
3159 /*
3160 * If we use the list map, we unmap the VPE once no VLPIs are
3161 * associated with the VM.
3162 */
3163 if (its_list_map)
3164 return;
3165
3166 list_for_each_entry(its, &its_nodes, entry) {
3167 if (!its->is_v4)
3168 continue;
3169
3170 its_send_vmapp(its, vpe, false);
3171 }
3172}
3173
3174static const struct irq_domain_ops its_vpe_domain_ops = {
3175 .alloc = its_vpe_irq_domain_alloc,
3176 .free = its_vpe_irq_domain_free,
3177 .activate = its_vpe_irq_domain_activate,
3178 .deactivate = its_vpe_irq_domain_deactivate,
3179};
3180
3181static int its_force_quiescent(void __iomem *base)
3182{
3183 u32 count = 1000000; /* 1s */
3184 u32 val;
3185
3186 val = readl_relaxed(base + GITS_CTLR);
3187 /*
3188 * GIC architecture specification requires the ITS to be both
3189 * disabled and quiescent for writes to GITS_BASER<n> or
3190 * GITS_CBASER to not have UNPREDICTABLE results.
3191 */
3192 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3193 return 0;
3194
3195 /* Disable the generation of all interrupts to this ITS */
3196 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3197 writel_relaxed(val, base + GITS_CTLR);
3198
3199 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3200 while (1) {
3201 val = readl_relaxed(base + GITS_CTLR);
3202 if (val & GITS_CTLR_QUIESCENT)
3203 return 0;
3204
3205 count--;
3206 if (!count)
3207 return -EBUSY;
3208
3209 cpu_relax();
3210 udelay(1);
3211 }
3212}
3213
3214static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3215{
3216 struct its_node *its = data;
3217
3218 /* erratum 22375: only alloc 8MB table size */
3219 its->device_ids = 0x14; /* 20 bits, 8MB */
3220 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3221
3222 return true;
3223}
3224
3225static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3226{
3227 struct its_node *its = data;
3228
3229 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3230
3231 return true;
3232}
3233
3234static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3235{
3236 struct its_node *its = data;
3237
3238 /* On QDF2400, the size of the ITE is 16Bytes */
3239 its->ite_size = 16;
3240
3241 return true;
3242}
3243
3244static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3245{
3246 struct its_node *its = its_dev->its;
3247
3248 /*
3249 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3250 * which maps 32-bit writes targeted at a separate window of
3251 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3252 * with device ID taken from bits [device_id_bits + 1:2] of
3253 * the window offset.
3254 */
3255 return its->pre_its_base + (its_dev->device_id << 2);
3256}
3257
3258static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3259{
3260 struct its_node *its = data;
3261 u32 pre_its_window[2];
3262 u32 ids;
3263
3264 if (!fwnode_property_read_u32_array(its->fwnode_handle,
3265 "socionext,synquacer-pre-its",
3266 pre_its_window,
3267 ARRAY_SIZE(pre_its_window))) {
3268
3269 its->pre_its_base = pre_its_window[0];
3270 its->get_msi_base = its_irq_get_msi_base_pre_its;
3271
3272 ids = ilog2(pre_its_window[1]) - 2;
3273 if (its->device_ids > ids)
3274 its->device_ids = ids;
3275
3276 /* the pre-ITS breaks isolation, so disable MSI remapping */
3277 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3278 return true;
3279 }
3280 return false;
3281}
3282
3283static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3284{
3285 struct its_node *its = data;
3286
3287 /*
3288 * Hip07 insists on using the wrong address for the VLPI
3289 * page. Trick it into doing the right thing...
3290 */
3291 its->vlpi_redist_offset = SZ_128K;
3292 return true;
3293}
3294
3295static const struct gic_quirk its_quirks[] = {
3296#ifdef CONFIG_CAVIUM_ERRATUM_22375
3297 {
3298 .desc = "ITS: Cavium errata 22375, 24313",
3299 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3300 .mask = 0xffff0fff,
3301 .init = its_enable_quirk_cavium_22375,
3302 },
3303#endif
3304#ifdef CONFIG_CAVIUM_ERRATUM_23144
3305 {
3306 .desc = "ITS: Cavium erratum 23144",
3307 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3308 .mask = 0xffff0fff,
3309 .init = its_enable_quirk_cavium_23144,
3310 },
3311#endif
3312#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3313 {
3314 .desc = "ITS: QDF2400 erratum 0065",
3315 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
3316 .mask = 0xffffffff,
3317 .init = its_enable_quirk_qdf2400_e0065,
3318 },
3319#endif
3320#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3321 {
3322 /*
3323 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3324 * implementation, but with a 'pre-ITS' added that requires
3325 * special handling in software.
3326 */
3327 .desc = "ITS: Socionext Synquacer pre-ITS",
3328 .iidr = 0x0001143b,
3329 .mask = 0xffffffff,
3330 .init = its_enable_quirk_socionext_synquacer,
3331 },
3332#endif
3333#ifdef CONFIG_HISILICON_ERRATUM_161600802
3334 {
3335 .desc = "ITS: Hip07 erratum 161600802",
3336 .iidr = 0x00000004,
3337 .mask = 0xffffffff,
3338 .init = its_enable_quirk_hip07_161600802,
3339 },
3340#endif
3341 {
3342 }
3343};
3344
3345static void its_enable_quirks(struct its_node *its)
3346{
3347 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3348
3349 gic_enable_quirks(iidr, its_quirks, its);
3350}
3351
3352static int its_save_disable(void)
3353{
3354 struct its_node *its;
3355 int err = 0;
3356
3357 raw_spin_lock(&its_lock);
3358 list_for_each_entry(its, &its_nodes, entry) {
3359 void __iomem *base;
3360
3361 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3362 continue;
3363
3364 base = its->base;
3365 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3366 err = its_force_quiescent(base);
3367 if (err) {
3368 pr_err("ITS@%pa: failed to quiesce: %d\n",
3369 &its->phys_base, err);
3370 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3371 goto err;
3372 }
3373
3374 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3375 }
3376
3377err:
3378 if (err) {
3379 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3380 void __iomem *base;
3381
3382 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3383 continue;
3384
3385 base = its->base;
3386 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3387 }
3388 }
3389 raw_spin_unlock(&its_lock);
3390
3391 return err;
3392}
3393
3394static void its_restore_enable(void)
3395{
3396 struct its_node *its;
3397 int ret;
3398
3399 raw_spin_lock(&its_lock);
3400 list_for_each_entry(its, &its_nodes, entry) {
3401 void __iomem *base;
3402 int i;
3403
3404 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3405 continue;
3406
3407 base = its->base;
3408
3409 /*
3410 * Make sure that the ITS is disabled. If it fails to quiesce,
3411 * don't restore it since writing to CBASER or BASER<n>
3412 * registers is undefined according to the GIC v3 ITS
3413 * Specification.
3414 */
3415 ret = its_force_quiescent(base);
3416 if (ret) {
3417 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3418 &its->phys_base, ret);
3419 continue;
3420 }
3421
3422 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3423
3424 /*
3425 * Writing CBASER resets CREADR to 0, so make CWRITER and
3426 * cmd_write line up with it.
3427 */
3428 its->cmd_write = its->cmd_base;
3429 gits_write_cwriter(0, base + GITS_CWRITER);
3430
3431 /* Restore GITS_BASER from the value cache. */
3432 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3433 struct its_baser *baser = &its->tables[i];
3434
3435 if (!(baser->val & GITS_BASER_VALID))
3436 continue;
3437
3438 its_write_baser(its, baser, baser->val);
3439 }
3440 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3441
3442 /*
3443 * Reinit the collection if it's stored in the ITS. This is
3444 * indicated by the col_id being less than the HCC field.
3445 * CID < HCC as specified in the GIC v3 Documentation.
3446 */
3447 if (its->collections[smp_processor_id()].col_id <
3448 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3449 its_cpu_init_collection(its);
3450 }
3451 raw_spin_unlock(&its_lock);
3452}
3453
3454static struct syscore_ops its_syscore_ops = {
3455 .suspend = its_save_disable,
3456 .resume = its_restore_enable,
3457};
3458
3459static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3460{
3461 struct irq_domain *inner_domain;
3462 struct msi_domain_info *info;
3463
3464 info = kzalloc(sizeof(*info), GFP_KERNEL);
3465 if (!info)
3466 return -ENOMEM;
3467
3468 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3469 if (!inner_domain) {
3470 kfree(info);
3471 return -ENOMEM;
3472 }
3473
3474 inner_domain->parent = its_parent;
3475 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3476 inner_domain->flags |= its->msi_domain_flags;
3477 info->ops = &its_msi_domain_ops;
3478 info->data = its;
3479 inner_domain->host_data = info;
3480
3481 return 0;
3482}
3483
3484static int its_init_vpe_domain(void)
3485{
3486 struct its_node *its;
3487 u32 devid;
3488 int entries;
3489
3490 if (gic_rdists->has_direct_lpi) {
3491 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3492 return 0;
3493 }
3494
3495 /* Any ITS will do, even if not v4 */
3496 its = list_first_entry(&its_nodes, struct its_node, entry);
3497
3498 entries = roundup_pow_of_two(nr_cpu_ids);
3499 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3500 GFP_KERNEL);
3501 if (!vpe_proxy.vpes) {
3502 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3503 return -ENOMEM;
3504 }
3505
3506 /* Use the last possible DevID */
3507 devid = GENMASK(its->device_ids - 1, 0);
3508 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3509 if (!vpe_proxy.dev) {
3510 kfree(vpe_proxy.vpes);
3511 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3512 return -ENOMEM;
3513 }
3514
3515 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3516
3517 raw_spin_lock_init(&vpe_proxy.lock);
3518 vpe_proxy.next_victim = 0;
3519 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3520 devid, vpe_proxy.dev->nr_ites);
3521
3522 return 0;
3523}
3524
3525static int __init its_compute_its_list_map(struct resource *res,
3526 void __iomem *its_base)
3527{
3528 int its_number;
3529 u32 ctlr;
3530
3531 /*
3532 * This is assumed to be done early enough that we're
3533 * guaranteed to be single-threaded, hence no
3534 * locking. Should this change, we should address
3535 * this.
3536 */
3537 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3538 if (its_number >= GICv4_ITS_LIST_MAX) {
3539 pr_err("ITS@%pa: No ITSList entry available!\n",
3540 &res->start);
3541 return -EINVAL;
3542 }
3543
3544 ctlr = readl_relaxed(its_base + GITS_CTLR);
3545 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3546 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3547 writel_relaxed(ctlr, its_base + GITS_CTLR);
3548 ctlr = readl_relaxed(its_base + GITS_CTLR);
3549 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3550 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3551 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3552 }
3553
3554 if (test_and_set_bit(its_number, &its_list_map)) {
3555 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3556 &res->start, its_number);
3557 return -EINVAL;
3558 }
3559
3560 return its_number;
3561}
3562
3563static int __init its_probe_one(struct resource *res,
3564 struct fwnode_handle *handle, int numa_node)
3565{
3566 struct its_node *its;
3567 void __iomem *its_base;
3568 u32 val, ctlr;
3569 u64 baser, tmp, typer;
3570 struct page *page;
3571 int err;
3572
3573 its_base = ioremap(res->start, resource_size(res));
3574 if (!its_base) {
3575 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3576 return -ENOMEM;
3577 }
3578
3579 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3580 if (val != 0x30 && val != 0x40) {
3581 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3582 err = -ENODEV;
3583 goto out_unmap;
3584 }
3585
3586 err = its_force_quiescent(its_base);
3587 if (err) {
3588 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3589 goto out_unmap;
3590 }
3591
3592 pr_info("ITS %pR\n", res);
3593
3594 its = kzalloc(sizeof(*its), GFP_KERNEL);
3595 if (!its) {
3596 err = -ENOMEM;
3597 goto out_unmap;
3598 }
3599
3600 raw_spin_lock_init(&its->lock);
3601 mutex_init(&its->dev_alloc_lock);
3602 INIT_LIST_HEAD(&its->entry);
3603 INIT_LIST_HEAD(&its->its_device_list);
3604 typer = gic_read_typer(its_base + GITS_TYPER);
3605 its->base = its_base;
3606 its->phys_base = res->start;
3607 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3608 its->device_ids = GITS_TYPER_DEVBITS(typer);
3609 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3610 if (its->is_v4) {
3611 if (!(typer & GITS_TYPER_VMOVP)) {
3612 err = its_compute_its_list_map(res, its_base);
3613 if (err < 0)
3614 goto out_free_its;
3615
3616 its->list_nr = err;
3617
3618 pr_info("ITS@%pa: Using ITS number %d\n",
3619 &res->start, err);
3620 } else {
3621 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3622 }
3623 }
3624
3625 its->numa_node = numa_node;
3626
3627 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3628 get_order(ITS_CMD_QUEUE_SZ));
3629 if (!page) {
3630 err = -ENOMEM;
3631 goto out_free_its;
3632 }
3633 its->cmd_base = (void *)page_address(page);
3634 its->cmd_write = its->cmd_base;
3635 its->fwnode_handle = handle;
3636 its->get_msi_base = its_irq_get_msi_base;
3637 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3638
3639 its_enable_quirks(its);
3640
3641 err = its_alloc_tables(its);
3642 if (err)
3643 goto out_free_cmd;
3644
3645 err = its_alloc_collections(its);
3646 if (err)
3647 goto out_free_tables;
3648
3649 baser = (virt_to_phys(its->cmd_base) |
3650 GITS_CBASER_RaWaWb |
3651 GITS_CBASER_InnerShareable |
3652 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3653 GITS_CBASER_VALID);
3654
3655 gits_write_cbaser(baser, its->base + GITS_CBASER);
3656 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3657
3658 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3659 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3660 /*
3661 * The HW reports non-shareable, we must
3662 * remove the cacheability attributes as
3663 * well.
3664 */
3665 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3666 GITS_CBASER_CACHEABILITY_MASK);
3667 baser |= GITS_CBASER_nC;
3668 gits_write_cbaser(baser, its->base + GITS_CBASER);
3669 }
3670 pr_info("ITS: using cache flushing for cmd queue\n");
3671 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3672 }
3673
3674 gits_write_cwriter(0, its->base + GITS_CWRITER);
3675 ctlr = readl_relaxed(its->base + GITS_CTLR);
3676 ctlr |= GITS_CTLR_ENABLE;
3677 if (its->is_v4)
3678 ctlr |= GITS_CTLR_ImDe;
3679 writel_relaxed(ctlr, its->base + GITS_CTLR);
3680
3681 if (GITS_TYPER_HCC(typer))
3682 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3683
3684 err = its_init_domain(handle, its);
3685 if (err)
3686 goto out_free_tables;
3687
3688 raw_spin_lock(&its_lock);
3689 list_add(&its->entry, &its_nodes);
3690 raw_spin_unlock(&its_lock);
3691
3692 return 0;
3693
3694out_free_tables:
3695 its_free_tables(its);
3696out_free_cmd:
3697 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3698out_free_its:
3699 kfree(its);
3700out_unmap:
3701 iounmap(its_base);
3702 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3703 return err;
3704}
3705
3706static bool gic_rdists_supports_plpis(void)
3707{
3708 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3709}
3710
3711static int redist_disable_lpis(void)
3712{
3713 void __iomem *rbase = gic_data_rdist_rd_base();
3714 u64 timeout = USEC_PER_SEC;
3715 u64 val;
3716
3717 if (!gic_rdists_supports_plpis()) {
3718 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3719 return -ENXIO;
3720 }
3721
3722 val = readl_relaxed(rbase + GICR_CTLR);
3723 if (!(val & GICR_CTLR_ENABLE_LPIS))
3724 return 0;
3725
3726 /*
3727 * If coming via a CPU hotplug event, we don't need to disable
3728 * LPIs before trying to re-enable them. They are already
3729 * configured and all is well in the world.
3730 *
3731 * If running with preallocated tables, there is nothing to do.
3732 */
3733 if (gic_data_rdist()->lpi_enabled ||
3734 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3735 return 0;
3736
3737 /*
3738 * From that point on, we only try to do some damage control.
3739 */
3740 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3741 smp_processor_id());
3742 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3743
3744 /* Disable LPIs */
3745 val &= ~GICR_CTLR_ENABLE_LPIS;
3746 writel_relaxed(val, rbase + GICR_CTLR);
3747
3748 /* Make sure any change to GICR_CTLR is observable by the GIC */
3749 dsb(sy);
3750
3751 /*
3752 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3753 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3754 * Error out if we time out waiting for RWP to clear.
3755 */
3756 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3757 if (!timeout) {
3758 pr_err("CPU%d: Timeout while disabling LPIs\n",
3759 smp_processor_id());
3760 return -ETIMEDOUT;
3761 }
3762 udelay(1);
3763 timeout--;
3764 }
3765
3766 /*
3767 * After it has been written to 1, it is IMPLEMENTATION
3768 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3769 * cleared to 0. Error out if clearing the bit failed.
3770 */
3771 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3772 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3773 return -EBUSY;
3774 }
3775
3776 return 0;
3777}
3778
3779int its_cpu_init(void)
3780{
3781 if (!list_empty(&its_nodes)) {
3782 int ret;
3783
3784 ret = redist_disable_lpis();
3785 if (ret)
3786 return ret;
3787
3788 its_cpu_init_lpis();
3789 its_cpu_init_collections();
3790 }
3791
3792 return 0;
3793}
3794
3795static const struct of_device_id its_device_id[] = {
3796 { .compatible = "arm,gic-v3-its", },
3797 {},
3798};
3799
3800static int __init its_of_probe(struct device_node *node)
3801{
3802 struct device_node *np;
3803 struct resource res;
3804
3805 for (np = of_find_matching_node(node, its_device_id); np;
3806 np = of_find_matching_node(np, its_device_id)) {
3807 if (!of_device_is_available(np))
3808 continue;
3809 if (!of_property_read_bool(np, "msi-controller")) {
3810 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3811 np);
3812 continue;
3813 }
3814
3815 if (of_address_to_resource(np, 0, &res)) {
3816 pr_warn("%pOF: no regs?\n", np);
3817 continue;
3818 }
3819
3820 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3821 }
3822 return 0;
3823}
3824
3825#ifdef CONFIG_ACPI
3826
3827#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3828
3829#ifdef CONFIG_ACPI_NUMA
3830struct its_srat_map {
3831 /* numa node id */
3832 u32 numa_node;
3833 /* GIC ITS ID */
3834 u32 its_id;
3835};
3836
3837static struct its_srat_map *its_srat_maps __initdata;
3838static int its_in_srat __initdata;
3839
3840static int __init acpi_get_its_numa_node(u32 its_id)
3841{
3842 int i;
3843
3844 for (i = 0; i < its_in_srat; i++) {
3845 if (its_id == its_srat_maps[i].its_id)
3846 return its_srat_maps[i].numa_node;
3847 }
3848 return NUMA_NO_NODE;
3849}
3850
3851static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3852 const unsigned long end)
3853{
3854 return 0;
3855}
3856
3857static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3858 const unsigned long end)
3859{
3860 int node;
3861 struct acpi_srat_gic_its_affinity *its_affinity;
3862
3863 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3864 if (!its_affinity)
3865 return -EINVAL;
3866
3867 if (its_affinity->header.length < sizeof(*its_affinity)) {
3868 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3869 its_affinity->header.length);
3870 return -EINVAL;
3871 }
3872
3873 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3874
3875 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3876 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3877 return 0;
3878 }
3879
3880 its_srat_maps[its_in_srat].numa_node = node;
3881 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3882 its_in_srat++;
3883 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3884 its_affinity->proximity_domain, its_affinity->its_id, node);
3885
3886 return 0;
3887}
3888
3889static void __init acpi_table_parse_srat_its(void)
3890{
3891 int count;
3892
3893 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3894 sizeof(struct acpi_table_srat),
3895 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3896 gic_acpi_match_srat_its, 0);
3897 if (count <= 0)
3898 return;
3899
3900 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3901 GFP_KERNEL);
3902 if (!its_srat_maps) {
3903 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3904 return;
3905 }
3906
3907 acpi_table_parse_entries(ACPI_SIG_SRAT,
3908 sizeof(struct acpi_table_srat),
3909 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3910 gic_acpi_parse_srat_its, 0);
3911}
3912
3913/* free the its_srat_maps after ITS probing */
3914static void __init acpi_its_srat_maps_free(void)
3915{
3916 kfree(its_srat_maps);
3917}
3918#else
3919static void __init acpi_table_parse_srat_its(void) { }
3920static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3921static void __init acpi_its_srat_maps_free(void) { }
3922#endif
3923
3924static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3925 const unsigned long end)
3926{
3927 struct acpi_madt_generic_translator *its_entry;
3928 struct fwnode_handle *dom_handle;
3929 struct resource res;
3930 int err;
3931
3932 its_entry = (struct acpi_madt_generic_translator *)header;
3933 memset(&res, 0, sizeof(res));
3934 res.start = its_entry->base_address;
3935 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3936 res.flags = IORESOURCE_MEM;
3937
3938 dom_handle = irq_domain_alloc_fwnode(&res.start);
3939 if (!dom_handle) {
3940 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3941 &res.start);
3942 return -ENOMEM;
3943 }
3944
3945 err = iort_register_domain_token(its_entry->translation_id, res.start,
3946 dom_handle);
3947 if (err) {
3948 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3949 &res.start, its_entry->translation_id);
3950 goto dom_err;
3951 }
3952
3953 err = its_probe_one(&res, dom_handle,
3954 acpi_get_its_numa_node(its_entry->translation_id));
3955 if (!err)
3956 return 0;
3957
3958 iort_deregister_domain_token(its_entry->translation_id);
3959dom_err:
3960 irq_domain_free_fwnode(dom_handle);
3961 return err;
3962}
3963
3964static void __init its_acpi_probe(void)
3965{
3966 acpi_table_parse_srat_its();
3967 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3968 gic_acpi_parse_madt_its, 0);
3969 acpi_its_srat_maps_free();
3970}
3971#else
3972static void __init its_acpi_probe(void) { }
3973#endif
3974
3975int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3976 struct irq_domain *parent_domain)
3977{
3978 struct device_node *of_node;
3979 struct its_node *its;
3980 bool has_v4 = false;
3981 int err;
3982
3983 its_parent = parent_domain;
3984 of_node = to_of_node(handle);
3985 if (of_node)
3986 its_of_probe(of_node);
3987 else
3988 its_acpi_probe();
3989
3990 if (list_empty(&its_nodes)) {
3991 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3992 return -ENXIO;
3993 }
3994
3995 gic_rdists = rdists;
3996
3997 err = allocate_lpi_tables();
3998 if (err)
3999 return err;
4000
4001 list_for_each_entry(its, &its_nodes, entry)
4002 has_v4 |= its->is_v4;
4003
4004 if (has_v4 & rdists->has_vlpis) {
4005 if (its_init_vpe_domain() ||
4006 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
4007 rdists->has_vlpis = false;
4008 pr_err("ITS: Disabling GICv4 support\n");
4009 }
4010 }
4011
4012 register_syscore_ops(&its_syscore_ops);
4013
4014 return 0;
4015}