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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_ringbuffer.h"
26
27struct msm_gem_submit;
28struct msm_gpu_perfcntr;
29
30/* So far, with hardware that I've seen to date, we can have:
31 * + zero, one, or two z180 2d cores
32 * + a3xx or a2xx 3d core, which share a common CP (the firmware
33 * for the CP seems to implement some different PM4 packet types
34 * but the basics of cmdstream submission are the same)
35 *
36 * Which means that the eventual complete "class" hierarchy, once
37 * support for all past and present hw is in place, becomes:
38 * + msm_gpu
39 * + adreno_gpu
40 * + a3xx_gpu
41 * + a2xx_gpu
42 * + z180_gpu
43 */
44struct msm_gpu_funcs {
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
50 struct msm_file_private *ctx);
51 void (*flush)(struct msm_gpu *gpu);
52 void (*idle)(struct msm_gpu *gpu);
53 irqreturn_t (*irq)(struct msm_gpu *irq);
54 uint32_t (*last_fence)(struct msm_gpu *gpu);
55 void (*recover)(struct msm_gpu *gpu);
56 void (*destroy)(struct msm_gpu *gpu);
57#ifdef CONFIG_DEBUG_FS
58 /* show GPU status in debugfs: */
59 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
60#endif
61};
62
63struct msm_gpu {
64 const char *name;
65 struct drm_device *dev;
66 const struct msm_gpu_funcs *funcs;
67
68 /* performance counters (hw & sw): */
69 spinlock_t perf_lock;
70 bool perfcntr_active;
71 struct {
72 bool active;
73 ktime_t time;
74 } last_sample;
75 uint32_t totaltime, activetime; /* sw counters */
76 uint32_t last_cntrs[5]; /* hw counters */
77 const struct msm_gpu_perfcntr *perfcntrs;
78 uint32_t num_perfcntrs;
79
80 struct msm_ringbuffer *rb;
81 uint32_t rb_iova;
82
83 /* list of GEM active objects: */
84 struct list_head active_list;
85
86 uint32_t submitted_fence;
87
88 /* is gpu powered/active? */
89 int active_cnt;
90 bool inactive;
91
92 /* worker for handling active-list retiring: */
93 struct work_struct retire_work;
94
95 void __iomem *mmio;
96 int irq;
97
98 struct msm_mmu *mmu;
99 int id;
100
101 /* Power Control: */
102 struct regulator *gpu_reg, *gpu_cx;
103 struct clk *ebi1_clk, *grp_clks[6];
104 uint32_t fast_rate, slow_rate, bus_freq;
105
106#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
107 struct msm_bus_scale_pdata *bus_scale_table;
108 uint32_t bsc;
109#endif
110
111 /* Hang and Inactivity Detection:
112 */
113#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
114#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD)
115 struct timer_list inactive_timer;
116 struct work_struct inactive_work;
117#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
118#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
119 struct timer_list hangcheck_timer;
120 uint32_t hangcheck_fence;
121 struct work_struct recover_work;
122
123 struct list_head submit_list;
124};
125
126static inline bool msm_gpu_active(struct msm_gpu *gpu)
127{
128 return gpu->submitted_fence > gpu->funcs->last_fence(gpu);
129}
130
131/* Perf-Counters:
132 * The select_reg and select_val are just there for the benefit of the child
133 * class that actually enables the perf counter.. but msm_gpu base class
134 * will handle sampling/displaying the counters.
135 */
136
137struct msm_gpu_perfcntr {
138 uint32_t select_reg;
139 uint32_t sample_reg;
140 uint32_t select_val;
141 const char *name;
142};
143
144static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
145{
146 msm_writel(data, gpu->mmio + (reg << 2));
147}
148
149static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
150{
151 return msm_readl(gpu->mmio + (reg << 2));
152}
153
154int msm_gpu_pm_suspend(struct msm_gpu *gpu);
155int msm_gpu_pm_resume(struct msm_gpu *gpu);
156
157void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
158void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
159int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
160 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
161
162void msm_gpu_retire(struct msm_gpu *gpu);
163int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
164 struct msm_file_private *ctx);
165
166int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
167 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
168 const char *name, const char *ioname, const char *irqname, int ringsz);
169void msm_gpu_cleanup(struct msm_gpu *gpu);
170
171struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
172void __init adreno_register(void);
173void __exit adreno_unregister(void);
174
175#endif /* __MSM_GPU_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __MSM_GPU_H__
8#define __MSM_GPU_H__
9
10#include <linux/adreno-smmu-priv.h>
11#include <linux/clk.h>
12#include <linux/devfreq.h>
13#include <linux/interconnect.h>
14#include <linux/pm_opp.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17
18#include "msm_drv.h"
19#include "msm_fence.h"
20#include "msm_ringbuffer.h"
21#include "msm_gem.h"
22
23struct msm_gem_submit;
24struct msm_gpu_perfcntr;
25struct msm_gpu_state;
26struct msm_file_private;
27
28struct msm_gpu_config {
29 const char *ioname;
30 unsigned int nr_rings;
31};
32
33/* So far, with hardware that I've seen to date, we can have:
34 * + zero, one, or two z180 2d cores
35 * + a3xx or a2xx 3d core, which share a common CP (the firmware
36 * for the CP seems to implement some different PM4 packet types
37 * but the basics of cmdstream submission are the same)
38 *
39 * Which means that the eventual complete "class" hierarchy, once
40 * support for all past and present hw is in place, becomes:
41 * + msm_gpu
42 * + adreno_gpu
43 * + a3xx_gpu
44 * + a2xx_gpu
45 * + z180_gpu
46 */
47struct msm_gpu_funcs {
48 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
49 uint32_t param, uint64_t *value, uint32_t *len);
50 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
51 uint32_t param, uint64_t value, uint32_t len);
52 int (*hw_init)(struct msm_gpu *gpu);
53 int (*pm_suspend)(struct msm_gpu *gpu);
54 int (*pm_resume)(struct msm_gpu *gpu);
55 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
56 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
57 irqreturn_t (*irq)(struct msm_gpu *irq);
58 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
59 void (*recover)(struct msm_gpu *gpu);
60 void (*destroy)(struct msm_gpu *gpu);
61#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
62 /* show GPU status in debugfs: */
63 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
64 struct drm_printer *p);
65 /* for generation specific debugfs: */
66 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
67#endif
68 /* note: gpu_busy() can assume that we have been pm_resumed */
69 u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
70 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
71 int (*gpu_state_put)(struct msm_gpu_state *state);
72 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
73 /* note: gpu_set_freq() can assume that we have been pm_resumed */
74 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
75 bool suspended);
76 struct msm_gem_address_space *(*create_address_space)
77 (struct msm_gpu *gpu, struct platform_device *pdev);
78 struct msm_gem_address_space *(*create_private_address_space)
79 (struct msm_gpu *gpu);
80 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
81
82 /**
83 * progress: Has the GPU made progress?
84 *
85 * Return true if GPU position in cmdstream has advanced (or changed)
86 * since the last call. To avoid false negatives, this should account
87 * for cmdstream that is buffered in this FIFO upstream of the CP fw.
88 */
89 bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
90};
91
92/* Additional state for iommu faults: */
93struct msm_gpu_fault_info {
94 u64 ttbr0;
95 unsigned long iova;
96 int flags;
97 const char *type;
98 const char *block;
99};
100
101/**
102 * struct msm_gpu_devfreq - devfreq related state
103 */
104struct msm_gpu_devfreq {
105 /** devfreq: devfreq instance */
106 struct devfreq *devfreq;
107
108 /** lock: lock for "suspended", "busy_cycles", and "time" */
109 struct mutex lock;
110
111 /**
112 * idle_constraint:
113 *
114 * A PM QoS constraint to limit max freq while the GPU is idle.
115 */
116 struct dev_pm_qos_request idle_freq;
117
118 /**
119 * boost_constraint:
120 *
121 * A PM QoS constraint to boost min freq for a period of time
122 * until the boost expires.
123 */
124 struct dev_pm_qos_request boost_freq;
125
126 /**
127 * busy_cycles: Last busy counter value, for calculating elapsed busy
128 * cycles since last sampling period.
129 */
130 u64 busy_cycles;
131
132 /** time: Time of last sampling period. */
133 ktime_t time;
134
135 /** idle_time: Time of last transition to idle: */
136 ktime_t idle_time;
137
138 struct devfreq_dev_status average_status;
139
140 /**
141 * idle_work:
142 *
143 * Used to delay clamping to idle freq on active->idle transition.
144 */
145 struct msm_hrtimer_work idle_work;
146
147 /**
148 * boost_work:
149 *
150 * Used to reset the boost_constraint after the boost period has
151 * elapsed
152 */
153 struct msm_hrtimer_work boost_work;
154
155 /** suspended: tracks if we're suspended */
156 bool suspended;
157};
158
159struct msm_gpu {
160 const char *name;
161 struct drm_device *dev;
162 struct platform_device *pdev;
163 const struct msm_gpu_funcs *funcs;
164
165 struct adreno_smmu_priv adreno_smmu;
166
167 /* performance counters (hw & sw): */
168 spinlock_t perf_lock;
169 bool perfcntr_active;
170 struct {
171 bool active;
172 ktime_t time;
173 } last_sample;
174 uint32_t totaltime, activetime; /* sw counters */
175 uint32_t last_cntrs[5]; /* hw counters */
176 const struct msm_gpu_perfcntr *perfcntrs;
177 uint32_t num_perfcntrs;
178
179 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
180 int nr_rings;
181
182 /**
183 * sysprof_active:
184 *
185 * The count of contexts that have enabled system profiling.
186 */
187 refcount_t sysprof_active;
188
189 /**
190 * cur_ctx_seqno:
191 *
192 * The ctx->seqno value of the last context to submit rendering,
193 * and the one with current pgtables installed (for generations
194 * that support per-context pgtables). Tracked by seqno rather
195 * than pointer value to avoid dangling pointers, and cases where
196 * a ctx can be freed and a new one created with the same address.
197 */
198 int cur_ctx_seqno;
199
200 /**
201 * lock:
202 *
203 * General lock for serializing all the gpu things.
204 *
205 * TODO move to per-ring locking where feasible (ie. submit/retire
206 * path, etc)
207 */
208 struct mutex lock;
209
210 /**
211 * active_submits:
212 *
213 * The number of submitted but not yet retired submits, used to
214 * determine transitions between active and idle.
215 *
216 * Protected by active_lock
217 */
218 int active_submits;
219
220 /** lock: protects active_submits and idle/active transitions */
221 struct mutex active_lock;
222
223 /* does gpu need hw_init? */
224 bool needs_hw_init;
225
226 /**
227 * global_faults: number of GPU hangs not attributed to a particular
228 * address space
229 */
230 int global_faults;
231
232 void __iomem *mmio;
233 int irq;
234
235 struct msm_gem_address_space *aspace;
236
237 /* Power Control: */
238 struct regulator *gpu_reg, *gpu_cx;
239 struct clk_bulk_data *grp_clks;
240 int nr_clocks;
241 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
242 uint32_t fast_rate;
243
244 /* Hang and Inactivity Detection:
245 */
246#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
247
248#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
249#define DRM_MSM_HANGCHECK_PROGRESS_RETRIES 3
250 struct timer_list hangcheck_timer;
251
252 /* Fault info for most recent iova fault: */
253 struct msm_gpu_fault_info fault_info;
254
255 /* work for handling GPU ioval faults: */
256 struct kthread_work fault_work;
257
258 /* work for handling GPU recovery: */
259 struct kthread_work recover_work;
260
261 /** retire_event: notified when submits are retired: */
262 wait_queue_head_t retire_event;
263
264 /* work for handling active-list retiring: */
265 struct kthread_work retire_work;
266
267 /* worker for retire/recover: */
268 struct kthread_worker *worker;
269
270 struct drm_gem_object *memptrs_bo;
271
272 struct msm_gpu_devfreq devfreq;
273
274 uint32_t suspend_count;
275
276 struct msm_gpu_state *crashstate;
277
278 /* Enable clamping to idle freq when inactive: */
279 bool clamp_to_idle;
280
281 /* True if the hardware supports expanded apriv (a650 and newer) */
282 bool hw_apriv;
283
284 struct thermal_cooling_device *cooling;
285
286 /* To poll for cx gdsc collapse during gpu recovery */
287 struct reset_control *cx_collapse;
288};
289
290static inline struct msm_gpu *dev_to_gpu(struct device *dev)
291{
292 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
293
294 if (!adreno_smmu)
295 return NULL;
296
297 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
298}
299
300/* It turns out that all targets use the same ringbuffer size */
301#define MSM_GPU_RINGBUFFER_SZ SZ_32K
302#define MSM_GPU_RINGBUFFER_BLKSIZE 32
303
304#define MSM_GPU_RB_CNTL_DEFAULT \
305 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
306 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
307
308static inline bool msm_gpu_active(struct msm_gpu *gpu)
309{
310 int i;
311
312 for (i = 0; i < gpu->nr_rings; i++) {
313 struct msm_ringbuffer *ring = gpu->rb[i];
314
315 if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))
316 return true;
317 }
318
319 return false;
320}
321
322/* Perf-Counters:
323 * The select_reg and select_val are just there for the benefit of the child
324 * class that actually enables the perf counter.. but msm_gpu base class
325 * will handle sampling/displaying the counters.
326 */
327
328struct msm_gpu_perfcntr {
329 uint32_t select_reg;
330 uint32_t sample_reg;
331 uint32_t select_val;
332 const char *name;
333};
334
335/*
336 * The number of priority levels provided by drm gpu scheduler. The
337 * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some
338 * cases, so we don't use it (no need for kernel generated jobs).
339 */
340#define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_HIGH - DRM_SCHED_PRIORITY_MIN)
341
342/**
343 * struct msm_file_private - per-drm_file context
344 *
345 * @queuelock: synchronizes access to submitqueues list
346 * @submitqueues: list of &msm_gpu_submitqueue created by userspace
347 * @queueid: counter incremented each time a submitqueue is created,
348 * used to assign &msm_gpu_submitqueue.id
349 * @aspace: the per-process GPU address-space
350 * @ref: reference count
351 * @seqno: unique per process seqno
352 */
353struct msm_file_private {
354 rwlock_t queuelock;
355 struct list_head submitqueues;
356 int queueid;
357 struct msm_gem_address_space *aspace;
358 struct kref ref;
359 int seqno;
360
361 /**
362 * sysprof:
363 *
364 * The value of MSM_PARAM_SYSPROF set by userspace. This is
365 * intended to be used by system profiling tools like Mesa's
366 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
367 *
368 * Setting a value of 1 will preserve performance counters across
369 * context switches. Setting a value of 2 will in addition
370 * suppress suspend. (Performance counters lose state across
371 * power collapse, which is undesirable for profiling in some
372 * cases.)
373 *
374 * The value automatically reverts to zero when the drm device
375 * file is closed.
376 */
377 int sysprof;
378
379 /**
380 * comm: Overridden task comm, see MSM_PARAM_COMM
381 *
382 * Accessed under msm_gpu::lock
383 */
384 char *comm;
385
386 /**
387 * cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE
388 *
389 * Accessed under msm_gpu::lock
390 */
391 char *cmdline;
392
393 /**
394 * elapsed:
395 *
396 * The total (cumulative) elapsed time GPU was busy with rendering
397 * from this context in ns.
398 */
399 uint64_t elapsed_ns;
400
401 /**
402 * cycles:
403 *
404 * The total (cumulative) GPU cycles elapsed attributed to this
405 * context.
406 */
407 uint64_t cycles;
408
409 /**
410 * entities:
411 *
412 * Table of per-priority-level sched entities used by submitqueues
413 * associated with this &drm_file. Because some userspace apps
414 * make assumptions about rendering from multiple gl contexts
415 * (of the same priority) within the process happening in FIFO
416 * order without requiring any fencing beyond MakeCurrent(), we
417 * create at most one &drm_sched_entity per-process per-priority-
418 * level.
419 */
420 struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS];
421};
422
423/**
424 * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
425 *
426 * @gpu: the gpu instance
427 * @prio: the userspace priority level
428 * @ring_nr: [out] the ringbuffer the userspace priority maps to
429 * @sched_prio: [out] the gpu scheduler priority level which the userspace
430 * priority maps to
431 *
432 * With drm/scheduler providing it's own level of prioritization, our total
433 * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES).
434 * Each ring is associated with it's own scheduler instance. However, our
435 * UABI is that lower numerical values are higher priority. So mapping the
436 * single userspace priority level into ring_nr and sched_prio takes some
437 * care. The userspace provided priority (when a submitqueue is created)
438 * is mapped to ring nr and scheduler priority as such:
439 *
440 * ring_nr = userspace_prio / NR_SCHED_PRIORITIES
441 * sched_prio = NR_SCHED_PRIORITIES -
442 * (userspace_prio % NR_SCHED_PRIORITIES) - 1
443 *
444 * This allows generations without preemption (nr_rings==1) to have some
445 * amount of prioritization, and provides more priority levels for gens
446 * that do have preemption.
447 */
448static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,
449 unsigned *ring_nr, enum drm_sched_priority *sched_prio)
450{
451 unsigned rn, sp;
452
453 rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp);
454
455 /* invert sched priority to map to higher-numeric-is-higher-
456 * priority convention
457 */
458 sp = NR_SCHED_PRIORITIES - sp - 1;
459
460 if (rn >= gpu->nr_rings)
461 return -EINVAL;
462
463 *ring_nr = rn;
464 *sched_prio = sp;
465
466 return 0;
467}
468
469/**
470 * struct msm_gpu_submitqueues - Userspace created context.
471 *
472 * A submitqueue is associated with a gl context or vk queue (or equiv)
473 * in userspace.
474 *
475 * @id: userspace id for the submitqueue, unique within the drm_file
476 * @flags: userspace flags for the submitqueue, specified at creation
477 * (currently unusued)
478 * @ring_nr: the ringbuffer used by this submitqueue, which is determined
479 * by the submitqueue's priority
480 * @faults: the number of GPU hangs associated with this submitqueue
481 * @last_fence: the sequence number of the last allocated fence (for error
482 * checking)
483 * @ctx: the per-drm_file context associated with the submitqueue (ie.
484 * which set of pgtables do submits jobs associated with the
485 * submitqueue use)
486 * @node: node in the context's list of submitqueues
487 * @fence_idr: maps fence-id to dma_fence for userspace visible fence
488 * seqno, protected by submitqueue lock
489 * @idr_lock: for serializing access to fence_idr
490 * @lock: submitqueue lock for serializing submits on a queue
491 * @ref: reference count
492 * @entity: the submit job-queue
493 */
494struct msm_gpu_submitqueue {
495 int id;
496 u32 flags;
497 u32 ring_nr;
498 int faults;
499 uint32_t last_fence;
500 struct msm_file_private *ctx;
501 struct list_head node;
502 struct idr fence_idr;
503 struct mutex idr_lock;
504 struct mutex lock;
505 struct kref ref;
506 struct drm_sched_entity *entity;
507};
508
509struct msm_gpu_state_bo {
510 u64 iova;
511 size_t size;
512 void *data;
513 bool encoded;
514 char name[32];
515};
516
517struct msm_gpu_state {
518 struct kref ref;
519 struct timespec64 time;
520
521 struct {
522 u64 iova;
523 u32 fence;
524 u32 seqno;
525 u32 rptr;
526 u32 wptr;
527 void *data;
528 int data_size;
529 bool encoded;
530 } ring[MSM_GPU_MAX_RINGS];
531
532 int nr_registers;
533 u32 *registers;
534
535 u32 rbbm_status;
536
537 char *comm;
538 char *cmd;
539
540 struct msm_gpu_fault_info fault_info;
541
542 int nr_bos;
543 struct msm_gpu_state_bo *bos;
544};
545
546static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
547{
548 msm_writel(data, gpu->mmio + (reg << 2));
549}
550
551static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
552{
553 return msm_readl(gpu->mmio + (reg << 2));
554}
555
556static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
557{
558 msm_rmw(gpu->mmio + (reg << 2), mask, or);
559}
560
561static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
562{
563 u64 val;
564
565 /*
566 * Why not a readq here? Two reasons: 1) many of the LO registers are
567 * not quad word aligned and 2) the GPU hardware designers have a bit
568 * of a history of putting registers where they fit, especially in
569 * spins. The longer a GPU family goes the higher the chance that
570 * we'll get burned. We could do a series of validity checks if we
571 * wanted to, but really is a readq() that much better? Nah.
572 */
573
574 /*
575 * For some lo/hi registers (like perfcounters), the hi value is latched
576 * when the lo is read, so make sure to read the lo first to trigger
577 * that
578 */
579 val = (u64) msm_readl(gpu->mmio + (reg << 2));
580 val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);
581
582 return val;
583}
584
585static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
586{
587 /* Why not a writeq here? Read the screed above */
588 msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));
589 msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
590}
591
592int msm_gpu_pm_suspend(struct msm_gpu *gpu);
593int msm_gpu_pm_resume(struct msm_gpu *gpu);
594
595void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
596 struct drm_printer *p);
597
598int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
599struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
600 u32 id);
601int msm_submitqueue_create(struct drm_device *drm,
602 struct msm_file_private *ctx,
603 u32 prio, u32 flags, u32 *id);
604int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
605 struct drm_msm_submitqueue_query *args);
606int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
607void msm_submitqueue_close(struct msm_file_private *ctx);
608
609void msm_submitqueue_destroy(struct kref *kref);
610
611int msm_file_private_set_sysprof(struct msm_file_private *ctx,
612 struct msm_gpu *gpu, int sysprof);
613void __msm_file_private_destroy(struct kref *kref);
614
615static inline void msm_file_private_put(struct msm_file_private *ctx)
616{
617 kref_put(&ctx->ref, __msm_file_private_destroy);
618}
619
620static inline struct msm_file_private *msm_file_private_get(
621 struct msm_file_private *ctx)
622{
623 kref_get(&ctx->ref);
624 return ctx;
625}
626
627void msm_devfreq_init(struct msm_gpu *gpu);
628void msm_devfreq_cleanup(struct msm_gpu *gpu);
629void msm_devfreq_resume(struct msm_gpu *gpu);
630void msm_devfreq_suspend(struct msm_gpu *gpu);
631void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
632void msm_devfreq_active(struct msm_gpu *gpu);
633void msm_devfreq_idle(struct msm_gpu *gpu);
634
635int msm_gpu_hw_init(struct msm_gpu *gpu);
636
637void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
638void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
639int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
640 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
641
642void msm_gpu_retire(struct msm_gpu *gpu);
643void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
644
645int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
646 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
647 const char *name, struct msm_gpu_config *config);
648
649struct msm_gem_address_space *
650msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
651
652void msm_gpu_cleanup(struct msm_gpu *gpu);
653
654struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
655void __init adreno_register(void);
656void __exit adreno_unregister(void);
657
658static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
659{
660 if (queue)
661 kref_put(&queue->ref, msm_submitqueue_destroy);
662}
663
664static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
665{
666 struct msm_gpu_state *state = NULL;
667
668 mutex_lock(&gpu->lock);
669
670 if (gpu->crashstate) {
671 kref_get(&gpu->crashstate->ref);
672 state = gpu->crashstate;
673 }
674
675 mutex_unlock(&gpu->lock);
676
677 return state;
678}
679
680static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
681{
682 mutex_lock(&gpu->lock);
683
684 if (gpu->crashstate) {
685 if (gpu->funcs->gpu_state_put(gpu->crashstate))
686 gpu->crashstate = NULL;
687 }
688
689 mutex_unlock(&gpu->lock);
690}
691
692/*
693 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
694 * support expanded privileges
695 */
696#define check_apriv(gpu, flags) \
697 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
698
699
700#endif /* __MSM_GPU_H__ */