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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_ringbuffer.h"
26
27struct msm_gem_submit;
28struct msm_gpu_perfcntr;
29
30/* So far, with hardware that I've seen to date, we can have:
31 * + zero, one, or two z180 2d cores
32 * + a3xx or a2xx 3d core, which share a common CP (the firmware
33 * for the CP seems to implement some different PM4 packet types
34 * but the basics of cmdstream submission are the same)
35 *
36 * Which means that the eventual complete "class" hierarchy, once
37 * support for all past and present hw is in place, becomes:
38 * + msm_gpu
39 * + adreno_gpu
40 * + a3xx_gpu
41 * + a2xx_gpu
42 * + z180_gpu
43 */
44struct msm_gpu_funcs {
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
50 struct msm_file_private *ctx);
51 void (*flush)(struct msm_gpu *gpu);
52 void (*idle)(struct msm_gpu *gpu);
53 irqreturn_t (*irq)(struct msm_gpu *irq);
54 uint32_t (*last_fence)(struct msm_gpu *gpu);
55 void (*recover)(struct msm_gpu *gpu);
56 void (*destroy)(struct msm_gpu *gpu);
57#ifdef CONFIG_DEBUG_FS
58 /* show GPU status in debugfs: */
59 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
60#endif
61};
62
63struct msm_gpu {
64 const char *name;
65 struct drm_device *dev;
66 const struct msm_gpu_funcs *funcs;
67
68 /* performance counters (hw & sw): */
69 spinlock_t perf_lock;
70 bool perfcntr_active;
71 struct {
72 bool active;
73 ktime_t time;
74 } last_sample;
75 uint32_t totaltime, activetime; /* sw counters */
76 uint32_t last_cntrs[5]; /* hw counters */
77 const struct msm_gpu_perfcntr *perfcntrs;
78 uint32_t num_perfcntrs;
79
80 struct msm_ringbuffer *rb;
81 uint32_t rb_iova;
82
83 /* list of GEM active objects: */
84 struct list_head active_list;
85
86 uint32_t submitted_fence;
87
88 /* is gpu powered/active? */
89 int active_cnt;
90 bool inactive;
91
92 /* worker for handling active-list retiring: */
93 struct work_struct retire_work;
94
95 void __iomem *mmio;
96 int irq;
97
98 struct msm_mmu *mmu;
99 int id;
100
101 /* Power Control: */
102 struct regulator *gpu_reg, *gpu_cx;
103 struct clk *ebi1_clk, *grp_clks[6];
104 uint32_t fast_rate, slow_rate, bus_freq;
105
106#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
107 struct msm_bus_scale_pdata *bus_scale_table;
108 uint32_t bsc;
109#endif
110
111 /* Hang and Inactivity Detection:
112 */
113#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
114#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD)
115 struct timer_list inactive_timer;
116 struct work_struct inactive_work;
117#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
118#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
119 struct timer_list hangcheck_timer;
120 uint32_t hangcheck_fence;
121 struct work_struct recover_work;
122
123 struct list_head submit_list;
124};
125
126static inline bool msm_gpu_active(struct msm_gpu *gpu)
127{
128 return gpu->submitted_fence > gpu->funcs->last_fence(gpu);
129}
130
131/* Perf-Counters:
132 * The select_reg and select_val are just there for the benefit of the child
133 * class that actually enables the perf counter.. but msm_gpu base class
134 * will handle sampling/displaying the counters.
135 */
136
137struct msm_gpu_perfcntr {
138 uint32_t select_reg;
139 uint32_t sample_reg;
140 uint32_t select_val;
141 const char *name;
142};
143
144static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
145{
146 msm_writel(data, gpu->mmio + (reg << 2));
147}
148
149static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
150{
151 return msm_readl(gpu->mmio + (reg << 2));
152}
153
154int msm_gpu_pm_suspend(struct msm_gpu *gpu);
155int msm_gpu_pm_resume(struct msm_gpu *gpu);
156
157void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
158void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
159int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
160 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
161
162void msm_gpu_retire(struct msm_gpu *gpu);
163int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
164 struct msm_file_private *ctx);
165
166int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
167 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
168 const char *name, const char *ioname, const char *irqname, int ringsz);
169void msm_gpu_cleanup(struct msm_gpu *gpu);
170
171struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
172void __init adreno_register(void);
173void __exit adreno_unregister(void);
174
175#endif /* __MSM_GPU_H__ */
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_fence.h"
26#include "msm_ringbuffer.h"
27
28struct msm_gem_submit;
29struct msm_gpu_perfcntr;
30
31/* So far, with hardware that I've seen to date, we can have:
32 * + zero, one, or two z180 2d cores
33 * + a3xx or a2xx 3d core, which share a common CP (the firmware
34 * for the CP seems to implement some different PM4 packet types
35 * but the basics of cmdstream submission are the same)
36 *
37 * Which means that the eventual complete "class" hierarchy, once
38 * support for all past and present hw is in place, becomes:
39 * + msm_gpu
40 * + adreno_gpu
41 * + a3xx_gpu
42 * + a2xx_gpu
43 * + z180_gpu
44 */
45struct msm_gpu_funcs {
46 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
47 int (*hw_init)(struct msm_gpu *gpu);
48 int (*pm_suspend)(struct msm_gpu *gpu);
49 int (*pm_resume)(struct msm_gpu *gpu);
50 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
51 struct msm_file_private *ctx);
52 void (*flush)(struct msm_gpu *gpu);
53 bool (*idle)(struct msm_gpu *gpu);
54 irqreturn_t (*irq)(struct msm_gpu *irq);
55 uint32_t (*last_fence)(struct msm_gpu *gpu);
56 void (*recover)(struct msm_gpu *gpu);
57 void (*destroy)(struct msm_gpu *gpu);
58#ifdef CONFIG_DEBUG_FS
59 /* show GPU status in debugfs: */
60 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
61#endif
62};
63
64struct msm_gpu {
65 const char *name;
66 struct drm_device *dev;
67 const struct msm_gpu_funcs *funcs;
68
69 /* performance counters (hw & sw): */
70 spinlock_t perf_lock;
71 bool perfcntr_active;
72 struct {
73 bool active;
74 ktime_t time;
75 } last_sample;
76 uint32_t totaltime, activetime; /* sw counters */
77 uint32_t last_cntrs[5]; /* hw counters */
78 const struct msm_gpu_perfcntr *perfcntrs;
79 uint32_t num_perfcntrs;
80
81 /* ringbuffer: */
82 struct msm_ringbuffer *rb;
83 uint64_t rb_iova;
84
85 /* list of GEM active objects: */
86 struct list_head active_list;
87
88 /* fencing: */
89 struct msm_fence_context *fctx;
90
91 /* is gpu powered/active? */
92 int active_cnt;
93 bool inactive;
94
95 /* worker for handling active-list retiring: */
96 struct work_struct retire_work;
97
98 void __iomem *mmio;
99 int irq;
100
101 struct msm_gem_address_space *aspace;
102 int id;
103
104 /* Power Control: */
105 struct regulator *gpu_reg, *gpu_cx;
106 struct clk *ebi1_clk, *grp_clks[6];
107 uint32_t fast_rate, slow_rate, bus_freq;
108
109#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
110 struct msm_bus_scale_pdata *bus_scale_table;
111 uint32_t bsc;
112#endif
113
114 /* Hang and Inactivity Detection:
115 */
116#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
117#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD)
118 struct timer_list inactive_timer;
119 struct work_struct inactive_work;
120#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
121#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
122 struct timer_list hangcheck_timer;
123 uint32_t hangcheck_fence;
124 struct work_struct recover_work;
125
126 struct list_head submit_list;
127};
128
129static inline bool msm_gpu_active(struct msm_gpu *gpu)
130{
131 return gpu->fctx->last_fence > gpu->funcs->last_fence(gpu);
132}
133
134/* Perf-Counters:
135 * The select_reg and select_val are just there for the benefit of the child
136 * class that actually enables the perf counter.. but msm_gpu base class
137 * will handle sampling/displaying the counters.
138 */
139
140struct msm_gpu_perfcntr {
141 uint32_t select_reg;
142 uint32_t sample_reg;
143 uint32_t select_val;
144 const char *name;
145};
146
147static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
148{
149 msm_writel(data, gpu->mmio + (reg << 2));
150}
151
152static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
153{
154 return msm_readl(gpu->mmio + (reg << 2));
155}
156
157static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
158{
159 uint32_t val = gpu_read(gpu, reg);
160
161 val &= ~mask;
162 gpu_write(gpu, reg, val | or);
163}
164
165static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
166{
167 u64 val;
168
169 /*
170 * Why not a readq here? Two reasons: 1) many of the LO registers are
171 * not quad word aligned and 2) the GPU hardware designers have a bit
172 * of a history of putting registers where they fit, especially in
173 * spins. The longer a GPU family goes the higher the chance that
174 * we'll get burned. We could do a series of validity checks if we
175 * wanted to, but really is a readq() that much better? Nah.
176 */
177
178 /*
179 * For some lo/hi registers (like perfcounters), the hi value is latched
180 * when the lo is read, so make sure to read the lo first to trigger
181 * that
182 */
183 val = (u64) msm_readl(gpu->mmio + (lo << 2));
184 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
185
186 return val;
187}
188
189static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
190{
191 /* Why not a writeq here? Read the screed above */
192 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
193 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
194}
195
196int msm_gpu_pm_suspend(struct msm_gpu *gpu);
197int msm_gpu_pm_resume(struct msm_gpu *gpu);
198
199void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
200void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
201int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
202 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
203
204void msm_gpu_retire(struct msm_gpu *gpu);
205void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
206 struct msm_file_private *ctx);
207
208int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
209 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
210 const char *name, const char *ioname, const char *irqname, int ringsz);
211void msm_gpu_cleanup(struct msm_gpu *gpu);
212
213struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
214void __init adreno_register(void);
215void __exit adreno_unregister(void);
216
217#endif /* __MSM_GPU_H__ */