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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_ringbuffer.h"
26
27struct msm_gem_submit;
28struct msm_gpu_perfcntr;
29
30/* So far, with hardware that I've seen to date, we can have:
31 * + zero, one, or two z180 2d cores
32 * + a3xx or a2xx 3d core, which share a common CP (the firmware
33 * for the CP seems to implement some different PM4 packet types
34 * but the basics of cmdstream submission are the same)
35 *
36 * Which means that the eventual complete "class" hierarchy, once
37 * support for all past and present hw is in place, becomes:
38 * + msm_gpu
39 * + adreno_gpu
40 * + a3xx_gpu
41 * + a2xx_gpu
42 * + z180_gpu
43 */
44struct msm_gpu_funcs {
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
50 struct msm_file_private *ctx);
51 void (*flush)(struct msm_gpu *gpu);
52 void (*idle)(struct msm_gpu *gpu);
53 irqreturn_t (*irq)(struct msm_gpu *irq);
54 uint32_t (*last_fence)(struct msm_gpu *gpu);
55 void (*recover)(struct msm_gpu *gpu);
56 void (*destroy)(struct msm_gpu *gpu);
57#ifdef CONFIG_DEBUG_FS
58 /* show GPU status in debugfs: */
59 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
60#endif
61};
62
63struct msm_gpu {
64 const char *name;
65 struct drm_device *dev;
66 const struct msm_gpu_funcs *funcs;
67
68 /* performance counters (hw & sw): */
69 spinlock_t perf_lock;
70 bool perfcntr_active;
71 struct {
72 bool active;
73 ktime_t time;
74 } last_sample;
75 uint32_t totaltime, activetime; /* sw counters */
76 uint32_t last_cntrs[5]; /* hw counters */
77 const struct msm_gpu_perfcntr *perfcntrs;
78 uint32_t num_perfcntrs;
79
80 struct msm_ringbuffer *rb;
81 uint32_t rb_iova;
82
83 /* list of GEM active objects: */
84 struct list_head active_list;
85
86 uint32_t submitted_fence;
87
88 /* is gpu powered/active? */
89 int active_cnt;
90 bool inactive;
91
92 /* worker for handling active-list retiring: */
93 struct work_struct retire_work;
94
95 void __iomem *mmio;
96 int irq;
97
98 struct msm_mmu *mmu;
99 int id;
100
101 /* Power Control: */
102 struct regulator *gpu_reg, *gpu_cx;
103 struct clk *ebi1_clk, *grp_clks[6];
104 uint32_t fast_rate, slow_rate, bus_freq;
105
106#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
107 struct msm_bus_scale_pdata *bus_scale_table;
108 uint32_t bsc;
109#endif
110
111 /* Hang and Inactivity Detection:
112 */
113#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
114#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD)
115 struct timer_list inactive_timer;
116 struct work_struct inactive_work;
117#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
118#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
119 struct timer_list hangcheck_timer;
120 uint32_t hangcheck_fence;
121 struct work_struct recover_work;
122
123 struct list_head submit_list;
124};
125
126static inline bool msm_gpu_active(struct msm_gpu *gpu)
127{
128 return gpu->submitted_fence > gpu->funcs->last_fence(gpu);
129}
130
131/* Perf-Counters:
132 * The select_reg and select_val are just there for the benefit of the child
133 * class that actually enables the perf counter.. but msm_gpu base class
134 * will handle sampling/displaying the counters.
135 */
136
137struct msm_gpu_perfcntr {
138 uint32_t select_reg;
139 uint32_t sample_reg;
140 uint32_t select_val;
141 const char *name;
142};
143
144static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
145{
146 msm_writel(data, gpu->mmio + (reg << 2));
147}
148
149static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
150{
151 return msm_readl(gpu->mmio + (reg << 2));
152}
153
154int msm_gpu_pm_suspend(struct msm_gpu *gpu);
155int msm_gpu_pm_resume(struct msm_gpu *gpu);
156
157void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
158void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
159int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
160 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
161
162void msm_gpu_retire(struct msm_gpu *gpu);
163int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
164 struct msm_file_private *ctx);
165
166int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
167 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
168 const char *name, const char *ioname, const char *irqname, int ringsz);
169void msm_gpu_cleanup(struct msm_gpu *gpu);
170
171struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
172void __init adreno_register(void);
173void __exit adreno_unregister(void);
174
175#endif /* __MSM_GPU_H__ */
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_fence.h"
26#include "msm_ringbuffer.h"
27
28struct msm_gem_submit;
29struct msm_gpu_perfcntr;
30
31struct msm_gpu_config {
32 const char *ioname;
33 const char *irqname;
34 uint64_t va_start;
35 uint64_t va_end;
36 unsigned int nr_rings;
37};
38
39/* So far, with hardware that I've seen to date, we can have:
40 * + zero, one, or two z180 2d cores
41 * + a3xx or a2xx 3d core, which share a common CP (the firmware
42 * for the CP seems to implement some different PM4 packet types
43 * but the basics of cmdstream submission are the same)
44 *
45 * Which means that the eventual complete "class" hierarchy, once
46 * support for all past and present hw is in place, becomes:
47 * + msm_gpu
48 * + adreno_gpu
49 * + a3xx_gpu
50 * + a2xx_gpu
51 * + z180_gpu
52 */
53struct msm_gpu_funcs {
54 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
55 int (*hw_init)(struct msm_gpu *gpu);
56 int (*pm_suspend)(struct msm_gpu *gpu);
57 int (*pm_resume)(struct msm_gpu *gpu);
58 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
59 struct msm_file_private *ctx);
60 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
61 irqreturn_t (*irq)(struct msm_gpu *irq);
62 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
63 void (*recover)(struct msm_gpu *gpu);
64 void (*destroy)(struct msm_gpu *gpu);
65#ifdef CONFIG_DEBUG_FS
66 /* show GPU status in debugfs: */
67 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
68 /* for generation specific debugfs: */
69 int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
70#endif
71 int (*gpu_busy)(struct msm_gpu *gpu, uint64_t *value);
72};
73
74struct msm_gpu {
75 const char *name;
76 struct drm_device *dev;
77 struct platform_device *pdev;
78 const struct msm_gpu_funcs *funcs;
79
80 /* performance counters (hw & sw): */
81 spinlock_t perf_lock;
82 bool perfcntr_active;
83 struct {
84 bool active;
85 ktime_t time;
86 } last_sample;
87 uint32_t totaltime, activetime; /* sw counters */
88 uint32_t last_cntrs[5]; /* hw counters */
89 const struct msm_gpu_perfcntr *perfcntrs;
90 uint32_t num_perfcntrs;
91
92 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
93 int nr_rings;
94
95 /* list of GEM active objects: */
96 struct list_head active_list;
97
98 /* does gpu need hw_init? */
99 bool needs_hw_init;
100
101 /* worker for handling active-list retiring: */
102 struct work_struct retire_work;
103
104 void __iomem *mmio;
105 int irq;
106
107 struct msm_gem_address_space *aspace;
108
109 /* Power Control: */
110 struct regulator *gpu_reg, *gpu_cx;
111 struct clk **grp_clks;
112 int nr_clocks;
113 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
114 uint32_t fast_rate;
115
116 /* Hang and Inactivity Detection:
117 */
118#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
119
120#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
121#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
122 struct timer_list hangcheck_timer;
123 struct work_struct recover_work;
124
125 struct drm_gem_object *memptrs_bo;
126
127 struct {
128 struct devfreq *devfreq;
129 u64 busy_cycles;
130 ktime_t time;
131 } devfreq;
132};
133
134/* It turns out that all targets use the same ringbuffer size */
135#define MSM_GPU_RINGBUFFER_SZ SZ_32K
136#define MSM_GPU_RINGBUFFER_BLKSIZE 32
137
138#define MSM_GPU_RB_CNTL_DEFAULT \
139 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
140 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
141
142static inline bool msm_gpu_active(struct msm_gpu *gpu)
143{
144 int i;
145
146 for (i = 0; i < gpu->nr_rings; i++) {
147 struct msm_ringbuffer *ring = gpu->rb[i];
148
149 if (ring->seqno > ring->memptrs->fence)
150 return true;
151 }
152
153 return false;
154}
155
156/* Perf-Counters:
157 * The select_reg and select_val are just there for the benefit of the child
158 * class that actually enables the perf counter.. but msm_gpu base class
159 * will handle sampling/displaying the counters.
160 */
161
162struct msm_gpu_perfcntr {
163 uint32_t select_reg;
164 uint32_t sample_reg;
165 uint32_t select_val;
166 const char *name;
167};
168
169struct msm_gpu_submitqueue {
170 int id;
171 u32 flags;
172 u32 prio;
173 int faults;
174 struct list_head node;
175 struct kref ref;
176};
177
178static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
179{
180 msm_writel(data, gpu->mmio + (reg << 2));
181}
182
183static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
184{
185 return msm_readl(gpu->mmio + (reg << 2));
186}
187
188static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
189{
190 uint32_t val = gpu_read(gpu, reg);
191
192 val &= ~mask;
193 gpu_write(gpu, reg, val | or);
194}
195
196static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
197{
198 u64 val;
199
200 /*
201 * Why not a readq here? Two reasons: 1) many of the LO registers are
202 * not quad word aligned and 2) the GPU hardware designers have a bit
203 * of a history of putting registers where they fit, especially in
204 * spins. The longer a GPU family goes the higher the chance that
205 * we'll get burned. We could do a series of validity checks if we
206 * wanted to, but really is a readq() that much better? Nah.
207 */
208
209 /*
210 * For some lo/hi registers (like perfcounters), the hi value is latched
211 * when the lo is read, so make sure to read the lo first to trigger
212 * that
213 */
214 val = (u64) msm_readl(gpu->mmio + (lo << 2));
215 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
216
217 return val;
218}
219
220static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
221{
222 /* Why not a writeq here? Read the screed above */
223 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
224 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
225}
226
227int msm_gpu_pm_suspend(struct msm_gpu *gpu);
228int msm_gpu_pm_resume(struct msm_gpu *gpu);
229
230int msm_gpu_hw_init(struct msm_gpu *gpu);
231
232void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
233void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
234int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
235 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
236
237void msm_gpu_retire(struct msm_gpu *gpu);
238void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
239 struct msm_file_private *ctx);
240
241int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
242 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
243 const char *name, struct msm_gpu_config *config);
244
245void msm_gpu_cleanup(struct msm_gpu *gpu);
246
247struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
248void __init adreno_register(void);
249void __exit adreno_unregister(void);
250
251static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
252{
253 if (queue)
254 kref_put(&queue->ref, msm_submitqueue_destroy);
255}
256
257#endif /* __MSM_GPU_H__ */