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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_ringbuffer.h"
26
27struct msm_gem_submit;
28struct msm_gpu_perfcntr;
29
30/* So far, with hardware that I've seen to date, we can have:
31 * + zero, one, or two z180 2d cores
32 * + a3xx or a2xx 3d core, which share a common CP (the firmware
33 * for the CP seems to implement some different PM4 packet types
34 * but the basics of cmdstream submission are the same)
35 *
36 * Which means that the eventual complete "class" hierarchy, once
37 * support for all past and present hw is in place, becomes:
38 * + msm_gpu
39 * + adreno_gpu
40 * + a3xx_gpu
41 * + a2xx_gpu
42 * + z180_gpu
43 */
44struct msm_gpu_funcs {
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
50 struct msm_file_private *ctx);
51 void (*flush)(struct msm_gpu *gpu);
52 void (*idle)(struct msm_gpu *gpu);
53 irqreturn_t (*irq)(struct msm_gpu *irq);
54 uint32_t (*last_fence)(struct msm_gpu *gpu);
55 void (*recover)(struct msm_gpu *gpu);
56 void (*destroy)(struct msm_gpu *gpu);
57#ifdef CONFIG_DEBUG_FS
58 /* show GPU status in debugfs: */
59 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
60#endif
61};
62
63struct msm_gpu {
64 const char *name;
65 struct drm_device *dev;
66 const struct msm_gpu_funcs *funcs;
67
68 /* performance counters (hw & sw): */
69 spinlock_t perf_lock;
70 bool perfcntr_active;
71 struct {
72 bool active;
73 ktime_t time;
74 } last_sample;
75 uint32_t totaltime, activetime; /* sw counters */
76 uint32_t last_cntrs[5]; /* hw counters */
77 const struct msm_gpu_perfcntr *perfcntrs;
78 uint32_t num_perfcntrs;
79
80 struct msm_ringbuffer *rb;
81 uint32_t rb_iova;
82
83 /* list of GEM active objects: */
84 struct list_head active_list;
85
86 uint32_t submitted_fence;
87
88 /* is gpu powered/active? */
89 int active_cnt;
90 bool inactive;
91
92 /* worker for handling active-list retiring: */
93 struct work_struct retire_work;
94
95 void __iomem *mmio;
96 int irq;
97
98 struct msm_mmu *mmu;
99 int id;
100
101 /* Power Control: */
102 struct regulator *gpu_reg, *gpu_cx;
103 struct clk *ebi1_clk, *grp_clks[6];
104 uint32_t fast_rate, slow_rate, bus_freq;
105
106#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
107 struct msm_bus_scale_pdata *bus_scale_table;
108 uint32_t bsc;
109#endif
110
111 /* Hang and Inactivity Detection:
112 */
113#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
114#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD)
115 struct timer_list inactive_timer;
116 struct work_struct inactive_work;
117#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
118#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
119 struct timer_list hangcheck_timer;
120 uint32_t hangcheck_fence;
121 struct work_struct recover_work;
122
123 struct list_head submit_list;
124};
125
126static inline bool msm_gpu_active(struct msm_gpu *gpu)
127{
128 return gpu->submitted_fence > gpu->funcs->last_fence(gpu);
129}
130
131/* Perf-Counters:
132 * The select_reg and select_val are just there for the benefit of the child
133 * class that actually enables the perf counter.. but msm_gpu base class
134 * will handle sampling/displaying the counters.
135 */
136
137struct msm_gpu_perfcntr {
138 uint32_t select_reg;
139 uint32_t sample_reg;
140 uint32_t select_val;
141 const char *name;
142};
143
144static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
145{
146 msm_writel(data, gpu->mmio + (reg << 2));
147}
148
149static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
150{
151 return msm_readl(gpu->mmio + (reg << 2));
152}
153
154int msm_gpu_pm_suspend(struct msm_gpu *gpu);
155int msm_gpu_pm_resume(struct msm_gpu *gpu);
156
157void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
158void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
159int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
160 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
161
162void msm_gpu_retire(struct msm_gpu *gpu);
163int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
164 struct msm_file_private *ctx);
165
166int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
167 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
168 const char *name, const char *ioname, const char *irqname, int ringsz);
169void msm_gpu_cleanup(struct msm_gpu *gpu);
170
171struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
172void __init adreno_register(void);
173void __exit adreno_unregister(void);
174
175#endif /* __MSM_GPU_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __MSM_GPU_H__
8#define __MSM_GPU_H__
9
10#include <linux/adreno-smmu-priv.h>
11#include <linux/clk.h>
12#include <linux/interconnect.h>
13#include <linux/pm_opp.h>
14#include <linux/regulator/consumer.h>
15
16#include "msm_drv.h"
17#include "msm_fence.h"
18#include "msm_ringbuffer.h"
19#include "msm_gem.h"
20
21struct msm_gem_submit;
22struct msm_gpu_perfcntr;
23struct msm_gpu_state;
24
25struct msm_gpu_config {
26 const char *ioname;
27 unsigned int nr_rings;
28};
29
30/* So far, with hardware that I've seen to date, we can have:
31 * + zero, one, or two z180 2d cores
32 * + a3xx or a2xx 3d core, which share a common CP (the firmware
33 * for the CP seems to implement some different PM4 packet types
34 * but the basics of cmdstream submission are the same)
35 *
36 * Which means that the eventual complete "class" hierarchy, once
37 * support for all past and present hw is in place, becomes:
38 * + msm_gpu
39 * + adreno_gpu
40 * + a3xx_gpu
41 * + a2xx_gpu
42 * + z180_gpu
43 */
44struct msm_gpu_funcs {
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
51 irqreturn_t (*irq)(struct msm_gpu *irq);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
55#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
56 /* show GPU status in debugfs: */
57 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
58 struct drm_printer *p);
59 /* for generation specific debugfs: */
60 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
61#endif
62 unsigned long (*gpu_busy)(struct msm_gpu *gpu);
63 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
64 int (*gpu_state_put)(struct msm_gpu_state *state);
65 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
66 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
67 struct msm_gem_address_space *(*create_address_space)
68 (struct msm_gpu *gpu, struct platform_device *pdev);
69 struct msm_gem_address_space *(*create_private_address_space)
70 (struct msm_gpu *gpu);
71 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
72};
73
74/* Additional state for iommu faults: */
75struct msm_gpu_fault_info {
76 u64 ttbr0;
77 unsigned long iova;
78 int flags;
79 const char *type;
80 const char *block;
81};
82
83struct msm_gpu {
84 const char *name;
85 struct drm_device *dev;
86 struct platform_device *pdev;
87 const struct msm_gpu_funcs *funcs;
88
89 struct adreno_smmu_priv adreno_smmu;
90
91 /* performance counters (hw & sw): */
92 spinlock_t perf_lock;
93 bool perfcntr_active;
94 struct {
95 bool active;
96 ktime_t time;
97 } last_sample;
98 uint32_t totaltime, activetime; /* sw counters */
99 uint32_t last_cntrs[5]; /* hw counters */
100 const struct msm_gpu_perfcntr *perfcntrs;
101 uint32_t num_perfcntrs;
102
103 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
104 int nr_rings;
105
106 /*
107 * List of GEM active objects on this gpu. Protected by
108 * msm_drm_private::mm_lock
109 */
110 struct list_head active_list;
111
112 /* does gpu need hw_init? */
113 bool needs_hw_init;
114
115 /* number of GPU hangs (for all contexts) */
116 int global_faults;
117
118 void __iomem *mmio;
119 int irq;
120
121 struct msm_gem_address_space *aspace;
122
123 /* Power Control: */
124 struct regulator *gpu_reg, *gpu_cx;
125 struct clk_bulk_data *grp_clks;
126 int nr_clocks;
127 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
128 uint32_t fast_rate;
129
130 /* Hang and Inactivity Detection:
131 */
132#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
133
134#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
135 struct timer_list hangcheck_timer;
136
137 /* Fault info for most recent iova fault: */
138 struct msm_gpu_fault_info fault_info;
139
140 /* work for handling GPU ioval faults: */
141 struct kthread_work fault_work;
142
143 /* work for handling GPU recovery: */
144 struct kthread_work recover_work;
145
146 /* work for handling active-list retiring: */
147 struct kthread_work retire_work;
148
149 /* worker for retire/recover: */
150 struct kthread_worker *worker;
151
152 struct drm_gem_object *memptrs_bo;
153
154 struct {
155 struct devfreq *devfreq;
156 u64 busy_cycles;
157 ktime_t time;
158 } devfreq;
159
160 uint32_t suspend_count;
161
162 struct msm_gpu_state *crashstate;
163 /* True if the hardware supports expanded apriv (a650 and newer) */
164 bool hw_apriv;
165
166 struct thermal_cooling_device *cooling;
167};
168
169static inline struct msm_gpu *dev_to_gpu(struct device *dev)
170{
171 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
172 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
173}
174
175/* It turns out that all targets use the same ringbuffer size */
176#define MSM_GPU_RINGBUFFER_SZ SZ_32K
177#define MSM_GPU_RINGBUFFER_BLKSIZE 32
178
179#define MSM_GPU_RB_CNTL_DEFAULT \
180 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
181 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
182
183static inline bool msm_gpu_active(struct msm_gpu *gpu)
184{
185 int i;
186
187 for (i = 0; i < gpu->nr_rings; i++) {
188 struct msm_ringbuffer *ring = gpu->rb[i];
189
190 if (ring->seqno > ring->memptrs->fence)
191 return true;
192 }
193
194 return false;
195}
196
197/* Perf-Counters:
198 * The select_reg and select_val are just there for the benefit of the child
199 * class that actually enables the perf counter.. but msm_gpu base class
200 * will handle sampling/displaying the counters.
201 */
202
203struct msm_gpu_perfcntr {
204 uint32_t select_reg;
205 uint32_t sample_reg;
206 uint32_t select_val;
207 const char *name;
208};
209
210struct msm_gpu_submitqueue {
211 int id;
212 u32 flags;
213 u32 prio;
214 int faults;
215 struct msm_file_private *ctx;
216 struct list_head node;
217 struct kref ref;
218};
219
220struct msm_gpu_state_bo {
221 u64 iova;
222 size_t size;
223 void *data;
224 bool encoded;
225};
226
227struct msm_gpu_state {
228 struct kref ref;
229 struct timespec64 time;
230
231 struct {
232 u64 iova;
233 u32 fence;
234 u32 seqno;
235 u32 rptr;
236 u32 wptr;
237 void *data;
238 int data_size;
239 bool encoded;
240 } ring[MSM_GPU_MAX_RINGS];
241
242 int nr_registers;
243 u32 *registers;
244
245 u32 rbbm_status;
246
247 char *comm;
248 char *cmd;
249
250 struct msm_gpu_fault_info fault_info;
251
252 int nr_bos;
253 struct msm_gpu_state_bo *bos;
254};
255
256static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
257{
258 msm_writel(data, gpu->mmio + (reg << 2));
259}
260
261static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
262{
263 return msm_readl(gpu->mmio + (reg << 2));
264}
265
266static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
267{
268 msm_rmw(gpu->mmio + (reg << 2), mask, or);
269}
270
271static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
272{
273 u64 val;
274
275 /*
276 * Why not a readq here? Two reasons: 1) many of the LO registers are
277 * not quad word aligned and 2) the GPU hardware designers have a bit
278 * of a history of putting registers where they fit, especially in
279 * spins. The longer a GPU family goes the higher the chance that
280 * we'll get burned. We could do a series of validity checks if we
281 * wanted to, but really is a readq() that much better? Nah.
282 */
283
284 /*
285 * For some lo/hi registers (like perfcounters), the hi value is latched
286 * when the lo is read, so make sure to read the lo first to trigger
287 * that
288 */
289 val = (u64) msm_readl(gpu->mmio + (lo << 2));
290 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
291
292 return val;
293}
294
295static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
296{
297 /* Why not a writeq here? Read the screed above */
298 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
299 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
300}
301
302int msm_gpu_pm_suspend(struct msm_gpu *gpu);
303int msm_gpu_pm_resume(struct msm_gpu *gpu);
304void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
305
306int msm_gpu_hw_init(struct msm_gpu *gpu);
307
308void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
309void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
310int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
311 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
312
313void msm_gpu_retire(struct msm_gpu *gpu);
314void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
315
316int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
317 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
318 const char *name, struct msm_gpu_config *config);
319
320struct msm_gem_address_space *
321msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
322
323void msm_gpu_cleanup(struct msm_gpu *gpu);
324
325struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
326void __init adreno_register(void);
327void __exit adreno_unregister(void);
328
329static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
330{
331 if (queue)
332 kref_put(&queue->ref, msm_submitqueue_destroy);
333}
334
335static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
336{
337 struct msm_gpu_state *state = NULL;
338
339 mutex_lock(&gpu->dev->struct_mutex);
340
341 if (gpu->crashstate) {
342 kref_get(&gpu->crashstate->ref);
343 state = gpu->crashstate;
344 }
345
346 mutex_unlock(&gpu->dev->struct_mutex);
347
348 return state;
349}
350
351static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
352{
353 mutex_lock(&gpu->dev->struct_mutex);
354
355 if (gpu->crashstate) {
356 if (gpu->funcs->gpu_state_put(gpu->crashstate))
357 gpu->crashstate = NULL;
358 }
359
360 mutex_unlock(&gpu->dev->struct_mutex);
361}
362
363/*
364 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
365 * support expanded privileges
366 */
367#define check_apriv(gpu, flags) \
368 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
369
370
371#endif /* __MSM_GPU_H__ */